LC4256V-75FN256BC1_技术文档

®

ispMACH 4000V/B/C/Z Family

3.3V/2.5V/1.8V In-System Programmable

TM

SuperFAST High Density PLDs

Coolest Power

November 2007

Data Sheet DS1020

TM

■ Broad Device Offering

Features

• Multiple temperature range support

■ High Performance

– Commercial: 0 to 90°C junction (T )

– Industrial: -40 to 105°C junction (T )

– Extended: -40 to 130°C junction (T )

• For AEC-Q100 compliant devices, refer to

LA-ispMACH 4000V/Z Automotive Data Sheet

j

• f

= 400MHz maximum operating frequency

MAX

j

• t = 2.5ns propagation delay

PD

j

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

■ Easy System Integration

• Superior solution for power sensitive consumer

applications

■ Ease of Design

• Enhanced macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V), 2.5V (4000B) or

1.8V (4000C/Z) supplies

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI

interfaces

• Individual local OE control per I/O pin

• Excellent First-Time-Fit^TMand reﬁt

• Fast path, SpeedLocking^TMPath, and wide-PT

path

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable

(ISP™) using IEEE 1532 compliant interface

• I/O pins with fast setup path

■ Zero Power (ispMACH 4000Z) and Low

Power (ispMACH 4000V/B/C)

• Typical static current 10µA (4032Z)

• Typical static current 1.3mA (4000C)

• 1.8V core low dynamic power

• ispMACH 4000Z operational down to 1.6V V

CC

• Lead-free package options

Table 1. ispMACH 4000V/B/C Family Selection Guide

ispMACH

4032V/B/C

ispMACH

4064V/B/C

ispMACH

4128V/B/C

ispMACH

4256V/B/C

ispMACH

4384V/B/C

ispMACH

4512V/B/C

Macrocells

32

64

128

256

384

512

I/O + Dedicated Inputs

30+2/32+4

30+2/32+4/

64+10

64+10/92+4/

96+4

64+10/96+14/

128+4/160+4

128+4/192+4

128+4/208+4

t

(ns)

2.5

1.8

2.5

1.8

2.7

1.8

3.0

2.0

3.5

2.0

3.5

2.0

PD

t (ns)

S

t

f

(ns)

2.2

2.7

CO

(MHz)

400

333

322

MAX

Supply Voltages (V)

Pins/Package

3.3/2.5/1.8V

44 TQFP

48 TQFP

44 TQFP

48 TQFP

100 TQFP

128 TQFP

144 TQFP¹

100 TQFP

144 TQFP¹

176 TQFP

256 ftBGA²/

fpBGA^{2, 3}

176 TQFP

256 ftBGA/

fpBGA³

176 TQFP

256 ftBGA/

fpBGA³

1. 3.3V (4000V) only.

2. 128-I/O and 160-I/O conﬁgurations.

3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1

DS1020_23.0

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 2. ispMACH 4000Z Family Selection Guide

ispMACH 4032ZC

32

ispMACH 4064ZC

ispMACH 4128ZC

128

ispMACH 4256ZC

Macrocells

64

256

I/O + Dedicated Inputs

32+4/32+4

32+4/32+12/

64+10/64+10

64+10/96+4

64+10/96+6/

128+4

t

(ns)

3.5

2.2

3.0

267

1.8

20

3.7

2.5

3.2

250

1.8

25

4.2

2.7

3.5

220

1.8

35

4.5

2.9

3.8

200

1.8

55

PD

t (ns)

S

t

f

(ns)

CO

(MHz)

MAX

Supply Voltage (V)

Max. Standby Icc (µA)

Pins/Package

48 TQFP

56 csBGA

48 TQFP

56 csBGA

100 TQFP

132 csBGA

100 TQFP

132csBGA

100 TQFP

132 csBGA

176 TQFP

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend

of Lattice’s two most popular architectures: the ispLSI^®2000 and ispMACH 4A. Retaining the best of both families,

the ispMACH 4000 architecture focuses on signiﬁcant innovations to combine the highest performance with low

power in a ﬂexible CPLD family.

The ispMACH 4000 combines high speed and low power with the ﬂexibility needed for ease of design. With its

robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-

ity, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-

binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages

ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key

parameters.

The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)

and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely

driven up to 5.5V when an I/O bank is conﬁgured for 3.3V operation, making this family 5V tolerant. The ispMACH

4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up

resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/

2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary

scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,

TMS, TDI and TDO are referenced to V (logic core).

CC

Overview

The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected

by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which

contain multiple I/O cells. This architecture is shown in Figure 1.

2

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 1. Functional Block Diagram

I/O

Block

I/O

Block

16

36

16

36

Generic

Logic

Block

Generic

Logic

Block

ORP

16

I/O

Block

I/O

Block

16

36

16

36

Generic

Logic

Block

Generic

Logic

Block

ORP 16

16

ORP

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can

support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-

patible with the power supply provided to the bank. Support for a variety of standards helps designers implement

designs in mixed voltage environments. In addition, 5V tolerant inputs are speciﬁed within an I/O bank that is con-

nected to V

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.

CCO

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has

36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be

connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still

must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and

predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-

ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock

generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-

pled from macrocells through the ORP. Figure 2 illustrates the GLB.

3

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 2. Generic Logic Block

To GRP

Clock

Generator

1+OE

36 Inputs

from GRP

To

Product Term

Output Enable

Sharing

AND Array

The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are

used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic

allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and

Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being

fed to the macrocells.

Every set of ﬁve product terms from the 80 logic product terms forms a product term cluster starting with PT0.

There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND

Array.

4

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 3. AND Array

In[0]

In[34]

In[35]

PT0

PT1

PT2

PT3

PT4

Cluster 0

PT75

PT76

PT77

PT78

PT79

Cluster 15

PT80 Shared PT Clock

PT81 Shared PT Initialization

PT82 Shared PTOE

Note:

Indicates programmable fuse.

Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term

cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.

The software automatically considers the availability and distribution of product term clusters as it ﬁts the functions

within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed

Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for

increased performance.

The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:

• Product Term Allocator

• Cluster Allocator

• Wide Steering Logic

Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.

Figure 4. Macrocell Slice

to to

n-1 n-2

from from

n-1 n-4

Fast 5-PT

Path

From

n-4

1-80

PTs

5-PT

n

To XOR (MC)

Cluster

to

n+1

from

n+2

from

n+1

To n+4

Individual Product

Term Allocator

Cluster

Allocator

SuperWIDE™

Steering Logic

5

Lattice Semiconductor

Product Term Allocator

ispMACH 4000V/B/C/Z Family Data Sheet

The product term allocator assigns product terms from a cluster to either logic or control applications as required

by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-

ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated

with the cluster. Table 3 shows the available functions for each of the ﬁve product terms in the cluster. The OR gate

output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic

allocator.

Table 3. Individual PT Steering

Product Term

PTn

Logic

Control

Logic PT

Single PT for XOR/OR

PTn+1

Individual Clock (PT Clock)

PTn+2

Individual Initialization or Individual Clock Enable (PT Initialization/CE)

Individual Initialization (PT Initialization)

PTn+3

PTn+4

Individual OE (PTOE)

Cluster Allocator

The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions

with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,

the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator

accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.

Table 4. Available Clusters for Each Macrocell

Macrocell

M0

Available Clusters

—

C0

C1

C2

C3

M1

M2

C1

C2

C3

C4

M3

C2

C3

C4

C5

M4

C3

C4

C5

C6

M5

C4

C5

C6

C7

M6

C5

C6

C7

C8

M7

C6

C7

C8

C9

M8

C7

C8

C9

C10

C11

C12

C13

C14

C15

—

M9

C8

C9

C10

C11

C12

C13

C14

C15

—

M10

M11

M12

M13

M14

M15

C9

C10

C11

C12

C13

C14

C15

C10

C11

C12

C13

C14

—

Wide Steering Logic

The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-

tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions

and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term

chains.

6

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 5. Product Term Expansion Capability

Expansion

Chains

Macrocells Associated with Expansion Chain

(with Wrap Around)

Max PT/

Macrocell

Chain-0

Chain-1

Chain-2

Chain-3

M0 → M4 → M8 → M12 → M0

M1 → M5 → M9 → M13 → M1

M2 → M6 → M10 → M14 → M2

M3 → M7 → M11 → M15 → M3

75

80

75

70

Every time the super cluster allocator is used, there is an incremental delay of t

. When the super cluster alloca-

EXP

tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-

ter is steered to M (n+4), then M (n) is ground).

Macrocell

The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-

grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.

Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input

from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable

delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.

Figure 5. Macrocell

Power-up

Initialization

Shared PT Initialization

PT Initialization (optional)

PT Initialization/CE (optional)

Delay

From I/O Cell

R

P

From Logic Allocator

To ORP

To GRP

D/T/L

Q

CE

Block CLK0

Block CLK1

Block CLK2

Block CLK3

Single PT

PT Clock (optional)

Shared PT Clock

Enhanced Clock Multiplexer

The clock input to the ﬂip-ﬂop can select any of the four block clocks along with the shared PT clock, and true and

complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The

eight sources for the clock multiplexer are as follows:

• Block CLK0

• Block CLK1

7

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

• Block CLK2

• Block CLK3

• PT Clock

• PT Clock Inverted

• Shared PT Clock

• Ground

Clock Enable Multiplexer

Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-

lowing four sources:

• PT Initialization/CE

• PT Initialization/CE Inverted

• Shared PT Clock

• Logic High

Initialization Control

The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.

There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell

level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-

tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing

ﬂexibility.

Note that the reset/preset swapping selection feature affects power-up reset as well. All ﬂip-ﬂops power up to a

known state for predictable system initialization. If a macrocell is conﬁgured to SET on a signal from the block-level

initialization, then that macrocell will be SET during device power-up. If a macrocell is conﬁgured to RESET on a

signal from the block-level initialization or is not conﬁgured for set/reset, then that macrocell will RESET on power-

up. To guarantee initialization values, the V rise must be monotonic, and the clock must be inactive until the reset

CC

delay time has elapsed.

GLB Clock Generator

Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These

pins drive a clock generator in each GLB, as shown in Figure 6.The clock generator provides four clock signals that

can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the

true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

CLK0

Block CLK0

CLK1

Block CLK1

CLK2

Block CLK2

CLK3

Block CLK3

8

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Output Routing Pool (ORP)

The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.

This provides greater ﬂexibility in determining the pinout and allows design changes to occur without affecting the

pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This

allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-

put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the

output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists

of the following elements:

• Output Routing Multiplexers

• OE Routing Multiplexers

• Output Routing Pool Bypass Multiplexers

Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each

ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.

Figure 7. ORP Slice

OE Routing Multiplexer

From PTOE

To I/O

Cell

OE

ORP

Bypass

Multiplexer

5-PT Fast Path

From Macrocell

To I/O

Cell

Output

Output Routing Multiplexer

Output Routing Multiplexers

The details of connections between the macrocells and the I/O cells vary across devices and within a device

dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.

Table 6. ORP Combinations for I/O Blocks with 8 I/Os

I/O Cell

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Available Macrocells

M0, M1, M2, M3, M4, M5, M6, M7

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M14, M15, M0, M1, M2, M3, M4, M5

9

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 7. ORP Combinations for I/O Blocks with 16 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

M0, M1, M2, M3, M4, M5, M6, M7

M1, M2, M3, M4, M5, M6, M7, M8

I/O 2

M2, M3, M4, M5, M6, M7, M8, M9

I/O 3

M3, M4, M5, M6, M7, M8, M9, M10

M4, M5, M6, M7, M8, M9, M10, M11

M5, M6, M7, M8, M9, M10, M11, M12

M6, M7, M8, M9, M10, M11, M12, M13

M7, M8, M9, M10, M11, M12, M13, M14

M8, M9, M10, M11, M12, M13, M14, M15

M9, M10, M11, M12, M13, M14, M15, M0

M10, M11, M12, M13, M14, M15, M0, M1

M11, M12, M13, M14, M15, M0, M1, M2

M12, M13, M14, M15, M0, M1, M2, M3

M13, M14, M15, M0, M1, M2, M3, M4

M14, M15, M0, M1, M2, M3, M4, M5

M15, M0, M1, M2, M3, M4, M5, M6

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

Table 8. ORP Combinations for I/O Blocks with 4 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

M0, M1, M2, M3, M4, M5, M6, M7

M4, M5, M6, M7, M8, M9, M10, M11

M8, M9, M10, M11, M12, M13, M14, M15

M12, M13, M14, M15, M0, M1, M2, M3

Table 9. ORP Combinations for I/O Blocks with 10 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

M0, M1, M2, M3, M4, M5, M6, M7

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M14, M15, M0, M1, M2, M3, M4, M5

M2, M3, M4, M5, M6, M7, M8, M9

M10, M11, M12, M13, M14, M15, M0, M1

10

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 10. ORP Combinations for I/O Blocks with 12 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

M0, M1, M2, M3, M4, M5, M6, M7

M1, M2, M3, M4, M5, M6, M7, M8

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M5, M6, M7, M8, M9, M10, M11, M12

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M9, M10, M11, M12, M13, M14, M15, M0

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M13, M14, M15, M0, M1, M2, M3, M4

M14, M15, M0, M1, M2, M3, M4, M5

ORP Bypass and Fast Output Multiplexers

The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the

ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also

allows the register output to bypass the ORP to achieve faster t

.

CO

Output Enable Routing Multiplexers

The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.

I/O Cell

The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus

maintenance circuitry. Figure 8 details the I/O cell.

Figure 8. I/O Cell

GOE 0

GOE 1

GOE 2

GOE 3

From ORP

VCC

V_CCO

*

From ORP

To Macrocell

To GRP

*Global fuses

Each output supports a variety of output standards dependent on the V

supplied to its I/O bank. Outputs can

CCO

also be conﬁgured for open drain operation. Each input can be programmed to support a variety of standards, inde-

pendent of the V supplied to its I/O bank. The I/O standards supported are:

CCO

11

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

• LVTTL

• LVCMOS 3.3

• LVCMOS 2.5

• LVCMOS 1.8

• 3.3V PCI Compatible

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down

Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both

hardware and software is such that when the device is erased or if the user does not specify, the input structure is

conﬁgured to be a Pull-up Resistor.

Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be

individually conﬁgured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-

ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reﬂec-

tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the

fast slew rate can be used to achieve the highest speed.

Global OE Generation

Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a

2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or

GOE pins. Each signal that drives the bus can optionally be inverted.

Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a

256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10

show a graphical representation of the global OE generation.

Figure 9. Global OE Generation for All Devices Except ispMACH 4032

Internal Global OE

Global OE

PT Bus

(4 lines)

4-Bit

Global OE Bus

Shared PTOE

(Block 0)

Shared PTOE

(Block n)

Global

Fuses

GOE (0:3)

to I/O cells

Fuse connection

Hard wired

12

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 10. Global OE Generation for ispMACH 4032

Internal Global OE

PT Bus

4-Bit

Global OE Bus

Global OE

(2 lines)

Shared PTOE

(Block 0)

Shared PTOE

(Block 1)

Global

Fuses

GOE (3:0)

to I/O cells

Fuse connection

Hard wired

Zero Power/Low Power and Power Management

The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and

low power. With an advanced E²low power cell and non sense-ampliﬁer design approach (full CMOS logic

approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low

standby power without needing any “turbo bits” or other power management schemes associated with a traditional

sense-ampliﬁer approach.

The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design

changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS

interface that corresponds to the power supply voltage.

I/O Quick Conﬁguration

To facilitate the most efﬁcient board test, the physical nature of the I/O cells must be set before running any continu-

ity tests. As these tests are fast, by nature, the overhead and time that is required for conﬁguration of the I/Os’

physical nature should be minimal so that board test time is minimized.The ispMACH 4000 family of devices allows

this by offering the user the ability to quickly conﬁgure the physical nature of the I/O cells. This quick conﬁguration

takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM^®

System programming software can either perform the quick conﬁguration through the PC parallel port, or can gen-

erate the ATE or test vectors necessary for a third-party test system.

13

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

IEEE 1532-Compliant In-System Programming

Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid prototyping, lower inven-

tory levels, higher quality and the ability to make in-ﬁeld modiﬁcations. All ispMACH 4000 devices provide In-Sys-

tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been

implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE

1149.1 as the communication interface through which ISP is achieved, users get the beneﬁt of a standard, well-

deﬁned interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard.

The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PC-

based Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the

JEDEC ﬁle output produced by the design implementation software, along with information about the scan chain,

and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain

via the parallel port of a PC. Alternatively, the software can output ﬁles in formats understood by common auto-

mated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a

circuit board.

User Electronic Signature

The User Electronic Signature (UES) allows the designer to include identiﬁcation bits or serial numbers inside the

device, stored in E²CMOS memory. The ispMACH 4000 device contains 32 UES bits that can be conﬁgured by the

user to store unique data such as ID codes, revision numbers or inventory control codes.

Security Bit

A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of

the array conﬁguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a

device programmer, securing proprietary designs from competitors. Programming and veriﬁcation are also

defeated by the security bit. The bit can only be reset by erasing the entire device.

Hot Socketing

The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a

device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-

out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The

ispMACH 4000 devices provide this capability for input voltages in the range 0V to 3.0V.

Density Migration

The ispMACH 4000 family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-

geted for a high density device to a lower density device. However, the exact details of the ﬁnal resource utilization

will impact the likely success in each case.

14

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

ispMACH 4000C/Z

(1.8V)

ispMACH 4000B

(2.5V)

ispMACH 4000V

(3.3V)

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

CC

Output Supply Voltage (V

) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V. . . . . . . . . . . -0.5 to 4.5V

CCO

Input or I/O Tristate Voltage Applied^{4, 5}. . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C. . . . . . . . . .-65 to 150°C

Junction Temperature (T ) with Power Applied . . .-55 to 150°C. . . . . . . . . -55 to 150°C. . . . . . . . . .-55 to 150°C

j

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation

is not implied.

2. Compliance with Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Undershoot of -2V and overshoot of (V (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.

IH

5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.

Recommended Operating Conditions

Symbol

Parameter

Min.

1.65

1.7

Max.

1.95

1.9

Units

ispMACH 4000C

ispMACH 4000Z

V

Supply Voltage for 1.8V Devices

ispMACH 4000Z, Extended Functional Voltage

Operation

1.6^{1, 2}

V

1.9

V

CC

Supply Voltage for 2.5V Devices

Supply Voltage for 3.3V Devices

Junction Temperature (Commercial)

Junction Temperature (Industrial)

Junction Temperature (Extended)

2.3

3.0

0

2.7

3.6

90

V

C

T

-40

105

130

j

1. Devices operating at 1.6V can expect performance degradation up to 35%.

2. Applicable for devices with 2004 date codes and later. Contact factory for ordering instructions.

Erase Reprogram Speciﬁcations

Parameter

Min.

Max.

Units

Erase/Reprogram Cycle

1,000

—

Cycles

Note: Valid over commercial temperature range.

Hot Socketing Characteristics^1,2,3

Symbol

Parameter

Condition

Min.

—

Typ.

30

Max.

150

Units

µA

0 ≤ V ≤ 3.0V, Tj = 105°C

IN

I

Input or I/O Leakage Current

DK

0 ≤ V ≤ 3.0V, Tj = 130°C

—

30

200

µA

IN

1. Insensitive to sequence of V or V

However, assumes monotonic rise/fall rates for V and V

provided (V - V

) ≤ 3.6V.

CCO

CC

CCO.

CC

CCO,

IN

2. 0 < V < V (MAX), 0 < V

< V (MAX).

CC

CCO

3. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.

DK

PU PD

BH

15

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

I/O Recommended Operating Conditions

V

(V)¹

CCO

Standard

Min.

3.0

Max.

LVTTL

3.6

2.7

1.95

3.6

LVCMOS 3.3

Extended LVCMOS 3.3²

LVCMOS 2.5

LVCMOS 1.8

PCI 3.3

3.0

2.7

2.3

1.65

3.0

1. Typical values for V

are the average of the min. and max. values.

CCO

2. ispMACH 4000Z only.

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Input Leakage Current (ispMACH

4000Z)

1, 4

I , I

0 ≤ V < V

—

0.5

1

µA

IL IH

IN

CCO

Input High Leakage Current

(ispMACH 4000Z)

1

I

V

< V ≤ 5.5V

—

10

µA

IH

CCO

IN

0 ≤ V ≤ 3.6V, T = 105°C

—

10

15

µA

Input Leakage Current (ispMACH

4000V/B/C)

IN

j

1

I , I

IL IH

0 ≤ V ≤ 3.6V, T = 130°C

IN

j

3.6V < V ≤ 5.5V, T = 105°C

IN

j

—

20

50

µA

3.0V ≤ V

≤ 3.6V

Input High Leakage Current

(ispMACH 4000V/B/C)

CCO

1,2

I

IH

3.6V < V ≤ 5.5V, T = 130°C

IN

CCO

j

3.0V ≤ V

≤ 3.6V

I/O Weak Pull-up Resistor Current

(ispMACH 4000Z)

0 ≤ V ≤ 0.7V

-30

-150

-200

IN

CCO

I

PU

I/O Weak Pull-up Resistor Current

(ispMACH 4000V/B/C)

0 ≤ V ≤ 0.7V

IN

CCO

I

I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MIN)

30

-30

—

150

—

µA

V

PD

IL

IN

IH

Bus Hold Low Sustaining Current

Bus Hold High Sustaining Current

Bus Hold Low Overdrive Current

Bus Hold High Overdrive Current

Bus Hold Trip Points

V

= V (MAX)

IL

BHLS

BHHS

BHLO

BHHO

IN

= 0.7 V

—

CCO

0V ≤ V ≤ V

150

-150

IN

BHT

V

≤ V ≤ V

CCO

—

BHT

IN

V

—

V

* 0.35

V

* 0.65

CCO

BHT

CCO

V

= 3.3V, 2.5V, 1.8V

—

CCO

C

I/O Capacitance³

8

6

pf

1

2

3

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

Clock Capacitance³

Global Input Capacitance³

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tristated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ V

≤ 3.6V.

CCO

3. T = 25°C, f = 1.0MHz

A

4. I excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of

IH

the device’s I/O pins.

16

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

ispMACH 4032V/B/C

Vcc = 3.3V

—

11.8

1.8

—

mA

ICC^1,2,3

ICC⁴

Operating Power Supply Current

Standby Power Supply Current

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

11.3

1.3

ispMACH 4064V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12

—

mA

ICC^1,2,3

Operating Power Supply Current

2

11.5

1.5

ICC⁵

Standby Power Supply Current

ispMACH 4128V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12

—

mA

ICC^1,2,3

Operating Power Supply Current

2

11.5

1.5

ICC⁴

Standby Power Supply Current

ispMACH 4256V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12.5

2.5

12

—

mA

1,2,3

I

Operating Power Supply Current

Standby Power Supply Current

CC

4

I

12

CC

2

ispMACH 4384V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

13.5

3.5

—

mA

1,2,3

I

Operating Power Supply Current

Standby Power Supply Current

CC

12.5

2.5

4

I

CC

ispMACH 4512V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

14

4

—

mA

1,2,3

I

Operating Power Supply Current

CC

17

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C (Cont.)

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Vcc = 3.3V

Min.

—

Typ.

13

3

Max.

—

Units

mA

4

I

Standby Power Supply Current

Vcc = 2.5V

Vcc = 1.8V

—

mA

CC

—

mA

1. T = 25°C, frequency = 1.0 MHz.

A

2. Device conﬁgured with 16-bit counters.

3. I varies with speciﬁc device conﬁguration and operating frequency.

CC

4. T = 25°C

A

Supply Current, ispMACH 4000Z

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min. Typ. Max. Units

ispMACH 4032ZC

Vcc = 1.8V, T = 25°C

—

50

58

60

70

10

13

15

22

—

20

25

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

ispMACH 4064ZC

Vcc = 1.8V, T = 25°C

—

80

89

92

109

11

15

18

37

—

25

35

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

ispMACH 4128ZC

Vcc = 1.8V, T = 25°C

—

168

190

195

212

12

—

35

50

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

16

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

19

A

Vcc = 1.9V, T = 125°C

42

A

18

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000Z (Cont.)

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min. Typ. Max. Units

ispMACH 4256ZC

Vcc = 1.8V, T = 25°C

—

341

361

372

468

13

—

55

90

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

32

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

43

A

Vcc = 1.9V, T = 125°C

135

A

1. T = 25°C, frequency = 1.0 MHz.

A

2. Device conﬁgured with 16-bit counters.

3. I varies with speciﬁc device conﬁguration and operating frequency.

CC

4. V

= 3.6V, V = 0V or V

bus maintenance turned off. V above V

will add transient current above the speciﬁed standby I

.

CC

CCO

IN

CCO,

IN

CCO

5. Includes V

current without output loading.

CCO

19

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

I/O DC Electrical Characteristics

Over Recommended Operating Conditions

V

IH

1

IL

V

I

OH

OL

OH

OL

Standard

LVTTL

Min (V)

Max (V)

Min (V)

Max (V) Max (V)

Min (V)

(mA) (mA)

0.40

V

- 0.40

8.0

0.1

8.0

0.1

8.0

0.1

2.0

0.1

2.0

0.1

1.5

-4.0

-0.1

-4.0

-0.1

-4.0

-0.1

-2.0

-0.1

-2.0

-0.1

-0.5

CCO

-0.3

0.80

0.70

0.63

2.0

5.5

0.20

- 0.20

- 0.40

- 0.20

- 0.40

- 0.20

- 0.45

- 0.20

- 0.45

- 0.20

0.40

LVCMOS 3.3

LVCMOS 2.5

-0.3

5.5

0.20

0.40

1.70

1.17

3.6

0.20

0.40

LVCMOS 1.8

(4000V/B)

3.6

0.20

0.40

LVCMOS 1.8

(4000C/Z)

0.35 * V

1.08

0.65 * V

1.5

3.6

CC

0.20

PCI 3.3 (4000V/B)

PCI 3.3 (4000C/Z)

-0.3

5.5

0.1 V

0.9 V

CCO

0.3 * 3.3 * (V / 1.8) 0.5 * 3.3 * (V / 1.8)

CC

CCO

1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of

the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND

connections or between the last GND in a bank and the end of a bank.

20

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

3.3V V_CCO

2.5V V_CCO

70

100

80

60

40

20

0

60

I_OL

I_OH

50

I_OL

I_OH

40

30

20

10

0

0.5

1.0

1.5

2.0

2.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

V_OOutput Voltage (V)

1.8V V_CCO

60

50

I_OL

I_OH

40

30

20

10

0

0.5

1.0

1.5

2.0

V_OOutput Voltage (V)

21

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics

Over Recommended Operating Conditions

-25

-27

-3

-35

Parameter

Description^{1, 2, 3}

Min. Max. Min. Max. Min. Max. Min. Max. Units

5-PT bypass combinatorial propagation

delay

t

—

2.5

—

2.7

—

3.0

—

3.5

ns

PD

20-PT combinatorial propagation delay

through macrocell

t

—

3.2

—

3.5

—

3.8

—

4.2

—

ns

PD_MC

GLB register setup time before clock

1.8

2.0

1.8

2.0

2.2

2.0

2.2

S

GLB register setup time before clock

with T-type register

—

ST

GLB register setup time before clock,

input register path

t

0.7

—

1.0

—

1.0

—

1.0

—

ns

SIR

GLB register setup time before clock

with zero hold

t

1.7

0.0

—

2.0

0.0

—

2.0

0.0

—

2.0

0.0

—

ns

SIRZ

GLB register hold time after clock

H

GLB register hold time after clock with

T-type register

HT

GLB register hold time after clock, input

register path

t

0.9

0.0

—

1.0

0.0

—

1.0

0.0

—

1.0

0.0

—

ns

HIR

GLB register hold time after clock, input

register path with zero hold

HIRZ

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

2.2

3.5

—

2.7

4.0

—

2.7

4.4

—

2.7

4.5

-

ns

CO

R

1.5

RW

Input to output local product term output

enable/disable

t

—

4.0

5.0

—

4.5

6.5

—

5.0

8.0

—

5.5

8.0

ns

PTOE/DIS

Input to output global product term

output enable/disable

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

3.0

—

3.5

—

4.0

—

4.5

—

ns

GOE/DIS

1.1

1.3

CW

Global gate width low (for low

transparent) or high (for high transparent)

t

1.1

—

1.3

—

1.3

—

1.3

—

ns

GW

t

f

Input register clock width, high or low

Clock frequency with internal feedback

Clock frequency with external feedback,

1.1

—

1.3

—

1.3

—

1.3

—

ns

WIR

4

400

333

322

MHz

MAX

f

(Ext.)

250

—

222

—

212

—

212

—

MHz

MAX

[1/ (t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.3.2

22

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description^{1, 2, 3}

Min. Max. Min. Max. Min. Max. Units

t

5-PT bypass combinatorial propagation delay

20-PT combinatorial propagation delay through macrocell

GLB register setup time before clock

—

5.0

5.5

—

7.5

8.0

—

10.0

10.5

—

ns

PD

t

—

PD_MC

S

3.0

3.2

1.2

2.2

0.0

1.0

4.5

4.7

1.7

2.7

0.0

1.0

5.5

1.7

2.7

0.0

1.0

GLB register setup time before clock with T-type register

GLB register setup time before clock, input register path

GLB register setup time before clock with zero hold

GLB register hold time after clock

—

ST

—

SIR

SIRZ

H

—

GLB register hold time after clock with T-type register

GLB register hold time after clock, input register path

—

HT

—

HIR

GLB register hold time after clock, input register path with

zero hold

t

0.0

—

0.0

—

0.0

—

ns

HIRZ

t

GLB register clock-to-output delay

—

3.4

6.3

—

4.5

9.0

—

6.0

10.5

—

ns

CO

External reset pin to output delay

R

External reset pulse duration

2.0

—

4.0

—

4.0

—

RW

Input to output local product term output enable/disable

Input to output global product term output enable/disable

Global OE input to output enable/disable

Global clock width, high or low

7.0

9.0

5.0

—

9.0

10.3

7.0

—

10.5

12.0

8.0

PTOE/DIS

GPTOE/DIS

GOE/DIS

CW

—

2.2

3.3

4.0

—

Global gate width low (for low transparent) or high (for

high transparent)

t

2.2

—

3.3

—

4.0

—

ns

GW

t

f

Input register clock width, high or low

Clock frequency with internal feedback

2.2

227

156

—

3.3

168

111

—

4.0

125

86

—

ns

MHz

WIR

4

MAX

(Ext.) Clock frequency with external feedback, [1/ (t + t )]

MHz

MAX

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.3.2

23

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description^{1, 2, 3}

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

5-PT bypass combinatorial propagation delay

—

3.5

—

3.7

—

4.2

ns

PD

20-PT combinatorial propagation delay

through macrocell

—

4.4

—

4.7

—

5.7

—

ns

PD_MC

GLB register setup time before clock

2.2

2.4

2.5

2.7

2.9

S

GLB register setup time before clock with

T-type register

—

ST

GLB register setup time before clock, input

register path

t

1.0

—

1.1

—

1.3

—

ns

SIR

GLB register setup time before clock with zero

hold

t

2.0

0.0

—

2.1

0.0

—

2.6

0.0

—

ns

SIRZ

GLB register hold time after clock

H

GLB register hold time after clock with T-type

register

HT

GLB register hold time after clock, input

register path

t

1.0

0.0

—

1.0

0.0

—

1.3

0.0

—

ns

HIR

GLB register hold time after clock, input

register path with zero hold

HIRZ

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

3.0

5.0

—

3.2

6.0

—

3.5

7.3

—

ns

CO

R

1.5

1.7

2.0

RW

Input to output local product term output

enable/disable

t

—

7.0

6.5

—

8.0

7.0

—

8.0

ns

PTOE/DIS

Input to output global product term output

enable/disable

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

4.5

—

4.5

—

4.8

—

ns

GOE/DIS

1.0

1.5

1.8

CW

Global gate width low (for low transparent) or

high (for high transparent)

t

1.0

—

1.5

—

1.8

—

ns

GW

t

f

Input register clock width, high or low

Clock frequency with internal feedback

clock frequency with external feedback,

1.0

—

1.5

—

1.8

—

ns

WIR

4

267

250

220

MHz

MAX

t

(Ext.)

192

—

175

—

161

—

MHz

MAX

[1 / (t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.2.2

24

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description^{1, 2, 3}

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

5-PT bypass combinatorial propagation delay

—

4.5

—

5.0

—

7.5

ns

PD

20-PT combinatorial propagation delay

through macrocell

—

5.8

—

6.0

—

8.0

—

ns

PD_MC

GLB register setup time before clock

2.9

3.1

3.0

3.2

4.5

4.7

S

GLB register setup time before clock with T-

type register

—

ST

GLB register setup time before clock, input

register path

t

1.3

—

1.3

—

1.4

—

ns

SIR

GLB register setup time before clock with zero

hold

t

2.6

0.0

—

2.6

0.0

—

2.7

0.0

—

ns

SIRZ

GLB register hold time after clock

H

GLB register hold time after clock with T-type

register

HT

GLB register hold time after clock, input regis-

ter path

t

1.3

0.0

—

1.3

0.0

—

1.3

0.0

—

ns

HIR

GLB register hold time after clock, input regis-

ter path with zero hold

HIRZ

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

3.8

7.5

—

4.2

7.5

—

4.5

9.0

—

ns

CO

R

2.0

4.0

RW

Input to output local product term output

enable/disable

t

—

8.2

—

8.5

—

9.0

ns

PTOE/DIS

Input to output global product term output

enable/disable

10.0

10.5

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

5.5

—

6.0

—

7.0

—

ns

GOE/DIS

1.8

2.0

3.3

CW

Global gate width low (for low transparent) or

high (for high transparent)

t

1.8

—

2.0

—

3.3

—

ns

GW

t

f

Input register clock width, high or low

Clock frequency with internal feedback

clock frequency with external feedback, [1 /

1.8

—

2.0

—

3.3

—

ns

WIR

4

200

168

MHz

MAX

t

(Ext.)

150

—

139

—

111

—

MHz

MAX

(t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.2.2

25

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Timing Model

The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing

model provided in Figure 11 shows the speciﬁc delay paths. Once the implementation of a given function is deter-

mined either conceptually or from the software report ﬁle, the delay path of the function can easily be determined

from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-

ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-

nal timing parameters are tested and guaranteed for every device. For more information on the timing model and

usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines.

Figure 11. ispMACH 4000 Timing Model

Routing/GLB Delays

From

Feedback

t_PDb

t_PDi

Feedback

Out

t_FBK

t_ROUTE

t_BLA

t_MCELL

t_EXP

t_IN

t_BUF

t_IOO

t_EN

DATA

IN

t_ORP

t_IOI

Q

t_INREG

t_INDIO

t_DIS

t_{GCLK_IN}

t_IOI

In/Out

Delays

SCLK

t_PTCLK

t_BCLK

C.E.

S/R

t_PTSR

t_BSR

Register/Latch

Delays

MC Reg.

t_GPTOE

t_PTOE

Control

Delays

t_GOE

t_IOI

OE

In/Out

Delays

Note: Italicized items are optional delay adders.

26

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

Parameter

Description

-2.5

-2.7

-3

-3.5

Units

In/Out Delays

t

Input Buffer Delay

—

0.60

2.04

0.78

0.85

0.96

—

0.60

2.54

1.28

0.85

0.96

—

0.70

3.04

1.28

0.85

0.96

—

0.70

3.54

1.28

0.85

0.96

ns

IN

Global OE Pin Delay

GOE

GCLK_IN

BUF

EN

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

Macrocell Delay

—

0.61

0.45

—

0.81

0.55

—

1.01

0.55

—

1.01

0.65

ns

ROUTE

MCELL

Input Buffer to Macrocell Register

Delay

t

—

0.11

—

0.31

—

0.31

—

0.31

ns

INREG

t

Internal Feedback Delay

—

0.00

0.44

0.64

—

0.00

0.44

0.64

—

0.00

0.44

0.64

—

0.00

0.94

ns

FBK

PDb

PDi

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

Register/Latch Delays

D-Register Setup Time

(Global Clock)

t

0.92

1.42

1.12

1.42

—

1.12

1.32

—

1.02

1.32

1.22

1.32

—

0.92

1.32

1.12

1.32

—

ns

S

D-Register Setup Time

(Product Term Clock)

S_PT

ST

T-Register Setup Time

(Global Clock)

T-Register Setup Time

(Product Term Clock)

ST_PT

t

D-Register Hold Time

T-Register Hold Time

0.88

—

0.68

—

0.98

—

1.08

—

ns

H

HT

D-Input Register Setup Time

(Global Clock)

t

0.82

1.45

0.88

—

1.37

1.45

0.63

—

1.27

1.45

0.73

—

1.27

1.45

0.73

—

ns

SIR

D-Input Register Setup Time

(Product Term Clock)

SIR_PT

HIR

D-Input Register Hold Time

(Global Clock)

—

D-Input Register Hold Time

(Product Term Clock)

—

HIR_PT

COi

Register Clock to Output/Feedback

MUX Time

0.52

t

Clock Enable Setup Time

Clock Enable Hold Time

2.25

1.88

—

2.25

1.88

—

2.25

1.88

—

2.25

1.88

—

ns

CES

CEH

Latch Setup Time

(Global Clock)

t

0.92

—

1.12

—

1.02

—

0.92

—

ns

SL

Latch Setup Time (Product Term

Clock)

t

1.42

1.17

—

1.32

1.17

—

1.32

1.17

—

1.32

1.17

—

ns

SL_PT

Latch Hold Time

HL

Latch Gate to Output/Feedback

MUX Time

0.33

GOi

27

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

Parameter

Description

-2.5

-2.7

-3

-3.5

Units

Propagation Delay through

Transparent Latch to Output/

Feedback MUX

t

—

0.25

—

0.25

—

0.25

—

0.25

ns

PDLi

Asynchronous Reset or Set to

Output/Feedback MUX Delay

t

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

ns

SRi

Asynchronous Reset or Set

Recovery Time

SRR

Control Delays

t

GLB PT Clock Delay

—

1.12

0.87

1.83

1.11

2.83

1.83

—

1.12

0.87

1.83

1.41

4.13

2.13

—

1.12

0.87

1.83

1.51

5.33

2.33

—

1.12

0.87

1.83

1.61

5.33

2.83

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

ns

PTSR

GPTOE

PTOE

ns

Macrocell PT OE Delay

ns

Timing v.3.2

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

28

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

—

0.95

4.04

1.83

1.00

0.96

—

1.50

6.04

2.28

1.50

0.96

—

2.00

7.04

3.28

1.50

0.96

ns

IN

Global OE Pin Delay

GOE

GCLK_IN

BUF

EN

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

—

1.51

1.05

0.56

0.00

1.54

0.94

—

2.26

1.45

0.96

0.00

2.24

1.24

—

3.26

1.95

1.46

0.00

3.24

1.74

ns

ROUTE

MCELL

INREG

FBK

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-Register Setup Time (Product Term Clock)

D-Register Hold Time

1.32

1.52

1.32

1.68

1.52

1.45

0.68

—

1.57

1.32

1.77

1.32

2.93

1.57

1.45

1.18

—

1.57

1.32

1.77

1.32

3.93

1.57

1.45

1.18

—

ns

S

S_PT

ST

—

ST_PT

H

—

T-Register Hold Time

—

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

—

SIR

—

SIR_PT

HIR

—

HIR_PT

COi

0.52

—

0.67

—

1.17

—

2.25

1.88

1.32

1.17

—

2.25

1.88

1.57

1.32

1.17

—

2.25

1.88

1.57

1.32

1.17

—

CES

CEH

SL

Clock Enable Hold Time

—

Latch Setup Time (Global Clock)

—

Latch Setup Time (Product Term Clock)

Latch Hold Time

—

SL_PT

HL

—

Latch Gate to Output/Feedback MUX Time

0.33

0.25

0.33

0.25

0.33

0.25

GOi

Propagation Delay through Transparent Latch to Output/

Feedback MUX

—

PDLi

t

Asynchronous Reset or Set to Output/Feedback MUX

Delay

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

ns

SRi

t

Asynchronous Reset or Set Recovery Time

SRR

Control Delays

t

GLB PT Clock Delay

—

1.12

0.87

1.83

2.51

—

1.12

0.87

1.83

3.41

—

0.62

0.87

1.83

3.41

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

PTSR

29

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Global PT OE Delay

—

5.58

3.58

—

5.58

4.28

—

5.78

4.28

ns

GPTOE

PTOE

Macrocell PT OE Delay

Timing v.3.2

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

30

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

—

0.75

2.25

1.60

0.75

2.25

1.35

—

0.80

2.25

1.60

0.90

2.25

1.35

—

0.75

2.30

1.95

0.90

2.50

ns

IN

Global OE Pin Delay

GOE

GCLK_IN

BUF

EN

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

—

1.60

0.65

0.91

0.05

0.40

0.25

—

1.60

0.75

1.00

0.00

0.40

0.25

—

2.15

0.85

1.00

0.00

0.40

0.65

ns

ROUTE

MCELL

INREG

FBK

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-register Setup Time (Product Term Clock)

D-Register Hold Time

0.80

1.35

1.00

1.55

1.40

0.94

1.45

1.06

0.88

—

0.95

1.95

1.15

1.75

1.55

0.90

1.45

1.20

1.00

—

0.90

1.90

1.10

2.10

1.80

1.50

1.45

1.10

1.00

—

ns

S

S_PT

ST

—

ST_PT

H

—

T-Resister Hold Time

—

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

—

SIR

—

SIR_PT

HIR

—

HIR_PT

COi

0.65

—

0.70

—

0.65

—

1.00

0.00

0.80

1.55

1.40

—

2.00

0.00

0.95

1.95

1.80

—

2.00

0.00

0.90

1.90

1.80

—

CES

CEH

SL

Clock Enable Hold Time

—

Latch Setup Time (Global Clock)

—

Latch Setup Time (Product Term Clock)

Latch Hold Time

—

SL_PT

HL

—

Latch Gate to Output/Feedback MUX Time

0.40

0.33

GOi

Propagation Delay through Transparent Latch to Output/

Feedback MUX

t

—

0.30

—

0.25

—

0.25

ns

PDLi

t

Asynchronous Reset or Set to Output/Feedback MUX Delay

Asynchronous Reset or Set Recovery Delay

—

0.28

2.00

—

0.28

1.67

—

1.27

1.80

ns

SRi

SRR

Control Delays

t

GLB PT Clock Delay

—

1.30

1.50

1.10

1.22

—

1.50

1.70

1.83

2.02

—

1.55

1.83

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

PTSR

31

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Global PT OE Delay

—

1.9

2.4

—

2.35

3.35

—

2.60

ns

GPTOE

Macrocell PT OE Delay

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for

further details.

Timing v.2.2

32

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

—

0.95

3.00

1.95

1.10

2.50

—

1.25

3.50

2.05

1.00

2.50

—

1.80

4.30

2.15

1.30

2.70

ns

IN

Global OE Pin Delay

GOE

GCLK_IN

BUF

EN

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

—

2.25

0.65

1.00

0.35

0.20

0.45

—

2.05

0.65

1.00

0.05

0.70

0.65

—

2.50

1.00

0.05

1.90

1.00

ns

ROUTE

MCELL

INREG

FBK

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-register Setup Time (Product Term Clock)

D-Register Hold Time

1.00

2.10

1.20

2.30

1.90

1.30

1.45

1.30

1.00

—

1.10

1.90

1.30

2.10

1.90

1.10

1.45

1.50

1.00

—

1.35

2.45

1.55

2.75

3.15

0.75

1.45

1.95

1.18

—

ns

S

S_PT

ST

—

ST_PT

H

—

T-Resister Hold Time

—

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

—

SIR

—

SIR_PT

HIR

—

HIR_PT

COi

0.75

—

1.15

—

1.05

—

2.00

0.00

1.00

2.10

2.00

—

2.00

0.00

1.00

1.90

2.00

—

2.00

0.00

1.65

2.15

1.17

—

CES

CEH

SL

Clock Enable Hold Time

—

Latch Setup Time (Global Clock)

—

Latch Setup Time (Product Term Clock)

Latch Hold Time

—

SL_PT

HL

—

Latch Gate to Output/Feedback MUX Time

0.33

GOi

Propagation Delay through Transparent Latch to Output/

Feedback MUX

t

—

0.25

—

0.25

—

0.25

ns

PDLi

t

Asynchronous Reset or Set to Output/Feedback MUX Delay

Asynchronous Reset or Set Recovery Delay

—

0.97

1.80

—

0.97

1.80

—

0.28

1.67

ns

SRi

SRR

Control Delays

t

GLB PT Clock Delay

—

1.55

1.83

4.30

—

1.55

1.83

4.20

—

1.25

1.83

2.72

3.50

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

33

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Macrocell PT OE Delay

—

2.50

—

2.70

—

2.00

ns

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for

further details.

Timing v.2.2

34

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Timing Adders¹

-25

-27

-3

-35

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Optional Delay Adders

t

Input register delay

—

0.95

0.33

0.05

0.03

—

1.00

0.33

—

1.00

0.33

—

1.00

0.33

ns

INDIO

INREG

Product term expander

delay

t

EXP

MCELL

—

Output routing pool delay

0.05

ns

ORP

BLA

Additional block loading

adder

t

ROUTE

t

Input Adjusters

IOI

t , t

t

,

IN GCLK_IN

GOE

LVTTL_in

Using LVTTL standard

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t , t

Using LVCMOS 3.3

standard

IN GCLK_IN

GOE

LVCMOS33_in

LVCMOS25_in

LVCMOS18_in

PCI_in

t

t , t

Using LVCMOS 2.5

standard

IN GCLK_IN

GOE

t

t , t

Using LVCMOS 1.8

standard

IN GCLK_IN

GOE

t

t , t

Using PCI compatible

input

IN GCLK_IN

GOE

t

Output Adjusters

IOO

Output conﬁgured as

TTL buffer

LVTTL_out

t

, t , t

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

BUF EN DIS

Output conﬁgured as

3.3V buffer

LVCMOS33_out t

LVCMOS25_out t

LVCMOS18_out t

, t , t

BUF EN DIS

Output conﬁgured as

2.5V buffer

, t , t

BUF EN DIS

Output conﬁgured as

1.8V buffer

, t , t

BUF EN DIS

Output conﬁgured as

PCI compatible buffer

PCI_out

t

, t , t

BUF EN DIS

Output conﬁgured for

slow slew rate

Slow Slew

t

, t

BUF EN

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.3.2

1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.

35

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Timing Adders¹(Cont.)

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Optional Delay Adders

t

Input register delay

—

1.00

0.33

0.05

—

1.00

0.33

0.05

—

1.00

0.33

0.05

ns

INDIO

EXP

INREG

MCELL

Product term expander delay

Output routing pool delay

—

ORP

BLA

t

Additional block loading adder

ROUTE

t

Input Adjusters

IOI

t , t

t

,

IN GCLK_IN

GOE

LVTTL_in

Using LVTTL standard

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t , t

IN GCLK_IN

GOE

LVCMOS33_in

LVCMOS25_in

LVCMOS18_in

PCI_in

Using LVCMOS 3.3 standard

Using LVCMOS 2.5 standard

Using LVCMOS 1.8 standard

Using PCI compatible input

t

t , t

IN GCLK_IN

GOE

t

t , t

IN GCLK_IN

GOE

t

t , t

IN GCLK_IN

GOE

t

Output Adjusters

IOO

LVTTL_out

t

, t , t

Output conﬁgured as TTL buffer

Output conﬁgured as 3.3V buffer

Output conﬁgured as 2.5V buffer

Output conﬁgured as 1.8V buffer

—

0.20

0.10

0.00

—

0.20

0.10

0.00

—

0.20

0.10

0.00

ns

BUF EN DIS

LVCMOS33_out t

LVCMOS25_out t

LVCMOS18_out t

, t , t

BUF EN DIS

, t , t

BUF EN DIS

, t , t

BUF EN DIS

Output conﬁgured as PCI compatible

buffer

PCI_out

t

, t , t

—

0.20

1.00

—

0.20

1.00

—

0.20

ns

BUF EN DIS

Slow Slew

t

, t

Output conﬁgured for slow slew rate

1.00

ns

BUF EN

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.3.2

1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.

36

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Timing Adders ¹

-35

-37

-42

Adder

Type

Base

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Optional Delay Adders

t

Input register delay

—

1.00

0.40

—

1.00

0.40

—

1.30

0.45

ns

INDIO

EXP

INREG

MCELL

Product term expander

delay

t

—

Output routing pool

delay

ORP

BLA

—

0.40

0.04

—

0.40

0.05

—

0.40

0.05

ns

t

Additional block load-

ing adder

ROUTE

t

Input Adjusters

IOI

LVTTL_in

t

Using LVTTL standard

—

0.60

—

0.60

—

0.60

ns

IN, GCLK_IN, GOE

LVCMOS33_in

t

Using LVCMOS 3.3

standard

IN, GCLK_IN, GOE

LVCMOS25_in

LVCMOS18_in

PCI_in

t

Using LVCMOS 2.5

standard

IN, GCLK_IN, GOE

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

Using LVCMOS 1.8

standard

IN, GCLK_IN, GOE

t

Using PCI compatible

input

IN, GCLK_IN, GOE

t

Output Adjusters

IOO

LVTTL_out

t

Output conﬁgured as

TTL buffer

BUF, EN, DIS

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

LVCMOS33_out

LVCMOS25_out

LVCMOS18_out

PCI_out

t

Output conﬁgured as

3.3V buffer

BUF, EN, DIS

t

Output conﬁgured as

2.5V buffer

BUF, EN, DIS

t

Output conﬁgured as

1.8V buffer

BUF, EN, DIS

t

Output conﬁgured as

PCI compatible buffer

BUF, EN, DIS

Slow Slew

t

Output conﬁgured for

slow slew rate

BUF, EN

ns

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.2.2

1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding the use of these

adders.

37

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Timing Adders (Cont.)¹

-45

-5

-75

Adder

Type

Base

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Optional Delay Adders

t

Input register delay

—

1.30

0.45

—

1.30

0.45

—

1.30

0.50

ns

INDIO

EXP

INREG

MCELL

Product term expander

delay

t

—

Output routing pool

delay

ORP

BLA

—

0.40

0.05

—

0.40

0.05

—

0.40

0.05

ns

t

Additional block load-

ing adder

ROUTE

t

Input Adjusters

IOI

LVTTL_in

t

Using LVTTL standard

—

0.60

—

0.60

—

0.60

ns

IN, GCLK_IN, GOE

LVCMOS33_in

t

Using LVCMOS 3.3

standard

IN, GCLK_IN, GOE

LVCMOS25_in

LVCMOS18_in

PCI_in

t

Using LVCMOS 2.5

standard

IN, GCLK_IN, GOE

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

Using LVCMOS 1.8

standard

IN, GCLK_IN, GOE

t

Using PCI compatible

input

IN, GCLK_IN, GOE

t

Output Adjusters

IOO

LVTTL_out

t

Output conﬁgured as

TTL buffer

BUF, EN, DIS

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

LVCMOS33_out

LVCMOS25_out

LVCMOS18_out

PCI_out

t

Output conﬁgured as

3.3V buffer

BUF, EN, DIS

t

Output conﬁgured as

2.5V buffer

BUF, EN, DIS

t

Output conﬁgured as

1.8V buffer

BUF, EN, DIS

t

Output conﬁgured as

PCI compatible buffer

BUF, EN, DIS

Slow Slew

t

Output conﬁgured for

slow slew rate

BUF, EN

ns

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.2.2

1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these

adders.

38

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Boundary Scan Waveforms and Timing Speciﬁcations

Symbol

Parameter

Min.

40

20

8

Max.

—

Units

ns

t

TCK [BSCAN test] clock cycle

BTCP

TCK [BSCAN test] pulse width high

—

ns

BTCH

BTCL

TCK [BSCAN test] pulse width low

—

ns

TCK [BSCAN test] setup time

—

ns

BTSU

BTH

TCK [BSCAN test] hold time

10

50

—

8

—

ns

TCK [BSCAN test] rise and fall time

—

mV/ns

ns

BRF

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to data output disable

TAP controller falling edge of clock to data output enable

BSCAN test Capture register setup time

10

—

BTCO

BTOZ

ns

BTVO

BTCPSU

BTCPH

BTUCO

BTUOZ

BTUOV

ns

BSCAN test Capture register hold time

10

—

ns

BSCAN test Update reg, falling edge of clock to valid output

BSCAN test Update reg, falling edge of clock to output disable

BSCAN test Update reg, falling edge of clock to output enable

25

ns

39

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Power Consumption

ispMACH 4000Z

ispMACH 4000V/B

ispMACH 4000C

Typical I vs. Frequency

Typical I

vs. Frequency

Typical I

vs. Frequency

CC

(Preliminary Information)

4512V/B

4384V/B

100

80

60

40

20

0

300

250

200

150

100

300

250

200

150

100

4512C

4384C

4256ZC

4256V/B

4256C

4128C

4128ZC

4064ZC

4128V/B

4064V/B

4032V/B

50

0

50

0

4032ZC

4064C

4032C

0

50

100

150

200

250

300

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

Note: The devices are configured with maximum number

of 16-bit counters, typical current at 1.8V, 25°C.

of 16-bit counters, typical current at 3.3V, 2.5V, 25°C.

Power Estimation Coefﬁcients¹

Device

ispMACH 4032V/B

ispMACH 4032C

ispMACH 4064V/B

ispMACH 4064C

ispMACH 4128V/B

ispMACH 4128C

ispMACH 4256V/B

ispMACH 4256C

ispMACH 4384V/B

ispMACH 4384C

ispMACH 4512V/B

ispMACH 4512C

ispMACH 4032ZC

ispMACH 4064ZC

ispMACH 4128ZC

ispMACH 4256ZC

A

11.3

1.3

B

0.010

0.011

0.013

0.010

11.5

1.5

11.5

1.5

12

2

12.5

2.5

13

3

0.010

0.011

0.012

0.013

1. For further information about the use of these coefﬁcients, refer to Technical Note

TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices.

40

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Switching Test Conditions

Figure 12 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Table 11.

Figure 12. Output Test Load, LVTTL and LVCMOS Standards

V

CCO

R

1

2

Test

Point

DUT

R

C

L

0213A/ispm4k

Table 11. Test Fixture Required Components

1

Test Condition

R

C

Timing Ref.

V

CCO

1

2

L

LVCMOS 3.3 = 1.5V

LVCMOS 3.3 = 3.0V

LVCMOS I/O, (L -> H, H -> L)

106Ω 106Ω

35pF

LVCMOS 2.5 = V

LVCMOS 1.8 = V

1.5V

/2

LVCMOS 2.5 = 2.3V

CCO

LVCMOS 1.8 = 1.65V

LVCMOS I/O (Z -> H)

LVCMOS I/O (Z -> L)

LVCMOS I/O (H -> Z)

LVCMOS I/O (L -> Z)

∞

106Ω

∞

35pF

5pF

3.0V

106Ω

∞

1.5V

106Ω

∞

V

- 0.3

OH

OL

106Ω

5pF

+ 0.3

1. C includes test ﬁxtures and probe capacitance.

L

41

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Signal Descriptions

Signal Names

Description

TMS

Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control

the state machine.

TCK

Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the

state machine.

TDI

Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data.

Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out.

TDO

GOE0/IO, GOE1/IO

These pins are conﬁgured to be either Global Output Enable Input or as general I/O

pins.

GND

NC

Ground

Not Connected

V

The power supply pins for logic core and JTAG port.

These pins are conﬁgured to be either CLK input or as an input.

The power supply pins for each I/O bank.

CC

CLK0/I, CLK1/I, CLK2/I, CLK3/I

, V

V

CCO0 CCO1

Input/Output¹– These are the general purpose I/O used by the logic array. y is GLB

reference (alpha) and z is macrocell reference (numeric). z: 0-15.

ispMACH 4032

ispMACH 4064

ispMACH 4128

ispMACH 4256

ispMACH 4384

ispMACH 4512

y: A-B

y: A-D

yzz

y: A-H

y: A-P

y: A-P, AX-HX

y: A-P, AX-PX

1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.

ispMACH 4000V/B/C ORP Reference Table

4032V/B/C

4064V/B/C

4128V/B/C

64

92³96

4256V/B/C

4384V/B/C

4512V/B/C

30¹

32 30²32

64

16

96⁴

128

16

160

16

128 192 128

208

16

Number of I/Os

Number of GLBs

2

4

8

4

8

4

8

16

8

16

8

16

8

Number of I/Os /

GLB

Mixture

16

8

12 12

4

8

10

of 8 & 4⁵

8 I/Os /

GLB

4 I/Os /

GLB

Reference ORP

Table

16 I/Os /

GLB

8 I/Os / 16 I/Os / 8 I/Os / 12 I/Os / 4 I/Os / 8 I/Os / 8 I/Os / 10 I/Os / 8 I/Os / 8 I/Os /

GLB

1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.

2. 64-macrocells device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.

3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os

4. 256-macrocell device, 144 TQFP: 16 GLBs have 6 I/Os per

5. 512-macrocell device: 20 GLBs have 8 I/Os per, 12 GLBs have 4 I/Os per

ispMACH 4000Z ORP Reference Table

4032Z

4064Z

4128Z

4256Z

Number of I/Os

32

4

64

4

64

8

96

8

64

16

4

96¹

16

8

128

16

8

Number of GLBs

Number of I/Os / GLB

2

16

8

16

8

12

16 I/Os /

GLB

8 I/Os /

GLB

16 I/Os /

GLB

8 I/Os /

GLB

12 I/Os /

GLB

4 I/Os /

GLB

8 I/Os /

GLB

8 I/Os /

GLB

Reference ORP Table

1. 256-macrocell device, 132 csBGA: 16 GLBs have 6 I/Os per

42

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C/Z Power Supply and NC Connections¹

Signal

44-pin TQFP²

48-pin TQFP²

56-ball csBGA³

100-pin TQFP²

128-pin TQFP²

VCC

11, 33

12, 36

K2, A9

25, 40, 75, 90

32, 51, 96, 115

VCCO0

VCCO (Bank 0)

6

F3

E8

13, 33, 95

45, 63, 83

3, 17, 30, 41, 122

58, 67, 81, 94, 105

VCCO1

VCCO (Bank 1)

28

30

GND

12, 34

5

13, 37

5

H3, C8

D3

1, 26, 51, 76

7, 18, 32, 96

46, 57, 68, 82

1, 33, 65, 97

GND (Bank 0)

GND (Bank 1)

NC

10, 24, 40, 113, 123

49, 59, 74, 88, 104

27

29

G8

4032Z: A8, B10, E1,

E3, F8, F10, J1, K3

—

1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with

the bank shown.

2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.

3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

43

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C/Z Power Supply and NC Connections¹(Cont.)

Signal

VCC

132-ball csBGA⁷

144-pin TQFP⁴

176-pin TQFP⁴

256-ball ftBGA/fpBGA^{2, 3, 7, 9}

P1, A14, B7, N8

36, 57, 108, 129

42, 69, 88, 130,

157, 176

B2, B15, G8, G9, K8, K9, R2, R15

VCCO0

G3, P5, C1⁸, M2⁸,

3, 19, 34, 47, 136

4, 22, 40, 56, 166 D6, F4, H7, J7, L4, N6

VCCO (Bank 0) C5

VCCO1

M10, M14⁸, H12,

64, 75, 91, 106, 119 78, 92, 110, 128, D11, F13, H10, J10, L13, N11

144

VCCO (Bank 1) A10, C13⁸

GND

B1, P2, N14, A13

1, 37, 73, 109

2, 46⁵, 65, 90, 134, A1, A16, C6, C11, F3, F14, G7, G10, H8,

153

10, 18⁶, 27, 46, 127, 13, 31, 55, 155,

137 167

GND (Bank 1) N11, K13, E13, B11 55, 65, 82, 90⁶, 99, 67, 79, 101, 119,

H9, J8, J9, K7, K10, L3, L14, P6, P11, T1,

T16

GND (Bank 0) E2, K2, N4, B4

118

143

NC

4064Z: C1, C3, E1, 4128V: 17, 20, 38,

E3, H2, J3, K1, M2, 45, 72, 89, 92, 110, 131, 132, 133

M4, N5, P7, P8, M8, 117, 144

1, 43, 44, 45, 89, 4256V/B/C, 128 I/O: A4, A5, A6, A11, A12,

A13, A15, B5, B6, B11, B12, B14, C7, D1,

D4, D5, D10, D12, D16, E1, E2, E4, E5, E7,

E10, E13, E14, E15, E16, F1, F2, F15, F16,

G1, G4, G5, G6, G12, G13, G14, J11, K3,

K4, K15, L1, L2, L12, L15, L16, M1, M2, M3,

M4, M5, M12, M13, M15, M16, N1, N2, N7,

N10, N12, N14, P5, P12, R4, R5, R6, R11,

R12, R16, T2, T4, T5, T6, T11, T12, T13, T15

P10, P11, P14, M12,

K14, K12, G13,

G14, E14, C13, B13,

B10, C10, A7, B5,

A5, A4, A1

4256V: 18, 90

4128Z: P8, A7

4256V/B/C, 160 I/O: A5, A12, A15, B5, B6,

B11, B12, B14, D4, D5, D12, E1, E4, E5,

E13, E15, E16, F1, F2, F15, G1, G5, G12,

G14, L1, L2, L12, L15, L16, M1, M2, M3,

M12, M16, N1, N12, N14, P5, R4, R5, R6,

R11, R12, R16, T4, T5, T12, T15

4384V/B/C: B5, B12, D5, D12, E1, E15,

E16, F2, L12, M1, M2, M16, N12, R5, R12,

T4

4512V/B/C: None

1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with

the bank shown.

2. Internal GNDs and I/O GNDs (Bank 0/1) are connected inside package.

3. V

balls connect to two power planes within the package, one for V

and one for V

.

CCO1

CCO

CCO0

4. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.

5. ispMACH 4384V/B/C pin 46 is tied to GND (Bank 0).

6. ispMACH 4128V only.

7. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

8. ispMACH 4128Z and 4256Z only. NC for ispMACH 4064Z.

9. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.

44

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:

44-Pin TQFP

ispMACH 4032V/B/C

ispMACH 4064V/B/C

Pin Number

Bank Number

GLB/MC/Pad ORP

GLB/MC/Pad

ORP

-

1

-

TDI

-

A^5

A^6

A^7

-

TDI

2

0

-

A5

A10

A^5

A^6

A^7

-

3

A6

A12

4

A7

A14

5

GND (Bank 0)

6

VCCO (Bank 0)

-

VCCO (Bank 0)

-

7

A8

A9

A^8

A^9

A^10

-

B0

B2

B^0

B^1

B^2

-

8

9

A10

B4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

TCK

-

VCC

GND

A12

-

VCC

GND

B8

-

0

1

-

A^12

A^13

A^14

A^15

-

B^4

B^5

B^6

B^7

-

A13

B10

A14

B12

A15

B14

CLK2/I

B0

CLK2/I

C0

B^0

B^1

B^2

B^3

B^4

-

C^0

C^1

C^2

C^3

C^4

-

B1

C2

B2

C4

B3

C6

B4

C8

TMS

B5

TMS

C10

1

-

B^5

B^6

B^7

-

C^5

C^6

C^7

-

B6

C12

B7

C14

GND (Bank 1)

VCCO (Bank 1)

B8

GND (Bank 1)

VCCO (Bank 1)

D0

-

B^8

B^9

B^10

-

D^0

D^1

D^2

-

B9

D2

B10

D4

TDO

VCC

GND

B12

TDO

VCC

GND

D8

-

1

0

B^12

B^13

B^14

B^15

-

D^4

D^5

D^6

D^7

-

B13

D10

B14

D12

B15/GOE1

CLK0/I

A0/GOE0

A1

D14/GOE1

CLK0/I

A0/GOE0

A2

A^0

A^1

A^0

A^1

45

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:

44-Pin TQFP (Cont.)

ispMACH 4032V/B/C

ispMACH 4064V/B/C

Pin Number

Bank Number

GLB/MC/Pad

ORP

A^2

A^3

A^4

GLB/MC/Pad

ORP

A^2

A^3

A^4

42

43

44

0

A2

A3

A4

A6

A8

ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections:

48-Pin TQFP

ispMACH 4032V/B/C/Z

ispMACH 4064V/B/C

ispMACH 4064Z

Bank

Number Number GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

-

TDI

2

0

-

A5

A^5

A^6

A^7

-

A10

A^5

A^6

A^7

-

A8

A^5

A^6

A^7

-

3

A6

A12

A10

4

A7

A14

A11

5

GND (Bank 0)

6

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

7

A8

A^8

A^9

A^10

A^11

-

B0

B^0

B^1

B^2

B^3

-

B15

B^7

B^6

B^5

B^4

-

8

A9

B2

B12

9

A10

B4

B10

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A11

B6

B8

TCK

-

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

0

1

-

A12

A^12

A^13

A^14

A^15

-

B8

B^4

B^5

B^6

B^7

-

B6

B^3

B^2

B^1

B^0

-

A13

B10

B4

A14

B12

B2

A15

B14

B0

CLK1/I

CLK2/I

-

CLK2/I

-

CLK2/I

-

B0

B^0

B^1

B^2

B^3

B^4

-

C0

C^0

C^1

C^2

C^3

C^4

-

C0

C^0

C^1

C^2

C^3

C^4

-

B1

C2

C1

B2

C4

C2

B3

C6

C4

B4

C8

C6

TMS

1

B5

B^5

B^6

B^7

-

C10

C^5

C^6

C^7

-

C8

C^5

C^6

C^7

-

B6

C12

C14

C10

B7

GND (Bank 1)

VCCO (Bank 1)

B8

C11

GND (Bank 1)

VCCO (Bank 1)

D0

GND (Bank 1)

VCCO (Bank 1)

D15

-

B^8

B^9

D^0

D^1

D^7

D^6

B9

D2

D12

46

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections:

48-Pin TQFP (Cont.)

ispMACH 4032V/B/C/Z

ispMACH 4064V/B/C

ispMACH 4064Z

Bank

Number Number GLB/MC/Pad

ORP

B^10

B^11

-

GLB/MC/Pad

ORP

D^2

D^3

-

GLB/MC/Pad

ORP

D^5

D^4

-

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

1

-

B10

B11

D4

D6

D10

D8

TDO

VCC

GND

B12

TDO

VCC

GND

D8

TDO

VCC

GND

D6

-

1

0

B^12

B^13

B^14

B^15

-

D^4

D^5

D^6

D^7

-

D^3

D^2

D^1

D^0

-

B13

D10

D4

B14

D12

D2

B15/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

D14/GOE1

CLK3/I

CLK0/I

A0/GOE0

A2

D0/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

-

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A2

A4

A2

A3

A6

A4

A8

A6

ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA

ispMACH 4032Z

ispMACH 4064Z

Ball Number

Bank Number

GLB/MC/Pad

ORP

GLB/MC/Pad ORP

B1

C3

C1

D1

D3

E3

E1

F3

F1

G3

G1

H1

J1

-

TDI

-

TDI

-

A^5

A^6

A^7

-

0

-

A5

A^5

A8

A6

A^6

A10

A7

A^7

A11

GND (Bank 0)

-

GND (Bank 0)

NC¹

-

I¹

-

VCCO (Bank 0)

A8

-

A^8

A^9

A^10

A^11

-

VCCO (Bank 0)

-

B15

B12

B10

B8

B^7

B^6

B^5

B^4

-

A9

A10

A11

NC

I

K1

K2

H3

K3

K4

H4

H5

TCK

-

TCK

VCC

GND

I¹

-

VCC

GND

NC¹

-

0

A12

A^12

A^13

A^14

B6

B^3

B^2

B^1

A13

B4

A14

B2

47

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA (Cont.)

ispMACH 4032Z

ispMACH 4064Z

Ball Number

K5

Bank Number

GLB/MC/Pad

ORP

A^15

-

GLB/MC/Pad

ORP

B^0

-

0

1

-

A15

CLK1/I

CLK2/I

B0

H6

CLK1/I

K6

-

CLK2/I

-

H7

B^0

B^1

B^2

B^3

B^4

-

C0

C^0

C^1

C^2

C^3

C^4

-

K7

B1

C1

K8

B2

C2

K9

B3

C4

K10

J10

H8

B4

C6

TMS

B5

TMS

1

-

B^5

B^6

B^7

-

C8

C^5

C^6

C^7

-

H10

G10

G8

B6

C10

B7

C11

GND (Bank 1)

NC¹

GND (Bank 1)

F8

-

I¹

-

F10

E8

NC¹

-

VCCO (Bank 1)

B8

-

VCCO (Bank 1)

-

E10

D8

B^8

B^9

B^10

B^11

-

D15

D12

D10

D8

D^7

D^6

D^5

D^4

-

B9

D10

C10

B10

A10

A9

B10

B11

NC¹

I¹

TDO

VCC

GND

NC¹

-

TDO

VCC

GND

I¹

-

C8

-

A8

1

0

-

A7

B12

B^12

B^13

B^14

B^15

-

D6

D^3

D^2

D^1

D^0

-

C7

B13

D4

C6

B14

D2

A6

B15/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

D0/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

C5

A5

-

C4

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A4

A3

A2

A3

A4

A1

A4

A6

1. For device migration considerations, these NC pins are input signal pins in ispMACH 4064Z devices.

48

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

2

-

GND

-

TDI

-

TDI

-

TDI

-

3

0

-

A8

A^8

A^9

A^10

A^11

-

B0

B^0

B^1

B^2

B^3

-

C12

C^3

C^2

C^1

C^0

-

4

A9

B2

C10

5

A10

B4

C6

6

A11

B6

C2

7

GND (Bank 0)

8

A12

A^12

A^13

A^14

A^15

-

B8

B^4

B^5

B^6

B^7

-

D12

D^3

D^2

D^1

D^0

-

9

A13

B10

D10

10

11

12*

13

14

15

16

17

18

19

20

21

22

23*

24

25

26

27*

28

29

30

31

32

33

34

35

36

37

38

39

40

41

A14

B12

D6

A15

B13

D4

I

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

B15

B^15

B^14

B^13

B^12

-

C14

C^7

C^6

C^5

C^4

-

E4

E^0

E^1

E^2

E^3

-

B14

C12

E6

B13

C10

E10

B12

C8

E12

GND (Bank 0)

B11

B^11

B^10

B^9

B^8

-

C6

C^3

C^2

C^1

C^0

-

F2

F^0

F^1

F^2

F^3

-

B10

C5

F6

B9

C4

F10

B8

C2

F12

I

TCK

-

TCK

-

TCK

-

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

0

1

-

I

-

I

-

I

-

B7

B^7

B^6

B^5

B^4

-

D13

D^7

D^6

D^5

D^4

-

G12

G^3

G^2

G^1

G^0

-

B6

D12

G10

B5

D10

G6

B4

D8

G2

GND (Bank 0)

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

B3

B2

B^3

B^2

B^1

B^0

-

D6

D4

D^3

D^2

D^1

D^0

-

H12

H10

H6

H^3

H^2

H^1

H^0

-

B1

D2

B0

D0

H2

CLK1/I

CLK2/I

VCC

C0

CLK1/I

CLK2/I

VCC

E0

CLK1/I

CLK2/I

VCC

I2

-

1

C^0

E^0

I^0

49

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP (Cont.)

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

42

Number

GLB/MC/Pad

ORP

C^1

C^2

C^3

-

GLB/MC/Pad

ORP

E^1

E^2

E^3

-

GLB/MC/Pad

ORP

I^1

I^2

I^3

-

1

-

C1

E2

I6

43

C2

E4

I10

44

C3

E6

I12

45

VCCO (Bank 1)

46

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

-

47

C4

C^4

C^5

C^6

C^7

-

E8

E^4

E^5

E^6

E^7

-

J2

J^0

J^1

J^2

J^3

-

48

C5

E10

J6

49

C6

E12

J10

50

C7

E14

J12

51

GND

52

-

TMS

-

TMS

-

TMS

-

53

1

-

C8

C^8

C^9

C^10

C^11

-

F0

F^0

F^1

F^2

F^3

-

K12

K^3

K^2

K^1

K^0

-

54

C9

F2

K10

55

C10

F4

K6

56

C11

F6

K2

57

GND (Bank 1)

58

C12

C^12

C^13

C^14

C^15

-

F8

F^4

F^5

F^6

F^7

-

L12

L^3

L^2

L^1

L^0

-

59

C13

F10

L10

60

C14

F12

L6

61

C15

F13

L4

62*

63

I

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

64

D15

D^15

D^14

D^13

D^12

-

G14

G^7

G^6

G^5

G^4

-

M4

M^0

M^1

M^2

M^3

-

65

D14

G12

M6

66

D13

G10

M10

67

D12

G8

M12

68

GND (Bank 1)

69

D11

D^11

D^10

D^9

D^8

-

G6

G^3

G^2

G^1

G^0

-

N2

N^0

N^1

N^2

N^3

-

70

D10

G5

N6

71

D9

G4

N10

72

D8

G2

N12

73*

74

I

TDO

-

TDO

-

TDO

-

75

-

VCC

-

VCC

-

VCC

-

76

-

GND

-

GND

-

GND

-

77*

78

1

I

-

I

H13

-

I

-

D7

D^7

D^6

D^5

D^4

-

H^7

H^6

H^5

H^4

-

O12

O10

O^3

O^2

O^1

O^0

-

79

D6

H12

80

D5

D4

H10

O6

81

H8

O2

82

GND (Bank 1)

50

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP (Cont.)

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

83

1

0

-

VCCO (Bank 1)

84

D3

D^3

D^2

D^1

D^0

-

H6

H4

H^3

H^2

H^1

H^0

-

P12

P10

P^3

P^2

P^1

P^0

-

85

D2

86

D1

H2

P6

87

D0/GOE1

H0/GOE1

CLK3/I

CLK0/I

VCC

P2/OE1

CLK3/I

CLK0/I

VCC

88

CLK3/I

89

CLK0/I

-

90

VCC

-

91

0

A0/GOE0

A^0

A^1

A^2

A^3

-

A0/GOE0

A2

A^0

A^1

A^2

A^3

-

A2/GOE0

A6

A^0

A^1

A^2

A^3

-

92

A1

93

A2

A4

A10

94

A3

A6

A12

95

VCCO (Bank 0)

GND (Bank 0)

A8

VCCO (Bank 0)

GND (Bank 0)

B2

96

GND (Bank 0)

-

97

A4

A5

A6

A7

A^4

A^5

A^6

A^7

A^4

A^5

A^6

A^7

B^0

B^1

B^2

B^3

98

A10

B6

99

A12

B10

100

A14

B12

*This pin is input only.

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP

ispMACH 4128V/B/C

Pin Number

Bank Number

GLB/MC/Pad

ORP

-

1

2

0

GND

TDI

-

3

VCCO (Bank 0)

-

4

B0

B^0

B^1

B^2

B^3

B^4

B^5

-

5

B1

6

B2

7

B4

8

B5

9

B6

10

11

12

13

14

15

16

17

18

GND (Bank 0)

B8

B^6

B^7

B^8

B^9

B^10

B^11

-

B9

B10

B12

B13

B14

VCCO (Bank 0)

C14

C^11

51

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

Bank Number

GLB/MC/Pad

ORP

C^10

C^9

C^8

C^7

C^6

-

0

1

C13

C12

C10

C9

C8

GND (Bank 0)

C6

C^5

C^4

C^3

C^2

C^0

-

C5

C4

C2

C0

VCCO (Bank 0)

TCK

-

VCC

-

GND

-

D14

D^11

D^10

D^9

D^8

D^7

D^6

-

D13

D12

D10

D9

D8

GND (Bank 0)

VCCO (Bank 0)

-

D6

D^5

D^4

D^3

D^2

D^1

D^0

-

D5

D4

D2

D1

D0

CLK1/I

GND (Bank 1)

-

CLK2/I

-

VCC

-

E0

E^0

E^1

E^2

E^3

E^4

E^5

-

E1

E2

E4

E5

E6

VCCO (Bank 1)

GND (Bank 1)

E8

-

E^6

E^7

E9

52

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

62

Bank Number

GLB/MC/Pad

ORP

E^8

E^9

E^11

-

1

E10

63

E12

64

E14

65

GND

66

TMS

-

67

VCCO (Bank 1)

-

68

F0

F^0

F^1

F^2

F^3

F^4

F^5

-

69

F1

70

F2

71

F4

72

F5

73

F6

74

GND (Bank 1)

75

F8

F^6

F^7

F^8

F^9

F^10

F^11

-

76

F9

77

F10

78

F12

79

F13

80

F14

81

VCCO (Bank 1)

82

G14

G^11

G^10

G^9

G^8

G^7

G^6

-

83

G13

84

G12

85

G10

86

G9

87

G8

88

GND (Bank 1)

89

G6

G^5

G^4

G^3

G^2

G^0

-

90

G5

91

G4

92

G2

93

G0

94

VCCO (Bank 1)

95

TDO

VCC

-

96

-

97

GND

-

98

H14

H^11

H^10

H^9

H^8

H^7

H^6

-

99

H13

100

101

102

103

104

H12

H10

H9

H8

GND (Bank 1)

53

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

Bank Number

GLB/MC/Pad

ORP

-

1

0

VCCO (Bank 1)

H6

H^5

H^4

H^3

H^2

H^1

H^0

-

H5

H4

H2

H1

H0/GOE1

CLK3/I

GND (Bank 0)

-

CLK0/I

-

VCC

-

A0/GOE0

A^0

A^1

A^2

A^3

A^4

A^5

-

A1

A2

A4

A5

A6

VCCO (Bank 0)

GND (Bank 0)

-

A8

A9

A^6

A^7

A^8

A^9

A^11

A10

A12

A14

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA

ispMACH 4064Z

ispMACH 4128Z

ispMACH 4256Z

Ball Number Bank Number GLB/MC/Pad ORP

GLB/MC/Pad ORP

GLB/MC/Pad

ORP

B1

B2

C1

C3

C2

D1

D3

D2

E1

E2

-

GND

-

GND

-

GND

-

TDI

-

TDI

-

0

NC

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

NC

-

B0

B^0

B^1

B^2

B^3

B^4

B^5

-

C12

C^6

C^5

C^4

C^3

C^2

C^1

-

A8

A^8

A^9

A^10

A^11

B1

C10

A9

A10

B2

C8

B4

C6

A11

B5

B6

C4

C2

NC

GND (Bank 0)

-

GND (Bank 0)

54

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

ispMACH 4128Z

ispMACH 4256Z

Ball Number Bank Number GLB/MC/Pad ORP

GLB/MC/Pad

ORP

B^6

B^7

B^8

B^9

B^10

B^11

-

GLB/MC/Pad

ORP

D^6

D^5

D^4

D^3

D^2

D^1

-

E3

F2

F1

F3

G1

G2

G3

H2

H1

H3

J1

0

-

NC

-

B8

D12

A12

A^12

B9

D10

A13

A^13

B10

D8

A14

A^14

B12

D6

A15

A^15

B13

D4

I

-

B14

D2

VCCO (Bank 0)

-

VCCO (Bank 0)

NC

-

C14

C^11

C^10

C^9

C^8

C^7

C^6

-

E2

E^1

E^2

E^3

E^4

E^5

E^6

-

B15

B^15

C13

E4

B14

B^14

C12

E6

B13

B^13

C10

E8

J2

B12

B^12

C9

E10

J3

NC

-

C8

E12

K2

K1

K3

L2

GND (Bank 0)

-

GND (Bank 0)

NC

-

C6

C^5

C^4

C^3

C^2

C^1

C^0

-

F2

F^1

F^2

F^3

F^4

F^5

F^6

-

B11

B^11

C5

F4

B10

B^10

C4

F6

L1

B9

B^9

C2

F8

L3

B8

B^8

C1

F10

M1

M2

N1

P1

P2

N2

P3

M3

N3

P4

M4

N4

P5

N5

M5

N6

P6

M6

P7

N7

M7

N8

I

-

C0

F12

NC

-

VCCO (Bank 0)

TCK

-

TCK

-

TCK

-

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

0

1

-

I

-

D14

D^11

D^10

D^9

D^8

D^7

D^6

-

G12

G^6

G^5

G^4

G^3

G^2

G^1

-

B7

B^7

D13

G10

B6

B^6

D12

G8

B5

B^5

D10

G6

B4

B^4

D9

G4

NC

-

D8

G2

GND (Bank 0)

VCCO (Bank 0)

H12

GND (Bank 0)

-

GND (Bank 0)

VCCO (Bank 0)

-

VCCO (Bank 0)

-

NC

B3

-

B^3

B^2

B^1

B^0

-

D6

D5

D^5

D^4

D^3

D^2

D^1

D^0

-

H^6

H^5

H^4

H^3

H^2

H^1

-

H10

B2

D4

H8

B1

D2

H6

B0

D1

H4

NC

D0

H2

CLK1/I

CLK2/I

VCC

-

CLK1/I

CLK2/I

VCC

CLK1/I

CLK2/I

VCC

-

55

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

ispMACH 4128Z

ispMACH 4256Z

GLB/MC/Pad ORP

I¹

Ball Number Bank Number GLB/MC/Pad ORP

GLB/MC/Pad ORP

P8

1

-

NC¹

-

NC¹

-

M8

NC

-

E0

E^0

E^1

E^2

E^3

E^4

E^5

-

I2

I^1

I^2

I^3

I^4

I^5

I^6

-

P9

C0

C^0

E1

I4

N9

C1

C^1

E2

I6

M9

C2

C^2

E4

I8

N10

P10

M10

N11

P11

M11

P12

N12

P13

P14

N14

N13

M14

M12

M13

L14

L12

L13

K14

K13

K12

J13

J14

J12

H14

H13

H12

G13

G14

G12

F14

F13

F12

E13

E14

E12

C3

C^3

E5

I10

NC

-

E6

I12

VCCO (Bank 1)

-

VCCO (Bank 1)

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

-

NC

-

E8

E^6

E^7

E^8

E^9

E^10

E^11

-

J2

J^1

J^2

J^3

J^4

J^5

J^6

-

C4

C^4

E9

J4

C5

C^5

E10

J6

C6

C^6

E12

J8

C7

C^7

E13

J10

NC

-

E14

J12

GND

-

GND

-

TMS

-

TMS

-

TMS

-

1

NC

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

NC

-

C^8

C^9

C^10

C^11

-

F0

F^0

F^1

F^2

F^3

F^4

F^5

-

K12

K^6

K^5

K^4

K^3

K^2

K^1

-

C8

F1

K10

C9

F2

K8

C10

F4

K6

C11

F5

K4

NC

F6

K2

GND (Bank 1)

-

GND (Bank 1)

NC

-

F8

F^6

F^7

F^8

F^9

F^10

F^11

-

L12

L^6

L^5

L^4

L^3

L^2

L^1

-

C12

C^12

C^13

C^14

C^15

-

F9

L10

C13

F10

L8

C14

F12

L6

C15

F13

L4

I

F14

L2

VCCO (Bank 1)

-

VCCO (Bank 1)

NC

-

G14

G^11

G^10

G^9

G^8

G^7

G^6

-

M2

M^1

M^2

M^3

M^4

M^5

M^6

-

G13

M4

D15

D^15

D^14

D^13

D^12

-

G12

M6

D14

G10

M8

M10

D13

G9

D12

G8

GND (Bank 1)

G6

M12

GND (Bank 1)

NC

GND (Bank 1)

N2

-

G^5

G^4

N^1

N^2

D11

D^11

G5

N4

56

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

ispMACH 4128Z

ispMACH 4256Z

Ball Number Bank Number GLB/MC/Pad ORP

GLB/MC/Pad

ORP

G^3

G^2

G^1

G^0

-

GLB/MC/Pad

ORP

N^3

N^4

N^5

N^6

-

D13

D14

D12

C14

C13

B14

A14

A13

B13

A12

C12

B12

A11

C11

B11

A10

B10

C10

B9

1

-

D10

D^10

G4

N6

D9

D^9

G2

N8

D8

D^8

G1

N10

I

-

G0

N12

NC

-

VCCO (Bank 1)

TDO

-

TDO

-

TDO

-

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

1

0

-

NC

-

H14

H^11

H^10

H^9

H^8

H^7

H^6

-

O12

O^6

O^5

O^4

O^3

O^2

O^1

-

I

-

D^7

D^6

D^5

D^4

-

H13

O10

D7

H12

O8

D6

H10

O6

D5

H9

O4

D4

H8

O2

GND (Bank 1)

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

NC

-

H6

H^5

H^4

H^3

H^2

H^1

H^0

-

P12

P^6

P^5

P^4

P^3

P^2

P^1

-

NC

-

H5

P10

D3

D^3

D^2

D^1

D^0

-

H4

P8

A9

D2

H2

P6

C9

D1

H1

H0/GOE1

CLK3/I

CLK0/I

VCC

P4

A8

D0/GOE1

P2/GOE1

B8

CLK3/I

C8

CLK0/I

-

CLK0/I

-

B7

VCC

-

VCC

-

A7

0

NC¹

-

NC¹

-

I¹

-

C7

A0/GOE0

A^0

A^1

A^2

A^3

-

A0/GOE0

A1

A^0

A^1

A^2

A^3

A^4

A^5

-

A2/GOE0

A^1

A^2

A^3

A^4

A^5

A^6

-

A6

A1

A4

B6

A2

A6

C6

A3

A4

A8

B5

NC

A5

A10

A5

NC

-

A6

A12

C5

VCCO (Bank 0)

-

VCCO (Bank 0)

GND (Bank 0)

A8

VCCO (Bank 0)

B4

GND (Bank 0)

-

GND (Bank 0)

-

A4

NC

A4

A5

A6

A7

NC

-

A^6

A^7

A^8

A^9

A^10

A^11

B2

B4

B^1

B^2

B^3

B^4

B^5

B^6

C4

A^4

A^5

A^6

A^7

-

A9

A3

A10

B6

B3

A12

B8

A2

A13

B10

B12

A1

A14

1. For device migration considerations, these NC pins are input signal pins in ispMACH 4256Z device.

57

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP

ispMACH 4128V

ispMACH 4256V

Pin Number

Bank Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

-

GND

2

-

TDI

-

TDI

-

3

0

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

4

B0

B^0

B^1

B^2

B^3

B^4

B^5

-

C12

C^6

C^5

C^4

C^3

C^2

C^1

-

5

B1

C10

6

B2

C8

7

B4

C6

8

B5

C4

9

B6

C2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

GND (Bank 0)

B8

B^6

B^7

B^8

B^9

B^10

B^11

-

D14

D^7

D^6

D^5

D^4

D^3

D^2

-

B9

D12

B10

D10

B12

D8

B13

D6

B14

NC²

GND (Bank 0)¹

D4

I²

NC¹

0

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

NC²

-

I²

-

C14

C^11

C^10

C^9

C^8

C^7

C^6

-

E2

E^1

E^2

E^3

E^4

E^5

E^6

-

C13

E4

C12

E6

C10

E8

C9

E10

C8

E12

GND (Bank 0)

C6

C^5

C^4

C^3

C^2

C^1

C^0

-

F2

F^1

F^2

F^3

F^4

F^5

F^6

-

C5

F4

C4

C2

F6

F8

C1

F10

C0

F12

VCCO (Bank 0)

TCK

VCCO (Bank 0)

-

TCK

VCC

GND

I²

-

VCC

-

GND

NC²

-

0

-

D14

D^11

D^10

D^9

D^8

G12

G10

G8

G^6

G^5

G^4

G^3

D13

D12

D10

G6

58

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

ispMACH 4256V

Pin Number

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Bank Number

GLB/MC/Pad

ORP

D^7

D^6

-

GLB/MC/Pad

ORP

G^2

G^1

-

0

1

-

D9

G4

D8

NC²

G2

I²

GND (Bank 0)

-

GND (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

D6

D^5

D^4

D^3

D^2

D^1

D^0

-

H12

H^6

H^5

H^4

H^3

H^2

H^1

-

D5

H10

D4

H8

D2

H6

D1

H4

D0

H2

CLK1/I

GND (Bank 1)

-

GND (Bank 1)

-

CLK2/I

-

CLK2/I

-

VCC

-

VCC

-

1

-

E0

E^0

E^1

E^2

E^3

E^4

E^5

-

I2

I^1

I^2

I^3

I^4

I^5

I^6

-

E1

I4

E2

I6

E4

I8

E5

I10

E6

I12

VCCO (Bank 1)

GND (Bank 1)

-

GND (Bank 1)

-

E8

E^6

E^7

E^8

E^9

E^10

E^11

-

J2

J^1

J^2

J^3

J^4

J^5

J^6

-

E9

J4

E10

J6

E12

J8

E13

J10

E14

NC²

J12

I²

GND

-

GND

-

TMS

-

TMS

-

1

VCCO (Bank 1)

-

VCCO (Bank 1)

-

F0

F^0

F^1

F^2

F^3

F^4

F^5

-

K12

K^6

K^5

K^4

K^3

K^2

K^1

-

F1

K10

F2

K8

F4

K6

F5

K4

F6

K2

GND (Bank 1)

L14

GND (Bank 1)

F8

F9

F^6

F^7

F^8

L^7

L^6

L^5

L12

F10

L10

59

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

ispMACH 4256V

Pin Number

86

Bank Number

GLB/MC/Pad

ORP

F^9

F^10

F^11

-

GLB/MC/Pad

ORP

L^4

L^3

L^2

-

1

-

F12

L8

87

F13

L6

88

F14

NC²

GND (Bank 1)¹

L4

I²

NC¹

89

90

-

91

VCCO (Bank 1)

-

VCCO (Bank 1)

-

92

NC²

-

I²

-

93

G14

G^11

G^10

G^9

G^8

G^7

G^6

-

M2

M^1

M^2

M^3

M^4

M^5

M^6

-

94

G13

M4

95

G12

M6

96

G10

M8

97

G9

M10

98

G8

M12

99

GND (Bank 1)

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

G6

G^5

G^4

G^3

G^2

G^1

G^0

-

N2

N^1

N^2

N^3

N^4

N^5

N^6

-

G5

N4

G4

N6

G2

N8

G1

N10

G0

N12

VCCO (Bank 1)

TDO

-

TDO

-

VCC

-

VCC

-

GND

NC²

-

GND

I²

-

1

0

-

H14

H^11

H^10

H^9

H^8

H^7

H^6

-

O12

O^6

O^5

O^4

O^3

O^2

O^1

-

H13

O10

H12

O8

H10

O6

H9

O4

H8

NC²

O2

I²

GND (Bank 1)

VCCO (Bank 1)

P12

GND (Bank 1)

VCCO (Bank 1)

H6

-

H^5

H^4

H^3

H^2

H^1

H^0

-

P^6

P^5

P^4

P^3

P^2

P^1

-

H5

P10

H4

P8

H2

P6

H1

P4

H0/GOE1

CLK3/I

GND (Bank 0)

CLK0/I

P2/GOE1

CLK3/I

-

GND (Bank 0)

CLK0/I

-

60

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

ispMACH 4256V

Pin Number

129

Bank Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

VCC

130

0

A0/GOE0

A^0

A^1

A^2

A^3

A^4

A^5

-

A2/GOE0

A^1

A^2

A^3

A^4

A^5

A^6

-

131

A1

A4

132

A2

A6

133

A4

A8

134

A5

A10

135

A6

A12

136

VCCO (Bank 0)

137

GND (Bank 0)

-

GND (Bank 0)

-

138

A8

A^6

A^7

A^8

A^9

A^10

A^11

-

B2

B4

B6

B8

B10

B12

I²

B^1

B^2

B^3

B^4

B^5

B^6

-

139

A9

140

A10

A12

A13

A14

NC²

141

142

143

144

1. For device migration considerations, these NC pins are GND pins for I/O banks in ispMACH 4128V devices.

2. For device migration considerations, these NC pins are input signal pins in ispMACH 4256V devices.

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

2

-

NC

-

GND

-

GND

-

GND

-

3

-

TDI

-

TDI

-

TDI

-

4

0

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

5

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

6

C12

7

C10

8

C8

9

C6

10

11

12

13

14

15

16

17

18

C4

C2

C0

GND (Bank 0)

G14

GND (Bank 0)

D14

D12

D10

D8

D^7

D^6

D^5

D^4

D^3

E14

E12

E10

E8

E^7

E^6

E^5

E^4

E^3

G^7

G^6

G^5

G^4

G^3

G12

G10

G8

D6

E6

G6

61

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

Number

GLB/MC/Pad

ORP

D^2

D^1

D^0

-

GLB/MC/Pad

ORP

E^2

E^1

E^0

-

GLB/MC/Pad

ORP

G^2

G^1

G^0

-

0

-

D4

E4

G4

D2

E2

G2

D0

E0

G0

VCCO (Bank 0)

E0

E^0

E^1

E^2

E^3

E^4

E^5

E^6

E^7

-

H0

H^0

H^1

H^2

H^3

H^4

H^5

H^6

H^7

-

J0

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

E2

H2

J2

E4

H4

J4

E6

H6

J6

E8

H8

J8

E10

H10

J10

E12

H12

J12

E14

H14

J14

GND (Bank 0)

F0

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

-

J0

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

N0

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

F2

J2

N2

F4

J4

N4

F6

J6

N6

F8

J8

N8

F10

J10

N10

F12

J12

N12

F14

J14

N14

VCCO (Bank 0)

TCK

-

TCK

-

TCK

-

VCC

-

VCC

-

VCC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

GND

-

GND (Bank 0)

-

GND

-

0

G14

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

K14

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

O14

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

-

G12

K12

O12

G10

K10

O10

G8

K8

O8

G6

K6

O6

G4

K4

O4

G2

G0

K2

O2

O0

K0

GND (Bank 0)

VCCO (Bank 0)

L14

GND (Bank 0)

VCCO (Bank 0)

H14

GND (Bank 0)

VCCO (Bank 0)

P14

-

H^7

H^6

H^5

L^7

L^6

L^5

P^7

P^6

P^5

H12

L12

P12

H10

L10

P10

62

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

60

Number

GLB/MC/Pad

ORP

H^4

H^3

H^2

H^1

H^0

-

GLB/MC/Pad

ORP

L^4

L^3

L^2

L^1

L^0

-

GLB/MC/Pad

ORP

P^4

P^3

P^2

P^1

P^0

-

0

-

H8

L8

P8

P6

61

H6

L6

62

H4

L4

P4

63

H2

L2

P2

64

H0

L0

P0

65

GND

66

0

1

-

CLK1/I

-

CLK1/I

-

CLK1/I

GND (Bank 1)

CLK2/I

VCC

-

67

GND (Bank 1)

-

GND (Bank 1)

-

68

CLK2/I

-

CLK2/I

-

69

VCC

-

VCC

-

70

1

-

I0

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

-

M0

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

AX0

AX^0

AX^1

AX^2

AX^3

AX^4

AX^5

AX^6

AX^7

-

71

I2

M2

AX2

72

I4

M4

AX4

73

I6

M6

AX6

74

I8

M8

AX8

75

I10

M10

AX10

AX12

AX14

VCCO (Bank 1)

GND (Bank 1)

BX0

76

I12

M12

77

I14

M14

78

VCCO (Bank 1)

79

GND (Bank 1)

-

GND (Bank 1)

-

80

J0

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

N0

N2

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

BX^0

BX^1

BX^2

BX^3

BX^4

BX^5

BX^6

BX^7

-

81

J2

BX2

82

J4

N4

BX4

83

J6

N6

BX6

84

J8

N8

BX8

85

J10

N10

N12

N14

VCC

NC

BX10

BX12

BX14

VCC

86

J12

87

J14

88

VCC

89

-

NC

-

NC

-

90

-

GND

-

GND

TMS

VCCO (Bank 1)

O14

O12

O10

O8

-

GND

-

91

-

TMS

-

TMS

-

92

1

VCCO (Bank 1)

-

VCCO (Bank 1)

CX14

CX12

CX10

CX8

-

93

K14

K12

K10

K8

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

CX^7

CX^6

CX^5

CX^4

CX^3

CX^2

CX^1

CX^0

94

95

96

97

K6

O6

CX6

98

K4

O4

CX4

99

K2

O2

CX2

100

K0

O0

CX0

63

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

-

GND (Bank 1)

AX14

AX12

AX10

AX8

GND (Bank 1)

GX14

GX12

GX10

GX8

L14

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

AX^7

AX^6

AX^5

AX^4

AX^3

AX^2

AX^1

AX^0

-

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

GX^0

-

L12

L10

L8

L6

AX6

GX6

L4

AX4

GX4

L2

AX2

GX2

L0

AX0

GX0

VCCO (Bank 1)

DX0

VCCO (Bank 1)

JX0

M0

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

DX^0

DX^1

DX^2

DX^3

DX^4

DX^5

DX^6

DX^7

-

JX^0

JX^1

JX^2

JX^3

JX^4

JX^5

JX^6

JX^7

-

M2

DX2

JX2

M4

DX4

JX4

M6

DX6

JX6

M8

DX8

JX8

M10

DX10

DX12

DX14

GND (Bank 1)

FX0

JX10

M12

JX12

M14

JX14

GND (Bank 1)

NX0

N0

N2

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

FX^0

FX^1

FX^2

FX^3

FX^4

FX^5

FX^6

FX^7

-

NX^0

NX^1

NX^2

NX^3

NX^4

NX^5

NX^6

NX^7

-

FX2

NX2

N4

FX4

NX4

N6

FX6

NX6

N8

FX8

NX8

N10

N12

N14

VCCO (Bank 1)

TDO

VCC

NC

FX10

FX12

FX14

VCCO (Bank 1)

TDO

NX10

NX12

NX14

VCCO (Bank 1)

TDO

-

VCC

-

VCC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

GND

O14

O12

O10

O8

-

GND

-

GND

-

1

O^7

O^6

O^5

O^4

O^3

O^2

O^1

GX14

GX12

GX10

GX8

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

OX14

OX12

OX10

OX8

OX^7

OX^6

OX^5

OX^4

OX^3

OX^2

OX^1

O6

GX6

OX6

O4

GX4

OX4

O2

GX2

OX2

64

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

Number

GLB/MC/Pad

ORP

O^0

-

GLB/MC/Pad

ORP

GX^0

-

GLB/MC/Pad

ORP

OX^0

-

1

-

O0

GX0

OX0

GND (Bank 1)

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

P14

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

HX14

HX12

HX10

HX8

HX^7

HX^6

HX^5

HX^4

HX^3

HX^2

HX^1

HX^0

-

PX14

PX12

PX10

PX8

PX^7

PX^6

PX^5

PX^4

PX^3

PX^2

PX^1

PX^0

-

P12

P10

P8

P6

HX6

PX6

P4

HX4

PX4

P2/GOE1

HX2/GOE1

HX0

PX2/GOE1

PX0

P0

GND

1

0

-

CLK3/I

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

GND (Bank 0)

-

CLK0/I

-

VCC

-

0

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A2/GOE0

A4

A2//GOE0

A4

A6

A8

A10

A12

A14

VCCO (Bank 0)

GND (Bank 0)

B0

VCCO (Bank 0)

GND (Bank 0)

B0

GND (Bank 0)

-

B0

B2

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B2

B4

B6

B8

B10

B12

B14

VCC

B10

B12

B14

VCC

65

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

VCC

-

GND

-

GND

-

GND

-

GND

-

C3

-

TDI

-

TDI

-

TDI

-

TDI

-

0

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

B1

F5

D3

C1

C2

E3

D2

F6

D1

E2

E4

G5

E1

-

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

C14

C^9

C^8

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

F^3

F^2

D^3

D^2

-

C14

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

H^0

H^1

F^2

F^3

F^4

-

C12

C10

C8

C9

C8

C6

C8

C6

C4

C6

C4

C2

C4

C2

C0

C2

C0

NC

C1

F6

H0

NC

-

C0

F4

H4

NC

-

NC

D6

F4

NC

-

NC

-

D4

F6

NC

-

NC

-

NC

F8

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

F2

F1

G1

G6

G4

H6

G3

H5

G2

H1

H2

H3

H4

-

NC

-

NC

-

NC

-

F10

F^5

F^6

F^7

H^2

H^3

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

NC

-

NC

-

D2

D^1

D^0

F^1

F^0

E^7

E^6

E^5

E^4

E^3

E^2

E^1

E^0

-

F12

NC

-

NC

-

D0

F14

NC

-

D14

D^9

D^8

D^7

D^6

D^5

D^4

D^3

D^2

D^1

D^0

-

F2

H8

NC

-

D12

F0

H12

D14

D^7

D^6

D^5

D^4

D^3

D^2

D^1

D^0

-

D10

E14

G14

D12

D9

E12

G12

D10

D8

E10

G10

D8

D6

E8

G8

D6

D4

E6

G6

D4

D2

E4

G4

D2

D1

E2

G2

D0

E0

G0

VCCO (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

J4

J3

J2

J1

K1

J5

K2

E0

E2

E4

E6

E8

E10

E12

E^0

E^1

E^2

E^3

E^4

E^5

E^6

E0

E1

E2

E4

E6

E8

E9

E^0

E^1

E^2

E^3

E^4

E^5

E^6

H0

H2

H^0

H^1

H^2

H^3

H^4

H^5

H^6

J0

J2

J^0

J^1

J^2

J^3

J^4

J^5

J^6

H4

J4

H6

J6

H8

J8

H10

H12

J10

J12

66

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

GLB/MC/Pad

ORP

E^7

E^8

E^9

-

GLB/MC/Pad

ORP

H^7

G^0

G^1

I^7

I^6

-

GLB/MC/Pad

ORP

J^7

I^0

I^1

K^0

K^1

K^2

-

J6

K3

K4

L1

L2

M1

-

0

-

E14

E^7

E10

H14

J14

NC

-

E12

G0

I0

NC

-

E14

G2

I4

NC

-

NC

I14

K0

NC

-

NC

-

I12

K2

NC

-

NC

-

NC

K4

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

M2

N1

M3

M4

N2

K5

P1

K6

N3

L5

P2

L6

R1

-

NC

-

NC

-

NC

-

K6

K^3

K^4

K^5

I^2

I^3

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

NC

-

NC

-

I10

I^5

I^4

G^2

G^3

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

K8

NC

-

NC

-

I8

K10

NC

F0

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

F^8

F^9

-

G4

I8

NC

-

F1

G6

I12

F0

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

-

F2

J0

N0

F2

F4

J2

N2

F4

F6

J4

N4

F6

F8

J6

N6

F8

F9

J8

N8

F10

J10

N10

F12

J12

N12

F14

J14

N14

VCCO (Bank 0)

P3

-

TCK

-

TCK

-

TCK

-

TCK

-

VCC

-

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

GND

-

0

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

T2

M5

N4

T3

R3

M6

P4

L7

N5

M7

P5

R4

T4

-

NC

-

G14

G^9

G^8

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

I6

I^3

I^2

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

G^4

G^5

-

K12

K^6

K^7

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

M^0

M^1

L^0

-

NC

-

G12

I4

K14

G14

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

G10

K14

O14

G12

G9

K12

O12

G10

G8

K10

O10

G8

G6

K8

O8

G6

G4

K6

O6

G4

G2

K4

O4

G2

G1

K2

O2

G0

NC

G0

NC

K0

G8

O0

M0

M4

NC

-

NC

-

G10

NC

-

NC

-

NC

L0

GND (Bank 0)

VCCO (Bank 0)

-

GND (Bank 0)

VCCO (Bank 0)

-

GND (Bank 0)

VCCO (Bank 0)

-

GND (Bank 0)

VCCO (Bank 0)

-

67

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

L4

ORP

L^1

R5

T5

0

-

NC

-

NC

-

I2

I^1

L8

L^2

R6

T6

NC

-

NC

-

I0

I^0

L12

L^3

NC

-

H14

H^9

H^8

H^7

H^6

H^5

H^4

H^3

H^2

H^1

H^0

-

G12

G^6

G^7

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

M8

M^2

M^3

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

N7

P7

NC

-

H12

G14

M12

H14

H^7

H^6

H^5

H^4

H^3

H^2

H^1

H^0

-

H10

L14

P14

R7

L8

H12

H9

L12

P12

H10

H8

L10

P10

T7

H8

H6

L8

P8

M8

N8

R8

P8

H6

H4

L6

P6

H4

H2

L4

P4

H2

H1

L2

P2

H0

L0

P0

-

GND

CLK1/I

GND (Bank 1)

CLK2/I

VCC

T8

0

1

-

CLK1/I

-

CLK1/I

-

CLK1/I

-

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

-

N9

-

CLK2/I

-

CLK2/I

-

CLK2/I

-

VCC

-

VCC

-

VCC

-

P9

1

I0

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

-

I0

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

I^8

I^9

-

M0

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

BX^7

BX^6

P^0

P^1

-

AX0

AX^0

AX^1

AX^2

AX^3

AX^4

AX^5

AX^6

AX^7

DX^0

DX^1

EX^0

EX^1

EX^2

-

R9

T9

I2

I1

M2

AX2

I4

I2

M4

AX4

T10

R10

M9

P10

L9

I6

I4

M6

AX6

I8

I6

M8

AX8

I10

I8

M10

AX10

AX12

AX14

DX0

I12

I9

M12

I14

I10

M14

N10

T11

R11

T12

N12

-

NC

I12

BX14

NC

-

I14

BX12

DX4

NC

-

NC

P0

EX0

NC

-

NC

-

P2

EX4

NC

-

NC

-

NC

EX8

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

GND (Bank 1)

EX12

DX8

-

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

-

R12

T13

P12

M10

R13

L10

T14

M11

NC

J0

-

NC

J0

J1

J2

J4

J6

J8

J9

-

NC

BX10

BX8

N0

-

EX^3

DX^2

DX^3

BX^0

BX^1

BX^2

BX^3

BX^4

-

J^0

J^1

J^2

J^3

J^4

J^5

J^6

BX^5

BX^4

N^0

N^1

N^2

N^3

N^4

-

DX12

BX0

J^0

J^1

J^2

J^3

J^4

J2

N2

BX2

J4

N4

BX4

J6

N6

BX6

J8

N8

BX8

68

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

GLB/MC/Pad

ORP

J^7

J^8

J^9

-

GLB/MC/Pad

ORP

N^5

N^6

N^7

P^2

P^3

-

GLB/MC/Pad

BX10

ORP

BX^5

BX^6

BX^7

FX^0

FX^1

-

R14

P13

N13

M12

T15

-

1

-

J10

J^5

J10

N10

J12

J^6

J12

N12

BX12

J14

J^7

J14

N14

BX14

NC

-

NC

P4

FX0

NC

-

NC

-

P6

FX2

VCC

-

VCC

-

VCC

-

GND

-

GND

-

GND

-

GND

-

1

-

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

TMS

-

P14

-

TMS

-

TMS

-

1

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

FX4

-

L12

R16

N14

P15

L11

P16

K11

M14

K12

N15

N16

M15

M13

-

NC

-

NC

-

NC

-

FX^2

FX^3

FX^4

CX^7

CX^6

CX^5

CX^4

CX^3

CX^2

CX^1

CX^0

HX^0

HX^1

-

NC

-

NC

-

P8

P^4

P^5

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

BX^3

BX^2

-

FX6

NC

-

NC

-

P10

FX8

K14

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

K14

K^9

K^8

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

O14

CX14

K12

O12

CX12

K10

O10

CX10

K8

K9

O8

CX8

K6

K8

O6

CX6

K4

K6

O4

CX4

K2

K4

O2

O0

CX2

K0

K2

CX0

NC

K1

BX6

HX0

NC

-

K0

BX4

HX4

-

VCCO (Bank 1)

GND (Bank 1)

NC

VCCO (Bank 1)

GND (Bank 1)

FX10

-

GND (Bank 1)

-

GND (Bank 1)

-

M16

L15

L16

J11

K15

J12

K13

K14

K16

J16

J15

H16

J13

-

NC

-

NC

-

FX^5

FX^6

FX^7

HX^2

HX^3

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

GX^0

-

NC

-

NC

-

P12

P^6

P^7

BX^1

BX^0

AX^7

AX^6

AX^5

AX^4

AX^3

AX^2

AX^1

AX^0

-

FX12

NC

-

NC

-

P14

FX14

NC

-

L14

L^9

L^8

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

BX2

HX8

NC

-

L12

BX0

HX12

L14

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

L10

AX14

GX14

L12

L9

AX12

GX12

L10

L8

AX10

GX10

L8

L6

AX8

GX8

L6

L4

AX6

GX6

L4

L2

AX4

GX4

L2

L1

L0

AX2

GX2

L0

AX0

GX0

VCCO (Bank 1)

GND (Bank 1)

M0

VCCO (Bank 1)

GND (Bank 1)

DX0

VCCO (Bank 1)

GND (Bank 1)

JX0

-

J14

M0

M^0

DX^0

JX^0

69

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

GLB/MC/Pad

ORP

M^1

M^2

M^3

M^4

M^5

M^6

M^7

M^8

M^9

-

GLB/MC/Pad

DX2

ORP

DX^1

DX^2

DX^3

DX^4

DX^5

DX^6

DX^7

CX^0

CX^1

EX^7

EX^6

-

GLB/MC/Pad

JX2

ORP

JX^1

JX^2

JX^3

JX^4

JX^5

JX^6

JX^7

IX^0

IX^1

KX^0

KX^1

KX^2

-

H15

H14

H13

G16

H12

G15

H11

F16

G13

G14

F15

E16

-

1

-

M2

M1

M4

M2

DX4

JX4

M6

M4

DX6

JX6

M8

M6

DX8

JX8

M10

M8

DX10

DX12

DX14

CX0

JX10

M12

M9

JX12

M14

M10

JX14

NC

M12

IX0

NC

-

M14

CX2

IX4

NC

-

NC

EX14

EX12

NC

KX0

NC

-

NC

-

KX2

NC

-

NC

-

KX4

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

VCCO (Bank 1)

NC

-

GND (Bank 1)

VCCO (Bank 1)

KX6

-

NC

-

VCCO (Bank 1)

-

E15

G12

E13

D16

E14

G11

D15

F11

C16

F12

D14

C15

B16

-

NC

-

KX^3

KX^4

KX^5

IX^2

IX^3

NX^0

NX^1

NX^2

NX^3

NX^4

NX^5

NX^6

NX^7

-

NC

-

NC

-

EX10

EX8

EX^5

EX^4

CX^2

CX^3

FX^0

FX^1

FX^2

FX^3

FX^4

FX^5

FX^6

FX^7

-

KX8

NC

-

NC

-

KX10

IX8

NC

-

N0

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

N^8

N^9

-

CX4

NC

-

N1

CX6

IX12

N0

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

N2

FX0

NX0

N2

N4

FX2

NX2

N4

N6

FX4

NX4

N6

N8

FX6

NX6

N8

N9

FX8

NX8

N10

N12

N14

VCCO (Bank 1)

TDO

VCC

GND

-

N10

FX10

FX12

FX14

VCCO (Bank 1)

TDO

NX10

NX12

NX14

VCCO (Bank 1)

TDO

N12

N14

VCCO (Bank 1)

C14

-

TDO

VCC

GND

GND (Bank 1)

NC

-

VCC

-

VCC

-

GND

-

GND

-

1

-

GND (Bank 1)

EX6

-

GND (Bank 1)

KX12

KX14

OX14

OX12

OX10

OX8

-

A15

B14

E12

A14

C13

D13

E11

B13

F10

NC

-

EX^3

EX^2

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

KX^6

KX^7

OX^7

OX^6

OX^5

OX^4

OX^3

OX^2

OX^1

NC

-

NC

-

EX4

O14

O12

O10

O8

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O14

O^9

O^8

O^7

O^6

O^5

O^4

O^3

GX14

GX12

GX10

GX8

O12

O10

O9

O6

O8

GX6

OX6

O4

O6

GX4

OX4

O2

O4

GX2

OX2

70

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

GLB/MC/Pad

ORP

O^2

O^1

O^0

-

GLB/MC/Pad

GX0

ORP

GX^0

CX^4

CX^5

-

GLB/MC/Pad

ORP

OX^0

MX^0

MX^1

LX^0

-

C12

E10

A13

D12

-

1

-

O0

O^0

O2

OX0

MX0

NC

-

O1

CX8

NC

-

O0

CX10

NC

MX4

NC

-

NC

LX0

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

VCCO (Bank 1)

NC

-

GND (Bank 1)

VCCO (Bank 1)

LX4

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

B12

A12

B11

A11

D10

C10

B10

A10

A9

F9

B9

E9

C9

-

NC

-

NC

-

LX^1

LX^2

LX^3

MX^2

MX^3

PX^7

PX^6

PX^5

PX^4

PX^3

PX^2

PX^1

PX^0

-

NC

-

NC

-

EX2

EX^1

EX^0

CX^6

CX^7

HX^7

HX^6

HX^5

HX^4

HX^3

HX^2

HX^1

HX^0

-

LX8

NC

-

NC

-

EX0

LX12

NC

-

P14

P^9

P^8

P^7

P6

P^5

P^4

P^3

P^2

P^1

P^0

CX12

CX14

HX14

HX12

HX10

HX8

MX8

NC

P12

MX12

PX14

PX12

PX10

PX8

P14

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

P10

P12

P9

P10

P8

P6

P4

HX6

PX6

P4

P2

HX4

PX4

P2/GOE1

P1/GOE1

HX2/GOE1

HX0

PX2/GOE1

PX0

P0

GND

D9

-

1

0

-

CLK3/I

-

CLK3/I

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

GND (Bank 0)

-

GND (Bank 0)

-

B8

-

CLK0/I

-

CLK0/I

-

VCC

-

VCC

-

D8

C8

A8

A7

B7

E8

D7

F8

C7

A6

B6

A5

B5

-

0

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

A^8

A^9

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

F^7

F^6

D^7

D^6

-

A0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

D^0

D^1

E^0

E^1

E^2

-

A2/GOE0

A1/GOE0

A2/GOE0

A4

A2/GOE0

A4

A2

A6

A4

A6

A8

A6

A8

A10

A8

A10

A12

A9

A12

A14

A10

A14

NC

A12

F14

D0

NC

-

A14

F12

D4

NC

-

NC

D14

E0

NC

-

NC

-

D12

E4

-

NC

VCCO (Bank 0)

GND (Bank 0)

NC

-

NC

E8

VCCO (Bank 0)

GND (Bank 0)

NC

-

VCCO (Bank 0)

GND (Bank 0)

NC

-

VCCO (Bank 0)

GND (Bank 0)

E12

-

D5

A4

-

E^3

D^2

NC

-

B0

B^0

F10

F^5

D8

71

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball ftBGA/fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

ispMACH 4256V/B/C

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

B^1

B^2

B^3

B^4

B^5

B^6

B^7

B^8

B^9

-

GLB/MC/Pad

ORP

F^4

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

D^5

D^4

-

GLB/MC/Pad

ORP

D^3

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

F^0

F^1

-

E7

A3

F7

B4

C5

A2

E6

B3

C4

D4

E5

-

0

-

NC

B0

B1

B2

B4

B6

B8

B9

B10

B12

B14

NC

VCC

-

F8

B0

D12

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B0

B2

B4

B6

B8

B10

B12

B14

NC

VCC

-

B10

B12

B14

D10

F0

-

D8

F2

-

VCC

GND

GND (Bank 0)

VCC

-

GND

GND (Bank 0)

-

0

-

Note: VCC, VCCO and GND are tied together to their respective common signal on the package substrate. See Power Supply and NC Con-

nections table for VCC/ VCCO/GND pin deﬁnitions.

72

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Part Number Description

LC XXXX X X – XX XX XXX X X XX

Production Status

Device Family

Blank = Final production

ES = Engineering Samples

Device Number

4032 = 32 Macrocells

4064 = 64 Macrocells

4128 = 128 Macrocells

4256 = 256 Macrocells

4384 = 384 Macrocells

4512 = 512 Macrocells

Operating Temperature Range

C = Commercial

I = Industrial

E = Extended¹

I/O Designator (if applicable)

A = 128 I/Os

Power

Z = Zero Power

Blank = Low Power

B = 160 I/Os

Pin/Ball Count

Supply Voltage

V = 3.3V

B = 2.5V

44 (1.0mm thickness)

48 (1.0mm thickness)

56

100

C = 1.8V

Speed

128

25 = 2.5ns

27 = 2.7ns

3 = 3.0ns

35 = 3.5ns

37 = 3.7ns

42 = 4.2ns

45 = 4.5ns

5 = 5.0ns

75 = 7.5ns

10 = 10.0ns

132

144

176

256

Package

T = TQFP

TN = Lead-free TQFP

FT = ftBGA FTN= Lead-free ftBGA

F = fpBGA²FN = Lead-free fpBGA²

M = csBGA MN = Lead-free csBGA

1. For automotive AEC-Q100 compliant devices, refer to the LA-ispMACH 4000V/Z Automotive Family Data Sheet (DS1017).

2. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000 Family Speed Grade Offering

-25

-27

-3

-35

-37

-42

-45

-5

-75

Ind

✔

-10

Ind

✔

Com Com Com Com Com Com Com Com

Ind

✔

Com

✔

Ext

1

ispMACH 4032V/B/C

ispMACH 4064V/B/C

ispMACH 4128V/B/C

ispMACH 4256V/B/C

ispMACH 4384V/B/C

ispMACH 4512V/B/C

ispMACH 4032ZC

ispMACH 4064ZC

ispMACH 4128ZC

ispMACH 4256ZC

1. 3.3V only.

✔

1

✔

1

✔

1

✔

1

✔

1

✔

73

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Ordering Information

Note: ispMACH 4000 devices are all dual marked except the slowest commercial speed grade ispMACH 4000Z

devices. For example, the commercial speed grade LC4128C-5T100C is also marked with the industrial grade -75I.

The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slow-

est commercial speed grade ispMACH 4000Z devices are marked as commercial grade only.

Conventional Packaging

ispMACH 4000ZC (Zero Power, 1.8V) Commercial Devices

Device

Part Number

LC4032ZC-35M56C

LC4032ZC-5M56C

LC4032ZC-75M56C

LC4032ZC-35T48C

LC4032ZC-5T48C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

64

32

96

64

128

96

64

Grade

C

PD

32

1.8

3.5

5

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

56

C

32

7.5

3.5

5

56

C

LC4032ZC

32

48

C

32

48

C

LC4032ZC-75T48C

LC4064ZC-37M132C

LC4064ZC-5M132C

LC4064ZC-75M132C

LC4064ZC-37T100C

LC4064ZC-5T100C

LC4064ZC-75T100C

LC4064ZC-37M56C

LC4064ZC-5M56C

LC4064ZC-75M56C

LC4064ZC-37T48C

LC4064ZC-5T48C

32

7.5

3.7

5

48

C

64

132

100

56

C

64

C

64

7.5

3.7

5

C

64

C

64

C

64

7.5

3.7

5

C

LC4064ZC

64

C

64

56

C

64

7.5

3.7

5

56

C

64

48

C

64

48

C

LC4064ZC-75T48C

LC4128ZC-42M132C

LC4128ZC-75M132C

LC4128ZC-42T100C

LC4128ZC-75T100C

LC4256ZC-45T176C

LC4256ZC-75T176C

LC4256ZC-45M132C

LC4256ZC-75M132C

LC4256ZC-45T100C

LC4256ZC-75T100C

64

7.5

4.2

7.5

4.2

7.5

4.5

7.5

4.5

7.5

4.5

7.5

48

C

128

256

132

100

176

132

100

C

LC4128ZC

LC4256ZC

C

ispMACH 4000ZC (1.8V, Zero Power) Industrial Devices

Device

Part Number

LC4032ZC-5M56I

LC4032ZC-75M56I

LC4032ZC-5T48I

LC4032ZC-75T48I

Macrocells Voltage tPD Package Pin/Ball Count

I/O

32

Grade

32

1.8

5

csBGA

TQFP

56

48

I

7.5

5

LC4032ZC

7.5

74

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000ZC (1.8V, Zero Power) Industrial Devices (Cont.)

Device

Part Number

LC4064ZC-5M132I

LC4064ZC-75M132I

LC4064ZC-5T100I

LC4064ZC-75T100I

LC4064ZC-5M56I

LC4064ZC-75M56I

LC4064ZC-5T48I

Macrocells Voltage tPD Package Pin/Ball Count

I/O

64

34

32

96

64

128

96

64

Grade

64

1.8

5

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

132

100

56

I

7.5

5

64

7.5

5

LC4064ZC

64

7.5

5

56

64

48

LC4064ZC-75T48I

LC4128ZC-75M132I

LC4128ZC-75T100I

LC4256ZC-75T176I

LC4256ZC-75M132I

LC4256ZC-75T100I

64

7.5

48

128

256

132

100

176

132

100

LC4128ZC

LC4256ZC

ispMACH 4000ZC (1.8V, Zero Power) Extended Temperature Devices

Family

Part Number

LC4032ZC-75T48E

LC4064ZC-75T100E

LC4064ZC-75T48E

LC4128ZC-75T100E

LC4256ZC-75T176E

LC4256ZC-75T100E

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

Grade

PD

LC4032ZC

32

64

1.8

7.5

TQFP

48

E

100

48

64

LC4064ZC

LC4128ZC

LC4256ZC

64

32

128

256

100

176

100

64

128

64

ispMACH 4000C (1.8V) Commercial Devices

Device

Part Number

LC4032C-25T48C

LC4032C-5T48C

LC4032C-75T48C

LC4032C-25T44C

LC4032C-5T44C

LC4032C-75T44C

LC4064C-25T100C

LC4064C-5T100C

LC4064C-75T100C

LC4064C-25T48C

LC4064C-5T48C

LC4064C-75T48C

LC4064C-25T44C

LC4064C-5T44C

LC4064C-75T44C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

Grade

C

PD

32

64

1.8

2.5

5

TQFP

48

C

7.5

2.5

5

48

C

LC4032C

44

C

44

C

7.5

2.5

5

44

C

100

48

C

7.5

2.5

5

C

LC4064C

48

C

7.5

2.5

5

48

C

44

C

44

C

7.5

44

C

75

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

92

Grade

C

PD

LC4128C-27T128C

LC4128C-5T128C

LC4128C-75T128C

LC4128C-27T100C

LC4128C-5T100C

LC4128C-75T100C

LC4256C-3FT256AC

LC4256C-5FT256AC

LC4256C-75FT256AC

LC4256C-3FT256BC

LC4256C-5FT256BC

LC4256C-75FT256BC

LC4256C-3F256AC¹

LC4256C-5F256AC¹

LC4256C-75F256AC¹

LC4256C-3F256BC¹

LC4256C-5F256BC¹

LC4256C-75F256BC¹

LC4256C-3T176C

LC4256C-5T176C

LC4256C-75T176C

LC4256C-3T100C

LC4256C-5T100C

LC4256C-75T100C

LC4384C-35FT256C

LC4384C-5FT256C

LC4384C-75FT256C

LC4384C-35F256C¹

LC4384C-5F256C¹

LC4384C-75F256C¹

LC4384C-35T176C

LC4384C-5T176C

LC4384C-75T176C

LC4512C-35FT256C

LC4512C-5FT256C

LC4512C-75FT256C

LC4512C-35F256C¹

LC4512C-5F256C¹

LC4512C-75F256C¹

LC4512C-35T176C

LC4512C-5T176C

LC4512C-75T176C

128

256

384

512

1.8

2.7

5

TQFP

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

128

100

256

176

100

256

176

256

176

92

7.5

2.7

5

92

LC4128C

64

7.5

3

64

128

160

128

160

128

64

5

7.5

3

5

7.5

3

5

7.5

3

LC4256C

5

7.5

3

5

7.5

3

5

64

7.5

3.5

5

64

192

128

208

128

7.5

3.5

5

LC4384C

7.5

3.5

5

7.5

3.5

5

7.5

3.5

5

LC4512C

7.5

3.5

5

7.5

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

76

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Industrial Devices

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

Grade

PD

LC4032C-5T48I

32

1.8

5

TQFP

ftBGA

fpBGA

TQFP

48

I

LC4032C-75T48I

LC4032C-10T48I

LC4032C-5T44I

7.5

10

5

32

48

32

LC4032C

32

44

30

LC4032C-75T44I

LC4032C-10T44I

LC4064C-5T100I

LC4064C-75T100I

LC4064C-10T100I

LC4064C-5T48I

32

7.5

10

5

44

30

32

44

30

64

100

48

64

7.5

10

5

64

32

LC4064C

LC4064C-75T48I

LC4064C-10T48I

LC4064C-5T44I

64

7.5

10

5

48

32

64

48

32

64

44

30

LC4064C-75T44I

LC4064C-10T44I

LC4128C-5T128I

LC4128C-75T128I

LC4128C-10T128I

LC4128C-5T100I

LC4128C-75T100I

LC4128C-10T100I

LC4256C-5FT256AI

LC4256C-75FT256AI

LC4256C-10FT256AI

LC4256C-5FT256BI

LC4256C-75FT256BI

LC4256C-10FT256BI

LC4256C-5F256AI¹

LC4256C-75F256AI¹

LC4256C-10F256AI¹

LC4256C-5F256BI¹

LC4256C-75F256BI¹

LC4256C-10F256BI¹

LC4256C-5T176I

LC4256C-75T176I

LC4256C-10T176I

LC4256C-5T100I

LC4256C-75T100I

LC4256C-10T100I

64

7.5

10

5

44

30

64

44

30

128

256

128

100

256

176

100

92

7.5

10

5

92

LC4128C

64

7.5

10

5

64

128

160

128

160

128

64

7.5

10

5

7.5

10

5

7.5

10

5

LC4256C

7.5

10

5

7.5

10

5

7.5

10

64

77

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

Grade

PD

LC4384C-5FT256I

LC4384C-75FT256I

LC4384C-10FT256I

LC4384C-5F256I¹

LC4384C-75F256I¹

LC4384C-10F256I¹

LC4384C-5T176I

LC4384C-75T176I

LC4384C-10T176I

LC4512C-5FT256I

LC4512C-75FT256I

LC4512C-10FT256I

LC4512C-5F256I¹

LC4512C-75F256I¹

LC4512C-10F256I¹

LC4512C-5T176I

LC4512C-75T176I

LC4512C-10T176I

384

512

1.8

5

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

256

176

256

176

192

128

208

128

I

7.5

10

5

LC4384C

7.5

10

5

7.5

10

5

7.5

10

5

LC4512C

7.5

10

5

7.5

10

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000B (2.5V) Commercial Devices

Device

Part Number

LC4032B-25T48C

LC4032B-5T48C

LC4032B-75T48C

LC4032B-25T44C

LC4032B-5T44C

LC4032B-75T44C

LC4064B-25T100C

LC4064B-5T100C

LC4064B-75T100C

LC4064B-25T48C

LC4064B-5T48C

LC4064B-75T48C

LC4064B-25T44C

LC4064B-5T44C

LC4064B-75T44C

LC4128B-27T128C

LC4128B-5T128C

LC4128B-75T128C

LC4128B-27T100C

LC4128B-5T100C

LC4128B-75T100C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

92

64

Grade

C

PD

32

2.5

5

TQFP

48

C

32

7.5

2.5

5

48

C

LC4032B

32

44

C

32

44

C

32

7.5

2.5

5

44

C

64

100

48

C

64

C

64

7.5

2.5

5

C

64

C

LC4064B

64

48

C

64

7.5

2.5

5

48

C

64

44

C

64

44

C

64

7.5

2.7

5

44

C

128

100

C

7.5

2.7

5

C

LC4128B

C

7.5

C

78

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

128

160

128

160

128

64

Grade

C

PD

LC4256B-3FT256AC

LC4256B-5FT256AC

LC4256B-75FT256AC

LC4256B-3FT256BC

LC4256B-5FT256BC

LC4256B-75FT256BC

LC4256B-3F256AC¹

LC4256B-5F256AC¹

LC4256B-75F256AC¹

LC4256B-3F256BC¹

LC4256B-5F256BC¹

LC4256B-75F256BC¹

LC4256B-3T176C

256

384

512

2.5

3

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

256

176

100

256

176

256

176

5

7.5

3

5

7.5

3

5

7.5

3

LC4256B

5

7.5

3

LC4256B-5T176C

5

LC4256B-75T176C

LC4256B-3T100C

7.5

3

LC4256B-5T100C

5

64

LC4256B-75T100C

LC4384B-35FT256C

LC4384B-5FT256C

LC4384B-75FT256C

LC4384B-35F256C¹

LC4384B-5F256C¹

LC4384B-75F256C¹

LC4384B-35T176C

LC4384B-5T176C

7.5

3.5

5

64

192

128

208

128

7.5

3.5

5

LC4384B

7.5

3.5

5

LC4384B-75T176C

LC4512B-35FT256C

LC4512B-5FT256C

LC4512B-75FT256C

LC4512B-35F256C¹

LC4512B-5F256C¹

LC4512B-75F256C¹

LC4512B-35T176C

LC4512B-5T176C

7.5

3.5

5

7.5

3.5

5

LC4512B

7.5

3.5

5

LC4512B-75T176C

7.5

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

79

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Industrial Devices

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

Grade

PD

LC4032B-5T48I

32

2.5

5

TQFP

ftBGA

fpBGA

TQFP

48

I

LC4032B-75T48I

LC4032B-10T48I

LC4032B-5T44I

7.5

10

5

32

48

32

LC4032B

32

44

30

LC4032B-75T44I

LC4032B-10T44I

LC4064B-5T100I

LC4064B-75T100I

LC4064B-10T100I

LC4064B-5T48I

32

7.5

10

5

44

30

32

44

30

64

100

48

64

7.5

10

5

64

32

LC4064B

LC4064B-75T48I

LC4064B-10T48I

LC4064B-5T44I

64

7.5

10

5

48

32

64

48

32

64

44

30

LC4064B-75T44I

LC4064B-10T44I

LC4128B-5T128I

LC4128B-75T128I

LC4128B-10T128I

LC4128B-5T100I

LC4128B-75T100I

LC4128B-10T100I

LC4256B-5FT256AI

LC4256B-75FT256AI

LC4256B-10FT256AI

LC4256B-5FT256BI

LC4256B-75FT256BI

LC4256B-10FT256BI

LC4256B-5F256AI¹

LC4256B-75F256AI¹

LC4256B-10F256AI¹

LC4256B-5F256BI¹

LC4256B-75F256BI¹

LC4256B-10F256BI¹

LC4256B-5T176I

LC4256B-75T176I

LC4256B-10T176I

LC4256B-5T100I

LC4256B-75T100I

LC4256B-10T100I

64

7.5

10

5

44

30

64

44

30

128

256

128

100

256

176

100

92

7.5

10

5

92

LC4128B

64

7.5

10

5

64

128

160

128

160

128

64

7.5

10

5

7.5

10

5

7.5

10

5

LC4256B

7.5

10

5

7.5

10

5

7.5

10

64

80

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

Grade

PD

LC4384B-5FT256I

LC4384B-75FT256I

LC4384B-10FT256I

LC4384B-5F256I¹

LC4384B-75F256I¹

LC4384B-10F256I¹

LC4384B-5T176I

LC4384B-75T176I

LC4384B-10T176I

LC4512B-5FT256I

LC4512B-75FT256I

LC4512B-10FT256I

LC4512B-5F256I¹

LC4512B-75F256I¹

LC4512B-10F256I¹

LC4512B-5T176I

LC4512B-75T176I

LC4512B-10T176I

384

512

2.5

5

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

256

176

256

176

192

128

208

128

I

7.5

10

5

LC4384B

7.5

10

5

7.5

10

5

7.5

10

5

LC4512B

7.5

10

5

7.5

10

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000V (3.3V) Commercial Devices

Device

Part Number

LC4032V-25T48C

LC4032V-5T48C

LC4032V-75T48C

LC4032V-25T44C

LC4032V-5T44C

LC4032V-75T44C

LC4064V-25T100C

LC4064V-5T100C

LC4064V-75T100C

LC4064V-25T48C

LC4064V-5T48C

LC4064V-75T48C

LC4064V-25T44C

LC4064V-5T44C

LC4064V-75T44C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

Grade

C

PD

32

64

3.3

2.5

5

TQFP

48

C

7.5

2.5

5

48

C

LC4032V

44

C

44

C

7.5

2.5

5

44

C

100

48

C

7.5

2.5

5

C

LC4064V

48

C

7.5

2.5

5

48

C

44

C

44

C

7.5

44

C

81

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

96

Grade

C

PD

LC4128V-27T144C

LC4128V-5T144C

LC4128V-75T144C

LC4128V-27T128C

LC4128V-5T128C

LC4128V-75T128C

LC4128V-27T100C

LC4128V-5T100C

LC4128V-75T100C

LC4256V-3FT256AC

LC4256V-5FT256AC

LC4256V-75FT256AC

LC4256V-3FT256BC

LC4256V-5FT256BC

LC4256V-75FT256BC

LC4256V-3F256AC¹

LC4256V-5F256AC¹

LC4256V-75F256AC¹

LC4256V-3F256BC¹

LC4256V-5F256BC¹

LC4256V-75F256BC¹

LC4256V-3T176C

LC4256V-5T176C

LC4256V-75T176C

LC4256V-3T144C

LC4256V-5T144C

LC4256V-75T144C

LC4256V-3T100C

LC4256V-5T100C

LC4256V-75T100C

LC4384V-35FT256C

LC4384V-5FT256C

LC4384V-75FT256C

LC4384V-35F256C¹

LC4384V-5F256C¹

LC4384V-75F256C¹

LC4384V-35T176C

LC4384V-5T176C

LC4384V-75T176C

128

256

384

3.3

2.7

5

TQFP

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

144

128

100

256

176

144

100

256

176

96

7.5

2.7

5

96

92

LC4128V

92

7.5

2.7

5

92

64

7.5

3

64

128

160

128

160

128

96

5

7.5

3

5

7.5

3

5

7.5

3

LC4256V

5

7.5

3

5

7.5

3

5

96

7.5

3

96

64

5

64

7.5

3.5

5

64

192

128

7.5

3.5

5

LC4384V

7.5

3.5

5

7.5

82

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

208

128

Grade

PD

LC4512V-35FT256C

LC4512V-5FT256C

LC4512V-75FT256C

LC4512V-35F256C¹

LC4512V-5F256C¹

LC4512V-75F256C¹

LC4512V-35T176C

LC4512V-5T176C

LC4512V-75T176C

512

3.3

3.5

5

ftBGA

fpBGA

TQFP

256

176

C

7.5

3.5

5

LC4512V

7.5

3.5

5

7.5

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000V (3.3V) Industrial Devices

Family

Part Number

LC4032V-5T48I

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

96

92

64

Grade

PD

32

3.3

5

TQFP

48

I

LC4032V-75T48I

LC4032V-10T48I

LC4032V-5T44I

LC4032V-75T44I

LC4032V-10T44I

LC4064V-5T100I

LC4064V-75T100I

LC4064V-10T100I

LC4064V-5T48I

LC4064V-75T48I

LC4064V-10T48I

LC4064V-5T44I

LC4064V-75T44I

LC4064V-10T44I

LC4128V-5T144I

LC4128V-75T144I

LC4128V-10T144I

LC4128V-5T128I

LC4128V-75T128I

LC4128V-10T128I

LC4128V-5T100I

LC4128V-75T100I

LC4128V-10T100I

7.5

10

5

32

48

LC4032V

32

44

32

7.5

10

5

44

32

44

64

100

48

64

7.5

10

5

64

LC4064V

64

7.5

10

5

48

64

48

64

44

64

7.5

10

5

44

64

44

128

144

128

100

7.5

10

5

LC4128V

7.5

10

5

7.5

10

83

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

128

160

128

160

128

96

Grade

PD

LC4256V-5FT256AI

LC4256V-75FT256AI

LC4256V-10FT256AI

LC4256V-5FT256BI

LC4256V-75FT256BI

LC4256V-10FT256BI

LC4256V-5F256AI¹

LC4256V-75F256AI¹

LC4256V-10F256AI¹

LC4256V-5F256BI¹

LC4256V-75F256BI¹

LC4256V-10F256BI¹

LC4256V-5T176I

256

384

512

3.3

5

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

ftBGA

fpBGA

TQFP

256

176

144

100

256

176

256

176

I

7.5

10

5

7.5

10

5

7.5

10

5

LC4256V

7.5

10

5

LC4256V-75T176I

LC4256V-10T176I

LC4256V-5T144I

7.5

10

5

LC4256V-75T144I

LC4256V-10T144I

LC4256V-5T100I

7.5

10

5

96

64

LC4256V-75T100I

LC4256V-10T100I

LC4384V-5FT256I

LC4384V-75FT256I

LC4384V-10FT256I

LC4384V-5F256I¹

LC4384V-75F256I¹

LC4384V-10F256I¹

LC4384V-5T176I

7.5

10

5

64

192

128

208

128

7.5

10

5

LC4384V

7.5

10

5

LC4384V-75T176I

LC4384V-10T176I

LC4512V-5FT256I

LC4512V-75FT256I

LC4512V-10FT256I

LC4512V-5F256I¹

LC4512V-75F256I¹

LC4512V-10F256I¹

LC4512V-5T176I

7.5

10

5

7.5

10

5

LC4512V

7.5

10

5

LC4512V-75T176I

LC4512V-10T176I

7.5

10

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

84

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Extended Temperature Devices

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

96

92

64

128

96

64

Grade

PD

LC4032V-75T48E

LC4032V-75T44E

LC4064V-75T100E

LC4064V-75T48E

LC4064V-75T44E

LC4128V-75T144E

LC4128V-75T128E

LC4128V-75T100E

LC4256V-75T176E

LC4256V-75T144E

LC4256V-75T100E

32

3.3

7.5

TQFP

48

44

E

LC4032V

64

100

48

LC4064V

LC4128V

LC4256V

64

44

128

256

144

128

100

176

144

100

85

Lattice Semiconductor

Lead-Free Packaging

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

3.5 Lead-free csBGA

Lead-free csBGA

I/O

32

64

32

96

64

128

96

64

Grade

C

PD

LC4032ZC-35MN56C

LC4032ZC-5MN56C

LC4032ZC-75MN56C

LC4032ZC-35TN48C

LC4032ZC-5TN48C

LC4032ZC-75TN48C

LC4064ZC-37MN132C

LC4064ZC-5MN132C

LC4064ZC-75MN132C

LC4064ZC-37TN100C

LC4064ZC-5TN100C

LC4064ZC-75TN100C

LC4064ZC-37MN56C

LC4064ZC-5MN56C

LC4064ZC-75MN56C

LC4064ZC-37TN48C

LC4064ZC-5TN48C

LC4064ZC-75TN48C

LC4128ZC-42MN132C

LC4128ZC-75MN132C

LC4128ZC-42TN100C

LC4128ZC-75TN100C

LC4256ZC-45TN176C

LC4256ZC-75TN176C

LC4256ZC-45MN132C

LC4256ZC-75MN132C

LC4256ZC-45TN100C

LC4256ZC-75TN100C

32

1.8

56

5

C

32

7.5 Lead-free csBGA

3.5 Lead-free TQFP

56

C

LC4032ZC

32

48

C

32

5

Lead-free TQFP

48

C

32

7.5 Lead-free TQFP

3.7 Lead-free csBGA

48

C

64

132

100

56

C

64

5

Lead-free csBGA

C

64

7.5 Lead-free csBGA

3.7 Lead-free TQFP

C

64

C

64

5

Lead-free TQFP

C

64

7.5 Lead-free TQFP

3.7 Lead-free csBGA

C

LC4064ZC

64

C

64

5

Lead-free csBGA

56

C

64

7.5 Lead-free csBGA

3.7 Lead-free TQFP

56

C

64

48

C

64

5

Lead-free TQFP

48

C

64

7.5 Lead-free TQFP

4.2 Lead-free csBGA

7.5 Lead-free csBGA

4.2 Lead-free TQFP

7.5 Lead-free TQFP

4.5 Lead-free TQFP

7.5 Lead-free TQFP

4.5 Lead-free csBGA

7.5 Lead-free csBGA

4.5 Lead-free TQFP

7.5 Lead-free TQFP

48

C

128

256

132

100

176

132

100

C

LC4128ZC

LC4256ZC

C

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Industrial Devices

Pin/Ball

Device

Part Number

LC4032ZC-5MN56I

LC4032ZC-75MN56I

LC4032ZC-5TN48I

LC4032ZC-75TN48I

Macrocells Voltage

t

Package

Count

I/O

32

Grade

PD

32

1.8

5

Lead-free csBGA

56

I

7.5 Lead-free csBGA

Lead-free TQFP

7.5 Lead-free TQFP

56

LC4032ZC

5

48

86

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

64

32

96

64

128

96

64

Grade

PD

LC4064ZC-5MN132I

LC4064ZC-75MN132I

LC4064ZC-5TN100I

LC4064ZC-75TN100I

LC4064ZC-5MN56I

LC4064ZC-75MN56I

LC4064ZC-5TN48I

64

1.8

5

Lead-free csBGA

132

100

56

I

7.5 Lead-free csBGA

Lead-free TQFP

7.5 Lead-free TQFP

Lead-free csBGA

7.5 Lead-free csBGA

Lead-free TQFP

64

5

64

LC4064ZC

64

5

64

56

64

5

48

LC4064ZC-75TN48I

LC4128ZC-75MN132I

LC4128ZC-75TN100I

LC4256ZC-75TN176I

LC4256ZC-75MN132I

LC4256ZC-75TN100I

64

7.5 Lead-free TQFP

7.5 Lead-free csBGA

7.5 Lead-free TQFP

7.5 Lead-free csBGA

7.5 Lead-free TQFP

48

128

256

132

100

176

132

100

LC4128ZC

LC4256ZC

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Extended Temperature Devices

Pin/Ball

Device

Part Number

LC4032ZC-75TN48E

LC4064ZC-75TN100E

LC4064ZC-75TN48E

LC4128ZC-75TN100E

LC4256ZC-75TN176E

LC4256ZC-75TN100E

Macrocells Voltage

t

Package

Count

I/O

32

Grade

PD

LC4032ZC

32

64

1.8

7.5 Lead-free TQFP

48

E

100

48

64

LC4064ZC

LC4128ZC

LC4256ZC

64

32

128

256

100

176

100

64

128

64

ispMACH 4000C (1.8V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

LC4032C-25TN48C

LC4032C-5TN48C

LC4032C-75TN48C

LC4032C-25TN44C

LC4032C-5TN44C

LC4032C-75TN44C

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

I/O

32

30

Grade

PD

32

1.8

48

44

C

5

7.5 Lead-free TQFP

2.5 Lead-free TQFP

LC4032C

5

Lead-free TQFP

7.5 Lead-free TQFP

87

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

I/O

64

Grade

C

PD

LC4064C-25TN100C

LC4064C-5TN100C

LC4064C-75TN100C

LC4064C-25TN48C

LC4064C-5TN48C

64

1.8

100

48

64

5

64

7.5 Lead-free TQFP

2.5 Lead-free TQFP

64

32

LC4064C

64

5

Lead-free TQFP

48

32

LC4064C-75TN48C

LC4064C-25TN44C

LC4064C-5TN44C

64

7.5 Lead-free TQFP

2.5 Lead-free TQFP

48

32

64

44

30

64

5

Lead-free TQFP

44

30

LC4064C-75TN44C

LC4128C-27TN128C

LC4128C-5TN128C

LC4128C-75TN128C

LC4128C-27TN100C

LC4128C-5TN100C

LC4128C-75TN100C

LC4256C-3FTN256AC

LC4256C-5FTN256AC

LC4256C-75FTN256AC

LC4256C-3FTN256BC

LC4256C-5FTN256BC

LC4256C-75FTN256BC

LC4256C-3FN256AC¹

LC4256C-5FN256AC¹

LC4256C-75FN256AC¹

LC4256C-3FN256BC¹

LC4256C-5FN256BC¹

LC4256C-75FN256BC¹

LC4256C-3TN176C

LC4256C-5TN176C

LC4256C-75TN176C

LC4256C-3TN100C

LC4256C-5TN100C

LC4256C-75TN100C

LC4384C-35FTN256C

LC4384C-5FTN256C

LC4384C-75FTN256C

LC4384C-35FN256C¹

LC4384C-5FN256C¹

LC4384C-75FN256C¹

LC4384C-35TN176C

LC4384C-5TN176C

LC4384C-75TN176C

64

7.5 Lead-free TQFP

2.7 Lead-free TQFP

44

30

128

256

384

128

100

256

176

100

256

176

92

5

Lead-free TQFP

92

7.5 Lead-free TQFP

2.7 Lead-free TQFP

92

LC4128C

64

5

Lead-free TQFP

64

7.5 Lead-free TQFP

64

3

5

Lead-free ftBGA

128

160

128

160

128

64

7.5 Lead-free ftBGA

3

5

Lead-free ftBGA

7.5 Lead-free ftBGA

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

LC4256C

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3

5

Lead-free TQFP

7.5 Lead-free TQFP

3

5

Lead-free TQFP

64

7.5 Lead-free TQFP

3.5 Lead-free ftBGA

64

192

128

5

Lead-free ftBGA

7.5 Lead-free ftBGA

3.5 Lead-free fpBGA

LC4384C

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

88

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

3.5 Lead-free ftBGA

Lead-free ftBGA

I/O

Grade

PD

LC4512C-35FTN256C

LC4512C-5FTN256C

LC4512C-75FTN256C

LC4512C-35FN256C¹

LC4512C-5FN256C¹

LC4512C-75FN256C¹

LC4512C-35TN176C

LC4512C-5TN176C

LC4512C-75TN176C

512

1.8

256

176

208

128

C

5

7.5 Lead-free ftBGA

3.5 Lead-free fpBGA

LC4512C

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000C (1.8V) Lead-Free Industrial Devices

Pin/Ball

Count

Device

Part Number

LC4032C-5TN48I

LC4032C-75TN48I

LC4032C-10TN48I

LC4032C-5TN44I

LC4032C-75TN44I

LC4032C-10TN44I

LC4064C-5TN100I

LC4064C-75TN100I

LC4064C-10TN100I

LC4064C-5TN48I

LC4064C-75TN48I

LC4064C-10TN48I

LC4064C-5TN44I

LC4064C-75TN44I

LC4064C-10TN44I

LC4128C-5TN128I

LC4128C-75TN128I

LC4128C-10TN128I

LC4128C-5TN100I

LC4128C-75TN100I

LC4128C-10TN100I

Macrocells Voltage

t

Package

I/O

32

30

64

32

30

92

64

Grade

PD

32

1.8

5

Lead-free TQFP

48

I

7.5 Lead-free TQFP

10 Lead-free TQFP

32

48

LC4032C

32

5

Lead-free TQFP

44

32

7.5 Lead-free TQFP

10 Lead-free TQFP

44

32

44

64

5

Lead-free TQFP

100

48

64

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free TQFP

LC4064C

64

7.5 Lead-free TQFP

10 Lead-free TQFP

48

64

48

64

5

Lead-free TQFP

44

64

44

64

10 Lead-free TQFP

Lead-free TQFP

44

128

5

128

100

7.5 Lead-free TQFP

10 Lead-free TQFP

LC4128C

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

89

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

128

160

128

160

128

64

Grade

PD

LC4256C-5FTN256AI

LC4256C-75FTN256AI

LC4256C-10FTN256AI

LC4256C-5FTN256BI

LC4256C-75FTN256BI

LC4256C-10FTN256BI

LC4256C-5FN256AI¹

LC4256C-75FN256AI¹

LC4256C-10FN256AI¹

LC4256C-5FN256BI¹

LC4256C-75FN256BI¹

LC4256C-10FN256BI¹

LC4256C-5TN176I

256

384

512

1.8

5

Lead-free ftBGA

256

176

100

256

176

256

176

I

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free ftBGA

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4256C

5

Lead-free fpBGA

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4256C-75TN176I

LC4256C-10TN176I

LC4256C-5TN100I

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4256C-75TN100I

LC4256C-10TN100I

LC4384C-5FTN256I

LC4384C-75FTN256I

LC4384C-10FTN256I

LC4384C-5FN256I¹

LC4384C-75FN256I¹

LC4384C-10FN256I¹

LC4384C-5TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free ftBGA

192

128

208

128

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

LC4384C

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4384C-75TN176I

LC4384C-10TN176I

LC4512C-5FTN256I

LC4512C-75FTN256I

LC4512C-10FTN256I

LC4512C-5FN256I¹

LC4512C-75FN256I¹

LC4512C-10FN256I¹

LC4512C-5TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free ftBGA

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

LC4512C

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4512C-75TN176I

LC4512C-10TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

90

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

2.5 Lead-Free TQFP

Lead-Free TQFP

I/O

32

Grade

C

PD

LC4032B-25TN48C

LC4032B-5TN48C

32

2.5

48

5

32

LC4032B-75TN48C

LC4032B-25TN44C

LC4032B-5TN44C

32

7.5 Lead-Free TQFP

2.5 Lead-Free TQFP

48

32

LC4032B

32

44

30

32

5

Lead-Free TQFP

44

30

LC4032B-75TN44C

LC4064B-25TN100C

LC4064B-5TN100C

LC4064B-75TN100C

LC4064B-25TN48C

LC4064B-5TN48C

32

7.5 Lead-Free TQFP

2.5 Lead-Free TQFP

44

30

64

100

48

64

5

Lead-Free TQFP

64

7.5 Lead-Free TQFP

2.5 Lead-Free TQFP

64

32

LC4064B

64

5

Lead-Free TQFP

48

32

LC4064B-75TN48C

LC4064B-25TN44C

LC4064B-5TN44C

64

7.5 Lead-Free TQFP

2.5 Lead-Free TQFP

48

32

64

44

30

64

5

Lead-Free TQFP

44

30

LC4064B-75TN44C

LC4128B-27TN128C

LC4128B-5TN128C

LC4128B-75TN128C

LC4128B-27TN100C

LC4128B-5TN100C

LC4128B-75TN100C

LC4256B-3FTN256AC

LC4256B-5FTN256AC

LC4256B-75FTN256AC

LC4256B-3FTN256BC

LC4256B-5FTN256BC

LC4256B-75FTN256BC

LC4256B-3FN256AC¹

LC4256B-5FN256AC¹

LC4256B-75FN256AC¹

LC4256B-3FN256BC¹

LC4256B-5FN256BC¹

LC4256B-75FN256BC¹

LC4256B-3TN176C

LC4256B-5TN176C

LC4256B-75TN176C

LC4256B-3TN100C

LC4256B-5TN100C

LC4256B-75TN100C

64

7.5 Lead-Free TQFP

2.7 Lead-Free TQFP

44

30

128

256

128

100

256

176

100

92

5

Lead-Free TQFP

92

7.5 Lead-Free TQFP

2.7 Lead-Free TQFP

92

LC4128B

92

5

Lead-Free TQFP

92

7.5 Lead-Free TQFP

92

3

5

Lead-Free ftBGA

128

160

128

160

128

64

7.5 Lead-Free ftBGA

3

5

Lead-Free ftBGA

7.5 Lead-Free ftBGA

3

5

Lead-Free fpBGA

7.5 Lead-Free fpBGA

LC4256B

3

5

Lead-Free fpBGA

7.5 Lead-Free fpBGA

3

5

Lead-Free TQFP

7.5 Lead-Free TQFP

3

5

Lead-Free TQFP

64

7.5 Lead-Free TQFP

64

91

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

3.5 Lead-Free ftBGA

Lead-Free ftBGA

I/O

Grade

C

PD

LC4384B-35FTN256C

LC4384B-5FTN256C

LC4384B-75FTN256C

LC4384B-35FN256C¹

LC4384B-5FN256C¹

LC4384B-75FN256C¹

LC4384B-35TN176C

LC4384B-5TN176C

LC4384B-75TN176C

LC4512B-35FTN256C

LC4512B-5FTN256C

LC4512B-75FTN256C

LC4512B-35FN256C¹

LC4512B-5FN256C¹

LC4512B-75FN256C¹

LC4512B-35TN176C

LC4512B-5TN176C

LC4512B-75TN176C

384

512

2.5

256

176

256

176

192

128

208

128

5

C

7.5 Lead-Free ftBGA

3.5 Lead-Free fpBGA

C

LC4384B

5

Lead-Free fpBGA

C

7.5 Lead-Free fpBGA

3.5 Lead-Free TQFP

C

5

Lead-Free TQFP

C

7.5 Lead-Free TQFP

3.5 Lead-Free ftBGA

C

5

Lead-Free ftBGA

C

7.5 Lead-Free ftBGA

3.5 Lead-Free fpBGA

C

LC4512B

5

Lead-Free fpBGA

C

7.5 Lead-Free fpBGA

3.5 Lead-Free TQFP

C

5

Lead-Free TQFP

C

7.5 Lead-Free TQFP

C

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

ispMACH 4000B (2.5V) Lead-Free Industrial Devices

Pin/Ball

Count

Device

Part Number

LC4032B-5TN48I

LC4032B-75TN48I

LC4032B-10TN48I

LC4032B-5TN44I

LC4032B-75TN44I

LC4032B-10TN44I

LC4064B-5TN100I

LC4064B-75TN100I

LC4064B-10TN100I

LC4064B-5TN48I

LC4064B-75TN48I

LC4064B-10TN48I

LC4064B-5TN44I

LC4064B-75TN44I

LC4064B-10TN44I

Macrocells Voltage

t

Package

I/O

32

30

64

32

30

Grade

PD

32

64

2.5

5

Lead-Free TQFP

48

I

7.5 Lead-Free TQFP

10 Lead-Free TQFP

48

LC4032B

5

Lead-Free TQFP

44

7.5 Lead-Free TQFP

10 Lead-Free TQFP

44

5

Lead-Free TQFP

100

48

7.5 Lead-Free TQFP

10 Lead-Free TQFP

5

Lead-Free TQFP

LC4064B

7.5 Lead-Free TQFP

10 Lead-Free TQFP

48

5

Lead-Free TQFP

44

7.5 Lead-Free TQFP

10 Lead-Free TQFP

44

92

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

92

Grade

PD

LC4128B-5TN128I

LC4128B-75TN128I

LC4128B-10TN128I

LC4128B-5TN100I

LC4128B-75TN100I

LC4128B-10TN100I

LC4256B-5FTN256AI

LC4256B-75FTN256AI

LC4256B-10FTN256AI

LC4256B-5FTN256BI

LC4256B-75FTN256BI

LC4256B-10FTN256BI

LC4256B-5FN256AI¹

LC4256B-75FN256AI¹

LC4256B-10FN256AI¹

LC4256B-5FN256BI¹

LC4256B-75FN256BI¹

LC4256B-10FN256BI¹

LC4256B-5TN176I

LC4256B-75TN176I

LC4256B-10TN176I

LC4256B-5TN100I

LC4256B-75TN100I

LC4256B-10TN100I

LC4384B-5FTN256I

LC4384B-75FTN256I

LC4384B-10FTN256I

LC4384B-5FN256I¹

LC4384B-75FN256I¹

LC4384B-10FN256I¹

LC4384B-5TN176I

LC4384B-75TN176I

LC4384B-10TN176I

LC4512B-5FTN256I

LC4512B-75FTN256I

LC4512B-10FTN256I

LC4512B-5FN256I¹

LC4512B-75FN256I¹

LC4512B-10FN256I¹

LC4512B-5TN176I

LC4512B-75TN176I

LC4512B-10TN176I

128

256

384

512

2.5

5

Lead-Free TQFP

128

100

256

176

100

256

176

256

176

I

7.5 Lead-Free TQFP

10 Lead-Free TQFP

92

LC4128B

5

Lead-Free TQFP

64

7.5 Lead-Free TQFP

10 Lead-Free TQFP

64

5

Lead-Free ftBGA

128

160

128

160

128

64

7.5 Lead-Free ftBGA

10 Lead-Free ftBGA

5

Lead-Free ftBGA

7.5 Lead-Free ftBGA

10 Lead-Free ftBGA

5

Lead-Free fpBGA

7.5 Lead-Free fpBGA

10 Lead-Free fpBGA

LC4256B

5

Lead-Free fpBGA

7.5 Lead-Free fpBGA

10 Lead-Free fpBGA

5

Lead-Free TQFP

7.5 Lead-Free TQFP

10 Lead-Free TQFP

5

Lead-Free TQFP

7.5 Lead-Free TQFP

10 Lead-Free TQFP

64

5

Lead-Free ftBGA

192

128

208

128

7.5 Lead-Free ftBGA

10 Lead-Free ftBGA

5

Lead-Free fpBGA

LC4384B

7.5 Lead-Free fpBGA

10 Lead-Free fpBGA

5

Lead-Free TQFP

7.5 Lead-Free TQFP

10 Lead-Free TQFP

5

Lead-Free ftBGA

7.5 Lead-Free ftBGA

10 Lead-Free ftBGA

5

Lead-Free fpBGA

LC4512B

7.5 Lead-Free fpBGA

10 Lead-Free fpBGA

5

Lead-Free TQFP

7.5 Lead-Free TQFP

10 Lead-Free TQFP

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

93

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

I/O

32

30

64

32

30

96

92

64

Grade

C

PD

LC4032V-25TN48C

LC4032V-5TN48C

LC4032V-75TN48C

LC4032V-25TN44C

LC4032V-5TN44C

LC4032V-75TN44C

LC4064V-25TN100C

LC4064V-5TN100C

LC4064V-75TN100C

LC4064V-25TN48C

LC4064V-5TN48C

LC4064V-75TN48C

LC4064V-25TN44C

LC4064V-5TN44C

LC4064V-75TN44C

LC4128V-27TN144C

LC4128V-5TN144C

LC4128V-75TN144C

LC4128V-27TN128C

LC4128V-5TN128C

LC4128V-75TN128C

LC4128V-27TN100C

LC4128V-5TN100C

LC4128V-75TN100C

32

3.3

48

5

C

32

7.5 Lead-free TQFP

2.5 Lead-free TQFP

48

C

LC4032V

32

44

C

32

5

Lead-free TQFP

44

C

32

7.5 Lead-free TQFP

2.5 Lead-free TQFP

44

C

64

100

48

C

64

5

Lead-free TQFP

C

64

7.5 Lead-free TQFP

2.5 Lead-free TQFP

C

64

C

LC4064V

64

5

Lead-free TQFP

48

C

64

7.5 Lead-free TQFP

2.5 Lead-free TQFP

48

C

64

44

C

64

5

Lead-free TQFP

44

C

64

7.5 Lead-free TQFP

2.7 Lead-free TQFP

44

C

128

144

128

100

C

5

Lead-free TQFP

C

7.5 Lead-free TQFP

2.7 Lead-free TQFP

C

LC4128V

5

Lead-free TQFP

C

7.5 Lead-free TQFP

2.7 Lead-free TQFP

C

5

Lead-free TQFP

C

7.5 Lead-free TQFP

C

94

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

128

160

128

160

128

96

Grade

C

PD

LC4256V-3FTN256AC

LC4256V-5FTN256AC

LC4256V-75FTN256AC

LC4256V-3FTN256BC

LC4256V-5FTN256BC

LC4256V-75FTN256BC

LC4256V-3FN256AC¹

LC4256V-5FN256AC¹

LC4256V-75FN256AC¹

LC4256V-3FN256BC¹

LC4256V-5FN256BC¹

LC4256V-75FN256BC¹

LC4256V-3TN176C

LC4256V-5TN176C

LC4256V-75TN176C

LC4256V-3TN144C

LC4256V-5TN144C

LC4256V-75TN144C

LC4256V-3TN100C

LC4256V-5TN100C

LC4256V-75TN100C

LC4384V-35FTN256C

LC4384V-5FTN256C

LC4384V-75FTN256C

LC4384V-35FN256C¹

LC4384V-5FN256C¹

LC4384V-75FN256C¹

LC4384V-35TN176C

LC4384V-5TN176C

LC4384V-75TN176C

LC4512V-35FTN256C

LC4512V-5FTN256C

LC4512V-75FTN256C

LC4512V-35FN256C¹

LC4512V-5FN256C¹

LC4512V-75FN256C¹

LC4512V-35TN176C

LC4512V-5TN176C

LC4512V-75TN176C

256

384

512

3.3

3

Lead-free ftBGA

256

176

144

100

256

176

256

176

5

7.5 Lead-free ftBGA

3

5

Lead-free ftBGA

7.5 Lead-free ftBGA

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3

5

Lead-free fpBGA

LC4256V

7.5 Lead-free fpBGA

3

5

Lead-free TQFP

7.5 Lead-free TQFP

3

5

Lead-free TQFP

96

7.5 Lead-free TQFP

96

3

5

Lead-free TQFP

64

7.5 Lead-free TQFP

3.5 Lead-free ftBGA

64

192

128

208

128

5

Lead-free ftBGA

7.5 Lead-free ftBGA

3.5 Lead-free fpBGA

LC4384V

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

3.5 Lead-free ftBGA

5

Lead-free ftBGA

7.5 Lead-free ftBGA

3.5 Lead-free fpBGA

LC4512V

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

95

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Lead-Free Industrial Devices

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

32

30

64

32

30

96

92

64

Grade

PD

LC4032V-5TN48I

LC4032V-75TN48I

LC4032V-10TN48I

LC4032V-5TN44I

LC4032V-75TN44I

LC4032V-10TN44I

LC4064V-5TN100I

LC4064V-75TN100I

LC4064V-10TN100I

LC4064V-5TN48I

LC4064V-75TN48I

LC4064V-10TN48I

LC4064V-5TN44I

LC4064V-75TN44I

LC4064V-10TN44I

LC4128V-5TN144I

LC4128V-75TN144I

LC4128V-10TN144I

LC4128V-5TN128I

LC4128V-75TN128I

LC4128V-10TN128I

LC4128V-5TN100I

LC4128V-75TN100I

LC4128V-10TN100I

32

3.3

5

Lead-free TQFP

48

I

7.5 Lead-free TQFP

10 Lead-free TQFP

32

48

LC4032V

32

5

Lead-free TQFP

44

32

7.5 Lead-free TQFP

10 Lead-free TQFP

44

32

44

64

5

Lead-free TQFP

100

48

64

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free TQFP

LC4064V

64

7.5 Lead-free TQFP

10 Lead-free TQFP

48

64

48

64

5

Lead-free TQFP

44

64

44

64

10 Lead-free TQFP

Lead-free TQFP

44

128

5

144

128

100

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4128V

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

96

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

128

160

128

160

128

96

Grade

PD

LC4256V-5FTN256AI

LC4256V-75FTN256AI

LC4256V-10FTN256AI

LC4256V-5FTN256BI

LC4256V-75FTN256BI

LC4256V-10FTN256BI

LC4256V-5FN256AI¹

LC4256V-75FN256AI¹

LC4256V-10FN256AI¹

LC4256V-5FN256BI¹

LC4256V-75FN256BI¹

LC4256V-10FN256BI¹

LC4256V-5TN176I

256

384

512

3.3

5

Lead-free ftBGA

256

176

144

100

256

176

256

176

I

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free ftBGA

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free fpBGA

LC4256V

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4256V-75TN176I

LC4256V-10TN176I

LC4256V-5TN144I

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4256V-75TN144I

LC4256V-10TN144I

LC4256V-5TN100I

7.5 Lead-free TQFP

10 Lead-free TQFP

96

5

Lead-free TQFP

64

LC4256V-75TN100I

LC4256V-10TN100I

LC4384V-5FTN256I

LC4384V-75FTN256I

LC4384V-10FTN256I

LC4384V-5FN256I¹

LC4384V-75FN256I¹

LC4384V-10FN256I¹

LC4384V-5TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free ftBGA

192

128

208

128

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

LC4384V

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4384V-75TN176I

LC4384V-10TN176I

LC4512V-5FTN256I

LC4512V-75FTN256I

LC4512V-10FTN256I

LC4512V-5FN256I¹

LC4512V-75FN256I¹

LC4512V-10FN256I¹

LC4512V-5TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free ftBGA

7.5 Lead-free ftBGA

10 Lead-free ftBGA

5

Lead-free fpBGA

LC4512V

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4512V-75TN176I

LC4512V-10TN176I

7.5 Lead-free TQFP

10 Lead-free TQFP

1. Use ftBGA package. fpBGA package devices have been discontinued via PCN#14A-07.

97

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Lead-Free Extended Temperature Devices

Pin/Ball

Count

Device

Part Number

Macrocells Voltage

t

Package

I/O

32

30

64

32

30

96

92

64

128

96

64

Grade

PD

LC4032V-75TN48E

LC4032V-75TN44E

LC4064V-75TN100E

LC4064V-75TN48E

LC4064V-75TN44E

LC4128V-75TN144E

LC4128V-75TN128E

LC4128V-75TN100E

LC4256V-75TN176E

LC4256V-75TN144E

LC4256V-75TN100E

32

3.3

7.5 Lead-free TQFP

48

44

E

LC4032V

64

100

48

LC4064V

LC4128V

LC4256V

64

44

128

256

144

128

100

176

144

100

For Further Information

In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH

4000V/B/C/Z family:

• ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004)

• ispMACH 4000V/B/C/Z Power Consumption (TN1005)

Revision History

Date

Version

Change Summary

—

Previous Lattice releases.

July 2003

17z

Changed device status for LC4064ZC and LC4128ZC to production release and updated/added

AC and DC parameters as well as ordering part numbers for LC4064ZC and LC4128ZC devices.

Improved leakage current speciﬁcations for ispMACH 4000Z. For ispMACH 4000V/B/C IIL, IIH

condition now includes 0V and 3.6V end points (0 ≤ VIN ≤ 3.6V).

Added 132-ball chip scale BGA power supply and NC connections.

Added 132-ball chip scale BGA logic signal connections for LC4064ZC, LC4128ZC and

LC4256ZC devices.

Added lead-free package designators.

October 2003

18z

Hot socketing characteristics footnote 1. has been enhanced; Insensitive to sequence of VCC or

VCCO. However, assumes monotonic rise/fall rates for Vcc and Vcco, provided (VIN - VCCO) ≤

3.6V.

Improved LC4064ZC t to 2.5ns, t to 2.7ns and f

(Ext.) to 175MHz, LC4128ZC t to

CO

S

ST

MAX

3.5ns and f

(Ext.) to 161MHz (version v.2.1).

MAX

Improved associated internal timing numbers and timing adders (version v.2.1).

Added ispMACH 4000V/B/C/Z ORP Reference Tables.

Enhanced ORP information in device pinout tables consistent with the ORP Combinations for I/O

Blocks tables (table 6, 7, 8 and 9 in page 9-11).

Corrected GLB/MC/Pad information in the 256-fpBGA pinouts for the LC4256V/B/C 160-I/O ver-

sion.

Added the ispMACH 4000 Family Speed Grade Offering table.

Added the ispMACH 4128ZC Industrial and Automotive Device OPNs

Added the ispMACH 4032ZC and 4064ZC Industrial and Automotive Device OPNs

December 2003

January 2004

19z

20z

ispMACH 4000Z data sheet status changed from preliminary to ﬁnal. Documents production

release of the ispMACH 4256Z device.

98

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Date

Version

Change Summary

Added new feature - ispMACH 4000Z supports operation down to 1.6V.

Added lead-free packaging ordering part numbers for the ispMACH 4000Z/C/V devices.

April 2004

21z

22z

Updated I (I/O Weak Pull-up Resistor Current) max. speciﬁcation for the ispMACH 4000V/B/C;

-150µA to -200µA.

PU

November 2004

Added User Electronic Signature section.

Added ispMACH 4000B (2.5V) Lead-Free Ordering Part Numbers.

December 2004

February 2006

March 2007

22z.1 Updated Further Information section.

22z.2 Clariﬁcation to ispMACH 4000Z Input Leakage (I ) speciﬁcation.

IH

22.3

Updated ispMACH 4000 Introduction section.

Updated Signal Descriptions table.

June 2007

22.4

Updated Features bullets to include reference to “LA” automotive data sheet under the “Broad

Device Offering” bullet.

Added footnote 1 to Part Number Description to reference the “LA” automotive data sheet.

Changed device temperature references from ‘Automotive’ to “Extended Temperature” for non-

AEC-Q100 qualiﬁed devices.

November 2007

23.0

Added 256-ftBGA package Ordering Part Number information per PCN#14A-07.

99


型号：	LC4256V-75FN256BC1
厂家：	LATTICE SEMICONDUCTOR
描述：	3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs 3.3V / 2.5V / 1.8V在系统可编程超快高密度可编程逻辑器件可编程逻辑器件
文件：	总99页 (文件大小：451K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC4256V-75FN256BC1 [LATTICE]

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