LC5512B-10F256C_技术文档

TM

ispMACH 5000B Family

2.5V In-System Programmable

TM

SuperWIDE High Density PLDs

September 2003

Data Sheet

■ Easy System Integration

• 2.5V power supply

Features

■ High Speed Logic Implementation

• SuperWIDE 68-input logic block

• Hot socketing

• Input pull-up, pull-down or Bus-keeper

(Pin-by-pin selectable)

• Up to 35 product terms per output

• Single-level Global Routing Pool (GRP)

• Open drain capability

■ sysIO^TMCapability

• LVCMOS 1.8, 2.5 and 3.3

• LVTTL

• Macrocell-based power management

• IEEE 1149.1 Boundary Scan testable

• IEEE 1532 compliant In-System Programmable

(ISP™)

• SSTL 2 (I and II)

• SSTL 3 (I and II)

• CTT 3.3, CTT 2.5

• HSTL (I and III)

• PCI 3.3

• GTL+

• AGP-1X

• LVDS (clock input)

• LVPECL (clock input)

• Programmable drive strength

ispMACH 5000B Introduction

The ispMACH 5000B represents the next generation of

Lattice’s SuperWIDE CPLD architecture. Through their

wide 68-input blocks, these devices give signiﬁcantly

improved speed performance for typical designs over

architectures with a lower number of inputs.

In addition to the unique beneﬁts of the SuperWIDE

architecture, the ispMACH 5000B provides sysIO capa-

bility to provide support for a variety of advanced I/O

standards.

■ Ease of Design

• Product term sharing

• Extensive clocking and OE capability

The ispMACH 5000B devices consist of multiple Super-

WIDE 68-input, 32-macrocell Generic Logic Blocks

(GLBs) interconnected by a single-level routing system

referred to as the Global Routing Pool (GRP). Figure 1

shows the ispMACH 5000B block diagram. Together,

the GLBs and the GRP allow designers to create large

designs in a single device without compromising perfor-

mance.

■ Broad Device Offering

• 128 to 512 macrocells

• 92 to 256 I/Os

• 128 to 484 pins/balls in TQFP, PQFP and fpBGA

packages

• Commercial and industrial temperature ranges

Table 1. ispMACH 5000B Family Selection Guide

ispMACH

5128B

ispMACH

5256B

ispMACH

5384B

ispMACH

5512B

Macrocells

128

256

92/144

4.0

384

156/186

4.0

512

156/196/256

4.5

User I/O Options

92

t

(ns)

3.0

PD

t – Set-up with 0 Hold (ns)

1.7

2.1

2.5

S

t

f

(ns)

2.2

275

2.7

2.8

CO

(MHz)

250

2.5

250

200

MAX

Supply Voltage (V)

Package

2.5

128-pin TQFP

208-pin PQFP

256-ball fpBGA

208-pin PQFP

256-ball fpBGA

208-pin PQFP

256-ball fpBGA

484-ball fpBGA

www.latticesemi.com

1

5kb_11.1

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Figure 1. Functional Block Diagram

I/O Bank 3

I/O Bank 0

VCCO3

VCCO0

VREF0

GCLK0

Generic

Logic

Block

Generic

Logic

Block

VREF3

GCLK3

TDI

TDO

TMS

TCK

TOE

GCLK1

VCCO1

Generic

Logic

Block

Generic

Logic

Block

GCLK2

VCCO2

VREF2

RESETB

GOE1

VREF1

GOE2

I/O Bank 1

I/O Bank 2

The GLB has 68 inputs coming from the GRP and contains 163 product terms.These product terms form groups of ﬁve

product term clusters, which feed the product term sharing array and the macrocell directly.The ispMACH 5000B allows

up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is

designed to provide ﬂexible clocking and control functionality with the capability to select between global, product

term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if

required, the sysIO cell.

All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate

I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging

interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage

requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing stan-

dards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide

range of standards allows designers to achieve signiﬁcantly higher board-level performance compared to the more

traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices.

ispMACH 5000B Architecture

The ispMACH 5000B Family of In-System Programmable (ISP™) high density programmable logic devices is

based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to

drive any or all of the GLBs. This mechanism allows fast, efﬁcient connections across the entire device. Figure 1

shows the basic ispMACH 5000B architecture.

Generic Logic Block

Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms

and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true

2

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

and complement form for every product term. The three control product terms are used for shared reset, clock and

output enable functions.

AND-Array

The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs from the GRP are

used to form 136 lines in the AND-array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-

OR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset, and

Shared PT OE. Every set of ﬁve product terms from the 160 logic product terms forms a product term cluster start-

ing with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control prod-

uct terms, the ﬁrst, third, fourth and ﬁfth product terms of each cluster can be used as a PTOE (output macrocells

only), PT Clock, PT Preset and PT Reset, respectively. Figure 2 is a graphical representation of the AND-Array.

Figure 2. ispMACH 5000B AND-Array

In[0]

In[66]

In[67]

PT0

PT1

PT2

PT3

PT4

Cluster 0

PT155

PT156

PT157

PT158

PT159

Cluster 31

PT160 Shared clock

PT161 Shared reset

PT162 Shared OE

Note:

Indicates programmable fuse.

Dual-OR Array

There are two OR gates per macrocell in the GLB. These OR gates are referred to as the PTSA OR gate and the

PTSA-Bypass OR gate. The PTSA-Bypass OR gate receives its ﬁve inputs from the combination of product terms

associated with the product term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow

logic. The PTSA OR gate receives its inputs from the combination of product terms associated with the product

term cluster. Figure 3 shows the Dual-OR Array.

3

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Figure 3. ispMACH 5000B Dual-OR Array

To I/O Block

PT OE

From PT0

From PT1

To Macrocell

PTSA Bypass

n

To PTSA

From PT2

From PT3

To Macrocell

PT Clock

To Macrocell

PT Preset

From PT4

To Macrocell

PT Reset

Product Term Sharing Array

The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array and 32 outputs directly to

the macrocells. Each output is the OR term of any combination of the seven PTSA OR terms connected to that out-

put. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2, and N+3 PTSA OR terms via a programma-

ble connection. Figure 4 shows the graphical representation of the PTSA.

Figure 4. ispMACH 5000B PTSA

PTSA OR 0

Macrocell 0

Macrocell 1

Macrocell 2

PTSA OR 1

PTSA OR 2

PTSA OR 3

PTSA OR 29

Macrocell 29

PTSA OR 30

Macrocell 30

PTSA OR 31

Macrocell 31

4

Lattice Semiconductor

Macrocell

ispMACH 5000B Family Data Sheet

The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each

macrocell contains a programmable XOR gate, a programmable register/latch ﬂip-ﬂop and the necessary clocks

and control logic to allow combinatorial or registered operation.

The macrocells each have two outputs, which can be fed to the GRP and I/O cell. This dual or concurrent output

capability from the macrocell gives efﬁcient use of the hardware resources. One output can be a registered function

for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O

cell facilitates efﬁcient use of the macrocell to construct high-speed input registers.

Macrocell registers can be clocked from one of several global or product term clocks available on the device. A glo-

bal and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers

directly. Reset and preset for the macrocell register is provided from both global and product term signals. The

macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 5 is a graphical rep-

resentation of the ispMACH 5000B macrocell.

Figure 5. ispMACH 5000B Macrocell

From

GRP

PT OE to

I/O Block

From

I/O Cell

68

PTSA Bypass

Output

to I/O Block

D

Q

PTSA

PT Clock

Clk En

GRP

R/L

Shared PT Clock

CLK0

CLK1

CLK2

CLK3

Clk

P

Speed/

Power

R

PT Preset

PT Reset

Shared PT Reset

Global Reset

AND Array

Dual-OR Array

Macrocell

I/O Cell

The ispMACH 5000B I/O cell provides a high degree of ﬂexibility. It includes the sysIO feature and an enhanced

output enable MUX for optimal performance both on- and off-chip. The sysIO feature allows I/O cells to be conﬁg-

ured to different I/O standards, drive strengths and slew rates. The enhanced output enable MUX provides up to 14

different output enable choices per I/O cell.

The I/O cell contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input

buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-friendly latch.

The I/O cell receives its input from its associated macrocell. The I/O cell has a feedback line to its associated mac-

rocell and a direct path to the GRP.

The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four shared

PTOE signals, PTOE, the two GOE signals. The OE MUX also has the ability to choose either the true or inverse of

5

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tri-

stating of the outputs for testing purposes.

The four Shared PTOE signals are derived from PT163 of each GLB. The PTOE signal is derived from the ﬁrst

product term in each macrocell cluster, which is directly routed to the OE MUX.Therefore, every I/O cell can have a

different OE signal. Figure 6 is a graphical representation of the I/O cell.

Figure 6. ispMACH 5000B I/O Cell

Global PTOE 0

Global PTOE 1

Global PTOE 2

Global PTOE 3

PTOE

V

_CCfor

GOE0

GOE1

whole chip

V

_CCOto all

TOE

other I/Os

in bank

Data Output

from Macrocell

Output Buffer

(V_CCOindependent for

open drain outputs)

GND

I/O

Pad

CMOS/TTL

Input Buffer

Data Input to Routing

Data Input to Macrocell

(V_REFindependent)

+

–

V_REFto all

other I/Os in bank

V

_REFdependent

Input Buffer

sysIO Capability

The ispMACH 5000B devices are divided into four sysIO banks, where each bank is capable of supporting 14 dif-

ferent I/O standards. Each sysIO bank has its own I/O supply voltage (V ), reference voltage (V ), and termi-

CCO

REF

nation voltage (V , as applicable), resources allowing each bank complete independence from the others. Each

TT

I/O within a bank is individually conﬁgurable consistent with the V

and V

settings. In addition, each I/O has

CCO

REF

individually conﬁgurable drive strength, weak pull-up, weak pull-down or a bus-friendly latch. Table 2 lists the

sysIO standards with the typical values for V , V and V .

CCO REF

TT

The TOE and JTAG pins of the ispMACH 5000B device are the only pins that do not have sysIO capabilities. These

pins support the 2.5V LVTTL and LVCMOS standards.

There are three classes of I/O interface standards implemented in the ispMACH 5000B devices. The ﬁrst is the

un-terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V

LVCMOS interface standards. Additionally, PCI and AGP-1X are all subsets of this type of interface.

The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-

faces includes different versions of SSTL and HSTL interfaces along with CTT, GTL+ and single-ended LVPECL.

Use of these particular I/O interfaces requires an additional V

signal. At the system level a termination voltage,

REF

V , is also required. Typically an output will be terminated to V at the receiving end of the transmission line it is

TT

driving.

The ﬁnal type of interfaces implemented are the differential standards LVDS and LVPECL. These interfaces are

implemented on clock pins only. When using one of the differential standards, a pair of global clock pins (GCLK0

and GCLK1 or GCLK2 and GCLK3) are combined to create a single clock signal.

6

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

For more information on the sysIO capability, please refer to technical note number TN1000, sysIO Design and

Usage Guidelines available on the Lattice web site at www.latticesemi.com.

Table 2. ispMACH 5000B Supported I/O Standards

sysIO Standard

LVTTL

V

TT

CCO

REF

3.3V

2.5V

1.8V

3.3V

2.5V

3.3V

2.5V

1.5V

N/A

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

PCI 3.3

N/A

AGP-1X

N/A

SSTL3, Class I, II

SSTL2, Class I, II

CTT 3.3

1.5V

1.25V

1.5V

1.25V

0.75V

0.9

1.5V

1.25V

1.5V

1.25V

0.75V

1.5V

CTT 2.5

HSTL, Class I

HSTL, Class III

GTL+

1.0V

GLB Clock Distribution

The ispLSI 5000B family has four dedicated clock input pins: GCLK0-GCLK3. These feed the Global Clock MUX,

which generates the four global clock signals (CLK0-CLK3). The global clock MUX allows a variety of combinat-

tions of complementary forms of the clock to be used within the device. Additionally, the ispMACH 5000B clock dis-

tribution network offers a differential pair of clock inputs into the global clock MUX for added ﬂexibility. Figure 7

shows the global clock MUX.

The global clock pins are arranged in two pairs, GCLK0 and GCLK1 signals are in one pair and GCLK2 and

GCLK3 signals are in the other pair. The pins are arranged on the die such that each pair of external clock signals

can generate one internal clock from either side of the die when used in differential inputs.This arrangement allows

the clock pins to be used either as four single ended clock signals or two differential (LVPECL or LVDS) clock sig-

nal. Both polarities of the clock are available to drive the internal clock distribution networks.

7

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Figure 7. ispMACH 5000B Global Clock MUX

+

–

GCLK0

VREF0

CLK0

CLK1

+

–

GCLK1

VREF1

VREF2

GCLK2

–

+

CLK2

CLK3

VREF3

GCLK3

–

+

Power Management

The ispMACH 5000B devices provide unique power management controls. The device has two power settings,

high power and low power, on a per node basis. Low power consumption is approximately 50% of high power con-

sumption with a timing delay adder (t ) to the routing delay of the low power node. Each node can be conﬁgured

LP

as either high power or low power. However, care should be taken when sharing product terms between nodes with

different power settings.

The ispMACH 5000B devices also have a power-off feature for product terms that are not used. By default, any product

term that is not used is conﬁgured as such. This allows the device to operate at minimal power consumption without

affecting the timing of the design. For further information on power management, please refer to technical note number

TN1023, Power Estimation in ispMACH 5000B Devices available on the Lattice web site at www.latticesemi.com.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 5000B devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly

onto test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be

linked into a board-level serial scan path for more board-level testing.

sysIO Quick Conﬁguration

To facilitate the most efﬁcient board test, the physical circuit conﬁguration of the I/O cells must be set before run-

ning any continuity tests. As these tests are fast, by nature, the overhead and time that is required for conﬁguration

of the I/Os should be minimal so that board test time is minimized. The ispMACH 5000B family of devices supports

this by offering the user the ability to quickly conﬁgure the I/O standard supported by the sysIO cells. This quick

conﬁguration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed.

Lattice's ispVM™ System programming software can either perform the quick conﬁguration through the PC parallel

port, or can generate the ATE or test vectors necessary for a third-party test system.

IEEE 1532-Compliant In-System Programming

In-system programming of devices provides a number of signiﬁcant beneﬁts including rapid prototyping, lower inven-

tory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations. All ispMACH 5000B devices provide in-system

programmability through their Boundary Scan Test Access Port. This capability has been implemented in a manner

8

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication

interface through which ISP is achieved, customers get the beneﬁt of a standard, well-deﬁned interface.

The ispMACH 5000B devices can be programmed across the commercial temperature and voltage range. The PC-

based Lattice software facilitates in-system programming of ispMACH 5000B devices. The software takes the

JEDEC ﬁle output produced by the design implementation software, along with information about the JTAG chain,

and creates a set of vectors that are used to drive the JTAG chain. The software can use these vectors to drive a

JTAG chain via the parallel port of a PC. Alternatively, the software can output ﬁles in formats understood by com-

mon automated test equipment. This equipment can then be used to program ispMACH 5000B devices during the

testing of a circuit board.

Security Scheme

A programmable security scheme is provided on the ispMACH 5000B devices as a deterrent to unauthorized copy-

ing of the array conﬁguration patterns. Once programmed, this security prevents readback of the programmed pat-

tern by a device programmer, securing proprietary designs from competitors. The security scheme also prevents

programming and veriﬁcation. The entire device must be erased in order to reset the security scheme.

Hot Socketing

The ispMACH 5000B devices are well suited for those applications that require hot socketing capability. Hot socket-

ing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs with-

out being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active

signals.

Density Migration

The ispMACH 5000B family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-

geted for a high density device to a lower density device. However, the exact details of the ﬁnal resource utilization

will impact the likely success in each case.

9

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.05V

CC

Output Supply Voltage V

. . . . . . . . . . . . . . . . . . -0.5 to 4.05V

CCO

Input Voltage Applied⁴. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.05V

Tri-state Output Voltage Applied. . . . . . . . . . . . . . . . -0.5 to 4.05V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Junction Temperature (Tj) with Power Applied. . . . . -55 to 130°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation

is not implied.

2. Compliance with Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and Undershoot of -2V to (V

+2) volts is permitted for a duration of < 20ns.

IHMAX

Recommended Operating Conditions

Symbol

Parameter

Min

2.3

0

Max

2.7

90

Units

V

Supply Voltage

V

C

CC

Junction Temperature (Commercial)

Junction Temperature (Industrial)

T

J

-40

105

Erase Reprogram Speciﬁcations

Parameter

Min

Max

Units

Erase/Reprogram Cycle

1,000

—

Cycles

Hot Socketing Characteristics^1,2,3

Symbol

Parameter

Condition

0 ≤ V ≤ V (MAX)

Min

—

Typ

—

Max

Units

µA

+/- 100

IN

IH

I

Input or I/O Leakage Current

DK

V

(MAX) ≤ V ≤ 3.6V

—

µA

IH

IN

1. Insensitive to sequence of V and V

. However, assumes monotonic rise / fall rates for V and V

.

CC

CCO

CC

CCO

2. LVTTL, LVCMOS only

3. 0 ≤ V ≤ V (MAX), 0 ≤ V

≤ V

(MAX)

CC

CCO

10

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min

—

Typ

—

Max

+/- 10

+/- 100

-150

150

Units

µA

V

Input

I/O

0V ≤ V ≤ V

IN CC

1, 2

IL IH

I , I

0V ≤ V ≤ V

—

IN

CCO

Input

I/O

V

≤ V ≤ 3.6V

—

CC

IN

I

DK

≤ V ≤ 3.6V

—

CCO

IN

0V ≤ V ≤ 1.7V

-30

-15

30

IN

2

I/O Weak Pull-up Resistor Current

PU

1.7V < V ≤ 2.0V

IN

I

I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MAX)

PD

IL

IN

IH

2

Bus Hold Low Sustaining Current

V

= V (MAX)

30

—

BHLS

IN

IL

= 1.7V

= 2.0V

-30

-15

—

2

I

Bus Hold High Sustaining Current

BHHS

—

2

I

Bus Hold Low Overdrive Current

Bus Hold High Overdrive Current

Bus Hold Trip Points

0V ≤ V ≤ 3.6V

150

BHLO

IN

2

0V ≤ V ≤ 3.6V

—

-150

BHHO

IN

V

(MAX)

V

IH

(MIN)

BHT

IL

No Output Loading

—

10

mA

V

= 3.3V

CCO

No Output Loading

= 2.5V

3, 4, 5, 6

CCO

I

I/O Supply Current

10

V

CCO

No Output Loading

V

= 1.8V

CCO

C

I/O Capacitance³

Clock Capacitance³

Global Input Capacitance³

= 2.5V, V = 0 to 3.6V

—

8

—

pf

1

2

3

CC

IO

= 2.5V, V

= 0 to 3.6V

10

CLOCK

= 0 to 3.6V

GLOBAL

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. Only available for LVCMOS and LVTTL standards.

3. T = 25°C, f = 1.0MHz.

A

4. Device conﬁgured with 16-bit counters.

5. I varies with speciﬁc device conﬁguration and operating frequency.

CC

6. Per bank.

Supply Current

Symbol

Parameter

Condition

= 2.5V

Min

—

Typ

83

Max

—

Units

mA

ispMACH 5128B

1, 2, 3

CC

I

Operating Power Supply Current

V

CCO

ispMACH 5256B

1, 2, 3

CC

I

Operating Power Supply Current

= 2.5V

—

130

216

270

—

mA

ispMACH 5384B

1, 2, 3

CC

I

Operating Power Supply Current

—

mA

ispMACH 5512B

1, 2, 3

CC

I

Operating Power Supply Current

—

mA

1. T = 25°C, f = 1.0MHz.

A

2. Device conﬁgured with 16-bit counters.

3. I varies with speciﬁc device conﬁguration and operating frequency.

CC

11

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

sysIO Recommended Operating Conditions

V

(V)

V

(V)

CCO

REF

Standard

Min

3.0

2.3

1.65

3.0

3.15

3.0

2.3

3.0

2.3

1.4

Max

3.6

2.7

1.95

3.6

3.45

3.6

2.7

3.6

2.7

1.6

3.6

Min

—

Max

—

LVTTL

LVCMOS 3.3

LVCMOS 2.5¹

LVCMOS 1.8

PCI 3.3

—

AGP-1X

—

SSTL 3, Class I, II

SSTL 2, Class I, II

CTT 3.3

1.3

1.15

1.35

0.68

0.882

1.7

1.35

1.65

0.9

1.122

CTT 2.5

HSTL

GTL+

1. Software default setting.

12

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

sysIO DC Electrical Characteristics

Over Recommended Operating Conditions

V

IH

2

IL

Input/Output

Standard

V

I

OH

OL

OH

OL

Min (V)

Max (V)

Min (V)

Max (V)

Min (V)

(mA)

20, 16, -20, -16,

12, 8, -12, -8,

5.33, 4 -5.33 -4

(mA)

LVCMOS 3.3

-0.3

0.8

2.0

3.6

0.4

2.4

0.4

0.2

0.4

2.4

20

0.1

8

20

0.1

-8

LVTTL

-0.3

0.8

0.7

2.0

1.7

3.6

V

- 0.2

CCO

LVCMOS 2.5¹

- 0.4

- 0.2

-0.4

16, 12, -16, -12,

5.33, 4 -5.33, -4

0.4

0.2

0.4

0.2

V

CCO

LVCMOS 2.5

LVCMOS 1.8

-0.3

0.7

1.7

3.6

0.1

-0.1

12, 8,

5.33, 4 -5.33, -4

-12, -8,

V

CCO

0.68

1.07

V

- 0.2

0.1

1.5

8

-0.1

-0.5

-8

PCI 3.3

-0.3

1.08

1.5

3.6

0.1V

0.9V

CCO

AGP-1X

CCO

SSTL3 class I

SSTL3 class II

SSTL2 class I

SSTL2 class II

CTT 3.3

V

-0.2

V

+0.2

0.7

V

- 1.1

REF

CCO

0.5

V

- 0.9

- 0.62

- 0.43

+ 0.4

- 0.4

16

7.6

15.2

8

-16

-7.6

-15.2

-8

V

-0.18

V

+0.18

0.54

0.35

V

REF

CCO

V

-0.2

-0.1

-0.2

V

+0.2

+0.1

+0.2

V

-0.4

V

REF

CTT 2.5

V

-0.4

V

8

-8

HSTL class I

HSTL class III

GLT+

V

0.4

V

8

-8

CCO

0.4

0.6

- 0.4

24

36

-8

N/A

1. Software default setting

2.The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the

I/O bank, as shown in the logic signals connection table, shall not exceed 96mA.

sysIO Differential Input DC Electrical Characteristics and Operating Conditions

Symbol

. V

Parameter

Test Conditions

Min

Max

V

LVDS Input voltage

—

0V

2.4V

INP

INM

LVDS Differential input

threshold

—

+/- 100mV

—

THD

V

= 3.0 to 3.6V

= 3.3V

V

-1.81V

V

-1.48V

CCIO

LVPECL Input Voltage

Low

CCIO

1

IL

V

1.49V

1.83V

-0.88V

= 3.0 to 3.6V

= 3.3V

V

-1.17V

LVPECL Input Voltage

High

CCIO

1

IH

V

2.14V

2.42V

1. V

is in 3.3V range.

CCIO

13

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B External Switching Characteristics

Over Recommended Operating Conditions

-3

-5

-75

-10

Parameter

Description^{1, 2, 3}

Data propagation delay, 5-PT bypass

Propagation delay

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

-

3.0

3.8

-

5.0

6.5

-

7.5

9.0

-

10.0

12.0

ns

PD

t

PD_PTSA

S

GLB register setup time before clock, 5-PT

bypass

1.7

2.2

2.0

-

3.0

4.0

2.5

-

5.0

6.5

3.5

-

6.5

8.5

5.0

-

ns

t

GLB register setup time before clock

S_PTSA

GLB register setup time before clock, input reg-

ister path, 5-PT bypass

SIR

t

GLB register hold time before clock, 5-PT

bypass

H

0.0

-

0.0

-

0.0

-

0.0

-

ns

t

GLB register hold time before clock

H_PTSA

GLB register hold time before clock, input

reg.path

HIR

t

GLB register clock-to-output delay

External reset pin to output delay

Reset pulse duration

-

2.2

2.5

-

3.0

5.0

-

4.0

7.5

-

5.5

10.0

-

ns

CO

R

3.0

3.5

5.0

6.5

RW

Input to output local product term output

enable/disable

PTEN/DIS

-

4.0

4.2

-

6.0

7.0

-

8.5

-

10.0

12.0

ns

t

Input to output global product term output

enable/disable

GPTEN/DIS

10.0

t

Global OE input to output enable/disable

Clock pulse duration

-

2.5

-

3.7

-

5.5

-

7.5

-

ns

GOE/DIS

1.3

2.2

2.5

2.8

CW

Global gate width low (for low transparent) or

high (for high transparent)

GW

1.3

-

2.2

-

2.5

-

2.8

-

ns

t

f

Input register clock width, high or low

Clock frequency with internal feedback

1.3

-

2.2

-

2.5

-

2.8

-

ns

WIR

4

275

180

150

110

MHz

MAX

(Ext.) Clock frequency with external feedback,

MAX

227

350

-

142

225

-

95

-

71

-

MHz

1/(t

+ t

)

S_PTSA

CO

f

(Tog.) Clock frequency max toggle

200

175

-

MHz

Timing v.1.0

1. Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other stan-

dards.

2. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and

high speed AND array.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

14

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B External Switching Characteristics

Over Recommended Operating Conditions

-4

-5

-75

-10

Parameter

Description^{1, 2, 3}

Data propagation delay, 5-PT bypass

Propagation delay

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

-

4.0

4.8

-

5.0

6.5

-

7.5

9.0

-

10.0

12.0

ns

PD

t

PD_PTSA

S

GLB register setup time before clock, 5-PT

bypass

2.1

2.7

1.9

-

3.0

4.0

2.5

-

5.0

6.5

3.5

-

6.5

8.5

5.0

-

ns

t

GLB register setup time before clock

S_PTSA

GLB register setup time before clock, input reg-

ister path, 5-PT bypass

SIR

t

GLB register hold time before clock, 5-PT

bypass

H

0.0

-

0.0

-

0.0

-

0.0

-

ns

t

GLB register hold time before clock

H_PTSA

GLB register hold time before clock, input

reg.path

HIR

t

GLB register clock-to-output delay

External reset pin to output delay

Reset pulse duration

-

2.7

3.8

-

3.0

5.0

-

4.0

7.5

-

5.5

10.0

-

ns

CO

R

3.0

3.5

5.0

6.5

RW

Input to output local product term output

enable/disable

PTEN/DIS

-

5.0

5.5

-

6.0

7.0

-

8.5

-

10.0

12.0

ns

t

Input to output global product term output

enable/disable

GPTEN/DIS

10.0

t

Global OE input to output enable/disable

Clock pulse duration

-

3.4

-

3.7

-

5.5

-

7.5

-

ns

GOE/DIS

1.5

2.2

2.5

2.8

CW

Global gate width low (for low transparent) or

high (for high transparent)

GW

1.5

-

2.2

-

2.5

-

2.8

-

ns

t

f

Input register clock width, high or low

Clock frequency with internal feedback

1.5

-

2.2

-

2.5

-

2.8

-

ns

WIR

4

250

180

150

110

MHz

MAX

(Ext.) Clock frequency with external feedback,

MAX

185

333

-

142

225

-

95

-

71

-

MHz

1/(t

+ t

)

S_PTSA

CO

f

(Tog.) Clock frequency max toggle

200

175

-

MHz

Timing v.1.3

1. Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other stan-

dards.

2. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and

high speed AND array.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

15

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5384B External Switching Characteristics

Over Recommended Operating Conditions

-4

-5

-75

-10

Parameter

Description^{1, 2, 3}

Data propagation delay, 5-PT bypass

Propagation delay

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

-

4.0

4.8

-

5.0

6.5

-

7.5

9.0

-

10.0

12.0

ns

PD

t

PD_PTSA

S

GLB register setup time before clock, 5-PT

bypass

2.1

2.7

1.9

-

3.0

4.0

2.5

-

5.0

6.5

3.5

-

6.5

8.5

5.0

-

ns

t

GLB register setup time before clock

S_PTSA

SIR

GLB register setup time before clock, input reg-

ister path, 5-PT bypass

t

GLB register hold time before clock, 5-PT

bypass

H

0.0

-

0.0

-

0.0

-

0.0

-

ns

t

GLB register hold time before clock

H_PTSA

HIR

GLB register hold time before clock, input

reg.path

0.00

t

GLB register clock-to-output delay

External reset pin to output delay

Reset pulse duration

-

2.7

3.8

-

3.0

5.0

-

4.0

7.5

-

5.5

10.0

-

ns

CO

R

3.0

3.5

5.0

6.5

RW

Input to output local product term output enable/

disable

PTEN/DIS

-

5.0

5.5

-

6.0

7.0

-

8.5

-

10.0

12.0

ns

t

Input to output global product term output

enable/disable

GPTEN/DIS

10.0

t

Global OE input to output enable/disable

Clock pulse duration

-

3.4

-

3.7

-

5.5

-

7.5

-

ns

GOE/DIS

CW

1.5

2.2

2.5

2.8

Global gate width low (for low transparent) or

high (for high transparent)

GW

1.5

-

2.2

-

2.5

-

2.8

-

ns

t

f

Input register clock width, high or low

Clock frequency with internal feedback

1.5

-

2.2

-

2.5

-

2.8

-

ns

WIR

4

250

180

150

110

MHz

MAX

(Ext.) Clock frequency with external feedback,

MAX

185

333

-

142

225

-

95

-

71

-

MHz

1/(t

)

S_PTSA+tCO

f

(Tog.) Clock frequency max toggle

200

175

-

MHz

Timing v.1.0

1. Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other standards.

2. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and

high speed AND array.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

16

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B External Switching Characteristics

Over Recommended Operating Conditions

-45

-75

-10

-12

Parameter

Description^{1, 2, 3}

Data propagation delay, 5-PT bypass

Propagation delay

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

-

4.5

5.3

-

7.5

9.0

-

10.0

12.0

-

12.0

15.0

ns

PD

PD_PTSA

S

GLB register setup time before clock, 5-PT

bypass

2.5

3.1

1.7

-

5.0

6.5

3.5

-

6.5

8.5

5.0

-

7.5

10.5

5.5

-

ns

t

GLB register setup time before clock

S_PTSA

SIR

GLB register setup time before clock, input reg-

ister path, 5-PT bypass

t

GLB register hold time before clock, 5-PT

bypass

H

0.0

-

0.0

-

0.0

-

0.0

-

ns

t

GLB register hold time before clock

H_PTSA

GLB register hold time before clock, input

reg.path

HIR

t

GLB register clock-to-output delay

External reset pin to output delay

Reset pulse duration

-

2.8

4.2

-

4.0

7.5

-

5.5

10.0

-

6.5

12.0

-

ns

CO

R

3.0

5.0

6.5

8.0

RW

Input to output local product term output enable/

disable

PTEN/DIS

-

5.5

6.3

-

8.5

-

10.0

12.0

-

12.0

15.0

ns

t

Input to output global product term output

enable/disable

GPTEN/DIS

10.0

t

Global OE input to output enable/disable

Clock pulse duration

-

3.5

-

5.5

-

7.5

-

9.0

-

ns

GOE/DIS

CW

2.0

2.5

2.8

3.3

Global gate width low (for low transparent) or

high (for high transparent)

GW

2.0

-

2.5

-

2.8

-

3.3

-

ns

t

f

Input register clock width, high or low

Clock frequency with internal feedback

2.0

-

2.5

-

2.8

-

3.3

90

-

ns

WIR

4

200

150

110

MHz

MAX

(Ext.) Clock frequency with external feedback,

MAX

169

250

-

95

-

71

-

58

-

MHz

1/(t

+ t

)

S_PTSA

CO

f

(Tog.) Clock frequency max toggle

200

175

150

-

MHz

Timing v.1.1

1. Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other stan-

dards.

2. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0 and 1 output switching

and high speed AND array.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

17

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Timing Model

The task of determining the timing through the ispLSI 5000B family, just as any CPLD, is relatively simple. The tim-

ing model provided in Figure 8 shows the speciﬁc delay paths. Once the implementation of a given function is

determined either conceptually or from the design tool report ﬁle, the delay path of the function can easily be

derived from the timing model. The design tool reports the timing delays based on the same timing model for a par-

ticular design. Note that the internal timing parameters are given for reference only and are not tested. The external

timing parameters are tested and guaranteed for every device.

Figure 8. ispMACH 5000B Timing Model

Routing/

GLB Delays

From Feedback

t_PDb

Feedback

t_PDi

t_FBK

t_ROUTE

t_BUF

t_EN

t_DIS

t_IOO

t_IN

t_BLA

t_LP

t_PTSA

DATA

OUT

IN

Q

t_IOI

t_INREG

In/Out

Delays

t_{GCLK_IN}

CLK

t_IOI

t_PTCLK

t_BCLK

CE

t_PTSR

t_BSR

S/R

MC Reg

t_RST

t_IOI

Register/

Latch Delays

RST

OE

t_GPTOE

t_PTOE

t_GOE

t_IOI

Control

Delays

In/Out

Delays

Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array

and VCC I/O option).

18

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B Internal Timing Parameters¹

Over Recommended Operating Conditions

-3

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

-

0.30

1.00

1.60

0.50

0.90

1.20

-

0.60

1.50

2.60

0.80

1.10

2.20

-

2.00

1.40

3.00

1.80

2.50

2.70

-

2.40

1.90

4.40

2.50

3.10

3.60

ns

IN

Global Clock Input Buffer Delay

Global OE Pin Delay

GCLK_IN

GOE

BUF

EN

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Global Rest Pin Delay

RST

Routing Delays

t

Delay through GRP

-

1.60

1.10

0.60

0.30

2.50

0.00

-

2.50

2.10

1.10

0.50

3.10

0.00

-

2.60

1.10

0.00

2.20

0.00

-

3.70

3.40

1.40

0.00

3.60

0.00

ns

ROUTE

PTSA

PDb

Product Term Sharing Array

5-PT Bypass Propogation Delay

Macrocell Propogation Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

PDi

INREG

FBK

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

Latch Setup Time (Product Term Clock)

D-Register Hold Time

0.20

1.50

-

0.30

0.20

2.70

-

0.70

4.30

-

0.90

5.60

-

ns

S

-

S_PT

SL_PT

H

-

Register Clock to Output/Feedback Mux Time

Clock Enable Setup Time

0.70

0.80

1.10

COi

CES

CEH

SL

3.30

0.20

1.50

-

4.30

0.40

0.30

2.70

-

4.70

0.50

0.70

4.30

-

5.00

0.60

0.90

5.60

-

Clock Enable Hold Time

-

Latch Setup Time

-

Latch Hold Time

HL

Latch Gate to Output/Feedback Mux Time

0.70

0.60

0.80

1.60

GOi

PDLi

Propogation Delay through Transparent Latch

to Output/Feedback Mux

-

0.50

-

0.50

-

0.50

-

0.50

ns

t

Asynchronous Reset or Set to Output/Feed-

back MUX Delay

SRi

-

0.80

-

2.00

-

3.00

-

3.90

-

ns

t

Asynchronous Reset or Set Recovery Delay

1.50

2.70

4.00

6.00

SRR

Control Delays

t

GLB PT Clock Delay

-

1.70

1.50

1.20

0.80

1.40

1.20

-

2.40

2.10

1.70

1.10

2.80

1.80

-

2.80

2.40

1.90

1.20

2.90

1.40

-

3.20

2.70

2.10

1.30

2.80

0.80

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

PTOE

Macrocell PT OE Delay

Timing v.1.0

1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

19

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B Internal Timing Parameters¹

Over Recommended Operating Conditions

-4

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

-

0.40

1.20

2.40

1.00

1.30

-

0.60

1.50

2.60

0.80

1.10

2.20

-

2.00

1.40

3.00

1.80

2.50

2.70

-

2.40

1.90

4.40

2.50

3.10

3.60

ns

IN

Global Clock Input Buffer Delay

Global OE Pin Delay

GCLK_IN

GOE

BUF

EN

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Global Rest Pin Delay

RST

Routing Delays

t

Delay through GRP

-

1.80

1.40

0.80

0.20

2.40

0.00

-

2.50

2.10

1.10

0.50

3.10

0.00

-

2.60

1.10

0.00

2.20

0.00

-

3.70

3.40

1.40

0.00

3.60

0.00

ns

ROUTE

PTSA

PDb

Product Term Sharing Array

5-PT Bypass Propogation Delay

Macrocell Propogation Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

PDi

INREG

FBK

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

Latch Setup Time (Product Term Clock)

D-Register Hold Time

0.30

1.80

-

0.30

0.20

2.70

-

0.70

4.30

-

0.90

5.60

-

ns

S

-

S_PT

SL_PT

H

-

Register Clock to Output/Feedback Mux Time

Clock Enable Setup Time

0.50

0.70

0.80

1.10

COi

CES

CEH

SL

3.90

0.30

1.80

-

4.30

0.40

0.30

2.70

-

4.70

0.50

0.70

4.30

-

5.00

0.60

0.90

5.60

-

Clock Enable Hold Time

-

Latch Setup Time

-

Latch Hold Time

HL

Latch Gate to Output/Feedback Mux Time

0.60

0.80

1.60

GOi

PDLi

Propogation Delay through Transparent Latch

to Output/Feedback Mux

-

0.50

-

0.50

-

0.50

-

0.50

ns

t

Asynchronous Reset or Set to Output/Feed-

back MUX Delay

SRi

-

1.50

-

2.00

-

3.00

-

3.90

-

ns

t

Asynchronous Reset or Set Recovery Delay

2.00

2.70

4.00

6.00

SRR

Control Delays

t

GLB PT Clock Delay

-

2.00

1.80

1.50

1.00

2.30

1.80

-

2.40

2.10

1.70

1.10

2.80

1.80

-

2.80

2.40

1.90

1.20

2.90

1.40

-

3.20

2.70

2.10

1.30

2.80

0.80

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

PTOE

Macrocell PT OE Delay

Timing v.1.3

1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

20

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5384B Internal Timing Parameters¹

Over Recommended Operating Conditions

-4

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

-

0.40

1.20

2.40

1.00

1.30

-

0.60

1.50

2.60

0.80

1.10

2.20

-

2.00

1.40

3.00

1.80

2.50

2.70

-

2.40

1.90

4.40

2.50

3.10

3.60

ns

IN

Global Clock Input Buffer Delay

Global OE Pin Delay

GCLK_IN

GOE

BUF

EN

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Global Rest Pin Delay

RST

Routing Delays

t

Delay through GRP

-

1.80

1.40

0.80

0.20

2.40

0.00

-

2.50

2.10

1.10

0.50

3.10

0.00

-

2.60

1.10

0.00

2.20

0.00

-

3.70

3.40

1.40

0.00

3.60

0.00

ns

ROUTE

PTSA

PDb

Product Term Sharing Array

5-PT Bypass Propogation Delay

Macrocell Propogation Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

PDi

INREG

FBK

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

Latch Setup Time (Product Term Clock)

D-Register Hold Time

0.30

1.80

-

0.30

0.20

2.70

-

0.70

4.30

-

0.90

5.60

-

ns

S

-

S_PT

SL_PT

H

-

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

0.50

0.70

0.80

1.10

COi

CES

CEH

SL

3.90

0.30

1.80

-

4.30

0.40

0.30

2.70

-

4.70

0.50

0.70

4.30

-

5.00

0.60

0.90

5.60

-

Clock Enable Hold Time

-

Latch Setup Time

-

Latch Hold Time

HL

Latch Gate to Output/Feedback Mux Time

0.60

0.80

1.60

GOi

PDLi

Propogation Delay through Transparent Latch

to Output/Feedback Mux

-

0.50

-

0.50

-

0.50

-

0.50

ns

t

Asynchronous Reset or Set to Output/Feed-

back MUX Delay

SRi

-

1.50

-

2.00

-

3.00

-

3.90

-

ns

t

Asynchronous Reset or Set Recovery Delay

2.00

2.70

4.00

6.00

SRR

Control Delays

t

GLB PT Clock Delay

-

2.00

1.80

1.50

1.00

2.30

1.80

-

2.40

2.10

1.70

1.10

2.80

1.80

-

2.80

2.40

1.90

1.20

2.90

1.40

-

3.20

2.70

2.10

1.30

2.80

0.80

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

PTOE

Macrocell PT OE Delay

Timing v.1.0

1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

21

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Internal Timing Parameters¹

Over Recommended Operating Conditions

-45

-75

-10

-12

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

-

0.30

1.50

2.50

0.60

1.00

1.90

-

2.00

1.40

3.00

1.80

2.50

2.70

-

2.40

1.90

4.40

2.50

3.10

3.60

-

3.20

2.50

5.50

2.80

3.50

4.90

ns

IN

Global Clock Input Buffer Delay

Global OE Pin Delay

GCLK_IN

GOE

BUF

EN

Delay through Output Buffer

Output Enable Time

Output Disable Time

DIS

Global Rest Pin Delay

RST

Routing Delays

t

Delay through GRP

-

2.50

1.70

1.10

0.20

2.80

0.00

-

2.60

1.10

0.00

2.20

0.00

-

3.70

3.40

1.40

0.00

3.60

0.00

-

4.10

4.90

1.90

0.00

4.00

0.00

ns

ROUTE

PTSA

PDb

Product Term Sharing Array

5-PT Bypass Propogation Delay

Macrocell Propogation Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

PDi

INREG

FBK

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

Latch Setup Time (Product Term Clock)

D-Register Hold Time

0.10

2.40

-

0.70

4.30

-

0.90

5.60

-

0.80

1.40

6.70

-

ns

S

-

S_PT

SL_PT

H

-

Register Clock to Output/Feedback Mux Time

Clock Enable Setup Time

0.70

0.80

1.10

1.20

COi

CES

CEH

SL

4.10

0.30

0.10

2.40

-

4.70

0.50

0.70

4.30

-

5.00

0.60

0.90

5.60

-

5.00

0.60

0.80

5.60

-

Clock Enable Hold Time

-

Latch Setup Time

-

Latch Hold Time

HL

Latch Gate to Output/Feedback Mux Time

0.60

0.80

1.60

GOi

PDLi

Propogation Delay throughTransparent Latch to

Output/Feedback Mux

-

0.50

-

0.50

-

0.50

-

0.50

ns

t

Asynchronous Reset or Set to Output/Feedback

Mux Delay

SRi

-

1.70

-

3.00

-

3.90

-

4.30

-

ns

t

Asynchronous Reset or Set Recovery Delay

2.30

4.00

6.00

7.50

SRR

Control Delays

t

GLB PT Clock Delay

-

2.20

2.00

1.60

1.10

2.50

1.70

-

2.80

2.40

1.90

1.20

2.90

1.40

-

3.20

2.70

2.10

1.30

2.80

0.80

-

3.60

3.00

2.30

1.40

4.20

1.20

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

PTOE

Macrocell PT OE Delay

Timing v.1.1

1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

22

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B Timing Adders

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Low Power Adder

-

1.00

-

1.00

-

1.00

-

1.00 ns

LP

ROUTE

t

Input Adders

IOI

t , t

,

Using LVCMOS1.8

standard

IN GCLK_IN

LVCMOS18_in

LVCMOS25_in

LVCMOS33_in

PCI_in

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40 ns

0.00 ns

0.20 ns

1.00 ns

0.90 ns

1.00 ns

t

RST, GOE

t , t

Using LVCMOS2.5

standard

IN GCLK_IN

t

RST, GOE

t , t

Using LVCMOS3.3

standard

IN GCLK_IN

t

RST, GOE

t , t

IN GCLK_IN

Using PCI standard

t

RST, GOE

t , t

Using AGP-1X

standard

IN GCLK_IN

AGP_1X_in

SSTL3_I_in

SSTL3_II_in

SSTL2_I_in

SSTL2_II_in

CTT33_in

t

RST, GOE

t , t

Using SSTL3_I

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL3_II

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL2_I

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL2_II

standard

IN GCLK_IN

t

RST, GOE

t , t

Using CTT3.3

standard

IN GCLK_IN

t

RST, GOE

t , t

Using CTT2.5

standard

IN GCLK_IN

CTT25_in

t

RST, GOE

t , t

Using HSTL_I

standard

IN GCLK_IN

HSTL_I_in

t

RST, GOE

t , t

Using HSTL_III

standard

IN GCLK_IN

HSTL_III_in

t

RST, GOE

t , t

IN GCLK_IN

GTL+_in

Using GTL+ standard

Using LVDS standard

-

1.00

0.50

1.10

-

1.00

0.50

1.10

-

1.00

0.50

1.10

-

1.00 ns

0.50 ns

1.10 ns

t

RST, GOE

LVDS_in

t

GCLK_IN

Using LVDS differen-

tial standard

LVPECL_D_in

t

Output Adders

IDO

Output conﬁgured for

slow slew rate

Slow Slew

t

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50 ns

0.80 ns

0.50 ns

0.10 ns

-0.10 ns

0.50 ns

EN, BUF

Output conﬁgured as

1.8V & 4mA Buffer

LVCMOS18_4mA_out

LVCMOS18_5mA_out

LVCMOS18_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 12mA Buffer

LVCMOS18_12mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 4mA Buffer

LVCMOS25_4mA_out

LVCMOS25_5mA_out

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 5.33mA Buffer

t

0.20 ns

Timing v.1.0

EN, DIS, BUF

Note: Open drain timing is the same as corresponding LVCMOS timing.

23

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B Timing Adders (Cont.)

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Output conﬁgured as

2.5V & 8mA Buffer

LVCMOS25_8mA_out

t

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00 ns

-0.10 ns

-0.20 ns

0.80 ns

0.20 ns

0.00 ns

-0.10 ns

EN, DIS, BUF

Output conﬁgured as

2.5V & 12mA Buffer

LVCMOS25_12mA_out t

LVCMOS25_16mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 4mA Buffer

LVCMOS33_4A_out

LVCMOS33_5mA_out

LVCMOS33_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 12mA Buffer

LVCMOS33_12mA_out t

LVCMOS33_16mA_out t

LVCMOS33_20mA_out t

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 20mA Buffer

t

-

-0.20

-

-0.20

-

-0.20

-

-0.20 ns

EN, DIS, BUF

PCI_out

t

Using PCI standard

EN, DIS, BUF

Using AGP-1X

standard

AGP_1X_out

t

EN, DIS, BUF

Using SSTL3_I

standard

SSTL3_I_out

SSTL3_II_out

SSTL2_I_out

SSTL2_II_out

CTT33_out

t

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50 ns

0.10 ns

0.50 ns

-0.10 ns

0.80 ns

0.20 ns

0.10 ns

EN, DIS, BUF

Using SSTL3_II

standard

t

EN, DIS, BUF

Using SSTL2_I

standard

t

EN, DIS, BUF

Using SSTL2_II

standard

t

EN, DIS, BUF

Using CCT3.3

standard

t

EN, DIS, BUF

Using CCT2.5

standard

CTT_25_out

HSTL_I_out

t

EN, DIS, BUF

Using HSTL_I

standard

t

EN, DIS, BUF

Using HSTL_III

standard

HSTL_III_out

GTL+_out

t

-

0.40

2.00

-

0.40

2.00

-

0.40

2.00

-

0.40 ns

2.00 ns

EN, DIS, BUF

t

Using GTL+ standard

EN, DIS, BUF

t

Input Adders

IOI

CLK0

CLK1

CLK2

CLK3

t

-

0.00

0.20

-

0.00

0.20

-

0.00

0.20

-

0.00 ns

0.20 ns

Timing v.1.0

GCLK_IN

Note: Open drain timing is the same as corresponding LVCMOS timing.

24

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B Timing Adders (Cont).

-4

-5

-75

-10

Adder Type

Base Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Additional Block Loading Adders

BLA

1

2

3

t

-

0.10

0.20

-

0.10

0.20

-

0.10

0.20

-

0.10

0.20

ns

ROUTE

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.1.0

25

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B Timing Adders

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Low Power Adder

-

1.00

-

1.00

-

1.00

-

1.00 ns

LP

ROUTE

t

Input Adders

IOI

t , t

,

Using LVCMOS1.8

standard

IN GCLK_IN

LVCMOS18_in

LVCMOS25_in

LVCMOS33_in

PCI_in

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40 ns

0.00 ns

0.20 ns

1.00 ns

0.90 ns

1.00 ns

t

RST, GOE

t , t

Using LVCMOS2.5

standard

IN GCLK_IN

t

RST, GOE

t , t

Using LVCMOS3.3

standard

IN GCLK_IN

t

RST, GOE

t , t

IN GCLK_IN

Using PCI standard

t

RST, GOE

t , t

Using AGP-1X

standard

IN GCLK_IN

AGP_1X_in

SSTL3_I_in

SSTL3_II_in

SSTL2_I_in

SSTL2_II_in

CTT33_in

t

RST, GOE

t , t

Using SSTL3_I

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL3_II

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL2_I

standard

IN GCLK_IN

t

RST, GOE

t , t

Using SSTL2_II

standard

IN GCLK_IN

t

RST, GOE

t , t

Using CTT3.3

standard

IN GCLK_IN

t

RST, GOE

t , t

Using CTT2.5

standard

IN GCLK_IN

CTT25_in

t

RST, GOE

t , t

Using HSTL_I

standard

IN GCLK_IN

HSTL_I_in

t

RST, GOE

t , t

Using HSTL_III

standard

IN GCLK_IN

HSTL_III_in

t

RST, GOE

t , t

IN GCLK_IN

GTL+_in

Using GTL+ standard

Using LVDS standard

-

1.00

0.50

1.10

-

1.00

0.50

1.10

-

1.00

0.50

1.10

-

1.00 ns

0.50 ns

1.10 ns

t

RST, GOE

LVDS_in

t

GCLK_IN

Using LVDS differen-

tial standard

LVPECL_D_in

t

Output Adders

IDO

Output conﬁgured for

slow slew rate

Slow Slew

t

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50 ns

0.80 ns

0.50 ns

0.10 ns

-0.10 ns

0.50 ns

EN, BUF

Output conﬁgured as

1.8V & 4mA Buffer

LVCMOS18_4mA_out

LVCMOS18_5mA_out

LVCMOS18_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 12mA Buffer

LVCMOS18_12mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 4mA Buffer

LVCMOS25_4mA_out

LVCMOS25_5mA_out

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 5.33mA Buffer

t

0.20 ns

Timing v.1.3

EN, DIS, BUF

Note: Open drain timing is the same as corresponding LVCMOS timing.

26

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B Timing Adders (Cont.)

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Output conﬁgured as

2.5V & 8mA Buffer

LVCMOS25_8mA_out

t

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00 ns

-0.10 ns

-0.20 ns

0.80 ns

0.20 ns

0.00 ns

-0.10 ns

EN, DIS, BUF

Output conﬁgured as

2.5V & 12mA Buffer

LVCMOS25_12mA_out t

LVCMOS25_16mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 4mA Buffer

LVCMOS33_4A_out

LVCMOS33_5mA_out

LVCMOS33_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 12mA Buffer

LVCMOS33_12mA_out t

LVCMOS33_16mA_out t

LVCMOS33_20mA_out t

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 20mA Buffer

t

-

-0.20

-

-0.20

-

-0.20

-

-0.20 ns

EN, DIS, BUF

PCI_out

t

Using PCI standard

EN, DIS, BUF

Using AGP-1X

standard

AGP_1X_out

t

EN, DIS, BUF

Using SSTL3_I

standard

SSTL3_I_out

SSTL3_II_out

SSTL2_I_out

SSTL2_II_out

CTT33_out

t

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50 ns

0.10 ns

0.50 ns

-0.10 ns

0.80 ns

0.20 ns

0.10 ns

EN, DIS, BUF

Using SSTL3_II

standard

t

EN, DIS, BUF

Using SSTL2_I

standard

t

EN, DIS, BUF

Using SSTL2_II

standard

t

EN, DIS, BUF

Using CCT3.3

standard

t

EN, DIS, BUF

Using CCT2.5

standard

CTT_25_out

HSTL_I_out

t

EN, DIS, BUF

Using HSTL_I

standard

t

EN, DIS, BUF

Using HSTL_III

standard

HSTL_III_out

GTL+_out

t

-

0.40

2.00

-

0.40

2.00

-

0.40

2.00

-

0.40 ns

2.00 ns

EN, DIS, BUF

t

Using GTL+ standard

EN, DIS, BUF

t

Input Adders

IOI

CLK0

CLK1

CLK2

CLK3

t

-

0.00

0.20

-

0.00

0.20

-

0.00

0.20

-

0.00 ns

0.20 ns

Timing v.1.3

GCLK_IN

Note: Open drain timing is the same as corresponding LVCMOS timing.

27

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B Timing Adders (Cont).

-4

-5

-75

-10

Adder Type

Base Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Additional Block Loading Adders

BLA

1

2

3

4

5

6

7

t

-

0.10

0.20

0.30

0.40

0.60

-

0.10

0.20

0.30

0.40

0.60

-

0.10

0.20

0.30

0.40

0.60

-

0.10

0.20

0.30

0.40

0.60

ns

ROUTE

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.1.3

28

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5384B Timing Adders

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Low Power Adder

-

1.00

-

1.00

-

1.00

-

1.00 ns

LP

ROUTE

t

Input Adders

IOI

LVCMOS18_in

LVCMOS25_in

LVCMOS33_in

PCI_in

t

Using LVCMOS1.8

standard

IN, GCLK_IN,

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40

0.00

0.20

1.00

0.90

1.00

-

0.40 ns

0.00 ns

0.20 ns

1.00 ns

0.90 ns

1.00 ns

t

RST, GOE

t

Using LVCMOS2.5

standard

IN, GCLK_IN,

t

RST, GOE

t

Using LVCMOS3.3

standard

IN, GCLK_IN,

t

RST, GOE

t

Using PCI standard

IN, GCLK_IN,

t

RST, GOE

AGP_1X_in

SSTL3_I_in

SSTL3_II_in

SSTL2_I_in

SSTL2_II_in

CTT33_in

t

Using AGP-1X

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL3_I

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL3_II

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL2_I

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL2_II

standard

IN, GCLK_IN,

t

RST, GOE

t

Using CTT3.3

standard

IN, GCLK_IN,

t

RST, GOE

CTT25_in

t

Using CTT2.5

standard

IN, GCLK_IN,

t

RST, GOE

HSTL_I_in

HSTL_III_in

GTL+_in

t

Using HSTL_I

standard

IN, GCLK_IN,

t

RST, GOE

t

Using HSTL_III

standard

IN, GCLK_IN,

t

RST, GOE

t

Using GTL+ standard

IN, GCLK_IN,

-

1.00

0.70

1.20

-

1.00

0.70

1.20

-

1.00

0.70

1.20

-

1.00 ns

0.70 ns

1.20 ns

t

RST, GOE

LVDS_in

t

Using LVDS standard

GCLK_IN

LVPECL_D_in

Using LVDS

differential standard

t

Output Adders

IDO

Slow Slew

t

Output conﬁgured for

slow slew rate

EN, BUF

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50 ns

0.80

LVCMOS18_4mA_out

LVCMOS18_5mA_out

LVCMOS18_8mA_out

t

Output conﬁgured as

1.8V & 4mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

1.8V & 5.33mA Buffer

EN, DIS, BUF

0.50 ns

0.10 ns

-0.10 ns

0.50 ns

t

Output conﬁgured as

1.8V & 8mA Buffer

EN, DIS, BUF

LVCMOS18_12mA_out t

t

Output conﬁgured as

1.8V & 12mA Buffer

EN, DIS, BUF

LVCMOS25_4mA_out

LVCMOS25_5mA_out

t

Output conﬁgured as

2.5V & 4mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

2.5V & 5.33mA Buffer

EN, DIS, BUF

0.20 ns

Timing v.1.0

Note: Open drain timing is the same as corresponding LVCMOS timing.

29

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5384B Timing Adders (Cont.)

-4

-5

-75

-10

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

LVCMOS25_8mA_out

t

Output conﬁgured as

2.5V & 8mA Buffer

EN, DIS, BUF

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00 ns

-0.10 ns

-0.20 ns

0.80 ns

0.20 ns

0.00 ns

-0.10 ns

LVCMOS25_12mA_out t

LVCMOS25_16mA_out t

t

Output conﬁgured as

2.5V & 12mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

2.5V & 16mA Buffer

EN, DIS, BUF

LVCMOS33_4mA_out

LVCMOS33_5mA_out

LVCMOS33_8mA_out

t

Output conﬁgured as

3.3V & 4mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

3.3V & 5.33mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

3.3V & 8mA Buffer

EN, DIS, BUF

LVCMOS33_12mA_out t

LVCMOS33_16mA_out t

LVCMOS33_20mA_out t

t

Output conﬁgured as

3.3V & 12mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

3.3V & 16mA Buffer

EN, DIS, BUF

t

Output conﬁgured as

3.3V & 20mA Buffer

EN, DIS, BUF

-

-0.20

-

-0.20

-

-0.20

-

-0.20 ns

PCI_out

t

Using PCI standard

EN, DIS, BUF

AGP_1X_out

t

Using AGP-1X

standard

EN, DIS, BUF

SSTL3_I_out

SSTL3_II_out

SSTL2_I_out

SSTL2_II_out

CTT33_out

t

Using SSTL3_I

standard

EN, DIS, BUF

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50 ns

0.10 ns

0.50 ns

-0.10 ns

0.80 ns

0.20 ns

0.10 ns

t

Using SSTL3_II

standard

EN, DIS, BUF

t

Using SSTL2_I

standard

EN, DIS, BUF

t

Using SSTL2_II

standard

EN, DIS, BUF

t

Using CCT3.3

standard

EN, DIS, BUF

CTT_25_out

HSTL_I_out

HSTL_III_out

GTL+_out

t

Using CCT2.5

standard

EN, DIS, BUF

t

Using HSTL_I

standard

EN, DIS, BUF

t

Using HSTL_III

standard

EN, DIS, BUF

-

0.40

2.00

-

0.40

2.00

-

0.40

2.00

-

0.40 ns

2.00 ns

t

Using GTL+ standard

EN, DIS, BUF

t

Input Adders

IOI

CLK0

CLK1

CLK2

CLK3

t

-

0.00

0.20

-

0.00

0.20

-

0.00

0.20

-

0.00 ns

0.20 ns

Timing v.1.0

GCLK_IN

Note: Open drain timing is the same as corresponding LVCMOS timing.

30

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5384B Timing Adders (Cont.)

-4

-5

-75

-10

Adder Type

Base Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Additional Block Loading Adders

BLA

1

t

-

0.20

0.40

0.60

0.80

1.00

1.10

1.20

-

0.20

0.40

0.60

0.80

1.00

1.10

1.20

-

0.20

0.40

0.60

0.80

1.00

1.10

1.20

-

0.20

0.40

0.60

0.80

1.00

1.10

1.20

ns

ROUTE

2

3

4

5

6

7

8

9

10

11

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.1.0

31

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Timing Adders

-45

-75

-10

-12

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Low Power Adder

-

1.00

-

1.00

-

1.00

-

1.00 ns

LP

ROUTE

t

Input Adders

IOI

t

Using LVCMOS1.8

standard

IN, GCLK_IN,

LVCMOS18_in

LVCMOS25_in

LVCMOS33_in

PCI_in

-

0.30

0.00

0.20

1.00

0.90

1.00

-

0.30

0.00

0.20

1.00

0.90

1.00

-

0.30

0.00

0.20

1.00

0.90

1.00

-

0.30 ns

0.00 ns

0.20 ns

1.00 ns

0.90 ns

1.00 ns

t

RST, GOE

t

Using LVCMOS2.5

standard

IN, GCLK_IN,

t

RST, GOE

t

Using LVCMOS3.3

standard

IN, GCLK_IN,

t

RST, GOE

t

IN, GCLK_IN,

Using PCI standard

t

RST, GOE

t

Using AGP-1X

standard

IN, GCLK_IN,

AGP_1X_in

SSTL3_I_in

SSTL3_II_in

SSTL2_I_in

SSTL2_II_in

CTT33_in

t

RST, GOE

t

Using SSTL3_I

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL3_II

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL2_I

standard

IN, GCLK_IN,

t

RST, GOE

t

Using SSTL2_II

standard

IN, GCLK_IN,

t

RST, GOE

t

Using CTT3.3

standard

IN, GCLK_IN,

t

RST, GOE

t

Using CTT2.5

standard

IN, GCLK_IN,

CTT25_in

t

RST, GOE

t

Using HSTL_I

standard

IN, GCLK_IN,

HSTL_I_in

t

RST, GOE

t

Using HSTL_III

standard

IN, GCLK_IN,

HSTL_III_in

t

RST, GOE

t

IN, GCLK_IN,

GTL+_in

Using GTL+ standard

Using LVDS standard

-

1.00

1.50

-

1.00

1.50

-

1.00

1.50

-

1.00 ns

1.50 ns

t

RST, GOE

LVDS_in

t

GCLK_IN

Using LVDS

differential standard

LVPECL_D_in

t

Output Adders

IOO

Output conﬁgured for

slow slew rate

Slow Slew

t

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50

0.80

0.50

0.10

-0.10

0.50

0.20

-

1.50 ns

0.80 ns

0.50 ns

0.10 ns

-0.10 ns

0.50 ns

EN, BUF

Output conﬁgured as

1.8V & 4mA Buffer

LVCMOS18_4mA_out

LVCMOS18_5mA_out

LVCMOS18_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

1.8V & 12mA Buffer

LVCMOS18_12mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 4mA Buffer

LVCMOS25_4mA_out

LVCMOS25_5mA_out

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 5.33mA Buffer

t

0.20 ns

Timing v.1.1

EN, DIS, BUF

Note: Open drain timing is the same as corresponding LVCMOS timing.

32

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Timing Adders (Cont.)

-45

-75

-10

-12

Adder

Type

Base

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Output conﬁgured as

2.5V & 8mA Buffer

LVCMOS25_8mA_out

t

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00

-0.10

-0.20

0.80

0.20

0.00

-0.10

-

0.00 ns

-0.10 ns

-0.20 ns

0.80 ns

0.20 ns

0.00 ns

-0.10 ns

EN, DIS, BUF

Output conﬁgured as

2.5V & 12mA Buffer

LVCMOS25_12mA_out t

LVCMOS25_16mA_out t

t

EN, DIS, BUF

Output conﬁgured as

2.5V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 4mA Buffer

LVCMOS33_4mA_out

LVCMOS33_5mA_out

LVCMOS33_8mA_out

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 5.33mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 8mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 12mA Buffer

LVCMOS33_12mA_out t

LVCMOS33_16mA_out t

LVCMOS33_20mA_out t

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 16mA Buffer

t

EN, DIS, BUF

Output conﬁgured as

3.3V & 20mA Buffer

t

-

-0.20

-

-0.20

-

-0.20

-

-0.20 ns

EN, DIS, BUF

PCI_out

t

Using PCI standard

EN, DIS, BUF

Using AGP-1X

standard

AGP_1X_out

t

EN, DIS, BUF

Using SSTL3_I

standard

SSTL3_I_out

SSTL3_II_out

SSTL2_I_out

SSTL2_II_out

CTT33_out

t

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50

0.10

0.50

-0.10

0.80

0.20

0.10

-

0.50 ns

0.10 ns

0.50 ns

-0.10 ns

0.80 ns

0.20 ns

0.10 ns

0.50 ns

EN, DIS, BUF

Using SSTL3_II

standard

t

EN, DIS, BUF

Using SSTL2_I

standard

t

EN, DIS, BUF

Using SSTL2_II

standard

t

EN, DIS, BUF

Using CCT3.3

standard

t

EN, DIS, BUF

Using CCT2.5

standard

CTT_25_out

HSTL_I_out

t

EN, DIS, BUF

Using HSTL_I

standard

t

EN, DIS, BUF

Using HSTL_III

standard

HSTL_III_out

GTL+_out

t

-

0.50

2.00

-

0.50

2.00

-

0.50

2.00

-

EN, DIS, BUF

t

Using GTL+ standard

2.00 ns

Timing v.1.1

EN, DIS, BUF

Note: Open drain timing is the same as corresponding LVCMOS timing.

33

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Timing Adders (Cont.)

-45

-75

-10

-12

Adder

Type

Base Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Adders

IOI

CLK0

CLK1

CLK2

CLK3

t

-

0.00

0.20

-

0.00

0.20

-

0.00

0.20

-

0.00

0.20

ns

GCLK_IN

t

Additional Block Loading Adders

BLA

1

t

-

0.30

0.70

0.90

1.10

1.20

1.30

1.50

1.60

1.80

1.90

2.10

2.40

2.60

2.90

3.00

-

0.30

0.70

0.90

1.10

1.20

1.30

1.50

1.60

1.80

1.90

2.10

2.40

2.60

2.90

3.00

-

0.30

0.70

0.90

1.10

1.20

1.30

1.50

1.60

1.80

1.90

2.10

2.40

2.60

2.90

3.00

-

0.30

0.70

0.90

1.10

1.20

1.30

1.50

1.60

1.80

1.90

2.10

2.40

2.60

2.90

3.00

ns

ROUTE

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.1.1

Boundary Scan Timing Speciﬁcations

Symbol

Parameter

TCK [BSCAN test] clock pulse width

Min.

125

62.5

25

Max.

—

Units

ns

t

BTCP

TCK [BSCAN test] pulse width high

TCK [BSCAN test] pulse width low

TCK [BSCAN test] setup time

—

ns

BTCH

BTCL

—

ns

—

ns

BTSU

TCK [BSCAN test] hold time

25

—

ns

BTH

TCK [BSCAN test] rise and fall time

TAP controller falling edge of clock to valid output

50

—

mV/ns

ns

BRF

—

25

—

BTCO

BTOZ

TAP controller falling edge of clock to data output disable

TAP controller falling edge of clock to data output enable

BSCAN test Capture register setup time

—

ns

—

ns

BTVO

25

ns

BVTCPSU

BTCPH

BTUCO

BTUOZ

BTUOV

BSCAN test Capture register hold time

25

—

ns

BSCAN test Update reg, falling edge of clock to valid output

BSCAN test Update reg, falling edge of clock to output disable

BSCAN test Update reg, falling edge of clock to output enable

—

50

ns

—

ns

—

ns

34

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Power Consumption

ispMACH 5000B Typical I_CCvs. Frequency

600

500

400

300

200

100

ispMACH 5512B (High Power Mode)

ispMACH 5384B (High Power Mode)

ispMACH 5512B (Low Power Mode)

ispMACH 5384B (Low Power Mode)

ispMACH 5256B (High Power Mode)

ispMACH 5256B (Low Power Mode)

ispMACH 5128B (High Power Mode)

ispMACH 5128B (Low Power Mode)

0

50

100

150

200

250

300

f_MAX(MHz)

Note: The devices are configured with maximum number of

16-bit counters, typical current at 2.5V, 25°C.

Power Estimation Coefﬁcients

Device

K0

K1

K2

K3

K4

I

(mA)

I

(mA)

DC

DCO

ispMACH 5128B

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

0.0055

0.005

0.0065

0.008

0.273

0.091

0.075

10.6

1.2

0.2215

10.5

18.4

22.9

1.2

Note: For further information about the use of these coefﬁcients, refer to Lattice technical note number TN1023, Power Estimation in ispMACH

5000B Devices.

The device power, I

is calculated from the following equation:

DEVICE,

I

= I

+ I

DEVICE

DEVICE-AC DEVICE-DC

Each term in I

is further deﬁned as:

DEVICE

I

= F

[(K0 * PT ) + (K1 * PT ) + K2 * GRP

)]

DEVICE-AC

DEVICE-DC

AVE

HP

LP

LINES

= K3 * PT + K4 * PT + I + I

HP

LP

DC

DCO

where:

PT = Number of product terms in high power

HP

PT = Number of product terms in low power

LP

F

= Average output frequency of switching product terms in MHz

AVE

K0 = average current per product term in high power/MHz

K1 = average current per product term in low power/MHz

K2 = average current per GRP line/MHz

K3 = DC current per product term in high power

K4 = DC current per product term in low power

I

= Static Device Current

DC

= Static I/O Bank Current

DCO

I

estimates are based on typical conditions (V = 2.5V, 25°C). These values are for estimates only. Since the

CC

value of I is sensitive to operating conditions and the program in the device, the actual I should be veriﬁed.

CC

35

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Switching Test Conditions

Figure 9 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance, volt-

age, and other test conditions are shown in Table 3.

Figure 9. Output Test Load, LVTTL and LVCMOS Standards

V

CCO

R

1

2

Test

Point

DUT

R

^C*

L

*C includes Test Fixture and Probe Capacitance.

L

0213A/ispm5kb

Table 3.Test Fixture Required Components

Test Condition

R

C

Timing Ref.

/2

V

CCO

1

2

L

Default LVCMOS 2.5 I/O (L -> H, H -> L)

188

35pF

V

2.3V

CCO

LVCMOS 3.3 = 1.5V

LVCMOS 3.3 = 3.0V

Other LVCMOS Settings (L -> H, H -> L)

∞

35pF

LVCMOS 2.5 = V

LVCMOS 1.8 = V

/2

LVCMOS 2.5 = 2.3V

CCO

LVCMOS 1.8 = 1.65V

Default LVCMOS 2.5 I/O (Z -> H)

Default LVCMOS 2.5 I/O (Z -> L)

Default LVCMOS 2.5 I/O (H -> Z)

Default LVCMOS 2.5 I/O (L -> Z)

∞

188

∞

35pF

5pF

V

/2

2.3V

CCO

188

∞

188

∞

- 0.15

+ 0.15

OH

OL

188

5pF

Output test conditions for all other interfaces are determined by the respective standards.

36

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Signal Descriptions

Signal Names

Description

TMS

Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine.

Input - This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state machine.

Input - This pin is the IEEE 1149.1 Test Data In pin, used to load data.

TCK

TDI

TDO

Output - This pin is the IEEE 1149.1 Test Data Out pin used to shift data out.

Input - Test Output Enable pin. TOE tristates all I/O pins when a logic low is driven.

Input - These two pins are the Global Output Enable input pins.

TOE

GOE0, GOE1

Dedicated Reset Input - This pin resets all registers in the devices. The global polarity (active high or low

input) for this pin is selectable.

RESETB

yzz

Input/Output – These are the general purpose I/O used by the logic array. y is the GLB reference (alpha)

and z is the macrocell reference (numeric). z: 0-31

ispMACH 5128B

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Ground

y: A-D, z: 0-31

y: A-H, z: 0-31

y: A-L, z: 0-31

y: A-P, z: 0-31

GND

NC

No connect

V

Vcc - These are the power supply pins for the logic core.

CC

GCLK0, GCLK1, Inputs - These pins are dedicated CLK inputs.

GCLK2, GCLK3

V

, V

,

Inputs - These are the reference supplies for the I/O banks.

REF0 REF1

, V

REF2 REF3

V

, V

,

V

- These are the V supplies for each I/O bank.

CCO0 CCO1

CC

, V

CCO2 CCO3

37

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5000B Power Supply and NC Connections

Signal

VCC

128-Pin TQFP^1,2

208-Pin PQFP^1,2

256-Ball fpBGA³

484-Ball fpBGA³

13, 45, 77, 109

11, 48, 74, 115, 152,

178

F8, F9, H6, H11, J6, J11, L8, B2, B6, B17, B21, C9, C14, E5, E18,

L9

F2, F21, J3, J20, P3, P20, U2, U21,

Y9, Y14, AA2, AA6, AA17, AA21

VCCO0

5, 120

5256B: 18, 189, 203

C3, C7, G3

B5, D7, E2, E6, E9, F5, G4, J5

5384B/5512B: 7, 18,

189, 203

VCCO1

VCCO2

28, 41

56, 69

41, 56, 70

K3, P3, P7

P5, U5, V6, V9, Y3,

5256B: 85, 99, 122

K14, P10, P14

P18, U18, V14, V17, Y20,

5384B/5512B: 85, 99,

109, 122

VCCO3

92, 105

145, 160, 174

C10, C14, G14

B18, D16, E14, E17, E21, F18, G19,

J18

VREF0

VREF1

VREF2

VREF3

GND

124

37

193

66

E7

A9

M7

R13

A8

AA10

61

90

AA13

100

169

A15

6, 20, 27, 40, 52, 5256B: 19, 20, 39, 40, A1, C5, C12, E3, E14, G7,

57, 70, 84, 91,

104, 116, 121

A1, A22, C3, C20, D4, D19, E7, E16,

55, 69, 81, 86, 100,

123, 124, 143, 144,

159, 173, 185, 190,

204

G8, G9, G10, H8, H9, H10, G5, G7, G8, G9, G10, G11, G12, G13,

J7, J8, J9, K7, K8, K9, K10, G14, G15, G16, G18, H7, H8, H9, H10,

M3, M14, P5, P12

H11, H12, H13, H14, H15, H16, J7, J8,

J9, J10, J11, J12, J13, J14, J15, J16,

K7, K8, K9, K10, K11, K12, K13, K14,

K15, K16, L8, L9, L10, L11, L12, L13,

L14, L15, M7, M8, M9, M10, M11,

M12, M13, M14, M15, M16, N7, N8,

N9, N10, N11, N12, N13, N14, N15,

N16, P7, P8, P9, P10, P11, P12, P13,

P14, P15, P16, R7, R8, R9, R10, R11,

R12, R13, R14, R15, R16, T4, T7, T8,

T9, T10, T11, T12, T13, T14, T15, T16,

T19, W7, W16, AB1, AB22

5384B/5512B: 8, 19,

20, 39, 40, 55, 69, 81,

86, 100, 110, 123, 124,

143, 144, 159, 173,

185, 190, 204

NC⁴

5128B: 45, 52,

109, 116

5256B: 1, 2, 7, 8, 101, 5256B: A11, A12, A13, A14, 5512B: A6, A7, A8, A19, A20, A21, B7,

102, 103, 104, 105,

106, 109, 110, 205,

206, 207, 208

B1, B2, B11, B12, B13, B16, B8, B19, B20, B22, C7, C8, C10, C16,

C1, C2, C13, C15, C16, D14, C17, D9, D15, D18, E3, E10, F1, F3,

D15, D16, E13, E15, F6, F7, F4, F9, F10, F16, F17, F19, F20, G1,

F10, F11, G6, G11, H1, H7, G2, G3, G6, G17, G20, G21, G22, H1,

H16, J1, J10, K6, K11, L5,

L6, L7, L10, L11, M4, N2,

N3, N4, N5, P1, P2, P4, P6,

P15, P16, R4, R5, R6, R15,

R16, T4, T5, T6

H2, H5, H6, H17, H18, H19, H20, H21,

H22, L6, L7, L16, N18, P4, AA1

5384B: A11, A12, A13, B13,

C13, H1, H7, H16, J1, J10,

P6, R5, R6, T5, T6

5512B: H1, H7, H16, J1, J10

1. All grounds must be electrically connected at the board level.

2. Not all grounds internally connected within the device. Pin orientation follows the conventional order from pin 1 marking of the top side view

and counter-clockwise.

3. Balls for ground (GND), VCC and VCCO signals are connected within the substrate. Pin orientation A1 starts from the upper left corner of

the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.

4. No connects should not be connected to any active signals, VCC, VCCO, or GND.

38

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP

ispMACH 5128B

ispMACH 5256B

Bank

Pin Number

Number

GLB/MC/Pad

1

0

-

D12

H16

2

D10

H14

3

D9

H12

4

D8

H10

5

VCCO (Bank 0)

6

GND (Bank 0)

7

D6

H8

8

D5

H6

9

D4

H5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

D2

H4

D1

H2

D0

H0

VCC

0

1

-

GCLK0

GCLK1

TDI

-

TMS

-

TCK

-

TDO

-

GND

1

A0

A1

A2

A4

A5

A6

A8

GND (Bank 1)

VCCO (Bank 1)

A10

GND (Bank 1)

VCCO (Bank 1)

A8

A9

A10

A12

A14

A12

A16

A14

A20

A16

B10

A17

B12

A18

B14

A20/VREF1

A21

B16/VREF1

B18

A22

B20

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

39

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.)

ispMACH 5128B

ispMACH 5256B

Bank

Pin Number

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

Number

GLB/MC/Pad

B21

1

-

A24

A25

B22

A26

B24

NC

VCC

1

2

-

A28

B26

A29

B28

A30

B30

B0

C0

B1

C2

B2

C4

NC

GND

2

-

B4

C5

B5

C6

B6

C8

VCCO (Bank 2)

GND (Bank 2)

B8

VCCO (Bank 2)

GND (Bank 2)

C10

B9

C12

B10

C14

B12/VREF2

B13

C16/VREF2

C18

B14

C20

B16

D10

B18

D14

B20

D16

B21

D18

B22

D20

VCCO (Bank 2)

GND (Bank 2)

B24

VCCO (Bank 2)

GND (Bank 2)

D21

B25

D22

B26

D24

B28

D26

B29

D28

B30

D30

VCC

-

TOE

2

3

-

RESETB

GOE0

GOE1

GCLK2

GCLK3

GND

RESETB

GOE0

GOE1

GCLK2

GCLK3

GND

40

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.)

ispMACH 5128B

ispMACH 5256B

Bank

Pin Number

85

Number

GLB/MC/Pad

3

-

C30

E30

86

C29

E28

87

C28

E26

88

C26

E24

89

C25

E22

90

C24

E21

91

GND (Bank 3)

92

VCCO (Bank 3)

93

C22

E20

94

C21

E18

95

C20

E16

96

C18

E14

97

C16

E10

98

C14

F20

99

C13

F18

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

C12/VREF3

F16/VREF3

C10

F14

C9

F12

C8

F10

GND (Bank 3)

VCCO (Bank 3)

C6

F8

C5

F6

C4

F5

VCC

NC

3

0

-

C2

F4

C1

F2

C0

D30

F0

G30

D29

G28

D28

G26

NC

GND

0

D26

G24

D25

G22

D24

G21

VCCO (Bank 0)

GND (Bank 0)

D22

VCCO (Bank 0)

GND (Bank 0)

G20

D21

G18

D20/VREF0

D18

G16/VREF0

G14

D17

G12

41

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.)

ispMACH 5128B

GLB/MC/Pad

D16

ispMACH 5256B

Bank

Number

Pin Number

127

GLB/MC/Pad

G10

0

128

D14

H20

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

O30

1

2

3

4

5

6

0

NC

K14

K12

K10

K8

O28

H30

H28

H26

H24

O26

O24

K6

O22

K4

O20

VCCO

(Bank 0)

VCCO

(Bank 0)

7

8

0

NC

GND

(Bank 0)

GND

(Bank 0)

9

0

-

H22

H21

VCC

H20

H18

H16

H14

H12

H10

K2

K0

O18

O16

VCC

P22

P20

P18

P16

P14

P12

10

11

12

13

14

15

16

17

VCC

L22

L20

L18

L16

L14

L12

0

VCC

(Bank 0)

VCCO

(Bank 0)

VCCO

(Bank 0)

18

19

20

0

-

GND

(Bank 0)

GND

(Bank 0)

GND

(Bank 0)

0

21

22

23

24

25

26

27

28

29

30

31

32

0

1

-

H8

H6

L10

L8

P10

P8

H5

L6

P6

H4

L4

P4

H2

L2

P2

H0

L0

P0

GCLK0

GCLK1

TDI

GCLK0

GCLK1

TDI

GCLK0

GCLK1

TDI

-

TMS

TCK

TDO

TMS

TCK

TDO

TMS

TCK

TDO

-

42

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.)

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

33

34

35

36

37

38

1

A0

A2

A4

A5

A6

A8

A0

A2

A0

A2

A4

A6

A8

A10

GND

(Bank 1)

GND

(Bank 1)

GND

(Bank 1)

39

40

41

1

-

GND

VCCO

(Bank 1)

VCCO

(Bank 1)

VCCO

(Bank 1)

1

42

43

44

45

46

47

48

49

50

51

52

53

54

1

-

A10

A12

A14

A16

A18

A20

VCC

A21

A22

A24

A26

A28

A30

A12

A14

A16

A18

A20

A22

VCC

B12

B14

B16

B18

B20

B21

A12

A14

A16

A18

A20

A22

VCC

B12

B14

B16

B18

B20

B21

1

GND

(Bank 1)

GND

(Bank 1)

GND

(Bank 1)

55

56

1

VCCO

(Bank 1)

VCCO

(Bank 1)

VCCO

(Bank 1)

57

58

59

60

61

62

63

64

65

66

67

68

1

B0

B2

C0

C2

C20

C24

B4

C4

C26

B5

C5

C28

B6

C6

D0

B8

C8

D2

B10

C10

C12

C14

C16/VREF1

C18

C20

D4

B12

D6

B14

D8

B16/VREF1

B18

D10/VREF1

D12

B20

D16

GND

(Bank 1)

GND

(Bank 1)

GND

(Bank 1)

69

70

1

VCCO

(Bank 1)

VCCO

(Bank 1)

VCCO

(Bank 1)

43

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.)

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

B21

B22

B24

VCC

B26

B28

B30

C0

GLB/MC/Pad

C21

C22

C24

VCC

C26

C28

C30

D0

GLB/MC/Pad

D18

D20

D22

VCC

D24

D26

D28

E0

71

72

73

74

75

76

77

78

79

80

81

82

83

84

1

-

1

2

-

C2

D2

E2

C4

D4

E4

GND

C5

GND

D5

GND

E6

2

C6

D6

E8

C8

D8

E10

VCCO

(Bank 2)

VCCO

(Bank 2)

VCCO

(Bank 2)

85

86

2

GND

(Bank 2)

GND

(Bank 2)

GND

(Bank 2)

87

88

89

90

91

92

93

94

95

96

97

98

2

C10

C12

D10

D12

E12

E16

C14

D14

E18

C16/VREF2

C18

D16/VREF2

D18

E20/VREF2

E22

C20

D20

E24

C21

D21

E26

C22

D22

E28

C24

D24

F0

C26

D26

F2

C28

D28

F4

C30

D30

F6

VCCO

(Bank 2)

VCCO

(Bank 2)

VCCO

(Bank 2)

99

2

GND

(Bank 2)

GND

(Bank 2)

GND

(Bank 2)

100

101

102

103

104

105

106

107

108

2

NC

D0

D2

E4

E6

G4

G6

E8

G8

E10

E20

E22

E24

E26

G10

G20

G22

G24

G26

VCCO

(Bank 2)

VCCO

(Bank 2)

109

2

NC

44

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.)

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

GND

(Bank 2)

GND

(Bank 2)

110

2

NC

111

112

113

114

115

116

117

118

119

120

121

2

-

D4

D5

E28

E30

F0

G28

G30

H0

D6

D8

F2

H2

VCC

D10

D12

D14

D16

D18

D20

VCC

F8

VCC

H8

2

F10

F12

F14

F16

F18

H10

H12

H14

H16

H18

VCCO

(Bank 2)

VCCO

(Bank 2)

VCCO

(Bank 2)

122

123

124

2

-

GND

(Bank 2)

GND

(Bank 2)

GND

(Bank 2)

2

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

2

-

D21

D22

F20

F22

H20

H22

D24

F24

H24

D26

F26

H26

D28

F28

H28

D30

F30

H30

TOE

RESETB

GOE0

GOE1

GCLK2

GCLK3

I30

2

3

RESETB

GOE0

GOE1

GCLK2

GCLK3

E30

RESETB

GOE0

GOE1

GCLK2

GCLK3

G30

E28

G28

I28

E26

G26

I26

E24

G24

I24

E22

G22

I22

E21

G20

I20

GND

(Bank 3)

GND

(Bank 3)

GND

(Bank 3)

143

144

145

3

-

GND

VCCO

(Bank 3)

VCCO

(Bank 3)

VCCO

(Bank 3)

3

146

147

148

3

E20

E18

E16

G18

G16

G14

I18

I16

I14

45

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.)

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

G12

GLB/MC/Pad

149

150

151

152

153

154

155

156

157

158

3

-

E14

E12

E10

VCC

E8

I12

I10

G10

G8

I8

VCC

H18

VCC

J0

3

E6

H16

K30

K28

K26

K24

K22

E5

H14

E4

H12

E2

H10

E0

H8

GND

(Bank 3)

GND

(Bank 3)

GND

(Bank 3)

159

160

3

VCCO

(Bank 3)

VCCO

(Bank 3)

VCCO

(Bank 3)

161

162

163

164

165

166

167

168

169

170

171

172

3

F30

F28

I30

I28

L30

L28

F26

I26

L26

F24

I24

L24

F22

I22

L22

F21

I21

L21

F20

I20

L20

F18

I18

L18

F16/VREF3

F14

I16/VREF3

I14

L16/VREF3

L14

F12

I12

L12

F10

I10

L10

GND

(Bank 3)

GND

(Bank 3)

GND

(Bank 3)

173

174

3

VCCO

(Bank 3)

VCCO

(Bank 3)

VCCO

(Bank 3)

175

176

177

178

179

180

181

182

183

184

185

186

187

188

3

-

F8

F6

I8

I6

L8

L6

F5

I5

L5

VCC

F4

VCC

I4

VCC

L4

3

0

-

F2

I2

L2

F0

I0

L0

G30

G28

G26

GND

G24

G22

G21

J30

J28

J26

GND

J24

J22

J21

M30

M28

M26

GND

M24

M22

M21

0

46

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.)

ispMACH 5256B

ispMACH 5384B

ispMACH 5512B

Bank

Number

GLB/MC/Pad

VCCO

(Bank 0)

VCCO

(Bank 0)

VCCO

(Bank 0)

189

190

0

GND

(Bank 0)

GND

(Bank 0)

GND

(Bank 0)

191

192

193

194

195

196

197

198

199

200

201

202

0

G20

G18

G16/VREF0

G14

G12

G10

G8

J20

M20

M18

M16/VREF0

M14

M12

M10

M8

J18

J16/VREF0

J14

J12

J10

J8

G6

J6

M6

G5

J5

M5

G4

J4

M4

G2

J2

M2

G0

J0

M0

VCCO

(Bank 0)

VCCO

(Bank 0)

VCCO

(Bank 0)

203

204

0

GND

(Bank 0)

GND

(Bank 0)

GND

(Bank 0)

205

206

207

208

0

NC

K26

K24

K22

K20

N8

N6

N5

N4

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

0

-

VCCO (Bank 0)

-

GND (Bank 0)

VCC

GND

NC

GND (Bank 0)

VCC

GND

K26

GND (Bank 0)

VCC

GND

N8

-

B2

B1

C2

C1

F7

F6

E5

D4

D3

D2

0

NC

K24

N6

NC

K22

N5

NC

K20

N4

NC

K14

O30

NC

K12

O28

H30

K10

O26

H28

K8

O24

H26

K6

O22

H24

K4

O20

47

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

NC

GND

-

NC

VCC

-

0

-

VCCO (Bank 0)

-

H22

GND (Bank 0)

D1

E4

G6

F5

E2

E1

F4

F3

F2

-

K2

O18

O16

H21

K0

NC

L30

P30

H20

L22

P22

H18

L20

P20

H16

L18

P18

H14

L16

P16

H12

L14

P14

H10

L12

P12

GND

VCC

VCCO (Bank 0)

GND (Bank 0)

H8

GND

VCC

VCCO (Bank 0)

GND (Bank 0)

P10

-

VCC

-

0

1

-

VCCO (Bank 0)

-

GND (Bank 0)

G5

G4

F1

G2

G1

H5

H1

H7

H4

J4

H3

H2

J3

J1

J2

-

L10

L8

H6

P8

H5

L6

P6

H4

L4

P4

H2

L2

P2

H0

L0

P0

NC

GCLK0

GCLK1

TDI

GCLK0

GCLK1

TDI

GCLK0

GCLK1

TDI

-

TMS

TCK

NC

TMS

TCK

NC

TMS

TCK

NC

-

1

-

TDO

VCC

GND

VCC

GND

A0

TDO

VCC

GND

VCC

GND

A0

TDO

VCC

GND

VCC

GND

A0

-

K1

K2

L1

J5

L2

K4

-

1

A2

A4

A5

A6

A8

A10

GND (Bank 1)

48

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

1

-

VCCO (Bank 1)

M1

L3

L4

K5

M2

N1

K6

L5

N2

L6

L7

-

A10

A12

A14

A16

A18

A20

NC

A12

A14

A16

A18

A20

A22

A26

NC

A28

NC

A30

NC

B0

NC

B2

NC

GND

-

NC

VCC

-

1

-

NC

GND (Bank 1)

-

NC

VCCO (Bank 1)

P1

P2

N3

R4

R1

T1

T2

R2

T3

R3

P4

-

NC

B4

NC

B5

NC

B6

NC

B8

A21

A22

A24

A26

A28

A30

NC

B12

B14

B16

B18

B20

B21

B22

GND (Bank 1)

VCCO (Bank 1)

VCC

GND

NC

GND (Bank 1)

-

VCCO (Bank 1)

-

VCC

-

GND

T4

N4

M4

N5

R5

T5

T6

R6

P6

-

1

B24

NC

B26

NC

B28

NC

B30

NC

C0

C2

NC

C12

NC

C16

NC

C18

NC

GND (Bank 1)

VCCO (Bank 1)

C0

GND (Bank 1)

VCCO (Bank 1)

C20

-

NC

M5

B0

49

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

T7

Bank Number

1

-

B2

C2

C24

T8

B4

C4

C26

R8

B5

C5

C28

M6

N6

B6

C6

D0

B8

C8

D2

R7

B10

C10

D4

T9

B12

C12

D6

T10

M7

N7

B14

C14

D8

B16/VREF1

C16/VREF1

D10/VREF1

B18

C18

D12

P8

B20

C20

D16

-

GND (Bank 1)

-

VCCO (Bank 1)

-

VCC

GND

B21

VCC

GND

C21

VCC

-

GND

R9

1

2

-

D18

N8

B22

C22

D20

M8

T11

T12

R10

P9

B24

C24

D22

B26

C26

D24

B28

C28

D26

B30

C30

D28

C0

D0

E0

R11

T13

N9

C2

D2

E2

C4

D4

E4

C5

D5

E6

M9

R12

-

C6

D6

E8

C8

D8

E10

GND

VCC

VCCO (Bank 2)

GND (Bank 2)

C10

GND

VCC

VCCO (Bank 2)

GND (Bank 2)

D10

GND

-

VCC

-

2

VCCO (Bank 2)

-

GND (Bank 2)

P11

N10

M10

R13

T14

R14

M11

N11

P13

T15

T16

N12

E12

E16

C12

D12

C14

D14

E18

C16/VREF2

C18

D16/VREF2

D18

E20/VREF2

E22

C20

D20

E24

C21

D21

E26

C22

D22

E28

C24

D24

F0

C26

D26

F2

C28

D28

F4

C30

D30

F6

50

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

GND

VCC

-

VCC

-

2

-

VCCO (Bank 2)

GND (Bank 2)

G4

-

GND (Bank 2)

NC

GND (Bank 2)

L10

L11

K11

R15

P15

R16

P16

N14

N13

-

E4

E6

NC

G6

NC

E8

G8

NC

E10

G10

NC

E18

G18

NC

E20

G20

NC

E22

G22

D0

E24

G24

D2

E26

G26

NC

VCCO (Bank 2)

GND (Bank 2)

VCC

VCCO (Bank 2)

GND (Bank 2)

VCC

-

NC

-

NC

-

NC

GND

E28

GND

N15

N16

M16

M12

M13

M15

L16

L15

L13

L14

-

2

-

D4

G28

D5

E30

G30

D6

F0

H0

D8

F2

H2

D10

F8

H8

D12

F10

H10

D14

F12

H12

D16

F14

H14

D18

F16

H16

D20

F18

H18

VCCO (Bank 2)

GND (Bank 2)

D21

VCCO (Bank 2)

GND (Bank 2)

F20

VCCO (Bank 2)

GND (Bank 2)

H20

-

L12

K13

K15

K16

J16

K12

-

D22

F22

H22

D24

F24

H24

D26

F26

H26

D28

F28

H28

D30

F30

H30

GND

VCC

GND

VCC

TOE

RESETB

GOE0

GOE1

GND

VCC

GND

-

VCC

-

GND

VCC

GND

-

VCC

J13

J14

J15

H15

-

TOE

2

RESETB

GOE0

GOE1

RESETB

GOE0

GOE1

51

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

H14

H13

H16

J10

J12

G16

G15

H12

G12

G13

-

Bank Number

2

3

-

GCLK2

GCLK3

NC

E30

G30

I30

E28

G28

I28

E26

G26

I26

E24

G24

I24

E22

G22

I22

E21

G20

I20

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

GND

E20

E18

E16

E14

E12

E10

NC

VCC

GND

G18

VCC

-

GND

F16

F15

F13

F14

F12

E16

G11

F11

F10

B11

E13

B12

-

3

-

I18

G16

I16

G14

I14

G12

I12

G10

I10

G8

I8

G6

I6

NC

G4

I4

NC

G2

I2

NC

G0

I0

NC

H30

J14

NC

H28

J12

NC

GND (Bank 3)

VCCO (Bank 3)

VCC

GND

H26

GND (Bank 3)

-

NC

VCCO (Bank 3)

-

NC

VCC

GND

J10

-

NC

E15

D15

D16

E12

A16

B15

A15

D13

B14

B16

-

3

-

NC

H24

J8

NC

H20

J2

E8

H18

J0

E6

H16

K30

E5

H14

K28

E4

H12

K26

E2

H10

K24

E0

H8

K22

NC

H6

K21

GND

VCC

GND (Bank 3)

GND

VCC

GND (Bank 3)

GND

VCC

GND (Bank 3)

-

3

52

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

3

-

VCCO (Bank 3)

C16

C15

D14

A14

C13

B13

-

NC

H5

K20

H4

K18

NC

H2

K16

NC

H0

K14

NC

K12

NC

K10

VCC

GND

NC

VCC

-

GND

A13

A12

A11

-

3

-

NC

K4

NC

K2

NC

K0

NC

GND (Bank 3)

-

NC

VCCO (Bank 3)

A10

C11

A9

D12

D11

B10

B9

E11

A8

D10

E10

A7

-

F30

I30

L30

F28

I28

L28

F26

I26

L26

F24

I24

L24

F22

I22

L22

F21

I21

L21

F20

I20

L20

F18

I18

L18

F16/VREF3

F14

I16/VREF3

L16/VREF3

I14

L14

F12

I12

L12

F10

I10

L10

GND (Bank 3)

VCCO (Bank 3)

VCC

GND

F8

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

GND

I8

VCC

GND

L8

-

C9

E9

D9

B8

A6

B7

C8

B6

A5

D8

E8

B5

-

3

0

-

F6

I6

L6

F5

I5

L5

F4

I4

L4

F2

I2

L2

F0

I0

L0

G30

G28

G26

G24

G22

G21

GND

J30

J28

J26

J24

J22

J21

GND

M30

M28

M26

M24

M22

M21

GND

53

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.)

ispMACH 5256B

GLB/MC/Pad

ispMACH 5384B

GLB/MC/Pad

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

VCC

-

0

-

VCCO (Bank 0)

-

GND (Bank 0)

M20

A4

D7

E7

C6

B4

A3

D6

E6

A2

B3

C4

D5

-

G20

G18

G16/VREF0

G14

G12

G10

G8

J20

J18

M18

J16/VREF0

J14

M16/VREF0

M14

J12

M12

J10

M10

J8

M8

G6

J6

M6

G5

J5

M5

G4

J4

M4

G2

J2

M2

G0

J0

M0

GND

VCC

GND

VCC

GND

VCC

-

ispMACH 5512B Logic Signal Connections: 484 fpBGA

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

0

-

VCCO (Bank 0)

GND (Bank 0)

-

VCC

-

GND

C2

C1

D1

D2

D3

E1

-

0

-

N8

N6

N5

N4

N2

N0

VCCO (Bank 0)

GND (Bank 0)

O30

-

J1

K1

H3

J2

H4

K2

-

O28

O26

O24

O22

O20

GND

-

VCC

-

0

VCCO (Bank 0)

54

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

0

-

GND (Bank 0)

J6

L1

K3

J4

L2

M1

K6

K4

L3

K5

-

O18

O16

O14

O12

O10

O8

O6

O4

O2

O0

GND

VCC

-

0

-

VCCO (Bank 0)

GND (Bank 0)

P30

-

N1

M2

P1

L4

N2

M3

L5

R1

P2

N3

-

P28

P26

P24

P22

P20

P18

P16

P14

P12

GND

VCC

-

0

1

-

VCCO (Bank 0)

GND (Bank 0)

P10

-

M6

M5

M4

N4

N6

N5

P6

R6

R2

T1

R3

R4

-

P8

P6

P4

P2

P0

GCLK0

GCLK1

TDI

-

TMS

-

TCK

-

TDO

-

VCC

-

GND

55

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

VCC

-

GND

-

VCC

-

GND

R5

T2

T5

T3

U1

U4

-

1

-

A0

A2

A4

A6

A8

A10

GND (Bank 1)

-

VCCO (Bank 1)

V1

U3

V5

V2

W1

V3

W2

Y1

Y2

W3

AA3

W4

-

A12

A14

A16

A18

A20

A22

A24

A26

A28

A30

B0

B2

GND

-

VCC

-

1

-

GND (Bank 1)

-

VCCO (Bank 1)

W5

Y4

T6

Y5

U6

AA4

W6

V4

U7

AB2

V7

AA5

-

B4

B5

B6

B8

B10

B12

B14

B16

B18

B20

B21

B22

GND (Bank 1)

VCCO (Bank 1)

VCC

-

56

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

AB3

Y6

-

GND

1

-

B24

B26

AB4

Y7

B28

B30

AB5

V8

C0

C2

AA7

Y8

C4

C8

C10

AB6

W8

AA8

Y10

-

C12

C16

C18

GND (Bank 1)

VCCO (Bank 1)

C20

-

U8

AB7

U9

AA9

W9

AB8

U10

AB9

V11

AA10

V10

AB10

-

C24

C26

C28

D0

D2

D4

D6

D8

D10/VREF1

D12

D16

GND (Bank 1)

VCCO (Bank 1)

VCC

-

GND

W10

W11

U11

AA11

V12

AB11

-

1

-

D18

D20

D22

D24

D26

D28

GND

-

VCC

-

VCC

-

GND

-

VCC

-

GND

57

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

W12

Y11

Y12

AB12

U12

AA12

-

Bank Number

2

-

E0

E2

E4

E6

E8

E10

GND

-

VCC

-

2

-

VCCO (Bank 2)

-

GND (Bank 2)

Y13

AB13

W13

AA13

U13

AB14

V13

AA14

U14

AB15

Y15

AB16

-

E12

E16

E18

E20/VREF2

E22

E24

E26

E28

F0

F2

F4

F6

VCCO (Bank 2)

-

GND (Bank 2)

AA15

W14

AB17

Y16

AA16

Y17

AB18

V15

AB19

W15

AB20

AA18

-

F8

F10

F12

F16

F18

F20

F22

F24

F26

F28

G0

G2

GND

-

VCC

-

2

VCCO (Bank 2)

-

GND (Bank 2)

U15

W17

U16

G4

G6

G8

58

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

AA19

V16

AB21

Y18

W18

AA20

W19

Y19

V19

-

Bank Number

2

-

G10

G12

G14

G16

G18

G20

G22

G24

G26

VCCO (Bank 2)

GND (Bank 2)

VCC

-

GND

Y21

W20

AA22

W21

Y22

V20

V21

W22

V18

U20

V22

U19

-

2

-

G28

G30

H0

H2

H4

H6

H8

H10

H12

H14

H16

H18

VCCO (Bank 2)

GND (Bank 2)

H20

-

U17

U22

T20

T21

T17

R20

-

H22

H24

H26

H28

H30

GND

-

VCC

-

GND

-

VCC

-

GND

-

VCC

T18

R19

R18

R17

-

TOE

2

RESETB

GOE0

GOE1

59

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

P17

P19

R21

T22

P21

N20

R22

N21

-

Bank Number

2

3

-

GCLK2

GCLK3

I30

I28

I26

I24

I22

I20

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

-

GND

M18

N19

P22

M20

N22

N17

M19

M21

L19

L20

-

3

-

I18

I16

I14

I12

I10

I8

I6

I4

I2

I0

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

-

GND

M17

M22

K20

L18

L21

K19

L22

K17

K22

L17

-

3

-

J30

J28

J26

J24

J22

J20

J18

J16

J14

J12

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

GND

J10

J8

-

K21

K18

J17

3

J6

60

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

J19

J22

J21

-

3

-

J4

J2

J0

GND (Bank 3)

-

VCCO (Bank 3)

F22

E22

E19

E20

D22

D21

-

K30

K28

K26

K24

K22

K21

GND

-

VCC

-

3

-

GND (Bank 3)

-

VCCO (Bank 3)

D20

C22

C18

C19

D17

C21

-

K20

K18

K16

K14

K12

K10

GND (Bank 3)

-

VCCO (Bank 3)

-

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

-

GND

B16

D14

A18

F15

A17

B15

-

3

K8

K6

K5

K4

K2

K0

GND (Bank 3)

-

VCCO (Bank 3)

A16

F14

C15

D13

E15

F13

B14

E13

L30

L28

L26

L24

L22

L21

L20

L18

61

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

A15

D12

A14

B13

-

3

-

L16/VREF3

L14

L12

L10

GND (Bank 3)

-

VCCO (Bank 3)

-

VCC

GND

L8

-

A13

B12

C13

A12

C12

A11

-

3

-

L6

L5

L4

L2

L0

GND

VCC

GND

VCC

GND

M30

-

D11

B11

E12

C11

F12

B10

-

0

-

M28

M26

M24

M22

M21

GND

VCC

VCCO (Bank 0)

GND (Bank 0)

M20

-

0

-

A10

D10

A9

E11

B9

F11

E8

A5

F8

C6

D8

A3

-

M18

M16/VREF0

M14

M12

M10

M8

M6

M5

M4

M2

M0

GND

62

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.)

ispMACH 5512B

GLB/MC/Pad

Ball Number

Bank Number

-

VCC

-

0

VCCO (Bank 0)

-

GND (Bank 0)

A2

A4

F7

C5

F6

B3

-

N30

N28

N26

N24

N22

N21

VCCO (Bank 0)

GND (Bank 0)

N20

-

B4

D5

B1

D6

C4

E4

N18

N16

N14

N12

N10

63

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Part Number Description

LC XXXXB – XX X XXX X

Device Family

Grade

C = Commercial

I = Industrial

Device Number

5128 = 128 Macrocells

5256 = 256 Macrocells

5384 = 384 Macrocells

5512 = 512 Macrocells

Pin/Ball Count

128

208

256

484

Supply Voltage

B = 2.5V

Package

T = TQFP

Q = PQFP

F = fpBGA

0212/ispm5b

Speed

3 = 3.0ns

4 = 4.0ns

45 = 4.5ns

5 = 5.0ns

75 = 7.5ns

10 = 10ns

12 = 12ns

Ordering Information

Commercial

Device

LC5128B

Part Number

LC5128B-3T128C

LC5128B-5T128C

LC5128B-75T128C

LC5256B-4T128C

LC5256B-4Q208C

LC5256B-4F256C

LC5256B-5T128C

LC5256B-5Q208C

LC5256B-5F256C

LC5256B-75T128C

LC5256B-75Q208C

LC5256B-75F256C

LC5384B-4Q208C

LC5384B-4F256C

LC5384B-5Q208C

LC5384B-5F256C

LC5384B-75Q208C

LC5384B-75F256C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

92

Grade

C

PD

128

256

384

2.5

3.0

5.0

7.5

4.0

5.0

7.5

4.0

5.0

7.5

TQFP

PQFP

fpBGA

TQFP

PQFP

fpBGA

TQFP

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

128

208

256

128

208

256

128

208

256

208

256

208

256

208

256

92

C

92

C

92

C

144

92

C

LC5256B

144

92

C

144

156

186

156

186

156

186

C

LC5384B

C

64

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

Commercial (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

156

196

256

156

196

256

156

196

256

Grade

PD

LC5512B-45Q208C

LC5512B-45F256C

LC5512B-45F484C

LC5512B-75Q208C

LC5512B-75F256C

LC5512B-75F484C

LC5512B-10Q208C

LC5512B-10F256C

LC5512B-10F484C

512

2.5

4.5

7.5

10

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

208

256

484

208

256

484

208

256

484

C

LC5512B

10

Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial

grade -5xxxxI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade.

Industrial

Device

LC5128B

Part Number

LC5128B-5T128I

LC5128B-75T128I

LC5128B-10T128I

LC5256B-5T128I

LC5256B-5Q208I

LC5256B-5F256I

LC5256B-75T128I

LC5256B-75Q208I

LC5256B-75F256I

LC5256B-10T128I

LC5256B-10Q208I

LC5256B-10F256I

LC5384B-5Q208I

LC5384B-5F256I

LC5384B-75Q208I

LC5384B-75F256I

LC5384B-10Q208I

LC5384B-10F256I

LC5512B-75Q208I

LC5512B-75F256I

LC5512B-75F484I

LC5512B-10Q208I

LC5512B-10F256I

LC5512B-10F484I

LC5512B-12Q208I

LC5512B-12F256I

LC5512B-12F484I

Macrocells Voltage

t

Package Pin/Ball Count

I/O

92

Grade

PD

128

256

384

512

2.5

5.0

7.5

10

TQFP

PQFP

fpBGA

TQFP

PQFP

fpBGA

TQFP

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

PQFP

fpBGA

128

208

256

128

208

256

128

208

256

208

256

208

256

208

256

208

256

484

208

256

484

208

256

484

I

92

5.0

7.5

10

92

144

92

LC5256B

LC5384B

LC5512B

144

92

10

144

156

186

156

186

156

186

156

196

256

156

196

256

156

196

256

10

5.0

7.5

10

7.5

10

12

Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial

grade -5xxxxI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade.

65

Lattice Semiconductor

ispMACH 5000B Family Data Sheet

For Further Information

In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 5000B family:

• sysIO Design and Usage Guidelines (TN1000)

• Power Estimation in ispMACH 5000B Devices (TN1023)

66


型号：	LC5512B-10F256C
厂家：	LATTICE SEMICONDUCTOR
描述：	EE PLD, 12ns, 512-Cell, CMOS, PBGA256, FBGA-256 时钟输入元件可编程逻辑
文件：	总66页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC5512B-10F256C [LATTICE]

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