LFE250E-7F256C_技术文档

LatticeECP2/M Family Data Sheet

DS1006 Version 03.3, August 2008

LatticeECP2/M Family Data Sheet

Introduction

June 2008

Data Sheet DS1006

■ Pre-Engineered Source Synchronous I/O

Features

• DDR registers in I/O cells

■ High Logic Density for System Integration

• Dedicated gearing logic

• 6K to 95K LUTs

• 90 to 583 I/Os

• Source synchronous standards support

– SPI4.2, SFI4 (DDR Mode), XGMII

– High Speed ADC/DAC devices

• Dedicated DDR and DDR2 memory support

– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)

• Dedicated DQS support

■ Embedded SERDES (LatticeECP2M Only)

• Data Rates 250 Mbps to 3.125 Gbps

• Up to 16 channels per device

PCI Express, Ethernet (1GbE, SGMII), OBSAI,

CPRI and Serial RapidIO.

■ Programmable sysI/O™ Buffer Supports

Wide Range Of Interfaces

■ sysDSP™ Block

• 3 to 42 blocks for high performance multiply and

accumulate

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 3/2/18 I, II

• Each block supports

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL

– One 36x36, four 18X18 or eight 9X9 multipliers

■ Flexible Memory Resources

• 55Kbits to 5308Kbits sysMEM™ Embedded

Block RAM (EBR)

■ Flexible Device Conﬁguration

• 1149.1 Boundary Scan compliant

• Dedicated bank for conﬁguration I/Os

• SPI boot ﬂash interface

– 18Kbit block

– Single, pseudo dual and true dual port

– Byte Enable Mode support

• Dual boot images supported

• 12K to 202Kbits distributed RAM

– Single port and pseudo dual port

■ sysCLOCK Analog PLLs and DLLs

• Two GPLLs and up to six SPLLs per device

– Clock multiply, divide, phase & delay adjust

– Dynamic PLL adjustment

• TransFR™ I/O for simple ﬁeld updates

• Soft Error Detect macro embedded

■ Optional Bitstream Encryption

(LatticeECP2/M “S”Versions Only)

■ System Level Support

• ispTRACY™ internal logic analyzer capability

• On-chip oscillator for initialization & general use

• 1.2V power supply

• Two general purpose DLLs per device

Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Guide

Device

ECP2-6

ECP2-12

12

ECP2-20

21

ECP2-35

32

ECP2-50

48

ECP2-70

68

LUTs (K)

6

12

Distributed RAM (Kbits)

EBR SRAM (Kbits)

24

42

64

96

136

55

221

12

276

15

332

18

387

21

1032

60

EBR SRAM Blocks

3

sysDSP Blocks

3

6

7

8

18

22

18x18 Multipliers

12

24

28

32

72

88

GPLL + SPLL + DLL

2+0+2

190

2+0+2

297

2+0+2

402

2+0+2

450

2+2+2

500

2+4+2

583

Maximum Available I/O

Packages and I/O Combinations

144-pin TQFP (20 x 20 mm)

208-pin PQFP (28 x 28 mm)

256-ball fpBGA (17 x 17 mm)

484-ball fpBGA (23 x 23 mm)

672-ball fpBGA (27 x 27 mm)

900-ball fpBGA (31 x 31 mm)

90

93

131

193

297

131

193

331

402

190

331

450

339

500

583

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

DS1006 Introduction_01.7

Introduction

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Guide

Device

ECP2M20

19

ECP2M35

34

ECP2M50

48

ECP2M70

67

ECP2M100

95

LUTs (K)

sysMEM Blocks (18kb)

Embedded Memory (Kbits)

Distributed Memory (Kbits)

sysDSP Blocks

66

114

225

246

288

1217

41

2101

71

4147

101

4534

145

5308

202

6

8

22

24

42

18x18 Multipliers

24

32

88

96

168

GPLL+SPLL+DLL

2+6+2

304

2+6+2

410

2+6+2

410

2+6+2

436

2+6+2

520

Maximum Available I/O

Packages and SERDES / I/O Combinations

256-ball fpBGA (17 x 17 mm)

484-ball fpBGA (23 x 23 mm)

672-ball fpBGA (27 x 27 mm)

900-ball fpBGA (31 x 31 mm)

1152-ball fpBGA (35 x 35 mm)

4 / 140

4 / 304

4 / 140

4 / 303

4 / 410

4 / 270

8 / 372

8 / 410

16 / 416

16 / 436

16 / 416

16 / 520

Introduction

The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced

DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an

economical FPGA fabric. This combination was achieved through advances in device architecture and the use of

90nm technology.

The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M

devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked

Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced conﬁgu-

ration support, including encryption (“S” versions only) and dual boot capabilities.

The LatticeECP2M device family features high speed SERDES with PCS.These high jitter tolerance and low trans-

mission jitter SERDES with PCS blocks can be conﬁgured to support an array of popular data protocols including

PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization

settings make SERDES suitable for chip to chip and small form factor backplane applications.

The ispLEVER^®design tool suite from Lattice allows large complex designs to be efﬁciently implemented using the

LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis

tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning tools to

place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing

and back-annotates it into the design for timing veriﬁcation.

Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2/M

family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of

their design, increasing their productivity.

1-2

LatticeECP2/M Family Data Sheet

Architecture

August 2008

Data Sheet DS1006

Architecture Overview

Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains

SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

ﬂexibility, allowing complex designs to be implemented quickly and efﬁciently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated

18K fast memory blocks. Each sysMEM block can be conﬁgured in a variety of depths and widths of RAM or ROM.

In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels.

Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic.

Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The

functionality of the SERDES/PCS Quads can be controlled by memory cells set during device conﬁguration or by

registers that are addressable during device operation. The registers in every quad can be programmed by a soft

IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners

of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of

the device can be conﬁgured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support

to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory

interfaces including DDR2.

Other blocks provided include PLLs, DLLs and conﬁguration functions. The LatticeECP2/M architecture provides

two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family

member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom-

most EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of

the other EBR/DSP rows.

The conﬁguration block that supports features such as conﬁguration bit-stream decryption, transparent updates

and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in

the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and ﬁve, which

allows for serial or parallel device conﬁguration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP2/M devices use 1.2V as their core voltage.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1006 Architecture_01.9

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-1. Simpliﬁed Block Diagram, ECP2-6 Device (Top Level)

Flexible sysIO Buffers:

LVCMOS, HSTL, SSTL,

LVDS, and other standards

Programmable

Function Units

(PFUs)

Pre-engineered source

synchronous support

• DDR1/2

• SPI4.2

• ADC/DAC devices

sysDSP Blocks

Multiply and

Accumulate Support

Flexible routing optimized

for speed, cost and routability

sysMEM Block RAM

18kbit Dual Port

Configuration logic, including

dual boot and encryption.

On-chip oscillator and

soft-error detection.

sysCLOCK PLLs and DLLs

Frequency Synthesis and

Clock Alignment

Configuration port

Figure 2-2. Simpliﬁed Block Diagram, ECP2M20 Device (Top Level)

SERDES

Flexible sysIO

Buffers:

LVCMOS, HSTL

Channel Channel

1

0

3

2

SSTL, LVDS

Programmable

Function Units

(PFUs)

Pre-Engineered

Source Synchronous

Support

• DDR1/2

• SPI4.2

DSP Blocks

• ADC/DAC devices

Multiply & Accumulate

Support

sysCLOCK SPLLs

Configuration

Logic, Including

dual boot and encryption,

and soft-error detection

Flexible Routing

optimized for speed,

cost & routability

sysCLOCK GPLLs

& GDLLs

sysMEM Block

RAM 18kbit Dual Port

Frequency Synthesis

& Clock Alignment

Configuration Port

On-Chip

Oscillator

2-2

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

PFU Blocks

The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF.

The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF

blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-

der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-

tions to and from PFU blocks are from routing.There are 50 inputs and 23 outputs associated with each PFU block.

Figure 2-3. PFU Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4

Slice 3

Slice 0

Slice 1

Slice 2

D

FF

To

Routing

Slice

Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For

PFUs, Slice 0 and Slice 2 can also be conﬁgured as distributed memory, a capability not available in the PFF.

Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they

enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such

as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro-

nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the

internal logic of the slice. The registers in the slice can be conﬁgured for positive/negative and edge triggered or

level sensitive clocks.

Table 2-1. Resources and Modes Available per Slice

PFU BLock

PFF Block

Slice

Slice 0

Slice 1

Slice 2

Slice 3

Resources

2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers

2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers

2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers

2 LUT4s Logic, ROM 2 LUT4s

Modes

Resources

Modes

Logic, Ripple, ROM

Logic, ROM

Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent

slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13

input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.

2-3

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-4. Slice Diagram

FCO To Different Slice/PFU

SLICE

OFX1

FXB

FXA

F1

A1

B1

C1

D1

CO

F/SUM

D

Q1

LUT4 &

CARRY*

FF*

To

CI

Routing

M1

M0

LUT5

From

Routing

Mux

OFX0

A0

CO

B0

C0

D0

F0

LUT4 &

CARRY*

F/SUM

Q0

D

FF*

CI

CE

CLK

LSR

* Not in Slice 3

FCI From Different Slice/PFU

For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data

WAD [A:D] is a 4bit address from slice 1 LUT input

Table 2-2. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Inter-slice signal

Data signals

Inter-PFU signal

M0

M1

Multipurpose Input

Clock Enable

Input

CE

Input

LSR

CLK

FC

Local Set/Reset

Input

System Clock

Fast Carry-in¹

Input

FXA

FXB

F0, F1

Q0, Q1

OFX0

OFX1

FCO

Intermediate signal to generate LUT6 and LUT7

LUT4 output register bypass signals

Input

Output

Register outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the slice

Slice 2 of each PFU is the fast carry chain output¹

1. See Figure 2-4 for connection details.

2. Requires two PFUs.

2-4

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are conﬁgured as 4-input combinatorial lookup tables. A LUT4 can have 16

possible input combinations. Any four input logic functions can be generated by programming this lookup table.

Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as

LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four

slices.

Ripple Mode

Ripple mode supports the efﬁcient implementation of small arithmetic functions. In ripple mode, the following func-

tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/Down counter with Async clear

• Up/Down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

– A greater-than-or-equal-to B

– A not-equal-to B

– A less-than-or-equal-to B

Ripple Mode includes an optional conﬁguration that performs arithmetic using fast carry chain methods. In this con-

ﬁguration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.

RAM Mode

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and

Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo

dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice

as the read-only port.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information about

using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this

data sheet.

Table 2-3. Number of Slices Required to Implement Distributed RAM

SPR 16X4

PDPR 16X4

Number of slices

3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

2-5

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

ROM Mode

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished

through the programming interface during PFU conﬁguration.

Routing

There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).

The x1 and x2 connections provide fast and efﬁcient connections in horizontal and vertical directions. The x2 and

x6 resources are buffered, allowing the routing of both short and long connections between PFUs.

The LatticeECP2/M family has an enhanced routing architecture that produces a compact design. The ispLEVER

design tool suite takes the output of the synthesis tool and places and routes the design. Generally, the place and

route tool is completely automatic, although an interactive routing editor is available to optimize the design.

sysCLOCK Phase Locked Loops (GPLL/SPLL)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2/M fam-

ily support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger

devices have two to six Standard PLLs (SPLLs) that have a subset of GPLL functionality.

General Purpose PLL (GPLL)

The architecture of the GPLL is shown in Figure 2-5. A description of the GPLL functionality follows.

CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the

Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/

logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-

quency.

The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can

either be programmed during conﬁguration or can be adjusted dynamically. The setup, hold or clock-to-out times of

the device can be improved by programming a delay in the feedback or input path of the PLL, which will advance or

delay the output clock with reference to the input clock.

Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator

(VCO) block. In this block the difference between the input path and feedback signals is used to control the fre-

quency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has locked

onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not

relock until the t

parameter has been satisﬁed. LatticeECP2/M devices have two dedicated pins on the left and

LOCK

right edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at

a lower frequency. This is a shared resource that can only be used by one PLL (GPLL or SPLL) per side.

The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at

higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider

takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block

adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle set-

ting can be pre-programmed or dynamically adjusted.

The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK)

and Phase/Duty select (CLKOS) are fed to the clock distribution network.

2-6

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-5. General Purpose PLL (GPLL) Diagram

Dynamic Adjustment

Dynamic Delay Adjustment

LOCK

CLKI

Input Clock

Divider

CLKOS

(CLKI)

(from routing or external pin)

Voltage

Controlled

Oscillator

Post Scalar

Phase/Duty

Divider

(CLKOP)

Delay

Adjust

Select

Feedback

Divider

CLKFB

CLKOP

CLKOK

(CLKFB)

from CLKOP (PLL internal),

from clock net(CLKOP) or from

a user clock (pin or logic)

RST

Secondary

Divider

RSTK

(CLKOK)

PLLCAP External Pin

(Optional External Capacitor)

Standard PLL (SPLL)

Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but

without delay adjustment capability. SPLLs also provide different parametric speciﬁcations. For more information,

please see the list of additional technical documentation at the end of this data sheet.

Table 2-4 provides a description of the signals in the GPLL and SPLL blocks.

Table 2-4. GPLL and SPLL Blocks Signal Descriptions

Signal

I/O

Description

CLKI

I

Clock input from external pin or routing

PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock

(PIN or logic)

CLKFB

I

RST

I

“1” to reset PLL counters, VCO, charge pumps and M-dividers

“1” to reset K-divider

RSTK

CLKOS

O

I

PLL output clock to clock tree (phase shifted/duty cycle changed)

PLL output clock to clock tree (no phase shift)

PLL output to clock tree through secondary clock divider

“1” indicates PLL LOCK to CLKI

CLKOP

CLKOK

LOCK

DDAMODE¹

DDAIZR¹

DDAILAG¹

DDAIDEL[2:0]¹

DPA MODES

DPHASE [3:0]

DDDUTY [3:0]

Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag

Dynamic Delay Input

I

DPA (Dynamic Phase Adjust/Duty Cycle Select) mode

DPA Phase Adjust inputs

I

—

DPA Duty Cycle Select inputs

1. These signals are not available in SPLL.

2-7

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Delay Locked Loops (DLL)

In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device.

CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes

block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference

input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated

from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI

or from tapped signal from the Delay chain.

The PFD produces a binary number proportional to the phase and frequency difference between the reference and

feedback signals. This binary output of the PFD is fed into a Arithmetic Logic Unit (ALU). Based on these inputs,

the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer-

ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL)

bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its

current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus.

The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the

outputs from the tapped delay line. The CLKOS has optional ﬁne phase shift and divider blocks to allow this output

to be further modiﬁed, if required. The ﬁne phase shift block allows the CLKOS output to phase shifted a further 45,

22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with

optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out-

put signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a

description of the DLL inputs and outputs.

The user can conﬁgure the DLL for many common functions such as time reference delay mode and clock injection

removal mode. Lattice provides primitives in its design tools for these functions. For more information about the

DLL, please see the list of additional technical documentation at the end of this data sheet.

Figure 2-6. Delay Locked Loop Diagram (DLL)

Delay Chain

Duty

Cycle

50%

ALUHOLD

Delay0

CLKOP

CLKOS

Delay1

Delay2

Output

Muxes

÷4

÷2

Duty

Cycle

50%

(from routing

or external pin)

Reference

Phase

Frequency

Detector

Delay3

Delay4

CLKI

Arithmetic

Logic Unit

÷4

÷2

from CLKOP (DLL

internal), from clock net

(CLKOP) or from a user

clock (pin or logic)

Feedback

LOCK

Lock

Detect

CLKFB

Digital

DCNTL

9

Control

Output

UDDCNTL

RSTN

2-8

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 2-5. DLL Signals

Signal

I/O

I

Description

CLKI

Clock input from external pin or routing

CLKFB

I

DLL feed input from DLL output, clock net, routing or external pin

Active low synchronous reset

RSTN

I

ALUHOLD

UDDCNTL

DCNTL[8:0]

CLKOP

I

Active high freezes the ALU

I

Synchronous enable signal (hold high for two cycles) from routing

Encoded digital control signals for PIC INDEL and slave delay calibration

The primary clock output

O

CLKOS

The secondary clock output with ﬁne phase shift and/or division by 2 or by 4

Active high phase lock indicator

LOCK

DLLDELA Delay Block

Closely associated with each DLL is a DLLDELA block.This is a delay block consisting of a delay line with taps and

a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-

cally this is the delay setting that the DLL uses to achieve phase alignment.This results in the delay providing a cal-

ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.

The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the

DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of

this data sheet.

Figure 2-7. DLLDELA Delay Block

PLL_PIO

CLKOP

Routing

CLKI

*

DLL_PIO

CLKOS

LOCK

DLL Block

CLKFB_CK

CLKOP

CLKFB

CLKI

GDLLFB_PIO

ECLK1

DCNTL[8:0]

CLKO

DLLDELA Delay Block

*

* Software selectable

PLL/DLL Cascading

LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-

cading. The allowable combinations are:

• PLL to PLL supported

• PLL to DLL supported

2-9

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

The DLLs in the LatticeECP2/M are used to shift the clock in relation to the data for source synchronous inputs.

PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL

and DLL blocks allows applications to utilize the unique beneﬁts of both DLLs and PLLs.

For further information about the DLL, please see the list of additional technical documentation at the end of this

data sheet.

GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only)

All LatticeECP2M devices contain two GDLLs, two GPLLs and six SPLLs, arranged in quadrants as shown in

Figure 2-8. In the LatticeECP2M devices GPLLs, SPLLs and GDLLs share their input pins. Figure 2-8 shows the

sharing of SPLLs input pin connections in the upper two quadrants and the sharing of GDLL, GPLL and SPLL input

pin connections in the lower two quadrants.

Figure 2-8. Sharing of PIO Pins by GPLL, SPLL and GDLL in LatticeECP2M Devices

SPLL_PIO

SPLL

Upper Left Quadrant

Lower Left Quadrant

Upper Right Quadrant

Lower Right Quadrant

GPLL_PIO

GDLL_PIO

SPLL_PIO

GPLL_PIO

GDLL_PIO

SPLL_PIO

GPLL

GDLL

SPLL

GDLL

SPLL

Clock Dividers

LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These

are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,

÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed

clock based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, DLL-

DELA delay blocks, routing or from an external clock input. The clock divider outputs serve as primary clock

sources and feed into the clock distribution network. The Reset (RST) control signal resets input and synchro-

nously forces all outputs to low.The RELEASE signal releases outputs synchronously to the input clock. For further

information about clock dividers, please see the list of additional technical documentation at the end of this data

sheet. Figure 2-9 shows the clock divider connections.

2-10

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-9. Clock Divider Connections

PLL PAD

Routing

CLKO

CLKOP (GPLL)

CLKOP (DLL)

CLKOS (GPLL)

CLKOS (DLL)

÷1

÷2

CLKDIV

÷4

RST

÷8

RELEASE

Clock Distribution Network

LatticeECP2/M devices have eight quadrant-based primary clocks and eight ﬂexible region-based secondary

clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high

speed interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These

clock inputs are fed throughout the chip via a clock distribution system.

Primary Clock Sources

LatticeECP2/M devices derive clocks from ﬁve primary sources: PLL (GPLL and SPLL) outputs, DLL outputs,

CLKDIV outputs, dedicated clock inputs and routing. LatticeECP2/M devices have two to eight sysCLOCK PLLs

and two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each

side of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated

clock inputs on the device. Figure 2-10 shows the primary clock sources.

2-11

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-10. Primary Clock Sources for ECP2-50

Clock Input

From Routing

PLL Input

SPLL

CLK

DIV

CLK

DIV

Clock

Input

Primary Clock Sources

to Eight Quadrant Clock Selection

Clock

Input

DLL Input

PLL Input

DLL Input

PLL Input

DLL

GPLL

From Routing

Clock Input

Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device

have six SPLLs.

2-12

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Secondary Clock/Control Sources

LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the

rest from routing. Figure 2-11 shows the secondary clock sources.

Figure 2-11. Secondary Clock Sources

Clock

Input

From

Routing Routing

From Routing

Clock Input

Secondary Clock Sources

Clock Input

From Routing

From

Routing Routing

Clock

Input

2-13

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Edge Clock Sources

Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be

driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.

Figure 2-12. Edge Clock Sources

Clock Input

From

Routing

Sources for top

edge clocks

From Routing

Clock

Input

Clock

Input

Clock

Input

Clock

Input

From Routing

Eight Edge Clocks (ECLK)

Two Clocks per Edge

From Routing

DLLDELA

DLL

Input

DLL

Input

DLL

PLL

Input

PLL

Input

GPLL

Sources for right edge clocks

Sources for left edge clocks

Sources for

bottom edge

clocks

From

Routing

From

Routing

Clock Input

2-14

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Primary Clock Routing

The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0

through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center

of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one

quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally

Figure 2-13. Per Quadrant Primary Clock Selection

Primary Clock Sources: PLLs + DLLs + CLKDIVs + PIOs + Routing

35:1

32:1

DCS

CLK6

8 Primary Clocks (CLK0 to CLK7) per Quadrant

DCS

CLK7

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-

gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the

DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7

(see Figure 2-13).

Figure 2-14 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information about the DCS, please see the list of additional technical documentation at

the end of this data sheet.

Figure 2-14. DCS Waveforms

CLK0

CLK1

SEL

DCSOUT

Secondary Clock/Control Routing

Secondary clocks in the LatticeECP2 devices are region-based resources. The beneﬁt of region-based resources

is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR/DSP rows and

a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns

with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-15 shows

2-15

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices

have four secondary clocks (SC0 to SC3) which are distrubed to every region.

The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the

secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for

high fan-out signals.

Figure 2-15. Secondary Clock Regions ECP2-50

I/O Bank 0

I/O Bank 1

Vertical Routing

Channel Regional

Boundary

Secondary Clock

Region 1

Secondary Clock

Region 5

DSP Row

Regional

Boundary

Secondary Clock

Region 2

Secondary Clock

Region 6

Secondary Clock

Region 3

Secondary Clock

Region 7

DSP Row

Regional

Boundary

Secondary Clock

Region 4

Secondary Clock

EBR Row

Regional

Boundary

Region 8

I/O Bank 5

I/O Bank 4

2-16

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-16. Secondary Clock Selection

Secondary Clock Feedlines: 8 PIOs + 16 Routing

24:1

SC0

SC1

SC2

SC3

SC4

SC5

SC6

SC7

4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region

Clock/Control

4 High Fan-out Data Signals (SC4 to SC7) per Region

High Fan-out Data

Slice Clock Selection

Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All

the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used

as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals

connected via routing.

If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3

does not have any registers; therefore it does not have the clock or control muxes.

Figure 2-17. Slice0 through Slice2 Clock Selection

Primary Clock

8

Secondary Clock

Clock to Slice

4

12

1

25:1

Routing

Vcc

2-17

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-18. Slice0 through Slice2 Control Selection

Secondary Clock

3

Slice Control

Routing

16:1

12

Vcc

1

Edge Clock Routing

LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the

implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-

ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the

CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides

of the device. Figure 2-19 shows the selection muxes for these clocks.

Figure 2-19. Edge Clock Mux Connections

Top and Bottom

Clock Input Pad

Routing

Edge Clocks

ECLK1/ ECLK2

(Both Mux)

Input Pad

GPLL Input Pad

Left and Right

Edge Clocks

ECLK1

DLL Output CLKOP

GPLL Output CLKOP

Routing

CLKO

Input Pad

GPLL Input Pad

Left and Right

Edge Clocks

ECLK2

DLL Output CLKOS

GPLL Output CLKOS

Routing

CLKO

2-18

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysMEM Memory

LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-

Kbit RAM with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by imple-

menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for

each data byte. EBR blocks provide byte-enable support for conﬁgurations with18-bit and 36-bit data widths.

Table 2-6. sysMEM Block Conﬁgurations

Memory Mode

Conﬁgurations

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

True Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

Pseudo Dual Port

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

EBR memory supports two forms of write behavior for single port or dual port operation:

1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2-19

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

2. Write Through – A copy of the input data appears at the output of the same port during a write cycle.This mode

is supported for all data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-

ated resets for both ports are as shown in Figure 2-20.

Figure 2-20. Memory Core Reset

SET

D

Q

Memory Core

Port A[17:0]

Port B[17:0]

L_CLR

Output Data

Latches

SET

D

Q

L_CLR

RSTA

RSTB

GSRN

Programmable Disable

For further information about the sysMEM EBR block, please see the the list of additional technical documentation

at the end of this data sheet.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the

EBR is always asynchronous.

Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f

(EBR clock). The reset

MAX

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

2-20

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

If an EBR is pre-loaded during conﬁguration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becomes active.

These instructions apply to all EBR RAM and ROM implementations.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

sysDSP™ Block

The LatticeECP2/M family provides a sysDSP block, making it ideally suited for low cost, high performance Digital

Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response

(FIR) ﬁlters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and

decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-

tiply-accumulators.

sysDSP Block Approach Compared to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with

ﬁxed data-width multipliers; this leads to limited parallelism and limited throughput.Their throughput is increased by

higher clock speeds. The LatticeECP2/M, on the other hand, has many DSP blocks that support different data-

widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can opti-

mize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-22 compares the fully

serial and the mixed parallel and serial implementations.

Figure 2-22. Comparison of General DSP and LatticeECP2/M Approaches

Operand

A

Operand

A

Operand

A

Operand

B

Operand

B

Operand

B

Operand

A

Operand

B

m/k

loops

Multiplier 0

x

Multiplier 1

M loops

Single

Multiplier

Multiplier k

x

Accumulator

(k adds)

+

Function implemented in

General purpose DSP

m/k

accumulate

Output

Function implemented

in LatticeECP2/M

sysDSP Block Capabilities

The sysDSP block in the LatticeECP2/M family supports four functional elements in three 9, 18 and 36 data path

widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)

of its operands.The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not

mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/

M family the DSP elements can be concatenated.

The resources in each sysDSP block can be conﬁgured to support the following four elements:

2-21

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

• MULT (Multiply)

• MAC (Multiply, Accumulate)

• MULTADDSUB (Multiply, Addition/Subtraction)

• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)

The number of elements available on each block depends in the width selected from the three available options x9,

x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.

Table 2-7 shows the capabilities of the block.

Table 2-7. Maximum Number of Elements in a Block

Width of Multiply

x9

8

x18

4

x36

1

MULT

MAC

2

—

MULTADDSUB

4

2

MULTADDSUBSUM

2

1

Some options are available in four elements. The input register in all the elements can be directly loaded or can be

loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-

tions are possible:

• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.

• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.

• The loading of operands can switch between parallel and serial operations.

2-22

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

MULT sysDSP Element

This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,

are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.

Figure 2-23 shows the MULT sysDSP element.

Figure 2-23. MULT sysDSP Element

Shift Register B In

Multiplicand

Shift Register A In

m

Multiplier

n

Multiplier

Input Data

Register A

m

n

m+n

(default)

m+n

n

x

Output

Input Data

Register B

Pipeline

Register

m

n

Signed A

Signed B

Input

Register

To

Multiplier

Input

Register

To

Multiplier

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Shift Register B Out

Shift Register A Out

2-23

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

MAC sysDSP Element

In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.

This accumulated value is available at the output. The user can enable the input and pipeline registers, but the out-

put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the

DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overﬂow signal is also avail-

able. The overﬂow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element.

Figure 2-24. MAC sysDSP

Serial Register B in

Multiplicand

Serial Register A in

Preload

m

Accumulator

m

n

Multiplier

n

m+n+16

(default)

Multiplier

m

n

Input Data

Register A

n

Output

m+n

m+n+16

(default)

x

(default)

Input Data

Register B

Pipeline

Register

n

Signed A

Signed B

Input

Register

Pipeline

Register

Overflow

signal

To Accumulator

Input

Register

Pipeline

Register

Input

Register

Pipeline

Register

Addn

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

Accumsload

Input

Register

Pipeline

Register

To Accumulator

RST(RST0,RST1,RST2,RST3)

SROB

SROA

2-24

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

MULTADDSUB sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25

shows the MULTADDSUB sysDSP element.

Figure 2-25. MULTADDSUB

Shift Register B In

Multiplicand A0

Shift Register A In

m

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

m

RST(RST0,RST1,RST2,RST3)

m

n

Multiplier B0

n

Multiplier

Input Data

Register A

m

n

x

m+n

Input Data

Register B

(default)

Pipeline

Register

m

Add/Sub

n

Multiplicand A1

Multiplier B1

m

Output

m+n+1

(default)

m+n+1

(default)

m

n

Multiplier

m+n

(default)

Input Data

Register A

m

n

x

Input Data

Register B

Pipeline

Register

m

n

Signed A

Input

Register

Pipeline

Register

Reg

Pipe

To Add/Sub

Signed B

Addn

Input

Register

Pipeline

Register

Reg

Pipe

Input

Register

Pipeline

Pipe

Register

Reg

Shift Register B Out

Shift Register A Out

2-25

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

MULTADDSUBSUM sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/

subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction

are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows

the MULTADDSUBSUM sysDSP element.

Figure 2-26. MULTADDSUBSUM

Shift Register B In

Multiplicand A0

Shift Register A In

m

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

m

n

Multiplier B0

n

Multiplier

Input Data

Register A

m

n

RST(RST0,RST1,RST2,RST3)

m+n

(default)

n

x

Input Data

Register B

Pipeline

Register

m

Add/Sub0

n

Multiplicand A1

Multiplier B1

m

m+n

(default)

m

n

Multiplier

Input Data

Register A

n

m+n+1

n

x

Input Data

Register B

SUM

Pipeline

Register

Output

Multiplicand A2

Multiplier B2

m

m+n+2

n

Multiplier

m

n

Input Data

Register A

m+n

(default)

n

x

m+n+1

Input Data

Register B

Pipeline

Register

m

Add/Sub1

n

Multiplicand A3

Multiplier B3

m

m+n

(default)

m

n

Multiplier

Input Data

Register A

m

n

x

Input Data

Register B

Pipeline

Register

m

n

Signed A

Signed B

Input

Register

Pipeline

Register

To Add/Sub0, Add/Sub1

Input

Register

Pipeline

Register

Addn0

Addn1

Input

Register

Pipeline

Register

To Add/Sub0

To Add/Sub1

Input

Register

Pipeline

Register

Shift Register B Out

Shift Register A Out

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset

and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)

2-26

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and

Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)

at each input register, pipeline register and output register.

Signed and Unsigned with Different Widths

The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For

unsigned operands, unused upper data bits should be ﬁlled to create a valid x9, x18 or x36 operand. For signed

two’s complement operands, sign extension of the most signiﬁcant bit should be performed until x9, x18 or x36

width is reached. Table 2-8 provides an example of this.

Table 2-8. Sign Extension Example

Unsigned

9-bit

Unsigned

18-bit

Two’s Complement

Signed 9 Bits

Two’s Complement

Signed 18 Bits

Number Unsigned

Signed

0101

+5

-6

0101

N/A

000000101

N/A

000000000000000101

N/A

000000101

111111010

000000000000000101

111111111111111010

1010

OVERFLOW Flag from MAC

The sysDSP block provides an overﬂow output to indicate that the accumulator has overﬂowed. When two

unsigned numbers are added and the result is a smaller number than the accumulator, “roll-over” is said to have

occurred and an overﬂow signal is indicated. When two positive numbers are added with a negative sum and when

two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and

an overﬂow signal is indicated. Note that when overﬂow occurs the overﬂow ﬂag is present for only one cycle. By

counting these overﬂow pulses in FPGA logic, larger accumulators can be constructed. The conditions overﬂow

signals for signed and unsigned operands are listed in Figure 2-27.

Figure 2-27. Accumulator Overﬂow/Underﬂow

000000011

000000010

000000001

000000000

3

2

1

0101111100

0101111101 253

252

Carry signal is generated for

one cycle when this

254

255

256

0101111110

0101111111

1010000000

0

boundary is crossed

111111111

111111110

111111101

511

510

509

1010000001 257

1010000010

258

Unsigned Operation

000000011

+3

+2

+1

0

-1

-2

-3

0101111100

0101111101 253

0101111110

0101111111

252

000000010

000000001

000000000

111111111

111111110

111111101

Overflow signal is generated

for one cycle when this

boundary is crossed

254

255

1010000000

1010000001

1010000010

-256

-255

-254

Signed Operation

2-27

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

IPexpress™

The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to conﬁgure

each DSP module (or group of modules) or by direct HDL instantiation. In addition, Lattice has partnered with The

MathWorks^®to support instantiation in the Simulink^®tool, a graphical simulation environment. Simulink works with

ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.

Optimized DSP Functions

Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP

include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/

Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest

list of available DSP IP cores.

Resources Available in the LatticeECP2/M Family

Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP2/M family. Table 2-10

shows the maximum available EBR RAM Blocks in each LatticeECP2/M device. EBR blocks, together with Distrib-

uted RAM can be used to store variables locally for fast DSP operations.

Table 2-9. Maximum Number of DSP Blocks in the LatticeECP2/M Family

Device

ECP2-6

DSP Block

9x9 Multiplier

18x18 Multiplier

36x36 Multiplier

3

6

24

48

12

24

28

32

72

88

24

32

88

96

168

3

6

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

7

56

7

8

64

8

18

22

6

144

176

48

18

22

6

8

64

8

22

24

42

176

192

336

22

24

42

Table 2-10. Embedded SRAM in the LatticeECP2/M Family

Total EBR SRAM

(Kbits)

Device

ECP2-6

EBR SRAM Block

3

55

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

12

221

15

277

18

332

21

387

60

1106

1217

2101

4147

4534

5308

66

114

225

246

288

2-28

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M DSP Performance

Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of

the LatticeECP2/M family.

Table 2-11. DSP Performance

DSP Performance

Device

ECP2-6

DSP Block

GMAC

3

6

3.9

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

7.8

7

9.1

8

10.4

23.4

28.6

7.8

18

22

6

8

10.4

28.6

31.2

54.6

22

24

42

For further information about the sysDSP block, please see the list of additional technical information at the end of

this data sheet.

Programmable I/O Cells (PIC)

Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block

supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the

buffer. Table 2-12 provides the PIO signal list.

2-29

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-28. PIC Diagram

PIOA

TD

OPOS1

ONEG1

IOLT0

Tristate

Register

Block

OPOS0

OPOS2*

ONEG0

ONEG2*

PADA

“T”

IOLD0

Output

Register

Block

sysIO

Buffer

QNEG0*

QNEG1*

QPOS0*

QPOS1*

INCK**

INDD

INFF

IPOS0

IPOS1

DI

Input

Register

Block

Control

Muxes

CLK1

CEO

CLK

CE

LSR

GSRN

LSR

GSR

ECLK1

CLK0

CEI

ECLK2

DDRCLKPOL*

DQSXFER*

PADB

“C”

PIOB

*Signals are available on left/right/bottom edges only.

** Selected blocks.

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.

The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right

edges of the device can be conﬁgured as true LVDS outputs. All I/O pairs can operate as inputs.

2-30

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 2-12. PIO Signals List

Name

Type

Description

CE0, CE1

CLK0, CLK1

ECLK1, ECLK2

LSR

Control from the core

Control from routing

Input to the core

Clock enables for input and output block ﬂip-ﬂops

System clocks for input and output blocks

Fast edge clocks

Local Set/Reset

GSRN

INCK²

Global Set/Reset (active low)

Input to Primary Clock Network or PLL reference inputs

DQS signal from logic (routing) to PIO

Unregistered data input to core

DQS

Input to PIO

INDD

Input to the core

INFF

Input to the core

Registered input on positive edge of the clock (CLK0)

Double data rate registered inputs to the core

Gearbox pipelined inputs to the core

IPOS0, IPOS1

Input to the core

QPOS0¹, QPOS1¹Input to the core

QNEG0¹, QNEG1¹Input to the core

OPOS0, ONEG0,

OPOS2, ONEG2

OPOS1 ONEG1

DEL[3:0]

Output data from the core

Output signals from the core for SDR and DDR operation

Tristate control from the core

Control from the core

Signals to Tristate Register block for DDR operation

Dynamic input delay control bits

TD

Tristate control from the core

Tristate signal from the core used in SDR operation

DDRCLKPOL

DQSXFER

Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block

Control from core Controls signal to the Output block

1. Signals available on left/right/bottom only.

2. Selected I/O.

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-

tion logic.

Input Register Block

The input register blocks for PIOs in left, right and bottom edges contain delay elements and registers that can be

used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-

faces, before they are passed to the device core. Figure 2-29 shows the diagram of the input register block for left,

right and bottom edges.The input register block for the top edge contains one memory element to register the input

signal as shown in Figure 2-30. The following description applies to the input register block for PIOs in the left, right

and bottom edges of the device.

Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,

in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a ﬁxed

delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when

using a global clock.

The input block allows three modes of operation. In the single data rate (SDR) the data is registered, by one of the

registers in the single data rate sync register block, with the system clock. In DDR Mode, two registers are used to

sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1.

These two data streams are synchronized with the system clock before entering the core. Further discussion on

this topic is in the DDR Memory section of this data sheet.

2-31

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox

function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data

streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For

more information about this topic, please see information regarding additional documentation at the end of this

data sheet.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred from the DQS to the system clock domain. For further information about this

topic, see the DDR Memory section of this data sheet.

Figure 2-29. Input Register Block for Left, Right and Bottom Edges

INCK**

To DQS Delay Block**

DI

(From sysIO

Buffer)

INDD

SDR & Sync

Registers

DDR Registers

Clock Transfer Registers

IPOS0A

Fixed Delay

0

1

0

1

D0

D2

Q

D

Dynamic Delay

D

QPOS0A

Q

D-Type

/LATCH

Q

D

D-Type*

DEL [3:0]

D-Type

From

Routing

IPOS1A

D1

Q

D

Q

D

QPOS1A

Q

D

Q

D

D-Type

/LATCH

Delayed

DQS

D-Type

D-Type*

0

1

To

Routing

CLK0 (of PIO A)

DDRCLKPOL

CLKA

True PIO (A) in LVDS I/O Pair

Comp PIO (B) in LVDS I/O Pair

INCK**

To DQS Delay Block**

INDD

DDRSRC

D0

DI

(From sysIO

Buffer)

SDR & Sync

Registers

DDR Registers

Clock Transfer Registers

0

1

Fixed Delay

IPOS0B

0

1

0

Dynamic Delay

Q

D

Q

D

QPOS0B

D

Q

1

D-Type

/LATCH

DEL [3:0]

D-Type*

D-Type

From

Routing

IPOS1B

0

1

D1

Q

QPOS1B

D

Q

D

Q

D2

D-Type

/LATCH

D-Type

D-Type*

Delayed

DQS

0

1

To

Routing

CLK0 (of PIO B)

Gearbox Configuration Bit

DDRCLKPOL

CLKB

Note: Simplified version does not

show CE and SET/RESET details

*Shared with output register

**Selected PIO.

2-32

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-30. Input Register Block Top Edge

INCK*

INDD

DI

(from sysIO

buffer)

Fixed Delay

Dynamic Delay

IPOS0

D

Q

D-Type

/LATCH

DEL[3:0]

CLK0

(from

routing)

Note: Simplified version does not show CE and SET/RESET details.

*On selected blocks.

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the sysI/O buffers. The blocks on the PIOs on the left, right and bottom contain a register for SDR operation that

is combined with an additional latch for DDR operation. Figure 2-31 shows the diagram of the Output Register

Block for PIOs on the left, right and the bottom edges. Figure 2-32 shows the diagram of the Output Register Block

for PIOs on the top edge of the device.

In SDR mode, ONEG0 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured as a D-

type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. Then at

the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock selects the correct

register for feeding to the output (D0).

By combining the output blocks of the complementary PIOs and sharing some registers from input blocks, a gear-

box function can be implemented, that takes four data streams: ONEG0A, ONEG1A, ONEG1B and ONEG1B.

Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor-

mation regarding additional documentation at the end of this data sheet.

2-33

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges

TD

Tristate Logic

D

Q

ONEG1

0

1

D-Type

/LATCH

TO

0

1

0

1

D

Q

D

Q

OPOS1

D-Type

Latch

0

1

DDR Output

Registers

Q

D

Q

ONEG0

D

0

1

D-Type

/LATCH

D-Type*

DO

0

1

OPOS0

0

1

0

1

Q

D

Latch

Q

D

Q

D

Q

D

0

1

^D-Type*

D-Type

Latch

CLKA

Clock Transfer

Registers

ECLK1

ECLK2

Programmable

0

1

0

1

Control

CLK1

(CLKA)

Output Logic

DQSXFER

True PIO (A) in LVDS I/O Pair

Comp PIO (B) in LVDS I/O Pair

TD

Tristate Logic

Q

D

ONEG1

0

1

D-Type

/LATCH

TO

0

1

0

1

Q

D

OPOS1

D-Type

Latch

Q

D

ONEG0

D

D-Type

/LATCH

DDR Output

Registers

D-Type*

DO

0

1

OPOS0

0

1

D

Q

D

Q

D

Q

D

Q

Latch

D-Type*

Latch

D-Type

CLKB

Clock Transfer

Registers

ECLK1

ECLK2

Programmable

0

Control

1

CLK1

1

(CLKB)

DQSXFER

Output Logic

Note: Simplified version does not show CE and SET/RESET details

* Shared with input register

2-34

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-32. Output and Tristate Block,Top Edge

TD

0

1

TO

0

Q

D

1

ONEG1

ONEG0

D-Type

/LATCH

Tristate Logic

DO

0

1

Q

D

D-Type

/LATCH

ECLK1

0

ECLK2

Output Logic

CLK1

1

(CLKA)

Note: Simplified version does not show CE and SET/RESET details.

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block with the Output Block for the left, right

and bottom edges and Figure 2-32 shows the diagram of the Tristate Register Block with the Output Block for the

top edge.

In SDR mode, ONEG1 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in

the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct

register for feeding to the output (D0).

Control Logic Block

The control logic block allows the selection and modiﬁcation of control signals for use in the PIO block. A clock is

selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (ECLK1/

ECLK2) and a DQS signal provided from the programmable DQS pin and provided to the input register block. The

clock can optionally be inverted.

DDR Memory Support

Certain PICs have additional circuitry to allow the implementation of high speed source synchronous and DDR

memory interfaces. The support varies by the edge of the device as detailed below.

Left and Right Edges

PICs on these edges have registered elements that support DDR memory interfaces. One of every 16 PIOs con-

tains a delay element to facilitate the generation of DQS signals.The DQS signal feeds the DQS bus that spans the

set of 16 PIOs. Figure 2-33 shows the assignment of DQS pins in each set of 16 PIOs.

Bottom Edge

PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs

contains a delay element to facilitate the generation of DQS signals.The DQS signal feeds the DQS bus that spans

the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs.

2-35

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Top Edge

The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not

have DDR registers or DQS signals.

The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-

tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR

data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR mem-

ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits

of data.

Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device

PADA "T"

LVDS Pair

PIO A

PADB "C"

PIO B

PADA "T"

LVDS Pair

PIO A

PADB "C"

PIO B

PADA "T"

LVDS Pair

PIO A

PADB "C"

PIO B

PADA "T"

LVDS Pair

PIO A

PADB "C"

PIO B

Assigned

sysIO

Buffer

PIO A

DQS Pin

PADA "T"

DQS

Delay

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PIO B

PADA "T"

LVDS Pair

PADB "C"

PADA "T"

LVDS Pair

PADB "C"

PIO A

PIO B

2-36

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-34. DQS Input Routing for the Bottom Edge of the Device

PADA "T"

LVDS Pair

PADB "C"

PIO A

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

Assigned

sysIO

Buffer

PIO A

DQS Pin

PADA "T"

DQS

Delay

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PIO B

PADA "T"

LVDS Pair

PADB "C"

PADA "T"

LVDS Pair

PADB "C"

PIO A

PIO B

PADA "T"

LVDS Pair

PADB "C"

PIO A

PIO B

DLL Calibrated DQS Delay Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock

(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS delay element to

a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of

the clock to the sync registers in the input register blocks. Figure 2-35 and Figure 2-36 show how the DQS transi-

tion signals are routed to the PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

(6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates

DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt-

age and process variations by the system clock and feedback loop.

2-37

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution

I/O Bank 0

I/O Bank 1

Spans 16 PIOs

ECLK1

ECLK2

I/O

B

a

n

k

B

a

n

k

DQS Input

2

7

Delayed

DQS

DDR_DLL

(Right)

DDR_DLL

(Left)

Polarity Control

DQSXFER

I/O

B

a

n

k

B

a

n

k

DQS Delay

Control Bus

6

3

Spans 18 PIOs

I/O Bank 4

I/O Bank 5

Note: Bank 8 is not shown.

2-38

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-36. DQS Local Bus

PIO

Output

Register Block

DDR

Datain

PAD

DQSXFER

sysIO

Buffer

Input

Register Block

DI

GSR

CEI

To Sync

Reg.

CLK1

DQS

To DDR

Reg.

DQS

Strobe

PAD

sysIO

Buffer

PIO

Polarity Control

Logic

DI

DQS

DQSDEL

Calibration bus

from DLL

DCNTL[6:0]

ECLK1

DQSXFER

DQSXFERDEL*

DCNTL[6:0]

*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.

Polarity Control Logic

In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the READ cycle) is unknown.

The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up

and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector

is used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects the ﬁrst DQS rising edge after the pre-

amble state. This signal is used to control the polarity of the clock to the synchronizing registers.

2-39

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

DQSXFER

LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memo-

ries that require DQS strobe be shifted 90^o. This shifted DQS strobe is generated by the DQSDEL block. The

DQSXFER signal runs the span of the data bus.

sysI/O Buffer

Each I/O is associated with a ﬂexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysI/O Buffer Banks

LatticeECP2/M devices have nine sysI/O buffer banks: eight banks for user I/Os arranged two per side. The ninth

sysI/O buffer bank (Bank 8) is located adjacent to Bank 3 and has dedicated/shared I/Os for conﬁguration. When a

shared pin is not used for conﬁguration it is available as a user I/O. Each bank is capable of supporting multiple I/O

standards. Each sysI/O bank has its own I/O supply voltage (V

). In addition, each bank, except Bank 8, has

CCIO

voltage references, V

and V

, which allow it to be completely independent from the others. Bank 8 shares

REF1

REF2

two voltage references, V

plies.

and V

, with Bank 3. Figure 2-37 shows the nine banks and their associated sup-

REF1

REF2

In LatticeECP2/M devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are

powered using V

independent of V

. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as ﬁxed threshold inputs

.

CCIO

Each bank can support up to two separate V

voltages, V

and V

, that set the threshold for the refer-

REF

REF1

REF2

enced input buffers. Some dedicated I/O pins in a bank can be conﬁgured to be a reference voltage supply pin.

Each I/O is individually conﬁgurable based on the bank’s supply and reference voltages.

2-40

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-37. LatticeECP2 Banks

TOP

Bank 0

Bank 1

V

CCIO2

V

REF1(2)

CCIO7

V

REF2(2)

REF1(7)

V

GND

REF2(7)

GND

V

CCIO3

V

REF1(3)

V

REF2(3)

CCIO6

V

GND

REF1(6)

V

REF2(6)

V

CCIO8

GND

Bank 5

Bank 4

BOTTOM

2-41

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 2-38. LatticeECP2M Banks

TOP

SERDES

Quad

SERDES

Quad

Bank 0

Bank 1

V

CCIO2

V

CCIO7

REF1(2)

V

REF1(7)

REF2(7)

GND

REF2(2)

GND

V

CCIO3

V

REF1(3)

V

CCIO6

REF2(3)

GND

REF1(6)

REF2(6)

GND

V

CCIO8

GND

Bank 5

Bank 4

SERDES

Quad

SERDES

Quad

BOTTOM

LatticeECP2/M devices contain two types of sysI/O buffer pairs.

1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only)

The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of

single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-

ﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

2. Bottom (Bank 4 and Bank 5) sysI/O Buffer Pairs (Single-Ended Outputs Only)

The sysI/O buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two

2-42

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also

be conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

3. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-

puts)

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-

erenced input buffers can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and

the comp (complementary) pad is associated with the negative side of the differential I/O.

LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.

4. Bank 8 sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by Conﬁgura-

tion)

The sysI/O buffers in Bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed

and referenced). The referenced input buffer can also be conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the

differential input buffer.

In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M

devices, the I/Os on the left and bottom banks have programmable PCI clamps.

Typical sysI/O I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when V , V

and V

have reached satisfactory

CC CCIO8

CCAUX

levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to

ensure that all other V banks are active with valid input logic levels to properly control the output logic states of

CCIO

all the I/O banks that are critical to the application. For more information about controlling the output logic state with

valid input logic levels during power-up in LatticeECP2/M devices, see the list of additional technical documentation

at the end of this data sheet.

The V and V

supply the power to the FPGA core fabric, whereas the V

supplies power to the I/O buff-

CC

CCAUX

CCIO

ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. V supplies should be powered-up before or

CCIO

together with the V and V

supplies.

CC

CCAUX

Supported sysI/O Standards

The LatticeECP2/M sysI/O buffer supports both single-ended and differential standards. Single-ended standards

can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS

1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual conﬁgura-

tion options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open

drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include

LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/

O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further

information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional

technical information at the end of this data sheet.

2-43

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 2-13. Supported Input Standards

Input Standard

Single Ended Interfaces

LVTTL

V

(Nom.)

V

¹(Nom.)

CCIO

REF

—

LVCMOS33

LVCMOS25

LVCMOS18

1.8

1.5

—

LVCMOS15

LVCMOS12

PCI 33

3.3

—

HSTL18 Class I, II

HSTL15 Class I

0.9

0.75

1.5

—

SSTL3 Class I, II

—

SSTL2 Class I, II

1.25

0.9

—

SSTL18 Class I, II

Differential Interfaces

Differential SSTL18 Class I, II

Differential SSTL2 Class I, II

Differential SSTL3 Class I, II

Differential HSTL15 Class I

Differential HSTL18 Class I, II

LVDS, MLVDS, LVPECL, BLVDS, RSDS

—

1

When not speciﬁed, V

can be set anywhere in the valid operating range (page 3-1).

CCIO

2-44

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 2-14. Supported Output Standards

Output Standard

Single-ended Interfaces

LVTTL

Drive

V

(Nom.)

CCIO

4mA, 8mA, 12mA, 16mA, 20mA

3.3

LVCMOS33

4mA, 8mA, 12mA 16mA, 20mA

3.3

2.5

1.8

1.5

1.2

—

LVCMOS25

4mA, 8mA, 12mA, 16mA, 20mA

LVCMOS18

4mA, 8mA, 12mA, 16mA

LVCMOS15

4mA, 8mA

LVCMOS12

2mA, 6mA

LVCMOS33, Open Drain

LVCMOS25, Open Drain

LVCMOS18, Open Drain

LVCMOS15, Open Drain

LVCMOS12, Open Drain

PCI33

4mA, 8mA, 12mA 16mA, 20mA

—

4mA, 8mA, 12mA 16mA

—

4mA, 8mA

2mA, 6mA

N/A

—

3.3

1.8

1.5

3.3

2.5

1.8

HSTL18 Class I, II

HSTL15 Class I

N/A

SSTL3 Class I, II

SSTL2 Class I, II

SSTL18 Class I, II

Differential Interfaces

Differential SSTL3, Class I, II

Differential SSTL2, Class I, II

Differential SSTL18, Class I, II

Differential HSTL18, Class I, II

Differential HSTL15, Class I

LVDS

MLVDS¹

BLVDS¹

LVPECL¹

RSDS¹

N/A

3.3

2.5

1.8

1.5

2.5

3.3

2.5

3.3

N/A

LVCMOS33D¹

4mA, 8mA, 12mA, 16mA, 20mA

1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at

the end of this data sheet.

Hot Socketing

LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and power-

down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is

high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within speciﬁed limits. This

allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many

multiple power supply and hot-swap applications.

2-45

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

SERDES and PCS (Physical Coding Sublayer)

LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the

devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and

LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices.

Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each

quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of

popular data protocols. PCS also contains logic to the interface to FPGA core.

Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100)

ULC SERDES Quad

Ch 3 Ch 2 Ch 1 Ch 0

PCS Digital Logic

URC SERDES Quad

Ch 3 Ch 2 Ch 1 Ch 0

PCS Digital Logic

Ch 3 Ch 2 Ch 1 Ch 0

PCS Digital Logic

Ch 3 Ch 2 Ch 1 Ch 0

LLC SERDES Quad

LRC SERDES Quad

Table 2-15. Available SERDES Quads per LatticeECP2M Devices

Device

URC Quad

Available

ULC Quad

—

LRC Quad

—

LLC Quad

—

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

—

Available

—

Available

SERDES Block

A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and

de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives

the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen-

tial buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its inter-

face to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the

FPGA core logic.

2-46

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Each Transmit and Receive channel has its independent power supplies. The Output and Input buffers of each

channel also have their own independent power supplies. In addition, there are separate power supplies for PLL,

terminating resistor per quad.

Figure 2-40. Simpliﬁed Channel Block Diagram for SERDES and PCS

SERDES (Analog)

PCS (Digital)

RX REFCLK

Recovered Clock

Receiver

Elastic Buffer

Read Clock

Down

Sample

FIFO

Byte Boundary

Detect, 8b/10b

Decoder

CTC

FIFO

Deserializer

1:8/1:10

Polarity

Adjust

Equalizer

16/20 bits

Receive Data

TX REFCLK

FPGA Receive Clock

FPGA Transmit Clock

To FPGA Core

TX PLL

Up

Sample

FIFO

8b/10b

Encoder

Serializer

8:1/10:1

Polarity

Adjust

8/10 bits or

16/20 bits

Transmit Data

Transmit

From Transmit PLL

(In Common Block)

PCS

As shown in Figure 2-40, the PCS receives the parallel digital data from the deserializer receivers and adjusts the

polarity, detects, byte boundary, decodes (8b/10b) and provides Clock Tolerance Compensation (CTC) FIFO for

changing the clock domain from receiver clock to the FPGA Clock.

For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b,

adjusts the polarity and passes the 8/10 bit data to the transmit SERDES channel.

The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA

logic. The PCS interface to FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the

FPGA logic.

SCI (SERDES Client Interface) Bus

The SERDES Client Interface (SCI) is a soft IP interface that allow the SERDES/PCS Quad block to be controlled

by registers as opposed to the conﬁguration memory cells. It is a simple register conﬁguration interface.

The ispLEVER design tools from Lattice support all modes of the PCS. Most modes are dedicated to applications

associated with a speciﬁc industry standard data protocol. Other more general purpose modes allow users to

deﬁne their own operation. With ispLEVER, the user can deﬁne the mode for each quad in a design.

Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using

IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core.

For further information about SERDES, please see the list of additional technical documentation at the end of this

data sheet.

2-47

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeECP2/M devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test

Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a

serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation.The test

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage

V

and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

CCJ

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

Device Conﬁguration

All LatticeECP2/M devices contain two ports that can be used for device conﬁguration. The Test Access Port (TAP),

which supports bit-wide conﬁguration, and the sysCONFIG port, support both byte-wide and serial conﬁguration,

including the standard SPI Flash interface. The TAP supports both the IEEE Standard 1149.1 Boundary Scan

speciﬁcation and the IEEE Standard 1532 In- System Conﬁguration speciﬁcation. The sysCONFIG port is a 20-pin

interface with six I/Os used as dedicated pins with the remainder used as dual-use pins. See Lattice technical note

number TN1108, LatticeECP2 sysCONFIG Usage Guide for more information about using the dual-use pins as

general purpose I/Os.

On power-up, the FPGA SRAM is ready to be conﬁgured using the selected sysCONFIG port. Once a conﬁguration

port is selected, it will remain active throughout that conﬁguration cycle.The IEEE 1149.1 port can be activated any

time after power-up by sending the appropriate command through the TAP port.

Enhanced Conﬁguration Option

LatticeECP2/M devices have enhanced conﬁguration features such as: decryption support, TransFR™ I/O and

dual boot image support.

1. Decryption Support

LatticeECP2/M devices provide on-chip, One Time Programmable (OTP) non-volatile key storage to support

decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy.

2. TransFR (Transparent Field Reconﬁguration)

TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the ﬁeld without

interrupting system operation using a single ispVM^®command. TransFR I/O allows I/O states to be frozen dur-

ing device conﬁguration. This allows the device to be ﬁeld updated with a minimum of system disruption and

downtime. See Lattice technical note number TN1087, Minimizing System Interruption During Conﬁguration

Using TransFR Technology, for details.

3. Dual Boot Image Support

Dual boot images are supported for applications requiring reliable remote updates of conﬁguration data for the

system FPGA. After the system is running with a basic conﬁguration, a new boot image can be downloaded

remotely and stored in a separate location in the conﬁguration storage device. Any time after the update the

LatticeECP2/M can be re-booted from this new conﬁguration ﬁle. If there is a problem, such as corrupt data

during download or incorrect version number with this new boot image, the LatticeECP2/M device can revert

back to the original backup conﬁguration and try again. This all can be done without power cycling the system.

For more information about device conﬁguration, please see the list of additional technical documentation at the

end of this data sheet.

Software Error Detect (SED) Support

LatticeECP2/M devices have dedicated logic to perform CRC checks. During conﬁguration, the conﬁguration data

bitstream can be checked with the CRC logic block. In addition, the LatticeECP2 device can also be programmed

2-48

Architecture

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

for checking soft errors (SED) in SRAM. This SED operation can be run in the background during user mode. If a

soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a

known good boot image or generate an error signal.

For further information about Soft Error Detect (SED) support, please see the list of additional technical documen-

tation at the end of this data sheet.

External Resistor

LatticeECP2/M devices require a single external, 10K ohm 1% value between the XRES pin and ground. Device

conﬁguration will not be completed if this resistor is missing. There is no boundary scan register on the external

resistor pad.

On-Chip Oscillator

Every LatticeECP2/M device has an internal CMOS oscillator which is used to derive a Master Clock for conﬁgura-

tion. The oscillator and the Master Clock run continuously and are available to user logic after conﬁguration is com-

pleted. The software default value of the Master Clock is 2.5MHz. Table 2-16 lists all the available Master

Conﬁguration Clock frequencies for normal non-encrypted mode and encrypted mode. When a different Master

Clock is selected during the design process, the following sequence takes place:

1. Device powers up with a Master Clock frequency of 3.1MHz.

2. During conﬁguration, users select a different master clock frequency.

3. The Master Clock frequency changes to the selected frequency once the clock conﬁguration bits are received.

4. If the user does not select a master clock frequency, then the conﬁguration bitstream defaults to the Master

Clock frequency of 2.5MHz.

This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further

information about the use of this oscillator for conﬁguration or user mode, please see the list of additional technical

documentation at the end of this data sheet.

Table 2-16. Selectable Master Clock (CCLK) Frequencies During Conﬁguration

Non-Encrypted Mode CCLK (MHz)

Encrypted Mode CCLK (MHz)

2.5¹

13.0

15.0

20.0

26.0

30.0

34.0

41.0

45.0

2.5¹

4.3

5.4

6.9

8.1

9.2

10.0

55.0

60.0

—

5.4

10.0

34.0

41.0

45.0

—

130.0

1. Software default frequency.

Density Shifting

The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same

package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design

migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-

lization design targeted for a high-density device to a lower density device. However, the exact details of the ﬁnal

resource utilization will impact the likelihood of success in each case. Design migration between LatticeECP2 and

LatticeECP2M families is not possible. For speciﬁc requirements relating to sysCONFIG pins of the ECP2M50,

M70 and M100, see the Logic Signal Connections tables.

2-49

LatticeECP2/M Family Data Sheet

DC and Switching Characteristics

February 2008

Data Sheet DS1006

Absolute Maximum Ratings^{1, 2, 3}

Supply Voltage V . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V

CC

Supply Voltage V

. . . . . . . . . . . . . . . . -0.5 to 3.75V

CCAUX

Supply Voltage V

. . . . . . . . . . . . . . . . . . -0.5 to 3.75V

CCJ

Output Supply Voltage V

. . . . . . . . . . . -0.5 to 3.75V

CCIO

Input or I/O Tristate Voltage Applied⁴. . . . . . -0.5 to 3.75V

Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C

Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V

+ 2) volts is permitted for a duration of <20ns.

IHMAX

Recommended Operating Conditions

Symbol

1, 4, 5

Parameter

Min.

1.14

3.135

1.14

0

Max.

1.26

3.465

1.26

3.465

85

Units

V

Core Supply Voltage

CC

1, 3, 4, 5

Auxiliary Supply Voltage

V

CCAUX

CCPLL

PLL Supply Voltage

V

1, 2, 4

I/O Driver Supply Voltage

V

CCIO

1

Supply Voltage for IEEE 1149.1 Test Access Port

Junction Temperature, Commercial Operation

Junction Temperature, Industrial Operation

V

CCJ

t

°C

JCOM

JIND

-40

100

SERDES External Power Supply (For LatticeECP2M Family Only)

Input Buffer Power Supply (1.2V)

1.14

1.425

1.14

1.26

1.575

1.26

V

CCIB

Input Buffer Power Supply (1.5V)

Output Buffer Power Supply (1.2V)

Output Buffer Power Supply (1.5V)

Termination Resistor Switching Power Supply

Receive Power Supply

CCOB

1.425

3.135

1.14

1.575

3.465

1.26

V

CCAUX33

6

CCRX

6

Transmit Power Supply

1.14

1.26

CCTX

6

PLL and Reference Clock Buffer Power

is set to 1.2V, they must be connected to the same power supply as V

1.14

1.26

CCP

1. If V

or V

If V

or V

is set to 3.3V, they must be con-

CCJ

CCIO

CCJ

CC.

CCIO

nected to the same power supply as V

. V and V

must be connected to the same power supply.

CCAUX CC

CCPLL

2. See recommended voltages by I/O standard in subsequent table.

3. V ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.

CCAUX

4. For proper power-up conﬁguration, users must ensure that the conﬁguration control signals such as the CFGx, INITN, PROGRAMN and

DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of V , V

or

CC CCAUX

V

supplies that reaches its minimum valid levels. Alternatively, if the conﬁguration control signals are pulled up by V

, the V

CCIO8

CCIO8 CCIO8

(conﬁguration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum levels.

5. For power-up, V must reach its valid minimum value before powering up V (LatticeECP2/M “S” version devices only).

CC

CCAUX

6. V

,V

and V

must be tied together in each quad and all quads need to be powered up.

CCRX CCTX

CCP

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

3-1

DS1006 DC and Switching_01.7

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Hot Socketing Speciﬁcations^{1, 2, 3, 4}

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

I

Input or I/O leakage current

0 ≤ V ≤ V (MAX.)

—

+/-1000

µA

DK

IN

IH

SERDES average input current when

device is powered down and inputs

are driven

5

I

—

4

mA

HDIN

1. V , V

and V

should rise/fall monotonically. V and V

must be connected to the same power supply (applies to ECP2-6,

CCPLL

CC CCAUX

CCIO

CC

ECP2-12 and ECP2-20 only).

2. 0 ≤ V ≤ V (MAX), 0 ≤ V

≤ V

(MAX) or 0 ≤ V

≤ V

(MAX).

CCAUX

CC

CCIO

CCAUX

3. I is additive to I , I

or I

.

DK

PU PW

BH

4. LVCMOS and LVTTL only.

5. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed

of 1.575V, 8b10b data and internal AC coupling.

V

CCIB

3-2

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

- 0.2V)

Min.

—

Typ.

—

8

Max.

10

Units

µA

V

1

I , I

Input or I/O Low Leakage

Input or I/O High Leakage

I/O Active Pull-up Current

I/O Active Pull-down Current

0 ≤ V ≤ (V

IN CCIO

IL IH

1

I

(V

- 0.2V) < V ≤ 3.6V

—

150

-210

210

—

IH

CCIO

IN

CCIO

0 ≤ V ≤ 0.7 V

-30

30

PU

IN

V

(MAX) ≤ V ≤ V (MAX)

IN IH

PD

IL

Bus Hold Low Sustaining Current V = V (MAX)

30

BHLS

BHHS

BHLO

BHHO

IN

IL

Bus Hold High Sustaining Current V = 0.7 V

-30

—

IN

CCIO

Bus Hold Low Overdrive Current 0 ≤ V ≤ V

210

-210

IN

Bus Hold High Overdrive Current 0 ≤ V ≤ V

—

IN

V

Bus Hold Trip Points

I/O Capacitance²

0 ≤ V ≤ V (MAX)

V

(MAX)

—

V

(MIN)

BHT

IN

IH

IL

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

—

pf

CCIO

CC

C1

C2

= 1.2V, V = 0 to V (MAX)

IO

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

—

6

pf

Dedicated Input Capacitance²

CCIO

CC

= 1.2V, V = 0 to V (MAX)

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. T 25^oC, f = 1.0MHz.

A

3-3

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Supply Current (Standby)^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

Typ.⁵

10

20

30

50

70

100

24

0.5

2

Units

mA

ECP2-6

ECP2-12

ECP2-20

I

Core Power Supply Current

CC

ECP2-35

ECP2-50

ECP2-70

ECP2-6

ECP2-12

ECP2-20

I

Auxiliary Power Supply Current

CCAUX

ECP2-35

ECP2-50

ECP2-70

I

GPLL Power Supply Current (per GPLL)

GPLL Power Supply Current (per SPLL)

ECP2-35, -50, -70 Only

ECP2-6

CCGPLL

CCSPLL

ECP2-12

2

ECP2-20

2

I

Bank Power Supply Current (Per Bank)

CCIO

CCJ

ECP2-35

2

ECP2-50

2

ECP2-70

2

I

VCCJ Power Supply Current

All Devices

3

1. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

3. Frequency 0MHz.

or GND.

CCIO

4. Pattern represents a “blank” conﬁguration data ﬁle.

5. T = 25°C, power supplies at normal voltage.

J

3-4

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Supply Current (Standby)^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

Typ.⁵

25

50

85

100

24

0.5

2

Units

mA

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

All Devices

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

All Devices

I

Core Power Supply Current

CC

I

Auxiliary Power Supply Current

CCAUX

I

GPLL Power Supply Current (per GPLL)

GPLL Power Supply Current (per SPLL)

CCGPLL

CCSPLL

2

I

Bank Power Supply Current (Per Bank)

2

CCIO

2

I

V

Power Supply Current

3

CCJ

1. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

3. Frequency 0MHz.

or GND.

CCIO

4. Pattern represents a “blank” conﬁguration data ﬁle.

5. T = 25°C, power supplies at normal voltage.

J

3-5

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Initialization Supply Current^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

Typ.^{5, 6}

34

Units

mA

ECP2-6

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2-6

54

82

I

Core Power Supply Current

CC

135

187

267

30

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

30

I

Auxiliary Power Supply Current

CCAUX

30

I

GPLL Power Supply Current (per GPLL)

SPLL Power Supply Current (per SPLL)

Bank Power Supply Current (per Bank)

VCCJ Power Supply Current

ECP2-35, -50, -70 Only

All Devices

0.5

3

CCGPLL

CCSPLL

CCIO

All Devices

4

CCJ

1. Until DONE signal is active.

2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.

3. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

4. Frequency 0MHz.

or GND.

CCIO

5. T = 25^oC, power supplies at nominal voltage.

J

6. A speciﬁc conﬁguration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-

ﬁguration.

3-6

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Initialization Supply Current^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

Typ.^{5, 6}

41

Units

mA

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

All Devices

107

169

254

378

30

I

Core Power Supply Current

CC

30

I

Auxiliary Power Supply Current

30

CCAUX

30

I

GPLL Power Supply Current (per GPLL)

SPLL Power Supply Current (per SPLL)

Bank Power Supply Current (per Bank)

VCCJ Power Supply Current

0.5

3

CCGPLL

CCSPLL

CCIO

4

CCJ

1. Until DONE signal is active.

2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.

3. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

4. Frequency 0MHz.

or GND.

CCIO

5. T = 25^oC, power supplies at nominal voltage.

J

6. A speciﬁc conﬁguration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-

ﬁguration.

3-7

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

SERDES Power Supply Requirements (LatticeECP2M Family Only)¹

Over Recommended Operating Conditions

Symbol

Description

Typ.²

Units

Standby (Power Down)

I

V

current (per channel)

10

75

0

µA

CCTX-SB

CCRX-SB

CCIB-SB

CCTX

current (per channel)

CCRX

Input buffer current (per channel)

Output buffer current (per channel)

SERDES PLL current (per quad)

SERDES termination current (per quad)

0

CCOB-SB

CCP-SB

30

10

CCAX33-SB

Operating (Data Rate = 3.125 Gbps)

I

V

current (per channel)

19

34

mA

CCTX-OP

CCRX-OP

CCIB-OP

CCOB-OP

CCP-OP

CCTX

CCRX

Input buffer current (per channel)

Output buffer current (per channel)

SERDES PLL current (per quad)

SERDES termination current (per quad)

4

13

26

0.01

CCAX33-OP

1. Equalization enabled, pre-emphasis disabled.

2. T = 25°C, power supplies at nominal voltage.

J

SERDES Power (LatticeECP2M Family Only)

Table 3-1 presents the SERDES power for one channel.

Table 3-1. SERDES Power¹

Symbol

Description

Typ.²

90

Units

mW

P

SERDES power (one channel @ 3.125 Gbps)

SERDES power (one channel @ 2.5 Gbps)

SERDES power (one channel @ 1.25 Gbps)

SERDES power (one channel @ 250 Mbps)

S-1CH-31

87

S-1CH-25

S-1CH-12

S-1CH-02

86

76

1. One quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating, pre-emphasis dis-

abled, equalization enabled).

2. Typical values measured at 25^oC and 1.2V.

3-8

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysI/O Recommended Operating Conditions

V

(V)

REF

CCIO

Standard

LVCMOS 3.3²

LVCMOS 2.5²

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2²

LVTTL²

Min.

3.135

2.375

1.71

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

1.8

2.5

3.3

1.5

1.8

2.5

3.3

2.5

1.8

2.5

3.3

1.5

1.8

Max.

3.465

2.625

1.89

Min.

—

Typ.

—

Max.

—

1.425

1.14

1.575

1.26

—

3.135

1.71

3.465

1.89

—

PCI

—

SSTL18²Class I, II

SSTL2²Class I, II

SSTL3²Class I, II

HSTL²15 Class I

HSTL²18 Class I, II

LVDS²

MLVDS25¹

LVPECL33^{1, 2}

BLVDS25^{1, 2}

0.833

1.15

1.3

0.68

0.816

—

0.9

1.25

1.5

0.75

0.9

—

0.969

1.35

1.7

0.9

1.08

—

2.375

3.135

1.425

1.71

2.625

3.465

1.575

1.89

2.375

3.135

2.375

1.71

2.625

3.465

2.625

1.89

—

RSDS^{1, 2}

—

SSTL18D_I², II²

SSTL25D_ I², II²

SSTL33D_ I², II²

HSTL15D_ I²

HSTL18D_ I², II²

—

2.375

3.135

1.425

1.71

2.625

3.465

1.575

1.89

—

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. Input on this standard does not depend on the value of V

.

CCIO

3-9

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysI/O Single-Ended DC Electrical Characteristics

V

IH

IL

Input/Output

Standard

V

OH

Min. (V)

OL

Min. (V)

Max. (V)

Min. (V)

Max. (V)

I

¹(mA)

I

¹(mA)

OH

OL

20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.4

V

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

CCIO

LVCMOS 3.3

LVTTL

-0.3

0.8

2.0

3.6

0.2

0.1

-0.1

20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.4

-0.3

0.8

0.7

2.0

1.7

3.6

0.2

0.1

-0.1

20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.4

LVCMOS 2.5

LVCMOS 1.8

0.2

0.1

-0.1

16, 12,

8, 4

-16, -12,

-8, -4

0.4

0.35 V

0.65 V

CCIO

0.2

0.4

0.2

0.4

0.2

V

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

0.1

8, 4

0.1

6, 2

0.1

1.5

8

-0.1

-8, -4

-0.1

-6, -2

-0.1

-0.5

-8

CCIO

LVCMOS 1.5

LVCMOS 1.2

-0.3

3.6

CCIO

0.35 V

0.65 V

CC

PCI

-0.3

0.3 V

0.5 V

3.6

0.1 V

0.9 V

CCIO

CCIO CCIO

SSTL3 Class I

SSTL3 Class II

V

- 0.2

V

+ 0.2

0.7

V

- 1.1

- 0.9

REF

CCIO

- 0.2

V

+ 0.2

0.5

16

7.6

12

15.2

20

6.7

8

-16

-7.6

-12

-15.2

-20

-6.7

-8

CCIO

SSTL2 Class I

-0.3

V

- 0.18

V

+ 0.18

3.6

0.54

V

- 0.62

REF

CCIO

SSTL2 Class II

SSTL18 Class I

SSTL18 Class II

-0.3

- 0.18

V

+ 0.18

3.6

0.35

0.4

V

- 0.43

- 0.4

REF

CCIO

V

- 0.125 V

+ 0.125

REF

V

0.28

- 0.28

11

4

-11

-4

HSTL Class I

-0.3

V

- 0.1

V

+ 0.1

3.6

0.4

V

- 0.4

REF

CCIO

8

-8

8

-8

HSTL18 Class I

HSTL18 Class II

-0.3

V

- 0.1

V

+ 0.1

3.6

0.4

V

- 0.4

REF

CCIO

12

16

-12

-16

REF

CCIO

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

3-10

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysI/O Differential Electrical Characteristics

LVDS

Over Recommended Operating Conditions

Parameter

Description

Input Voltage

Test Conditions

Min.

0

Typ.

—

Max.

2.4

Units

V

, V

INP INM

Input Common Mode Voltage

Differential Input Threshold

Input Current

Half the Sum of the Two Inputs

Difference Between the Two Inputs

Power On or Power Off

0.05

+/-100

—

2.35

—

V

CM

—

mV

µA

V

THD

I

—

+/-10

1.60

—

IN

V

Output High Voltage for V or V

R = 100 Ohm

—

1.38

1.03

350

OH

OL

OD

OP

OM

T

Output Low Voltage for V or V

R = 100 Ohm

0.9V

250

V

OP

OM

T

Output Voltage Differential

(V - V ), R = 100 Ohm

450

mV

OP

OM

T

Change in V Between High and

Low

OD

ΔV

—

50

mV

OD

V

Output Voltage Offset

(V + V )/2, R = 100 Ohm

1.125

—

1.20

—

1.375

50

V

OS

OP

OM

T

ΔV

Change in V Between H and L

mV

OS

V

= 0V Driver Outputs Shorted to

OD

I

Output Short Circuit Current

—

24

12

mA

SA

Ground

V

= 0V Driver Outputs Shorted to

OD

I

SAB

Each Other

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list

of additional technical information at the end of this data sheet.

3-11

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LVDS25E

The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS

outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one

possible solution for point-to-point signals.

Figure 3-1. LVDS25E Output Termination Example

VCCIO = 2.5V ( 5%)

RS=158 ohms

( 1%)

8 mA

+

-

RP = 140 ohms

( 1%)

RT = 100 ohms

( 1%)

VCCIO = 2.5V ( 5%)

8 mA

RS=158 ohms

( 1%)

Transmission line, Zo = 100 ohm differential

OFF-chip ON-chip

ON-chip

OFF-chip

Table 3-2. LVDS25E DC Conditions

Parameter

Description

Typical

2.50

20

Units

V

Output Driver Supply (+/-5%)

Driver Impedance

CCIO

OUT

Z

Ω

R

Driver Series Resistor (+/-1%)

Driver Parallel Resistor (+/-1%)

Receiver Termination (+/-1%)

Output High Voltage

158

Ω

S

140

Ω

P

100

Ω

T

V

1.43

1.07

0.35

1.25

100.5

6.03

V

OH

OL

OD

CM

BACK

Output Low Voltage

V

Output Differential Voltage

Output Common Mode Voltage

Back Impedance

V

Z

Ω

I

DC Output Current

mA

DC

LVCMOS33D

All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external

resistor network, provides the system designer the ﬂexibility to place differential outputs on an I/O bank with 3.3V

VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to

4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 speciﬁcations for the DC characteristics of the LVCMOS33D.

3-12

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

BLVDS

The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVC-

MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use

when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is

one possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

16mA

2.5V

16mA

R_S=

90 ohms

R_S=

90 ohms

45-90

ohms

45-90

ohms

R_TL

R_TR

2.5V

16mA

2.5V

16mA

R_S= 90 ohms

R_S=

90 ohms

R_S=

90 ohms

R_S=

90 ohms

.⁹.^{0 o}.^hms

+

-

+

-

2.5V

16mA

Table 3-3. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Typical

Parameter

Description

Zo = 45Ω

2.50

Zo = 90Ω

2.50

Units

V

Output Driver Supply (+/- 5%)

Driver Impedance

CCIO

OUT

Z

10.00

90.00

45.00

1.38

10.00

90.00

1.48

Ω

R

Driver Series Resistor (+/- 1%)

Driver Parallel Resistor (+/- 1%)

Receiver Termination (+/- 1%)

Output High Voltage

Ω

S

Ω

TL

Ω

TR

OH

OL

OD

CM

V

Output Low Voltage

1.12

1.02

V

Output Differential Voltage

Output Common Mode Voltage

DC Output Current

0.25

0.46

V

1.25

V

I

11.24

10.20

mA

DC

1. For input buffer, see LVDS table.

3-13

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LVPECL

The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using comple-

mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan-

dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for

point-to-point signals.

Figure 3-3. Differential LVPECL

V

= 3.3V

CCIO

(+/-5%)

R

= 93.1 ohms

(+/-1%)

S

16mA

+

-

V

= 3.3V

CCIO

R

= 196 ohms

(+/-1%)

R

= 100 ohms

(+/-1%)

P

T

(+/-5%)

R

= 93.1 ohms

(+/-1%)

16mA

Transmission line,

Zo = 100 ohm differential

On-chip

Off-chip

On-chip

Table 3-4. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Parameter

Description

Output Driver Supply (+/-5%)

Driver Impedance

Typical

Units

V

3.30

10

V

Ω

V

CCIO

OUT

Z

R

Driver Series Resistor (+/-1%)

Driver Parallel Resistor (+/-1%)

Receiver Termination (+/-1%)

Output High Voltage

93

S

196

P

100

T

V

2.05

1.25

0.80

1.65

100.5

12.11

OH

OL

OD

CM

BACK

Output Low Voltage

V

Output Differential Voltage

Output Common Mode Voltage

Back Impedance

V

Z

Ω

mA

I

DC Output Current

DC

1. For input buffer, see LVDS table.

3-14

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

RSDS

The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary

LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-

ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS

standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.

Figure 3-4. RSDS (Reduced Swing Differential Signaling)

V

= 2.5V

(+/-5%)

CCIO

R

S

= 294 ohms

(+/-1%)

8mA

+

-

V

= 2.5V

(+/-5%)

R

P

= 121 ohms

(+/-1%)

R = 100 ohms

T

CCIO

(+/-1%)

R

S

= 294 ohms

(+/-1%)

8mA

On-chip

Transmission line,

Zo = 100 ohm differential

Off-chip

On-chip

Table 3-5. RSDS DC Conditions¹

Over Recommended Operating Conditions

Parameter

Description

Typical

2.50

20

Units

V

Output Driver Supply (+/-5%)

Driver Impedance

CCIO

OUT

Z

Ω

R

Driver Series Resistor (+/-1%)

Driver Parallel Resistor (+/-1%)

Receiver Termination (+/-1%)

Output High Voltage

294

Ω

S

121

Ω

P

100

Ω

T

V

1.35

1.15

0.20

1.25

101.5

3.66

V

OH

OL

OD

CM

BACK

Output Low Voltage

V

Output Differential Voltage

Output Common Mode Voltage

Back Impedance

V

Z

Ω

I

DC Output Current

mA

DC

1. For input buffer, see LVDS table.

3-15

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

MLVDS

The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for

MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.

Figure 3-5. MLVDS (Multipoint Low Voltage Differential Signaling)

Heavily loaded backplace, effective Zo~50 to 70 ohms differential

2.5V

R

=

R =

S

35ohms

2.5V

16mA

S

35ohms

16mA

50 to 70 ohms +/-1%

R

TR

TL

2.5V

16mA

2.5V

16mA

R

=

S

R =

S

35ohms

R

=

R

=

R

=

R =

S

35ohms

S

+

-

+

-

35ohms

. . .

2.5V

16mA

Table 3-6. MLVDS DC Conditions¹

Typical

Parameter

Description

Zo=50Ω

2.50

Zo=70Ω

2.50

Units

V

Output Driver Supply (+/-5%)

Driver Impedance

CCIO

OUT

Z

10.00

35.00

50.00

1.52

10.00

35.00

70.00

1.60

Ω

R

Driver Series Resistor (+/-1%)

Driver Parallel Resistor (+/-1%)

Receiver Termination (+/-1%)

Output High Voltage

Ω

S

Ω

TL

Ω

TR

OH

OL

OD

CM

V

Output Low Voltage

0.98

0.90

V

Output Differential Voltage

Output Common Mode Voltage

DC Output Current

0.54

0.70

V

1.25

V

I

21.74

20.00

mA

DC

1. For input buffer, see LVDS table.

For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list

of additional technical information at the end of this data sheet.

3-16

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Typical Building Block Function Performance¹

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function

-7 Timing

Units

Basic Functions

16-bit Decoder

32-bit Decoder

64-bit Decoder

4:1 MUX

3.8

4.5

5.0

3.2

3.4

3.5

4.0

ns

8:1 MUX

16:1 MUX

32:1 MUX

1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool

uses internal parameters that have been characterized but are not tested on every device.

Timing v.A 0.11

Register-to-Register Performance

Function

Basic Functions

-7 Timing

Units

16-bit Decoder

32-bit Decoder

64-bit Decoder

4:1 MUX

599

542

417

847

803

660

577

591

500

306

488

378

260

253

MHz

8:1 MUX

16:1 MUX

32:1 MUX

8-bit Adder

16-bit Adder

64-bit Adder

16-bit Counter

32-bit Counter

64-bit Counter

64-bit Accumulator

Embedded Memory Functions

512x36 Single Port RAM, EBR Output

Registers

370

MHz

1024x18 True-Dual Port RAM (Write

Through or Normal, EBR Output Regis-

ters)

1024x18 True-Dual Port RAM (Write

Through or Normal, PLC Output

Registers)

280

MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (One PFU)

32x4 Pseudo-Dual Port RAM

64x8 Pseudo-Dual Port RAM

DSP Functions

819

521

435

MHz

18x18 Multiplier (All Registers)

420

MHz

3-17

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Register-to-Register Performance (Continued)

Function

-7 Timing

Units

9x9 Multiplier (All Registers)

420

MHz

36x36 Multiplier

(All Registers)

372

295

420

MHz

18x18 Multiplier/Accumulate (Input and

Output Registers)

18x18 Multiplier-Add/Sub-Sum (All Reg-

isters)

DSP IP Functions

16-Tap Fully-Parallel FIR Filter

304

227

223

MHz

1024-pt, Radix 4, Decimation in

Frequency FFT

8x8 Matrix Multiplier

Timing v.A 0.11

Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case

numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be

much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a

particular temperature and voltage.

3-18

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

Min.

Max.

Min.

Max.

Min.

Max.

Units

General I/O Pin Parameters (using Primary Clock without PLL)¹

LFE2-6

—

3.50

3.70

3.90

4.50

—

3.90

4.10

4.30

5.00

—

4.20

4.40

4.70

5.40

—

ns

LFE2-12

LFE2-20

LFE2-35

—

LFE2-50

—

Clock to Output - PIO Output

Register

t

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

—

CO

SU

H

—

0.00

1.40

1.80

0.00

1.70

2.10

0.00

1.90

2.30

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

—

Clock to Data Setup - PIO Input

Register

—

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

—

Clock to Data Hold - PIO Input

Register

—

3-19

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

LFE2-6

Min.

1.40

0.00

Max.

—

Min.

1.70

0.00

Max.

—

Min.

1.90

0.00

Max.

—

Units

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

Clock to Data Setup - PIO Input

Register with Data Input Delay

t

SU_DEL

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

Clock to Data Hold - PIO Input Reg-

ister with Input Data Delay

t

f

H_DEL

Clock Frequency of I/O Register and

PFU Register

ECP2/M

—

420

—

357

—

311

MHz

MAX_IO

General I/O Pin Parameters (using Edge Clock without PLL)¹

LFE2-6

—

2.60

3.10

—

2.90

3.40

—

3.20

3.70

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

Clock to Output - PIO Output

Register

t

LFE2-70

COE

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

3-20

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

LFE2-6

Min.

0.00

0.90

1.20

1.00

1.20

Max.

—

Min.

0.00

1.10

1.40

1.30

1.60

Max.

—

Min.

0.00

1.30

1.60

1.90

Max.

—

Units

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

Clock to Data Setup - PIO Input

Register

t

SUE

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

Clock to Data Hold - PIO Input

Register

HE

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

Clock to Data Setup - PIO Input

Register with Data Input Delay

SU_DELE

3-21

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

LFE2-6

Min.

0.00

Max.

—

Min.

0.00

Max.

—

Min.

0.00

Max.

—

Units

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

—

ns

—

ns

—

ns

—

ns

Clock to Data Hold - PIO Input

Register with Input Data Delay

t

f

—

ns

H_DELE

—

ns

—

ns

—

ns

—

ns

—

ns

Clock Frequency of I/O and PFU

Register

ECP2/M

—

420

—

357

—

311

MHz

MAX_IOE

General I/O Pin Parameters (using Primary Clock with PLL)¹

LFE2-6

—

2.30

2.60

2.70

—

2.60

2.90

3.00

—

2.80

3.10

3.20

—

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

—

Clock to Output - PIO Output

Register

10

t

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

—

COPLL

—

0.70

0.80

0.90

1.00

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

—

Clock to Data Setup - PIO Input

Register

t

—

SUPLL

—

3-22

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

LFE2-6

Min.

1.00

1.80

1.90

2.00

0.00

Max.

—

Min.

1.20

2.00

2.10

2.20

0.00

Max.

—

Min.

1.40

2.20

2.30

2.40

0.00

Max.

—

Units

ns

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

Clock to Data Hold - PIO Input

Register

t

HPLL

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

LFE2-6

Clock to Data Setup - PIO Input

Register with Data Input Delay

SU_DELPLL

LFE2-12

LFE2-20

LFE2-35

LFE2-50

LFE2-70

LFE2M20

LFE2M35

LFE2M50

LFE2M70

LFE2M100

Clock to Data Hold - PIO Input

Register with Input Data Delay

H_DELPLL

DDR I/O Pin Parameters²

t

f

Data Valid After DQS (DDR Read) ECP2/M

Data Hold After DQS (DDR Read) ECP2/M

Data Valid Before DQS (DDR Write) ECP2/M

—

0.225

—

0.225

—

0.225

—

UI

DVADQ

DVEDQ

DQVBS

DQVAS

MAX_DDR

0.640

0.250

95

0.640

0.250

95

0.640

0.250

95

—

UI

Data Valid After DQS (DDR Write)

ECP2/M

—

UI

DDR Clock Frequency⁶

200

166

133

MHz

DDR2 I/O Pin Parameters³

t

Data Valid After DQS (DDR Read) ECP2/M

Data Hold After DQS (DDR Read) ECP2/M

—

0.225

—

0.225

—

0.225

—

UI

DVADQ

DVEDQ

0.640

3-23

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

Min.

0.250

133

Max.

—

Min.

0.250

133

Max.

—

Min.

0.250

133

Max.

—

Units

UI

t

f

Data Valid Before DQS (DDR Write) ECP2/M

DQVBS

Data Valid After DQS (DDR Write)

ECP2/M

—

UI

DQVAS

DDR Clock Frequency

266

200

166

MHz

MAX_DDR2

SPI4.2 I/O Pin Parameters Static Alignment^{4, 8, 11}

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

ECP2-20

ECP2-35

ECP2-50

ECP2-70

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

—

750

622

0.25

0.21

—

622

0.25

0.21

—

622

0.25

0.21

—

Mbps

UI

—

Maximum Data Rate

—

UI

—

UI

—

UI

t

Data Valid After CLK (Receive)

Data Hold After CLK (Receive)

Data Invalid After Clock (Transmit)

—

UI

DVACLKSPI

DVECLKSPI

DIASPI

—

UI

—

UI

—

UI

—

UI

0.75

0.79

—

0.75

0.79

—

0.75

0.79

—

UI

—

UI

—

UI

—

UI

—

UI

—

UI

—

UI

—

UI

—

UI

280

230

280

230

280

230

ps

—

ps

—

ps

—

ps

—

ps

—

ps

—

ps

—

ps

—

ps

3-24

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M External Switching Characteristics⁹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Device

ECP2-20

ECP2-35

ECP2-50

ECP2-70

Min.

—

Max.

280

230

Min.

—

Max.

280

230

Min.

—

Max.

280

230

Units

ps

—

ps

—

ps

—

ps

t

Data Invalid Before Clock (Transmit) ECP2M20

—

ps

DIBSPI

ECP2M35

ECP2M50

ECP2M70

ECP2M100

—

ps

—

ps

—

ps

—

ps

XGMII I/O Pin Parameters (312 Mbps)⁵

t

Data Setup Before Read Clock

Data Hold After Read Clock

Data Valid Before Clock

ECP2/M

480

960

—

480

960

—

480

960

—

ps

SUXGMII

HXGMII

DVBCKXGMII

DVACKXGMII

Data Valid After Clock

Primary

7

f

t

Frequency for Primary Clock Tree

ECP2/M

—

0.95

—

420

—

1.19

—

357

—

2.00

—

311

—

MHz

ns

MAX_PRI

Clock Pulse Width for Primary Clock ECP2/M

Primary Clock Skew Within a Bank ECP2/M

W_PRI

300

360

420

ps

SKEW_PRI

Edge Clock

7

f

t

Frequency for Edge Clock

ECP2/M

—

420

—

357

—

311

—

MHz

ns

MAX_EDGE

Clock Pulse Width for Edge Clock

0.95

1.19

2.00

W_EDGE

Edge Clock Skew Within an Edge of

the Device

t

ECP2/M

—

300

—

360

—

420

ps

SKEW_EDGE

1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.

2. DDR timing numbers based on SSTL25 for BGA packages only.

3. DDR2 timing numbers based on SSTL18 for BGA packages only.

4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only.

5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to

the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer.

6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz.This approach uses a free-running clock and PFU register to

sample the data instead of the hardwired DDR memory interface.

7. Using the LVDS I/O standard.

8. ECP2-6 and ECP2-12 do not support SPI4.2

9. The AC numbers do not apply to PCLK6 and PCLK7.

10. Applies to CLKOP only.

11. Please refer to technical note TN1159, LatticeECP2M Pin Assignment Recommendations for best performance.

Timing v.A 0.11

3-25

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 3-6. SPI4.2 Parameters

Transmit Parameters

t_DIBSPI

t_DIASPI

CLK

Data (TDAT, TCTL)

t_DIASPI

t_DIBSPI

Receiver Parameters

RDTCLK

Data (RDAT,RCTL)

t_DVACLKSPI

t_DVECLKSPI

3-26

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 3-7. DDR and DDR2 Parameters

Transmit Parameters

DQS

DQ

t_DQVBS

t_DQVAS

t_DQVBS

Receiver Parameters

DQS

DQ

t_DVADQ

t_DVEDQ

Figure 3-8. XGMII Parameters

Transmit Parameters

CLOCK

DATA

t_DVBCKXGMII

t_DVACKXGMII

t_DVBCKXGMII

Receiver Parameters

CLOCK

DATA

t_SUXGMII

t_HXGMII

3-27

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M Internal Switching Characteristics¹

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

PFU/PFF Logic Mode Timing

t

LUT4 delay (A to D inputs to F output)

LUT6 delay (A to D inputs to OFX output)

—

0.180

0.304

—

0.198

0.331

—

0.216

0.358

ns

LUT4_PFU

LUT6_PFU

Set/Reset to output of PFU (Asynchro-

nous)

t

—

0.600

—

0.655

—

0.711

ns

LSR_PFU

t

Clock to Mux (M0,M1) Input Setup Time

Clock to Mux (M0,M1) Input Hold Time

Clock to D input setup time

0.128

-0.051

0.061

0.002

—

0.129

-0.049

0.071

0.003

—

0.129

-0.046

0.081

0.003

—

ns

SUM_PFU

HM_PFU

SUD_PFU

HD_PFU

Clock to D input hold time

Clock to Q delay, (D-type Register Conﬁgu-

ration)

t

—

0.285

—

0.309

—

0.333

ns

CK2Q_PFU

PFU Dual Port Memory Mode Timing

t

Clock to Output (F Port)

Data Setup Time

—

0.902

—

1.083

—

1.263

—

ns

CORAM_PFU

SUDATA_PFU

HDATA_PFU

-0.172

0.199

-0.245

0.246

-0.122

0.132

-0.205

0.235

-0.284

0.285

-0.145

0.156

-0.238

0.271

-0.323

0.324

-0.168

0.180

Data Hold Time

—

Address Setup Time

Address Hold Time

—

SUADDR_PFU

HADDR_PFU

SUWREN_PFU

HWREN_PFU

—

Write/Read Enable Setup Time

Write/Read Enable Hold Time

—

PIC Timing

PIO Input/Output Buffer Timing

t

Input Buffer Delay (LVCMOS25)

Output Buffer Delay (LVCMOS25)

—

0.613

1.115

—

0.681

1.115

—

0.749

1.343

ns

IN_PIO

OUT_PIO

IOLOGIC Input/Output Timing

Input Register Setup Time (Data Before

Clock)

t

0.596

—

0.645

—

0.694

—

ns

SUI_PIO

Input Register Hold Time (Data after

Clock)

-0.570

-0.614

-0.658

HI_PIO

t

Output Register Clock to Output Delay

Input Register Clock Enable Setup Time

Input Register Clock Enable Hold Time

Set/Reset Setup Time

—

0.61

—

0.66

—

0.72

—

ns

COO_PIO

SUCE_PIO

HCE_PIO

0.032

-0.022

0.184

-0.080

0.037

-0.025

0.201

-0.086

0.041

-0.028

0.217

-0.093

—

SULSR_PIO

HLSR_PIO

Set/Reset Hold Time

—

EBR Timing

Clock (Read) to output from Address or

Data

t

—

2.51

0.33

—

2.75

0.36

—

2.99

0.39

ns

CO_EBR

Clock (Write) to output from EBR output

Register

COO_EBR

t

Setup Data to EBR Memory

Hold Data to EBR Memory

Setup Address to EBR Memory

Hold Address to EBR Memory

-0.157

0.173

-0.115

0.138

—

-0.181

0.195

-0.130

0.155

-0.149

—

-0.205

0.217

-0.145

0.172

-0.170

—

ns

SUDATA_EBR

HDATA_EBR

SUADDR_EBR

HADDR_EBR

SUWREN_EBR

Setup Write/Read Enable to PFU Memory -0.128

3-28

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M Internal Switching Characteristics¹(Continued)

Over Recommended Operating Conditions

-7

-6

-5

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

Hold Write/Read Enable to PFU Memory

0.139

—

0.156

—

0.173

—

ns

HWREN_EBR

Clock Enable Setup Time to EBR Output

Register

0.123

-0.081

—

0.134

-0.090

—

0.145

-0.100

—

ns

SUCE_EBR

HCE_EBR

RSTO_EBR

SUBE_EBR

HBE_EBR

Clock Enable Hold Time to EBR Output

Register

t

Reset To Output Delay Time from EBR

Output Register

1.03

—

1.15

—

1.26

—

Byte Enable Set-Up Time to EBR Output

Register

-0.115

0.138

-0.130

0.155

-0.145

0.172

Byte Enable Hold Time to EBR Output

Register

—

GPLL Parameters

t

Reset Recovery to Rising Clock

1.00

—

1.00

—

1.00

—

ns

RSTREC_GPLL

SPLL Parameters

t

RSTREC_SPLL

DSP Block Timing^2,3

t

Input Register Setup Time

0.12

0.02

2.18

-0.68

4.26

-1.25

—

0.13

-0.01

2.42

-0.77

4.71

-1.40

—

0.14

-0.03

2.66

-0.86

5.16

-1.54

—

ns

SUI_DSP

HI_DSP

Input Register Hold Time

Pipeline Register Setup Time

Pipeline Register Hold Time

—

SUP_DSP

tHP_DSP

SUO_DSP

HO_DSP

—

Output Register Setup Time

—

Output Register Hold Time

—

Input Register Clock to Output Time

Pipeline Register Clock to Output Time

Output Register Clock to Output Time

AddSub Input Register Setup Time

AddSub Input Register Hold Time

3.92

1.87

0.50

—

4.30

1.98

0.52

—

4.68

2.08

0.55

—

COI_DSP

COP_DSP

COO_DSP

SUADDSUB

HADDSUB

—

-0.24

0.27

-0.26

0.29

-0.28

0.32

—

1. Internal parameters are characterized but not tested on every device.

2. These parameters apply to LatticeECP devices only.

3. DSP Block is conﬁgured in Multiply Add/Sub 18x18 Mode.

Timing v.A 0.11

3-29

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Timing Diagrams

Figure 3-9. Read/Write Mode (Normal)

CLKA

CSA

WEA

ADA

DIA

A0

A1

D1

A0

A1

A0

t_SUt_H

D0

t_{CO_EBR}

D0

D1

DOA

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

Figure 3-10. Read/Write Mode with Input and Output Registers

CLKA

CSA

WEA

ADA

A1

A0

A1

D1

A0

t

H

SU

DIA

D0

t

COO_EBR

DOA (Regs)

D1

D0

Mem(n) data from previous read

output is only updated during a read cycle

3-30

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only)

CLKA

CSA

WEA

Three consecutive writes to A0

ADA

A0

A1

D1

A0

t

H

SU

D2

D3

D2

D4

D0

DIA

t

ACCESS

Data from Prev Read

or Write

D0

D1

D3

DOA

D4

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

3-31

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M Family Timing Adders^{1, 2, 3}

Over Recommended Operating Conditions

Buffer Type

Input Adjusters

LVDS25

Description

-7

-6

-5

Units

LVDS

-0.04

-0.15

0.16

-0.02

-0.09

-0.15

0.15

0.00

-0.15

0.13

ns

BLVDS25

BLVDS

MLVDS

LVDS

RSDS

LVPECL33

HSTL18_I

HSTL18_II

HSTL18D_I

HSTL18D_II

HSTL15_I

HSTL15D_I

SSTL33_I

SSTL33_II

SSTL33D_I

SSTL33D_II

SSTL25_I

SSTL25_II

SSTL25D_I

SSTL25D_II

SSTL18_I

SSTL18_II

SSTL18D_I

SSTL18D_II

LVTTL33

LVPECL

HSTL_18 class I

HSTL_18 class II

Differential HSTL 18 class I

Differential HSTL 18 class II

HSTL_15 class I

Differential HSTL 15 class I

SSTL_3 class I

SSTL_3 class II

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL_2 class II

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_18 class I

SSTL_18 class II

Differential SSTL_18 class I

Differential SSTL_18 class II

LVTTL

0.01

-0.01

-0.07

-0.04

-0.16

-0.12

0.00

-0.04

-0.10

-0.07

-0.16

0.00

0.01

-0.03

-0.04

-0.01

-0.16

-0.08

0.00

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

-0.16

-0.14

-0.04

-0.08

-0.17

-0.14

-0.01

-0.12

-0.17

-0.14

0.01

LVCMOS 1.5

LVCMOS 1.2

PCI

-0.16

Output Adjusters

LVDS25E

LVDS 2.5 E⁴

0.25

0.10

0.00

0.25

-0.02

-0.19

-0.30

-0.19

-0.30

0.19

0.13

0.17

ns

LVDS25

LVDS 2.5

BLVDS25

BLVDS 2.5

MLVDS 2.5⁴

RSDS 2.5⁴

LVPECL 3.3⁴

-0.01

0.19

-0.03

0.13

MLVDS

RSDS

LVPECL33

HSTL18_I

HSTL18_II

HSTL18D_I

HSTL18D_II

-0.04

-0.22

-0.34

-0.22

-0.34

-0.06

-0.25

-0.37

-0.25

-0.37

HSTL_18 class I 8mA drive

HSTL_18 class II

Differential HSTL 18 class I 8mA drive

Differential HSTL 18 class II

3-32

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M Family Timing Adders^{1, 2, 3}(Continued)

Over Recommended Operating Conditions

Buffer Type

HSTL15_I

Description

HSTL_15 class I 4mA drive

-7

-6

-5

Units

ns

-0.22

-0.12

-0.20

-0.12

-0.20

-0.16

-0.19

-0.16

-0.19

-0.14

-0.20

-0.14

-0.20

0.52

0.06

0.04

0.03

-0.09

0.52

0.06

0.04

0.03

-0.09

0.41

0.01

0.00

0.04

-0.09

0.37

0.10

-0.02

0.29

0.05

0.58

0.13

2.17

2.50

1.72

1.64

1.33

-0.25

-0.15

-0.23

-0.15

-0.23

-0.19

-0.22

-0.19

-0.22

-0.17

-0.23

-0.17

-0.23

0.60

0.08

0.04

0.02

-0.09

0.60

0.08

0.04

0.02

-0.09

0.47

0.01

0.00

0.04

-0.10

0.40

0.12

-0.02

-0.03

0.31

0.05

0.69

0.19

2.44

2.67

1.88

1.63

1.36

-0.27

-0.18

-0.27

-0.18

-0.27

-0.22

-0.25

-0.22

-0.25

-0.20

-0.25

-0.20

-0.25

0.68

0.09

0.05

0.02

-0.10

0.68

0.09

0.05

0.02

-0.10

0.53

0.00

0.04

-0.11

0.43

0.13

-0.02

-0.03

0.32

0.06

0.79

0.26

2.71

2.83

2.05

1.62

1.39

HSTL15D_I

Differential HSTL 15 class I 4mA drive

SSTL_3 class I

SSTL33_I

SSTL33_II

SSTL_3 class II

SSTL33D_I

Differential SSTL_3 class I

SSTL33D_II

Differential SSTL_3 class II

SSTL25_I

SSTL_2 class I 8mA drive

SSTL25_II

SSTL_2 class II 16mA drive

SSTL25D_I

Differential SSTL_2 class I 8mA drive

Differential SSTL_2 class II 16mA drive

SSTL_1.8 class I

SSTL25D_II

SSTL18_I

SSTL18_II

SSTL_1.8 class II 8mA drive

SSTL18D_I

Differential SSTL_1.8 class I

SSTL18D_II

Differential SSTL_1.8 class II 8mA drive

LVTTL 4mA drive

LVTTL33_4mA

LVTTL33_8mA

LVTTL33_12mA

LVTTL33_16mA

LVTTL33_20mA

LVCMOS33_4mA

LVCMOS33_8mA

LVCMOS33_12mA

LVCMOS33_16mA

LVCMOS33_20mA

LVCMOS25_4mA

LVCMOS25_8mA

LVCMOS25_12mA

LVCMOS25_16mA

LVCMOS25_20mA

LVCMOS18_4mA

LVCMOS18_8mA

LVCMOS18_12mA

LVCMOS18_16mA

LVCMOS15_4mA

LVCMOS15_8mA

LVCMOS12_2mA

LVCMOS12_6mA

LVCMOS33_4mA

LVCMOS33_8mA

LVCMOS33_12mA

LVCMOS33_16mA

LVCMOS33_20mA

LVTTL 8mA drive

LVTTL 12mA drive

LVTTL 16mA drive

LVTTL 20mA drive

LVCMOS 3.3 4mA drive, fast slew rate

LVCMOS 3.3 8mA drive, fast slew rate

LVCMOS 3.3 12mA drive, fast slew rate

LVCMOS 3.3 16mA drive, fast slew rate

LVCMOS 3.3 20mA drive, fast slew rate

LVCMOS 2.5 4mA drive, fast slew rate

LVCMOS 2.5 8mA drive, fast slew rate

LVCMOS 2.5 12mA drive, fast slew rate

LVCMOS 2.5 16mA drive, fast slew rate

LVCMOS 2.5 20mA drive, fast slew rate

LVCMOS 1.8 4mA drive, fast slew rate

LVCMOS 1.8 8mA drive, fast slew rate

LVCMOS 1.8 12mA drive, fast slew rate

LVCMOS 1.8 16mA drive, fast slew rate

LVCMOS 1.5 4mA drive, fast slew rate

LVCMOS 1.5 8mA drive, fast slew rate

LVCMOS 1.2 2mA drive, fast slew rate

LVCMOS 1.2 6mA drive, fast slew rate

LVCMOS 3.3 4mA drive, slow slew rate

LVCMOS 3.3 8mA drive, slow slew rate

LVCMOS 3.3 12mA drive, slow slew rate

LVCMOS 3.3 16mA drive, slow slew rate

LVCMOS 3.3 20mA drive, slow slew rate

3-33

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M Family Timing Adders^{1, 2, 3}(Continued)

Over Recommended Operating Conditions

Buffer Type

LVCMOS25_4mA

LVCMOS25_8mA

LVCMOS25_12mA

LVCMOS25_16mA

LVCMOS25_20mA

LVCMOS18_4mA

LVCMOS18_8mA

LVCMOS18_12mA

LVCMOS18_16mA

LVCMOS15_4mA

LVCMOS15_8mA

LVCMOS12_2mA

LVCMOS12_6mA

PCI33

Description

-7

-6

-5

Units

ns

LVCMOS 2.5 4mA drive, slow slew rate

LVCMOS 2.5 8mA drive, slow slew rate

LVCMOS 2.5 12mA drive, slow slew rate

LVCMOS 2.5 16mA drive, slow slew rate

LVCMOS 2.5 20mA drive, slow slew rate

LVCMOS 1.8 4mA drive, slow slew rate

LVCMOS 1.8 8mA drive, slow slew rate

LVCMOS 1.8 12mA drive, slow slew rate

LVCMOS 1.8 16mA drive, slow slew rate

LVCMOS 1.5 4mA drive, slow slew rate

LVCMOS 1.5 8mA drive, slow slew rate

LVCMOS 1.2 2mA drive, slow slew rate

LVCMOS 1.2 6mA drive, slow slew rate

PCI33

2.18

2.19

1.50

1.60

1.43

2.22

1.93

1.43

1.47

2.32

1.84

2.52

1.69

0.04

2.26

2.35

1.66

1.59

1.39

2.27

2.08

1.51

1.46

2.38

1.98

2.63

1.83

0.04

2.33

2.51

1.82

1.58

1.34

2.32

2.23

1.58

1.45

2.43

2.12

2.74

1.96

0.04

1. Timing Adders are characterized but not tested on every device.

2. LVCMOS timing measured with the load speciﬁed in Switching Test Condition table.

3. All other standards tested according to the appropriate speciﬁcations.

4. These timing adders are measured with the recommended resistor values.

Timing v.A 0.11

3-34

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysCLOCK GPLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Without external capacitor

With external capacitor^{5, 6}

Without external capacitor

With external capacitor⁵

Without external capacitor

With external capacitor⁵

Min.

20

Typ.

—

Max.

420

50

Units

MHz

f

Input Clock Frequency (CLKI, CLKFB)

IN

2

20

Output Clock Frequency (CLKOP,

CLKOS)

OUT

5

0.156

0.039

640

20

210

25

f

K-Divider Output Frequency (CLKOK)

PLL VCO Frequency

OUT2

VCO

PFD

1280

420

50

Without external capacitor

With external capacitor^{5, 6}

Phase Detector Input Frequency

2

AC Characteristics

t

Output Clock Duty Cycle

Default duty cycle selected³

45

—

50

—

55

0.05

125

0.025

0.04

250

—

%

UI

DT

PH

4

Output Phase Accuracy

Output Clock Period Jitter

f

≥ 100 MHz

—

ps

OUT

1

t

50 ≤ f

< 100 MHz

—

UIPP

ps

OPJIT

OUT

f

< 50 MHz

—

130

—

OUT

t

Input Clock to Output Clock Skew

N/M = integer

—

SK

Output Clock Pulse Width

At 90% or 10%

1

ns

W

Without external capacitor

With external capacitor⁵

—

150

500

360

200

10

µs

2

t

PLL Lock-in Time

LOCK

—

µs

t

Programmable Delay Unit

Input Clock Period Jitter

External Feedback Delay

Input Clock High Time

85

—

ps

PA

ps

IPJIT

—

ns

FBKDLY

HI

90% to 90%

10% to 10%

0.5

15

500

20

—

ns

Input Clock Low Time

—

ns

LO

RST Pulse Width (RESETM/RESETK)

—

ns

t

Without external capacitor

With external capacitor⁵

—

ns

RST

Reset Signal Pulse Width (CNTRST)

—

µs

1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.

2. Output clock is valid after t for PLL reset and dynamic delay adjustment.

LOCK

3. Using LVDS output buffers.

4. Relative to CLKOP.

5. Value of external capacitor: 5.6 nF 20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.

6. f (max) = f * 10 for f < 5MHz.

OUT

IN

Timing v.A 0.11

3-35

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

sysCLOCK SPLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Without external capacitor

With external capacitor^{5, 6}

Without external capacitor

With external capacitor⁵

Without external capacitor

With external capacitor⁵

Min.

33

Typ.

—

Max.

420

50

Units

MHz

f

Input Clock Frequency (CLKI, CLKFB)

IN

2

33

f

Output Clock Frequency (CLKOP, CLKOS)

OUT

5

0.258

0.039

640

33

210

25

f

K-Divider Output Frequency (CLKOK)

PLL VCO Frequency

OUT2

VCO

PFD

1280

420

50

Without external capacitor

With external capacitor⁶

Phase Detector Input Frequency

2

AC Characteristics

t

Output Clock Duty Cycle

Default Duty Cycle Selected³

45

—

50

—

55

0.05

125

0.025

0.04

250

—

%

UI

DT

PH

4

Output Phase Accuracy

Output Clock Period Jitter

f

≥ 100 MHz

—

ps

OUT

1

t

50 ≤ f

< 100 MHz

—

UIPP

ps

OPJIT

OUT

f

< 50 MHz

—

OUT

t

Input Clock to Output Clock Skew

Divider Ratio = Integer

At 90% or 10%

—

SK

Output Clock Pulse Width

1

ns

W

Without external capacitor

With external capacitor⁵

—

150

500

200

10

µs

2

t

PLL Lock-in Time

LOCK

IPJIT

—

µs

t

Input Clock Period Jitter

External Feedback Delay

Input Clock High Time

—

ps

—

ns

FBKDLY

HI

90% to 90%

10% to 10%

0.5

15

500

20

—

ns

Input Clock Low Time

—

ns

LO

RST Pulse Width (RESETM/RESETK)

—

ns

t

Without external capacitor

With external capacitor⁵

—

ns

RST

Reset Signal Pulse Width (CNTRST)

—

µs

1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.

2. Output clock is valid after t for PLL reset and dynamic delay adjustment.

LOCK

3. Using LVDS output buffers.

4. Phase accuracy of CLKOS compared to CLKOP.

5. Value of external capacitor: 5.6 nF 20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.

6. f (max) = f * 10 for f < 5MHz.

OUT

IN

Timing v.A 0.11

3-36

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

DLL Timing

Over Recommended Operating Conditions

Parameter

Description

Min.

100

25

Typ.

—

Max.

500

250

Units

MHz

f

t

Input reference clock frequency (on-chip or off-chip)

Feedback clock frequency (on-chip or off-chip)

Output clock frequency, CLKOP

REF

—

MHz

FB

1

2

—

MHz

CLKOP

CLKOS

PJIT

Output clock frequency, CLKOS

—

MHz

Output clock period jitter (clean input)

Output clock cycle to cycle jitter (clean input)

—

ps p-p

CYJIT

Output clock duty cycle (at 50% levels, 50% duty cycle input clock,

50% duty cycle circuit turned off, time reference delay mode)

t

35

40

65

60

%

DUTY

Output clock duty cycle (at 50% levels, arbitrary duty cycle input

clock, 50% duty cycle circuit enabled, time reference delay mode)

t

DUTYTRD

DUTYCIR

Output clock duty cycle (at 50% levels, arbitrary duty cycle input

clock, 50% duty cycle circuit enabled, clock injection removal

mode)

t

40

—

60

%

Output clock to clock skew between two outputs with the same

phase setting

3

—

100

ps

SKEW

t

Input clock minimum pulse width high (at 80% level)

Input clock minimum pulse width low (at 20% level)

Input clock rise and fall time (20% to 80% levels)

Input clock period jitter

750

—

42

6

—

ps

PWH

PWL

t , t

—

1

ns

R

F

t

—

+/-250

—

ps

INSTB

LOCK

RSWD

PA

DLL lock time

18,500

3

cycles

ns

Digital reset minimum pulse width (at 80% level)

Delay step size

—

16.5

2.376

9.504

59.4

8.553

34.214

ps

Max. delay setting for single delay block (144 taps)

Max. delay setting for four chained delay blocks

ns

RANGE1

24

ns

RANGE4

1. CLKOP runs at the same frequency as the input clock.

2. CLKOS minimum frequency is obtained with divide by 4.

3. This is intended to be a “path-matching” design guideline and is not a measurable speciﬁcation.

Timing v.A 0.11

3-37

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

SERDES High Speed Data Transmitter(LatticeECP2M Family Only)^{1, 2}

Table 3-7. Serial Output Timing and Levels

Symbol

Description

Frequency

0.25 to 3.125 Gbps

—

Min.

—

Typ.

1.25

1.4

1.0

1.2

0.8

70

Max.

—

Units

V, p-p

V

Differential swing (1.25V setting)^{1, 2}

Differential swing (1.4V setting)^{1, 2}

Differential swing (1.0V setting)^{1, 2}

Differential swing (1.2V setting)^{1, 2}

Output common mode voltage

Rise time (20% to 80%)

TX-DIFF-P-P-1.25

TX-DIFF-P-P-1.4

TX-DIFF-P-P-1.0

TX-DIFF-P-P-1.2

OCM

—

T

—

ps

TX-R

Fall time (80% to 20%)

—

70

—

ps

TX-F

Output Impedance 50/75/HiZ K Ohms

(single ended)

50/75

HiZ

Z

—

Ohms

dB

TX-OI-SE

R

Return loss (with package)

9

LTX-RL

1. All measurements are with 50 ohm impedance.

2. See technical note TN1124, LatticeECP2/M SERDES/PCS Usage Guide for actual binary settings and the min-max range.

Table 3-8. Channel Output Jitter

Description

Deterministic

Frequency

3.125 Gbps

Min.

—

Typ.

0.08

0.22

0.33

0.05

0.17

0.24

0.03

0.10

0.15

0.04

0.12

0.15

Max.

0.12

0.38

0.43

0.11

0.30

0.39

0.11

0.18

0.29

0.17

0.13

0.29

Units

UI, p-p

Random

Total

3.125 Gbps

2.5Gbps

Deterministic

Random

Total

2.5Gbps

Deterministic

Random

Total

1.25 Gbps

250 Mbps

Deterministic

Random

Total

Note: Values are measured with PRBS 2⁷-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock @

10X mode.

3-38

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 3-9. SERDES/PCS Latency Breakdown (Parallel Clock Cycle)

Item

Description

Min.

Average

Max.

Bypass

Transmit Data Latency

T1

T2

T3

T4

FPGA Bridge Transmit²

1

2

3

2

5

2

1

8b10b Encoder

SERDES Bridge Transmit

Serializer³

2

2.4

Receive Data Latency

R1

R2

R3

R4

R5

R6

Deserializer³

1.2

2

SERDES Bridge Receive

Word Alignment

2

4

1

7

1

2

4

1

0

1

4

8b10b Decoder

1

Clock Tolerance Compensation

FPGA Bridge Receive²

15

3

23

5

1. PCS internal Parallel Clock. This clock rate is same as the rxfullclk in table 8-6.

2. FPGA Bridge latency varies by UP/DOWN Sample FIFO read/write. These numbers were presented for

8bit/10bit interface. The depth of Down Sample/Up Sample FIFO is 4. The earliest read can be done after

write clock cycle (1 clock) in Down Sample FIFO. The latest read will be done after the FIFO is full (4 + 1

= 5). For 16b/20b interface, the numbers become doubled. Min = 2, Max = 10. This latency depends on

the internal FIFO ﬂag operation.

3. The maximum latency applies to bit0.

Bit1 latency = Bit0 latency + 1 UI.

Bit2 latency = Bit0 latency + 2 UI.

Figure 3-12.Transmitter and Receiver Block Diagram

SERDES

SERDES Bridge

Recovered Clock

FPGA Core

PCS

FPGA Bridge

REFCLK

FPGA

EBRD Clock

R4

R5

R3

R6

R1

R2

WA

DEC

Elastic

Buffer

FIFO

HDINPi

HDINNi

Down

Sample

FIFO

Receive Data

Deserializer

1:8/1:10

Polarity

Adjust

EQ

CDR

BYPASS

Receiver

REFCLK

BYPASS

FPGA

Receive Clock

Transmit Clock

TX PLL

T2

T1

T3

T4

Encoder

Up

Sample

FIFO

Polarity

Adjust

Transmit Data

HDOUTPi

HDOUTNi

Serializer

8:1/10:1

BYPASS

Transmitter

FPGA

Transmit Clock

3-39

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

SERDES High Speed Data Receiver (LatticeECP2M Family Only)

Table 3-10. Serial Input Data Speciﬁcations

Symbol

Description

Min.

Typ.

Max.

Units

Stream of nontransitions¹

7 @ 3.125 Gbps

20 @ 1.25 Gbps

RX-CID

Bits

(CID = Consecutive Identical Digits) @ 10^-12BER

Differential input sensitivity

S

V

T

100

0

—

50

9

—

mV, p-p

V

RX-DIFF-S

Input levels

V

+ 0.8

RX-IN

CCRX

Input common mode range (DC coupled)

Input common mode range (AC coupled)³

CDR re-lock time²

0.5

0

1.2

1.5

V

RX-CM-DC

RX-CM-AC

V

—

3000

Bits

Ohms

dB

RX-RELOCK

RX-TERM

Z

Input termination 50/75 Ohm/High Z

Return loss (without package)

RL

—

RX-RL

1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.

2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data.

3. AC coupling is used to interface to LVPECL and LVDS.

Input Data Jitter Tolerance

A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-

dards have recognized the dependency on jitter type and have recently modiﬁed speciﬁcations to indicate toler-

ance levels for different jitter types as they relate to speciﬁc protocols (e.g. FC, etc.). Sinusoidal jitter is considered

to be a worst case jitter type.

Table 3-11. Receiver Total Jitter Tolerance Speciﬁcation¹

Description

Deterministic

Random

Total

Frequency

Condition

Min.

—

Typ.

—

Max.

0.54

0.26

0.80

0.61

0.22

0.81

0.53

0.22

0.80

0.42

0.10

0.60

Units

UI, p-p

600 mV differential eye

3.125 Gbps 600 mV differential eye

600 mV differential eye

Deterministic

Random

Total

600 mV differential eye

2.5 Gbps

600 mV differential eye

Deterministic

Random

Total

1.25 Gbps 600 mV differential eye

600 mV differential eye

Deterministic

Random

Total

600 mV differential eye

250 Mbps²600 mV differential eye

600 mV differential eye

1. Values are measured with PRBS 2⁷-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,

room temperature.

2. Jitter speciﬁcation is limited by measurement equipment capability.

Table 3-12. Periodic Receiver Jitter Tolerance Speciﬁcation¹

Description

Frequency

3.125 Gbps 600 mV differential eye

2.5 Gbps 600 mV differential eye

Condition

Min.

—

Typ.

—

Max.

0.20

0.22

0.20

0.08

Units

UI, p-p

—

Periodic

1.25 Gbps 600 mV differential eye

250 Mbps²600 mV differential eye

—

1. Values are measured with PRBS 2⁷-1, all channels operating.

2. Jitter speciﬁcation is limited by measurement equipment capability.

3-40

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

SERDES External Reference Clock (LatticeECP2M Family Only)

The external reference clock selection and its interface are a critical part of system applications for this product.

Table 3-13 speciﬁes reference clock requirements, over the full range of operating conditions.

Table 3-13. External Reference Clock Speciﬁcation (refclkp/refclkn)

Symbol

Description

Frequency range

Min.

25

Typ.

—

Max.

320

Units

MHz

ppm

mV, p-p

V

F

REF

REF-PPM

Frequency tolerance

Input swing, single-ended clock¹

-300

100

0

—

300

V

—

1200

REF-IN-SE

REF-IN

Input levels

—

V

+ 0.8

CCP

Input common mode range (DC coupled)

Input common mode range (AC coupled)²

Duty cycle³

0.5

0

—

1.2

1.5

V

REF-CM-DC

REF-CM-AC

—

V

D

40

—

60

%

REF

T

Z

Rise time (20% to 80%)

Fall time (80% to 20%)

Input termination

500

50/2K

—

1000

ps

REF-R

ps

REF-F

Ohms

pF

REF-IN-TERM

C

Input capacitance⁴

—

1.5

REF-IN-CAP

1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same

gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.

2. When AC coupled, the input common mode range is determined by:

(Min input level) + (Peak-to-peak input swing)/2 ≤ (Input common mode voltage) ≤ (Max input level) - (Peak-to-peak input swing)/2

3. Measured at 50% amplitude.

4. Input capacitance of 1.5pF is total capacitance, including both device and package.

Figure 3-13. Jitter Transfer

5.00

0.00

Jitter T.

Gain@25°C,1.20V,

PJ=100ps

-5.00

-10.00

-15.00

-20.00

-25.00

0.1

1

10

100

Frequency (MHz)

Note: This graph is for a nominal device.

SERDES Power-Down/Power-Up Speciﬁcation

Table 3-14. Power-Down and Power-Up Speciﬁcation

Symbol

Description

Max.

10

Units

s

t

Power-down time after all power down register bitsset to ‘0’

Power-up time after all power down register bits set to ‘1’

PWRDN

PWRUP

5

ms

3-41

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

PCI Express Electrical and Timing Characteristics

AC and DC Characteristics

Table 3-15.Transmit^{1, 2}

Symbol

Description

Unit interval

Test Conditions

Min

Typ

Max

Units

UI

399.88

400

400.12

ps

Differential peak-to-peak output

voltage

V

0.8

0

1.0

-3.5

20

1.2

-7.96

—

V

TX-DIFF_P-P

De-emphasis differential output

voltage ratio

dB

mV

V

TX-DE-RATIO

TX-CM-AC_P

RMS AC peak common-mode out-

put voltage

—

0

Maximum Common mode voltage

delta between n and p channels

—

25

TX-CM-DC-LINE-DELTA

TX-DC-CM

V

+

CCOB

5%

Tx DC common mode voltage

Output short circuit current

—

V

=0.0V

TX-D+

TX-D-

I

—

90

mA

TX-SHORT

Z

T

Differential output impedance

Tx output rise time

80

100

—

120

—

Ohms

UI

TX-DIFF-DC

20 to 80%

0.125

TX-RISE

Tx output fall time

—

UI

TX-FALL

Lane-to-lane static output skew for

all lanes in port/link

L

—

1.3

ns

TX-SKEW

T

Transmitter eye width

0.75

—

UI

nF

TX-EYE

3

T

0.125

200

TX-EYE-MEDIAN-TO-MAX-JITTER

C

AC coupling capacitor

75

TX

1. Values are measured at 2.5 Gbps.

2. Compliant to PCI Express v1.1.

3. Measured at 60ps with plug-in board and jitter due to socket removed.

Table 3-16. Receive

Symbol

Description

Unit Interval

Test Conditions Min.

Typ.

Max.

Units

UI

399.88

400

400.12

ps

Differential peak-to-peak input

voltage

V

0.175

—

V

RX-DIFF_P-P

V

Idle detect threshold voltage

DC differential input impedance

DC input impedance

65

80

—

100

50

—

175

120

60

mV

Ohms

UI

RX-IDLE-DET-DIFF_P-P

RX-DIFF-DC

Z

T

40

RX-DC

1

Power-down DC input impedance

Receiver eye width

200K

0.4

—

RX-HIGH-IMP-DC

—

RX-EYE

—

0.3

UI

RX-EYE-MEDIAN-TO-MAX-JITTER

Notes:

1. Measured with external AC-coupling on the receiver

2. Values are measured at 2.5 Gbps

3-42

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Table 3-17. Reference Clock

Symbol

Description

Test Conditions

Min.

—

Typ.

100

0.65

—

Max.

—

Units

MHz

V

F

Reference clock frequency

Input common mode voltage

Clock input rise/fall time

Differential input voltage swing

Input clock duty cycle

REFCLK

V

—

CM

T /T

—

1.0

1.6

60

ns

R

F

V

0.6

40

—

V

SW

DC

50

%

REFCLK

PPM

Reference clock tolerance

-300

—

+300

ppm

3-43

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M sysCONFIG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Parameter

Description

Min.

Max.

Units

sysCONFIG Byte Data Flow

t

Byte D[0:7] Setup Time to CCLK

7

1

—

12

—

12

ns

SUCBDI

HCBDI

CODO

SUCS

HCS

Byte D[0:7] Hold Time to CCLK

CCLK to DOUT in Flowthrough Mode

CSN[0:1] Setup Time to CCLK

CSN[0:1] Hold Time to CCLK

Write Signal Setup Time to CCLK

Write Signal Hold Time to CCLK

CCLK to BUSY Delay Time

—

7

1

7

SUWD

HWD

1

—

DCB

CCLK to Out for Read Data

CORD

sysCONFIG Byte Slave Clocking

t

Byte Slave CCLK Minimum High Pulse

Byte Slave CCLK Minimum Low Pulse

Byte Slave CCLK Cycle Time

6

9

—

ns

BSCH

BSCL

15

BSCYC

sysCONFIG Serial (Bit) Data Flow

t

DI Setup Time to CCLK Slave Mode

DI Hold Time to CCLK Slave Mode

CCLK to DOUT in Flowthrough Mode

7

1

—

12

ns

SUSCDI

HSCDI

CODO

—

sysCONFIG Serial Slave Clocking

t

Serial Slave CCLK Minimum High Pulse

Serial Slave CCLK Minimum Low Pulse

6

—

ns

SSCH

SSCL

sysCONFIG POR, Initialization and Wake-up

t

Minimum Vcc to INITN High

Time from t to Valid Master CCLK

—

25

—

120

28

2

ms

us

ICFG

VMC

ICFG

PROGRAMN Pin Pulse Rejection

8

ns

PRGMRJ

PRGM

PROGRAMN Low Time to Start Conﬁguration

PROGRAMN High to INITN High Delay

—

1

ns

ms

ns

DINIT

Delay Time from PROGRAMN Low to INITN Low

Delay Time from PROGRAMN Low to DONE Low

User I/O Disable from PROGRAMN Low

37

35

25

—

DPPINIT

DPPDONE

IODISS

IOENSS

MWC

ns

User I/O Enabled Time from CCLK Edge During Wake-up Sequence

Additional Wake Master Clock Signals after DONE Pin High

ns

cycles

sysCONFIG SPI Port

t

INITN High to CCLK Low

—

1

µs

us

ns

CFGX

INITN High to CSSPIN Low

—

2

CSSPI

CSCCLK

SOCDO

SOE

CCLK Low before CSSPIN Low

CCLK Low to Output Valid

0

—

15

CSSPIN[0:1] Active Setup Time

CSSPIN[0:1] Low to First CCLK Edge Setup Time

300

—

300+3cyc

600+6cyc

CSPID

Max. CCLK Frequency - SPI Flash Read Opcode (0x03)

(SPIFASTN = 1)

—

20

50

MHz

f

MAXSPI

Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)

(SPIFASTN = 0)

3-44

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2/M sysCONFIG Port Timing Speciﬁcations (Continued)

Over Recommended Operating Conditions

Parameter

Description

SOSPI Data Setup Time Before CCLK

SOSPI Data Hold Time After CCLK

Min.

Max.

—

Units

ns

t

7

2

SUSPI

—

ns

HSPI

Timing v.A 0.11

Parameter

Min.

Selected value - 30%

40

Max.

Selected value + 30%

60

Units

MHz

%

Master Clock Frequency

Duty Cycle

Timing v.A 0.11

Figure 3-14. sysCONFIG Parallel Port Read Cycle

t_BSCYC

t_BSCH

t_BSCL

CCLK

t_SUCS

t_HCS

CS1N

CSN

t_SUWD

t_HWD

WRITEN

t_DCB

BUSY

t_CORD

Byte 1

Byte 0

Byte 2

Byte n*

D[0:7]

*n = last byte of read cycle.

Figure 3-15. sysCONFIG Parallel Port Write Cycle

t_BSCL

t_BSCH

CCLK

t_SUCS

t_HCS

CS1N

CSN

t_SUWD

t_HWD

WRITEN

t_DCB

BUSY

t_HCBDI

Byte 1

t_SUCBDI

Byte 0

Byte 2

Byte n*

D[0:7]

*n = last byte of write cycle.

3-45

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 3-16. sysCONFIG Slave Serial Port Timing

t_SSCL

t_SSCH

CCLK (input)

t_HSCDI

t_SUSCDI

DIN

DOUT

t_CODO

Figure 3-17. Power-On-Reset (POR) Timing

V

/ V

/

CC

CCIO8

CCAUX

1

t_ICFG

INITN

DONE

CCLK ²

t_VMC

CFG[2:0] ³

Valid

1. Time taken from V , V

or V

, whichever is the last to cross the POR trip point.

CC CCAUX

CCIO8

2. Device is in a Master Mode (SPI, SPIm).

3. The CFG pins are normally static (hard wired).

Figure 3-18. Conﬁguration from PROGRAMN Timing

t_PRGMRJ

PROGRAMN

t_DINIT

t_DPPINIT

INITN

t_DINITD

DONE

CCLK

CFG[2:0]¹

Valid

t_IODISS

USER I/O

1. The CFG pins are normally static (hard wired)

3-46

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Figure 3-19. Wake-Up Timing

PROGRAMN

INITN

Wake-Up

DONE

t_MWC

CCLK

t_IOENSS

USER I/O

Figure 3-20. SPI/SPIm Conﬁguration Waveforms

Capture CR0 & CIB

Capture CFGx and SPIFASTN

VCC

PROGRAMN

DONE

INITN

SPIFASTN

CSSPI0N

CSSPI1N

0

1

2

3

…

7

8

9

10

…

31 32 33 34

… 127 128

CCLK

Opcode

Address

SISPI/BUSY

SPID0

Ignore

Valid Bitstream

3-47

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Symbol

Parameter

Min

—

40

20

8

Max

25

—

Units

MHz

ns

f

t

TCK clock frequency

MAX

TCK [BSCAN] clock pulse width

BTCP

TCK [BSCAN] clock pulse width high

—

ns

BTCPH

BTCPL

BTS

TCK [BSCAN] clock pulse width low

—

ns

TCK [BSCAN] setup time

—

ns

TCK [BSCAN] hold time

10

50

—

8

—

ns

BTH

TCK [BSCAN] rise/fall time

—

mV/ns

ns

BTRF

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enable

BSCAN test capture register setup time

10

—

BTCO

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

BUTCO

BTUODIS

BTUPOEN

ns

BSCAN test capture register hold time

25

—

ns

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

25

ns

Timing v.A 0.11

Figure 3-21. JTAG Port Timing Waveforms

TMS

TDI

t

BTH

BTS

t

BTCP

BTCPL

BTCPH

TCK

TDO

t

BTCODIS

t

BTCO

BTCOEN

Valid Data

t

BTCRH

t

BTCRS

Data to be

captured

from I/O

Data Captured

t

BTUPOEN

BUTCO

BTUODIS

Data to be

driven out

to I/O

Valid Data

3-48

DC and Switching Characteristics

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Switching Test Conditions

Figure 3-23 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-18.

Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards

V_T

R1

DUT

Test Point

R2

CL*

*CL Includes Test Fixture and Probe Capacitance

Table 3-18. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R

C

Timing Ref.

V

T

1

2

L

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = V

LVCMOS 1.8 = V

LVCMOS 1.5 = V

LVCMOS 1.2 = V

/2

CCIO

LVTTL and other LVCMOS settings (L -> H, H -> L)

0pF

∞

LVCMOS 2.5 I/O (Z -> H)

LVCMOS 2.5 I/O (Z -> L)

LVCMOS 2.5 I/O (H -> Z)

LVCMOS 2.5 I/O (L -> Z)

∞

1MΩ

∞

1MΩ

∞

V

/2

CCIO

V

CCIO

100

- 0.10

+ 0.10

—

OH

OL

100

∞

CCIO

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-49

LatticeECP2/M Family Data Sheet

Pinout Information

August 2008

Data Sheet DS1006

Signal Descriptions

Signal Name

I/O

Description

General Purpose

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-

ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

P[Edge] [Row/Column Number*]_[A/B]

I/O

[A/B] indicates the PIO within the PIC to which the pad is connected. Some of

these user-programmable pins are shared with special function pins. These

pins, when not used as special purpose pins, can be programmed as I/Os for

user logic. During conﬁguration the user-programmable I/Os are tri-stated

with an internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor enabled

after conﬁguration.

GSRN

NC

I

Global RESET signal (active low). Any I/O pin can be GSRN.

No connect.

—

GND

Ground. Dedicated pins.

V

Power supply pins for core logic. Dedicated pins.

CC

Auxiliary power supply pin. This dedicated pin powers all the differential and

referenced input buffers.

—

CCAUX

CCIOx

CCPLL

Dedicated power supply pins for I/O bank x.

PLL supply pins. Should be tied to V even when the corresponding PLL is

CC

unused.

Reference supply pins for I/O bank x. Pre-determined pins in each bank are

V

, V

—

REF1_x REF2_x

assigned as V

inputs. When not used, they may be used as I/O pins.

REF

XRES⁴

PLLCAP⁴

—

10K ohm +/-1% resistor must be connected between this pad and ground.

External capacitor connection for PLL.

PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

[LOC][num]_V

—

Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center.

CCPLL

General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row

from center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_GPLL[T, C]_IN_A

[LOC][num]_GPLL[T, C]_FB_A

[LOC][num]_SPLL[T, C]_IN_A

[LOC][num]_SPLL[T, C]_FB_A

[LOC][num]_DLL[T, C]_IN_A

[LOC][num]_DLL[T, C]_FB_A

PCLK[T, C]_[n:0]_[3:0]

I

Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

I

Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row

from center, T = true and C = complement, index A,B,C...at each side.

DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and

C = complement, index A,B,C...at each side.

Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0,1,2,3 within bank.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

4-1

DS1006 Pinout Information_01.9

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball

function number.

[LOC]DQS[num]

I/O

DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated

DQS number.

[LOC]DQ[num]

Test and Programming (Dedicated Pins)

Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during conﬁguration.

TMS

I

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

TCK

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for conﬁguration by sending

appropriate command. (Note: once a conﬁguration port is selected it is

locked. Another conﬁguration port cannot be selected until the power-up

sequence). Pull-up is enabled during conﬁguration.

TDI

I

TDO

O

Output pin. Test Data Out pin used to shift data out of a device using 1149.1.

Power supply pin for JTAG Test Access Port.

VCCJ

—

Conﬁguration Pads (Used During sysCONFIG)

Mode pins used to specify conﬁguration mode values latched on rising edge

of INITN. During conﬁguration, a pull-up is enabled. These are dedicated

pins.

CFG[2:0]

I

Open Drain pin. Indicates the FPGA is ready to be conﬁgured. During conﬁg-

uration, a pull-up is enabled. It is a dedicated pin.

INITN

I/O

I

Initiates conﬁguration sequence when asserted low. This pin always has an

active pull-up. This is a dedicated pin.

PROGRAMN

DONE

Open Drain pin. Indicates that the conﬁguration sequence is complete, and

the startup sequence is in progress. This is a dedicated pin.

I/O

CCLK

I/O Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

I/O Read control command in SPI or SPIm mode.

BUSY/SISPI

sysCONFIG chip select (active low). During conﬁguration, a pull-up is

enabled.

CSN

I

sysCONFIG chip select (active low). During conﬁguration, a pull-up is

enabled.

CS1N

I

WRITEN

I

Write Data on Parallel port (active low).

sysCONFIG Port Data I/O for Parallel mode.

D[0]/SPIFASTN

I/O

sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm

mode, this pin should either be tied high or low, must not be left ﬂoating.

D[1:6]

I/O sysCONFIG Port Data I/O for Parallel

D[7]/SPID0

I/O sysCONFIG Port Data I/O for Parallel, SPI, SPIm

Output for serial conﬁguration data (rising edge of CCLK) when using

sysCONFIG port.

DOUT/CSON

O

Input for serial conﬁguration data (clocked with CCLK) when using sysCON-

I/O FIG port. During conﬁguration, a pull-up is enabled. Output when used in SPI/

SPIm modes.

DI/CSSPI0N

Dedicated SERDES Signals^{1, 2, 3}

Termination resistor switching power (3.3V). This pin must be tied to 3.3V

even if the quad is unused.

[LOC]_SQ_VCCAUX33

—

[LOC]_SQ_REFCLKN

[LOC]_SQ_REFCLKP

I

Negative Reference Clock Input

Positive Reference Clock Input

PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V

even if the quad is unused.

[LOC]_SQ_VCCP

—

4-2

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

Input buffer power supply, channel m (1.2V/1.5V). This pin should be left ﬂoat-

ing if the channel is unused.

[LOC]_SQ_VCCIBm

—

Output buffer power supply, channel m (1.2V/1.5V). This pin should be left

ﬂoating if the channel is unused.

[LOC]_SQ_VCCOBm

[LOC]_SQ_HDOUTNm

[LOC]_SQ_HDOUTPm

[LOC]_SQ_HDINNm

[LOC]_SQ_HDINPm

O

I

High-speed output, negative channel m

High-speed output, positive channel m

High-speed input, negative channel m

High-speed input, positive channel m

I

Transmitter power supply, channel m (1.2V). This pin must be tied to 1.2V

even if the channel is unused.

[LOC]_SQ_VCCTXm⁴

—

Receiver power supply, channel m (1.2V).This pin must be tied to 1.2V even if

the channel is unused.

[LOC]_SQ_VCCRXm⁴

1. These signals are relevant for LatticeECP2M family.

2. m deﬁnes the associated channel in the Quad.

3. These signals are deﬁned in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower

left), LRC (lower right).

4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,

care must be given. For more information, refer to technical note TN1159, LatticeECP2/M Pin Assignment Recommendations.

4-3

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin

PICs Associated with

DQS Strobe

DDR Strobe (DQS) and

Data (DQ) Pins

PIO Within PIC

For Left and Right Edges of the Device

A

DQ

P[Edge] [n-4]

B

A

DQ

P[Edge] [n-3]

B

DQ

A

DQ

P[Edge] [n-2]

B

DQ

A

DQ

P[Edge] [n-1]

B

DQ

A

[Edge]DQSn

DQ

P[Edge] [n]

B

A

DQ

P[Edge] [n+1]

B

DQ

A

DQ

P[Edge] [n+2]

B

DQ

A

DQ

P[Edge] [n+3]

B

DQ

For Bottom Edge of the Device

A

DQ

P[Edge] [n-4]

B

A

DQ

P[Edge] [n-3]

B

DQ

A

DQ

P[Edge] [n-2]

B

DQ

A

DQ

P[Edge] [n-1]

B

DQ

A

[Edge]DQSn

DQ

P[Edge] [n]

B

A

DQ

P[Edge] [n+1]

B

DQ

A

DQ

P[Edge] [n+2]

B

DQ

A

DQ

P[Edge] [n+3]

B

DQ

A

DQ

P[Edge] [n+4]

B

DQ

Notes:

1. “n” is a row PIC number.

2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits

of data for the left and right edges and up to 17 bits of data for the bottom edge. In some

packages, all the potential DDR data (DQ) pins may not be available. PIC numbering

deﬁnitions are provided in the “Signal Names” column of the Signal Descriptions table.

4-4

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12

LFE2-6

LFE2-12

144

256

144

208

256

484

Pin Type

TQFP

fpBGA

TQFP

PQFP

131

62

5

fpBGA

Single Ended User I/O

Differential Pair User I/O

90

43

5

190

93

45

5

193

297

95

96

148

TAP Pins

5

Conﬁguration

Muxed Pins

14

7

14

7

14

7

14

Dedicated Pins (Non TAP)

Muxed Pins

7

34

3

54

33

3

40

3

54

57

Non Conﬁguration

Dedicated Pins

3

VCC

10

4

7

10

4

14

8

7

16

VCCAUX

VCCPLL

4

16

0

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

1

2

1

2

4

1

2

1

2

4

1

2

1

2

4

1

2

1

2

4

VCCIO

1

2

1

2

4

1

2

1

2

4

1

2

1

2

1

2

4

1

2

1

2

GND, GND0 to GND7

NC

12

4

20

12

1

22

0

20

60

3

0

44

Bank0

8/4

17/8

4/2

8/4

18/9

8/4

9/4

12/6

6/2

0

18/6

34/17

20/10

12/6

32/16

14/7

26/13

20/10

14/7

0

8/4

18/9

4/2

8/4

18/9

10/5

9/4

12/6

6/2

0

18/9

11/5

19/9

18/9

18/8

12/6

6/2

0

18/9

34/17

20/10

12/6

32/16

17/8

26/13

20/10

14/7

0

50/25

46/23

24/12

16/8

46/23

32/16

23/11

14/7

0

Bank1

Bank2

Bank3

Single Ended/ Differential I/O

Pairs per Bank (including

emulated with resistors)

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0 (Top Edge)

Bank1 (Top Edge)

Bank2 (Right Edge)

Bank3 (Right Edge)

Bank4 (Bottom Edge)

Bank5 (Bottom Edge)

Bank6 (Left Edge)

Bank7 (Left Edge)

Bank8 (Right Edge)

0

1

5

1

4

5

6

3

4

True LVDS I/O Pairs per Bank

0

2

7

2

6

7

8

5

0

4-5

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.)

LFE2-6

LFE2-12

144

256

144

208

256

484

Pin Type

Bank0

TQFP

fpBGA

TQFP

PQFP

fpBGA

0

18

8

0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

1

0

1

0

Available DDR-Interfaces per I/O

Bank¹

2

0

2

3

1

0

1

3

1

0

1

0

1

0

PCI Capable I/Os per Bank

32

14

0

18

10

0

19

18

0

32

17

0

46

0

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1

DQSB + 8 DQs + 1 DM + Bank VREF1).

4-6

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35

LFE2-20

LFE2-35

208

PQFP

256

fpBGA

484

fpBGA

672

fpBGA

484

fpBGA

672

fpBGA

Pin Type

Single Ended User I/O

Differential Pair User I/O

131

62

5

193

331

402

331

450

224

5

96

165

200

165

TAP Pins

5

Conﬁguration

Muxed Pins

14

7

14

7

Dedicated Pins (Non TAP)

Muxed Pins

7

42

3

54

60

64

60

68

3

Non Conﬁguration

Dedicated Pins

3

VCC

14

8

7

18

24

16

22

16

2

VCCAUX

VCCPLL

4

16

0

2

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

2

4

5

4

5

2

4

5

4

5

2

4

5

4

5

2

4

5

4

5

VCCIO

2

4

5

2

4

5

4

5

2

4

5

4

5

2

5

2

1

2

GND, GND0 to GND7

NC

22

0

20

60

72

60

72

102

67/33

52/26

48/24

42/21

54/27

68/34

58/29

47/23

14/7

0

1

8

101

67/33

52/26

36/18

32/16

50/25

68/34

48/24

35/17

14/7

0

8

Bank0

18/9

11/5

19/9

18/9

18/8

12/6

6/2

0

18/9

34/17

20/10

12/6

32/16

17/8

26/13

20/10

14/7

0

50/25

46/23

34/17

22/11

46/23

40/20

33/16

14/7

0

50/25

46/23

34/17

22/11

46/23

40/20

33/16

14/7

0

Bank1

Bank2

Bank3

Single Ended/ Differential I/O

Pairs per Bank (including

emulated with resistors)

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0 (Top Edge)

Bank1 (Top Edge)

Bank2 (Right Edge)

Bank3 (Right Edge)

Bank4 (Bottom Edge)

Bank5 (Bottom Edge)

Bank6 (Left Edge)

Bank7 (Left Edge)

Bank8 (Right Edge)

0

4

5

9

12

9

3

5

8

5

True LVDS I/O Pairs per Bank

0

6

7

10

12

10

13

11

0

5

8

0

4-7

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.)

LFE2-20

LFE2-35

208

256

484

672

484

672

Pin Type

Bank0

PQFP

fpBGA

0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

0

1

2

3

0

2

0

2

Available DDR-Interfaces per I/O

Bank¹

0

2

3

0

1

3

4

3

4

0

1

2

3

1

3

0

1

2

3

0

PCI Capable I/Os per Bank

19

18

0

32

17

0

46

0

50

68

0

46

0

54

68

0

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1

DQSB + 8 DQs + 1 DM + Bank VREF1).

4-8

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70

LFE2-50

LFE2-70

Pin Type

484 fpBGA

672 fpBGA

900 fpBGA

Single Ended User I/O

Differential Pair User I/O

339

500

249

5

500

249

5

583

290

5

169

TAP Pins

5

Conﬁguration

Muxed Pins

14

7

14

7

14

Dedicated Pins (Non TAP)

Muxed Pins

7

68

79

3

79

3

89

Non Conﬁguration

Dedicated Pins

3

VCC

16

20

16

4

20

16

2

26

VCCAUX

VCCPLL

16

17

4

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

4

5

6

4

5

6

4

5

6

4

5

6

VCCIO

4

5

6

4

5

6

4

5

6

5

6

2

GND, GND0 to GND7

NC

60

72

3

72

5

104

101

84/42

76/38

74/37

48/24

72/35

80/40

64/32

71/35

14/7

0

Bank0

50/25

46/23

38/19

22/11

46/23

40/20

37/18

14/7

0

67/33

66/33

56/28

48/24

62/31

68/34

64/32

55/27

14/7

0

67/33

66/33

56/28

48/24

62/31

68/34

64/32

55/27

14/7

0

Bank1

Bank2

Bank3

Single Ended/ Differential I/O

Pairs per Bank (including

emulated with resistors)

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0 (Top Edge)

Bank1 (Top Edge)

Bank2 (Right Edge)

Bank3 (Right Edge)

Bank4 (Bottom Edge)

Bank5 (Bottom Edge)

Bank6 (Left Edge)

Bank7 (Left Edge)

Bank8 (Right Edge)

0

9

13

12

0

13

12

0

18

5

12

True LVDS I/O Pairs per Bank

0

10

16

12

0

16

12

0

16

8

16

0

4-9

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)

LFE2-50

LFE2-70

Pin Type

Bank0

484 fpBGA

672 fpBGA

900 fpBGA

0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

2

3

4

0

3

Available DDR-Interfaces per I/O

Bank¹

3

4

3

4

5

1

4

2

3

4

0

PCI Capable I/Os per Bank

46

0

62

68

0

62

68

0

72

80

0

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1

DQSB + 8 DQs + 1 DM + Bank VREF1).

4-10

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35

LFE2M20

LFE2M35

Pin Type

256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA

Single Ended User I/O

Differential Pair User I/O

140

304

140

303

410

199

5

70

152

70

151

TAP Pins

5

Conﬁguration

Muxed Pins

14

7

Dedicated Pins (Non TAP)

Muxed Pins

7

64

84

60

84

89

3

Non Conﬁguration

Dedicated Pins

3

VCC

6

16

6

16

29

17

8

VCCAUX

VCCPLL

4

8

4

8

1

4

1

4

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

1

4

1

4

5

3

4

2

4

2

4

5

2

5

VCCIO

2

4

2

4

2

4

2

4

5

2

4

2

4

5

2

4

2

4

5

1

2

1

2

GND, GND0 to GND7

NC

22

17

0/0

14/7

16/8

32/16

20/10

16/8

28/14

14/7

0

57

22

17

0/0

14/7

16/8

32/16

20/10

16/8

28/14

14/7

0

57

80

37

63/31

18/9

50/25

43/21

50/21

60/30

52/25

60/30

14/7

0

11

12

Bank0

36/18

18/9

30/15

36/18

62/31

28/14

40/20

14/7

0

36/18

18/9

30/15

36/18

62/31

28/14

39/19

40/20

14/7

0

Bank1

Bank2

Bank3

Single Ended/ Differential I/O

Pairs per Bank (including

emulated with resistors)

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0 (Top Edge)

Bank1 (Top Edge)

Bank2 (Right Edge)

Bank3 (Right Edge)

0

3

7

3

7

12

11

0

4

9

4

9

True LVDS I/O Pairs per Bank Bank4 (Bottom Edge)

Bank5 (Bottom Edge)

0

Bank6 (Left Edge)

4

10

4

10

14

15

0

Bank7 (Left Edge)

7

10

7

10

Bank8 (Right Edge)

0

4-11

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.)

LFE2M20

LFE2M35

Pin Type

Bank0

256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA

0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

0

1

0

1

3

0

1

0

1

2

Available DDR-Interfaces per

I/O Bank¹

2

4

2

4

3

1

2

1

2

3

0

3

0

1

2

1

2

1

2

3

0

PCI Capable I/Os per Bank

32

20

16

28

0

62

28

40

0

32

20

16

28

0

62

28

39

40

0

50

60

52

60

0

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1

DQSB + 8 DQs + 1 DM + Bank VREF1).

4-12

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and

LFE2M100

LFE2M50

LFE2M70

LFE2M100

Pin Type

Single Ended User I/O

484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA

270

135

5

372

185

5

410

205

5

416

208

5

436

218

5

416

207

5

520

260

5

Differential Pair User I/O

TAP Pins

Muxed Pins

14

Conﬁguration

Dedicated Pins

(Non TAP)

7

Muxed Pins

69

72

3

72

3

75

3

76

3

74

3

78

3

Non Conﬁguration

Dedicated Pins

3

VCC

16

20

26

8

62

44

16

4

44

16

4

44

VCCAUX

VCCPLL

8

18

12

4

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

4

5

6

7

6

7

3

4

6

7

6

7

4

5

9

5

9

VCCIO

4

6

7

6

7

4

5

6

7

6

7

4

5

9

4

5

9

2

GND, GND0 to GND7

NC

57

80

35

63/31

18/9

50/25

43/21

24/12

60/30

54/27

60/30

0/0

0

122

121

56/28

36/18

54/27

44/22

38/19

58/29

60/30

64/32

0/0

0

122

63

34/17

42/21

70/35

60/30

38/19

40/20

62/31

70/35

0/0

0

134

283

46/23

34/17

72/36

64/32

40/20

66/33

74/37

0/0

0

122

63

34/17

42/21

70/35

60/30

38/19

40/20

62/31

70/35

0/0

0

134

199

54/27

44/22

80/40

44/22

46/23

82/41

90/45

0/0

0

31

Bank0

36/18

18/9

30/15

36/18

42/21

28/14

40/20

0/0

0

Bank1

Bank2

Bank3

Single Ended/ Differential

I/O Pairs per Bank (includ-

ing emulated with resis-

tors)

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0 (Top Edge)

Bank1 (Top Edge)

Bank2 (Right Edge)

Bank3 (Right Edge)

Bank4 (Bottom Edge)

Bank5 (Bottom Edge)

Bank6 (Left Edge)

Bank7 (Left Edge)

Bank8 (Right Edge)

0

7

12

11

0

13

17

15

0

18

17

15

0

20

9

11

16

20

True LVDS I/O Pairs per

Bank

0

10

14

15

0

15

17

0

16

15

17

0

20

10

17

18

22

0

4-13

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100

(Cont.)

LFE2M50

LFE2M70

LFE2M100

Pin Type

Bank0

484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA

0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

Bank8

Bank0

Bank1

Bank2

Bank3

2

4

2

4

2

3

1

3

4

3

5

Available DDR-Interfaces

per I/O Bank¹

3

1

3

2

3

2

3

2

3

1

3

2

3

4

3

5

3

4

3

4

5

0

72

64

40

66

74

0

80

44

46

82

90

0

PCI Capable I/Os per Bank Bank4

50

60

52

60

0

24

60

54

60

0

48

50

60

68

0

48

40

62

70

0

48

40

62

70

0

Bank5

Bank6

Bank7

Bank8

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1

DQSB + 8 DQs + 1 DM + Bank VREF1).

4-14

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Available Device Resources by Package, LatticeECP2

Resource

Device

ECP2-6

256 fpBGA

484 fpBGA

672 fpBGA

900 fpBGA

4

—

4

—

4

—

8

ECP2-12

ECP2-20

ECP2-35

ECP2-50

ECP2-70

4

PLL/DLL

—

4

6

—

8

Available Device Resources by Package, LatticeECP2M

Resource

Device

256 fpBGA

484 fpBGA

672 fpBGA

900 fpBGA

1152 fpBGA

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

10

—

10

—

10

—

10

—

10

PLL/DLL

4-15

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Power Supply and NC

Signals

VCC

144 TQFP³

208 PQFP³

256 fpBGA⁴

484 fpBGA⁴

16, 22, 29, 48, 54, 83, 12, 19, 28, 40, 74, 80, LFE2-6: G7, G9, G10, LFE2-12/LFE2-20: N6, N18, J10,

94, 102, 128, 135

97, 116, 129, 140, 146, H7, J10, K10, K8

171, 188, 198

J11, J12, J13, K14, K9, L14, L9,

M14, M9, N14, N9, P10, P11, P12,

P13

LFE2-12/LFE2-20: G7,

G9, G10, H7, J10, K10,

K8

LFE2-35/LFE2-50: J10, J11, J12,

J13, K14, K9, L14, L9, M14, M9,

N14, N9, P10, P11, P12, P13

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCJ

139

195, 206

162, 170

143, 148

123, 135

93, 100

55, 63

C5, E7

C12, E10

E14, G12

K12, M14

M10, P12

M7, P5

K5, M3

E3, G5

T15

G10, G9, H8, H9

G11, G12, G13, G14

H14, H15, J15, K16

L16, M16, N16, P16

R14, T12, T13, T14

R9, T10, T11, T9

N7, P7, P8, R8

J8, K7, L7, M7

P15, R15

117

106

89

64

42

31

38, 44

9

10, 14

85

113, 118

51

35

K7

T8

VCCAUX

6, 39, 90, 142

7, 30, 70, 86, 125, 151, G8, H10, J7, K9

174, 190

G5, K5, R5, V7, V11, V8, V13, V15,

M17, P17, E17, G18, D11, F13,

C5, E6

VCCPLL

GND¹

None

LFE2-12/LFE2-20: None

LFE2-35: N6, N18

LFE2-50: N6, N18, K6, J16

11, 21, 30, 47, 51, 61, 5, 13, 17, 25, 32, 42, 60, A1, A16, B12, B5, C8, A22, AA19, AA4, AB1, AB22, B19,

81, 95, 105, 120, 133, 68, 77, 81, 89, 102, 115, E15, E2, H14, H8, H9, B4, C14, C9, D2, D21, F17, F6,

138

122, 139, 145, 159, 169, J3, J8, J9, M15, M2, P9, H10, H11, H12, H13, J14, J20, J3,

175, 184, 192, 201

R12, R5, T1, T16

J9, K10, K11, K12, K13, K15, K8,

L10, L11, L12, L13, L15, L8, M10,

M11, M12, M13, M15, M8, N10,

N11, N12, N13, N15, N8, P14,

P20, P3, P9, R10, R11, R12, R13,

U17, U6, W2, W21, Y14, Y9, A1

NC²

LFE2-6: 45, 46, 124,

None

LFE2-6: K6, R3, P4

LFE2-12: E3, F3, F1, H4, F2, H5,

G1, G3, G2, G4, K6, N1, M2, N2,

M1, N3, N5, N4, P5, N19, M19,

J22, L22, H22, K22, J16, D22,

F21, E21, E22, H19, G20, G19,

F20, C21, C22, H6, J6, H3, H2,

H17, H16, H20, H18

127

LFE2-12/LFE2-20:

None

LFE2-12: 127

LFE2-20/LFE2-35: K6, J16, H6,

J6, H3, H2, H17, H16, H20, H18

LFE2-50: None

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. Pin orientation follows the conventional order from the pin 1 marking of the top side view and counter-clockwise.

4. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

4-16

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Power Supply and NC (Cont.)

Signals

672 fpBGA³

900 fpBGA³

VCC

LFE2-20: R8, P18, M8, L20, L12, L13, L14, L15,

M11, M12, M15, M16, N11, N16, P11, P16, R11,

R12, R15, R16, T12, T13, T14, T15

AA11, AA20, K11, K21, K22, L11, L12, L13, L18, L19, L20,

M11, M20, N11, N20, V11, V20, W11, W20, Y10, Y11, Y12,

Y13, Y18, Y19, Y20

LFE2-35/LFE2-50: L12, L13, L14, L15, M11, M12,

M15, M16, N11, N16, P11, P16, R11, R12, R15,

R16, T12, T13, T14, T15

LFE2-70: L12, L13, L14, L15, M11, M12, M15,

M16, N11, N16, P11, P16, R11, R12, R15, R16,

T12, T13, T14, T15

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCJ

D11, D6, G9, J12, K12

D16, D21, G18, J15, K15

F23, J20, L23, M17, M18

AA23, R17, R18, T23, V20

AC16, AC21, U15, V15, Y18

AC11, AC6, U12, V12, Y9

AA4, R10, R9, T4, V7

F4, J7, L4, M10, M9

AE25, V18

J13, J14, K12, K13, K14, K15

J17, J18, J20, K17, K18, K20

L21, M21, M22, N21, N22, R21

U21, U22, V21, V22, W21, Y22

AA16, AA17, AA18, AA19, AB17, AB18

AA12, AA13, AA14, AB12, AB13, AB14

U10, U9, V10, W10, W9, Y9

L10, L9, M10, N10, P10, R10

AA21, Y21

AB5

AD3

VCCAUX

J10, J11, J16, J17, K18, L18, T18, U18, V16, V17, AA15, AB11, AB19, AB20, J11, J12, J19, K19, L22, M9,

V10, V11, T9, U9, K9, L9

N9, P21, P9, T10, T21, V9, W22

VCCPLL

GND¹

LFE2-20: None

P22, P8, T22, Y7

LFE2-35/LFE2-70: R8, P18

LFE2-50: R8, P18, M8, L20

A2, A25, AA18, AA24, AA3, AA9, AD11, AD16,

A1, A30, AC28, AC3, AH13, AH18, AH23, AH28, AH3,

AD21, AD6, AE1, AE26, AF2, AF25, B1, B26, C11, AH8, AK1, AK30, C13, C18, C23, C28, C3, C8, H28, H3,

C16, C21, C6, F18, F24, F3, F9, J13, J14, J21, J6, L14, L15, L16, L17, M12, M13, M14, M15, M16, M17,

K10, K11, K13, K14, K16, K17, L10, L11, L16, L17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19,

L24, L3, M13, M14, N10, N12, N13, N14, N15,

N17, P10, P12, P13, P14, P15, P17, R13, R14,

N28, N3, P11, P12, P13, P14, P15, P16, P17, P18, P19,

P20, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,

T10, T11, T16, T17, T24, T3, U10, U11, U13, U14, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, U11,

U16, U17, V13, V14, V21, V6

U12, U13, U14, U15, U16, U17, U18, U19, U20, V12, V13,

V14, V15, V16, V17, V18, V19, V28, V3, W12, W13, W14,

W15, W16, W17, W18, W19, Y14, Y15, Y16, Y17

NC²

LFE2-20: E4, E3, E2, E1, H6, H5, F2, F1, H8, J9, A2, A3, A4, A5, AB28, AC4, AD23, AE1, AE2, AE29, AE3,

G4, G3, K3, K2, K1, L2, L1, M2, M1, N2, T1, T2,

AE30, AE4, AE5, AE6, AF1, AF2, AF23, AF26, AF27,

AF28, AF29, AF3, AF30, AF4, AF5, AG1, AG13, AG16,

P8, P6, P5, P4, U1, V1, P3, R3, R4, U2, V2, W2,

T6, R5, AA19, W17, Y19, Y17, AF20, AE20, AA20, AG18, AG2, AG26, AG27, AG28, AG29, AG3, AG30, AG4,

W18, AD20, AE21, AF21, AF22, R22, T21, P26,

P25, R24, R23, P20, R19, P21, P19, P23, P22,

N22, R21, N26, N25, J26, J25, J23, K23, H26,

H25, H24, H23, F22, E24, D25, C25, D24, B25,

H21, G22, B24, C24, D23, C23, E19, C19, B21,

B20, D19, B19, G17, E18, G19, F17, A20, A19,

E17, D18, M3, N6, P24

AG8, AH1, AH16, AH2, AH26, AH27, AH29, AH30, AH4,

AJ1, AJ2, AJ27, AJ28, AJ29, AJ3, AJ30, AK2, AK27,

AK28, AK29, AK3, B1, B2, B3, B30, B4, B5, C1, C2, C29,

C30, C4, D13, D18, D23, D28, D29, D3, D30, D4, E25,

E26, E27, E28, E29, E3, E30, E4, E5, E6, F25, F5, F6, G6,

G7, K10, K9, N27, N4, R1, R2, V27, V4

LFE2-35: K3, K2, K1, L2, L1, M2, M1, N2, M8, P3,

R3, R4, U2, V2, W2, AF20, AE20, AA20, W18,

AD20, AE21, AF21, AF22, P26, P25, R24, R23,

P20, R19, L20, J26, J25, J23, K23, H26, H25, H24,

H23, E19, C19, B21, B20, D19, B19, G17, E18,

G19, F17, A20, A19, E17, D18, M3, N6, P24

LFE2-50: N6, P24, M3

LFE2-70: M8, L20, M3, P24, N6

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

4-17

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Power Supply and NC

Signal

256 fpBGA

484 fpBGA

V

G7, G9, H7, J10, K10, K8

J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14,

N9, P10, P11, P12, P13

CC

V

E7

B5, B9, E7, H9

CCIO0

CCIO1

CCIO2

CCIO3

CCIO4

CCIO5

CCIO6

CCIO7

CCIO8

CCJ

E10

D13, E16, H14

E14, G12

K12, M14

M10, P12

M7, P5

K5, M3

E3, G5

T15

E21, G18, J15, K19

N19, P15, T18, V21

AA18, R14, V16, W13

AA5, R9, V7, W10

N4, P8, T5, V2

E2, G5, J8, K4

AA22, U19

K7

W4

G8, H10, J7, K9

G10

H11, H12, L15, L8, M15, M8, R11, R12

R8, H15, H8, R15

CCAUX

CCPLL

SERDES Power³

C15, B15, C12, A12, C11, C10, C14, C13, B9, C22, B22, C19, A19, C18, C17, C21, C20, B16, C16,

C9, C5, C4, C8, C7, A6, C6, B3, C3

C12, C11, C15, C14, A13, C13, B10, C10

GND¹

A1, A15, A16, A3, A9, B12, B6, E15, E2, H14,

H8, H9, J3, J8, J9, M15, M2, P9, R12, R5, T1,

T16

A1, A10, A16, A22, AA19, AA4, AB1, AB22, B13,

B19, B4, D16, D2, D21, D7, G19, G4, H10, H13, J14,

J9, K10, K11, K12, K13, K15, K20, K3, K8, L10, L11,

L12, L13, M10, M11, M12, M13, N10, N11, N12, N13,

N15, N20, N3, N8, P14, P9, R10, R13, T19, T4, W16,

W2, W21, W7, Y10, Y13

NC²

D10, D11, D12, D13, D14, D4, D5, D6, D7, E11, LFE2M20: D14, D15, E14, E15, F13, F14, F15, G12,

E6, E8, E9, F10, F7, F8, F9

G13, G14, G15

LFE2M35: D14, D15, E14, E15, F13, F14, F15, G12,

G13, G14, G15, U6

LFE2M50:Y15, W15, AB20, AB21, AA20, AB19,

AB18, Y22, Y21, Y17, Y18, Y16, W17, Y19, Y20, W19,

W18, V17, V18, D15, G14, G15, D14, E15, E14, F15,

F14, F13, G12, G13

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Spe-

ciﬁcally, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using

the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details.

4-18

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Power Supply and NC (Cont.)

Signal

672 fpBGA

900 fpBGA

V

LFE2M35: AD13, AD14, AD16, AD17, AD19, AD21, LFE2M50: AH1, AH4, AH5, AH2, AH7, AH12, AH9,

AD22, AD24, AD25, L12, L13, L14, L15, M11, M12, AH10, AH13, C13, C10, C9, C12, C7, C2, C5, C4,

M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, C1, L12, L13, L18, L19, M11, M12, M13, M14, M15,

CC

T12, T13, T14, T15

M16, M17, M18, M19, M20, N11, N12, N19, N20,

P12, P19, R12, R19, T12, T19, U12, U19, V11, V12,

LFE2M50: L12, L13, L14, L15, M11, M12, M15, M16, V19, V20, W11, W12, W13, W14, W15, W16, W17,

N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, W18, W19, W20, Y12, Y13, Y18, Y19

T14, T15

LFE2M70/LFE2M100: L12, L13, L18, L19, M11,

M12, M13, M14, M15, M16, M17, M18, M19, M20,

N11, N12, N19, N20, P12, P19, R12, R19, T12, T19,

U12, U19, V11, V12, V19, V20, W11, W12, W13,

W14, W15, W16, W17, W18, W19, W20, Y12, Y13,

Y18, Y19

V

B12, B7, F11, J13, K12

D18, F16, J14, K15

G25, L21, M17, M25, N18

P18, R17, R25, T21, Y25

AA16, AC18, U15, V14

AA11, AE12, AE7, U12, V13

P9, R10, R2, T6, Y2

G2, L6, M10, M2, N9

AC24, U17

D14, E6, E9, F12, K12, K13

CCIO0

CCIO1

CCIO2

CCIO3

CCIO4

CCIO5

CCIO6

CCIO7

CCIO8

CCJ

D17, E22, E25, F19, K18, K19

F28, J25, K28, M21, M24, N21, N28, P21, R25

AA28, AB25, AE28, T25, U21, V21, V28, W21, W24

AA18, AA19, AE19, AF22, AG17, AG25

AA12, AA13, AE12, AF9, AG14, AG6

AA3, AB6, AE3, T6, U10, V10, V3, W10, W7

F3, J6, K3, M10, M7, N10, N3, P10, R6

AA25, AD28

AA7

AG1

LFE2M35: AE19, J11, J12, J15, J16, L18, L9, M18, LFE2M50: AJ7, B7, AA10, AA11, AA20, AA21, K10,

M9, R18, R9, T18, T9, V11, V12, V15, V16

CCAUX

K11, K20, K21, L10, L11, L20, L21, Y10, Y11, Y20,

Y21

LFE2M50: J11, J12, J15, J16, L18, L9, M18, M9,

R18, R9, T18, T9, V11, V12, V15, V16

LFE2M70/LFE2M100: AA10, AA11, AA20, AA21,

K10, K11, K20, K21, L10, L11, L20, L21, Y10, Y11,

Y20, Y21

V

H7, K6, P7, R8, V18, P20, J17, G19

N13, N18, V13, V18

CCPLL

SERDES Power³LFE2M35: C25, B25, C22, A22, C21, C20, C24, C23, LFE2M50: AH18, AJ18, AH21, AK21, AH22, AH23,

B19, C19, C15, C14, C18, C17, A16, C16, B13, C13 AH19, AH20, AH24, AJ24, AH28, AH29, AH25,

AH26, AK27, AH27, AJ30, AH30, C30, B30, C27,

LFE2M50: AD13, AE13, AD16, AF16, AD17, AD18, A27, C26, C25, C29, C28, B24, C24, C20, C19, C23,

AD14, AD15, AD19, AE19, AD23, AD24, AD20,

AD21, AF22, AD22, AE25, AD25, C25, B25, C22,

C22, A21, C21, B18, C18

A22, C21, C20, C24, C23, B19, C19, C15, C14, C18, LFE2M70/LFE2M100: C13, B13, C10, A10, C9, C8,

C17, A16, C16, B13, C13

C12, C11, B7, C7, C3, C2, C6, C5, A4, C4, B1, C1,

C30, B30, C27, A27, C26, C25, C29, C28, B24, C24,

C20, C19, C23, C22, A21, C21, B18, C18, AH18,

AJ18, AH21, AK21, AH22, AH23, AH19, AH20,

AH24, AJ24, AH28, AH29, AH25, AH26, AK27,

AH27, AJ30, AH30, AH1, AJ1, AH4, AK4, AH5, AH6,

AH2, AH3, AH7, AJ7, AH11, AH12, AH8, AH9, AK10,

AH10, AJ13, AH13

4-19

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Power Supply and NC (Cont.)

Signal

GND¹

672 fpBGA

900 fpBGA

A13, A19, A2, A25, AA2, AA25, AB18, AB22, AB5,

AB9, AE1, AE11, AE16, AE22, AE26, AE6, AF13,

LFE2M50: A1, A13, A18, A24, A30, A7, AA14, AA15,

AA16, AA17, AA24, AA27, AA4, AB24, AB7, AD12,

AF19, AF2, AF25, B1, B11, B16, B22, B26, B6, E18, AD19, AD27, AE22, AE27, AE4, AE9, AF14, AF17,

E22, E5, E9, F2, F25, G11, G16, J22, J5, K11, K13, AF25, AF6, AJ10, AJ21, AJ27, AJ4, AK1, AK13,

K14, K16, L10, L11, L16, L17, L2, L20, L25, L7, M13, AK18, AK24, AK30, AK7, B10, B21, B27, B4, D25,

M14, N10, N12, N13, N14, N15, N17, P10, P12, P13, D6, E14, E17, F22, F27, F4, F9, G12, G19, J24, J7,

P14, P15, P17, R13, R14, T10, T11, T16, T17, T2,

K14, K15, K16, K17, K27, K4, L14, L15, L16, L17,

T20, T25, T7, U11, U13, U14, U16, V22, V5,Y11,Y16 M23, M8, N14, N15, N16, N17, N27, N4, P11, P13,

P14, P15, P16, P17, P18, P20, R10, R11, R13, R14,

R15, R16, R17, R18, R20, R21, R24, R7, T10, T11,

T13, T14, T15, T16, T17, T18, T20, T21, T24, T7,

U11, U13, U14, U15, U16, U17, U18, U20, V14, V15,

V16, V17, V27, V4, W23, W8, Y14, Y15, Y16, Y17

LFE2M70/LFE2M100: A1, A13, A18, A24, A30, A7,

AA14, AA15, AA16, AA17, AA24, AA27, AA4, AB24,

AB7, AD12, AD19, AD27, AE22, AE27, AE4, AE9,

AF14, AF17, AF25, AF6, AJ10, AJ21, AJ27, AJ4,

AK1, AK13, AK18, AK24, AK30, AK7, B10, B21, B27,

B4, D25, D6, E14, E17, F22, F27, F4, F9, G12, G19,

J24, J7, K14, K15, K16, K17, K27, K4, L14, L15, L16,

L17, M23, M8, N15, N16, N17, N27, N4, P11, P13,

P14, P15, P16, P17, P18, P20, R10, R11, R13, R14,

R15, R16, R17, R18, R20, R21, R24, R7, T10, T11,

T13, T14, T15, T16, T17, T18, T20, T21, T24, T7,

U11, U13, U14, U15, U16, U17, U18, U20, V14, V15,

V16, V17, V27, V4, W23, W8, Y14, Y15, Y16, Y17

NC²

LFE2M35: AB3, AB4, AC1, AC2, AD15, AD18, AD20, LFE2M50: G5, G4, K7, K8, E1, F2, F1, G3, G2, G1,

AD23, AE13, AE25, AF16, AF22, B4, B5, C26, D20, L9, L7, K6, K5, L8, L6, AA1, AA2, Y3, AB1, Y9, Y8,

D21, D22, D23, D24, D25, D26, E20, E21, E25, E26, Y7, AA7, AB2, AB3, AA5, AA6, AB4, AB5, AA8, AA9,

F20, G20, K10, K17, R4, U10, U23, V10, W7, N7, V7 AJ1, AK4, AH6, AH3, AH11, AH8, AK10, AJ13,

AB26, AB27, Y24, Y25, AA29, Y28, Y30, Y29, W22,

LFE2M50: AB3, AB4, AC1, AC2, B4, B5, C26, D20, V22,Y27,Y26, W30, W29, W25, W26, L24, L23, D30,

D21, D22, D23, D24, D25, D26, E20, E21, E25, E26, D29, K24, K25, J27, K26, J26, H26, H27, G26, H23,

F20, G20, K10, K17, R4, U10, U23, V10, W7, AB21, H24, D28, E28, J18, J19, H17, J17, F18, F17, B13,

AC20, AC21, AC22, AC23, AC25, AD26, W20

A10, C8, C11, C3, C6, A4, B1, AA26, AB11, AB12,

AB13, AB14, AB15, AB16, AB17, AB19, AB20, AB21,

AC11, AC21, AC22, AD21, AD22, AE23, AF20,

AF23, AG23, AG26, F20, F23, G10, G20, G21, H19,

H20, H21, H22, J20, J21, R9, U22, W9

LFE2M70/LFE2M100: AA26, AB10, AB11, AB12,

AB13, AB14, AB15, AB16, AB17, AB19, AB20, AB21,

AB9, AC10, AC11, AC21, AC22, AC8, AC9, AD21,

AD22, AD4, AD5, AD6, AD7, AD8, AE23, AE5, AE6,

AE7, AF20, AF23, AF5, AG23, AG26, D10, E10, E11,

F10, F20, F23, F8, G10, G20, G21, G7, G8, G9, H19,

H20, H21, H22, H6, H8, H9, J10, J20, J21, J9, K9,

R9, U22, W9

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Spe-

ciﬁcally, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using

the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details.

4-20

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Power Supply and NC (Cont.)

Signal

1152 fpBGA

V

AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AB14, AB15, AB20, AB21, N14, N15, N20, N21,

P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, R13, R14, R21, R22, T14, T21, U14, U21, V14, V21, W14, W21,

Y13, Y14, Y21, Y22

CC

V

C12, C16, E14, H12, H16, M14, M15

C19, C23, E21, H19, H23, M20, M21

G32, K28, K32, N27, N32, P23, R23, T27, T32

AA23, AB27, AB32, AE28, AE32, AH32, W27, W32, Y23

AC20, AC21, AG19, AG23, AK21, AM19, AM23

AC14, AC15, AG12, AG16, AK14, AM12, AM16

AA12, AB3, AB8, AE3, AE7, AH3, W3, W8, Y12

G3, K3, K7, N3, N8, P12, R12, T3, T8

AD28, AG32

CCIO0

CCIO1

CCIO2

CCIO3

CCIO4

CCIO5

CCIO6

CCIO7

CCIO8

CCJ

AK3

AB12, AB13, AB22, AB23, AC13, AC22, M13, M22, N12, N13, N22, N23

R15, R20, Y15, Y20

CCAUX

CCPLL

SERDES Power³

D7, B9, B8, D9, B7, E7, B6, D8, E6, D6, D4, B5, D3, B4, C1, B3, B1, B2, B33, B34, B32, C34, B31, D32, B30, D31, E29,

D29, D27, B29, E28, B28, D26, B27, B26, D28, AL28, AN26, AN27, AL26, AN28, AK28, AN29, AL27, AL29, AK29,

AL31, AN30, AL32, AN31, AM34, AN32, AN34, AN33, AN2, AN1, AN3, AM1, AN4, AL3, AN5, AL4, AL6, AK6, AL8, AN6,

AK7, AN7, AL9, AN8, AN9, AL7

GND¹

A1, A10, A13, A22, A25, A34, AB16, AB17, AB18, AB19, AB26, AB31, AB4, AB9, AC16, AC17, AC18, AC19, AD27,

AE27, AE31, AE4, AE8, AF12, AF16, AF19, AF23, AG31, AH31, AH4, AJ14, AJ21, AK27, AK8, AL10, AL16, AL19, AL2,

AL25, AL33, AP1, AP10, AP13, AP22, AP25, AP34, D10, D16, D19, D2, D25, D33, E27, E8, F14, F21, G31, G4, J12,

J16, J19, J23, K27, K31, K4, K8, M16, M17, M18, M19, N16, N17, N18, N19, N26, N31, N4, N9, R16, R17, R18, R19,

T12, T13, T15, T16, T17, T18, T19, T20, T22, T23, T26, T31, T4, T9, U12, U13, U15, U16, U17, U18, U19, U20, U22,

U23, V12, V13, V15, V16, V17, V18, V19, V20, V22, V23, W12, W13, W15, W16, W17, W18, W19, W20, W22, W23, W26,

W31, W4, W9, Y16, Y17, Y18, Y19

NC²

LFE2M70: H2, H1, G5, G6, M9, M10, H3, H4, P3, P4, P9, M7, P1, P2, N7, P7, AC7, AC5, AC6, AD5, AD4, AD3, AD10,

AD8, AD2, AD1, AD9, AC11, AD6, AD7, AE1, AE2, AJ12, AH12, AL13, AK13, AE14, AG13, AH22, AH21, AG22, AG21,

AF33, AF34, AC27, AC28, AD29, AD30, AE33, AE34, AD32, AD31, AB25, AC25, AB28, AA26, AD33, AD34, P30, P29,

P31, P32, R25, T24, N34, N33, F24, G23, J22, G22, H21, K21, L19, L20, L18, K19, J14, L15, H14, K14, F12, D11, F11,

E11, A11, A12, A23, A24, AA11, AB11, AC26, AC30, AD11, AD12, AD13, AD14, AD15, AD19, AD21, AD22, AD23,

AE10, AE11, AE12, AE13, AE19, AE21, AE22, AE23, AF11, AF21, AF22, AF24, AF8, AF9, AG10, AG11, AG24, AG25,

AG26, AG3, AG7, AG8, AG9, AH10, AH11, AH13, AH24, AH25, AH26, AH27, AH5, AH6, AH7, AH8, AH9, AJ10, AJ11,

AJ13, AJ24, AJ25, AJ26, AJ27, AJ3, AJ4, AJ5, AJ6, AJ7, AJ8, AJ9, AK10, AK11, AK12, AK24, AK25, AK26, AK4, AK9,

AL11, AL12, AL34, AM10, AM11, AM13, AM25, AN10, AN11, AN12, AN13, AN24, AN25, AP11, AP12, AP24, B10, B11,

B12, B13, B22, B23, B24, B25, C10, C11, C13, C22, C24, C25, D1, D15, D24, D34, E10, E24, E25, E26, E3, E31, E32,

E33, E34, E4, E9, F10, F25, F26, F27, F28, F29, F30, F31, F32, F33, F34, F5, F6, F7, F8, F9, G10, G11, G24, G25,

G26, G27, G28, G29, G30, G33, G34, G7, G8, G9, H10, H11, H24, H25, H26, H27, H28, H29, H8, H9, J10, J11, J24,

J25, J26, J9, K10, K11, K12, K13, K23, K24, K25, K26, L11, L12, L13, L14, L21, L22, L23, L24, L25, L26, M11, M24,

M25, M6, M8, N10, N11, P10, P25, P26, R9, T11, U11, W11, Y10, Y11

LFE2M100: A11, A12, A23, A24, AA11, AB11, AC26, AC30, AD11, AD12, AD13, AD14, AD15, AD19, AD21, AD22,

AD23, AE10, AE11, AE12, AE13, AE19, AE21, AE22, AE23, AF11, AF21, AF22, AF24, AF8, AF9, AG10, AG11, AG24,

AG25, AG26, AG3, AG7, AG8, AG9, AH10, AH11, AH13, AH24, AH25, AH26, AH27, AH5, AH6, AH7, AH8, AH9, AJ10,

AJ11, AJ13, AJ24, AJ25, AJ26, AJ27, AJ3, AJ4, AJ5, AJ6, AJ7, AJ8, AJ9, AK10, AK11, AK12, AK24, AK25, AK26, AK4,

AK9, AL11, AL12, AL34, AM10, AM11, AM13, AM25, AN10, AN11, AN12, AN13, AN24, AN25, AP11, AP12, AP24, B10,

B11, B12, B13, B22, B23, B24, B25, C10, C11, C13, C22, C24, C25, D1, D15, D24, D34, E10, E24, E25, E26, E3, E31,

E32, E33, E34, E4, E9, F10, F25, F26, F27, F28, F29, F30, F31, F32, F33, F34, F5, F6, F7, F8, F9, G10, G11,G24, G25,

G26, G27, G28, G29, G30, G33, G34, G7, G8, G9, H10, H11, H24, H25, H26, H27, H28, H29, H8, H9, J10, J11, J24,

J25, J26, J9, K10, K11, K12, K13, K23, K24, K25, K26, L11, L12, L13, L14, L21, L22, L23, L24, L25, L26, M11, M24,

M25, M6, M8, N10, N11, P10, P25, P26, R9, T11, U11, W11, Y10, Y11

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks.

Speciﬁcally, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices

using the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details.

4-21

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP

LFE2-6E/SE

LFE2-12E/12SE

Pin/Pad

Dual

Number

Function

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

Function

Bank

Function

VREF2_7

VREF1_7

Differential

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

1

PL2A

PL2B

VREF2_7

VREF1_7

PL2A

PL2B

7

-

2

3

PL4A

4

PL4B

5

PL6A

LDQ10

PL6A

LDQ10

6

VCCAUX

PL6B

VCCAUX

PL6B

7

-

LDQ10

C (LVDS)*

T (LVDS)*

7

-

LDQ10

C (LVDS)*

T (LVDS)*

8

PL8A

9

VCCIO7

PL8B

VCCIO7

PL8B

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

LDQ10

C (LVDS)*

LDQ10

C (LVDS)*

GND

PL12A

PL12B

PL13A

PL13B

VCC

7

-

LDQ10

T (LVDS)*

PL12A

PL12B

PL13A

PL13B

VCC

7

-

LDQ10

T (LVDS)*

LDQ10

C (LVDS)*

LDQ10

C (LVDS)*

PCLKT7_0/LDQ10

PCLKC7_0/LDQ10

T

PCLKT7_0/LDQ10

PCLKC7_0/LDQ10

T

C

PL15A

PL15B

PL16A

PL16B

GND

6

-

PCLKT6_0

PCLKC6_0

VREF2_6

VREF1_6

T (LVDS)*

PL15A

PL15B

PL16A

PL16B

GND

6

-

PCLKT6_0

PCLKC6_0

VREF2_6

VREF1_6

T (LVDS)*

C (LVDS)*

T

C

VCC

-

VCC

-

PL18A

PL18B

LLM0_PLLCAP

PL20A

PL20B

PL22A

VCC

6

-

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T

PL18A

PL18B

LLM0_PLLCAP

PL20A

PL20B

PL22A

VCC

6

-

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T

C

LLM0_GPLLT_IN_A**

T (LVDS)*

LLM0_GPLLT_IN_A**

LLM0_GPLLC_IN_A**

T (LVDS)*

C (LVDS)*

LLM0_GPLLC_IN_A** C (LVDS)*

GND

-

GND

-

VCCIO6

TCK

6

-

VCCIO6

TCK

6

-

TDI

-

TDI

-

TDO

-

TDO

-

VCCJ

TMS

-

VCCJ

-

TMS

-

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

T

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

T

PB2B

C

PB2B

C

VCCAUX

PB4A

VCCAUX

PB6A

5

BDQ6

T

5

BDQS6

BDQ6

T

PB4B

C

PB6B

C

VCCIO5

PB6A

VCCIO5

PB12A

PB12B

PB16A

BDQS6

BDQ6

T

BDQ15

T

C

T

PB6B

C

NC

4-22

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)

LFE2-6E/SE

LFE2-12E/12SE

Number

Pin/Pad

Function

Pin/Pad

Function

Dual

Function

Bank

Dual Function

Differential

Bank

Differential

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

NC

GND

5

-

PB16B

GND

5

-

BDQ15

C

VCC

-

PB8A

5

-

PCLKT5_0/BDQ6

PCLKC5_0/BDQ6

T

PB26A

PB26B

GND

5

-

PCLKT5_0/BDQ24

PCLKC5_0/BDQ24

T

PB8B

C

GND

PB13A

PB13B

VCC

4

-

PCLKT4_0/BDQ15

PCLKC4_0/BDQ15

T

PB31A

PB31B

VCC

4

-

PCLKT4_0/BDQ33

PCLKC4_0/BDQ33

T

C

PB14A

PB14B

PB16A

PB16B

PB18A

PB18B

GND

4

-

BDQ15

T

C

T

PB34A

PB34B

PB40A

PB40B

PB44A

PB44B

GND

4

-

BDQ33

BDQ42

T

C

T

C

T

C

T

C

PB20A

PB20B

VCCIO4

PB22A

PB22B

PB24A

PB24B

PB26A

PB26B

PB28A

PB28B

CFG1

4

8

-

BDQ24

T

PB48A

PB48B

VCCIO4

PB50A

PB50B

PB52A

PB52B

PB54A

PB54B

PB55A

PB55B

CFG1

4

8

-

BDQ51

T

C

BDQ24

T

C

T

BDQ51

T

C

T

BDQS24

BDQ51

BDQ24

C

T

BDQ51

C

T

BDQ24

BDQ51

BDQ24

C

T

BDQ51

C

T

VREF2_4/BDQ24

VREF1_4/BDQ24

VREF2_4/BDQ51

VREF1_4/BDQ51

C

CFG2

PROGRAMN

INITN

PROGRAMN

INITN

CFG0

CCLK

DONE

PR29A

GND

DONE

PR29A

GND

D0/SPIFASTN

PR26A

VCC

8

-

D6

D7

PR26A

VCC

8

-

D6

D7

PR25B

VCCIO8

PR25A

PR24B

PR24A

VCCIO3

VCCAUX

8

3

-

C

PR25B

VCCIO8

PR25A

PR24B

PR24A

VCCIO3

VCCAUX

8

3

-

C

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

4-23

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)

LFE2-6E/SE

LFE2-12E/12SE

Pin/Pad

Dual

Number

Function

Bank

3

-

Dual Function

Differential

Function

Bank

Function

Differential

91

PR20B

PR20A

RLM0_PLLCAP

VCC

RLM0_GPLLC_IN_A** C (LVDS)*

PR20B

PR20A

RLM0_PLLCAP

VCC

3

-

RLM0_GPLLC_IN_A** C (LVDS)*

RLM0_GPLLT_IN_A** T (LVDS)*

92

RLM0_GPLLT_IN_A**

T (LVDS)*

93

94

95

GND

-

GND

-

96

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

VCC

3

-

RLM0_GDLLC_IN_A** C (LVDS)*

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

VCC

3

-

RLM0_GDLLC_IN_A** C (LVDS)*

97

RLM0_GDLLT_IN_A**

VREF2_3

T (LVDS)*

C

RLM0_GDLLT_IN_A**

VREF2_3

T (LVDS)*

C

98

99

VREF1_3

T

VREF1_3

T

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

PCLKC3_0

C (LVDS)*

T (LVDS)*

PCLKC3_0

C (LVDS)*

T (LVDS)*

PCLKT3_0

PR13B

PR13A

GND

2

-

PCLKC2_0/RDQ10

PCLKT2_0/RDQ10

C

T

PR13B

PR13A

GND

2

-

PCLKC2_0/RDQ10

PCLKT2_0/RDQ10

C

T

VCCIO2

PR2B

2

1

-

VCCIO2

PR2B

2

1

-

VREF2_2

VREF1_2

VREF2_1

VREF1_1

C (LVDS)*

VREF2_2

VREF1_2

VREF2_1

VREF1_1

C (LVDS)*

PR2A

T (LVDS)*

PR2A

T (LVDS)*

PT28B

PT28A

PT26B

PT26A

PT24B

PT24A

PT22B

PT22A

VCCIO1

PT20B

PT20A

GND

C

T

C

T

C

T

C

T

PT55B

PT55A

PT54B

PT54A

PT52B

PT52A

PT50B

PT50A

VCCIO1

PT48B

PT48A

GND

C

T

C

T

C

T

C

T

C

T

C

T

PT18B

PT18A

PT16A

NC

1

-

C

T

PT44B

PT44A

PT40B

PT40A

PT34B

PT34A

NC

1

-

C

T

C

T

C

T

PT14B

PT14A

NC

C

T

VCC

PT12B

PT12A

PT10B

XRES

GND

1

0

-

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

PT30B

PT30A

PT28B

XRES

1

0

-

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

C

GND

PT10A

VCC

0

-

PCLKT0_0

T

PT28A

VCC

0

-

PCLKT0_0

T

4-24

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)

LFE2-6E/SE

LFE2-12E/12SE

Number

Pin/Pad

Function

Pin/Pad

Function

Dual

Function

Bank

Dual Function

Differential

Bank

Differential

136

137

138

139

140

141

142

143

144

PT6B

PT6A

0

-

C

T

PT16B

PT16A

GND

0

-

C

T

GND

VCCIO0

PT4B

0

-

VCCIO0

PT6B

0

-

C

T

C

T

PT4A

PT6A

VCCAUX

PT2B

VCCAUX

PT2B

0

VREF2_0

VREF1_0

C

T

0

VREF2_0

VREF1_0

C

T

PT2A

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one

connection with a package ball or pin.

4-25

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP

LFE2-12E/SE

LFE2-20E/SE

Pin/Pad

Dual

Pin/Pad

Dual

Number

Function

Bank

7

-

Function

VREF2_7

VREF1_7

Differential

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

Function

Bank

7

-

Function

Differential

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

1

PL2A

PL2B

PL2A

PL2B

VREF2_7

VREF1_7

LDQ8

2

3

PL4A

PL6A

4

PL4B

PL6B

LDQ8

5

GND

6

PL6A

7

-

LDQ10

T (LVDS)*

PL12A

VCCAUX

PL12B

PL14A

VCCIO7

PL14B

VCC

7

-

LDQ16

T (LVDS)*

7

VCCAUX

PL6B

8

7

-

LDQ10

C (LVDS)*

T (LVDS)*

7

-

LDQ16

C (LVDS)*

T (LVDS)*

9

PL8A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

VCCIO7

PL8B

LDQ10

C (LVDS)*

LDQ16

C (LVDS)*

VCC

GND

-

GND

-

VCCIO7

PL12A

PL12B

GND

7

-

VCCIO7

PL18A

PL18B

GND

7

-

LDQ10

T (LVDS)*

C (LVDS)*

LDQ16

T (LVDS)*

C (LVDS)*

PL13A

VCC

7

-

PCLKT7_0/LDQ10

T

PL19A

VCC

7

-

PCLKT7_0/LDQ16

T

PL13B

PL15A

PL15B

PL16A

PL16B

GND

7

6

-

PCLKC7_0/LDQ10

PCLKT6_0

C

PL19B

PL21A

PL21B

PL22A

PL22B

GND

7

6

-

PCLKC7_0/LDQ16

PCLKT6_0/LDQ25

PCLKC6_0/LDQ25

VREF2_6/LDQ25

VREF1_6/LDQ25

C

T (LVDS)*

PCLKC6_0

VREF2_6

C (LVDS)*

T

VREF1_6

C

PL17A

PL17B

VCC

6

-

LLM0_GDLLT_IN_A** T (LVDS)*

LLM0_GDLLC_IN_A** C (LVDS)*

PL27A

PL27B

VCC

6

-

LLM0_GDLLT_IN_A**/LDQ25

LLM0_GDLLC_IN_A**/LDQ25

T (LVDS)*

C (LVDS)*

LLM0_PLLCAP

VCCAUX

PL20A

GND

6

-

LLM0_PLLCAP

VCCAUX

PL30A

GND

6

-

6

-

LLM0_GPLLT_IN_A** T (LVDS)*

6

-

LLM0_GPLLT_IN_A**/LDQ34

T (LVDS)*

PL21A

PL20B

PL21B

PL23A

PL24A

VCCIO6

PL24B

VCC

6

-

LLM0_GPLLT_FB_A

T

PL31A

PL30B

PL31B

PL33A

PL38A

VCCIO6

PL38B

VCC

6

-

LLM0_GPLLT_FB_A/LDQ34

LLM0_GPLLC_IN_A**/LDQ34

LLM0_GPLLC_FB_A/LDQ34

LDQ34

T

C (LVDS)*

C

LLM0_GPLLC_IN_A** C (LVDS)*

LLM0_GPLLC_FB_A

LDQ28

C

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

LDQ42

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

LDQ28

LDQ42

LDQS42

PL26A

GND

6

-

LDQ28

PL40A

GND

6

-

PL26B

VCCIO6

PL28A

6

LDQ28

PL40B

VCCIO6

PL42A

6

LDQS28

4-26

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)

LFE2-12E/SE

LFE2-20E/SE

Pin/Pad

Dual

Pin/Pad

Dual

Number

Function

Bank

6

-

Function

Differential

Function

Bank

6

-

Function

Differential

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

PL28B

PL30A

TCK

LDQ28

C (LVDS)*

PL42B

PL44A

TCK

LDQ42

C (LVDS)*

LDQ28

TDI

-

TDI

-

TDO

-

TDO

-

VCCJ

TMS

-

VCCJ

TMS

-

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

T

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

T

PB2B

C

PB2B

C

VCCIO5

PB6A

VCCIO5

PB6A

BDQS6

BDQ6

T

C

T

BDQS6

BDQ6

T

C

T

PB6B

PB8A

PB8B

C

PB8B

C

GND

PB12A

PB12B

VCCIO5

PB16A

PB16B

PB18A

PB18B

GND

5

-

BDQ15

T

PB12A

PB12B

VCCIO5

PB16A

PB16B

PB18A

PB18B

GND

5

-

BDQ15

T

C

BDQ15

T

C

T

BDQ15

T

C

T

C

PB20A

VCCAUX

PB20B

PB22A

PB22B

VCC

5

-

BDQ24

T

PB30A

VCCAUX

PB30B

PB32A

PB32B

VCC

5

-

BDQ33

T

5

-

BDQ24

C

T

5

-

BDQ33

C

T

C

PB26A

PB26B

GND

5

-

PCLKT5_0/BDQ24

PCLKC5_0/BDQ24

T

PB35A

PB35B

GND

5

-

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

T

C

PB31A

PB31B

VCC

4

-

PCLKT4_0/BDQ33

PCLKC4_0/BDQ33

T

PB40A

PB40B

VCC

4

-

PCLKT4_0/BDQ42

PCLKC4_0/BDQ42

T

C

GND

-

GND

-

PB34A

PB34B

PB36A

PB36B

VCCAUX

PB40A

PB40B

GND

4

-

BDQ33

T

C

T

PB42A

PB42B

PB44A

PB44B

VCCAUX

PB50A

PB50B

GND

4

-

BDQS42

BDQ42

T

C

T

C

4

-

BDQ42

T

4

-

BDQ51

T

C

PB42A

PB42B

4

BDQS42

BDQ42

T

PB52A

PB52B

4

BDQ51

T

C

4-27

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)

LFE2-12E/SE

LFE2-20E/SE

Pin/Pad

Dual

Pin/Pad

Dual

Number

Function

Bank

4

-

Function

Differential

Function

Bank

4

-

Function

Differential

92

PB44A

VCCIO4

PB44B

PB48A

PB48B

VCC

BDQ42

T

PB54A

VCCIO4

PB54B

PB58A

PB58B

VCC

BDQ51

T

93

94

BDQ42

BDQ51

C

T

BDQ51

BDQ60

C

T

95

96

C

97

98

PB52A

PB52B

VCCIO4

PB54A

GND

4

-

BDQ51

T

PB60A

PB60B

VCCIO4

PB63A

GND

4

-

BDQS60

BDQ60

T

99

C

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

BDQ51

BDQ60

PB55A

PB55B

CFG1

4

8

-

VREF2_4/BDQ51

VREF1_4/BDQ51

T

PB64A

PB64B

CFG1

4

8

-

VREF2_4/BDQ60

VREF1_4/BDQ60

T

C

PROGRAMN

CFG2

PROGRAMN

CFG2

INITN

CFG0

CCLK

DONE

PR29A

VCCIO8

PR26A

GND

D0/SPIFASTN

D6

PR43A

VCCIO8

PR40A

GND

D0/SPIFASTN

D6

VCC

-

VCC

-

PR25B

VCCIO8

PR25A

PR24B

PR24A

GND

8

-

D7

C

PR39B

VCCIO8

PR39A

PR38B

PR38A

GND

8

-

D7

C

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

VCCIO3

PR21A

VCCAUX

PR20B

PR20A

RLM0_PLLCAP

VCC

3

-

VCCIO3

PR31A

VCCAUX

PR30B

PR30A

RLM0_PLLCAP

VCC

3

-

RLM0_GPLLT_FB_A

RLM0_GPLLT_FB_A/RDQ34

3

-

RLM0_GPLLC_IN_A** C (LVDS)*

RLM0_GPLLT_IN_A** T (LVDS)*

3

-

RLM0_GPLLC_IN_A**/RDQ34 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ34

T (LVDS)*

PR18B

PR18A

PR17B

PR17A

PR16B

VCCIO3

PR16A

PR15B

3

RLM0_GDLLC_FB_A

RLM0_GDLLT_FB_A

C

T

PR28B

PR28A

PR27B

PR27A

PR22B

VCCIO3

PR22A

PR21B

3

RLM0_GDLLC_FB_A/RDQ25

RLM0_GDLLT_FB_A**/RDQ25

RLM0_GDLLC_IN_A/RDQ25

RLM0_GDLLT_IN_A**/RDQ25

VREF2_3/RDQ25

C

T

RLM0_GDLLC_IN_A** C (LVDS)*

RLM0_GDLLT_IN_A** T (LVDS)*

C (LVDS)*

T (LVDS)*

C

VREF2_3

C

VREF1_3

T

VREF1_3/RDQ25

PCLKC3_0/RDQ25

T

PCLKC3_0

C (LVDS)*

4-28

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)

LFE2-12E/SE

LFE2-20E/SE

Number

Pin/Pad

Dual

Pin/Pad

Dual

Function

Bank

3

-

Function

Differential

Function

Bank

3

-

Function

Differential

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

PR15A

GND

PCLKT3_0

T (LVDS)*

PR21A

GND

PCLKT3_0/RDQ25

T (LVDS)*

VCC

-

VCC

-

PR13B

PR13A

VCCIO2

PR12A

GND

2

-

PCLKC2_0/RDQ10

PCLKT2_0/RDQ10

C

T

PR19B

PR19A

VCCIO2

PR16A

GND

2

-

PCLKC2_0/RDQ16

PCLKT2_0/RDQ16

C

T

RDQ10

RDQS16

RDQ16

VCC

-

VCC

-

PR8B

2

-

C (LVDS)*

PR14B

VCCIO2

PR14A

PR12B

VCCAUX

PR12A

PR6B

2

-

C (LVDS)*

VCCIO2

PR8A

RDQ10

T (LVDS)*

C (LVDS)*

RDQ16

T (LVDS)*

C (LVDS)*

PR6B

VCCAUX

PR6A

2

1

-

RDQ10

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

C

2

1

-

RDQ16

RDQ8

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

C

PR4B

PR4A

PR6A

RDQ8

PR2B

VREF2_2

VREF1_2

VREF2_1

VREF1_1

PR2B

VREF2_2

VREF1_2

VREF2_1

VREF1_1

PR2A

PT55B

PT55A

GND

PT64B

PT64A

GND

T

PT54B

PT54A

VCCIO1

PT52B

PT52A

PT50B

PT50A

PT48B

PT48A

GND

1

-

C

T

PT62B

PT62A

VCCIO1

PT60B

PT60A

PT58B

PT58A

PT56B

PT56A

GND

1

-

C

T

C

T

C

T

C

T

C

T

C

T

C

T

VCCIO1

VCC

1

-

VCCIO1

VCC

1

-

PT40B

PT40A

VCCAUX

GND

1

-

C

T

PT50B

PT50A

VCCAUX

GND

1

-

C

T

-

PT36B

PT36A

PT34B

PT34A

PT30B

PT30A

XRES

PT28B

1

0

C

T

C

T

C

T

PT44B

PT44A

PT42B

PT42A

PT39B

PT39A

XRES

PT37B

1

0

C

T

C

T

C

T

PCLKC1_0

PCLKT1_0

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

PCLKC0_0

C

4-29

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)

LFE2-12E/SE

LFE2-20E/SE

Number

Pin/Pad

Function

Dual

Function

Pin/Pad

Function

Dual

Function

Bank

Differential

Bank

Differential

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

GND

PT28A

PT26B

PT26A

VCC

-

GND

PT37A

PT36B

PT36A

VCC

-

0

-

PCLKT0_0

T

C

T

0

-

PCLKT0_0

T

C

T

PT20B

VCCAUX

PT20A

GND

0

-

C

T

PT30B

VCCAUX

PT30A

GND

0

-

C

T

0

-

0

-

PT18B

PT18A

VCCIO0

PT16B

PT16A

VCC

0

-

C

T

PT26B

PT26A

VCCIO0

PT20B

PT20A

VCC

0

-

C

T

C

T

C

T

PT12B

PT12A

GND

0

-

C

T

PT12B

PT12A

GND

0

-

C

T

PT8B

0

C

T

C

T

PT8B

0

C

T

C

T

PT8A

PT6B

PT6A

VCCIO0

PT2B

VCCIO0

PT2B

VREF2_0

VREF1_0

C

T

VREF2_0

VREF1_0

C

T

PT2A

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-30

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA

LFE2-6E/SE

LFE2-12E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

T (LVDS)*

Bank Dual Function

Differential

T (LVDS)*

C3

C2

PL2A

PL2B

7

-

VREF2_7

VREF1_7

PL2A

PL2B

7

-

VREF2_7

VREF1_7

C (LVDS)*

VCCIO

-

VCCIO7

-

VCCIO7

-

D3

PL5A

7

-

T

T (LVDS)*

C

PL5A

7

-

T

T (LVDS)*

C

D4

PL4A

D2

PL5B

GND

E4

GNDIO7

PL4B

GNDIO7

PL4B

7

-

C (LVDS)*

7

-

C (LVDS)*

B1

PL7A

LDQ10

T

C

T

PL7A

LDQ10

T

C

T

C1

PL7B

F5

PL9A

VCCIO

F4

VCCIO7

PL8A

VCCIO7

PL8A

LDQ10

LDQS10

T (LVDS)*

C

LDQ10

LDQS10

T (LVDS)*

C

G6

PL9B

G4

PL8B

C (LVDS)*

T (LVDS)*

PL8B

C (LVDS)*

T (LVDS)*

D1

PL10A

GNDIO7

PL10B

PL11A

PL11B

VCCIO7

PL12A

PL12B

GNDIO7

PL13A

PL13B

PL15A

VCCIO6

PL15B

PL16A

GNDIO6

PL16B

PL17A

PL17B

VCC

PL10A

GNDIO7

PL10B

PL11A

PL11B

VCCIO7

PL12A

PL12B

GNDIO7

PL13A

PL13B

PL15A

VCCIO6

PL15B

PL16A

GNDIO6

PL16B

PL17A

PL17B

VCC

GND

E1

7

-

LDQ10

C (LVDS)*

7

-

LDQ10

C (LVDS)*

F3

T

G3

C

VCCIO

F2

LDQ10

T (LVDS)*

C (LVDS)*

LDQ10

T (LVDS)*

C (LVDS)*

F1

GND

G2

7

6

-

PCLKT7_0/LDQ10

PCLKC7_0/LDQ10

PCLKT6_0

T

C

7

6

-

PCLKT7_0/LDQ10

PCLKC7_0/LDQ10

PCLKT6_0

T

C

G1

H6

T (LVDS)*

VCCIO

H5

PCLKC6_0

VREF2_6

C (LVDS)*

T

PCLKC6_0

VREF2_6

C (LVDS)*

T

H4

GND

H3

6

-

VREF1_6

C

6

-

VREF1_6

C

H2

LLM0_GDLLT_IN_A**

LLM0_GDLLC_IN_A**

T (LVDS)*

C (LVDS)*

LLM0_GDLLT_IN_A**

LLM0_GDLLC_IN_A**

T (LVDS)*

C (LVDS)*

H1

G10

J4

PL18A

PL18B

LLM0_PLLCAP

PL20A

GNDIO6

PL21A

PL20B

VCCIO6

PL21B

6

-

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T

PL18A

PL18B

LLM0_PLLCAP

PL20A

GNDIO6

PL21A

PL20B

VCCIO6

PL21B

6

-

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T

J5

C

J6

K4

LLM0_GPLLT_IN_A**

T (LVDS)*

LLM0_GPLLT_IN_A**

T (LVDS)*

GND

J1

6

LLM0_GPLLT_FB_A

LLM0_GPLLC_IN_A**

T

6

LLM0_GPLLT_FB_A

LLM0_GPLLC_IN_A**

T

K3

C (LVDS)*

VCCIO

J2

LLM0_GPLLC_FB_A

C

LLM0_GPLLC_FB_A

C

4-31

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

GND

L2

GNDIO6

PL24A

PL25A

PL24B

PL25B

VCCIO6

PL26A

PL27A

PL26B

PL27B

GNDIO6

PL29A

PL28A

PL29B

VCCIO6

PL28B

PL30A

GNDIO6

PL30B

TDI

-

6

-

GNDIO6

PL24A

PL25A

PL24B

PL25B

VCCIO6

PL26A

PL27A

PL26B

PL27B

GNDIO6

PL29A

PL28A

PL29B

VCCIO6

PL28B

PL30A

GNDIO6

PL30B

TDI

-

LDQ28

T (LVDS)*

6

-

LDQ28

T (LVDS)*

K2

T

C (LVDS)*

C

T

C (LVDS)*

C

L3

K1

VCCIO

L4

LDQ28

T (LVDS)*

LDQ28

T (LVDS)*

L1

T

C (LVDS)*

C

T

C (LVDS)*

C

L5

M1

GND

N1

6

-

LDQ28

LDQS28

LDQ28

T

T (LVDS)*

C

6

-

LDQ28

LDQS28

LDQ28

T

T (LVDS)*

C

N2

P1

VCCIO

P2

LDQ28

C (LVDS)*

T (LVDS)*

LDQ28

C (LVDS)*

T (LVDS)*

R1

GND

R2

6

-

LDQ28

C (LVDS)*

6

-

LDQ28

C (LVDS)*

N4

M4

P3

TCK

-

TCK

-

TDO

-

TDO

-

N3

TMS

-

TMS

-

K7

VCCJ

PB2A

NC

-

VCCJ

-

M5

K6

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

T

PB2A

5

-

VREF2_5/BDQ6

BDQ6

T

PB3A

M6

R3

PB2B

NC

5

-

C

PB2B

VREF1_5/BDQ6

BDQ6

C

T

PB5A

P4

NC

-

PB5B

BDQ6

C

-

VCCIO

GNDIO5

PB21A

PB21B

PB22A

PB23A

VCCIO5

PB22B

PB23B

GNDIO5

PB24A

PB25A

PB24B

PB25B

PB26A

VCCIO5

-

N5

PB3A

PB3B

PB4A

PB5A

VCCIO5

PB4B

PB5B

GNDIO5

PB6A

PB7A

PB6B

PB7B

PB8A

VCCIO5

5

-

BDQ6

T

C

T

BDQ24

T

C

T

N6

T2

P6

VCCIO

T3

BDQ6

C

BDQ24

C

R6

GND

R4

5

BDQS6

BDQ6

T

C

T

5

BDQS24

BDQ24

T

C

T

L6

T4

BDQ6

BDQ24

L7

BDQ6

BDQ24

N7

PCLKT5_0/BDQ6

PCLKT5_0/BDQ24

VCCIO

4-32

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank Dual Function

Differential

M8

GND

P7

PB8B

GNDIO5

PB13A

PB13B

VCCIO4

PB14A

PB14B

PB15A

GNDIO4

PB16A

PB15B

PB16B

PB17A

VCCIO4

PB18A

PB17B

PB18B

PB19A

GNDIO4

PB19B

-

5

-

PCLKC5_0/BDQ6

C

PB26B

GNDIO5

PB31A

PB31B

VCCIO4

PB32A

PB32B

PB33A

GNDIO4

PB34A

PB33B

PB34B

PB35A

VCCIO4

PB36A

PB35B

PB36B

PB37A

GNDIO4

PB37B

VCCIO

GNDIO4

PB47A

PB48A

PB47B

PB48B

PB49A

PB50A

VCCIO4

PB49B

PB50B

PB51A

GNDIO4

PB52A

PB51B

PB52B

PB53A

PB54A

VCCIO4

PB53B

PB54B

GNDIO4

PB55A

PB55B

CFG2

5

-

PCLKC5_0/BDQ24

C

4

-

PCLKT4_0/BDQ15

PCLKC4_0/BDQ15

T

4

-

PCLKT4_0/BDQ33

PCLKC4_0/BDQ33

T

R8

C

VCCIO

T5

BDQ15

T

C

T

BDQ33

T

C

T

T6

T8

BDQS15

BDQS33

GND

R7

4

-

BDQ15

T

C

T

4

-

BDQ33

T

C

T

T9

T7

L8

VCCIO

P8

BDQ15

T

C

T

BDQ33

T

C

T

L9

N8

R9

GND

R10

-

4

-

BDQ15

C

4

-

BDQ33

C

-

N9

PB20A

PB21A

PB20B

PB21B

PB22A

PB23A

VCCIO4

PB22B

PB23B

PB24A

GNDIO4

PB25A

PB24B

PB25B

PB26A

PB27A

VCCIO4

PB26B

PB27B

GNDIO4

PB28A

PB28B

CFG2

4

-

BDQ24

T

C

T

BDQ51

T

C

T

T10

M9

R11

P10

N11

VCCIO

N10

P11

T11

GND

M11

T12

L11

T13

R13

VCCIO

T14

P13

GND

N12

M12

R15

BDQ24

C

T

BDQ51

C

T

BDQS24

BDQS51

4

-

BDQ24

T

C

T

4

-

BDQ51

T

C

T

BDQ24

C

BDQ51

C

4

8

VREF2_4/BDQ24

VREF1_4/BDQ24

T

4

8

VREF2_4/BDQ51

VREF1_4/BDQ51

T

C

4-33

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

N14

N13

N15

P15

CFG1

PROGRAMN

CFG0

8

-

CFG1

PROGRAMN

CFG0

8

-

PR30B

INITN

WRITEN

C

PR30B

INITN

WRITEN

C

L12

N16

GND

R14

P14

PR29B

GNDIO8

CCLK

CSN

PR29B

GNDIO8

CCLK

CSN

8

-

8

-

PR30A

DONE

CS1N

D1

T

PR30A

DONE

CS1N

D1

T

M13

R16

VCCIO

M16

P16

PR28B

VCCIO8

PR29A

PR28A

PR27B

GNDIO8

PR26A

PR27A

PR25B

PR26B

VCCIO8

PR25A

PR24B

PR24A

GNDIO8

PR21B

VCCIO3

PR21A

GNDIO3

PR20B

PR20A

RLM0_PLLCAP

PR18B

PR18A

PR17B

GNDIO3

PR17A

PR16B

VCCIO3

PR16A

PR15B

PR15A

PR13B

GNDIO2

PR13A

C

PR28B

VCCIO8

PR29A

PR28A

PR27B

GNDIO8

PR26A

PR27A

PR25B

PR26B

VCCIO8

PR25A

PR24B

PR24A

GNDIO8

PR21B

VCCIO3

PR21A

GNDIO3

PR20B

PR20A

RLM0_PLLCAP

PR18B

PR18A

PR17B

GNDIO3

PR17A

PR16B

VCCIO3

PR16A

PR15B

PR15A

PR13B

GNDIO2

PR13A

C

D0/SPIFASTN

T

C

D0/SPIFASTN

T

C

D2

D3

D2

D3

L15

GND

L14

8

-

D6

D4

D7

D5

T

8

-

D6

D4

D7

D5

T

L16

L10

C

L13

VCCIO

K11

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

K14

K13

GND

K15

3

-

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

C

T

3

-

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

C

T

VCCIO

K16

GND

J16

3

-

RLM0_GPLLC_IN_A**

RLM0_GPLLT_IN_A**

C (LVDS)*

T (LVDS)*

3

-

RLM0_GPLLC_IN_A** C (LVDS)*

J15

RLM0_GPLLT_IN_A**

T (LVDS)*

J14

J13

RLM0_GDLLC_FB_A

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A**

C

T

RLM0_GDLLC_FB_A

RLM0_GDLLT_FB_A

C

T

J12

H12

GND

H13

H15

VCCIO

H16

H11

J11

C (LVDS)*

RLM0_GDLLC_IN_A** C (LVDS)*

3

2

-

RLM0_GDLLT_IN_A**

VREF2_3

T (LVDS)*

C

3

2

-

RLM0_GDLLT_IN_A**

VREF2_3

T (LVDS)*

C

VREF1_3

PCLKC3_0

T

VREF1_3

PCLKC3_0

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

PCLKT3_0

G16

GND

G15

PCLKC2_0/RDQ10

2

PCLKT2_0/RDQ10

T

2

PCLKT2_0/RDQ10

T

4-34

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank Dual Function

Differential

F15

G11

F14

PR11B

PR12B

PR11A

VCCIO2

PR12A

PR10B

PR10A

GNDIO2

PR8B

2

-

RDQ10

C

C (LVDS)*

T

PR11B

PR12B

PR11A

VCCIO2

PR12A

PR10B

PR10A

GNDIO2

PR8B

2

-

RDQ10

C

C (LVDS)*

T

VCCIO

F12

RDQ10

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQ10

T (LVDS)*

C (LVDS)*

T (LVDS)*

G14

G13

GND

F16

RDQS10

2

-

RDQ10

C (LVDS)*

2

-

RDQ10

C (LVDS)*

F9

PR9B

C

T (LVDS)*

T

PR9B

C

T (LVDS)*

T

E16

PR8A

F10

PR9A

VCCIO

D16

D15

C15

C16

GND

D14

B16

VCCIO2

PR7B

VCCIO2

PR7B

RDQ10

C

RDQ10

C

PR7A

T

C (LVDS)*

C

PR7A

T

C (LVDS)*

C

PR4B

PR5B

GNDIO2

PR4A

GNDIO2

PR4A

2

1

-

T (LVDS)*

T

2

1

-

T (LVDS)*

T

PR5A

F13

PR2B

VREF2_2

C (LVDS)*

PR2B

VREF2_2

C (LVDS)*

VCCIO

E13

VCCIO2

PR2A

VCCIO2

PR2A

VREF1_2

VREF2_1

VREF1_1

T (LVDS)*

VREF1_2

VREF2_1

VREF1_1

T (LVDS)*

F11

PT28B

PT28A

GNDIO1

PT27B

PT26B

PT27A

VCCIO1

PT26A

PT25B

PT24B

PT25A

PT24A

PT23B

GNDIO1

PT22B

PT23A

VCCIO1

PT22A

PT21B

PT20B

PT21A

PT20A

C

T

PT55B

PT55A

GNDIO1

PT54B

PT53B

PT54A

VCCIO1

PT53A

PT52B

PT51B

PT52A

PT51A

PT50B

GNDIO1

PT49B

PT50A

VCCIO1

PT49A

PT48B

PT47B

PT48A

PT47A

C

T

E11

GND

A15

1

-

C

T

1

-

C

T

E12

B15

VCCIO

D12

B14

T

C

T

C

T

C14

A14

D13

C13

GND

A13

T

C

1

C

T

1

C

T

B13

VCCIO

A12

T

C

T

C

T

B11

D11

A11

C11

4-35

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

-

GNDIO1

VCCIO

PT37B

PT37A

GNDIO1

PT36B

PT35B

PT36A

PT35A

VCCIO1

PT34B

PT33B

PT34A

PT33A

GNDIO1

PT32B

PT31B

PT32A

PT31A

VCCIO1

PT30B

PT30A

XRES

1

-

D10

C10

GND

B10

A9

PT19B

PT19A

GNDIO1

PT18B

PT17B

PT18A

PT17A

VCCIO1

PT16B

PT15B

PT16A

PT15A

GNDIO1

PT14B

PT13B

PT14A

PT13A

VCCIO1

PT12B

PT12A

XRES

PT10B

GNDIO0

PT10A

PT9B

1

-

C

T

C

T

1

-

C

T

1

-

C

T

A10

B9

VCCIO

A8

C

T

C

T

D9

B8

C9

GND

B7

1

-

C

T

1

0

-

C

T

E9

A7

D8

VCCIO

A6

PCLKC1_0

PCLKT1_0

C

T

PCLKC1_0

PCLKT1_0

C

T

B6

E6

F8

0

-

PCLKC0_0

PCLKT0_0

C

PT28B

GNDIO0

PT28A

PT27B

PT26B

PT27A

VCCIO0

PT26A

PT25B

PT24B

PT25A

PT24A

PT23B

GNDIO0

PT22B

PT23A

VCCIO0

PT22A

PT21B

PT21A

GNDIO0

VCCIO

PCLKC0_0

PCLKT0_0

C

GND

E8

0

-

T

C

T

0

-

T

C

T

A5

A3

PT8B

A4

PT9A

VCCIO

B3

VCCIO0

PT8A

T

C

T

C

T

A2

PT7B

C7

PT6B

B2

PT7A

D7

PT6A

T

D6

PT5B

C

GND

F7

GNDIO0

PT4B

0

-

C

T

0

C

T

C6

PT5A

VCCIO

F6

VCCIO0

PT4A

T

C

T

C

T

C4

PT3B

B4

PT3A

-

4-36

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank Dual Function

Differential

D5

E5

PT2B

PT2A

0

-

VREF2_0

VREF1_0

C

T

PT2B

PT2A

0

-

VREF2_0

VREF1_0

C

T

G7

G9

H7

VCC

-

VCC

-

VCC

-

VCC

-

J10

K10

K8

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

G8

H10

J7

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

GND

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

GND

-

K9

-

C5

0

1

2

3

4

5

6

7

8

-

0

1

2

3

4

5

6

7

8

-

E7

C12

E10

E14

G12

K12

M14

M10

P12

M7

P5

K5

M3

E3

G5

T15

A1

A16

B12

B5

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

C8

GND

-

GND

-

E15

E2

GND

-

GND

-

GND

-

GND

-

H14

H8

GND

-

GND

-

GND

-

GND

-

H9

GND

-

GND

-

J3

GND

-

GND

-

J8

GND

-

GND

-

J9

GND

-

GND

-

M15

M2

P9

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-37

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-6E/SE

LFE2-12E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank Dual Function

Differential

R12

R5

GND

-

GND

-

T1

T16

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-38

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA

LFE2-20E/SE

Ball

Number

Ball Number

C3

Ball/Pad Function

PL2A

Bank

7

-

Dual Function

VREF2_7

Differential

T (LVDS)*

C (LVDS)*

C3

C2

PL2B

VREF1_7

VCCIO

-

VCCIO

GND

D3

VCCIO7

GNDIO7

PL7A

D3

LDQ8

T

T (LVDS)*

C

D4

PL6A

D2

PL7B

GND

E4

GND

E4

GNDIO7

PL6B

7

-

LDQ8

LDQ16

C (LVDS)*

B1

PL13A

PL13B

PL15A

VCCIO

PL14A

PL15B

PL14B

PL16A

GNDIO7

PL16B

PL17A

PL17B

VCCIO7

PL18A

PL18B

GNDIO7

PL19A

PL19B

PL21A

VCCIO6

PL21B

PL22A

GNDIO6

PL22B

PL27A

PL27B

VCC

T

C

T

C1

F5

VCCIO

F4

VCC

F4

LDQ16

LDQS16

T (LVDS)*

C

G6

G4

C (LVDS)*

T (LVDS)*

D1

GND

E1

GND

E1

7

-

LDQ16

C (LVDS)*

F3

T

G3

C

VCCIO

F2

VCCIO

F2

LDQ16

T (LVDS)*

C (LVDS)*

F1

GND

G2

GND

G2

7

6

-

PCLKT7_0/LDQ16

PCLKC7_0/LDQ16

PCLKT6_0/LDQ25

T

C

G1

H6

T (LVDS)*

VCCIO

H5

VCCIO

H5

PCLKC6_0/LDQ25

VREF2_6/LDQ25

C (LVDS)*

T

H4

GND

H3

GND

H3

6

-

VREF1_6/LDQ25

C

H2

LLM0_GDLLT_IN_A**/LDQ25

LLM0_GDLLC_IN_A**/LDQ25

T (LVDS)*

C (LVDS)*

H1

G10

J4

G10

J4

PL28A

PL28B

LLM0_PLLCAP

PL30A

GNDIO6

6

-

LLM0_GDLLT_FB_A/LDQ25

LLM0_GDLLC_FB_A/LDQ25

T

J5

C

J6

K4

LLM0_GPLLT_IN_A**/LDQ34

T (LVDS)*

GND

4-39

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

Ball Number

J1

Ball/Pad Function

PL31A

PL30B

VCCIO6

PL31B

GNDIO6

PL38A

PL39A

PL38B

PL39B

VCCIO6

PL40A

PL41A

PL40B

PL41B

GNDIO6

PL43A

PL42A

PL43B

VCCIO6

PL42B

PL44A

GNDIO6

PL44B

TDI

Bank

6

-

Dual Function

Differential

T

J1

LLM0_GPLLT_FB_A/LDQ34

LLM0_GPLLC_IN_A**/LDQ34

K3

C (LVDS)*

VCCIO

J2

VCCIO

J2

LLM0_GPLLC_FB_A/LDQ34

C

GND

L2

GND

L2

6

-

LDQ42

T (LVDS)*

K2

T

C (LVDS)*

C

L3

K1

VCCIO

L4

VCCIO

L4

LDQ42

T (LVDS)*

L1

T

C (LVDS)*

C

L5

M1

GND

N1

M1

GND

N1

6

-

LDQ42

LDQS42

LDQ42

T

T (LVDS)*

C

N2

P1

VCCIO

P2

VCCIO

P2

LDQ42

C (LVDS)*

T (LVDS)*

R1

GND

R2

GND

R2

6

-

LDQ42

C (LVDS)*

N4

M4

P3

M4

TCK

-

P3

TDO

-

N3

TMS

-

K7

VCCJ

-

M5

K6

M5

PB2A

5

VREF2_5/BDQ6

BDQ6

T

K6

PB3A

M6

R3

M6

PB2B

VREF1_5/BDQ6

BDQ6

C

T

R3

PB5A

P4

PB5B

BDQ6

C

-

VCC

GND

N5

VCCIO

GNDIO5

PB30A

PB30B

PB31A

PB32A

VCCIO5

PB31B

PB32B

-

N5

BDQ33

T

C

T

N6

T2

P6

VCCIO

T3

VCCIO

T3

BDQ33

C

R6

4-40

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

GND

R4

Ball Number

GND

R4

Ball/Pad Function

GNDIO5

PB33A

PB34A

PB33B

PB34B

PB35A

VCCIO5

PB35B

GNDIO5

PB40A

PB40B

VCCIO4

PB41A

PB41B

PB42A

GNDIO4

PB43A

PB42B

PB43B

PB44A

VCCIO4

PB45A

PB44B

PB45B

PB46A

GNDIO4

PB46B

VCCIO

GNDIO4

PB56A

PB57A

PB56B

PB57B

PB58A

PB59A

VCCIO4

PB58B

PB59B

PB60A

GNDIO4

PB61A

PB60B

Bank

-

Dual Function

Differential

5

-

BDQS33

BDQ33

T

C

T

L6

T4

BDQ33

L7

BDQ33

N7

PCLKT5_0/BDQ33

VCCIO

M8

VCCIO

M8

PCLKC5_0/BDQ33

C

GND

P7

GND

P7

4

-

PCLKT4_0/BDQ42

PCLKC4_0/BDQ42

T

R8

C

VCCIO

T5

VCCIO

T5

BDQ42

T

C

T

T6

T8

BDQS42

GND

R7

GND

R7

4

-

BDQ42

T

C

T

T9

T7

L8

VCCIO

P8

VCCIO

P8

BDQ42

T

C

T

L9

N8

R9

GND

R10

-

GND

R10

VCC

GND

N9

4

-

BDQ42

C

-

N9

BDQ60

T

C

T

T10

M9

T10

M9

R11

P10

N11

VCCIO

N10

P11

T11

GND

M11

T12

R11

P10

N11

VCCIO

N10

P11

T11

GND

M11

T12

BDQ60

C

T

BDQS60

4

BDQ60

T

C

4-41

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

Ball Number

L11

Ball/Pad Function

PB61B

Bank

4

-

Dual Function

BDQ60

Differential

L11

C

T

T13

PB62A

BDQ60

R13

VCCIO

T14

R13

PB63A

BDQ60

VCCIO

T14

VCCIO4

PB62B

BDQ60

C

P13

PB63B

GND

N12

M12

R15

N14

N13

N15

P15

GND

N12

GNDIO4

PB64A

4

8

-

VREF2_4/BDQ60

VREF1_4/BDQ60

T

M12

R15

PB64B

C

CFG2

N14

CFG1

N13

PROGRAMN

CFG0

N15

P15

PR44B

WRITEN

C

L12

INITN

N16

GND

R14

P14

N16

PR43B

CSN

GND

R14

GNDIO8

CCLK

8

-

P14

PR44A

CS1N

D1

T

M13

R16

VCCIO

M16

P16

M13

R16

DONE

PR42B

C

VCCIO

M16

P16

VCCIO8

PR43A

D0/SPIFASTN

T

C

PR42A

D2

D3

L15

PR41B

GND

L14

GND

L14

GNDIO8

PR40A

8

-

D6

D4

D7

D5

T

L16

PR41A

L10

PR39B

C

L13

PR40B

VCCIO

K11

VCCIO

K11

VCCIO8

PR39A

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

K14

PR38B

K13

PR38A

GND

K15

GND

K15

GNDIO8

PR31B

3

-

RLM0_GPLLC_FB_A/RDQ34

RLM0_GPLLT_FB_A/RDQ34

C

T

VCCIO

K16

VCCIO

K16

VCCIO3

PR31A

GND

J16

GND

J16

GNDIO3

PR30B

3

RLM0_GPLLC_IN_A**/RDQ34

RLM0_GPLLT_IN_A**/RDQ34

C (LVDS)*

T (LVDS)*

J15

PR30A

J14

RLM0_PLLCAP

4-42

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

Ball Number

J13

Ball/Pad Function

PR28B

PR28A

PR27B

GNDIO3

PR27A

PR22B

VCCIO3

PR22A

PR21B

PR21A

PR19B

GNDIO2

PR19A

PR17B

PR18B

PR17A

VCCIO2

PR18A

PR16B

PR16A

GNDIO2

PR14B

PR15B

PR14A

PR15A

VCCIO2

PR13B

PR13A

PR6B

Bank

3

-

Dual Function

Differential

J13

RLM0_GDLLC_FB_A/RDQ25

RLM0_GDLLT_FB_A/RDQ25

RLM0_GDLLC_IN_A**/RDQ25

C

T

J12

H12

GND

H13

H15

VCCIO

H16

H11

J11

H12

C (LVDS)*

GND

H13

3

2

-

RLM0_GDLLT_IN_A**/RDQ25

VREF2_3/RDQ25

T (LVDS)*

C

H15

VCCIO

H16

VREF1_3/RDQ25

PCLKC3_0/RDQ25

PCLKT3_0/RDQ25

PCLKC2_0/RDQ16

T

H11

C (LVDS)*

T (LVDS)*

C

J11

G16

GND

G15

F15

G16

GND

G15

F15

2

-

PCLKT2_0/RDQ16

RDQ16

T

C

C (LVDS)*

T

G11

F14

G11

F14

RDQ16

VCCIO

F12

VCCIO

F12

RDQ16

T (LVDS)*

C (LVDS)*

T (LVDS)*

G14

G13

GND

F16

G14

G13

GND

F16

RDQS16

2

-

RDQ16

C (LVDS)*

F9

C

T (LVDS)*

T

E16

F10

VCCIO

D16

D15

C15

C16

GND

D14

B16

VCCIO

D16

RDQ16

RDQ8

C

D15

T

C (LVDS)*

C

C15

C16

PR7B

RDQ8

GND

D14

GNDIO2

PR6A

2

1

-

RDQ8

T (LVDS)*

T

B16

PR7A

F13

PR2B

VREF2_2

C (LVDS)*

VCCIO

E13

VCCIO

E13

VCCIO2

PR2A

VREF1_2

VREF2_1

VREF1_1

T (LVDS)*

F11

PT64B

PT64A

GNDIO1

PT63B

PT62B

PT63A

C

T

E11

GND

A15

GND

A15

1

C

T

E12

B15

4-43

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

VCCIO

D12

B14

C14

A14

D13

C13

GND

A13

B13

VCCIO

A12

B11

D11

A11

C11

-

Ball Number

VCCIO

D12

B14

C14

A14

D13

C13

GND

A13

B13

VCCIO

A12

B11

D11

A11

C11

GND

VCC

D10

C10

GND

B10

A9

Ball/Pad Function

VCCIO1

PT62A

PT61B

PT60B

PT61A

PT60A

PT59B

GNDIO1

PT58B

PT59A

VCCIO1

PT58A

PT57B

PT56B

PT57A

PT56A

GNDIO1

VCCIO

PT46B

PT46A

GNDIO1

PT45B

PT44B

PT45A

PT44A

VCCIO1

PT43B

PT42B

PT43A

PT42A

GNDIO1

PT41B

PT40B

PT41A

PT40A

VCCIO1

PT39B

PT39A

XRES

Bank

1

-

Dual Function

Differential

T

C

T

C

1

-

C

T

C

T

-

D10

C10

GND

B10

A9

C

T

1

-

C

T

A10

B9

A10

B9

VCCIO

A8

VCCIO

A8

C

T

D9

B8

C9

GND

B7

GND

B7

1

0

-

C

T

E9

A7

D8

VCCIO

A6

VCCIO

A6

PCLKC1_0

PCLKT1_0

C

T

B6

E6

F8

PT37B

GNDIO0

PT37A

PCLKC0_0

PCLKT0_0

C

T

GND

E8

GND

E8

0

4-44

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

Ball Number

A5

Ball/Pad Function

PT36B

PT35B

PT36A

VCCIO0

PT35A

PT34B

PT33B

PT34A

PT33A

PT32B

GNDIO0

PT31B

PT32A

VCCIO0

PT31A

PT30B

PT30A

GNDIO0

VCCIO

PT2B

Bank

0

-

Dual Function

Differential

A5

C

T

A3

A4

VCCIO

B3

VCCIO

B3

T

C

T

A2

C7

B2

D7

T

D6

C

GND

F7

GND

F7

0

-

C

T

C6

VCCIO

F6

VCCIO

F6

T

C

T

C4

B4

-

GND

VCC

D5

-

D5

VREF2_0

VREF1_0

C

T

E5

PT2A

G7

VCC

G9

VCC

-

H7

VCC

-

J10

K10

K8

J10

K10

K8

VCC

-

VCC

-

VCC

-

G8

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

-

H10

J7

H10

J7

-

K9

-

C5

0

1

2

3

4

5

E7

C12

E10

E14

G12

K12

M14

M10

P12

M7

C12

E10

E14

G12

K12

M14

M10

P12

M7

4-45

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)

LFE2-20E/SE

Ball

Number

Ball Number

P5

Ball/Pad Function

VCCIO5

VCCIO6

VCCIO7

VCCIO8

GND

Bank

Dual Function

Differential

P5

5

6

7

8

-

K5

M3

E3

M3

E3

G5

T15

A1

T15

A1

A16

B12

B5

A16

B12

B5

GND

-

GND

-

GND

-

C8

GND

-

E15

E2

E15

E2

GND

-

GND

-

H14

H8

H14

H8

GND

-

GND

-

H9

GND

-

J3

GND

-

J8

GND

-

J9

GND

-

M15

M2

P9

M15

M2

GND

-

GND

-

P9

GND

-

R12

R5

R12

R5

GND

-

GND

-

T1

GND

-

T16

GND

-

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-46

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

E4

E5

PL2A

PL2B

-

VREF2_7

VREF1_7

PL2A

PL2B

VREF2_7

VREF1_7

-

GNDIO7

PL4A

E3

NC

-

7

-

LDQ8

T (LVDS)*

F4

PL3A

NC

7

-

T

PL5A

T

C (LVDS)*

C

F3

PL4B

F5

PL3B

VCCIO7

PL4A

PL5A

PL4B

PL5B

GNDIO7

NC

7

-

C

PL5B

VCCIO

E2

VCCIO7

PL6A

T (LVDS)*

LDQ8

T (LVDS)*

G6

T

C (LVDS)*

C

PL7A

T

C (LVDS)*

C

E1

PL6B

G7

PL7B

GNDIO

F1

GNDIO7

PL9A

-

7

-

LDQ8

LDQS8

LDQ8

T

T (LVDS)*

C

H4

NC

-

PL8A

F2

NC

-

PL9B

-

VCCIO7

PL8B

H5

NC

-

LDQ8

C (LVDS)*

G1

NC

-

PL11A

PL10A

PL11B

GNDIO

PL10B

PL13A

PL12A

PL13B

PL15A

VCCIO7

PL14A

PL15B

PL14B

PL16A

GNDIO

PL16B

PL17A

VCCIO7

PL17B

PL18A

GNDIO

PL18B

PL19A

PL19B

PL21A

-

T

T (LVDS)*

C

G3

NC

-

G2

NC

-

G4

NC

-

7

-

LDQ8

LDQ16

C (LVDS)*

J4

PL7A

PL6A

PL7B

PL9A

VCCIO7

PL8A

PL9B

PL8B

PL10A

GNDIO7

PL10B

PL11A

VCCIO7

PL11B

PL12A

GNDIO7

PL12B

PL13A

PL13B

PL15A

VCCIO6

PL15B

7

-

LDQ10

T

H1

T (LVDS)*

J5

C

T

C

T

L6

VCCIO

J2

LDQ10

LDQS10

T (LVDS)*

C

LDQ16

LDQS16

T (LVDS)*

C

L5

J1

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

K3

GNDIO

K4

7

-

LDQ10

C (LVDS)*

T

7

-

LDQ16

C (LVDS)*

T

K2

VCCIO

K1

LDQ10

C

LDQ16

C

L4

T (LVDS)*

GNDIO

L3

7

6

LDQ10

C (LVDS)*

7

6

-

LDQ16

C (LVDS)*

L2

PCLKT7_0/LDQ10

PCLKC7_0/LDQ10

PCLKT6_0

T

C

PCLKT7_0/LDQ16

PCLKC7_0/LDQ16

PCLKT6_0/LDQ25

T

C

L1

M5

VCCIO

M6

T (LVDS)*

PCLKC6_0

C (LVDS)*

PL21B

6

PCLKC6_0/LDQ25

C (LVDS)*

4-47

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

6

-

Dual Function

Differential

Bank

6

-

Dual Function

Differential

M3

GNDIO

M4

-

PL16A

GNDIO6

PL16B

-

VREF2_6

T

PL22A

-

VREF2_6/LDQ25

VREF1_6/LDQ25

T

6

-

VREF1_6

C

PL22B

VCCIO6

PL24A

PL23A

PL24B

PL23B

GNDIO

PL25A

PL26A

PL25B

VCCIO6

PL26B

PL27A

PL27B

PL28A

GNDIO

PL28B

LLM0_PLLCAP

PL30A

-

6

-

C

N1

NC

-

LDQ25

T

M2

N2

NC

-

T (LVDS)*

C

NC

-

M1

-

NC

-

C (LVDS)*

-

N3

NC

-

6

-

LDQS25

LDQ25

T (LVDS)*

T

N5

NC

-

N4

NC

-

C (LVDS)*

-

P5

NC

-

LDQ25

C

P1

PL17A

PL17B

PL18A

-

6

-

LLM0_GDLLT_IN_A** T (LVDS)*

LLM0_GDLLC_IN_A** C (LVDS)*

LLM0_GDLLT_IN_A**/LDQ25 T (LVDS)*

LLM0_GDLLC_IN_A**/LDQ25 C (LVDS)*

P2

P4

LLM0_GDLLT_FB_A

T

LLM0_GDLLT_FB_A/LDQ25

T

-

R4

PL18B

LLM0_PLLCAP

PL20A

GNDIO6

PL21A

PL20B

PL21B

PL23A

VCCIO6

PL22A

PL23B

PL22B

GNDIO6

-

6

-

LLM0_GDLLC_FB_A

C

6

-

LLM0_GDLLC_FB_A/LDQ25

C

P6

R1

LLM0_GPLLT_IN_A** T (LVDS)*

LLM0_GPLLT_IN_A**/LDQ34 T (LVDS)*

GNDIO

R3

6

-

LLM0_GPLLT_FB_A

T

PL31A

PL30B

PL31B

PL33A

VCCIO6

PL32A

PL33B

PL32B

GNDIO6

VCCIO6

PL39A

GNDIO

PL39B

PL38A

PL41A

VCCIO6

PL38B

PL41B

PL40A

PL43A

GNDIO

PL43B

PL40B

6

-

LLM0_GPLLT_FB_A/LDQ34

LLM0_GPLLC_IN_A/LDQ34

LLM0_GPLLC_FB_A/LDQ34

LDQ34

T

R2

LLM0_GPLLC_IN_A** C (LVDS)*

C (LVDS)*

T4

LLM0_GPLLC_FB_A

C

T

C

T

T5

VCCIO

T1

T (LVDS)*

C

LDQ34

T (LVDS)*

C

T3

T2

C (LVDS)*

GNDIO

-

6

-

V1

PL25A

-

6

-

LDQ28

T

LDQ42

T

-

V2

PL25B

PL24A

PL27A

VCCIO6

PL24B

PL27B

PL26A

PL29A

GNDIO6

PL29B

PL26B

6

-

LDQ28

C

T (LVDS)*

T

6

-

LDQ42

C

T (LVDS)*

T

U1

U3

VCCIO

U2

LDQ28

C (LVDS)*

LDQ42

C (LVDS)*

U4

C

T (LVDS)*

T

C

T (LVDS)*

T

R6

R7

GNDIO

T7

6

LDQ28

C

6

LDQ42

C

T6

C (LVDS)*

4-48

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

6

-

Dual Function

Differential

Bank

6

-

Dual Function

Differential

AA2

VCCIO

Y1

PL31A

VCCIO6

PL28A

PL31B

PL28B

PL30B

GNDIO6

PL30A

TDI

LDQ28

T

PL45A

VCCIO6

PL42A

PL45B

PL42B

PL44B

GNDIO

PL44A

TDI

LDQ42

T

LDQS28

LDQ28

T (LVDS)*

C

LDQS42

LDQ42

T (LVDS)*

C

AA1

W1

C (LVDS)*

V3

GNDIO

V4

6

-

LDQ28

T (LVDS)*

6

-

LDQ42

T (LVDS)*

U5

U7

TCK

-

TCK

-

V6

TDO

-

TDO

-

V5

TMS

-

TMS

-

T8

VCCJ

PB3A

-

VCCJ

-

W4

5

-

BDQ6

VREF2_5/BDQ6

BDQ6

T

C

T

PB3A

5

-

BDQ6

VREF2_5/BDQ6

BDQ6

T

C

T

Y3

PB2A

W3

PB3B

Y2

PB2B

VREF1_5/BDQ6

BDQ6

PB2B

VREF1_5/BDQ6

BDQ6

AB3

VCCIO

W5

PB5A

VCCIO5

PB4A

VCCIO5

PB4A

BDQ6

T

C

T

BDQ6

T

C

T

AB2

W6

PB5B

PB4B

AB5

GNDIO

Y4

PB7A

GNDIO5

PB6A

GNDIO

PB6A

5

-

BDQS6

BDQ6

T

C

T

5

-

BDQS6

BDQ6

T

C

T

AB4

AA3

AB6

VCCIO

AA5

AA6

Y5

PB7B

PB6B

PB9A

VCCIO5

PB8A

VCCIO5

PB8A

BDQ6

T

C

BDQ6

T

C

PB9B

PB8B

GNDIO

-

GNDIO5

-

GNDIO

VCCIO5

PB21A

PB20A

PB21B

PB20B

PB23A

VCCIO5

PB22A

PB23B

PB22B

PB25A

GNDIO

-

5

-

Y6

PB12A

PB11A

PB12B

PB11B

PB14A

VCCIO5

PB13A

PB14B

PB13B

PB16A

GNDIO5

5

-

BDQ15

T

C

T

BDQ24

T

C

T

W7

Y7

W8

U8

VCCIO

AA7

U9

BDQ15

T

C

T

BDQ24

T

C

T

AB7

Y8

GNDIO

4-49

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

5

-

Dual Function

Differential

Bank

5

-

Dual Function

Differential

W9

AA8

PB15A

PB16B

PB15B

PB18A

VCCIO5

PB17A

PB18B

PB17B

GNDIO5

PB21A

PB20A

PB21B

PB20B

PB23A

PB22A

VCCIO5

PB23B

PB22B

GNDIO5

PB25A

PB24A

PB25B

PB24B

PB26A

VCCIO5

PB26B

GNDIO5

PB32A

PB32B

VCCIO4

PB31A

PB31B

PB34A

GNDIO4

PB33A

PB34B

PB33B

PB36A

VCCIO4

PB35A

PB36B

PB35B

PB37A

GNDIO4

PB37B

BDQS15

BDQ15

T

C

T

PB24A

PB25B

PB24B

PB27A

VCCIO5

PB26A

PB27B

PB26B

GNDIO

PB30A

PB29A

PB30B

PB29B

PB32A

PB31A

VCCIO5

PB32B

PB31B

GNDIO5

PB34A

PB33A

PB34B

PB33B

PB35A

VCCIO5

PB35B

GNDIO5

PB41A

PB41B

VCCIO4

PB40A

PB40B

PB43A

GNDIO4

PB42A

PB43B

PB42B

PB45A

VCCIO4

PB44A

PB45B

PB44B

PB46A

GNDIO4

PB46B

BDQS24

BDQ24

T

C

T

V9

AB8

VCCIO

W10

BDQ15

T

C

BDQ24

T

C

AA9

V10

GNDIO

Y10

5

-

BDQ24

T

C

T

5

-

BDQ33

T

C

T

AB9

AA10

AB10

AB11

U10

VCCIO

AA11

U11

BDQ24

C

BDQ33

C

GNDIO

AB12

Y11

5

-

BDQ24

BDQS24

T

C

T

5

-

BDQ33

BDQS33

T

C

T

AA12

W11

BDQ24

BDQ33

BDQ24

BDQ33

AB13

VCCIO

AB14

GNDIO

Y12

PCLKT5_0/BDQ24

PCLKT5_0/BDQ33

PCLKC5_0/BDQ24

C

PCLKC5_0/BDQ33

C

4

-

BDQ33

T

4

-

BDQ42

T

W12

C

VCCIO

U12

PCLKT4_0/BDQ33

PCLKC4_0/BDQ33

BDQ33

T

C

T

PCLKT4_0/BDQ42

PCLKC4_0/BDQ42

BDQ42

T

C

T

V12

U13

GNDIO

AA13

U14

4

-

BDQS33

BDQ33

T

C

T

4

-

BDQS42

BDQ42

T

C

T

Y13

AB16

VCCIO

AB15

AB17

AA14

W13

BDQ33

T

C

T

BDQ42

T

C

T

GNDIO

W14

4

BDQ33

C

4

BDQ42

C

4-50

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

4

-

Dual Function

Differential

Bank

4

-

Dual Function

Differential

AB18

AB19

Y15

PB39A

PB39B

PB41A

PB40A

VCCIO4

PB41B

PB40B

GNDIO4

PB43A

PB42A

PB43B

PB42B

PB45A

PB44A

VCCIO4

PB45B

PB44B

PB46A

PB46B

GNDIO4

PB49A

PB49B

PB48A

VCCIO4

PB51A

PB48B

PB51B

PB50A

GNDIO4

PB53A

PB50B

PB53B

PB52A

VCCIO4

PB54A

PB52B

PB54B

GNDIO4

PB55A

PB55B

CFG2

BDQ42

T

C

T

PB48A

PB48B

PB50A

PB49A

VCCIO4

PB50B

PB49B

GNDIO

PB52A

PB51A

PB52B

PB51B

PB54A

PB53A

VCCIO4

PB54B

PB53B

PB55A

PB55B

GNDIO

PB58A

PB58B

PB57A

VCCIO4

PB60A

PB57B

PB60B

PB59A

GNDIO4

PB62A

PB59B

PB62B

PB61A

VCCIO4

PB63A

PB61B

PB63B

GNDIO4

PB64A

PB64B

CFG2

BDQ51

T

C

T

V14

VCCIO

AA15

W15

GNDIO

AB20

AA16

AB21

AA17

Y16

BDQ42

C

BDQ51

C

4

-

BDQ42

BDQS42

BDQ42

T

C

T

4

-

BDQ51

BDQS51

BDQ51

T

C

T

U15

VCCIO

W16

U16

BDQ42

C

T

BDQ51

C

T

AA18

AA20

GNDIO

V16

C

4

-

BDQ51

T

C

T

4

-

BDQ60

T

C

T

V17

AA21

VCCIO

Y19

BDQS51

BDQ51

T

C

T

BDQS60

BDQ60

T

C

T

AA22

Y20

Y18

GNDIO

Y21

4

-

BDQ51

T

C

T

4

-

BDQ60

T

C

T

Y17

Y22

W17

VCCIO

U18

BDQ51

T

C

BDQ60

T

C

W18

V18

GNDIO

T15

4

8

VREF2_4/BDQ51

VREF1_4/BDQ51

T

4

8

VREF2_4/BDQ60

VREF1_4/BDQ60

T

T16

C

W19

V19

CFG1

V20

PROGRAMN

CFG0

PROGRAMN

CFG0

W20

U22

PR28B

D1/SPID6

C

PR42B

D1/SPID6

C

4-51

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

8

-

Dual Function

Differential

Bank

8

-

Dual Function

Differential

V22

R16

GNDIO

W22

R17

V21

VCCIO

U19

T17

INITN

PR30B

GNDIO8

CCLK

INITN

PR44B

GNDIO8

CCLK

WRITEN

C

WRITEN

C

8

-

8

-

PR30A

DONE

VCCIO8

PR29B

PR26B

PR29A

PR28A

GNDIO8

PR26A

PR27B

PR25B

PR27A

VCCIO8

PR25A

PR24B

PR24A

-

CS1N

T

PR44A

DONE

CS1N

T

VCCIO8

PR43B

PR40B

PR43A

PR42A

GNDIO8

PR40A

PR41B

PR39B

PR41A

VCCIO8

PR39A

PR38B

PR38A

VCCIO3

GNDIO3

PR32B

PR33B

PR32A

PR33A

VCCIO3

PR31B

PR31A

PR30B

PR30A

RLM0_PLLCAP

PR28B

PR27B

GNDIO3

PR28A

PR27A

PR26B

VCCIO3

PR26A

PR23B

GNDIO

PR24B

PR23A

PR24A

CSN

C

T

CSN

C

T

D5

D0/SPIFASTN

D2

D5

D0/SPIFASTN

D2

U20

U21

GNDIO

T18

8

-

D6

D3

D7

D4

T

C

T

8

3

-

D6

D3

D7

D4

T

C

T

T20

T21

T19

VCCIO

T22

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

R18

R19

-

GNDIO

P18

R22

P19

R21

VCCIO

R20

P22

P21

N21

N17

N22

M22

GNDIO

N20

M21

N19

-

GNDIO3

PR22B

PR23B

PR22A

PR23A

VCCIO3

PR21B

PR21A

PR20B

PR20A

RLM0_PLLCAP

PR18B

PR17B

GNDIO3

PR18A

PR17A

NC

-

3

-

C (LVDS)*

3

-

RDQ34

C (LVDS)*

C

T (LVDS)*

T

C

T (LVDS)*

T

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

C

T

RLM0_GPLLC_FB_A/RDQ34

RLM0_GPLLT_FB_A/RDQ34

C

T

RLM0_GPLLC_IN_A** C (LVDS)*

RLM0_GPLLT_IN_A** T (LVDS)*

RLM0_GPLLC_IN_A**/RDQ34 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ34 T (LVDS)*

RLM0_GDLLC_FB_A

C

RLM0_GDLLC_FB_A/RDQ25

C

RLM0_GDLLC_IN_A** C (LVDS)*

RLM0_GDLLC_IN_A**/RDQ25 C (LVDS)*

3

-

RLM0_GDLLT_FB_A

T

3

-

RLM0_GDLLT_FB_A/RDQ25

T

RLM0_GDLLT_IN_A** T (LVDS)*

RLM0_GDLLT_IN_A**/RDQ25 T (LVDS)*

RDQ25

C

-

M19

J22

NC

-

RDQ25

T

NC

-

C (LVDS)*

-

L22

NC

-

3

RDQ25

C

T (LVDS)*

T

H22

K22

NC

-

NC

-

4-52

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

3

2

-

Dual Function

Differential

Bank

3

2

-

Dual Function

Differential

M20

VCCIO

L21

PR16B

VCCIO3

PR16A

PR15B

PR15A

PR13B

GNDIO2

PR13A

PR12B

PR10B

PR12A

VCCIO2

PR10A

PR11B

PR11A

GNDIO2

PR8B

PR9B

PR8A

PR9A

VCCIO2

PR6B

PR7B

PR6A

PR7A

NC

VREF2_3

C

PR22B

VCCIO3

PR22A

PR21B

PR21A

PR19B

GNDIO2

PR19A

PR18B

PR16B

PR18A

VCCIO2

PR16A

PR17B

PR17A

GNDIO2

PR14B

PR15B

PR14A

PR15A

VCCIO2

PR12B

PR13B

PR12A

PR13A

PR10B

PR11B

GNDIO

PR10A

PR11A

PR8B

VREF2_3/RDQ25

C

VREF1_3

PCLKC3_0

T

VREF1_3/RDQ25

PCLKC3_0/RDQ25

PCLKT3_0/RDQ25

PCLKC2_0/RDQ16

T

K21

J21

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

PCLKT3_0

M18

GNDIO

L17

PCLKC2_0/RDQ10

2

-

PCLKT2_0/RDQ10

RDQ10

T

2

-

PCLKT2_0/RDQ16

RDQ16

T

L19

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

K18

L20

RDQ10

RDQ16

RDQ10

RDQ16

VCCIO

K19

L18

RDQS10

RDQ10

T (LVDS)*

RDQS16

RDQ16

T (LVDS)*

C

T

C

T

K17

GNDIO

J17

2

-

RDQ10

C (LVDS)*

2

-

RDQ16

C (LVDS)*

G22

J18

C

T (LVDS)*

T

C

T (LVDS)*

T

F22

VCCIO

H21

K20

G21

J19

RDQ10

C (LVDS)*

RDQ16

RDQ8

C (LVDS)*

C

T (LVDS)*

T

C

T (LVDS)*

T

C (LVDS)*

C

D22

F21

NC

-

RDQ8

-

E21

E22

H19

G20

-

NC

-

2

-

RDQ8

T (LVDS)*

NC

-

T

C (LVDS)*

C

NC

-

NC

-

PR9B

-

VCCIO2

PR8A

G19

F20

NC

-

RDQS8

RDQ8

T (LVDS)*

NC

-

PR9A

T

G17

GNDIO

E20

F19

PR5B

GNDIO2

PR4B

PR5A

PR4A

PR3B

VCCIO2

NC

2

-

C

PR7B

C

GNDIO2

PR6B

2

-

C (LVDS)*

2

RDQ8

C (LVDS)*

T

T (LVDS)*

C

PR7A

T

T (LVDS)*

C

D20

F18

PR6A

PR5B

VCCIO

C21

F16

VCCIO2

PR4B

RDQ8

C (LVDS)*

T

PR3A

NC

2

-

T

PR5A

C22

PR4A

T (LVDS)*

4-53

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

-

GNDIO

PR2B

D19

PR2B

2

1

-

VREF2_2

VREF1_2

VREF2_1

VREF1_1

C (LVDS)*

2

1

-

VREF2_2

VREF1_2

VREF2_1

VREF1_1

C (LVDS)*

E19

PR2A

T (LVDS)*

PR2A

T (LVDS)*

B21

PT55B

PT55A

GNDIO1

PT53B

PT54B

PT53A

PT54A

VCCIO1

PT51B

PT52B

PT51A

PT52A

GNDIO1

PT49B

PT50B

PT49A

PT50A

VCCIO1

PT47B

PT48B

PT47A

PT48A

PT46B

GNDIO1

PT46A

PT44B

PT45B

PT44A

VCCIO1

PT45A

PT42B

PT43B

PT42A

PT43A

PT40B

GNDIO1

PT40A

VCCIO1

PT39A

PT39B

PT37B

PT36B

C

T

PT64B

PT64A

GNDIO1

PT62B

PT63B

PT62A

PT63A

VCCIO1

PT60B

PT61B

PT60A

PT61A

GNDIO1

PT58B

PT59B

PT58A

PT59A

VCCIO1

PT56B

PT57B

PT56A

PT57A

PT55B

GNDIO1

PT55A

PT53B

PT54B

PT53A

VCCIO1

PT54A

PT51B

PT52B

PT51A

PT52A

PT49B

GNDIO1

PT49A

VCCIO1

PT48A

PT48B

PT46B

PT45B

C

T

B22

GNDIO

D18

1

-

C

T

1

-

C

T

C20

E18

C19

VCCIO

D17

C

T

C

T

B20

C18

A19

GNDIO

A18

1

-

C

T

1

-

C

T

A21

B18

A20

VCCIO

D16

C

T

C

T

G16

E16

G15

C17

T

C

GNDIO

C16

1

-

T

C

T

1

-

T

C

T

A17

B17

A16

VCCIO

B16

T

C

T

C

T

E15

C15

F15

D15

T

B15

C

GNDIO

A15

1

T

1

T

VCCIO

A14

T

C

T

C

B14

D14

E14

4-54

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

GNDIO

C13

F14

GNDIO1

PT37A

PT36A

PT35B

PT34B

VCCIO1

PT35A

PT34A

PT33B

GNDIO1

PT33A

PT31B

PT30B

VCCIO1

PT31A

PT30A

XRES

GNDIO1

PT46A

PT45A

PT44B

PT43B

VCCIO1

PT44A

PT43A

PT42B

GNDIO1

PT42A

PT40B

PT39B

VCCIO1

PT40A

PT39A

XRES

1

-

T

1

-

T

A13

C

E13

VCCIO

B13

T

C

T

C

D13

E12

GNDIO

D12

A12

1

0

-

T

C

1

0

-

T

C

B12

PCLKC1_0

VCCIO

A11

T

C12

F12

PCLKT1_0

PCLKC0_0

PCLKT0_0

PCLKT1_0

PCLKC0_0

PCLKT0_0

B10

PT28B

GNDIO0

PT28A

PT26B

PT27B

PT26A

VCCIO0

PT27A

PT24B

PT25B

PT24A

PT25A

GNDIO0

PT23B

VCCIO0

PT23A

PT20B

PT21B

PT20A

PT21A

GNDIO0

PT17B

PT18B

PT17A

PT18A

VCCIO0

PT15B

PT16B

C

PT37B

GNDIO0

PT37A

PT35B

PT36B

PT35A

VCCIO0

PT36A

PT33B

PT34B

PT33A

PT34A

GNDIO0

PT32B

VCCIO0

PT32A

PT29B

PT30B

PT29A

PT30A

GNDIO0

PT26B

PT27B

PT26A

PT27A

VCCIO0

PT24B

PT25B

C

GNDIO

B11

0

-

T

C

T

0

-

T

C

T

C11

A10

C10

VCCIO

A9

T

C

T

C

T

A8

E11

A7

F11

GNDIO

B8

0

-

C

0

-

C

VCCIO

B9

T

C

T

C

T

C8

B7

D8

A6

GNDIO

C7

0

C

T

0

C

T

D10

C6

E10

VCCIO

F10

C

B6

4-55

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

0

-

Dual Function

Differential

Bank

0

-

Dual Function

Differential

D9

B5

PT15A

PT16A

GNDIO0

PT13B

PT14B

PT13A

PT14A

VCCIO0

PT11B

PT12B

PT11A

PT12A

GNDIO0

-

T

PT24A

PT25A

GNDIO0

PT22B

PT23B

PT22A

PT23A

VCCIO0

PT20B

PT21B

PT20A

PT21A

GNDIO0

VCCIO0

PT10B

PT10A

GNDIO0

PT8B

T

GNDIO

A5

0

-

C

T

0

-

C

T

F9

A4

E9

VCCIO

G8

C

T

C

T

A3

E8

A2

GNDIO

-

0

-

C3

PT10B

PT10A

-

0

-

C

T

C

T

B3

-

E7

PT8B

PT9B

PT8A

PT9A

VCCIO0

PT6B

PT7B

PT6A

PT7A

GNDIO0

PT4B

PT5B

PT4A

PT5A

VCCIO0

PT2B

PT3B

PT2A

PT3A

VCC

0

-

C

T

0

-

C

T

F8

PT9B

F7

PT8A

D7

PT9A

VCCIO

D4

VCCIO0

PT6B

C

T

C

T

D5

PT7B

C4

PT6A

D6

PT7A

GNDIO

J7

GNDIO

PT4B

0

-

C

T

0

-

C

T

B2

PT5B

H7

PT4A

B1

PT5A

VCCIO

D1

VCCIO0

PT2B

VREF2_0

VREF1_0

C

T

VREF2_0

VREF1_0

C

T

D3

PT3B

C1

PT2A

C2

PT3A

J10

J11

J12

J13

K14

K9

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

L14

L9

VCC

-

VCC

-

VCC

-

VCC

-

M14

VCC

-

VCC

-

4-56

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

M9

N14

N9

VCC

-

VCC

-

VCC

-

VCC

-

P10

P11

P12

P13

G10

G9

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

0

1

2

3

4

5

6

7

8

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

0

1

2

3

4

5

6

7

8

-

H9

H8

G11

G12

G13

G14

H14

H15

J15

K16

L16

M16

N16

P16

R14

T12

T13

T14

R9

T10

T11

T9

N7

P7

P8

R8

J8

K7

L7

M7

P15

R15

C5

D11

E17

E6

-

4-57

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

F13

G18

G5

VCCAUX

GND

-

VCCAUX

GND

-

K5

M17

P17

R5

V11

V13

V15

V7

V8

A1

A22

AA19

AA4

AB1

AB22

B19

B4

GND

C14

C9

GND

D2

GND

D21

F17

F6

GND

H10

H11

H12

H13

J14

J20

J3

GND

J9

GND

K10

K11

K12

K13

K15

K8

GND

L10

L11

L12

L13

L15

GND

4-58

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA

LFE2-12E/12SE

LFE2-20E/20SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

L8

M10

M11

M12

M13

M15

M8

GND

NC

-

GND

NC

-

N10

N11

N12

N13

N15

N8

P14

P20

P3

P9

R10

R11

R12

R13

U17

U6

W2

W21

Y14

Y9

H6

J6

NC

H3

NC

H2

NC

H17

H16

H20

H18

K6

NC

J16

N18

N6

NC

VCC

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-59

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

E4

E5

PL2A

PL2B

VREF2_7/LDQ6

VREF1_7/LDQ6

PL2A

PL2B

VREF2_7

VREF1_7

VCCIO

GNDIO

E3

VCCIO7

GNDIO7

PL10A

PL10B

PL11A

PL11B

PL12A

VCCIO7

PL12B

PL13A

PL13B

PL14A

GNDIO7

PL14B

PL15A

PL15B

VCCIO7

PL16A

PL16B

PL17A

PL17B

GNDIO7

-

GNDIO7

VCCIO

PL12A

PL12B

PL13A

PL13B

PL14A

VCCIO

PL14B

PL15A

PL15B

PL16A

GNDIO7

PL16B

PL17A

PL17B

VCCIO

PL18A

PL18B

PL19A

PL19B

GNDIO7

VCCIO

PL25A

VCCIO

PL25B

PL26A

PL26B

GNDIO7

VCCIO

PL37A

PL38A

PL38B

VCCIO

PL39A

PL39B

PL40A

PL40B

GNDIO7

PL41A

PL41B

PL42A

VCCIO

PL42B

PL43A

-

7

-

7

-

LDQ14

T (LVDS)*

C (LVDS)*

T

LDQ16

T (LVDS)*

C (LVDS)*

T

F3

F4

F5

C

E2

T (LVDS)*

VCCIO

E1

LDQ14

LDQS14

C (LVDS)*

LDQ16

LDQS16

C (LVDS)*

G6

T

C

T

C

G7

H4

T (LVDS)*

GNDIO

H5

7

-

LDQ14

C (LVDS)*

7

-

LDQ16

C (LVDS)*

F1

T

F2

C

VCCIO

G3

LDQ14

T (LVDS)*

LDQ16

T (LVDS)*

G4

C (LVDS)*

G1

T

G2

C

GNDIO

-

7

-

H6

NC

-

LUM0_SPLLT_IN_A/LDQ24

T

-

J6

NC

-

LUM0_SPLLC_IN_A/LDQ24

LUM0_SPLLT_FB_A/LDQ24

LUM0_SPLLC_FB_A/LDQ24

C

T

H3

NC

-

H2

NC

-

C

-

7

-

H1

PL18A

PL19A

PL19B

VCCIO7

PL20A

PL20B

PL21A

PL21B

GNDIO7

PL22A

PL22B

PL23A

VCCIO7

PL23B

PL24A

7

-

LDQ22

LDQ41

J4

T

J5

C

VCCIO

J2

LDQ22

T (LVDS)*

LDQ41

T (LVDS)*

J1

C (LVDS)*

L6

T

L5

C

GNDIO

K3

7

LDQS22

LDQ22

T (LVDS)*

C (LVDS)*

T

7

LDQS41

LDQ41

T (LVDS)*

C (LVDS)*

T

K4

K2

VCCIO

K1

LDQ22

C

LDQ41

C

L4

T (LVDS)*

4-60

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

C (LVDS)*

T

Bank

7

-

Dual Function

Differential

C (LVDS)*

T

L3

L2

PL24B

PL25A

LDQ22

PL43B

PL44A

GNDIO7

PL44B

PL46A

PL46B

PL47A

PL47B

PL48A

VCCIO

PL48B

PL49A

PL49B

GNDIO6

VCCIO

PL58A

PL58B

PL59A

VCCIO

PL59B

PL60A

PL60B

PL61A

GNDIO6

PL61B

LLM0_PLLCAP

PL63A

PL63B

PL64A

PL64B

PL65A

VCCIO

PL65B

PL66A

PL66B

VCCIO

GNDIO6

PL71A

PL71B

PL72A

PL72B

VCCIO

PL73A

PL73B

PL74A

PL74B

GNDIO6

LDQ41

PCLKT7_0/LDQ22

PCLKT7_0/LDQ41

GNDIO

L1

GNDIO7

PL25B

7

6

-

PCLKC7_0/LDQ22

PCLKT6_0/LDQ31

PCLKC6_0/LDQ31

VREF2_6/LDQ31

VREF1_6/LDQ31

LDQ31

C

7

6

-

PCLKC7_0/LDQ41

PCLKT6_0/LDQ50

PCLKC6_0/LDQ50

VREF2_6/LDQ50

VREF1_6/LDQ50

LDQ50

C

M5

PL27A

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

M6

PL27B

M3

PL28A

M4

PL28B

C

M2

PL29A

T (LVDS)*

VCCIO

M1

VCCIO6

PL29B

LDQ31

C (LVDS)*

LDQ50

C (LVDS)*

N1

PL30A

T

N2

PL30B

C

GNDIO

VCCIO

N3

GNDIO6

VCCIO6

PL39A

6

-

6

-

LDQS39***

LDQ39

T (LVDS)*

C (LVDS)*

T

LDQS58***

LDQ58

T (LVDS)*

C (LVDS)*

T

N4

PL39B

N5

PL40A

LDQ39

LDQ58

VCCIO

P5

VCCIO6

PL40B

LDQ39

C

LDQ58

C

P1

PL41A

LLM0_GDLLT_IN_A**/LDQ39

T (LVDS)*

LLM0_GDLLT_IN_A**/LDQ58

T (LVDS)*

P2

PL41B

LLM0_GDLLC_IN_A**/LDQ39 C (LVDS)*

LLM0_GDLLC_IN_A**/LDQ58 C (LVDS)*

P4

PL42A

LLM0_GDLLT_FB_A/LDQ39

LLM0_GDLLC_FB_A/LDQ39

LLM0_GPLLT_IN_A**/LDQ48

T

LLM0_GDLLT_FB_A/LDQ58

LLM0_GDLLC_FB_D/LDQ58

LLM0_GPLLT_IN_A**/LDQ67

T

GNDIO

R4

GNDIO6

PL42B

6

-

C

6

-

C

P6

LLM0_PLLCAP

PL44A

R1

T (LVDS)*

R2

PL44B

LLM0_GPLLC_IN_A**/LDQ48 C (LVDS)*

LLM0_GPLLC_IN_A**/LDQ67 C (LVDS)*

R3

PL45A

LLM0_GPLLT_FB_A/LDQ48

LLM0_GPLLC_FB_A/LDQ48

LDQ48

T

C

LLM0_GPLLT_FB_A/LDQ67

LLM0_GPLLC_FB_A/LDQ67

LDQ67

T

C

T4

PL45B

T1

PL46A

T (LVDS)*

VCCIO

T2

VCCIO6

PL46B

LDQ48

C (LVDS)*

LDQ67

C (LVDS)*

T5

PL47A

T

T3

PL47B

C

GNDIO

VCCIO

U1

GNDIO6

VCCIO6

PL52A

-

6

-

LDQ56

T (LVDS)*

6

-

LDQ75

T (LVDS)*

U2

PL52B

C (LVDS)*

V1

PL53A

T

V2

PL53B

C

VCCIO

R6

VCCIO6

PL54A

LDQ56

T (LVDS)*

LDQ75

T (LVDS)*

T6

PL54B

C (LVDS)*

U3

PL55A

T

U4

PL55B

C

GNDIO

GNDIO6

4-61

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

6

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

T

Bank

6

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

T

Y1

W1

PL56A

PL56B

PL57A

VCCIO6

PL57B

PL58A

PL58B

PL59A

GNDIO6

PL59B

TCK

LDQS56

LDQ56

PL75A

PL75B

PL76A

VCCIO

PL76B

PL77A

PL77B

PL78A

GNDIO6

PL78B

TCK

LDQS75

LDQ75

R7

VCCIO

T7

LDQ56

C

LDQ75

C

V4

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

V3

AA2

GNDIO

AA1

U7

6

-

LDQ56

C

6

-

LDQ75

C

U5

TDI

-

TDI

-

V5

TMS

-

TMS

-

V6

TDO

-

TDO

-

T8

VCCJ

-

VCCJ

PB2A

-

Y3

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

Y2

PB2B

W4

PB3A

W3

PB3B

BDQ6

C

T

PB3B

BDQ6

C

T

W5

PB4A

BDQ6

PB4A

BDQ6

W6

PB4B

BDQ6

C

PB4B

BDQ6

C

VCCIO

AB3

AB2

GNDIO

Y4

VCCIO5

PB5A

VCCIO

PB5A

BDQ6

T

BDQ6

T

PB5B

C

PB5B

C

GNDIO5

PB6A

GNDIO5

PB6A

5

-

BDQS6

BDQ6

T

C

T

5

-

BDQS6

BDQ6

T

C

T

AA3

AB5

AB4

AA5

Y5

PB6B

PB7A

PB7B

C

T

PB7B

C

T

PB8A

PB8B

C

PB8B

C

VCCIO

AB6

AA6

GNDIO

VCCIO

W7

VCCIO5

PB9A

VCCIO

PB9A

BDQ6

T

BDQ6

T

PB9B

C

PB9B

C

GNDIO5

VCCIO5

PB20A

PB20B

PB21A

PB21B

PB22A

VCCIO5

PB22B

PB23A

PB23B

PB24A

GNDIO5

VCCIO

PB29A

PB29B

PB30A

PB30B

PB31A

VCCIO

PB31B

PB32A

PB32B

PB33A

GNDIO5

5

-

5

-

BDQ24

T

C

T

C

T

BDQ33

T

C

T

C

T

W8

Y6

Y7

AA7

VCCIO

AB7

U8

BDQ24

BDQS24

C

T

C

T

BDQ33

BDQS33

C

T

C

T

U9

W9

GNDIO

4-62

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

5

-

Dual Function

Differential

Bank

5

-

Dual Function

Differential

V9

Y8

PB24B

PB25A

PB25B

PB26A

VCCIO5

PB26B

PB27A

PB27B

GNDIO5

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

VCCIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

PB40A

VCCIO4

PB40B

PB41A

PB41B

PB42A

GNDIO4

PB42B

PB43A

PB43B

PB44A

VCCIO4

PB44B

PB45A

PB45B

PB46A

GNDIO4

PB46B

PB48A

PB48B

BDQ24

C

T

C

T

PB33B

PB34A

PB34B

PB35A

VCCIO

PB35B

PB36A

PB36B

GNDIO5

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

VCCIO

PB41A

PB41B

GNDIO5

PB42A

PB42B

PB43A

PB43B

PB44A

PB44B

VCCIO

GNDIO5

PB49A

VCCIO

PB49B

PB50A

PB50B

PB51A

GNDIO4

PB51B

PB52A

PB52B

PB53A

VCCIO

PB53B

PB54A

PB54B

PB55A

GNDIO4

PB55B

PB57A

PB57B

BDQ33

C

T

C

T

AA8

W10

VCCIO

V10

BDQ24

C

T

BDQ33

C

T

AB8

AA9

C

GNDIO

AB9

5

-

BDQ33

T

C

T

5

-

BDQ42

T

C

T

AB10

Y10

AA10

U10

C

T

C

T

U11

C

VCCIO

AB11

AA11

GNDIO

Y11

BDQ33

T

BDQ42

T

C

5

-

BDQS33

BDQ33

T

C

T

5

-

BDQS42

BDQ42

T

C

T

W11

AB12

AA12

AB13

AB14

VCCIO

GNDIO

U12

BDQ33

BDQ42

BDQ33

C

T

BDQ42

C

T

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

PCLKT5_0/BDQ42

PCLKC5_0/BDQ42

C

4

-

PCLKT4_0/BDQ42

T

4

-

PCLKT4_0/BDQ51

T

VCCIO

V12

PCLKC4_0/BDQ42

BDQ42

C

T

C

T

PCLKC4_0/BDQ51

BDQ51

C

T

C

T

Y12

W12

BDQ42

BDQ51

AA13

GNDIO

Y13

BDQS42

BDQS51

4

-

BDQ42

C

T

C

T

4

-

BDQ51

C

T

C

T

U13

U14

AB15

VCCIO

AA14

AB16

AB17

W13

BDQ42

C

T

C

T

BDQ51

C

T

C

T

GNDIO

W14

4

BDQ42

BDQ51

C

T

4

BDQ51

BDQ60

C

T

AB18

AB19

C

4-63

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

4

-

Dual Function

Differential

Bank

4

-

Dual Function

Differential

V14

W15

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

PB54A

PB54B

PB55A

PB55B

GNDIO4

VCCIO4

PB66A

PB66B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

PB72A

PB72B

PB73A

PB73B

GNDIO4

CFG2

BDQ51

T

PB58A

PB58B

VCCIO

PB59A

PB59B

GNDIO4

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO

PB63A

PB63B

PB64A

PB64B

GNDIO4

VCCIO

PB75A

PB75B

PB76A

PB76B

VCCIO

PB77A

PB77B

GNDIO4

PB78A

PB78B

PB79A

PB79B

PB80A

PB80B

VCCIO

PB81A

PB81B

PB82A

PB82B

GNDIO4

CFG2

BDQ60

T

C

VCCIO

Y15

BDQ51

T

BDQ60

T

AA15

GNDIO

AA16

AA17

AB20

AB21

U15

C

4

-

BDQS51

BDQ51

T

C

T

4

-

BDQS60

BDQ60

T

C

T

C

T

C

T

U16

C

VCCIO

Y16

BDQ51

T

C

T

BDQ60

T

C

T

W16

AA18

AA20

GNDIO

VCCIO

AA21

AA22

V16

C

4

-

4

-

BDQ69

T

C

T

BDQ78

T

C

T

V17

C

VCCIO

Y18

BDQ69

T

BDQ78

T

Y17

C

GNDIO

Y19

4

-

BDQS69

BDQ69

T

C

T

4

-

BDQS78

BDQ78

T

C

T

Y20

W17

W18

C

T

C

T

Y21

Y22

C

VCCIO

U18

BDQ69

T

C

T

BDQ78

T

C

T

V18

BDQ69

BDQ78

T15

VREF2_4/BDQ69

VREF1_4/BDQ69

VREF2_4/BDQ78

VREF1_4/BDQ78

T16

C

GNDIO

W19

8

-

8

-

V19

CFG1

W20

CFG0

V20

PROGRAMN

CCLK

PROGRAMN

CCLK

W22

V22

INITN

V21

DONE

GNDIO

GNDIO8

4-64

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

8

-

Dual Function

Differential

Bank

8

-

Dual Function

Differential

R16

R17

PR58B

PR58A

PR57B

PR57A

VCCIO8

PR56B

PR56A

PR55B

GNDIO8

PR55A

PR54B

PR54A

PR53B

VCCIO8

PR53A

PR52B

PR52A

GNDIO3

VCCIO3

PR47B

PR47A

PR46B

PR46A

VCCIO3

PR45B

PR45A

PR44B

PR44A

RLM0_PLLCAP

PR42B

PR42A

GNDIO3

PR41B

PR41A

PR40B

PR40A

VCCIO3

GNDIO3

PR30B

PR30A

PR29B

PR29A

VCCIO3

PR28B

PR28A

PR27B

PR27A

WRITEN

CS1N

C

T

C

T

PR77B

PR77A

PR76B

PR76A

VCCIO

PR75B

PR75A

PR74B

GNDIO8

PR74A

PR73B

PR73A

PR72B

VCCIO

PR72A

PR71B

PR71A

GNDIO3

VCCIO

PR66B

PR66A

PR65B

PR65A

VCCIO

PR64B

PR64A

PR63B

PR63A

RLM0_PLLCAP

PR61B

PR61A

GNDIO3

PR60B

PR60A

PR59B

PR59A

VCCIO

GNDIO3

PR49B

PR49A

PR48B

PR48A

VCCIO

PR47B

PR47A

PR46B

PR46A

WRITEN

CS1N

C

T

C

T

U19

CSN

U20

D0/SPIFASTN

VCCIO

U22

D1

D2

D3

C

T

D1

D2

D3

C

T

U21

T20

C

GNDIO

T19

8

-

D4

D5

D6

D7

T

C

T

8

-

D4

D5

D6

D7

T

C

T

T17

T18

T21

C

VCCIO

T22

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

T

C

T

R18

R19

GNDIO

VCCIO

R22

3

-

3

-

RDQ48

C

RDQ67

C

R21

T

P18

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

P19

VCCIO

R20

RLM0_GPLLC_FB_A/RDQ48

RLM0_GPLLT_FB_A/RDQ48

C

T

RLM0_GPLLC_FB_A/RDQ67

RLM0_GPLLT_FB_A/RDQ67

C

T

P22

P21

RLM0_GPLLC_IN_A**/RDQ48 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ48 T (LVDS)*

RLM0_GPLLC_IN_A**/RDQ67 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ67 T (LVDS)*

N21

N17

N22

RLM0_GDLLC_FB_A/RDQ39

RLM0_GDLLT_FB_A/RDQ39

C

T

RLM0_GDLLC_FB_A/RDQ58

RLM0_GDLLT_FB_A/RDQ58

C

T

N20

GNDIO

M22

M21

N19

3

-

RLM0_GDLLC_IN_A**/RDQ39 C (LVDS)*

RLM0_GDLLT_IN_A**/RDQ39 T (LVDS)*

3

-

RLM0_GDLLC_IN_A**/RDQ58 C (LVDS)*

RLM0_GDLLT_IN_A**/RDQ58 T (LVDS)*

RDQ39

C

T

RDQ58

C

T

M19

VCCIO

GNDIO

L22

3

RDQ31

C

3

RDQ50

C

K22

T

J22

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

H22

VCCIO

M20

L21

VREF2_3/RDQ31

VREF1_3/RDQ31

PCLKC3_0/RDQ31

PCLKT3_0/RDQ31

C

VREF2_3/RDQ50

VREF1_3/RDQ50

PCLKC3_0/RDQ50

PCLKT3_0/RDQ50

C

T

K21

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

J21

4-65

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

-

Dual Function

Differential

Bank

2

-

Dual Function

Differential

M18

L17

PR25B

PR25A

GNDIO2

PR24B

PR24A

PR23B

PR23A

VCCIO2

PR22B

PR22A

PR21B

GNDIO2

PR21A

PR20B

PR20A

PR19B

VCCIO2

PR19A

PR18B

PR18A

-

PCLKC2_0/RDQ22

PCLKT2_0/RDQ22

C

T

PR44B

PR44A

GNDIO2

PR43B

PR43A

PR42B

PR42A

VCCIO

PR41B

PR41A

PR40B

GNDIO2

PR40A

PR39B

PR39A

PR38B

VCCIO

PR38A

PR37B

PR37A

GNDIO2

VCCIO

PR26B

PR26A

PR25B

PR25A

GNDIO2

VCCIO

PR19B

GNDIO2

PR19A

PR18B

PR18A

PR17B

VCCIO

PR17A

PR16B

PR16A

GNDIO2

PR15B

PR15A

PR14B

PR14A

VCCIO

PR13B

PR13A

PR12B

PCLKC2_0/RDQ41

PCLKT2_0/RDQ41

C

T

GNDIO

L19

2

-

RDQ22

C (LVDS)*

2

-

RDQ41

C (LVDS)*

L20

T (LVDS)*

L18

C

T

C

T

K17

VCCIO

K18

K19

G22

GNDIO

F22

RDQ22

RDQS22

RDQ22

C (LVDS)*

T (LVDS)*

C

RDQ41

RDQS41

RDQ41

C (LVDS)*

T (LVDS)*

C

2

-

RDQ22

T

2

-

RDQ41

T

J17

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

J18

K20

VCCIO

J19

RDQ22

T

RDQ41

T

H21

G21

-

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

-

2

-

H17

H16

H20

H18

-

NC

-

RUM0_SPLLC_FB_A/RDQ24

RUM0_SPLLT_FB_A/RDQ24

RUM0_SPLLC_IN_A/RDQ24

RUM0_SPLLT_IN_A/RDQ24

C

T

C

T

NC

-

NC

-

NC

-

2

-

F21

PR17B

GNDIO2

PR17A

PR16B

PR16A

PR15B

VCCIO2

PR15A

PR14B

PR14A

GNDIO2

PR13B

PR13A

PR12B

PR12A

VCCIO2

PR11B

PR11A

PR10B

2

-

RDQ14

C

RDQ16

C

GNDIO

E22

D22

E21

G20

VCCIO

F20

2

-

RDQ14

T

2

-

RDQ16

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

RDQ14

T

RDQ16

RDQS16

T

H19

G19

GNDIO

G17

F19

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS14

2

RDQ14

C

2

RDQ16

C

T

E20

D20

VCCIO

F18

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQ14

C

T

RDQ16

C

T

F16

C21

C (LVDS)*

4-66

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

-

Dual Function

Differential

Bank

2

-

Dual Function

Differential

C22

VCCIO

GNDIO

D19

PR10A

VCCIO2

GNDIO2

PR2B

RDQ14

T (LVDS)*

PR12A

VCCIO

GNDIO2

PR2B

RDQ16

T (LVDS)*

2

1

-

VREF2_2/RDQ6

VREF1_2/RDQ6

VREF2_1

C (LVDS)*

T (LVDS)*

C

2

1

-

VREF2_2

VREF1_2

VREF2_1

C (LVDS)*

T (LVDS)*

C

E19

PR2A

B21

PT73B

GNDIO1

PT73A

PT72B

PT72A

PT71B

VCCIO1

PT71A

PT70B

PT70A

PT69B

PT69A

PT68B

GNDIO1

PT68A

PT67B

VCCIO1

PT67A

PT66B

PT66A

PT65B

PT65A

GNDIO1

VCCIO1

PT55B

GNDIO1

PT55A

PT54B

PT54A

PT53B

VCCIO1

PT53A

PT52B

PT52A

PT51B

PT51A

GNDIO1

PT49B

VCCIO1

PT49A

PT48B

PT48A

PT82B

GNDIO1

PT82A

PT81B

PT81A

PT80B

VCCIO

PT80A

PT79B

PT79A

PT78B

PT78A

PT77B

GNDIO1

PT77A

PT76B

VCCIO

PT76A

PT75B

PT75A

PT74B

PT74A

GNDIO1

VCCIO

PT64B

GNDIO1

PT64A

PT63B

PT63A

PT62B

VCCIO

PT62A

PT61B

PT61A

PT60B

PT60A

GNDIO1

PT58B

VCCIO

PT58A

PT57B

PT57A

GNDIO

B22

1

-

VREF1_1

T

C

T

1

-

VREF1_1

T

C

T

C20

C19

D18

C

VCCIO

E18

T

C

T

C

T

B20

A19

D17

C

T

C

T

C18

A21

C

GNDIO

A20

1

-

T

1

-

T

A18

C

VCCIO

B18

T

C

T

C

T

C

T

C

T

G16

G15

D16

E16

GNDIO

VCCIO

C17

1

-

1

-

C

GNDIO

C16

1

-

T

C

T

1

-

T

C

T

B17

B16

A17

C

VCCIO

A16

T

C

T

C

T

C

T

C

T

C15

D15

E15

F15

GNDIO

B15

1

C

1

C

VCCIO

A15

T

C

T

C

T

B14

A14

4-67

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

1

-

Dual Function

Differential

Bank

1

-

Dual Function

Differential

D14

C13

GNDIO

E14

PT46B

PT46A

GNDIO1

PT45B

PT45A

PT44B

PT44A

VCCIO1

PT43B

PT43A

PT42B

PT42A

GNDIO1

PT40B

PT40A

VCCIO1

PT39B

PT39A

XRES

C

T

PT55B

PT55A

GNDIO1

PT54B

PT54A

PT53B

PT53A

VCCIO

PT52B

PT52A

PT51B

PT51A

GNDIO1

PT49B

PT49A

VCCIO

PT48B

PT48A

XRES

C

T

1

-

C

T

C

T

1

-

C

T

C

T

F14

A13

B13

VCCIO

E13

C

T

C

T

C

T

C

T

D13

E12

D12

GNDIO

A12

1

0

-

C

T

1

0

C

T

A11

VCCIO

B12

PCLKC1_0

PCLKT1_0

C

T

PCLKC1_0

PCLKT1_0

C

T

C12

F12

B10

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

VCCIO0

PT30B

PT30A

PT29B

PT29A

GNDIO0

PT27B

PT27A

PT26B

PT26A

VCCIO0

PT25B

PT25A

PCLKC0_0

PCLKT0_0

C

PT46B

GNDIO0

PT46A

PT45B

PT45A

PT44B

VCCIO

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

GNDIO0

PT41A

VCCIO

PT39B

PT39A

PT38B

PT38A

GNDIO0

PT36B

PT36A

PT35B

PT35A

VCCIO

PT34B

PT34A

PCLKC0_0

PCLKT0_0

C

GNDIO

B11

0

-

T

C

T

C

T

A10

A9

C11

VCCIO

C10

E11

C

T

C

T

C

T

F11

A8

C

T

C

T

A7

B8

C

GNDIO

B9

0

-

T

VCCIO

B7

C

T

C

T

C

T

C

T

A6

C8

D8

GNDIO

D10

E10

0

C

T

C

T

C

T

C

T

C7

C6

VCCIO

B6

C

T

C

T

B5

4-68

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

0

-

Dual Function

Differential

Bank

0

-

Dual Function

Differential

F10

D9

PT24B

PT24A

GNDIO0

PT23B

PT23A

PT22B

PT22A

VCCIO0

PT21B

PT21A

PT20B

PT20A

GNDIO0

VCCIO0

PT10B

PT10A

GNDIO0

PT9B

C

T

PT33B

PT33A

GNDIO0

PT32B

PT32A

PT31B

PT31A

VCCIO

PT30B

PT30A

PT29B

PT29A

GNDIO0

VCCIO

PT10B

PT10A

GNDIO0

PT9B

PT9A

PT8B

VCCIO

PT8A

PT7B

PT7A

PT6B

PT6A

GNDIO0

PT5B

PT5A

PT4B

VCCIO

PT4A

PT3B

PT3A

PT2B

PT2A

VCC

C

T

GNDIO

F9

0

-

C

T

C

T

C

T

C

T

E9

A5

A4

VCCIO

A3

C

T

C

T

C

T

C

T

A2

G8

E8

GNDIO

VCCIO

C3

0

-

C

T

C

T

B3

GNDIO

F8

0

-

C

T

C

T

D7

PT9A

E7

PT8B

C

VCCIO

F7

VCCIO0

PT8A

T

C

T

C

T

C

T

C

T

D5

PT7B

D6

PT7A

D4

PT6B

C4

PT6A

GNDIO

B2

GNDIO0

PT5B

0

-

C

T

C

T

B1

PT5A

J7

PT4B

C

VCCIO

H7

VCCIO0

PT4A

T

C

T

C

T

C

T

C

T

D3

PT3B

C2

PT3A

D1

PT2B

VREF2_0

VREF1_0

VREF2_0

VREF1_0

C1

PT2A

J10

J11

J12

J13

K14

K9

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

L14

L9

VCC

-

VCC

-

VCC

-

VCC

-

M14

M9

VCC

-

VCC

-

VCC

-

VCC

-

N14

VCC

-

VCC

-

4-69

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

N9

P10

P11

P12

P13

G5

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

K5

-

R5

-

V7

-

V11

V8

-

V13

V15

M17

P17

E17

G18

D11

F13

C5

-

E6

-

G10

G9

0

1

2

3

4

5

6

H8

H9

G11

G12

G13

G14

H14

H15

J15

K16

L16

M16

N16

P16

R14

T12

T13

T14

R9

T10

T11

T9

N7

P7

4-70

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

P8

R8

VCCIO6

VCCIO7

VCCIO8

GND

6

7

8

-

VCCIO6

VCCIO7

VCCIO8

GND

6

7

8

-

J8

K7

L7

M7

P15

R15

A22

AA19

AA4

AB1

AB22

B19

B4

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

C14

C9

GND

-

GND

-

GND

-

GND

-

D2

GND

-

GND

-

D21

F17

F6

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

H10

H11

H12

H13

J14

J20

J3

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

J9

GND

-

GND

-

K10

K11

K12

K13

K15

K8

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

L10

L11

L12

L13

L15

L8

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

M10

M11

M12

M13

M15

M8

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-71

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA

LFE2-35E/SE

LFE2-50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

N10

N11

N12

N13

N15

N8

GND

VCCPLL

NC

-

GND

-

GND

P14

P20

P3

GND

P9

GND

R10

R11

R12

R13

U17

U6

GND

W2

W21

Y14

Y9

GND

A1

GND

N18

K6

VCCPLL

N6

VCCPLL

NC

J16

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-72

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

VREF2_7

Differential

T (LVDS)*

C (LVDS)*

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

D2

D1

PL2A

PL2B

GNDIO7

PL3A

PL3B

VCCIO7

NC

7

-

PL2A

PL2B

VREF2_7/LDQ6

VREF1_7/LDQ6

VREF1_7

GND

F6

GNDIO7

PL3A

7

-

T

7

-

LDQ6

T

F5

C

PL3B

C

VCCIO

E4

VCCIO7

PL4A

LDQ6

T (LVDS)*

E3

NC

-

PL4B

C (LVDS)*

E2

NC

-

PL5A

T

E1

NC

-

PL5B

C

GND

H6

GNDIO7

NC

-

GNDIO7

PL6A

-

7

-

LDQS6

LDQ6

T (LVDS)*

C (LVDS)*

T

H5

NC

-

PL6B

F2

NC

-

PL7A

VCCIO

F1

VCCIO7

NC

7

-

VCCIO7

PL7B

LDQ6

C

H8

NC

-

PL8A

T (LVDS)*

C (LVDS)*

T

J9

NC

-

PL8B

G4

NC

-

PL9A

GND

G3

GNDIO7

NC

-

GNDIO7

PL9B

-

7

-

LDQ6

LDQ14

C

H7

PL4A

PL4B

PL5A

PL5B

PL6A

VCCIO7

PL6B

PL7A

PL7B

PL8A

GNDIO7

PL8B

PL9A

PL9B

VCCIO7

PL10A

PL10B

PL11A

PL11B

GNDIO7

VCCIO7

NC

7

-

LDQ8

T (LVDS)*

C (LVDS)*

T

PL10A

PL10B

PL11A

PL11B

PL12A

VCCIO7

PL12B

PL13A

PL13B

PL14A

GNDIO7

PL14B

PL15A

PL15B

VCCIO7

PL16A

PL16B

PL17A

PL17B

GNDIO7

VCCIO7

NC

T (LVDS)*

C (LVDS)*

T

J8

G2

G1

C

H3

T (LVDS)*

VCCIO

H4

LDQ8

LDQS8

C (LVDS)*

LDQ14

LDQS14

C (LVDS)*

J5

T

C

T

C

J4

J3

T (LVDS)*

GND

K4

7

-

LDQ8

C (LVDS)*

7

-

LDQ14

C (LVDS)*

H1

T

H2

C

VCCIO

K6

LDQ8

T (LVDS)*

LDQ14

T (LVDS)*

K7

C (LVDS)*

J1

T

J2

C

GND

VCCIO

K3

7

-

7

-

K2

NC

-

NC

-

GND

K1

GNDIO7

NC

-

GNDIO7

NC

-

L2

NC

-

NC

-

4-73

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

-

Dual Function

Differential

L1

VCCIO

M2

NC

VCCIO7

NC

-

7

-

NC

VCCIO7

NC

7

-

M1

NC

-

NC

-

N2

NC

-

NC

-

GND

M8

GNDIO7

VCC

-

GNDIO7

NC

-

VCCIO

GND

N1

VCCIO7

GNDIO7

PL12A

PL13A

PL13B

VCCIO7

PL14A

PL14B

PL15A

PL15B

GNDIO7

PL16A

PL16B

PL17A

VCCIO7

PL17B

PL18A

PL18B

PL19A

GNDIO7

PL19B

PL21A

PL21B

PL22A

PL22B

PL23A

VCCIO6

PL23B

PL24A

PL24B

NC

7

-

VCCIO7

GNDIO7

PL18A

PL19A

PL19B

VCCIO7

PL20A

PL20B

PL21A

PL21B

GNDIO7

PL22A

PL22B

PL23A

VCCIO7

PL23B

PL24A

PL24B

PL25A

GNDIO7

PL25B

PL27A

PL27B

PL28A

PL28B

PL29A

VCCIO6

PL29B

PL30A

PL30B

PL31A

GNDIO6

PL31B

PL32A

PL32B

VCCIO6

PL33A

PL33B

PL34A

PL34B

7

-

7

-

LDQ16

7

-

LDQ22

L8

T

K8

C

VCCIO

L6

LDQ16

T (LVDS)*

LDQ22

T (LVDS)*

K5

C (LVDS)*

L7

T

L5

C

GND

P1

7

-

LDQS16

LDQ16

T (LVDS)*

C (LVDS)*

T

7

-

LDQS22

LDQ22

T (LVDS)*

C (LVDS)*

T

P2

M6

VCCIO

N8

LDQ16

C

LDQ22

C

R1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

R2

LDQ16

LDQ22

M7

PCLKT7_0/LDQ16

PCLKT7_0/LDQ22

GND

N9

7

6

-

PCLKC7_0/LDQ16

PCLKT6_0/LDQ25

PCLKC6_0/LDQ25

VREF2_6/LDQ25

VREF1_6/LDQ25

LDQ25

C

7

6

-

PCLKC7_0/LDQ22

PCLKT6_0/LDQ31

PCLKC6_0/LDQ31

VREF2_6/LDQ31

VREF1_6/LDQ31

LDQ31

C

M4

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

M5

N7

P9

C

N3

T (LVDS)*

VCCIO

N4

LDQ25

C (LVDS)*

LDQ31

LDQS31

C (LVDS)*

N5

T

C

P7

C

T1

T (LVDS)*

GND

T2

GNDIO6

NC

-

6

LDQ31

C (LVDS)*

P8

NC

-

T

P6

NC

-

C

VCCIO

P5

VCCIO6

NC

6

-

LDQ31

T (LVDS)*

P4

NC

-

C (LVDS)*

U1

NC

-

T

V1

NC

-

C

4-74

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

-

Dual Function

Differential

GND

P3

GNDIO6

NC

-

GNDIO6

NC

-

R3

NC

-

NC

-

R4

NC

-

NC

-

U2

NC

-

NC

-

VCCIO

V2

VCCIO6

NC

6

-

VCCIO6

NC

6

-

W2

T6

NC

-

NC

-

NC

-

PL38A

PL38B

GNDIO6

PL39A

PL39B

PL40A

VCCIO6

PL40B

PL41A

PL41B

PL42A

GNDIO6

PL42B

VCCPLL

LLM0_PLLCAP

PL44A

PL44B

PL45A

PL45B

PL46A

VCCIO6

PL46B

PL47A

PL47B

PL48A

GNDIO6

PL48B

PL49A

PL49B

VCCIO6

PL50A

PL50B

PL51A

PL51B

GNDIO6

PL52A

PL52B

PL53A

PL53B

6

-

LDQ39

T

R5

NC

-

C

GND

R6

GNDIO6

PL25A

PL25B

PL26A

VCCIO6

PL26B

PL27A

PL27B

PL28A

GNDIO6

PL28B

VCC

-

6

-

LDQS25***

LDQ25

T (LVDS)*

C (LVDS)*

T

6

-

LDQS39***

LDQ39

T (LVDS)*

C (LVDS)*

T

R7

W1

VCCIO

Y2

LDQ25

LDQ39

LDQ25

C

LDQ39

C

Y1

LLM0_GDLLT_IN_A**/LDQ25

T (LVDS)*

LLM0_GDLLT_IN_A**/LDQ39 T (LVDS)*

LLM0_GDLLC_IN_A**/LDQ39 C (LVDS)*

AA2

T5

LLM0_GDLLC_IN_A**/LDQ25 C (LVDS)*

LLM0_GDLLT_FB_A/LDQ25

LLM0_GDLLC_FB_A/LDQ25

T

LLM0_GDLLT_FB_A/LDQ39

T

GND

T7

6

-

C

6

-

LLM0_GDLLC_FB_A/LDQ39

C

R8

T8

LLM0_PLLCAP

PL30A

PL30B

PL31A

PL31B

PL32A

VCCIO6

PL32B

PL33A

PL33B

PL34A

GNDIO6

PL34B

PL35A

PL35B

VCCIO6

PL36A

PL36B

PL37A

PL37B

GNDIO6

PL38A

PL38B

PL39A

PL39B

U3

LLM0_GPLLT_IN_A**/LDQ34

T (LVDS)*

LLM0_GPLLT_IN_A**/LDQ48

T (LVDS)*

U4

LLM0_GPLLC_IN_A**/LDQ34 C (LVDS)*

LLM0_GPLLC_IN_A**/LDQ48 C (LVDS)*

V3

LLM0_GPLLT_FB_A/LDQ34

LLM0_GPLLC_FB_A/LDQ34

LDQ34

T

C

LLM0_GPLLT_FB_A/LDQ48

LLM0_GPLLC_FB_A/LDQ48

LDQ48

T

C

U5

V4

T (LVDS)*

VCCIO

V5

LDQ34

LDQS34

C (LVDS)*

LDQ48

LDQS48

C (LVDS)*

Y3

T

C

T

C

Y4

W3

GND

W4

AA1

AB1

VCCIO

U8

T (LVDS)*

6

-

LDQ34

C (LVDS)*

6

-

LDQ48

C (LVDS)*

T

C

LDQ34

T (LVDS)*

LDQ48

T (LVDS)*

U7

C (LVDS)*

V8

T

U6

C

GND

W6

W5

AC1

AD1

6

LDQ42

T (LVDS)*

6

LDQ56

T (LVDS)*

C (LVDS)*

T

C

4-75

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

6

-

Dual Function

Differential

VCCIO

Y6

VCCIO6

PL40A

PL40B

PL41A

PL41B

GNDIO6

PL42A

PL42B

PL43A

VCCIO6

PL43B

PL44A

PL44B

PL45A

GNDIO6

PL45B

TCK

6

-

VCCIO6

PL54A

PL54B

PL55A

PL55B

GNDIO6

PL56A

PL56B

PL57A

VCCIO6

PL57B

PL58A

PL58B

PL59A

GNDIO6

PL59B

TCK

LDQ42

T (LVDS)*

LDQ56

T (LVDS)*

Y5

C (LVDS)*

AE2

AD2

GND

AB3

AB2

W7

T

C

6

-

LDQS42

LDQ42

T (LVDS)*

C (LVDS)*

T

6

-

LDQS56

LDQ56

T (LVDS)*

C (LVDS)*

T

VCCIO

W8

LDQ42

C

LDQ56

C

Y7

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

Y8

AC2

GND

AD3

AC3

AA8

AB4

AA5

AB5

AE3

AF3

AC4

AD4

AE4

AF4

VCCIO

V9

6

-

LDQ42

C

6

-

LDQ56

C

TDI

-

TDI

-

TMS

-

TMS

-

TDO

-

TDO

-

VCCJ

-

VCCJ

-

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

PB2B

PB3A

PB3B

BDQ6

C

T

PB3B

BDQ6

C

T

PB4A

BDQ6

PB4A

BDQ6

PB4B

BDQ6

C

PB4B

BDQ6

C

VCCIO5

PB5A

VCCIO5

PB5A

BDQ6

T

BDQ6

T

W9

PB5B

C

PB5B

C

GND

AA6

AB6

AC5

AD5

AA7

AB7

VCCIO

AE5

AF5

AC7

AD7

VCCIO

GND

W10

Y10

GNDIO5

PB6A

GNDIO5

PB6A

5

-

BDQS6

BDQ6

T

C

T

5

-

BDQS6

BDQ6

T

C

T

PB6B

PB7A

PB7B

C

T

PB7B

C

T

PB8A

PB8B

C

PB8B

C

VCCIO5

PB9A

VCCIO5

PB9A

BDQ6

T

C

T

BDQ6

T

C

T

PB9B

PB10A

PB10B

VCCIO5

GNDIO5

PB11A

PB11B

PB12A

PB10A

PB10B

VCCIO5

GNDIO5

PB11A

PB11B

PB12A

C

5

BDQ15

T

C

T

5

BDQ15

T

C

T

W11

4-76

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

BDQ15

Differential

Bank

5

-

Dual Function

Differential

AA10

AC8

PB12B

PB13A

PB13B

VCCIO5

PB14A

PB14B

GNDIO5

PB15A

PB15B

PB16A

PB16B

PB17A

PB17B

VCCIO5

PB18A

PB18B

PB19A

PB19B

GNDIO5

PB20A

PB20B

PB21A

PB21B

PB22A

VCCIO5

PB22B

PB23A

PB23B

PB24A

GNDIO5

PB24B

PB25A

PB25B

PB26A

VCCIO5

PB26B

PB27A

PB27B

PB28A

GNDIO5

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

5

-

C

T

PB12B

PB13A

PB13B

VCCIO5

PB14A

PB14B

GNDIO5

PB15A

PB15B

PB16A

PB16B

PB17A

PB17B

VCCIO5

PB18A

PB18B

PB19A

PB19B

GNDIO5

PB20A

PB20B

PB21A

PB21B

PB22A

VCCIO5

PB22B

PB23A

PB23B

PB24A

GNDIO5

PB24B

PB25A

PB25B

PB26A

VCCIO5

PB26B

PB27A

PB27B

PB28A

GNDIO5

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

BDQ15

C

T

BDQ15

AD8

BDQ15

C

VCCIO

AB8

BDQ15

T

BDQ15

T

AB10

GND

AE6

C

5

-

BDQS15

BDQ15

T

C

T

5

-

BDQS15

BDQ15

T

C

T

AF6

AA11

AC9

C

T

C

T

AB9

AD9

C

VCCIO

Y11

BDQ15

T

C

T

BDQ15

T

C

T

AB11

AE7

AF7

C

GND

AC10

AD10

AA12

W12

5

-

BDQ24

T

C

T

C

T

5

-

BDQ24

T

C

T

C

T

AB12

VCCIO

Y12

BDQ24

BDQS24

C

T

C

T

BDQ24

BDQS24

C

T

C

T

AD12

AC12

AC13

GND

AA13

AD13

AC14

AE8

5

-

BDQ24

C

T

C

T

5

-

BDQ24

C

T

C

T

VCCIO

AF8

BDQ24

C

T

C

T

BDQ24

C

T

C

T

AB15

Y13

AE9

GND

AF9

5

BDQ24

BDQ33

C

T

5

BDQ24

BDQ33

C

T

W13

AA14

AE10

AF10

W14

C

T

C

T

C

T

C

T

AB13

C

4-77

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

5

-

Dual Function

Differential

VCCIO

Y14

VCCIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

PB40A

VCCIO4

PB40B

PB41A

PB41B

PB42A

GNDIO4

PB42B

PB43A

PB43B

PB44A

VCCIO4

PB44B

PB45A

PB45B

PB46A

GNDIO4

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

5

-

VCCIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

PB40A

VCCIO4

PB40B

PB41A

PB41B

PB42A

GNDIO4

PB42B

PB43A

PB43B

PB44A

VCCIO4

PB44B

PB45A

PB45B

PB46A

GNDIO4

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

BDQ33

T

BDQ33

T

AB14

GND

C

AE11

AF11

AD14

AA15

AE12

AF12

VCCIO

GND

5

-

BDQS33

BDQ33

T

C

T

5

-

BDQS33

BDQ33

T

C

T

BDQ33

C

T

BDQ33

C

T

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

C

AD15

VCCIO

AC15

AE13

AF13

AB17

GND

4

-

PCLKT4_0/BDQ42

T

4

-

PCLKT4_0/BDQ42

T

PCLKC4_0/BDQ42

BDQ42

C

T

C

T

PCLKC4_0/BDQ42

BDQ42

C

T

C

T

BDQ42

BDQS42

Y15

4

-

BDQ42

C

T

C

T

4

-

BDQ42

C

T

C

T

AE14

AF14

AA16

VCCIO

W15

BDQ42

C

T

C

T

BDQ42

C

T

C

T

AC17

AB16

AE15

GND

AF15

AE16

AF16

Y16

4

-

BDQ42

BDQ51

C

T

4

-

BDQ42

BDQ51

C

T

C

T

C

T

AB18

AD17

AD18

VCCIO

AC18

AD19

GND

C

T

C

T

C

BDQ51

T

BDQ51

T

C

AC19

AE17

AB19

AE19

AF17

AE18

VCCIO

4

BDQS51

BDQ51

T

C

T

4

BDQS51

BDQ51

T

C

T

C

T

C

T

C

4-78

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

BDQ51

Differential

Bank

4

-

Dual Function

Differential

W16

AA17

AF18

AF19

GND

AA19

W17

PB54A

PB54B

PB55A

PB55B

GNDIO4

NC

4

-

T

C

T

PB54A

PB54B

PB55A

PB55B

GNDIO4

PB56A

PB56B

PB57A

PB57B

NC

BDQ51

T

C

T

BDQ51

C

-

4

-

BDQ60

T

C

T

NC

-

Y19

NC

-

Y17

NC

-

C

AF20

VCCIO

AE20

AA20

W18

NC

-

VCCIO4

NC

4

-

VCCIO4

NC

4

-

NC

-

NC

-

NC

-

NC

-

AD20

GND

AE21

AF21

AF22

VCCIO

GND

AE22

AD22

AF23

AE23

AD23

AC23

VCCIO

AB20

AC20

GND

AB21

AC22

W19

NC

-

NC

-

GNDIO4

NC

-

GNDIO4

NC

-

NC

-

NC

-

NC

-

NC

-

VCCIO4

GNDIO4

PB56A

PB56B

PB57A

PB57B

PB58A

PB58B

VCCIO4

PB59A

PB59B

GNDIO4

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO4

PB63A

PB63B

PB64A

PB64B

GNDIO4

CFG2

CFG1

CFG0

PROGRAMN

4

-

VCCIO4

GNDIO4

PB65A

PB65B

PB66A

PB66B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

PB72A

PB72B

PB73A

PB73B

GNDIO4

CFG2

4

-

4

-

BDQ60

T

C

T

4

-

BDQ69

T

C

T

C

T

C

T

C

BDQ60

T

BDQ69

T

C

4

-

BDQS60

BDQ60

T

C

T

4

-

BDQS69

BDQ69

T

C

T

AA21

AF24

AE24

VCCIO

Y20

C

T

C

T

C

BDQ60

T

C

T

BDQ69

T

C

T

AB22

Y21

BDQ60

BDQ69

VREF2_4/BDQ60

VREF1_4/BDQ60

VREF2_4/BDQ69

VREF1_4/BDQ69

AB23

GND

AD24

W20

C

8

CFG1

AC24

V19

CFG0

PROGRAMN

4-79

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

8

-

Dual Function

Differential

AA22

AB24

AD25

GND

W21

Y22

CCLK

INITN

8

-

CCLK

INITN

DONE

GNDIO8

PR44B

PR44A

PR43B

PR43A

VCCIO8

PR42B

PR42A

PR41B

GNDIO8

PR41A

PR40B

PR40A

PR39B

VCCIO8

PR39A

PR38B

PR38A

PR37B

GNDIO3

PR37A

PR36B

PR36A

PR35B

VCCIO3

PR35A

PR34B

PR34A

GNDIO3

PR33B

PR33A

PR32B

PR32A

VCCIO3

PR31B

PR31A

PR30B

PR30A

RLM0_PLLCAP

VCC

GNDIO8

PR58B

PR58A

PR57B

PR57A

VCCIO8

PR56B

PR56A

PR55B

GNDIO8

PR55A

PR54B

PR54A

PR53B

VCCIO8

PR53A

PR52B

PR52A

PR51B

GNDIO3

PR51A

PR50B

PR50A

PR49B

VCCIO3

PR49A

PR48B

PR48A

GNDIO3

PR47B

PR47A

PR46B

PR46A

VCCIO3

PR45B

PR45A

PR44B

PR44A

RLM0_PLLCAP

VCCPLL

PR42B

PR42A

GNDIO3

PR41B

8

-

WRITEN

CS1N

C

T

C

T

8

-

WRITEN

CS1N

C

T

C

T

AC25

AB25

VCCIO

AD26

AC26

Y23

CSN

D0/SPIFASTN

D1

D2

D3

C

T

D1

D2

D3

C

T

C

GND

W22

AA25

AB26

W23

VCCIO

V22

8

3

-

D4

D5

D6

D7

T

C

T

8

3

-

D4

D5

D6

D7

T

C

T

C

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

RDQ34

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

RDQ48

T

C

T

Y24

Y25

W24

GND

V23

C

3

-

RDQ34

T

3

-

RDQ48

T

AA26

Y26

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

U21

VCCIO

U19

RDQ34

T

RDQ48

T

W25

W26

GND

V24

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS34

RDQS48

3

-

RDQ34

C

3

-

RDQ48

C

V25

T

V26

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

U26

VCCIO

U22

RLM0_GPLLC_FB_A/RDQ34

RLM0_GPLLT_FB_A/RDQ34

C

T

RLM0_GPLLC_FB_A/RDQ48

RLM0_GPLLT_FB_A/RDQ48

C

T

U23

U24

RLM0_GPLLC_IN_A**/RDQ34 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ34 T (LVDS)*

RLM0_GPLLC_IN_A**/RDQ48 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ48 T (LVDS)*

U25

R20

P18

T19

PR28B

PR28A

GNDIO3

PR27B

RLM0_GDLLC_FB_A/RDQ25

RLM0_GDLLT_FB_A/RDQ25

C

T

RLM0_GDLLC_FB_A/RDQ39

RLM0_GDLLT_FB_A/RDQ39

C

T

U20

GND

T25

3

RLM0_GDLLC_IN_A**/RDQ25 C (LVDS)*

3

RLM0_GDLLC_IN_A**/RDQ39 C (LVDS)*

4-80

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

3

-

Dual Function

Differential

T26

T20

PR27A

PR26B

PR26A

VCCIO3

PR25B

PR25A

NC

3

-

RLM0_GDLLT_IN_A**/RDQ25 T (LVDS)*

PR41A

PR40B

PR40A

VCCIO3

PR39B

PR39A

PR38B

GNDIO3

PR38A

NC

RLM0_GDLLT_IN_A**/RDQ39 T (LVDS)*

RDQ25

C

T

RDQ39

C

T

T22

VCCIO

R26

R25

R22

GND

T21

RDQ25

C (LVDS)*

T (LVDS)*

RDQ39

RDQS39***

RDQ39

C (LVDS)*

T (LVDS)*

C

RDQS25***

GNDIO3

NC

-

3

-

RDQ39

T

P26

NC

-

P25

NC

-

NC

-

R24

VCCIO

R23

P20

NC

-

NC

-

VCCIO3

NC

3

-

VCCIO3

NC

3

-

NC

-

NC

-

R19

P21

NC

-

NC

-

NC

-

PR34B

GNDIO3

PR34A

PR33B

PR33A

PR32B

VCCIO3

PR32A

PR31B

PR31A

GNDIO3

PR30B

PR30A

PR29B

PR29A

VCCIO3

PR28B

PR28A

PR27B

PR27A

PR25B

PR25A

GNDIO2

PR24B

PR24A

PR23B

PR23A

VCCIO2

PR22B

PR22A

PR21B

3

-

RDQ31

C

GND

P19

GNDIO3

NC

-

3

-

RDQ31

T

P23

NC

-

C (LVDS)*

T (LVDS)*

C

P22

NC

-

N22

VCCIO

R21

N26

N25

GND

N19

N20

M26

M25

VCCIO

N18

N21

L26

NC

-

VCCIO3

NC

3

-

RDQ31

T

NC

-

C (LVDS)*

T (LVDS)*

NC

-

RDQS31

GNDIO3

PR24B

PR24A

PR23B

PR23A

VCCIO3

PR22B

PR22A

PR21B

PR21A

PR19B

PR19A

GNDIO2

PR18B

PR18A

PR17B

PR17A

VCCIO2

PR16B

PR16A

PR15B

-

3

2

-

RDQ25

C

3

2

-

RDQ31

C

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

VREF2_3/RDQ25

VREF1_3/RDQ25

PCLKC3_0/RDQ25

PCLKT3_0/RDQ25

PCLKC2_0/RDQ16

PCLKT2_0/RDQ16

C

VREF2_3/RDQ31

VREF1_3/RDQ31

PCLKC3_0/RDQ31

PCLKT3_0/RDQ31

PCLKC2_0/RDQ22

PCLKT2_0/RDQ22

C

T

C (LVDS)*

L25

T (LVDS)*

N24

M23

GND

L21

C

T

C

T

2

RDQ16

C (LVDS)*

2

RDQ22

C (LVDS)*

K22

T (LVDS)*

M24

N23

VCCIO

K26

C

T

C

T

RDQ16

RDQS16

RDQ16

C (LVDS)*

T (LVDS)*

C

RDQ22

RDQS22

RDQ22

C (LVDS)*

T (LVDS)*

C

K25

M20

4-81

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

-

Dual Function

Differential

GND

M19

L22

GNDIO2

PR15A

PR14B

PR14A

PR13B

VCCIO2

PR13A

PR12B

PR12A

GNDIO2

VCCIO2

VCC

-

2

-

GNDIO2

PR21A

PR20B

PR20A

PR19B

VCCIO2

PR19A

PR18B

PR18A

GNDIO2

VCCIO2

NC

RDQ16

T

2

-

RDQ22

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

M22

K21

VCCIO

M21

K24

RDQ16

T

RDQ22

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

J24

GND

VCCIO

L20

2

-

2

-

GND

J26

GNDIO2

NC

-

GNDIO2

NC

-

J25

NC

-

NC

-

J23

NC

-

NC

-

K23

NC

-

NC

-

VCCIO

H26

VCCIO2

NC

2

-

VCCIO2

NC

2

-

H25

NC

-

NC

-

H24

NC

-

NC

-

GND

H23

GNDIO2

NC

-

GNDIO2

NC

-

VCCIO

G26

GND

G25

F26

VCCIO2

PR11B

GNDIO2

PR11A

PR10B

PR10A

PR9B

VCCIO2

PR9A

PR8B

PR8A

GNDIO2

PR7B

PR7A

PR6B

PR6A

VCCIO2

PR5B

PR5A

PR4B

PR4A

NC

2

-

VCCIO2

PR17B

GNDIO2

PR17A

PR16B

PR16A

PR15B

VCCIO2

PR15A

PR14B

PR14A

GNDIO2

PR13B

PR13A

PR12B

PR12A

VCCIO2

PR11B

PR11A

PR10B

PR10A

PR9B

2

-

RDQ8

C

RDQ14

C

2

-

RDQ8

T

2

-

RDQ14

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

F25

K20

VCCIO

L19

RDQ8

T

RDQ14

RDQS14

T

E26

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

E25

RDQS8

GND

J22

2

-

RDQ8

C

2

-

RDQ14

C

H22

T

G24

G23

VCCIO

K19

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQ8

C

RDQ14

RDQ6

C

J19

T

D26

C (LVDS)*

T (LVDS)*

C (LVDS)*

C26

T (LVDS)*

F22

C

T

E24

NC

-

PR9A

RDQ6

GND

GNDIO2

-

GNDIO2

4-82

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

2

-

Dual Function

Differential

C (LVDS)*

T (LVDS)*

C

D25

C25

D24

B25

NC

-

PR8B

PR8A

RDQ6

NC

-

PR7B

NC

-

PR7A

T

VCCIO

H21

G22

B24

VCCIO2

NC

2

-

VCCIO2

PR6B

RDQ6

RDQS6

RDQ6

C (LVDS)*

T (LVDS)*

C

NC

-

PR6A

NC

-

PR5B

GND

C24

D23

C23

G21

VCCIO

H20

GND

E22

GNDIO2

NC

-

GNDIO2

PR5A

-

2

-

RDQ6

T

NC

-

PR4B

C (LVDS)*

T (LVDS)*

C

NC

-

PR4A

PR3B

VCCIO2

PR3A

GNDIO2

PR2B

PR2A

PT64B

GNDIO1

PT64A

PT63B

PT63A

PT62B

VCCIO1

PT62A

PT61B

PT61A

PT60B

PT60A

PT59B

GNDIO1

PT59A

PT58B

VCCIO1

PT58A

PT57B

PT57A

PT56B

PT56A

GNDIO1

NC

2

-

C

T

PR3B

VCCIO2

PR3A

RDQ6

T

GNDIO2

PR2B

2

1

-

VREF2_2

VREF1_2

VREF2_1

C (LVDS)*

T (LVDS)*

C

2

1

-

VREF2_2/RDQ6

VREF1_2/RDQ6

VREF2_1

C (LVDS)*

T (LVDS)*

C

F21

PR2A

E23

PT73B

GNDIO1

PT73A

PT72B

PT72A

PT71B

VCCIO1

PT71A

PT70B

PT70A

PT69B

PT69A

PT68B

GNDIO1

PT68A

PT67B

VCCIO1

PT67A

PT66B

PT66A

PT65B

PT65A

GNDIO1

NC

GND

D22

G20

J18

1

-

VREF1_1

T

C

T

1

-

VREF1_1

T

C

T

F20

C

VCCIO

H19

A24

T

C

T

C

T

A23

E21

C

T

C

T

F19

C22

GND

E20

C

1

-

T

1

-

T

B22

C

VCCIO

B23

T

C

T

C

T

C

T

C

T

C20

D20

A22

A21

GND

E19

-

C19

VCCIO

B21

NC

-

NC

-

VCCIO1

NC

1

-

VCCIO1

NC

1

-

B20

NC

-

NC

-

D19

NC

-

NC

-

4-83

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

-

Dual Function

Differential

B19

GND

G17

E18

NC

-

NC

GNDIO1

NC

-

GNDIO1

NC

-

NC

-

NC

-

G19

F17

NC

-

NC

-

NC

-

NC

-

VCCIO

A20

VCCIO1

NC

1

-

VCCIO1

NC

1

-

A19

NC

-

NC

-

E17

NC

-

NC

-

D18

B18

NC

-

NC

-

PT55B

GNDIO1

PT55A

PT54B

PT54A

PT53B

VCCIO1

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

GNDIO1

PT50A

PT49B

VCCIO1

PT49A

PT48B

PT48A

PT47B

PT47A

PT46B

PT46A

GNDIO1

PT45B

PT45A

PT44B

PT44A

VCCIO1

PT43B

PT43A

PT42B

PT42A

GNDIO1

PT41B

1

-

C

PT55B

GNDIO1

PT55A

PT54B

PT54A

PT53B

VCCIO1

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

GNDIO1

PT50A

PT49B

VCCIO1

PT49A

PT48B

PT48A

PT47B

PT47A

PT46B

PT46A

GNDIO1

PT45B

PT45A

PT44B

PT44A

VCCIO1

PT43B

PT43A

PT42B

PT42A

GNDIO1

PT41B

1

-

C

GND

A18

1

-

T

C

T

1

-

T

C

T

E16

G16

F16

C

VCCIO

H18

A17

T

C

T

C

T

B17

C18

B16

C

T

C

T

C17

GND

D17

E15

C

1

-

T

1

-

T

C

VCCIO

G15

A16

T

C

T

C

T

C

T

C

T

C

T

C

T

B15

D15

F15

A14

B14

GND

C15

A15

1

-

C

T

C

T

1

-

C

T

C

T

A13

B13

VCCIO

H17

H15

D13

C14

GND

G14

C

T

C

T

C

T

C

T

1

C

1

C

4-84

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

1

0

-

Dual Function

Differential

E14

A12

B12

VCCIO

F14

D14

H16

H14

GND

H13

A11

B11

C13

VCCIO

E13

D12

F13

A10

B10

C12

GND

C10

G13

VCCIO

H12

A9

PT41A

PT40B

PT40A

VCCIO1

PT39B

PT39A

XRES

1

0

-

T

C

T

PT41A

PT40B

PT40A

VCCIO1

PT39B

PT39A

XRES

T

C

T

PCLKC1_0

PCLKT1_0

C

T

PCLKC1_0

PCLKT1_0

C

T

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

PT31B

VCCIO0

PT31A

PT30B

PT30A

PT29B

PT29A

PT28B

PT28A

GNDIO0

PT27B

PT27A

PT26B

PT26A

VCCIO0

PT25B

PT25A

PT24B

PT24A

GNDIO0

PT23B

PT23A

PT22B

PT22A

VCCIO0

PCLKC0_0

PCLKT0_0

C

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

PT31B

VCCIO0

PT31A

PT30B

PT30A

PT29B

PT29A

PT28B

PT28A

GNDIO0

PT27B

PT27A

PT26B

PT26A

VCCIO0

PT25B

PT25A

PT24B

PT24A

GNDIO0

PT23B

PT23A

PT22B

PT22A

VCCIO0

PCLKC0_0

PCLKT0_0

C

0

-

T

C

T

0

-

T

C

T

C

T

C

T

C

T

C

T

C

T

C

0

-

T

0

-

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

B9

E12

G12

A8

B8

GND

E11

C9

0

-

C

T

C

T

0

-

C

T

C

T

A7

B7

VCCIO

F12

D10

H11

G11

GND

A6

C

T

C

T

C

T

C

T

0

C

T

C

T

0

C

T

C

T

B6

D8

C8

VCCIO

4-85

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

0

-

Dual Function

Differential

F11

E10

E9

PT21B

PT21A

PT20B

PT20A

PT19B

GNDIO0

PT19A

PT18B

PT18A

PT17B

VCCIO0

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

GNDIO0

PT14A

PT13B

VCCIO0

GNDIO0

VCCIO0

GNDIO0

VCCIO0

PT10B

GNDIO0

PT10A

PT9B

0

-

C

T

PT21B

PT21A

PT20B

PT20A

PT19B

GNDIO0

PT19A

PT18B

PT18A

PT17B

VCCIO0

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

GNDIO0

PT14A

PT13B

VCCIO0

GNDIO0

VCCIO0

GNDIO0

VCCIO0

PT10B

GNDIO0

PT10A

PT9B

C

T

C

T

C

T

D9

G10

GND

H10

A5

C

0

-

T

C

T

0

-

T

C

T

B5

C7

C

VCCIO

D7

T

C

T

C

T

E8

F10

F8

C

T

C

T

H9

C5

C

GND

D5

0

-

T

0

-

T

B4

VCCIO

GND

VCCIO

GND

VCCIO

C4

0

-

0

-

0

-

0

-

C

GND

C3

0

-

T

C

T

0

-

T

C

T

A4

A3

PT9A

B3

PT8B

C

PT8B

C

VCCIO

B2

VCCIO0

PT8A

VCCIO0

PT8A

T

C

T

C

T

D4

PT7B

D3

PT7A

C2

PT6B

C

T

PT6B

C

T

C1

PT6A

G8

PT5B

C

PT5B

C

GND

G7

GNDIO0

PT5A

GNDIO0

PT5A

0

T

0

T

E7

PT4B

C

PT4B

C

VCCIO

F7

VCCIO0

PT4A

VCCIO0

PT4A

T

C

T

C

T

C

T

C

T

E6

PT3B

E5

PT3A

G6

PT2B

VREF2_0

VREF1_0

PT2B

VREF2_0

VREF1_0

G5

PT2A

4-86

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

-

Dual Function

Differential

L12

L13

VCC

-

VCC

-

L14

VCC

-

VCC

-

L15

VCC

-

VCC

-

M11

M12

M15

M16

N11

N16

P11

P16

R11

R12

R15

R16

T12

T13

T14

T15

D11

D6

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

G9

K12

J12

D16

D21

G18

J15

K15

F23

J20

L23

M17

M18

AA23

R17

R18

T23

V20

AC16

AC21

U15

V15

Y18

AC11

AC6

4-87

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

U12

V12

Y9

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

AA4

R10

R9

T4

V7

F4

J7

L4

M10

M9

AE25

V18

J10

J11

J16

J17

K18

K9

-

L18

L9

-

T18

T9

-

U18

U9

-

V10

V11

V16

V17

A2

-

A25

AA18

AA24

AA3

AA9

AD11

AD16

AD21

AD6

AE1

AE26

AF2

AF25

B1

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

B26

GND

-

GND

-

4-88

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

C11

C16

C21

C6

GND

-

GND

-

F18

F24

F3

F9

J13

J14

J21

J6

K10

K11

K13

K14

K16

K17

L10

L11

L16

L17

L24

L3

M13

M14

N10

N12

N13

N14

N15

N17

P10

P12

P13

P14

P15

P17

R13

R14

T10

T11

T16

T17

T24

T3

U10

4-89

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA

LFE2-20E/20SE

LFE2-35E/35SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

U11

U13

U14

U16

U17

V13

V14

V21

V6

GND

NC

-

GND

NC

-

M3

N6

NC

P24

NC

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-90

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

D2

D1

PL2A

PL2B

VREF2_7

VREF1_7

PL2A

PL2B

VREF2_7

VREF1_7

GND

F6

GNDIO7

PL5A

GNDIO7

PL18A

PL18B

VCCIO7

PL19A

PL19B

PL20A

PL20B

GNDIO7

PL21A

PL21B

PL22A

VCCIO7

PL22B

PL23A

PL23B

PL24A

GNDIO7

PL24B

PL25A

PL25B

PL26A

PL26B

PL27A

VCCIO7

PL27B

PL28A

PL28B

PL29A

GNDIO7

PL29B

PL30A

PL30B

VCCIO7

PL31A

PL31B

PL32A

PL32B

GNDIO7

VCCIO7

PL36A

PL36B

GNDIO7

PL37A

PL37B

7

-

LDQ8

T

7

-

LDQ21

T

F5

PL5B

C

VCCIO

E4

VCCIO7

PL6A

LDQ8

T (LVDS)*

LDQ21

T (LVDS)*

E3

PL6B

C (LVDS)*

E2

PL7A

T

E1

PL7B

C

GND

H6

GNDIO7

PL8A

7

-

LDQS8

LDQ8

T (LVDS)*

C (LVDS)*

T

7

-

LDQS21

LDQ21

T (LVDS)*

C (LVDS)*

T

H5

PL8B

F2

PL9A

VCCIO

F1

VCCIO7

PL9B

LDQ8

C

LDQ21

C

H8

PL10A

PL10B

PL11A

GNDIO7

PL11B

PL12A

PL12B

PL13A

PL13B

PL14A

VCCIO7

PL14B

PL15A

PL15B

PL16A

GNDIO7

PL16B

PL17A

PL17B

VCCIO7

PL18A

PL18B

PL19A

PL19B

GNDIO7

VCCIO7

PL23A

PL23B

GNDIO7

PL24A

PL24B

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

J9

G4

GND

G3

7

-

LDQ8

LDQ16

C

7

-

LDQ21

LDQ29

C

H7

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

J8

G2

G1

C

H3

T (LVDS)*

VCCIO

H4

LDQ16

LDQS16

C (LVDS)*

LDQ29

LDQS29

C (LVDS)*

J5

T

C

T

C

J4

J3

T (LVDS)*

GND

K4

7

-

LDQ16

C (LVDS)*

7

-

LDQ29

C (LVDS)*

H1

T

H2

C

VCCIO

K6

LDQ16

T (LVDS)*

LDQ29

T (LVDS)*

K7

C (LVDS)*

J1

T

J2

C

GND

VCCIO

K3

7

-

7

-

LDQ24

T

LDQ37

T

K2

C

GND

K1

7

LDQS24***

LDQ24

T (LVDS)*

C (LVDS)*

7

LDQS37***

LDQ37

T (LVDS)*

C (LVDS)*

L2

4-91

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

Bank

7

-

Dual Function

Differential

L1

VCCIO

M2

PL25A

VCCIO7

PL25B

PL26A

PL26B

GNDIO7

VCCPLL

VCCIO7

GNDIO7

PL37A

PL38A

PL38B

VCCIO7

PL39A

PL39B

PL40A

PL40B

GNDIO7

PL41A

PL41B

PL42A

VCCIO7

PL42B

PL43A

PL43B

PL44A

GNDIO7

PL44B

PL46A

PL46B

PL47A

PL47B

PL48A

VCCIO6

PL48B

PL49A

PL49B

PL50A

GNDIO6

PL50B

PL51A

PL51B

VCCIO6

PL52A

PL52B

PL53A

PL53B

LUM0_SPLLT_IN_A/LDQ24

T

PL38A

VCCIO7

PL38B

PL39A

PL39B

GNDIO7

NC

LUM0_SPLLT_IN_A/LDQ37

T

LUM0_SPLLC_IN_A/LDQ24

LUM0_SPLLT_FB_A/LDQ24

LUM0_SPLLC_FB_A/LDQ24

C

T

LUM0_SPLLC_IN_A/LDQ37

LUM0_SPLLT_FB_A/LDQ37

LUM0_SPLLC_FB_A/LDQ37

C

T

M1

N2

C

GND

M8

7

-

VCCIO

GND

N1

VCCIO7

GNDIO7

PL50A

PL51A

PL51B

VCCIO7

PL52A

PL52B

PL53A

PL53B

GNDIO7

PL54A

PL54B

PL55A

VCCIO7

PL55B

PL56A

PL56B

PL57A

GNDIO7

PL57B

PL59A

PL59B

PL60A

PL60B

PL61A

VCCIO6

PL61B

PL62A

PL62B

PL63A

GNDIO6

PL63B

PL64A

PL64B

VCCIO6

PL65A

PL65B

PL66A

PL66B

7

-

7

-

LDQ41

7

-

LDQ54

L8

T

K8

C

VCCIO

L6

LDQ41

T (LVDS)*

LDQ54

T (LVDS)*

K5

C (LVDS)*

L7

T

L5

C

GND

P1

7

-

LDQS41

LDQ41

T (LVDS)*

C (LVDS)*

T

7

-

LDQS54

LDQ54

T (LVDS)*

C (LVDS)*

T

P2

M6

VCCIO

N8

LDQ41

C

LDQ54

C

R1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

R2

LDQ41

LDQ54

M7

PCLKT7_0/LDQ41

PCLKT7_0/LDQ54

GND

N9

7

6

-

PCLKC7_0/LDQ41

PCLKT6_0/LDQ50

PCLKC6_0/LDQ50

VREF2_6/LDQ50

VREF1_6/LDQ50

LDQ50

C

7

6

-

PCLKC7_0/LDQ54

PCLKT6_0/LDQ63

PCLKC6_0/LDQ63

VREF2_6/LDQ63

VREF1_6/LDQ63

LDQ63

C

M4

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

M5

N7

P9

C

N3

T (LVDS)*

VCCIO

N4

LDQ50

LDQS50

C (LVDS)*

LDQ63

LDQS63

C (LVDS)*

N5

T

C

T

C

P7

T1

T (LVDS)*

GND

T2

6

LDQ50

C (LVDS)*

6

LDQ63

C (LVDS)*

P8

T

P6

C

VCCIO

P5

LDQ50

T (LVDS)*

LDQ63

T (LVDS)*

P4

C (LVDS)*

U1

T

V1

C

4-92

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

GND

P3

GNDIO6

PL54A

PL54B

PL55A

PL55B

VCCIO6

PL56A

PL56B

PL57A

PL57B

GNDIO6

PL58A

PL58B

PL59A

VCCIO6

PL59B

PL60A

PL60B

PL61A

GNDIO6

PL61B

VCCPLL

LLM0_PLLCAP

PL63A

PL63B

PL64A

PL64B

PL65A

VCCIO6

PL65B

PL66A

PL66B

PL67A

GNDIO6

PL67B

PL68A

PL68B

VCCIO6

PL69A

PL69B

PL70A

PL70B

GNDIO6

PL71A

PL71B

PL72A

PL72B

GNDIO6

PL67A

PL67B

PL68A

PL68B

VCCIO6

PL69A

PL69B

PL70A

PL70B

GNDIO6

PL71A

PL71B

PL72A

VCCIO6

PL72B

PL73A

PL73B

PL74A

GNDIO6

PL74B

VCCPLL

LLM0_PLLCAP

PL76A

PL76B

PL77A

PL77B

PL78A

VCCIO6

PL78B

PL79A

PL79B

PL80A

GNDIO6

PL80B

PL81A

PL81B

VCCIO6

PL82A

PL82B

PL83A

PL83B

GNDIO6

PL84A

PL84B

PL85A

PL85B

6

-

LDQ58

T (LVDS)*

6

-

LDQ71

T (LVDS)*

R3

C (LVDS)*

R4

T

U2

C

VCCIO

V2

LDQ58

T (LVDS)*

LDQ71

T (LVDS)*

W2

T6

C (LVDS)*

T

R5

C

GND

R6

6

-

LDQS58

LDQ58

T (LVDS)*

C (LVDS)*

T

6

-

LDQS71

LDQ71

T (LVDS)*

C (LVDS)*

T

R7

W1

VCCIO

Y2

LDQ58

C

LDQ71

C

Y1

LLM0_GDLLT_IN_A**/LDQ58

T (LVDS)*

LLM0_GDLLT_IN_A**/LDQ71 T (LVDS)*

LLM0_GDLLC_IN_A**/LDQ71 C (LVDS)*

AA2

T5

LLM0_GDLLC_IN_A**/LDQ58 C (LVDS)*

LLM0_GDLLT_FB_A/LDQ58

LLM0_GDLLC_FB_D/LDQ58

T

LLM0_GDLLT_FB_A/LDQ71

T

GND

T7

6

-

C

6

-

LLM0_GDLLC_FB_D/LDQ71

C

R8

T8

6

-

U3

LLM0_GPLLT_IN_A**/LDQ67

T (LVDS)*

LLM0_GPLLT_IN_A**/LDQ80

T (LVDS)*

U4

LLM0_GPLLC_IN_A**/LDQ67 C (LVDS)*

LLM0_GPLLC_IN_A**/LDQ80 C (LVDS)*

V3

LLM0_GPLLT_FB_A/LDQ67

LLM0_GPLLC_FB_A/LDQ67

LDQ67

T

C

LLM0_GPLLT_FB_A/LDQ80

LLM0_GPLLC_FB_A/LDQ80

LDQ80

T

C

U5

V4

T (LVDS)*

VCCIO

V5

LDQ67

LDQS67

C (LVDS)*

LDQ80

LDQS80

C (LVDS)*

Y3

T

C

T

C

Y4

W3

GND

W4

AA1

AB1

VCCIO

U8

T (LVDS)*

6

-

LDQ67

C (LVDS)*

6

-

LDQ80

C (LVDS)*

T

C

LDQ67

T (LVDS)*

LDQ80

T (LVDS)*

U7

C (LVDS)*

V8

T

U6

C

GND

W6

W5

AC1

AD1

6

LDQ75

T (LVDS)*

6

LDQ88

T (LVDS)*

C (LVDS)*

T

C

4-93

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

6

-

Dual Function

Differential

Bank

6

-

Dual Function

Differential

VCCIO

Y6

VCCIO6

PL73A

PL73B

PL74A

PL74B

GNDIO6

PL75A

PL75B

PL76A

VCCIO6

PL76B

PL77A

PL77B

PL78A

GNDIO6

PL78B

TCK

VCCIO6

PL86A

PL86B

PL87A

PL87B

GNDIO6

PL88A

PL88B

PL89A

VCCIO6

PL89B

PL90A

PL90B

PL91A

GNDIO6

PL91B

TCK

LDQ75

T (LVDS)*

LDQ88

T (LVDS)*

Y5

C (LVDS)*

AE2

AD2

GND

AB3

AB2

W7

T

C

6

-

LDQS75

LDQ75

T (LVDS)*

C (LVDS)*

T

6

-

LDQS88

LDQ88

T (LVDS)*

C (LVDS)*

T

VCCIO

W8

LDQ75

C

LDQ88

C

Y7

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

Y8

AC2

GND

AD3

AC3

AA8

AB4

AA5

AB5

AE3

AF3

AC4

AD4

AE4

AF4

VCCIO

V9

6

-

LDQ75

C

6

-

LDQ88

C

TDI

-

TDI

-

TMS

-

TMS

-

TDO

-

TDO

-

VCCJ

-

VCCJ

-

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

PB2B

PB3A

PB3B

BDQ6

C

T

PB3B

BDQ6

C

T

PB4A

BDQ6

PB4A

BDQ6

PB4B

BDQ6

C

PB4B

BDQ6

C

VCCIO5

PB5A

VCCIO5

PB5A

BDQ6

T

BDQ6

T

W9

PB5B

C

PB5B

C

GND

AA6

AB6

AC5

AD5

AA7

AB7

VCCIO

AE5

AF5

AC7

AD7

VCCIO

GND

W10

Y10

GNDIO5

PB6A

GNDIO5

PB6A

5

-

BDQS6

BDQ6

T

C

T

5

-

BDQS6

BDQ6

T

C

T

PB6B

PB7A

PB7B

C

T

PB7B

C

T

PB8A

PB8B

C

PB8B

C

VCCIO5

PB9A

VCCIO5

PB9A

BDQ6

T

C

T

BDQ6

T

C

T

PB9B

PB10A

PB10B

VCCIO5

GNDIO5

PB20A

PB20B

PB21A

PB10A

PB10B

VCCIO5

GNDIO5

PB29A

PB29B

PB30A

C

5

BDQ24

T

C

T

5

BDQ33

T

C

T

W11

4-94

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

5

-

Dual Function

Differential

Bank

5

-

Dual Function

Differential

AA10

AC8

PB21B

PB22A

PB22B

VCCIO5

PB23A

PB23B

GNDIO5

PB24A

PB24B

PB25A

PB25B

PB26A

PB26B

VCCIO5

PB27A

PB27B

PB28A

PB28B

GNDIO5

PB29A

PB29B

PB30A

PB30B

PB31A

VCCIO5

PB31B

PB32A

PB32B

PB33A

GNDIO5

PB33B

PB34A

PB34B

PB35A

VCCIO5

PB35B

PB36A

PB36B

PB37A

GNDIO5

PB37B

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

BDQ24

C

T

PB30B

PB31A

PB31B

VCCIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

PB36A

PB36B

PB37A

PB37B

GNDIO5

PB38A

PB38B

PB39A

PB39B

PB40A

VCCIO5

PB40B

PB41A

PB41B

PB42A

GNDIO5

PB42B

PB43A

PB43B

PB44A

VCCIO5

PB44B

PB45A

PB45B

PB46A

GNDIO5

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

BDQ33

C

T

AD8

C

VCCIO

AB8

BDQ24

T

BDQ33

T

AB10

GND

AE6

C

5

-

BDQS24

BDQ24

T

C

T

5

-

BDQS33

BDQ33

T

C

T

AF6

AA11

AC9

C

T

C

T

AB9

AD9

C

VCCIO

Y11

BDQ24

T

C

T

BDQ33

T

C

T

AB11

AE7

AF7

C

GND

AC10

AD10

AA12

W12

5

-

BDQ33

T

C

T

C

T

5

-

BDQ42

T

C

T

C

T

AB12

VCCIO

Y12

BDQ33

BDQS33

C

T

C

T

BDQ42

BDQS42

C

T

C

T

AD12

AC12

AC13

GND

AA13

AD13

AC14

AE8

5

-

BDQ33

C

T

C

T

5

-

BDQ42

C

T

C

T

VCCIO

AF8

BDQ33

C

T

C

T

BDQ42

C

T

C

T

AB15

Y13

AE9

GND

AF9

5

BDQ33

BDQ42

C

T

5

BDQ42

BDQ51

C

T

W13

AA14

AE10

AF10

W14

C

T

C

T

C

T

C

T

AB13

C

4-95

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

5

-

Dual Function

Differential

Bank

5

-

Dual Function

Differential

VCCIO

Y14

VCCIO5

PB41A

PB41B

GNDIO5

PB42A

PB42B

PB43A

PB43B

PB44A

PB44B

VCCIO5

GNDIO5

PB49A

VCCIO4

PB49B

PB50A

PB50B

PB51A

GNDIO4

PB51B

PB52A

PB52B

PB53A

VCCIO4

PB53B

PB54A

PB54B

PB55A

GNDIO4

PB55B

PB56A

PB56B

PB57A

PB57B

PB58A

PB58B

VCCIO4

PB59A

PB59B

GNDIO4

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO4

VCCIO5

PB50A

PB50B

GNDIO5

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO5

GNDIO5

PB58A

VCCIO4

PB58B

PB59A

PB59B

PB60A

GNDIO4

PB60B

PB61A

PB61B

PB62A

VCCIO4

PB62B

PB63A

PB63B

PB64A

GNDIO4

PB64B

PB65A

PB65B

PB66A

PB66B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

BDQ42

T

BDQ51

T

AB14

GND

C

AE11

AF11

AD14

AA15

AE12

AF12

VCCIO

GND

5

-

BDQS42

BDQ42

T

C

T

5

-

BDQS51

BDQ51

T

C

T

BDQ42

BDQ51

BDQ42

C

T

BDQ51

C

T

PCLKT5_0/BDQ42

PCLKC5_0/BDQ42

PCLKT5_0/BDQ51

PCLKC5_0/BDQ51

C

AD15

VCCIO

AC15

AE13

AF13

AB17

GND

4

-

PCLKT4_0/BDQ51

T

4

-

PCLKT4_0/BDQ60

T

PCLKC4_0/BDQ51

BDQ51

C

T

C

T

PCLKC4_0/BDQ60

BDQ60

C

T

C

T

BDQ51

BDQ60

BDQS51

BDQS60

Y15

4

-

BDQ51

C

T

C

T

4

-

BDQ60

C

T

C

T

AE14

AF14

AA16

VCCIO

W15

BDQ51

C

T

C

T

BDQ60

C

T

C

T

AC17

AB16

AE15

GND

AF15

AE16

AF16

Y16

4

-

BDQ51

BDQ60

C

T

4

-

BDQ60

BDQ69

C

T

C

T

C

T

AB18

AD17

AD18

VCCIO

AC18

AD19

GND

C

T

C

T

C

BDQ60

T

BDQ69

T

C

AC19

AE17

AB19

AE19

AF17

AE18

VCCIO

4

BDQS60

BDQ60

T

C

T

4

BDQS69

BDQ69

T

C

T

C

T

C

T

C

4-96

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

4

-

Dual Function

Differential

Bank

4

-

Dual Function

Differential

W16

AA17

AF18

AF19

GND

AA19

W17

PB63A

PB63B

PB64A

PB64B

GNDIO4

PB65A

PB65B

PB66A

PB66B

PB67A

VCCIO4

PB67B

PB68A

PB68B

PB69A

GNDIO4

PB69B

PB70A

PB70B

VCCIO4

GNDIO4

PB74A

PB74B

PB75A

PB75B

PB76A

PB76B

VCCIO4

PB77A

PB77B

GNDIO4

PB78A

PB78B

PB79A

PB79B

PB80A

PB80B

VCCIO4

PB81A

PB81B

PB82A

PB82B

GNDIO4

CFG2

BDQ60

T

C

T

PB72A

PB72B

PB73A

PB73B

GNDIO4

PB74A

PB74B

PB75A

PB75B

PB76A

VCCIO4

PB76B

PB77A

PB77B

PB78A

GNDIO4

PB78B

PB79A

PB79B

VCCIO4

GNDIO4

PB92A

PB92B

PB93A

PB93B

PB94A

PB94B

VCCIO4

PB95A

PB95B

GNDIO4

PB96A

PB96B

PB97A

PB97B

PB98A

PB98B

VCCIO4

PB99A

PB99B

PB100A

PB100B

GNDIO4

CFG2

BDQ69

T

C

T

C

4

-

BDQ69

T

C

T

C

T

4

-

BDQ78

T

C

T

C

T

Y19

Y17

AF20

VCCIO

AE20

AA20

W18

BDQ69

BDQS69

C

T

C

T

BDQ78

BDQS78

C

T

C

T

AD20

GND

AE21

AF21

AF22

VCCIO

GND

AE22

AD22

AF23

AE23

AD23

AC23

VCCIO

AB20

AC20

GND

AB21

AC22

W19

4

-

BDQ69

C

T

4

-

BDQ78

C

T

C

4

-

BDQ78

T

C

T

4

-

BDQ96

T

C

T

C

T

C

T

C

BDQ78

T

BDQ96

T

C

4

-

BDQS78

BDQ78

T

C

T

4

-

BDQS96

BDQ96

T

C

T

AA21

AF24

AE24

VCCIO

Y20

C

T

C

T

C

BDQ78

T

C

T

BDQ96

T

C

T

AB22

Y21

BDQ78

BDQ96

VREF2_4/BDQ78

VREF1_4/BDQ78

VREF2_4/BDQ96

VREF1_4/BDQ96

AB23

GND

AD24

W20

C

8

CFG1

AC24

V19

CFG0

PROGRAMN

4-97

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

8

-

Dual Function

Differential

Bank

8

-

Dual Function

Differential

AA22

AB24

AD25

GND

W21

Y22

CCLK

INITN

CCLK

INITN

DONE

GNDIO8

PR77B

PR77A

PR76B

PR76A

VCCIO8

PR75B

PR75A

PR74B

GNDIO8

PR74A

PR73B

PR73A

PR72B

VCCIO8

PR72A

PR71B

PR71A

PR70B

GNDIO3

PR70A

PR69B

PR69A

PR68B

VCCIO3

PR68A

PR67B

PR67A

GNDIO3

PR66B

PR66A

PR65B

PR65A

VCCIO3

PR64B

PR64A

PR63B

PR63A

RLM0_PLLCAP

VCCPLL

PR61B

PR61A

GNDIO3

PR60B

GNDIO8

PR90B

PR90A

PR89B

PR89A

VCCIO8

PR88B

PR88A

PR87B

GNDIO8

PR87A

PR86B

PR86A

PR85B

VCCIO8

PR85A

PR84B

PR84A

PR83B

GNDIO3

PR83A

PR82B

PR82A

PR81B

VCCIO3

PR81A

PR80B

PR80A

GNDIO3

PR79B

PR79A

PR78B

PR78A

VCCIO3

PR77B

PR77A

PR76B

PR76A

RLM0_PLLCAP

VCCPLL

PR74B

PR74A

GNDIO3

PR73B

8

-

WRITEN

CS1N

C

T

C

T

8

-

WRITEN

CS1N

C

T

C

T

AC25

AB25

VCCIO

AD26

AC26

Y23

CSN

D0/SPIFASTN

D1

D2

D3

C

T

D1

D2

D3

C

T

C

GND

W22

AA25

AB26

W23

VCCIO

V22

8

3

-

D4

D5

D6

D7

T

C

T

8

3

-

D4

D5

D6

D7

T

C

T

C

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

RDQ67

T

C

T

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

RDQ80

T

C

T

Y24

Y25

W24

GND

V23

C

3

-

RDQ67

T

3

-

RDQ80

T

AA26

Y26

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

U21

VCCIO

U19

RDQ67

T

RDQ80

T

W25

W26

GND

V24

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS67

RDQS80

3

-

RDQ67

C

3

-

RDQ80

C

V25

T

V26

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

U26

VCCIO

U22

RLM0_GPLLC_FB_A/RDQ67

RLM0_GPLLT_FB_A/RDQ67

C

T

RLM0_GPLLC_FB_A/RDQ80

RLM0_GPLLT_FB_A/RDQ80

C

T

U23

U24

RLM0_GPLLC_IN_A**/RDQ67 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ67 T (LVDS)*

RLM0_GPLLC_IN_A**/RDQ80 C (LVDS)*

RLM0_GPLLT_IN_A**/RDQ80 T (LVDS)*

U25

R20

P18

T19

RLM0_GDLLC_FB_A/RDQ58

RLM0_GDLLT_FB_A/RDQ58

C

T

3

-

RLM0_GDLLC_FB_A/RDQ71

RLM0_GDLLT_FB_A/RDQ71

C

T

U20

GND

T25

3

RLM0_GDLLC_IN_A**/RDQ58 C (LVDS)*

3

RLM0_GDLLC_IN_A**/RDQ71 C (LVDS)*

4-98

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

3

-

Dual Function

Differential

Bank

3

-

Dual Function

Differential

T26

T20

PR60A

PR59B

PR59A

VCCIO3

PR58B

PR58A

PR57B

GNDIO3

PR57A

PR56B

PR56A

PR55B

VCCIO3

PR55A

PR54B

PR54A

PR53B

GNDIO3

PR53A

PR52B

PR52A

PR51B

VCCIO3

PR51A

PR50B

PR50A

GNDIO3

PR49B

PR49A

PR48B

PR48A

VCCIO3

PR47B

PR47A

PR46B

PR46A

PR44B

PR44A

GNDIO2

PR43B

PR43A

PR42B

PR42A

VCCIO2

PR41B

PR41A

PR40B

RLM0_GDLLT_IN_A**/RDQ58 T (LVDS)*

PR73A

PR72B

PR72A

VCCIO3

PR71B

PR71A

PR70B

GNDIO3

PR70A

PR69B

PR69A

PR68B

VCCIO3

PR68A

PR67B

PR67A

PR66B

GNDIO3

PR66A

PR65B

PR65A

PR64B

VCCIO3

PR64A

PR63B

PR63A

GNDIO3

PR62B

PR62A

PR61B

PR61A

VCCIO3

PR60B

PR60A

PR59B

PR59A

PR57B

PR57A

GNDIO2

PR56B

PR56A

PR55B

PR55A

VCCIO2

PR54B

PR54A

PR53B

RLM0_GDLLT_IN_A**/RDQ71 T (LVDS)*

RDQ58

C

T

RDQ71

C

T

T22

VCCIO

R26

R25

R22

GND

T21

RDQ58

RDQS58

RDQ58

C (LVDS)*

T (LVDS)*

C

RDQ71

RDQS71

RDQ71

C (LVDS)*

T (LVDS)*

C

3

-

RDQ58

T

3

-

RDQ71

T

P26

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

P25

R24

VCCIO

R23

P20

RDQ58

RDQ50

T

RDQ71

RDQ63

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

R19

P21

GND

P19

3

-

RDQ50

T

3

-

RDQ63

T

P23

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

P22

N22

VCCIO

R21

N26

N25

GND

N19

N20

M26

M25

VCCIO

N18

N21

L26

RDQ50

T

RDQ63

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS50

RDQS63

3

2

-

RDQ50

C

3

2

-

RDQ63

C

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

VREF2_3/RDQ50

VREF1_3/RDQ50

PCLKC3_0/RDQ50

PCLKT3_0/RDQ50

PCLKC2_0/RDQ41

PCLKT2_0/RDQ41

C

VREF2_3/RDQ63

VREF1_3/RDQ63

PCLKC3_0/RDQ63

PCLKT3_0/RDQ63

PCLKC2_0/RDQ54

PCLKT2_0/RDQ54

C

T

C (LVDS)*

L25

T (LVDS)*

N24

M23

GND

L21

C

T

C

T

2

RDQ41

C (LVDS)*

2

RDQ54

C (LVDS)*

K22

T (LVDS)*

M24

N23

VCCIO

K26

C

T

C

T

RDQ41

RDQS41

RDQ41

C (LVDS)*

T (LVDS)*

C

RDQ54

RDQS54

RDQ54

C (LVDS)*

T (LVDS)*

C

K25

M20

4-99

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

GND

M19

L22

GNDIO2

PR40A

PR39B

PR39A

PR38B

VCCIO2

PR38A

PR37B

PR37A

GNDIO2

VCCIO2

VCCPLL

GNDIO2

PR26B

PR26A

PR25B

PR25A

VCCIO2

PR24B

PR24A

PR23B

GNDIO2

PR23A

VCCIO2

PR19B

GNDIO2

PR19A

PR18B

PR18A

PR17B

VCCIO2

PR17A

PR16B

PR16A

GNDIO2

PR15B

PR15A

PR14B

PR14A

VCCIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR53A

PR52B

PR52A

PR51B

VCCIO2

PR51A

PR50B

PR50A

GNDIO2

VCCIO2

NC

2

-

RDQ41

T

2

-

RDQ54

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

M22

K21

VCCIO

M21

K24

RDQ41

T

RDQ54

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

J24

GND

VCCIO

L20

2

-

2

-

GND

J26

GNDIO2

PR39B

PR39A

PR38B

PR38A

VCCIO2

PR37B

PR37A

PR36B

GNDIO2

PR36A

VCCIO2

PR32B

GNDIO2

PR32A

PR31B

PR31A

PR30B

VCCIO2

PR30A

PR29B

PR29A

GNDIO2

PR28B

PR28A

PR27B

PR27A

VCCIO2

PR26B

PR26A

PR25B

PR25A

PR24B

PR24A

GNDIO2

-

2

-

RUM0_SPLLC_FB_A/RDQ24

RUM0_SPLLT_FB_A/RDQ24

RUM0_SPLLC_IN_A/RDQ24

RUM0_SPLLT_IN_A/RDQ24

C

T

C

T

2

-

RUM0_SPLLC_FB_A/RDQ37

RUM0_SPLLT_FB_A/RDQ37

RUM0_SPLLC_IN_A/RDQ37

RUM0_SPLLT_IN_A/RDQ37

C

T

C

T

J25

J23

K23

VCCIO

H26

RDQ24

RDQS24***

RDQ24

C (LVDS)*

T (LVDS)*

C

RDQ37

RDQS37***

RDQ37

C (LVDS)*

T (LVDS)*

C

H25

H24

GND

H23

2

-

RDQ24

RDQ16

T

2

-

RDQ37

RDQ29

T

VCCIO

G26

GND

G25

F26

C

2

-

RDQ16

T

2

-

RDQ29

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

F25

K20

VCCIO

L19

RDQ16

T

RDQ29

T

E26

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

E25

RDQS16

RDQS29

GND

J22

2

-

RDQ16

C

2

-

RDQ29

C

H22

T

G24

G23

VCCIO

K19

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQ16

RDQ8

C

RDQ29

RDQ21

C

J19

T

D26

C (LVDS)*

C26

T (LVDS)*

F22

C

T

C

T

E24

RDQ8

GND

4-100

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

-

Dual Function

Differential

C (LVDS)*

T (LVDS)*

C

Bank

2

-

Dual Function

Differential

C (LVDS)*

T (LVDS)*

C

D25

C25

D24

B25

PR10B

PR10A

PR9B

RDQ8

PR23B

PR23A

PR22B

PR22A

VCCIO2

PR21B

PR21A

PR20B

GNDIO2

PR20A

PR19B

PR19A

PR18B

VCCIO2

PR18A

GNDIO2

PR2B

RDQ21

PR9A

T

VCCIO

H21

G22

B24

VCCIO2

PR8B

RDQ8

RDQS8

RDQ8

C (LVDS)*

T (LVDS)*

C

RDQ21

RDQS21

RDQ21

C (LVDS)*

T (LVDS)*

C

PR8A

PR7B

GND

C24

D23

C23

G21

VCCIO

H20

GND

E22

GNDIO2

PR7A

2

-

RDQ8

T

2

-

RDQ21

T

PR6B

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

PR6A

PR5B

VCCIO2

PR5A

RDQ8

T

RDQ21

T

GNDIO2

PR2B

2

1

-

VREF2_2

VREF1_2

VREF2_1

C (LVDS)*

T (LVDS)*

C

2

1

-

VREF2_2

VREF1_2

VREF2_1

C (LVDS)*

T (LVDS)*

C

F21

PR2A

E23

PT82B

GNDIO1

PT82A

PT81B

PT81A

PT80B

VCCIO1

PT80A

PT79B

PT79A

PT78B

PT78A

PT77B

GNDIO1

PT77A

PT76B

VCCIO1

PT76A

PT75B

PT75A

PT74B

PT74A

GNDIO1

PT71B

PT71A

VCCIO1

PT70B

PT70A

PT69B

PT100B

GNDIO1

PT100A

PT99B

PT99A

PT98B

VCCIO1

PT98A

PT97B

PT97A

PT96B

PT96A

PT95B

GNDIO1

PT95A

PT94B

VCCIO1

PT94A

PT93B

PT93A

PT92B

PT92A

GNDIO1

PT85B

PT85A

VCCIO1

PT79B

PT79A

PT78B

GND

D22

G20

J18

1

-

VREF1_1

T

C

T

1

-

VREF1_1

T

C

T

F20

C

VCCIO

H19

A24

T

C

T

C

T

A23

E21

C

T

C

T

F19

C22

GND

E20

C

1

-

T

1

-

T

B22

C

VCCIO

B23

T

C

T

C

T

C

T

C

T

C20

D20

A22

A21

GND

E19

1

C

T

1

C

T

C19

VCCIO

B21

C

T

C

T

B20

D19

C

4-101

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

1

-

Dual Function

Differential

Bank

1

-

Dual Function

Differential

B19

GND

G17

E18

PT69A

GNDIO1

PT68B

PT68A

PT67B

PT67A

VCCIO1

PT66B

PT66A

PT65B

PT65A

PT64B

GNDIO1

PT64A

PT63B

PT63A

PT62B

VCCIO1

PT62A

PT61B

PT61A

PT60B

PT60A

PT59B

GNDIO1

PT59A

PT58B

VCCIO1

PT58A

PT57B

PT57A

PT56B

PT56A

PT55B

PT55A

GNDIO1

PT54B

PT54A

PT53B

PT53A

VCCIO1

PT52B

PT52A

PT51B

PT51A

GNDIO1

PT50B

T

PT78A

GNDIO1

PT77B

PT77A

PT76B

PT76A

VCCIO1

PT75B

PT75A

PT74B

PT74A

PT73B

GNDIO1

PT73A

PT72B

PT72A

PT71B

VCCIO1

PT71A

PT70B

PT70A

PT69B

PT69A

PT68B

GNDIO1

PT68A

PT67B

VCCIO1

PT67A

PT66B

PT66A

PT65B

PT65A

PT64B

PT64A

GNDIO1

PT63B

PT63A

PT62B

PT62A

VCCIO1

PT61B

PT61A

PT60B

PT60A

GNDIO1

PT59B

T

1

-

C

T

C

T

1

-

C

T

C

T

G19

F17

VCCIO

A20

C

T

C

T

A19

E17

C

T

C

T

D18

B18

C

GND

A18

1

-

T

C

T

1

-

T

C

T

E16

G16

F16

C

VCCIO

H18

A17

T

C

T

C

T

B17

C18

B16

C

T

C

T

C17

GND

D17

E15

C

1

-

T

1

-

T

C

VCCIO

G15

A16

T

C

T

C

T

C

T

C

T

C

T

C

T

B15

D15

F15

A14

B14

GND

C15

A15

1

-

C

T

C

T

1

-

C

T

C

T

A13

B13

VCCIO

H17

H15

D13

C14

GND

G14

C

T

C

T

C

T

C

T

1

C

1

C

4-102

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

1

0

-

Dual Function

Differential

Bank

1

0

-

Dual Function

Differential

E14

A12

B12

VCCIO

F14

D14

H16

H14

GND

H13

A11

B11

C13

VCCIO

E13

D12

F13

A10

B10

C12

GND

C10

G13

VCCIO

H12

A9

PT50A

PT49B

PT49A

VCCIO1

PT48B

PT48A

XRES

T

C

T

PT59A

PT58B

PT58A

VCCIO1

PT57B

PT57A

XRES

T

C

T

PCLKC1_0

PCLKT1_0

C

T

PCLKC1_0

PCLKT1_0

C

T

PT46B

GNDIO0

PT46A

PT45B

PT45A

PT44B

VCCIO0

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

GNDIO0

PT41A

PT40B

VCCIO0

PT40A

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

GNDIO0

PT36B

PT36A

PT35B

PT35A

VCCIO0

PT34B

PT34A

PT33B

PT33A

GNDIO0

PT32B

PT32A

PT31B

PT31A

VCCIO0

PCLKC0_0

PCLKT0_0

C

PT55B

GNDIO0

PT55A

PT54B

PT54A

PT53B

VCCIO0

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

GNDIO0

PT50A

PT49B

VCCIO0

PT49A

PT48B

PT48A

PT47B

PT47A

PT46B

PT46A

GNDIO0

PT45B

PT45A

PT44B

PT44A

VCCIO0

PT43B

PT43A

PT42B

PT42A

GNDIO0

PT41B

PT41A

PT40B

PT40A

VCCIO0

PCLKC0_0

PCLKT0_0

C

0

-

T

C

T

0

-

T

C

T

C

T

C

T

C

T

C

T

C

T

C

0

-

T

0

-

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

B9

E12

G12

A8

B8

GND

E11

C9

0

-

C

T

C

T

0

-

C

T

C

T

A7

B7

VCCIO

F12

D10

H11

G11

GND

A6

C

T

C

T

C

T

C

T

0

C

T

C

T

0

C

T

C

T

B6

D8

C8

VCCIO

4-103

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

0

-

Dual Function

Differential

Bank

0

-

Dual Function

Differential

F11

E10

E9

PT30B

PT30A

PT29B

PT29A

PT28B

GNDIO0

PT28A

PT27B

PT27A

PT26B

VCCIO0

PT26A

PT25B

PT25A

PT24B

PT24A

PT23B

GNDIO0

PT23A

PT22B

VCCIO0

GNDIO0

VCCIO0

GNDIO0

VCCIO0

PT10B

GNDIO0

PT10A

PT9B

C

T

PT39B

PT39A

PT38B

PT38A

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

PT31B

VCCIO0

GNDIO0

VCCIO0

GNDIO0

VCCIO0

PT10B

GNDIO0

PT10A

PT9B

C

T

C

T

C

T

D9

G10

GND

H10

A5

C

0

-

T

C

T

0

-

T

C

T

B5

C7

C

VCCIO

D7

T

C

T

C

T

E8

F10

F8

C

T

C

T

H9

C5

C

GND

D5

0

-

T

0

-

T

B4

VCCIO

GND

VCCIO

GND

VCCIO

C4

0

-

0

-

0

-

0

-

C

GND

C3

0

-

T

C

T

0

-

T

C

T

A4

A3

PT9A

B3

PT8B

C

PT8B

C

VCCIO

B2

VCCIO0

PT8A

VCCIO0

PT8A

T

C

T

C

T

D4

PT7B

D3

PT7A

C2

PT6B

C

T

PT6B

C

T

C1

PT6A

G8

PT5B

C

PT5B

C

GND

G7

GNDIO0

PT5A

GNDIO0

PT5A

0

T

0

T

E7

PT4B

C

PT4B

C

VCCIO

F7

VCCIO0

PT4A

VCCIO0

PT4A

T

C

T

C

T

C

T

C

T

E6

PT3B

E5

PT3A

G6

PT2B

VREF2_0

VREF1_0

PT2B

VREF2_0

VREF1_0

G5

PT2A

4-104

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

L12

L13

VCC

-

L14

VCC

-

VCC

-

L15

VCC

-

VCC

-

M11

M12

M15

M16

N11

N16

P11

P16

R11

R12

R15

R16

T12

T13

T14

T15

D11

D6

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

G9

K12

J12

D16

D21

G18

J15

K15

F23

J20

L23

M17

M18

AA23

R17

R18

T23

V20

AC16

AC21

U15

V15

Y18

AC11

AC6

4-105

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

U12

V12

Y9

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

AA4

R10

R9

T4

V7

F4

J7

L4

M10

M9

AE25

V18

J10

J11

J16

J17

K18

K9

-

L18

L9

-

T18

T9

-

U18

U9

-

V10

V11

V16

V17

A2

-

A25

AA18

AA24

AA3

AA9

AD11

AD16

AD21

AD6

AE1

AE26

AF2

AF25

B1

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

B26

GND

-

GND

-

4-106

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

C11

C16

C21

C6

GND

-

GND

-

F18

F24

F3

F9

J13

J14

J21

J6

K10

K11

K13

K14

K16

K17

L10

L11

L16

L17

L24

L3

M13

M14

N10

N12

N13

N14

N15

N17

P10

P12

P13

P14

P15

P17

R13

R14

T10

T11

T16

T17

T24

T3

U10

4-107

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA

LFE2-50E/SE

LFE2-70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

U11

U13

U14

U16

U17

V13

V14

V21

V6

GND

NC

-

GND

NC

-

M3

N6

NC

P24

NC

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-108

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA

LFE2-70E/SE

Ball Number

VCCIO

F4

Ball/Pad Function

VCCIO7

PL2A

Bank

7

-

Dual Function

Differential

VREF2_7

VREF1_7

T (LVDS)*

F3

PL2B

C (LVDS)*

H4

PL3A

T

G5

PL3B

C

GND

D2

GNDIO7

PL4A

7

-

T (LVDS)*

C (LVDS)*

T

D1

PL4B

E2

PL5A

VCCIO

E1

VCCIO7

PL5B

C

GND

VCCIO

F1

GNDIO7

VCCIO7

PL14A

PL14B

PL15A

PL15B

GNDIO7

PL18A

PL18B

VCCIO7

PL19A

PL19B

PL20A

PL20B

GNDIO7

PL21A

PL21B

PL22A

VCCIO7

PL22B

PL23A

PL23B

PL24A

GNDIO7

PL24B

PL25A

PL25B

PL26A

PL26B

VCCIO7

PL27A

7

-

LUM1_SPLLT_IN_A/LDQ12

LUM1_SPLLC_IN_A/LDQ12

LUM1_SPLLT_FB_A/LDQ12

LUM1_SPLLC_FB_A/LDQ12

T (LVDS)*

F2

C (LVDS)*

G1

T

G2

C

GND

H8

7

-

LDQ21

T

H6

C

VCCIO

G4

LDQ21

T (LVDS)*

G3

C (LVDS)*

H7

T

H5

C

GND

H2

7

-

LDQS21

LDQ21

T (LVDS)*

C (LVDS)*

T

H1

J6

VCCIO

J8

LDQ21

C

J2

T (LVDS)*

C (LVDS)*

T

J1

J5

GND

J7

7

LDQ21

LDQ29

C

J4

T (LVDS)*

J3

C (LVDS)*

K6

T

K8

C

VCCIO

K2

LDQ29

T (LVDS)*

4-109

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

K1

Ball/Pad Function

PL27B

PL28A

PL28B

GNDIO7

PL29A

PL29B

PL30A

VCCIO7

PL30B

PL31A

PL31B

PL32A

GNDIO7

PL32B

PL33A

PL33B

PL34A

PL34B

VCCIO7

PL35A

PL35B

PL36A

PL36B

GNDIO7

PL37A

PL37B

PL38A

VCCIO7

PL38B

PL39A

PL39B

GNDIO7

VCCIO7

PL50A

PL51A

PL51B

VCCIO7

PL52A

PL52B

PL53A

PL53B

GNDIO7

PL54A

Bank

7

-

Dual Function

LDQ29

Differential

C (LVDS)*

K5

LDQ29

T

K7

LDQ29

C

GND

K4

7

-

LDQS29

LDQ29

T (LVDS)*

C (LVDS)*

T

K3

L8

VCCIO

L6

LDQ29

C

L2

T (LVDS)*

C (LVDS)*

T

L1

L7

GND

L5

7

-

LDQ29

LDQ37

C

L4

T (LVDS)*

L3

C (LVDS)*

M8

T

M6

C

VCCIO

M2

LDQ37

T (LVDS)*

M1

C (LVDS)*

M7

T

M5

C

GND

M4

7

-

LDQS37

LDQ37

T (LVDS)*

C (LVDS)*

T

M3

N6

LUM0_SPLLT_IN_A/LDQ37

VCCIO

N8

LUM0_SPLLC_IN_A/LDQ37

LUM0_SPLLT_FB_A/LDQ37

LUM0_SPLLC_FB_A/LDQ37

C

T

N5

N7

C

GND

VCCIO

T9

7

-

LDQ54

R9

T

P7

C

VCCIO

N2

LDQ54

T (LVDS)*

N1

C (LVDS)*

P6

T

P5

C

GND

P4

7

LDQS54

T (LVDS)*

4-110

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

P3

Ball/Pad Function

PL54B

PL55A

VCCIO7

PL55B

PL56A

PL56B

PL57A

GNDIO7

PL57B

PL59A

PL59B

PL60A

PL60B

PL61A

VCCIO6

PL61B

PL62A

PL62B

PL63A

GNDIO6

PL63B

PL64A

PL64B

VCCIO6

PL65A

PL65B

PL66A

PL66B

GNDIO6

PL67A

PL67B

PL68A

PL68B

VCCIO6

PL69A

PL69B

PL70A

PL70B

GNDIO6

PL71A

PL71B

PL72A

VCCIO6

Bank

7

-

Dual Function

LDQ54

Differential

C (LVDS)*

T

R6

LDQ54

VCCIO

R8

LDQ54

C

P2

T (LVDS)*

C (LVDS)*

T

P1

LDQ54

R5

PCLKT7_0/LDQ54

GND

R7

7

6

-

PCLKC7_0/LDQ54

PCLKT6_0/LDQ63

PCLKC6_0/LDQ63

VREF2_6/LDQ63

VREF1_6/LDQ63

LDQ63

C

R4

T (LVDS)*

C (LVDS)*

T

R3

T5

T7

C

T3

T (LVDS)*

VCCIO

T4

LDQ63

LDQS63

C (LVDS)*

T6

T

C

T8

T2

T (LVDS)*

GND

T1

6

-

LDQ63

C (LVDS)*

U7

T

U5

C

VCCIO

U4

LDQ63

T (LVDS)*

U3

C (LVDS)*

U8

T

U6

C

GND

U2

6

-

LDQ71

T (LVDS)*

U1

C (LVDS)*

V7

T

V5

C

VCCIO

V2

LDQ71

T (LVDS)*

V1

C (LVDS)*

V8

T

V6

C

GND

W1

6

LDQS71

LDQ71

T (LVDS)*

C (LVDS)*

T

W2

W5

VCCIO

4-111

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

W7

Ball/Pad Function

PL72B

Bank

6

-

Dual Function

LDQ71

Differential

C

W4

PL73A

LLM0_GDLLT_IN_A**/LDQ71

LLM0_GDLLC_IN_A**/LDQ71

LLM0_GDLLT_FB_A/LDQ71

T (LVDS)*

C (LVDS)*

T

W3

PL73B

W6

PL74A

GND

W8

GNDIO6

PL74B

6

-

LLM0_GDLLC_FB_D/LDQ71

C

Y8

LLM0_PLLCAP

PL76A

Y1

LLM0_GPLLT_IN_A**/LDQ80

LLM0_GPLLC_IN_A**/LDQ80

LLM0_GPLLT_FB_A/LDQ80

LLM0_GPLLC_FB_A/LDQ80

LDQ80

T (LVDS)*

C (LVDS)*

T

Y2

PL76B

Y5

PL77A

Y6

PL77B

C

Y4

PL78A

T (LVDS)*

VCCIO

Y3

VCCIO6

PL78B

LDQ80

LDQS80

C (LVDS)*

AA6

AA8

AA2

GND

AA1

AA7

AA5

VCCIO

AA4

AA3

AB7

AB5

GND

AB2

AB1

AB8

AB6

VCCIO

AB4

AB3

AC7

AC5

GND

AC2

AC1

AC6

VCCIO

AD6

AD1

PL79A

T

C

PL79B

PL80A

T (LVDS)*

GNDIO6

PL80B

6

-

LDQ80

C (LVDS)*

PL81A

T

PL81B

C

VCCIO6

PL82A

LDQ80

T (LVDS)*

PL82B

C (LVDS)*

PL83A

T

PL83B

C

GNDIO6

PL84A

6

-

LDQ88

T (LVDS)*

PL84B

C (LVDS)*

PL85A

T

PL85B

C

VCCIO6

PL86A

LDQ88

T (LVDS)*

PL86B

C (LVDS)*

PL87A

T

PL87B

C

GNDIO6

PL88A

6

LDQS88

LDQ88

T (LVDS)*

C (LVDS)*

T

PL88B

PL89A

VCCIO6

PL89B

LDQ88

C

PL90A

T (LVDS)*

4-112

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AD2

Ball/Pad Function

PL90B

PL91A

GNDIO6

PL91B

TCK

Bank

6

-

Dual Function

LDQ88

Differential

C (LVDS)*

T

AD7

LDQ88

GND

AB9

6

-

LDQ88

C

AD5

AE7

TDI

-

AD4

TMS

-

AA9

TDO

-

AD3

VCCJ

-

AC8

PB2A

5

-

VREF2_5/BDQ6

VREF1_5/BDQ6

BDQ6

T

C

T

C

T

AE8

PB2B

AD8

PB3A

AF8

PB3B

BDQ6

AG7

VCCIO

AH7

PB4A

BDQ6

VCCIO5

PB4B

BDQ6

BDQS6

C

T

C

T

AC9

PB5A

AE9

PB5B

AD9

PB6A

GND

AF9

GNDIO5

PB6B

5

-

BDQ6

C

T

C

T

AB10

AA10

AJ7

PB7A

PB7B

PB8A

VCCIO

AK7

VCCIO5

PB8B

BDQ6

C

T

C

T

AC10

AE10

AJ8

PB9A

PB9B

PB10A

GNDIO5

PB10B

PB11A

PB11B

PB12A

PB12B

PB13A

PB13B

VCCIO5

PB14A

PB14B

GNDIO5

PB15A

PB15B

GND

AK8

5

-

BDQ6

BDQ15

C

T

AF6

AF7

C

T

AG5

AH5

C

T

AG6

AH6

C

VCCIO

AJ4

BDQ15

T

AK4

C

GND

AJ5

5

BDQS15

BDQ15

T

AK5

C

4-113

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AJ6

Ball/Pad Function

PB16A

PB16B

VCCIO5

GNDIO5

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

VCCIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

PB36A

PB36B

PB37A

PB37B

GNDIO5

PB38A

PB38B

PB39A

PB39B

PB40A

VCCIO5

PB40B

PB41A

PB41B

PB42A

GNDIO5

PB42B

PB43A

PB43B

PB44A

VCCIO5

PB44B

Bank

5

-

Dual Function

BDQ15

Differential

T

AK6

BDQ15

C

VCCIO

GND

AD10

AF10

AC11

AD11

AG9

5

99

5

-

BDQ33

T

C

T

C

T

AH9

C

VCCIO

AE11

AG10

GND

BDQ33

T

C

AJ9

5

-

BDQS33

BDQ33

T

C

T

AK9

AF11

AH10

AC12

AE12

VCCIO

AD12

AF12

AJ10

AK10

GND

C

T

C

BDQ33

T

C

T

C

AG11

AH11

AE13

AC13

AF13

VCCIO

AD13

AJ11

AK11

AD14

GND

5

-

BDQ42

T

C

T

C

T

BDQ42

BDQS42

C

T

C

T

AC14

AG12

AE14

AJ12

VCCIO

AK12

5

BDQ42

C

T

C

T

BDQ42

C

4-114

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AH12

AF14

AJ13

Ball/Pad Function

PB45A

PB45B

PB46A

GNDIO5

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO5

PB50A

PB50B

GNDIO5

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO5

GNDIO5

PB58A

VCCIO4

PB58B

PB59A

PB59B

PB60A

GNDIO4

PB60B

PB61A

PB61B

PB62A

VCCIO4

PB62B

PB63A

PB63B

PB64A

GNDIO4

PB64B

PB65A

PB65B

Bank

5

-

Dual Function

BDQ42

Differential

T

C

T

BDQ42

GND

AK13

AB15

AD15

AE15

AF15

AG15

AG14

VCCIO

AH15

AH14

GND

5

-

BDQ42

BDQ51

C

T

C

T

C

T

C

BDQ51

T

C

AJ14

5

-

BDQS51

BDQ51

T

C

T

AK14

AD16

AF16

AJ15

BDQ51

C

T

PCLKT5_0/BDQ51

PCLKC5_0/BDQ51

AK15

VCCIO

GND

C

AE16

VCCIO

AC15

AJ16

4

-

PCLKT4_0/BDQ60

T

PCLKC4_0/BDQ60

BDQ60

C

T

C

T

AK16

AC16

GND

BDQ60

BDQS60

AB16

AH17

AG17

AF17

VCCIO

AD17

AE17

AC17

AJ17

4

-

BDQ60

C

T

C

T

BDQ60

C

T

C

T

GND

AK17

AK18

AJ18

4

BDQ60

BDQ69

C

T

C

4-115

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AD18

AF18

AC18

AE18

VCCIO

AG19

AH19

GND

Ball/Pad Function

PB66A

PB66B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

PB72A

PB72B

PB73A

PB73B

GNDIO4

PB74A

PB74B

PB75A

PB75B

PB76A

VCCIO4

PB76B

PB77A

PB77B

PB78A

GNDIO4

PB78B

PB79A

PB79B

PB80A

VCCIO4

PB80B

GNDIO4

VCCIO4

PB87A

PB87B

PB88A

PB88B

Bank

4

-

Dual Function

BDQ69

Differential

T

C

T

BDQ69

C

BDQ69

T

C

AE19

AF19

AC19

AD19

AJ19

4

-

BDQS69

BDQ69

T

C

T

C

T

AK19

VCCIO

AF20

AH20

AE20

AG20

GND

C

BDQ69

T

C

T

C

AD20

AC20

AH21

AF21

AJ20

4

-

BDQ78

T

C

T

C

T

VCCIO

AK20

AG21

AE21

AD21

GND

BDQ78

BDQS78

C

T

C

T

AC21

AD22

AB21

AJ21

4

-

BDQ78

C

T

C

T

VCCIO

AK21

GND

BDQ78

C

VCCIO

AJ25

4

BDQS87***

BDQ87

T

C

T

AK24

AJ24

BDQ87

AK25

BDQ87

C

4-116

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AH24

AH25

VCCIO

AJ26

Ball/Pad Function

PB89A

PB89B

VCCIO4

PB90A

PB90B

PB91A

PB91B

GNDIO4

PB92A

PB92B

PB93A

PB93B

PB94A

VCCIO4

PB94B

PB95A

PB95B

PB96A

GNDIO4

PB97A

PB98A

VCCIO4

PB98B

PB99A

PB99B

PB100A

GNDIO4

PB100B

CFG2

Bank

4

-

Dual Function

BDQ87

Differential

T

BDQ87

C

BDQ87

T

C

T

AK26

AF25

AG25

GND

C

AK22

AJ22

4

-

BDQ96

T

C

T

C

T

AE22

AF22

AG22

VCCIO

AH22

AG24

AG23

AE23

GND

BDQ96

BDQS96

C

T

C

AC22

AJ23

4

-

BDQ96

T

VCCIO

AK23

AD24

AF24

AC23

GND

BDQ96

C

T

C

T

BDQ96

VREF2_4/BDQ96

AE24

AE25

AB22

AE26

AA22

AD25

AD26

AC24

GND

4

8

-

VREF1_4/BDQ96

C

CFG1

CFG0

PROGRAMN

CCLK

INITN

DONE

GNDIO4

PR90B

PR90A

PR89B

PR89A

VCCIO8

PR88B

PR88A

AC25

AE27

AC26

AE28

VCCIO

AD27

AD28

8

WRITEN

CS1N

C

T

C

T

CSN

D0/SPIFASTN

D1

D2

C

T

4-117

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AB24

GND

AB23

AB25

AB26

AC27

VCCIO

AB27

AD29

AD30

AA25

GND

AA23

AC29

AC30

AA26

VCCIO

AA24

AB29

AB30

GND

Y23

Ball/Pad Function

PR87B

Bank

8

-

Dual Function

Differential

D3

C

GNDIO4

PR87A

8

3

-

D4

D5

D6

D7

T

C

T

PR86B

PR86A

PR85B

C

VCCIO8

PR85A

DI/CSSPI0N

DOUT/CSON

BUSY/SISPI

RDQ80

T

C

T

PR84B

PR84A

PR83B

C

GNDIO3

PR83A

3

-

RDQ80

T

PR82B

C (LVDS)*

T (LVDS)*

C

PR82A

PR81B

VCCIO3

PR81A

RDQ80

RDQS80

T

PR80B

C (LVDS)*

T (LVDS)*

PR80A

GNDIO3

PR79B

3

-

RDQ80

C

Y25

PR79A

T

AA27

AA28

VCCIO

Y24

PR78B

C (LVDS)*

T (LVDS)*

PR78A

VCCIO3

PR77B

RLM0_GPLLC_FB_A/RDQ80

RLM0_GPLLT_FB_A/RDQ80

RLM0_GPLLC_IN_A**/RDQ80

RLM0_GPLLT_IN_A**/RDQ80

C

Y26

PR77A

T

AA29

AA30

R22

PR76B

C (LVDS)*

T (LVDS)*

PR76A

RLM0_PLLCAP

PR74B

W23

RLM0_GDLLC_FB_A/RDQ71

RLM0_GDLLT_FB_A/RDQ71

C

T

W25

PR74A

GND

Y27

GNDIO3

PR73B

3

-

RLM0_GDLLC_IN_A**/RDQ71

RLM0_GDLLT_IN_A**/RDQ71

RDQ71

C (LVDS)*

Y28

PR73A

T (LVDS)*

W24

PR72B

C

T

W26

PR72A

RDQ71

VCCIO

Y29

VCCIO3

PR71B

RDQ71

RDQS71

RDQ71

C (LVDS)*

T (LVDS)*

C

Y30

PR71A

V25

PR70B

GND

GNDIO3

4-118

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

V23

Ball/Pad Function

PR70A

PR69B

PR69A

PR68B

VCCIO3

PR68A

PR67B

PR67A

PR66B

GNDIO3

PR66A

PR65B

PR65A

PR64B

VCCIO3

PR64A

PR63B

PR63A

GNDIO3

PR62B

PR62A

PR61B

PR61A

VCCIO3

PR60B

PR60A

PR59B

PR59A

PR57B

PR57A

GNDIO2

PR56B

PR56A

PR55B

PR55A

VCCIO2

PR54B

PR54A

PR53B

GNDIO2

PR53A

PR52B

PR52A

Bank

3

-

Dual Function

RDQ71

Differential

T

W27

W28

V26

RDQ71

C (LVDS)*

T (LVDS)*

C

RDQ71

VCCIO

V24

RDQ71

RDQ63

T

W29

W30

U25

C (LVDS)*

T (LVDS)*

C

GND

U23

3

-

RDQ63

T

V29

C (LVDS)*

T (LVDS)*

C

V30

U26

VCCIO

U24

RDQ63

RDQS63

T

U27

C (LVDS)*

T (LVDS)*

U28

GND

T23

3

2

-

RDQ63

C

T25

T

U29

C (LVDS)*

T (LVDS)*

U30

VCCIO

T24

VREF2_3/RDQ63

VREF1_3/RDQ63

PCLKC3_0/RDQ63

PCLKT3_0/RDQ63

PCLKC2_0/RDQ54

PCLKT2_0/RDQ54

C

T26

T

T27

C (LVDS)*

T28

T (LVDS)*

R24

C

T

R26

GND

T29

2

-

RDQ54

C (LVDS)*

T30

T (LVDS)*

R23

C

T

R25

VCCIO

R27

RDQ54

RDQS54

RDQ54

C (LVDS)*

T (LVDS)*

C

R28

P26

GND

P24

2

RDQ54

T

R29

C (LVDS)*

T (LVDS)*

R30

4-119

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

P25

Ball/Pad Function

PR51B

VCCIO2

PR51A

PR50B

PR50A

GNDIO2

VCCIO2

PR39B

PR39A

PR38B

PR38A

VCCIO2

PR37B

PR37A

PR36B

GNDIO2

PR36A

PR35B

PR35A

PR34B

VCCIO2

PR34A

PR33B

PR33A

PR32B

GNDIO2

PR32A

PR31B

PR31A

PR30B

VCCIO2

PR30A

PR29B

PR29A

GNDIO2

PR28B

PR28A

PR27B

PR27A

VCCIO2

PR26B

PR26A

PR25B

Bank

2

-

Dual Function

Differential

RDQ54

C

VCCIO

P23

RDQ54

T

P27

C (LVDS)*

T (LVDS)*

P28

GND

VCCIO

N24

2

-

RUM0_SPLLC_FB_A/RDQ37

RUM0_SPLLT_FB_A/RDQ37

RUM0_SPLLC_IN_A/RDQ37

RUM0_SPLLT_IN_A/RDQ37

C

T

C

T

N26

N23

N25

VCCIO

P29

RDQ37

RDQS37

RDQ37

C (LVDS)*

T (LVDS)*

C

P30

M26

GND

M24

N29

2

-

RDQ37

T

C (LVDS)*

T (LVDS)*

C

N30

M25

VCCIO

M23

M27

M28

L26

RDQ37

RDQ29

T

C (LVDS)*

T (LVDS)*

C

GND

L24

2

-

RDQ29

T

M29

M30

L25

C (LVDS)*

T (LVDS)*

C

VCCIO

L23

RDQ29

RDQS29

T

L27

C (LVDS)*

T (LVDS)*

L28

GND

K24

2

RDQ29

C

K26

T

L29

C (LVDS)*

T (LVDS)*

L30

VCCIO

K23

RDQ29

C

T

K25

K27

C (LVDS)*

4-120

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

K28

Ball/Pad Function

PR25A

PR24B

PR24A

GNDIO2

PR23B

PR23A

PR22B

PR22A

VCCIO2

PR21B

PR21A

PR20B

GNDIO2

PR20A

PR19B

PR19A

PR18B

VCCIO2

PR18A

PR15B

GNDIO2

PR15A

PR14B

PR14A

VCCIO2

GNDIO2

PR6B

Bank

2

-

Dual Function

RDQ29

Differential

T (LVDS)*

J24

RDQ21

C

T

J26

RDQ21

GND

K29

2

99

2

-

RDQ21

C (LVDS)*

K30

T (LVDS)*

J23

C

T

J25

VCCIO

J27

RDQ21

RDQS21

RDQ21

C (LVDS)*

T (LVDS)*

C

J28

H26

GND

H24

2

-

RDQ21

T

J29

C (LVDS)*

T (LVDS)*

C

J30

H25

VCCIO

H23

RDQ21

T

G27

GND

H27

RUM1_SPLLC_FB_A/RDQ12

C

2

-

RUM1_SPLLT_FB_A/RDQ12

RUM1_SPLLC_IN_A/RDQ12

RUM1_SPLLT_IN_A/RDQ12

T

G29

G28

VCCIO

GND

G26

G25

G30

F30

C (LVDS)*

T (LVDS)*

2

-

C (LVDS)*

PR6A

T (LVDS)*

PR5B

C

T

PR5A

VCCIO

F26

VCCIO2

PR4B

C (LVDS)*

T (LVDS)*

C

F27

PR4A

F29

PR3B

GND

F28

GNDIO2

PR3A

2

1

-

T

H29

PR2B

VREF2_2

VREF1_2

C (LVDS)*

T (LVDS)*

H30

PR2A

VCCIO

B26

VCCIO2

PT100B

PT100A

GNDIO1

PT99B

VREF2_1

VREF1_1

C

T

A26

GND

C25

1

C

4-121

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

D25

Ball/Pad Function

PT99A

PT98B

PT98A

VCCIO1

PT97B

PT97A

PT96B

PT96A

GNDIO1

PT95B

PT95A

PT94B

PT94A

VCCIO1

PT93B

PT93A

PT92B

PT92A

PT91B

GNDIO1

PT91A

PT90B

PT90A

PT89B

VCCIO1

PT89A

PT88B

PT88A

PT87B

PT87A

GNDIO1

VCCIO1

PT80B

PT80A

VCCIO1

PT79B

PT79A

PT78B

PT78A

GNDIO1

PT77B

PT77A

PT76B

Bank

1

-

Dual Function

Differential

T

C

T

J22

J21

VCCIO

B25

C

T

C

T

A25

E24

F24

GND

F23

1

-

C

T

C

T

H22

D24

C24

VCCIO

E23

C

T

G23

B24

C

T

A24

C27

C

GND

D27

1

-

T

C

T

C26

D26

A27

C

VCCIO

B27

T

C

T

C

T

A28

B28

A29

B29

GND

VCCIO

H21

1

-

C

T

F22

VCCIO

B23

C

T

C

T

A23

G24

E22

GND

D22

1

C

T

C22

G22

C

4-122

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

E21

Ball/Pad Function

PT76A

VCCIO1

PT75B

PT75A

PT74B

PT74A

PT73B

GNDIO1

PT73A

PT72B

PT72A

PT71B

VCCIO1

PT71A

PT70B

PT70A

PT69B

PT69A

PT68B

GNDIO1

PT68A

PT67B

VCCIO1

PT67A

PT66B

PT66A

PT65B

PT65A

PT64B

PT64A

GNDIO1

PT63B

PT63A

PT62B

PT62A

VCCIO1

PT61B

PT61A

PT60B

PT60A

GNDIO1

PT59B

PT59A

Bank

1

-

Dual Function

Differential

T

VCCIO

B22

C

T

A22

H20

C

T

F21

F20

C

GND

H19

1

-

T

C

T

D21

C21

E20

C

VCCIO

G21

B21

T

C

T

A21

F19

C

T

G20

E19

C

GND

G19

D20

1

-

T

C

VCCIO

C20

T

C

T

C

T

C

T

B20

A20

F18

H18

D19

C19

GND

G18

E18

1

-

C

T

C

T

H17

F17

VCCIO

G17

E17

C

T

C

T

B19

A19

GND

D17

1

C

T

B18

4-123

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

C17

Ball/Pad Function

PT58B

PT58A

VCCIO1

PT57B

PT57A

XRES

Bank

1

0

-

Dual Function

Differential

C

T

A18

VCCIO

H16

PCLKC1_0

PCLKT1_0

C

T

F16

K16

E16

PT55B

GNDIO0

PT55A

PT54B

PT54A

PT53B

VCCIO0

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

GNDIO0

PT50A

PT49B

VCCIO0

PT49A

PT48B

PT48A

PT47B

PT47A

PT46B

PT46A

GNDIO0

PT45B

PT45A

PT44B

PT44A

VCCIO0

PT43B

PT43A

PT42B

PT42A

GNDIO0

PT41B

PT41A

PCLKC0_0

PCLKT0_0

C

GND

G16

B17

0

-

T

C

T

A17

J15

C

VCCIO

J16

T

C

T

C16

D16

F15

C

T

H15

E15

C

GND

G15

C15

0

-

T

C

VCCIO

D15

T

C

T

C

T

C

T

B16

A16

E14

G14

B15

A15

GND

H14

0

-

C

T

C

T

F14

D14

C14

VCCIO

G13

E13

C

T

C

T

B14

A14

GND

H13

0

C

T

F13

4-124

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

G12

E12

Ball/Pad Function

PT40B

PT40A

VCCIO0

PT39B

PT39A

PT38B

PT38A

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

PT31B

VCCIO0

PT31A

PT30B

PT30A

PT29B

PT29A

GNDIO0

VCCIO0

PT16B

PT16A

PT15B

PT15A

PT14B

GNDIO0

PT14A

PT13B

VCCIO0

PT13A

PT12B

PT12A

Bank

0

-

Dual Function

Differential

C

T

VCCIO

B13

C

T

A13

H12

F12

C

T

C12

GND

D12

B12

C

0

-

T

C

T

A12

E11

C

VCCIO

G11

F11

T

C

T

H11

C11

D11

B11

C

T

C

GND

A11

0

-

T

E10

C

VCCIO

G10

F10

T

C

T

C

T

H10

D10

C10

GND

VCCIO

A7

0

-

C

T

B7

A6

C

T

B6

C7

C

GND

D7

0

T

D8

C

VCCIO

E7

T

C

T

C6

D6

4-125

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

C5

Ball/Pad Function

PT11B

PT11A

PT10B

PT10A

GNDIO0

PT9B

PT9A

PT8B

PT8A

VCCIO0

PT7B

PT7A

PT6B

PT6A

GNDIO0

PT5B

PT5A

PT4B

PT4A

VCCIO0

PT3B

PT3A

PT2B

PT2A

VCC

Bank

0

-

Dual Function

Differential

C

T

C

T

D5

E9

G9

GND

B10

A10

D9

0

-

C

T

C

T

C9

VCCIO

F9

C

T

C

T

H9

B9

A9

GND

E8

0

-

C

T

C

T

G8

A8

B8

VCCIO

F8

C

T

C

T

F7

J10

VREF2_0

VREF1_0

J9

AA11

AA20

K11

K21

K22

L11

L12

L13

L18

L19

L20

M11

M20

N11

N20

V11

V20

W11

W20

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

4-126

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

Y10

Ball/Pad Function

VCC

Bank

-

Dual Function

Differential

Y11

VCC

-

Y12

VCC

-

Y13

VCC

-

Y18

VCC

-

Y19

VCC

-

Y20

VCC

-

J13

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

J14

K12

K13

K14

K15

J17

J18

J20

K17

K18

K20

L21

M21

M22

N21

N22

R21

U21

U22

V21

V22

W21

Y22

AA16

AA17

AA18

AA19

AB17

AB18

AA12

AA13

AA14

AB12

AB13

AB14

4-127

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

U10

U9

Ball/Pad Function

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

Bank

Dual Function

Differential

6

7

8

-

V10

W10

W9

Y9

L10

L9

M10

N10

P10

R10

AA21

Y21

AA15

AB11

AB19

AB20

J11

-

J12

-

J19

-

K19

L22

-

M9

-

N9

-

P21

P9

-

T10

-

T21

-

V9

-

W22

A1

-

A30

AC28

AC3

AH13

AH18

AH23

AH28

AH3

AH8

AK1

AK30

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-128

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

C13

C18

C23

C28

C3

Ball/Pad Function

GND

Bank

Dual Function

Differential

-

C8

H28

H3

L14

L15

L16

L17

M12

M13

M14

M15

M16

M17

M18

M19

N12

N13

N14

N15

N16

N17

N18

N19

N28

N3

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

R11

R12

R13

4-129

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

R14

R15

R16

R17

R18

R19

R20

T11

Ball/Pad Function

GND

Bank

Dual Function

Differential

-

T12

T13

T14

T15

T16

T17

T18

T19

T20

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V12

V13

V14

V15

V16

V17

V18

V19

V28

V3

W12

W13

W14

W15

W16

W17

4-130

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

W18

W19

Y14

Ball/Pad Function

GND

NC

Bank

Dual Function

Differential

-

Y15

Y16

Y17

A2

A3

NC

A4

NC

A5

NC

AB28

AC4

NC

AD23

AE1

NC

AE2

NC

AE29

AE3

NC

AE30

AE4

NC

AE5

NC

AE6

NC

AF1

NC

AF2

NC

AF23

AF26

AF27

AF28

AF29

AF3

NC

AF30

AF4

NC

AF5

NC

AG1

AG13

AG16

AG18

AG2

AG26

AG27

AG28

AG29

AG3

AG30

NC

4-131

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

AG4

AG8

AH1

AH16

AH2

AH26

AH27

AH29

AH30

AH4

AJ1

Ball/Pad Function

NC

Bank

Dual Function

Differential

-

NC

AJ2

NC

AJ27

AJ28

AJ29

AJ3

NC

AJ30

AK2

AK27

AK28

AK29

AK3

B1

NC

B2

NC

B3

NC

B30

B4

NC

B5

NC

C1

NC

C2

NC

C29

C30

C4

NC

D13

D18

D23

D28

D29

D3

NC

D30

D4

NC

E25

E26

NC

4-132

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2-70E/SE

Ball Number

E27

E28

E29

E3

Ball/Pad Function

Bank

Dual Function

Differential

NC

-

NC

E30

E4

NC

E5

NC

E6

NC

F25

F5

NC

F6

NC

G6

NC

G7

NC

K10

K9

NC

N27

N4

NC

R1

NC

R2

NC

V27

V4

NC

P22

P8

VCCPLL

T22

Y7

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-133

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Number

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

T

Bank

7

-

Function

Differential

T (LVDS)*

C(LVDS)*

T

A2

B2

PL2A

PL2B

LDQ6

PL2A

PL2B

LDQ6

D3

PL3A

LDQ6

C2

PL3B

C

PL3B

LDQ6

C

E4

PL4A

T (LVDS)*

PL4A

LDQ6

T (LVDS)*

VCCIO

E5

VCCIO7

PL4B

VCCIO7

PL4B

LDQ6

LDQS6

C (LVDS)*

LDQ6

LDQS6

C(LVDS)*

B1

PL5A

T

C

PL5A

T

C

C1

PL5B

D2

PL6A

T (LVDS)*

PL6A

T (LVDS)*

GNDIO

D1

GNDIO7

PL6B

GNDIO7

PL6B

7

-

LDQ6

C (LVDS)*

7

-

LDQ6

C(LVDS)*

E1

PL7A

T

PL7A

T

F1

PL7B

C

PL7B

C

VCCIO

F3

VCCIO7

PL8A

VCCIO7

PL8A

LDQ6

T (LVDS)*

LDQ6

T (LVDS)*

F2

PL8B

LDQ6

C (LVDS)*

PL8B

LDQ6

C(LVDS)*

F6

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

F5

PL9B

C

PL9B

C

GNDIO

G4

GNDIO7

PL11A

PL11B

PL12A

PL12B

PL13A

VCCIO7

PL13B

PL14A

PL14B

GNDIO7

VCCIO7

PL24A

PL24B

PL25A

GNDIO7

PL25B

PL27A

PL27B

PL28A

PL28B

VCCIO6

PL31A

GNDIO6

PL31B

PL32A

PL32B

VCCIO6

GNDIO6

PL42A

GNDIO7

PL11A

PL11B

PL12A

PL12B

PL13A

VCCIO7

PL13B

PL14A

PL14B

GNDIO7

VCCIO7

PL34A

PL34B

PL35A

GNDIO7

PL35B

PL37A

PL37B

PL38A

PL38B

VCCIO6

PL41A

GNDIO6

PL41B

PL42A

PL42B

VCCIO6

GNDIO6

PL57A

7

-

LUM0_SPLLT_IN_A

LUM0_SPLLC_IN_A

LUM0_SPLLT_FB_A

LUM0_SPLLC_FB_A

T (LVDS)*

C (LVDS)*

T

7

-

LUM0_SPLLT_IN_A/LDQ15

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

LDQ15

T (LVDS)*

C(LVDS)*

T

G3

G1

G2

C

H1

T (LVDS)*

VCCIO

J1

C (LVDS)*

LDQ15

C(LVDS)*

H2

T

H3

C

GNDIO

VCCIO

G6

7

-

7

-

LDQ22

T (LVDS)*

C (LVDS)*

T

LDQ32

T (LVDS)*

C(LVDS)*

T

H6

J2

PCLKT7_0/LDQ22

PCLKT7_0/LDQ32

GNDIO

K1

7

6

-

PCLKC7_0/LDQ22

PCLKT6_0

C

7

6

-

PCLKC7_0/LDQ32

PCLKT6_0

C

H4

T (LVDS)*

H5

PCLKC6_0

VREF2_6

C (LVDS)*

PCLKC6_0

VREF2_6

C(LVDS)*

J4

T

K4

VREF1_6

C

VREF1_6

C

VCCIO

J6

LLM1_SPLLT_IN_A

T (LVDS)*

LLM2_SPLLT_IN_A

T (LVDS)*

GNDIO

J5

6

-

LLM1_SPLLC_IN_A

LLM1_SPLLT_FB_A

LLM1_SPLLC_FB_A

C (LVDS)*

6

-

LLM2_SPLLC_IN_A

LLM2_SPLLT_FB_A

LLM2_SPLLC_FB_A

C(LVDS)*

K3

T

K2

C

VCCIO

GNDIO

L1

6

LLM0_GPLLT_IN_A

T (LVDS)*

6

LLM0_GPLLT_IN_A**/LDQS57*** T (LVDS)*

4-134

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Number

Bank

-

Dual Function

Differential

Bank

-

Function

Differential

GNDIO

L2

GNDIO6

PL42B

PL43A

PL43B

VCCIO6

PL44A

PL44B

PL45A

PL45B

GNDIO6

LLM0_PLLCAP

VCCIO6

GNDIO6

TCK

GNDIO6

PL57B

PL58A

PL58B

VCCIO6

PL59A

PL59B

PL60A

PL60B

GNDIO6

LLM0_PLLCAP

VCCIO6

GNDIO6

TCK

6

-

LLM0_GPLLC_IN_A

LLM0_GPLLT_FB_A

LLM0_GPLLC_FB_A

C (LVDS)*

6

-

LLM0_GPLLC_IN_A**/LDQ57

LLM0_GPLLT_FB_A/LDQ57

LLM0_GPLLC_FB_A/LDQ57

C(LVDS)*

L3

T

L4

C

VCCIO

M1

LLM0_GDLLT_IN_A

LLM0_GDLLC_IN_A

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T (LVDS)*

LLM0_GDLLT_IN_A**/LDQ57

LLM0_GDLLC_IN_A**/LDQ57

LLM0_GDLLT_FB_A/LDQ57

LLM0_GDLLC_FB_A/LDQ57

T (LVDS)*

N1

C (LVDS)*

C(LVDS)*

N2

T

N3

C

GNDIO

M4

6

-

6

-

VCCIO

GNDIO

K6

-

L5

TDI

-

TDI

-

N4

TMS

-

TMS

-

N6

TDO

-

TDO

-

K7

VCCJ

-

VCCJ

-

M5

PB2A

5

-

BDQ6

T

C

T

C

T

PB2A

5

-

BDQ6

T

C

T

C

T

N5

PB2B

L6

PB3A

M6

PB3B

P3

PB4A

VCCIO

P4

VCCIO5

PB4B

VCCIO5

PB4B

BDQ6

BDQS6

C

T

C

T

BDQ6

BDQS6

C

T

C

T

P2

PB5A

P1

PB5B

R1

PB6A

GNDIO

R2

GNDIO5

PB6B

GNDIO5

PB6B

5

-

BDQ6

C

T

C

T

5

-

BDQ6

C

T

C

T

R3

PB7A

T2

PB7B

R4

PB8A

VCCIO

T3

VCCIO5

PB8B

VCCIO5

PB8B

BDQ6

C

T

BDQ6

C

T

T4

PB10A

GNDIO5

PB10B

VCCIO5

GNDIO5

PB16A

PB16B

PB17A

PB17B

VCCIO5

GNDIO5

PB22A

VCCIO4

PB22B

PB10A

GNDIO5

PB10B

VCCIO5

GNDIO5

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

PB40A

VCCIO4

PB40B

GNDIO

T5

5

-

BDQ6

C

5

-

BDQ6

C

VCCIO

GNDIO

T6

5

-

VREF2_5/BDQ15

VREF1_5/BDQ15

PCLKT5_0/BDQ15

PCLKC5_0/BDQ15

T

C

T

5

-

VREF2_5/BDQ33

VREF1_5/BDQ33

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

T

C

T

R6

P6

P7

C

VCCIO

GNDIO

T7

4

PCLKT4_0/BDQ24

PCLKC4_0/BDQ24

T

4

PCLKT4_0/BDQ42

PCLKC4_0/BDQ42

T

VCCIO

T8

C

4-135

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Number

Bank

4

-

Dual Function

Differential

Bank

4

-

Function

Differential

L7

L8

PB23A

PB23B

GNDIO4

VCCIO4

GNDIO4

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

VCCIO4

PB32A

PB32B

GNDIO4

PB33A

PB33B

PB34A

PB34B

VCCIO4

GNDIO4

PB47A

PB47B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

PB54A

PB54B

PB55A

PB55B

GNDIO4

CFG2

VREF2_4/BDQ24

VREF1_4/BDQ24

T

PB41A

PB41B

GNDIO4

VCCIO4

GNDIO4

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

VCCIO4

GNDIO4

PB65A

PB65B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

PB72A

PB72B

PB73A

PB73B

GNDIO4

CFG2

VREF2_4/BDQ42

VREF1_4/BDQ42

T

C

GNDIO

VCCIO

GNDIO

P8

4

-

4

-

4

-

BDQ33

T

C

T

4

-

BDQ51

T

C

T

N8

R7

R8

C

T

C

T

N7

M8

C

VCCIO

R9

BDQ33

T

BDQ51

T

T9

C

GNDIO

T10

4

-

BDQS33

BDQ33

T

C

T

4

-

BDQS51

BDQ51

T

C

T

R10

N9

P10

C

VCCIO

GNDIO

L9

4

-

BDQ51

T

C

T

4

-

BDQ69

T

C

T

M9

T11

R11

C

VCCIO

T12

BDQ51

T

BDQ69

T

T13

C

GNDIO

P11

4

-

BDQS51

BDQ51

T

C

T

4

-

BDQS69

BDQ69

T

C

T

N10

T14

R13

C

T

C

T

R15

R16

C

VCCIO

R14

BDQ51

T

C

T

BDQ69

T

C

T

P15

P16

P14

C

GNDIO

L11

8

-

8

-

L10

CFG1

P13

CFG0

N12

PROGRAMN

CCLK

PROGRAMN

CCLK

N11

M11

N13

INITN

DONE

GNDIO

GNDIO8

4-136

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Number

Bank

8

-

Dual Function

Differential

Bank

8

-

Function

WRITEN

CS1N

Differential

M12

M13

PR53B

PR53A

PR52B

PR52A

VCCIO8

PR51B

PR51A

PR50B

GNDIO8

PR50A

PR49B

PR49A

PR48B

VCCIO8

PR48A

PR47B

PR47A

RLM0_PLLCAP

PR45B

GNDIO3

PR45A

PR44B

PR44A

PR43B

VCCIO3

PR43A

PR42B

PR42A

GNDIO3

VCCIO3

PR32B

VCCIO3

PR32A

PR31B

PR31A

GNDIO3

VCCIO3

PR28B

PR28A

PR27B

PR27A

PR25B

PR25A

GNDIO2

PR24B

PR24A

VCCIO2

GNDIO2

PR14B

WRITEN

CS1N

C

T

C

T

PR68B

PR68A

PR67B

PR67A

VCCIO8

PR66B

PR66A

PR65B

GNDIO8

PR65A

PR64B

PR64A

PR63B

VCCIO8

PR63A

PR62B

PR62A

RLM0_PLLCAP

PR60B

GNDIO3

PR60A

PR59B

PR59A

PR58B

VCCIO3

PR58A

PR57B

PR57A

GNDIO3

VCCIO3

PR42B

VCCIO3

PR42A

PR41B

PR41A

GNDIO3

VCCIO3

PR38B

PR38A

PR37B

PR37A

PR35B

PR35A

GNDIO2

PR34B

PR34A

VCCIO2

GNDIO2

PR14B

C

T

C

T

N14

CSN

N15

D0/SPIFASTN

VCCIO

N16

D1

D2

D3

C

T

D1

D2

D3

C

T

M16

L12

C

GNDIO

L13

8

3

-

D4

D5

D6

D7

T

C

T

8

3

-

D4

D5

D6

D7

T

C

T

L16

K16

L14

C

VCCIO

L15

DI/CSSPI0N

DOUT/CSON/CSSPI1N

BUSY/SISPI

T

C

T

DI/CSSPI0N

DOUT/CSON/CSSPI1N

BUSY/SISPI

T

C

T

K13

K14

K11

K15

RLM0_GDLLC_FB_A

C

RLM0_GDLLC_FB_A/RDQ57

C

GNDIO

J16

3

-

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A

RLM0_GDLLT_IN_A

RLM0_GPLLC_IN_A

T

3

-

RLM0_GDLLT_FB_A/RDQ57

RLM0_GDLLC_IN_A**/RDQ57

RLM0_GDLLT_IN_A**/RDQ57

RLM0_GPLLC_IN_A**/RDQ57

T

H16

C (LVDS)*

T (LVDS)*

C

C(LVDS)*

T (LVDS)*

C

J15

J14

VCCIO

J13

RLM0_GPLLT_IN_A

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

T

RLM0_GPLLT_IN_A**/RDQ57

RLM0_GPLLC_FB_A/RDQ57

T

H13

C (LVDS)*

T (LVDS)*

C(LVDS)*

H12

RLM0_GPLLT_FB_A/RDQS57*** T (LVDS)*

GNDIO

VCCIO

G16

3

-

3

-

RLM1_SPLLC_FB_A

C

RLM2_SPLLC_FB_A

C

VCCIO

H15

RLM1_SPLLT_FB_A

RLM1_SPLLC_IN_A

RLM1_SPLLT_IN_A

T

RLM2_SPLLT_FB_A

RLM2_SPLLC_IN_A

RLM2_SPLLT_IN_A

T

E16

C (LVDS)*

T (LVDS)*

C(LVDS)*

T (LVDS)*

F15

GNDIO

VCCIO

F16

3

2

-

3

2

-

VREF2_3

VREF1_3

C

VREF2_3

VREF1_3

C

G15

T

J11

PCLKC3_0

C (LVDS)*

PCLKC3_0

C(LVDS)*

J12

PCLKT3_0

T (LVDS)*

PCLKT3_0

T (LVDS)*

G14

PCLKC2_0/RDQ22

PCLKT2_0/RDQ22

C

T

PCLKC2_0/RDQ32

PCLKT2_0/RDQ32

C

T

G13

GNDIO

F14

2

-

RDQ22

C (LVDS)*

T (LVDS)*

2

-

RDQ32

C(LVDS)*

T (LVDS)*

F13

VCCIO

GNDIO

H11

2

C

2

RDQ15

C

4-137

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Number

Bank

2

Dual Function

Differential

T

Bank

2

Function

RDQ15

Differential

T

G11

E13

F12

VCCIO

F11

E12

D16

D15

C16

GNDIO

B16

VCCIO

F4

PR14A

PR13B

PR14A

PR13B

2

C (LVDS)*

T (LVDS)*

2

C(LVDS)*

T (LVDS)*

PR13A

2

PR13A

2

VCCIO2

2

VCCIO2

2

PR12B

2

RUM0_SPLLC_FB_A

RUM0_SPLLT_FB_A

RUM0_SPLLC_IN_A

RUM0_SPLLT_IN_A

VREF2_2

C

PR12B

2

RUM0_SPLLC_FB_A/RDQ15

RUM0_SPLLT_FB_A/RDQ15

RUM0_SPLLC_IN_A/RDQ15

RUM0_SPLLT_IN_A/RDQ15

VREF2_2

C

PR12A

2

T

PR12A

2

T

PR11B

2

C (LVDS)*

T (LVDS)*

C

PR11B

2

C(LVDS)*

T (LVDS)*

C

PR11A

2

PR11A

2

PR9B

2

PR9B

2

GNDIO2

-

GNDIO2

-

PR9A

2

VREF1_2

T

PR9A

2

VREF1_2

T

VCCIO2

2

VCCIO2

2

XRES

-

XRES

-

C15

A14

B15

B14

C12

A11

A12

B11

C11

B10

C10

A10

C14

B13

C13

A13

B9

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

T

C

T

C

T

C

T

C

T

C

T

C

T

URC_SQ_VCCAUX33 12

D8

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

12

C

T

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

12

C

T

D9

C9

A5

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

T

C

T

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

T

C

T

C5

B5

C4

A8

C8

B8

C

T

C

T

C7

B7

A6

A7

C6

B4

C

T

C

T

B3

A4

C3

4-138

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Dual

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Differential

GNDIO

VCCIO

GNDIO

VCCIO

G10

G7

GNDIO1

VCCIO1

GNDIO0

VCCIO0

VCCPLL

VCC

GNDIO1

VCCIO1

GNDIO0

VCCIO0

VCCPLL

VCC

1

-

1

-

0

-

0

-

G9

VCC

-

VCC

-

H7

VCC

-

VCC

-

J10

VCC

-

VCC

-

K10

VCC

-

VCC

-

K8

VCC

-

VCC

-

E7

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

0

1

2

3

4

5

6

7

8

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

0

1

2

3

4

5

6

7

8

-

VCCIO

E10

VCCIO

E14

G12

VCCIO

K12

M14

VCCIO

M10

P12

VCCIO

M7

P5

VCCIO

K5

M3

VCCIO

E3

G5

VCCIO

T15

VCCIO

G8

H10

J7

-

K9

-

A1

-

A15

GND

-

GND

-

A16

GND

-

GND

-

A3

GND

-

GND

-

A9

GND

-

GND

-

B12

GND

-

GND

-

B6

GND

-

GND

-

E15

GND

-

GND

-

E2

GND

-

GND

-

H14

GND

-

GND

-

4-139

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Dual

Function

Bank

Dual Function

Differential

Bank

Differential

H8

H9

GND

NC

-

GND

NC

-

J3

J8

J9

M15

M2

P9

R12

R5

T1

T16

D10

D11

D12

D13

D14

D4

NC

D5

NC

D6

NC

D7

NC

E11

E6

NC

E8

NC

E9

NC

F10

F7

NC

F8

NC

F9

NC

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-140

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

T (LVDS)*

C (LVDS)*

T

Bank

7

-

Dual Function

Differential

T (LVDS)*

C (LVDS)*

T

D1

E1

PL2A

PL2B

7

-

LDQ6

PL2A

PL2B

LDQ6

F1

PL3A

F2

PL3B

C

PL3B

C

F5

PL4A

T (LVDS)*

PL4A

T (LVDS)*

VCCIO

G6

VCCIO7

PL4B

VCCIO7

PL4B

LDQ6

LDQS6

C (LVDS)*

LDQ6

LDQS6

C (LVDS)*

F4

PL5A

T

C

PL5A

T

C

F3

PL5B

G1

PL6A

T (LVDS)*

PL6A

T (LVDS)*

GNDIO

G2

GNDIO7

PL6B

GNDIO7

PL6B

7

-

LDQ6

C (LVDS)*

7

-

LDQ6

C (LVDS)*

H1

PL7A

T

PL7A

T

H2

PL7B

C

PL7B

C

VCCIO

H7

VCCIO7

PL8A

VCCIO7

PL8A

LDQ6

T (LVDS)*

LDQ6

T (LVDS)*

H6

PL8B

LDQ6

C (LVDS)*

PL8B

LDQ6

C (LVDS)*

G3

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

H3

PL9B

C

PL9B

C

GNDIO

H5

GNDIO7

PL11A

PL11B

PL12A

PL12B

PL13A

VCCIO7

PL13B

PL14A

PL14B

GNDIO7

VCCIO7

PL18A

PL18B

PL19A

PL19B

VCCIO7

PL20A

PL20B

PL21A

PL21B

GNDIO7

PL22A

PL22B

PL23A

VCCIO7

PL23B

PL24A

PL24B

PL25A

GNDIO7

PL11A

PL11B

PL12A

PL12B

PL13A

VCCIO7

PL13B

PL14A

PL14B

GNDIO7

VCCIO7

PL28A

PL28B

PL29A

PL29B

VCCIO7

PL30A

PL30B

PL31A

PL31B

GNDIO7

PL32A

PL32B

PL33A

VCCIO7

PL33B

PL34A

PL34B

PL35A

7

-

LUM0_SPLLT_IN_A

LUM0_SPLLC_IN_A

LUM0_SPLLT_FB_A

LUM0_SPLLC_FB_A

T (LVDS)*

C (LVDS)*

T

7

-

LUM0_SPLLT_IN_A/LDQ15

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

LDQ15

T (LVDS)*

C (LVDS)*

T

H4

J1

J2

C

J3

T (LVDS)*

VCCIO

J4

C (LVDS)*

LDQ15

C (LVDS)*

J7

T

J6

C

GNDIO

VCCIO

K1

7

-

7

-

LUM1_SPLLT_IN_A/LDQ22 T (LVDS)*

LUM1_SPLLC_IN_A/LDQ22 C (LVDS)*

LUM1_SPLLT_IN_A/LDQ32

LUM1_SPLLC_IN_A/LDQ32

LUM1_SPLLT_FB_A/LDQ32

LUM1_SPLLC_FB_A/LDQ32

T (LVDS)*

K2

C (LVDS)*

J5

LUM1_SPLLT_FB_A/LDQ22

LUM1_SPLLC_FB_A/LDQ22

T

K5

C

VCCIO

K7

LDQ22

T (LVDS)*

LDQ32

T (LVDS)*

K6

C (LVDS)*

L6

T

L7

C

GNDIO

L1

7

LDQS22

LDQ22

T (LVDS)*

C (LVDS)*

T

7

LDQS32

LDQ32

T (LVDS)*

C (LVDS)*

T

L2

M7

VCCIO

L5

LDQ22

C

LDQ32

C

L3

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

L4

LDQ22

LDQ32

M1

PCLKT7_0/LDQ22

PCLKT7_0/LDQ32

4-141

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

-

Dual Function

Differential

GNDIO

M2

GNDIO7

PL25B

-

GNDIO7

PL35B

PL37A

PL37B

PL38A

PL38B

VCCIO6

PL41A

GNDIO6

PL41B

PL42A

PL42B

VCCIO6

GNDIO6

PL48A

PL48B

PL49A

VCCIO6

PL49B

PL50A

PL50B

PL51A

GNDIO6

PL51B

PL57A

GNDIO6

PL57B

PL58A

PL58B

VCCIO6

PL59A

PL59B

PL60A

PL60B

GNDIO6

LLM0_PLLCAP

PL62A

PL62B

PL63A

PL63B

VCCIO6

PL64A

PL64B

NC

7

6

-

PCLKC7_0/LDQ22

PCLKT6_0

C

7

6

-

PCLKC7_0/LDQ32

PCLKT6_0

C

M6

PL27A

T (LVDS)*

M5

PL27B

PCLKC6_0

VREF2_6

C (LVDS)*

PCLKC6_0

VREF2_6

C (LVDS)*

M3

PL28A

T

M4

PL28B

VREF1_6

C

VREF1_6

C

VCCIO

N7

VCCIO6

PL31A

LLM1_SPLLT_IN_A

T (LVDS)*

LLM2_SPLLT_IN_A

T (LVDS)*

GNDIO

N6

GNDIO6

PL31B

6

-

LLM1_SPLLC_IN_A

LLM1_SPLLT_FB_A

LLM1_SPLLC_FB_A

C (LVDS)*

6

-

LLM2_SPLLC_IN_A

LLM2_SPLLT_FB_A

LLM2_SPLLC_FB_A

C (LVDS)*

N1

PL32A

T

N2

PL32B

C

VCCIO

GNDIO

P6

VCCIO6

GNDIO6

PL38A

6

-

LDQS38****

LDQ38

T (LVDS)*

C (LVDS)*

T

6

-

LDQS48****

LDQ48

T (LVDS)*

C (LVDS)*

T

N5

PL38B

P1

PL39A

LDQ38

LDQ48

VCCIO

P2

VCCIO6

PL39B

LDQ38

C

LDQ48

C

P3

PL40A

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

P4

PL40B

P5

PL41A

GNDIO

P7

GNDIO6

PL41B

6

-

LDQ38

C

6

-

LDQ48

C

R1

PL42A

LLM0_GPLLT_IN_A**

T (LVDS)*

LLM0_GPLLT_IN_A**/LDQS57**** T (LVDS)*

GNDIO

R2

GNDIO6

PL42B

6

-

LLM0_GPLLC_IN_A**

LLM0_GPLLT_FB_A

LLM0_GPLLC_FB_A

C (LVDS)*

6

-

LLM0_GPLLC_IN_A**/LDQ57

LLM0_GPLLT_FB_A/LDQ57

LLM0_GPLLC_FB_A/LDQ57

C (LVDS)*

R3

PL43A

T

R4

PL43B

C

VCCIO

R6

VCCIO6

PL44A

LLM0_GDLLT_IN_A**

LLM0_GDLLC_IN_A**

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T (LVDS)*

LLM0_GDLLT_IN_A**/LDQ57

LLM0_GDLLC_IN_A**/LDQ57

LLM0_GDLLT_FB_A/LDQ57

LLM0_GDLLC_FB_A/LDQ57

T (LVDS)*

R5

PL44B

C (LVDS)*

T1

PL45A

T

T2

PL45B

C

GNDIO

R7

GNDIO6

LLM0_PLLCAP

PL47A

6

-

6

-

T6

LDQ51

T (LVDS)*

LDQ66

T (LVDS)*

T7

PL47B

C (LVDS)*

U1

PL48A

T

U2

PL48B

C

VCCIO

T3

VCCIO6

PL49A

LDQ51

T (LVDS)*

LDQ66

T (LVDS)*

C (LVDS)*

U3

PL49B

C (LVDS)*

U6

PL50A

T

U5

PL50B

C

PL65B

GNDIO6

PL66A

PL66B

PL67A

6

-

LDQ66

C

GNDIO

V5

GNDIO6

PL51A

6

LDQS51

LDQ51

T (LVDS)*

C (LVDS)*

T

6

LDQS66

LDQ66

T (LVDS)*

C (LVDS)*

T

U4

PL51B

V1

PL52A

4-142

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

6

-

Dual Function

Differential

VCCIO

V3

VCCIO6

PL52B

PL53A

PL53B

PL54A

GNDIO6

PL54B

TCK

6

-

VCCIO6

PL67B

PL68A

PL68B

PL69A

GNDIO6

PL69B

TCK

LDQ51

C

LDQ66

C

W1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

Y1

AA1

GNDIO

AA2

V4

6

-

LDQ51

C

6

-

LDQ66

C

Y2

TDI

-

TDI

-

Y3

TMS

-

TMS

-

W3

TDO

-

TDO

-

W4

VCCJ

-

VCCJ

-

W5

PB2A

5

-

BDQ6

T

C

T

C

T

PB2A

5

-

BDQ6

T

C

T

C

T

Y4

PB2B

W6

PB3A

V6

PB3B

AA3

VCCIO

AB2

T8

PB4A

VCCIO5

PB4B

VCCIO5

PB4B

BDQ6

BDQS6

C

T

C

T

BDQ6

BDQS6

C

T

C

T

PB5A

U7

PB5B

U8

PB6A

GNDIO

T9

GNDIO5

PB6B

GNDIO5

PB6B

5

-

BDQ6

C

T

C

T

5

-

BDQ6

C

T

C

T

V8

PB7A

W8

PB7B

Y6

PB8A

VCCIO

Y5

VCCIO5

PB8B

VCCIO5

PB8B

BDQ6

C

T

C

T

BDQ6

C

T

C

T

AB3

AB4

AB5

GNDIO

AA6

V9

PB9A

PB9B

PB10A

GNDIO5

PB10B

PB13A

PB13B

VCCIO5

-

PB10A

GNDIO5

PB10B

PB31A

PB31B

VCCIO5

GNDIO5

PB32A

PB32B

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

5

-

BDQ6

BDQ15

C

T

5

-

BDQ6

BDQ33

C

T

U9

C

VCCIO

-

U10

T10

GNDIO

W9

PB14A

PB14B

GNDIO5

PB15A

PB15B

PB16A

PB16B

PB17A

PB17B

VCCIO5

GNDIO5

5

-

BDQ15

T

5

-

BDQ33

T

C

5

-

BDQS15****

BDQ15

T

C

T

5

-

BDQS33****

BDQ33

T

C

T

Y8

AA7

Y7

VREF2_5/BDQ15

VREF1_5/BDQ15

PCLKT5_0/BDQ15

PCLKC5_0/BDQ15

VREF2_5/BDQ33

VREF1_5/BDQ33

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

C

T

C

T

AB6

AB7

VCCIO

GNDIO

C

4-143

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

4

-

Dual Function

Differential

AA8

VCCIO

AB8

PB22A

VCCIO4

PB22B

PB23A

PB23B

PB24A

GNDIO4

PB24B

PB25A

PB25B

VCCIO4

GNDIO4

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

VCCIO4

PB32A

PB32B

GNDIO4

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO4

PB36A

PB36B

PB37A

PB37B

GNDIO4

PB38A

PB38B

PB39A

PB39B

PB40A

VCCIO4

PB40B

PB41A

PB41B

PB42A

GNDIO4

PB42B

PB43A

PB43B

PB44A

4

-

PCLKT4_0/BDQ24

T

PB40A

VCCIO4

PB40B

PB41A

PB41B

PB42A

GNDIO4

PB42B

PB43A

PB43B

VCCIO4

GNDIO4

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

PB54A

PB54B

PB55A

PB55B

GNDIO4

PB56A

PB56B

PB57A

PB57B

PB58A

VCCIO4

PB58B

PB59A

PB59B

PB60A

GNDIO4

PB60B

PB61A

PB61B

PB62A

PCLKT4_0/BDQ42

T

PCLKC4_0/BDQ24

VREF2_4/BDQ24

VREF1_4/BDQ24

BDQS24****

C

T

C

T

PCLKC4_0/BDQ42

VREF2_4/BDQ42

VREF1_4/BDQ42

BDQS42****

C

T

C

T

AA9

Y9

AB9

GNDIO

AB10

AA10

Y11

4

-

BDQ24

C

T

4

-

BDQ42

C

T

C

VCCIO

GNDIO

V10

4

-

BDQ33

T

C

T

4

-

BDQ51

T

C

T

U11

V11

W11

C

T

C

T

AA11

AB11

VCCIO

T11

C

BDQ33

T

BDQ51

T

U12

C

GNDIO

AA12

Y12

4

-

BDQS33

BDQ33

T

C

T

4

-

BDQS51

BDQ51

T

C

T

V12

W12

C

T

C

T

AB12

AA13

VCCIO

T12

C

BDQ33

T

C

T

BDQ51

T

C

T

U13

V13

T13

C

GNDIO

AB13

AB14

U14

4

-

BDQ42

T

C

T

C

T

4

-

BDQ60

T

C

T

C

T

T14

AA14

VCCIO

Y14

BDQ42

BDQS42

C

T

C

T

BDQ60

BDQS60

C

T

C

T

W14

V14

AB15

GNDIO

AA15

V15

4

BDQ42

C

T

C

T

4

BDQ60

C

T

C

T

U15

AB16

4-144

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

4

-

Dual Function

Differential

VCCIO

AA16

AB17

AA17

Y15

VCCIO4

PB44B

PB45A

PB45B

PB46A

GNDIO4

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO4

PB50A

PB50B

GNDIO4

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO4

PB54A

PB54B

PB55A

PB55B

GNDIO4

CFG2

4

-

VCCIO4

PB62B

PB63A

PB63B

PB64A

GNDIO4

PB64B

PB65A

PB65B

PB66A

PB66B

PB67A

PB67B

VCCIO4

PB68A

PB68B

GNDIO4

PB69A

PB69B

PB70A

PB70B

PB71A

PB71B

VCCIO4

PB72A

PB72B

PB73A

PB73B

GNDIO4

CFG2

BDQ42

C

T

C

T

BDQ60

C

T

C

T

GNDIO

W15

AB20

AB21

AA21

AA20

AB19

AB18

VCCIO

Y22

4

-

BDQ42

BDQ51

C

T

4

-

BDQ60

BDQ69

C

T

C

T

C

T

C

T

C

T

C

BDQ51

T

BDQ69

T

Y21

C

GNDIO

Y17

4

-

BDQS51

BDQ51

T

C

T

4

-

BDQS69

BDQ69

T

C

T

Y18

Y16

W17

Y19

C

T

C

T

Y20

C

VCCIO

W19

W18

V17

BDQ51

T

C

T

BDQ69

T

C

T

V18

C

GNDIO

W20

V20

8

-

8

-

CFG1

V19

CFG0

V22

PROGRAMN

CCLK

PROGRAMN

CCLK

W22

U18

INITN

U22

DONE

GNDIO

U20

GNDIO8

PR53B

PR53A

PR52B

PR52A

VCCIO8

PR51B

PR51A

PR50B

GNDIO8

PR50A

PR49B

PR49A

GNDIO8

PR68B

PR68A

PR67B

PR67A

VCCIO8

PR66B

PR66A

PR65B

GNDIO8

PR65A

PR64B

PR64A

8

-

WRITEN***

CS1N***

C

T

C

T

8

-

WRITEN***

CS1N***

C

T

C

T

U21

U17

CSN***

U16

D0/SPIFASTN***

VCCIO

T16

D1***

D2***

D3***

C

T

D1***

D2***

D3***

C

T

T17

T22

C

GNDIO

R22

8

D4***

D5***

D6***

T

C

T

8

D4***

D5***

D6***

T

C

T

T15

R17

4-145

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

8

3

-

Dual Function

Differential

T20

VCCIO

T21

PR48B

VCCIO8

PR48A

PR47B

PR47A

RLM0_PLLCAP

PR45B

GNDIO3

PR45A

PR44B

PR44A

PR43B

VCCIO3

PR43A

PR42B

PR42A

GNDIO3

-

8

3

-

D7***

C

PR63B

VCCIO8

PR63A

PR62B

PR62A

RLM0_PLLCAP

PR60B

GNDIO3

PR60A

PR59B

PR59A

PR58B

VCCIO3

PR58A

PR57B

PR57A

GNDIO3

VCCIO3

PR51B

PR51A

GNDIO3

PR50B

PR50A

PR49B

PR49A

VCCIO3

PR48B

PR48A

PR47B

GNDIO3

PR47A

PR46B

PR46A

PR45B

VCCIO3

PR45A

PR44B

PR44A

PR42B

VCCIO3

PR42A

PR41B

PR41A

GNDIO3

PR40B

PR40A

PR39B

PR39A

VCCIO3

D7***

C

DI/CSSPI0N***

DOUT/CSON/CSSPI1N***

BUSY/SISPI***

T

C

T

DI/CSSPI0N***

DOUT/CSON/CSSPI1N***

BUSY/SISPI***

T

C

T

R21

R20

R16

R18

RLM0_GDLLC_FB_A

C

RLM0_GDLLC_FB_A/RDQ57

C

GNDIO

R19

3

-

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A**

RLM0_GDLLT_IN_A**

RLM0_GPLLC_IN_A**

T

3

-

RLM0_GDLLT_FB_A/RDQ57

RLM0_GDLLC_IN_A**/RDQ57

RLM0_GDLLT_IN_A**/RDQ57

RLM0_GPLLC_IN_A**/RDQ57

T

P22

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

P21

P16

VCCIO

P17

RLM0_GPLLT_IN_A**

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

T

RLM0_GPLLT_IN_A**/RDQ57

RLM0_GPLLC_FB_A/RDQ57

T

P20

C (LVDS)*

T (LVDS)*

C (LVDS)*

P19

RLM0_GPLLT_FB_A/RDQS57**** T (LVDS)*

GNDIO

-

3

-

P18

PR41B

PR41A

GNDIO3

PR40B

PR40A

PR39B

PR39A

VCCIO3

PR38B

PR38A

PR37B

GNDIO3

PR37A

PR36B

PR36A

PR35B

VCCIO3

PR35A

PR34B

PR34A

PR32B

VCCIO3

PR32A

PR31B

PR31A

GNDIO3

PR30B

PR30A

PR29B

PR29A

VCCIO3

3

-

RDQ38

C

T

RDQ48

C

T

N16

GNDIO

N22

3

-

RDQ38

C (LVDS)*

3

-

RDQ48

C (LVDS)*

N21

T (LVDS)*

N17

C

T

C

T

N18

VCCIO

M22

M21

M16

GNDIO

M17

M20

M19

M18

VCCIO

L16

RDQ38

RDQS38

RDQ38

C (LVDS)*

T (LVDS)*

C

RDQ48

RDQS48

RDQ48

C (LVDS)*

T (LVDS)*

C

3

-

RDQ38

T

3

-

RDQ48

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

RDQ38

T

RDQ48

T

L22

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

L21

RDQ38

RDQ48

K22

RLM1_SPLLC_FB_A

RLM2_SPLLC_FB_A

VCCIO

K21

RLM1_SPLLT_FB_A

RLM1_SPLLC_IN_A

RLM1_SPLLT_IN_A

T

RLM2_SPLLT_FB_A

RLM2_SPLLC_IN_A

RLM2_SPLLT_IN_A

T

L17

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

L18

GNDIO

L20

3

C

3

C

L19

T

K16

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

K17

VCCIO

4-146

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

3

2

-

Dual Function

Differential

J16

K18

PR28B

PR28A

PR27B

PR27A

PR25B

PR25A

GNDIO2

PR24B

PR24A

PR23B

PR23A

VCCIO2

PR22B

PR22A

PR21B

GNDIO2

PR21A

PR20B

PR20A

PR19B

VCCIO2

PR19A

PR18B

PR18A

GNDIO2

PR16B

VCCIO2

PR16A

-

3

2

-

VREF2_3

VREF1_3

C

PR38B

PR38A

PR37B

PR37A

PR35B

PR35A

GNDIO2

PR34B

PR34A

PR33B

PR33A

VCCIO2

PR32B

PR32A

PR31B

GNDIO2

PR31A

PR30B

PR30A

PR29B

VCCIO2

PR29A

PR28B

PR28A

-

VREF2_3

VREF1_3

C

T

J22

PCLKC3_0

C (LVDS)*

PCLKC3_0

C (LVDS)*

J21

PCLKT3_0

T (LVDS)*

PCLKT3_0

T (LVDS)*

H22

PCLKC2_0/RDQ22

PCLKT2_0/RDQ22

C

T

PCLKC2_0/RDQ32

PCLKT2_0/RDQ32

C

T

H21

GNDIO

J17

2

-

RDQ22

C (LVDS)*

2

-

RDQ32

C (LVDS)*

J18

T (LVDS)*

J20

C

T

C

T

J19

VCCIO

H16

RDQ22

RDQS22

RDQ22

C (LVDS)*

T (LVDS)*

C

RDQ32

RDQS32

RDQ32

C (LVDS)*

T (LVDS)*

C

H17

G22

GNDIO

G21

H20

2

-

RDQ22

T

2

-

RDQ32

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

H19

RDQ22

RDQ32

G16

VCCIO

H18

RUM1_SPLLC_FB_A/RDQ22

RUM1_SPLLC_FB_A/RDQ32

RUM1_SPLLT_FB_A/RDQ22

T

RUM1_SPLLT_FB_A/RDQ32

RUM1_SPLLC_IN_A/RDQ32

RUM1_SPLLT_IN_A/RDQ32

T

F22

RUM1_SPLLC_IN_A/RDQ22 C (LVDS)*

RUM1_SPLLT_IN_A/RDQ22 T (LVDS)*

C (LVDS)*

T (LVDS)*

F21

GNDIO

G20

VCCIO

F20

2

-

C

T

PR26B

-

2

-

RDQ23

C

T

PR26A

GNDIO2

PR25B

PR25A

VCCIO2

GNDIO2

PR14B

PR14A

PR13B

PR13A

VCCIO2

PR12B

PR12A

PR11B

PR11A

PR9B

2

-

G17

F17

PR15B

PR15A

-

2

-

C (LVDS)*

T (LVDS)*

2

-

RDQ23

C (LVDS)*

T (LVDS)*

-

GNDIO

E22

GNDIO2

PR14B

PR14A

PR13B

PR13A

VCCIO2

PR12B

PR12A

PR11B

PR11A

PR9B

-

2

-

C

2

-

RDQ15

C

D22

T

E20

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

D20

VCCIO

D19

RUM0_SPLLC_FB_A

RUM0_SPLLT_FB_A

RUM0_SPLLC_IN_A

RUM0_SPLLT_IN_A

VREF2_2

C

RUM0_SPLLC_FB_A/RDQ15

RUM0_SPLLT_FB_A/RDQ15

RUM0_SPLLC_IN_A/RDQ15

RUM0_SPLLT_IN_A/RDQ15

VREF2_2

C

E19

T

F18

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

F19

E18

GNDIO

D18

GNDIO2

PR9A

GNDIO2

PR9A

2

-

VREF1_2

T

2

-

VREF1_2

T

VCCIO

F16

VCCIO2

XRES

-

XRES

-

C22

URC_SQ_VCCRX0

URC_SQ_HDINP0

12

URC_SQ_VCCRX0

URC_SQ_HDINP0

12

A21

T

4-147

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

12

Dual Function

Differential

B22

B21

C19

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

12

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

C

12

C

12

URC_SQ_HDOUTP

0

URC_SQ_HDOUTP

0

A18

A19

B18

C18

B17

C17

A17

12

T

C

T

12

T

C

T

URC_SQ_VCCOB0

URC_SQ_HDOUTN

0

URC_SQ_HDOUTN

0

URC_SQ_VCCTX1

URC_SQ_HDOUTN

1

URC_SQ_HDOUTN

1

URC_SQ_VCCOB1

URC_SQ_HDOUTP

1

URC_SQ_HDOUTP

1

C21

B20

C20

A20

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

C

T

C

T

URC_SQ_VCCAUX

33

URC_SQ_VCCAUX

33

B16

E17

D17

12

URC_SQ_REFCLK

N

URC_SQ_REFCLK

N

C

T

C

T

URC_SQ_REFCLK

P

URC_SQ_REFCLK

P

C16

A12

C12

B12

C11

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

12

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

12

T

C

URC_SQ_HDOUTP

2

URC_SQ_HDOUTP

2

A15

C15

B15

C14

B14

A13

A14

12

T

C

T

12

T

C

T

URC_SQ_VCCOB2

URC_SQ_HDOUTN

2

URC_SQ_HDOUTN

2

URC_SQ_VCCTX2

URC_SQ_HDOUTN

3

URC_SQ_HDOUTN

3

URC_SQ_VCCOB3

URC_SQ_HDOUTP

3

URC_SQ_HDOUTP

3

C13

B11

B10

A11

C10

E13

D12

GNDIO

A9

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT28B

12

1

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT46B

12

1

C

T

C

T

C

T

C

T

PT28A

1

PT46A

1

GNDIO1

-

GNDIO1

-

PT27B

1

C

T

C

T

PT45B

1

C

T

C

T

A8

PT27A

1

PT45A

1

A7

PT26B

1

PT44B

1

A6

PT26A

1

PT44A

1

VCCIO

E12

VCCIO1

1

VCCIO1

1

PT25B

1

C

PT43B

1

C

4-148

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

1

-

Dual Function

Differential

F12

A5

PT25A

PT24B

PT24A

GNDIO1

PT23B

PT23A

PT22B

PT22A

VCCIO1

PT21B

PT21A

PT20A

PT20B

PT19B

GNDIO0

PT19A

PT18B

PT18A

PT17B

VCCIO0

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

GNDIO0

PT14A

PT13B

VCCIO0

PT13A

PT12B

PT12A

PT11B

PT11A

-

1

-

T

C

T

PT43A

PT42B

PT42A

GNDIO1

PT41B

PT41A

PT40B

PT40A

VCCIO1

PT39B

PT39A

PT38A

PT38B

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

GNDIO0

PT32A

PT31B

VCCIO0

PT31A

PT30B

PT30A

PT29B

PT29A

GNDIO0

VCCIO0

PT10B

PT10A

GNDIO0

PT9B

T

C

T

A4

GNDIO

B7

1

0

-

C

T

C

T

1

0

-

C

T

C

T

B8

G11

E11

VCCIO

D11

D10

F11

G10

G9

VREF2_1

VREF1_1

C

T

VREF2_1

VREF1_1

C

T

PCLKT1_0

PCLKC1_0

PCLKC0_0

T

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

C

GNDIO

F9

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

C9

D9

A2

C

VCCIO

A3

T

C

T

C

T

B3

C4

E10

F10

C7

C

T

C

T

C

GNDIO

B6

0

-

T

0

-

T

C6

C

VCCIO

C5

T

C

T

C

T

C

T

C

T

C8

D8

E8

E9

-

0

-

F8

PT10B

PT10A

GNDIO0

PT9B

0

-

C

T

C

T

G8

GNDIO

F7

0

C

T

C

T

0

C

T

C

T

G7

PT9A

C3

PT8B

D4

PT8A

VCCIO

F6

VCCIO0

PT7B

VCCIO0

PT7B

C

T

C

T

C

T

C

T

E6

PT7A

E5

PT6B

D6

PT6A

4-149

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

-

Dual Function

Differential

GNDIO

D3

GNDIO0

PT5B

-

0

-

GNDIO0

PT5B

C

T

C

T

0

-

C

T

C

T

E3

PT5A

D5

PT4B

E4

PT4A

VCCIO

C2

VCCIO0

PT3B

VCCIO0

PT3B

C

T

C

T

C

T

C

T

B2

PT3A

B1

PT2B

C1

PT2A

R8

VCCPLL

VCC

VCCPLL

VCC

H15

H8

-

R15

J10

J11

J12

J13

K14

K9

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

L14

L9

VCC

-

VCC

-

VCC

-

VCC

-

M14

M9

VCC

-

VCC

-

VCC

-

VCC

-

N14

N9

VCC

-

VCC

-

VCC

-

VCC

-

P10

P11

P12

P13

B5

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

0

1

2

3

4

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

0

1

2

3

4

B9

E7

H9

D13

E16

H14

E21

G18

J15

K19

N19

P15

T18

V21

AA18

R14

V16

W13

4-150

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

AA5

R9

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

5

6

7

8

-

V7

W10

N4

P8

T5

V2

E2

G5

J8

K4

AA22

U19

H11

H12

L15

L8

-

M15

M8

-

R11

R12

A1

-

A10

A16

A22

AA19

AA4

AB1

AB22

B13

B19

B4

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

D16

D2

GND

-

GND

-

GND

-

GND

-

D21

D7

GND

-

GND

-

GND

-

GND

-

G19

G4

GND

-

GND

-

GND

-

GND

-

H10

H13

J14

J9

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

K10

K11

K12

K13

K15

K20

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-151

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA

LFE2M20E/SE

LFE2M35E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

K3

K8

GND

NC

-

GND

NC

-

L10

L11

L12

L13

M10

M11

M12

M13

N10

N11

N12

N13

N15

N20

N3

N8

P14

P9

R10

R13

T19

T4

W16

W2

W21

W7

Y10

Y13

D15

G14

G15

D14

E15

E14

F15

F14

F13

G12

G13

NC

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices

(ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100).

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-152

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA

LFE2M50E/SE

Ball Number

D1

Ball/Pad Function

PL2A

Bank

7

-

Dual Function

LDQ6

Differential

T (LVDS)*

C (LVDS)*

T

E1

PL2B

LDQ6

F1

PL3A

LDQ6

F2

PL3B

LDQ6

C

F5

PL4A

LDQ6

T (LVDS)*

VCCIO

G6

VCCIO7

PL4B

LDQ6

LDQS6

C (LVDS)*

F4

PL5A

T

C

F3

PL5B

G1

PL6A

T (LVDS)*

GNDIO

G2

GNDIO7

PL6B

7

-

LDQ6

C (LVDS)*

H1

PL7A

T

H2

PL7B

C

VCCIO

H7

VCCIO7

PL8A

LDQ6

T (LVDS)*

H6

PL8B

LDQ6

C (LVDS)*

G3

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

H3

PL9B

C

GNDIO

VCCIO

H5

GNDIO7

VCCIO7

PL11A

PL11B

PL12A

PL12B

GNDIO7

PL13A

PL13B

PL14A

VCCIO7

PL14B

GNDIO7

VCCIO7

PL32A

PL32B

PL33A

PL33B

VCCIO7

PL34A

PL34B

PL35A

PL35B

7

-

LUM0_SPLLT_IN_A

LUM0_SPLLC_IN_A

LUM0_SPLLT_FB_A

LUM0_SPLLC_FB_A

T (LVDS)*

H4

C (LVDS)*

J1

T

J2

C

GNDIO

J3

7

-

T (LVDS)*

C (LVDS)*

T

J4

J7

VCCIO

J6

C

GNDIO

VCCIO

K1

7

LUM3_SPLLT_IN_A/LDQ36

LUM3_SPLLC_IN_A/LDQ36

LUM3_SPLLT_FB_A/LDQ36

LUM3_SPLLC_FB_A/LDQ36

T (LVDS)*

K2

C (LVDS)*

J5

T

K5

C

VCCIO

K7

LDQ36

T (LVDS)*

K6

C (LVDS)*

L6

T

L7

C

4-153

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

GNDIO

L1

Ball/Pad Function

GNDIO7

PL36A

Bank

-

Dual Function

Differential

7

-

LDQS36

LDQ36

T (LVDS)*

C (LVDS)*

T

L2

PL36B

M7

PL37A

VCCIO

L5

VCCIO7

PL37B

LDQ36

C

L3

PL38A

T (LVDS)*

C (LVDS)*

T

L4

PL38B

LDQ36

M1

PL39A

PCLKT7_0/LDQ36

GNDIO

M2

GNDIO7

PL39B

7

6

-

PCLKC7_0/LDQ36

PCLKT6_0

C

M6

PL41A

T (LVDS)*

M5

PL41B

PCLKC6_0

VREF2_6

C (LVDS)*

M3

PL42A

T

M4

PL42B

VREF1_6

C

VCCIO

N7

VCCIO6

PL45A

LLM3_SPLLT_IN_A

T (LVDS)*

GNDIO

N6

GNDIO6

PL45B

6

-

LLM3_SPLLC_IN_A

LLM3_SPLLT_FB_A

LLM3_SPLLC_FB_A

C (LVDS)*

N1

PL46A

T

N2

PL46B

C

VCCIO

GNDIO

P6

VCCIO6

GNDIO6

PL52A

6

-

LDQS52****

LDQ52

T (LVDS)*

C (LVDS)*

T

N5

PL52B

P1

PL53A

LDQ52

VCCIO

P2

VCCIO6

PL53B

LDQ52

C

P3

PL54A

T (LVDS)*

C (LVDS)*

T

P4

PL54B

P5

PL55A

GNDIO

P7

GNDIO6

PL55B

6

-

LDQ52

C

VCCIO

GNDIO

R1

VCCIO6

GNDIO6

PL62A

6

-

LLM0_GPLLT_IN_A**

T (LVDS)*

GNDIO

R2

GNDIO6

PL62B

6

LLM0_GPLLC_IN_A**

LLM0_GPLLT_FB_A

LLM0_GPLLC_FB_A

C (LVDS)*

R3

PL63A

T

R4

PL63B

C

VCCIO

R6

VCCIO6

PL64A

LLM0_GDLLT_IN_A**

LLM0_GDLLC_IN_A**

T (LVDS)*

C (LVDS)*

R5

PL64B

4-154

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

T1

Ball/Pad Function

PL65A

PL65B

GNDIO6

LLM0_PLLCAP

PL67A

PL67B

PL68A

PL68B

VCCIO6

PL69A

PL69B

PL70A

PL70B

GNDIO6

PL71A

PL71B

PL72A

VCCIO6

PL72B

PL73A

PL73B

PL74A

GNDIO6

PL74B

TCK

Bank

6

-

Dual Function

Differential

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T

T2

C

GNDIO

R7

6

-

T6

LDQ71

T (LVDS)*

T7

C (LVDS)*

U1

T

U2

C

VCCIO

T3

LDQ71

T (LVDS)*

U3

C (LVDS)*

U6

T

U5

C

GNDIO

V5

6

-

LDQS71

LDQ71

T (LVDS)*

C (LVDS)*

T

U4

V1

VCCIO

V3

LDQ71

C

W1

T (LVDS)*

C (LVDS)*

T

Y1

AA1

GNDIO

AA2

V4

6

-

LDQ71

C

Y2

TDI

-

Y3

TMS

-

W3

TDO

-

W4

VCCJ

-

W5

PB2A

5

-

BDQ6

T

C

T

Y4

PB2B

W6

PB3A

V6

PB3B

C

T

AA3

AB2

VCCIO

T8

PB4A

PB4B

C

VCCIO5

PB5A

BDQ6

T

U7

PB5B

C

GNDIO

U8

GNDIO5

PB6A

5

BDQS6

BDQ6

T

C

T

T9

PB6B

V8

PB7A

W8

PB7B

C

4-155

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

Y6

Ball/Pad Function

PB8A

Bank

5

-

Dual Function

BDQ6

Differential

T

Y5

PB8B

BDQ6

C

VCCIO

AB3

VCCIO5

PB9A

BDQ6

T

C

T

AB4

PB9B

AB5

PB10A

PB10B

GNDIO5

VCCIO5

PB40A

PB40B

VCCIO5

PB41A

PB41B

GNDIO5

PB42A

PB42B

PB43A

PB43B

PB44A

PB44B

VCCIO5

GNDIO5

PB49A

VCCIO4

PB49B

PB50A

PB50B

PB51A

GNDIO4

PB51B

PB52A

PB52B

VCCIO4

GNDIO4

PB56A

PB56B

PB57A

PB57B

PB58A

PB58B

VCCIO4

PB59A

AA6

C

GNDIO

VCCIO

V9

5

-

BDQ42

T

U9

C

VCCIO

U10

BDQ42

T

T10

C

GNDIO

W9

5

-

BDQS42****

BDQ42

T

C

T

Y8

AA7

VREF2_5/BDQ42

VREF1_5/BDQ42

PCLKT5_0/BDQ42

PCLKC5_0/BDQ42

Y7

C

T

AB6

AB7

C

VCCIO

GNDIO

AA8

4

-

PCLKT4_0/BDQ51

T

VCCIO

AB8

PCLKC4_0/BDQ51

VREF2_4/BDQ51

VREF1_4/BDQ51

BDQS51****

C

T

C

T

AA9

Y9

AB9

GNDIO

AB10

AA10

Y11

4

-

BDQ51

C

T

C

VCCIO

GNDIO

V10

4

BDQ60

T

C

T

U11

V11

W11

C

T

AA11

AB11

VCCIO

T11

C

BDQ60

T

4-156

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

U12

Ball/Pad Function

PB59B

GNDIO4

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO4

PB63A

PB63B

PB64A

PB64B

GNDIO4

PB65A

PB65B

PB66A

PB66B

PB67A

VCCIO4

PB67B

PB68A

PB68B

PB69A

GNDIO4

PB69B

PB70A

PB70B

PB71A

VCCIO4

PB71B

PB72A

PB72B

GNDIO4

CFG2

Bank

4

-

Dual Function

Differential

BDQ60

C

GNDIO

AA12

Y12

4

-

BDQS60

BDQ60

T

C

T

V12

W12

C

T

AB12

AA13

VCCIO

T12

C

BDQ60

T

C

T

U13

V13

T13

C

GNDIO

AB13

AB14

U14

4

-

BDQ69

T

C

T

C

T

T14

AA14

VCCIO

Y14

BDQ69

BDQS69

C

T

C

T

W14

V14

AB15

GNDIO

AA15

V15

4

-

BDQ69

C

T

C

T

U15

AB16

VCCIO

AA16

AB17

AA17

GNDIO

W20

BDQ69

C

T

C

8

-

V20

CFG1

V19

CFG0

V22

PROGRAMN

CCLK

W22

U18

INITN

U22

DONE

GNDIO

U20

GNDIO8

WRITEN***

8

4-157

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

U21

Ball/Pad Function

CS1N***

CSN***

Bank

8

-

Dual Function

Differential

U17

U16

D0/SPIFASTN***

VCCIO8

D1***

VCCIO

T16

T17

D2***

T22

D3***

GNDIO

R22

GNDIO8

D4***

8

3

-

T15

D5***

R17

D6***

T20

D7***

VCCIO

T21

VCCIO8

DI/CSSPI0N***

DOUT/CSON/CSSPI1N***

BUSY/SISPI***

RLM0_PLLCAP

PR65B

R21

R20

R16

R18

RLM0_GDLLC_FB_A

C

GNDIO

R19

GNDIO3

PR65A

3

-

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A**

RLM0_GDLLT_IN_A**

RLM0_GPLLC_IN_A**

T

P22

PR64B

C (LVDS)*

T (LVDS)*

C

P21

PR64A

P16

PR63B

VCCIO

P17

VCCIO3

PR63A

RLM0_GPLLT_IN_A**

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

T

P20

PR62B

C (LVDS)*

T (LVDS)*

P19

PR62A

GNDIO

VCCIO

P18

GNDIO3

VCCIO3

PR55B

3

-

RDQ52

C

T

N16

PR55A

GNDIO

N22

GNDIO3

PR54B

3

-

RDQ52

C (LVDS)*

N21

PR54A

T (LVDS)*

N17

PR53B

C

T

N18

PR53A

VCCIO

M22

VCCIO3

PR52B

RDQ52

RDQS52

RDQ52

C (LVDS)*

T (LVDS)*

C

M21

PR52A

M16

PR51B

GNDIO

M17

GNDIO3

PR51A

3

RDQ52

T

M20

PR50B

C (LVDS)*

4-158

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

M19

Ball/Pad Function

PR50A

PR49B

VCCIO3

PR49A

PR48B

PR48A

GNDIO3

PR46B

VCCIO3

PR46A

PR45B

PR45A

GNDIO3

PR44B

PR44A

PR43B

PR43A

VCCIO3

PR42B

PR42A

PR41B

PR41A

PR39B

PR39A

GNDIO2

PR38B

PR38A

PR37B

PR37A

VCCIO2

PR36B

PR36A

PR35B

GNDIO2

PR35A

PR34B

PR34A

PR33B

VCCIO2

PR33A

PR32B

PR32A

PR30B

Bank

3

-

Dual Function

RDQ52

Differential

T (LVDS)*

C

M18

RDQ52

VCCIO

L16

RDQ52

T

L22

C (LVDS)*

T (LVDS)*

L21

GNDIO

K22

3

-

RLM3_SPLLC_FB_A

C

VCCIO

K21

RLM3_SPLLT_FB_A

RLM3_SPLLC_IN_A

RLM3_SPLLT_IN_A

T

L17

C (LVDS)*

T (LVDS)*

L18

GNDIO

L20

3

2

-

C

L19

T

K16

C (LVDS)*

T (LVDS)*

K17

VCCIO

J16

VREF2_3

VREF1_3

C

K18

T

J22

PCLKC3_0

C (LVDS)*

J21

PCLKT3_0

T (LVDS)*

H22

PCLKC2_0/RDQ36

PCLKT2_0/RDQ36

C

T

H21

GNDIO

J17

2

-

RDQ36

C (LVDS)*

J18

T (LVDS)*

J20

C

T

J19

VCCIO

H16

RDQ36

RDQS36

RDQ36

C (LVDS)*

T (LVDS)*

C

H17

G22

GNDIO

G21

2

RDQ36

T

H20

C (LVDS)*

T (LVDS)*

C

H19

RDQ36

G16

RUM3_SPLLC_FB_A/RDQ36

VCCIO

H18

RUM3_SPLLT_FB_A/RDQ36

RUM3_SPLLC_IN_A/RDQ36

RUM3_SPLLT_IN_A/RDQ36

RDQ27

T

F22

C (LVDS)*

T (LVDS)*

C

F21

G20

4-159

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

F20

Ball/Pad Function

PR30A

Bank

2

Dual Function

Differential

RDQ27

T

GNDIO

G17

GNDIO2

-

PR29B

2

RDQ27

C (LVDS)*

T (LVDS)*

F17

PR29A

2

VCCIO

GNDIO

E22

VCCIO2

2

GNDIO2

-

PR14B

2

C

T

D22

PR14A

2

VCCIO

E20

VCCIO2

-

PR13B

2

C (LVDS)*

T (LVDS)*

C

D20

PR13A

2

D19

PR12B

2

RUM0_SPLLC_FB_A

GNDIO

E19

GNDIO2

-

PR12A

2

RUM0_SPLLT_FB_A

RUM0_SPLLC_IN_A

RUM0_SPLLT_IN_A

T

F18

PR11B

2

C (LVDS)*

T (LVDS)*

F19

PR11A

2

VCCIO

E18

VCCIO2

-

PR9B

2

VREF2_2

VREF1_2

C

T

GNDIO

D18

GNDIO2

-

PR9A

2

VCCIO

F16

VCCIO2

2

XRES

-

C22

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

URC_SQ_VCCAUX33

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

URC_SQ_HDINP2

12

A21

T

C

T

B22

B21

C19

A18

A19

B18

C

T

C18

B17

C17

A17

C21

B20

C

T

C20

A20

B16

E17

C

T

D17

C16

A12

T

4-160

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

C12

B12

Ball/Pad Function

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

GNDIO1

Bank

12

-

Dual Function

Differential

C

T

C11

A15

C15

B15

C

T

C14

B14

A13

A14

C13

B11

C

T

B10

A11

C10

GNDIO

VCCIO

E13

VCCIO1

1

PT55B

1

C

T

D12

GNDIO

A9

PT55A

1

GNDIO1

-

PT54B

1

C

T

C

T

A8

PT54A

1

A7

PT53B

1

A6

PT53A

1

VCCIO

E12

VCCIO1

1

PT52B

1

C

T

C

T

F12

PT52A

1

A5

PT51B

1

A4

PT51A

1

GNDIO

B7

GNDIO1

-

PT50B

1

C

T

C

T

B8

PT50A

1

G11

E11

PT49B

1

PT49A

1

VCCIO

D11

D10

G10

F11

VCCIO1

1

PT48B

1

VREF2_1

VREF1_1

C

T

PT48A

1

PT47B

1

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

PT47A

1

G9

PT46B

0

C

GNDIO

F9

GNDIO0

-

PT46A

0

PCLKT0_0

VREF2_0

T

C9

PT45B

0

C

4-161

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

D9

Ball/Pad Function

PT45A

PT44B

VCCIO0

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

GNDIO0

PT41A

PT40B

VCCIO0

PT40A

PT39B

PT39A

PT38B

PT38A

GNDIO0

VCCIO0

PT10B

GNDIO0

PT10A

PT9B

Bank

0

-

Dual Function

Differential

VREF1_0

T

A2

C

VCCIO

A3

T

C

T

B3

C4

E10

F10

C7

C

T

C

GNDIO

B6

0

-

T

C6

C

VCCIO

C5

T

C

T

C

T

C8

D8

E8

E9

GNDIO

VCCIO

F8

0

-

C

GNDIO

G8

0

-

T

C

T

F7

G7

PT9A

C3

PT8B

C

VCCIO

D4

VCCIO0

PT8A

T

C

T

F6

PT7B

E6

PT7A

E5

PT6B

C

T

D6

PT6A

D3

PT5B

C

GNDIO

E3

GNDIO0

PT5A

0

-

T

D5

PT4B

C

VCCIO

E4

VCCIO0

PT4A

T

C

T

C

T

C2

PT3B

B2

PT3A

B1

PT2B

C1

PT2A

J10

VCC

4-162

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

J11

J12

J13

K14

K9

Ball/Pad Function

VCC

Bank

-

Dual Function

Differential

VCC

-

VCC

-

VCC

-

VCC

-

L14

L9

VCC

-

VCC

-

M14

M9

VCC

-

VCC

-

N14

N9

VCC

-

VCC

-

P10

P11

P12

P13

B5

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

0

1

2

3

4

5

6

7

B9

E7

H9

D13

E16

H14

E21

G18

J15

K19

N19

P15

T18

V21

AA18

R14

V16

W13

AA5

R9

V7

W10

N4

P8

T5

V2

E2

4-163

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

G5

Ball/Pad Function

VCCIO7

VCCIO8

VCCAUX

GND

Bank

Dual Function

Differential

7

8

-

J8

K4

AA22

U19

H11

H12

L15

L8

M15

M8

R11

R12

A1

A10

A16

A22

AA19

AA4

AB1

AB22

B13

B19

B4

GND

D16

D2

GND

D21

D7

GND

G19

G4

GND

H10

H13

J14

J9

GND

K10

K11

K12

K13

K15

K20

K3

GND

K8

GND

L10

GND

4-164

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

L11

Ball/Pad Function

GND

NC

Bank

Dual Function

Differential

-

L12

L13

M10

M11

M12

M13

N10

N11

N12

N13

N15

N20

N3

N8

P14

P9

R10

R13

T19

T4

W16

W2

W21

W7

Y10

Y13

Y15

W15

AB20

AB21

AA21

AA20

AB19

AB18

Y22

Y21

Y17

Y18

Y16

W17

Y19

Y20

NC

4-165

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)

LFE2M50E/SE

Ball Number

W19

W18

V17

Ball/Pad Function

Bank

Dual Function

Differential

NC

-

NC

V18

NC

D15

G14

G15

D14

E15

NC

E14

NC

F15

NC

F14

NC

F13

NC

G12

G13

H8

NC

VCCPLL

H15

R8

R15

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices

(ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100).

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-166

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

LDQ6

Differential

T (LVDS)*

C (LVDS)*

T

Bank

7

-

Dual Function

Differential

C2

C1

PL2A

PL2B

7

-

PL2A

PL2B

LDQ6

T*

C*

T

LDQ6

F6

PL3A

LDQ6

PL3A

H9

PL3B

LDQ6

C

PL3B

C

D3

PL4A

LDQ6

T (LVDS)*

PL4A

T*

VCCIO

D2

VCCIO7

PL4B

VCCIO7

PL4B

LDQ6

LDQS6

C (LVDS)*

LDQ6

LDQS6

C*

T

F5

PL5A

T

C

PL5A

H8

PL5B

C

E3

PL6A

T (LVDS)*

PL6A

T*

GNDIO

E2

GNDIO7

PL6B

GNDIO7

PL6B

7

-

LDQ6

C (LVDS)*

7

-

LDQ6

C*

T

J9

PL7A

T

PL7A

E4

PL7B

C

PL7B

C

VCCIO

E1

VCCIO7

PL8A

VCCIO7

PL8A

LDQ6

T (LVDS)*

LDQ6

T*

C*

T

D1

PL8B

LDQ6

C (LVDS)*

PL8B

LDQ6

J8

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

T

PL9A

VREF2_7/LDQ6

VREF1_7/LDQ6

F4

PL9B

C

PL9B

C

GNDIO

-

GNDIO7

-

GNDIO7

VCCIO7

PL11A

PL11B

PL12A

PL12B

GNDIO7

PL13A

-

7

-

F3

PL11A

PL11B

PL12A

PL12B

-

7

-

LUM0_SPLLT_IN_A/LDQ15

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

T (LVDS)*

LUM0_SPLLT_IN_A

LUM0_SPLLC_IN_A

LUM0_SPLLT_FB_A

LUM0_SPLLC_FB_A

T*

C*

T

F1

C (LVDS)*

G6

T

K9

C

-

G5

PL13A

VCCIO7

PL13B

PL14A

-

7

-

LDQ15

T (LVDS)*

7

-

T*

VCCIO

G4

LDQ15

C (LVDS)*

T

PL13B

PL14A

VCCIO7

PL14B

GNDIO7

PL19A

PL19B

PL20A

VCCIO7

PL20B

GNDIO7

PL23A

PL23B

PL24A

PL24B

VCCIO7

PL25A

PL25B

PL26A

PL26B

GNDIO7

7

-

C*

T

H5

-

H6

PL14B

GNDIO7

PL16A

PL16B

PL17A

VCCIO7

PL17B

GNDIO7

PL19A

PL19B

PL20A

PL20B

VCCIO7

PL21A

PL21B

PL22A

PL22B

GNDIO7

7

-

LDQ15

C

GNDIO

J7

7

-

LDQ15

T

C

7

-

T

C

H4

H3

T (LVDS)*

T*

VCCIO

G3

LDQ15

C (LVDS)*

C*

GNDIO

G1

7

-

LDQ23

T (LVDS)*

7

-

LDQ27

T*

C*

T

H1

C (LVDS)*

J3

T

J4

C

VCCIO

H2

LDQ23

T (LVDS)*

LDQ27

T*

C*

T

J2

C (LVDS)*

K7

T

J6

C

GNDIO

4-167

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

LDQS23

LDQ23

Differential

T (LVDS)*

C (LVDS)*

T

Bank

7

-

Dual Function

Differential

K5

L5

PL23A

PL23B

PL24A

VCCIO7

PL24B

PL25A

PL25B

PL26A

GNDIO7

PL26B

PL28A

PL28B

PL29A

PL29B

VCCIO7

PL30A

PL30B

PL31A

PL31B

GNDIO7

PL32A

PL32B

PL33A

VCCIO7

PL33B

PL34A

PL34B

PL35A

GNDIO7

PL35B

PL37A

PL37B

PL38A

PL38B

PL39A

VCCIO6

PL39B

PL40A

NC

7

-

PL27A

PL27B

PL28A

VCCIO7

PL28B

PL29A

PL29B

PL30A

GNDIO7

PL30B

PL32A

PL32B

PL33A

PL33B

VCCIO7

PL34A

PL34B

PL35A

PL35B

GNDIO7

PL36A

PL36B

PL37A

VCCIO7

PL37B

PL38A

PL38B

PL39A

GNDIO7

PL39B

PL41A

PL41B

PL42A

PL42B

PL43A

VCCIO6

PL43B

PL44A

PL44B

PL45A

GNDIO6

PL45B

PL46A

PL46B

VCCIO6

PL48A

PL48B

PL49A

PL49B

LDQS27

LDQ27

T*

C*

T

K4

LDQ23

VCCIO

L4

LDQ23

C

LDQ27

C

T*

C*

T

K3

T (LVDS)*

C (LVDS)*

T

L3

J1

GNDIO

K2

7

-

LDQ23

C

7

-

LDQ27

C

T*

C*

T

K1

LUM1_SPLLT_IN_A/LDQ32

LUM1_SPLLC_IN_A/LDQ32

LUM1_SPLLT_FB_A/LDQ32

LUM1_SPLLC_FB_A/LDQ32

T (LVDS)*

LUM3_SPLLT_IN_A/LDQ36

LUM3_SPLLC_IN_A/LDQ36

LUM3_SPLLT_FB_A/LDQ36

LUM3_SPLLC_FB_A/LDQ36

L1

C (LVDS)*

K8

T

M5

C

VCCIO

M4

LDQ32

T (LVDS)*

LDQ36

T*

C*

T

M3

C (LVDS)*

L8

T

M6

C

GNDIO

M1

7

-

LDQS32

LDQ32

T (LVDS)*

C (LVDS)*

T

7

-

LDQS36

LDQ36

T*

C*

T

N1

N3

VCCIO

N2

LDQ32

C

LDQ36

C

T*

C*

T

N5

T (LVDS)*

C (LVDS)*

T

N4

LDQ32

LDQ36

M7

PCLKT7_0/LDQ32

PCLKT7_0/LDQ36

GNDIO

M8

7

6

-

PCLKC7_0/LDQ32

PCLKT6_0

C

T (LVDS)*

C (LVDS)*

T

7

6

-

PCLKC7_0/LDQ36

PCLKT6_0

C

T*

C*

T

P3

P2

PCLKC6_0

VREF2_6

PCLKC6_0

VREF2_6

P5

N6

VREF1_6

C

VREF1_6

C

P4

T (LVDS)*

T*

VCCIO

R3

C (LVDS)*

T

C*

T

P6

N7

C

P1

PL41A

GNDIO6

PL41B

PL42A

PL42B

VCCIO6

PL44A

PL44B

PL45A

PL45B

6

-

LLM2_SPLLT_IN_A

T (LVDS)*

LLM3_SPLLT_IN_A

T*

GNDIO

R1

6

LLM2_SPLLC_IN_A

LLM2_SPLLT_FB_A

LLM2_SPLLC_FB_A

C (LVDS)*

6

LLM3_SPLLC_IN_A

LLM3_SPLLT_FB_A

LLM3_SPLLC_FB_A

C*

T

N8

T

R5

C

VCCIO

T3

LDQ48

T (LVDS)*

LDQ52

T*

C*

T

T4

C (LVDS)*

P8

T

R6

C

4-168

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

6

-

Dual Function

Differential

VCCIO

T1

VCCIO6

PL46A

PL46B

PL47A

PL47B

GNDIO6

PL48A

PL48B

PL49A

VCCIO6

PL49B

PL50A

PL50B

PL51A

GNDIO6

PL51B

PL55A

VCCIO6

PL55B

-

6

-

VCCIO6

PL50A

LDQ48

T (LVDS)*

LDQ52

T*

C*

T

U1

C (LVDS)*

PL50B

R7

T

PL51A

T5

C

PL51B

C

GNDIO

U3

GNDIO6

PL52A

6

-

LDQS48

LDQ48

T (LVDS)*

C (LVDS)*

T

6

-

LDQS52

LDQ52

T*

C*

T

U4

PL52B

U5

PL53A

VCCIO

U6

VCCIO6

PL53B

LDQ48

C

LDQ52

C

T*

C*

T

U2

T (LVDS)*

C (LVDS)*

T

PL54A

V1

PL54B

W2

PL55A

GNDIO

V2

GNDIO6

PL55B

6

-

LDQ48

LDQ57

C

6

-

LDQ52

C

V4

T (LVDS)*

PL59A

T*

VCCIO

V3

VCCIO6

PL59B

LDQ57

C (LVDS)*

C*

T*

-

GNDIO6

PL62A

W4

PL57A

GNDIO6

PL57B

PL58A

PL58B

VCCIO6

PL59A

PL59B

PL60A

PL60B

GNDIO6

LLM0_PLLCAP

PL62A

PL62B

PL63A

PL63B

VCCIO6

PL64A

PL64B

NC

6

-

LLM0_GPLLT_IN_A**/LDQS57**** T (LVDS)*

6

-

LLM0_GPLLT_IN_A

GNDIO

W3

GNDIO6

PL62B

6

-

LLM0_GPLLC_IN_A**/LDQ57

LLM0_GPLLT_FB_A/LDQ57

LLM0_GPLLC_FB_A/LDQ57

C (LVDS)*

6

-

LLM0_GPLLC_IN_A

LLM0_GPLLT_FB_A

LLM0_GPLLC_FB_A

C*

T

W1

T

PL63A

Y1

C

PL63B

C

VCCIO

AA1

AB1

U7

VCCIO6

PL64A

LLM0_GDLLT_IN_A**/LDQ57

LLM0_GDLLC_IN_A**/LDQ57

LLM0_GDLLT_FB_A/LDQ57

LLM0_GDLLC_FB_A/LDQ57

T (LVDS)*

LLM0_GDLLT_IN_A

LLM0_GDLLC_IN_A

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T*

C*

T

C (LVDS)*

PL64B

T

PL65A

V6

C

PL65B

C

GNDIO

T8

GNDIO6

LLM0_PLLCAP

PL67A

6

-

6

-

W5

LDQ66

T (LVDS)*

LDQ71

T*

C*

T

Y4

C (LVDS)*

PL67B

U8

T

PL68A

W6

C

PL68B

C

VCCIO

Y3

VCCIO6

PL69A

LDQ66

T (LVDS)*

C (LVDS)*

LDQ71

T*

C*

T

AA3

V7

PL69B

PL70A

Y5

PL65B

GNDIO6

PL66A

PL66B

PL67A

VCCIO6

PL67B

PL68A

PL68B

6

-

LDQ66

C

PL70B

C

GNDIO

AB2

AA4

Y6

GNDIO6

PL71A

6

LDQS66

LDQ66

T (LVDS)*

C (LVDS)*

T

6

LDQS71

LDQ71

T*

C*

T

PL71B

PL72A

VCCIO

U9

VCCIO6

PL72B

LDQ66

C

LDQ71

C

AA5

AA6

T (LVDS)*

C (LVDS)*

PL73A

T*

C*

PL73B

4-169

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

6

-

Dual Function

Differential

Y7

GNDIO

V9

PL69A

GNDIO6

PL69B

TCK

6

-

LDQ66

T

PL74A

GNDIO6

PL74B

TCK

LDQ71

T

6

-

LDQ66

C

6

-

C

AC3

W8

TDI

-

TDI

-

AC4

V8

TMS

-

TMS

-

TDO

-

TDO

-

AA7

VCCJ

-

VCCJ

-

AB6

PB2A

5

-

BDQ6

T

C

T

PB2A

5

-

BDQ6

T

C

T

Y8

PB2B

AD1

AD2

AC5

AA8

PB3A

PB3B

C

T

PB3B

C

T

PB4A

PB4B

C

PB4B

C

VCCIO

AC6

W9

VCCIO5

PB5A

VCCIO5

PB5A

BDQ6

T

C

T

BDQ6

T

C

T

PB5B

AB7

PB6A

BDQS6

PB6A

BDQS6

GNDIO

Y9

GNDIO5

PB6B

GNDIO5

PB6B

5

-

BDQ6

C

T

5

-

BDQ6

C

T

AD3

AD4

AA9

PB7A

PB7B

C

T

PB7B

C

T

PB8A

W10

VCCIO

AC7

Y10

PB8B

C

PB8B

C

VCCIO5

PB9A

VCCIO5

PB9A

BDQ6

T

C

T

BDQ6

T

C

T

PB9B

AE2

PB10A

PB10B

GNDIO5

PB11A

PB11B

PB12A

PB12B

PB13A

PB13B

VCCIO5

PB14A

PB14B

PB15A

GNDIO5

PB15B

PB16A

PB16B

PB17A

PB17B

VCCIO5

PB18A

PB18B

PB10A

PB10B

GNDIO5

PB11A

PB11B

PB12A

PB12B

PB13A

PB13B

VCCIO5

PB14A

PB14B

PB15A

GNDIO5

PB15B

PB16A

PB16B

PB17A

PB17B

VCCIO5

PB18A

PB18B

AD5

GNDIO

AE4

C

5

-

BDQ15

T

C

T

5

-

BDQ15

T

C

T

AE3

W11

AB8

C

T

C

T

AE5

AD6

VCCIO

AA10

AC8

W12

GNDIO

AC9

W13

AB10

AF3

C

BDQ15

T

C

T

BDQ15

T

C

T

BDQS15

5

BDQ15

C

T

5

BDQ15

C

T

C

T

C

T

AF4

C

VCCIO

AF5

BDQ15

T

BDQ15

T

AF6

C

4-170

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

5

-

Dual Function

Differential

Y12

GNDIO

AB11

-

PB19A

GNDIO5

PB19B

-

5

-

BDQ15

T

PB19A

GNDIO5

PB19B

VCCIO5

GNDIO5

PB29A

PB29B

PB30A

PB30B

PB31A

VCCIO5

PB31B

PB32A

PB32B

PB33A

GNDIO5

PB33B

PB34A

PB34B

PB35A

VCCIO5

PB35B

PB36A

PB36B

PB37A

GNDIO5

PB37B

VCCIO5

GNDIO5

PB42A

PB42B

PB43A

PB43B

PB44A

PB44B

VCCIO5

GNDIO5

PB49A

VCCIO4

PB49B

PB50A

PB50B

PB51A

GNDIO4

PB51B

VCCIO4

GNDIO4

PB56A

PB56B

BDQ15

T

5

-

BDQ15

C

5

-

C

-

AD7

PB20A

PB20B

PB21A

PB21B

PB22A

VCCIO5

PB22B

PB23A

PB23B

PB24A

GNDIO5

PB24B

PB25A

PB25B

PB26A

VCCIO5

PB26B

PB27A

PB27B

PB28A

GNDIO5

PB28B

VCCIO5

GNDIO5

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

VCCIO5

GNDIO5

PB40A

VCCIO4

PB40B

PB57A

PB41B

PB42A

GNDIO4

PB42B

VCCIO4

GNDIO4

PB65A

PB65B

5

-

BDQ24

T

C

T

C

T

5

-

BDQ33

T

C

T

C

T

AF7

AD8

AA12

AE8

VCCIO

AF8

BDQ24

BDQS24

C

T

C

T

BDQ33

BDQS33

C

T

C

T

AD9

AC10

AC11

GNDIO

AB12

AD10

Y13

5

-

BDQ24

C

T

C

T

5

-

BDQ33

C

T

C

T

AF9

VCCIO

AE9

BDQ24

C

T

C

T

BDQ33

C

T

C

T

AF10

AE10

AD11

GNDIO

AF11

VCCIO

GNDIO

AA13

AB13

W14

5

-

BDQ24

C

5

-

BDQ33

C

5

-

BDQS33****

BDQ33

T

C

T

5

-

BDQS42****

BDQ42

T

C

T

VREF2_5/BDQ33

VREF1_5/BDQ33

PCLKT5_0/BDQ33

PCLKC5_0/BDQ33

VREF2_5/BDQ42

VREF1_5/BDQ42

PCLKT5_0/BDQ42

PCLKC5_0/BDQ42

AC12

AF12

AD12

VCCIO

GNDIO

AC13

VCCIO

Y14

C

T

C

T

C

4

-

PCLKT4_0/BDQ42

T

4

-

PCLKT4_0/BDQ51

T

PCLKC4_0/BDQ42

BDQ60

C

T

C

T

PCLKC4_0/BDQ51

VREF2_4/BDQ51

VREF1_4/BDQ51

BDQS51****

C

T

C

T

AB20

AC14

AB14

GNDIO

AA14

VCCIO

GNDIO

W17

VREF1_4/BDQ42

BDQS42****

4

-

BDQ42

C

4

-

BDQ51

C

4

BDQ69

T

4

BDQ60

T

AA19

C

4-171

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

BDQ51

Differential

Bank

4

Dual Function

Differential

AC15

Y18

PB48A

PB68B

PB49A

PB49B

VCCIO4

PB60A

PB50B

GNDIO4

PB51A

PB59B

PB52A

PB52B

PB61A

PB61B

-

4

-

T

C

T

PB57A

PB57B

BDQ60

T

C

T

BDQ69

4

AB15

AC16

VCCIO

AA17

AB16

GNDIO

AA15

W16

BDQ51

PB58A

4

BDQ51

C

PB58B

4

C

VCCIO4

4

BDQS60****

BDQ51

T

PB59A

4

BDQ60

T

C

PB59B

4

C

GNDIO4

-

4

-

BDQS51****

BDQ60

T

C

T

PB60A

4

BDQS60

BDQ60

T

C

T

PB60B

4

Y15

BDQ51

PB61A

4

AC17

AA18

Y17

BDQ51

C

T

PB61B

4

C

T

BDQ60

PB62A

4

BDQ60

C

PB62B

4

C

-

VCCIO4

4

GNDIO

W15

GNDIO4

PB54A

PB54B

GNDIO4

VCCIO4

PB73A

PB73B

GNDIO4

VCC

-

4

-

BDQ51

T

PB63A

4

BDQ60

T

AB17

GNDIO

VCCIO

V17

C

PB63B

4

C

GNDIO4

-

4

-

VCCIO4

4

BDQ69

T

PB72A

4

BDQ69

T

AA20

GNDIO

AD13

AF14

AE13

AE14

AD16

AF17

AF16

AE17

AD17

AE18

AD18

AF18

AD14

AE15

AD15

AF15

AD19

AC19

AB19

AE19

AF23

AD23

AE23

AD24

AF20

AD20

C

PB72B

4

C

GNDIO4

-

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

LRC_SQ_VCCAUX33

LRC_SQ_HDINP1

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

13

PB47A

NC

4

-

BDQ51

VREF2_4/BDQ42

BDQ51

T

C

T

PB41A

VCC

4

-

PB51B

NC

4

-

C

T

PB50A

VCC

4

-

BDQ51

C

T

PB53B

NC

4

-

BDQ51

C

T

PB53A

VCC

4

-

BDQ51

PB48B

NC

4

-

BDQ51

C

T

PB47B

VCC

4

-

BDQ51

PB57B

PB59A

VCCAUX

PB64A

NC

4

-

BDQ60

C

T

C

4

-

BDQ60

BDQ69

BDQ51

T

C

T

C

T

PB66B

VCC

4

-

PB55A

NC

4

-

4-172

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

13

8

Dual Function

Differential

AE20

AD21

AE21

AF22

AF21

AD22

AE24

AE25

AF24

AD25

AA21

AA22

AB23

AC26

AB24

AA23

AB25

GNDIO

Y19

PB55B

VCC

4

-

BDQ51

C

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

C

PB63B

NC

4

-

BDQ60

BDQ69

C

T

C

T

C

T

C

T

PB62A

VCC

4

-

PB67B

NC

4

-

PB67A

VCC

4

-

CFG2

8

-

CFG1

8

CFG0

8

PROGRAMN

CCLK

PROGRAMN

CCLK

8

INITN

8

DONE

GNDIO8

PR68B

PR68A

PR67B

PR67A

VCCIO8

PR66B

PR66A

PR65B

GNDIO8

PR65A

PR64B

PR64A

PR63B

VCCIO8

PR63A

DONE

8

GNDIO8

-

8

-

WRITEN***

CS1N***

C

T

C

T

WRITEN***

8

Y21

CS1N***

8

AB26

Y22

CSN***

8

D0/SPIFASTN***

8

VCCIO

W19

8

D1***

D2***

D3***

C

T

D1***

D2***

D3***

8

Y20

8

W22

C

8

GNDIO

W18

-

8

D4***

D5***

D6***

D7***

T

C

T

D4***

D5***

8

Y23

8

AA24

W21

D6***

8

C

D7***

8

VCCIO

V20

VCCIO8

DI/CSSPI0N***

8

DI/CSSPI0N***

DOUT/CSON/CSSPI1N***

BUSY/SISPI***

T

C

T

8

DOUT/CSON/

CSSPI1N***

W23

PR62B

8

Y24

V19

PR62A

RLM0_PLLCAP

PR60B

8

3

-

BUSY/SISPI***

RLM0_PLLCAP

PR65B

8

3

-

V21

RLM0_GDLLC_FB_A

C

RLM0_GDLLC_FB_A

C

GNDIO

U19

GNDIO3

PR60A

GNDIO3

PR65A

3

-

RLM0_GDLLT_FB_A/RDQ57

RLM0_GDLLC_IN_A**/RDQ57

RLM0_GDLLT_IN_A**/RDQ57

RLM0_GPLLC_IN_A**/RDQ57

T

3

-

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A

RLM0_GDLLT_IN_A

RLM0_GPLLC_IN_A

T

C*

T*

C

AA26

Y26

PR59B

C (LVDS)*

T (LVDS)*

C

PR64B

PR59A

PR64A

V23

PR58B

PR63B

VCCIO

U20

VCCIO3

PR58A

VCCIO3

PR63A

RLM0_GPLLT_IN_A**/RDQ57

RLM0_GPLLC_FB_A/RDQ57

RLM0_GPLLT_FB_A/RDQS57

T

RLM0_GPLLT_IN_A

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

T

W24

V24

PR57B

C (LVDS)*

T (LVDS)*

PR62B

C*

T*

PR57A

PR62A

GNDIO

U21

GNDIO3

PR56A

GNDIO3

PR60A

3

RDQ57

T

3

T

W25

PR55B

C (LVDS)*

PR59B

C*

4-173

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

3

-

Dual Function

Differential

W26

VCCIO

U18

PR55A

VCCIO3

PR54B

PR54A

PR53B

PR53A

PR51B

PR51A

GNDIO3

PR50B

PR50A

PR49B

PR49A

VCCIO3

PR48B

PR48A

PR47B

GNDIO3

PR47A

PR46B

PR46A

PR45B

VCCIO3

PR45A

PR44B

PR44A

-

3

-

RDQ57

T (LVDS)*

PR59A

VCCIO3

PR58B

PR58A

PR57B

PR57A

PR55B

PR55A

GNDIO3

PR54B

PR54A

PR53B

PR53A

VCCIO3

PR52B

PR52A

PR51B

GNDIO3

PR51A

PR50B

PR50A

PR49B

VCCIO3

PR49A

PR48B

PR48A

GNDIO3

PR46B

VCCIO3

PR46A

PR45B

PR45A

GNDIO3

PR44B

PR44A

PR43B

PR43A

VCCIO3

PR42B

PR42A

PR41B

PR41A

PR39B

PR39A

GNDIO2

PR38B

PR38A

PR37B

PR37A

T*

RDQ57

RDQ48

C

T

U22

T

V25

C (LVDS)*

C*

T*

C

V26

T (LVDS)*

U24

C

T

RDQ52

T24

T

GNDIO

T22

3

-

RDQ48

C (LVDS)*

3

-

RDQ52

C*

T*

C

T23

T (LVDS)*

U25

C

T

U26

T

VCCIO

T19

RDQ48

RDQS48

RDQ48

C (LVDS)*

T (LVDS)*

C

RDQ52

RDQS52

RDQ52

C*

T*

C

R19

R21

GNDIO

R20

3

-

RDQ48

T

3

-

RDQ52

T

C*

T*

C

T26

C (LVDS)*

T (LVDS)*

C

R26

P21

VCCIO

P19

RDQ48

T

RDQ52

T

R23

C (LVDS)*

T (LVDS)*

C*

T*

R24

-

R22

PR42B

VCCIO3

PR42A

PR41B

PR41A

GNDIO3

PR40B

PR40A

PR39B

PR39A

VCCIO3

PR38B

PR38A

PR37B

PR37A

PR35B

PR35A

GNDIO2

PR34B

PR34A

PR33B

PR33A

3

-

RLM2_SPLLC_FB_A

C

3

-

RLM3_SPLLC_FB_A

C

VCCIO

N19

RLM2_SPLLT_FB_A

RLM2_SPLLC_IN_A

RLM2_SPLLT_IN_A

T

RLM3_SPLLT_FB_A

RLM3_SPLLC_IN_A

RLM3_SPLLT_IN_A

T

P23

C (LVDS)*

T (LVDS)*

C*

T*

P24

GNDIO

N21

3

2

-

C

3

2

-

C

T

P22

T

N20

C (LVDS)*

T (LVDS)*

C*

T*

N22

VCCIO

P25

VREF2_3

VREF1_3

C

VREF2_3

VREF1_3

C

T

P26

T

M21

N23

PCLKC3_0

C (LVDS)*

PCLKC3_0

C*

T*

C

PCLKT3_0

T (LVDS)*

PCLKT3_0

N24

PCLKC2_0/RDQ32

PCLKT2_0/RDQ32

C

T

PCLKC2_0/RDQ36

PCLKT2_0/RDQ36

N25

T

GNDIO

M22

M24

M23

N26

2

RDQ32

C (LVDS)*

2

RDQ36

C*

T*

C

T (LVDS)*

C

T

4-174

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

2

-

Dual Function

Differential

VCCIO

L22

VCCIO2

PR32B

PR32A

PR31B

GNDIO2

PR31A

PR30B

PR30A

PR29B

VCCIO2

PR29A

PR28B

PR28A

PR26B

PR26A

GNDIO2

PR25B

PR25A

PR24B

PR24A

VCCIO2

PR23B

PR23A

PR22B

GNDIO2

PR22A

PR21B

PR21A

PR20B

VCCIO2

PR20A

PR19B

PR19A

GNDIO2

PR18B

PR18A

PR17B

PR17A

VCCIO2

PR16B

PR16A

PR15B

PR15A

GNDIO2

PR14B

PR14A

-

2

-

VCCIO2

PR36B

PR36A

PR35B

GNDIO2

PR35A

PR34B

PR34A

PR33B

VCCIO2

PR33A

PR32B

PR32A

PR30B

PR30A

GNDIO2

PR29B

PR29A

PR28B

PR28A

VCCIO2

PR27B

PR27A

PR26B

GNDIO2

PR26A

PR25B

PR25A

PR24B

VCCIO2

PR24A

PR23B

PR23A

GNDIO2

PR21B

PR21A

PR20B

PR20A

VCCIO2

PR19B

PR19A

PR18B

PR18A

GNDIO2

PR14B

PR14A

VCCIO2

PR13B

PR13A

RDQ32

RDQS32

RDQ32

C (LVDS)*

T (LVDS)*

C

RDQ36

RDQS36

RDQ36

C*

T*

C

L24

L23

GNDIO

M20

M26

L26

2

-

RDQ32

T

2

-

RDQ36

T

C*

T*

C

C (LVDS)*

T (LVDS)*

C

RDQ32

RDQ36

K22

RUM1_SPLLC_FB_A/RDQ32

RUM3_SPLLC_FB_A/RDQ36

VCCIO

M19

K25

RUM1_SPLLT_FB_A/RDQ32

RUM1_SPLLC_IN_A/RDQ32

RUM1_SPLLT_IN_A/RDQ32

RDQ23

T

RUM3_SPLLT_FB_A/RDQ36

RUM3_SPLLC_IN_A/RDQ36

RUM3_SPLLT_IN_A/RDQ36

RDQ27

T

C*

T*

C

C (LVDS)*

K26

T (LVDS)*

K24

C

T

K23

RDQ23

RDQ27

T

GNDIO

L19

2

-

RDQ23

C (LVDS)*

2

-

RDQ27

C*

T*

C

K21

T (LVDS)*

J23

C

T

J24

T

VCCIO

K20

RDQ23

RDQS23

RDQ23

C (LVDS)*

T (LVDS)*

C

RDQ27

RDQS27

RDQ27

C*

T*

C

J21

H21

GNDIO

K18

2

-

RDQ23

T

2

-

RDQ27

T

C*

T*

C

H22

C (LVDS)*

T (LVDS)*

C

J20

J25

VCCIO

J26

RDQ23

T

RDQ27

T

G21

J19

C (LVDS)*

T (LVDS)*

C*

T*

GNDIO

H23

2

-

RDQ15

C

2

-

C

T

H24

T

H25

C (LVDS)*

T (LVDS)*

C*

T*

H26

VCCIO

G22

K19

RDQ15

RDQS15

C

T

G24

G23

GNDIO

J18

C (LVDS)*

T (LVDS)*

C*

T*

2

-

RDQ15

C

T

2

C

T

F22

-

F23

PR13B

PR13A

2

RDQ15

C (LVDS)*

T (LVDS)*

C*

T*

F24

4-175

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

VCCIO

H20

-

VCCIO2

PR12B

-

2

-

RUM0_SPLLC_FB_A/RDQ15

C

PR12B

GNDIO2

PR12A

PR11B

PR11A

VCCIO2

PR9B

2

-

RUM0_SPLLC_FB_A

C

F21

PR12A

PR11B

PR11A

-

2

-

RUM0_SPLLT_FB_A/RDQ15

RUM0_SPLLC_IN_A/RDQ15

RUM0_SPLLT_IN_A/RDQ15

T

2

-

RUM0_SPLLT_FB_A

RUM0_SPLLC_IN_A

RUM0_SPLLT_IN_A

T

G26

F26

C (LVDS)*

T (LVDS)*

C*

T*

-

E24

GNDIO

E23

VCCIO

H19

PR9B

GNDIO2

PR9A

VCCIO4

XRES

2

-

VREF2_2

VREF1_2

C

T

VREF2_2

VREF1_2

C

T

GNDIO2

PR9A

2

4

-

2

-

VCCIO2

XRES

URC_SQ_VCCRX

0

C25

12

URC_SQ_VCCRX0

12

A24

B25

B24

URC_SQ_HDINP0 12

URC_SQ_VCCIB0 12

URC_SQ_HDINN0 12

T

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

12

T

C

URC_SQ_VCCTX

C22

A21

A22

B21

C21

B20

C20

A20

C24

12

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

12

0

URC_SQ_HDOUT

12

P0

T

C

T

C

T

URC_SQ_VCCOB

12

0

URC_SQ_HDOUT

12

N0

URC_SQ_VCCTX

12

1

URC_SQ_HDOUT

12

N1

URC_SQ_VCCOB

12

1

URC_SQ_HDOUT

12

P1

URC_SQ_VCCRX

12

1

B23

C23

A23

URC_SQ_HDINN1 12

URC_SQ_VCCIB1 12

URC_SQ_HDINP1 12

C

T

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

C

T

URC_SQ_VCCAU

B19

E19

D19

12

URC_SQ_VCCAUX33 12

X33

URC_SQ_REFCL

12

C

T

URC_SQ_REFCLKN

URC_SQ_REFCLKP

12

C

T

KN

URC_SQ_REFCL

12

KP

C19

A15

C15

B15

URC_SQ_VCCP

12

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

12

URC_SQ_HDINP2 12

URC_SQ_VCCIB2 12

URC_SQ_HDINN2 12

T

C

URC_SQ_VCCRX

C14

A18

C18

B18

12

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

12

2

URC_SQ_HDOUT

12

P2

T

URC_SQ_VCCOB

12

2

URC_SQ_HDOUT

12

C

N2

4-176

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

URC_SQ_VCCTX

2

C17

B17

A16

A17

C16

12

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

12

URC_SQ_HDOUT

N3

C

12

C

URC_SQ_VCCOB

3

URC_SQ_HDOUT

P3

T

URC_SQ_VCCTX

3

B14

B13

A14

URC_SQ_HDINN3 12

URC_SQ_VCCIB3 12

URC_SQ_HDINP3 12

C

T

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

12

C

T

URC_SQ_VCCRX

C13

12

URC_SQ_VCCRX3

12

3

-

GNDIO1

VCCIO1

PT55B

PT55A

GNDIO1

PT54B

PT54A

PT53B

PT53A

VCCIO1

PT52B

PT52A

PT51B

PT51A

GNDIO1

PT50B

PT50A

PT49B

PT49A

VCCIO1

PT48B

PT48A

PT47B

PT47A

PT46B

GNDIO0

PT46A

PT45B

PT45A

PT44B

VCCIO0

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

-

1

-

E17

PT46B

PT46A

GNDIO1

PT45B

PT45A

PT44B

PT44A

VCCIO1

PT43B

PT43A

PT42B

PT42A

GNDIO1

PT41B

PT41A

PT40B

PT40A

VCCIO1

PT39B

PT39A

PT38B

PT38A

PT37B

GNDIO0

PT37A

PT36B

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

PT32B

1

-

C

T

C

T

D17

GNDIO

F17

1

-

C

T

C

T

1

-

C

T

C

T

D16

F19

F18

VCCIO

E16

C

T

C

T

C

T

C

T

D15

G18

E15

GNDIO

G17

E14

1

0

-

C

T

C

T

1

0

-

C

T

C

T

D14

D13

VCCIO

F15

VREF2_1

VREF1_1

C

T

VREF2_1

VREF1_1

C

T

E12

H17

E13

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

C12

GNDIO

G15

C11

F14

C

0

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

0

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

A12

C

VCCIO

A11

T

C

T

C

T

D12

H16

H18

H15

A10

C

T

C

T

C

4-177

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

-

Dual Function

Differential

GNDIO

B10

D11

VCCIO

G14

E11

F13

D10

H14

GNDIO

VCCIO

A9

GNDIO0

PT32A

PT31B

VCCIO0

PT31A

PT30B

PT30A

PT29B

PT29A

GNDIO0

VCCIO0

PT24B

PT23B

GNDIO0

PT23A

PT22B

PT22A

VCCIO0

PT21B

PT21A

PT20B

PT20A

PT19B

GNDIO0

PT19A

PT18B

PT18A

PT17B

PT17A

VCCIO0

PT16B

PT16A

PT15B

PT15A

GNDIO0

PT14B

PT14A

PT13B

PT13A

VCCIO0

PT12B

PT12A

PT11B

PT11A

PT10B

GNDIO0

PT10A

PT9B

-

GNDIO0

PT41A

PT40B

VCCIO0

PT40A

PT39B

PT39A

PT38B

PT38A

GNDIO0

VCCIO0

PT24B

PT23B

GNDIO0

PT23A

PT22B

PT22A

VCCIO0

PT21B

PT21A

PT20B

PT20A

PT19B

GNDIO0

PT19A

PT18B

PT18A

PT17B

PT17A

VCCIO0

PT16B

PT16A

PT15B

PT15A

GNDIO0

PT14B

PT14A

PT13B

PT13A

VCCIO0

PT12B

PT12A

PT11B

PT11A

PT10B

GNDIO0

PT10A

PT9B

0

-

T

0

-

T

C

T

C

T

C

T

C

T

C

T

0

-

0

-

C

C10

GNDIO

E8

0

-

T

C

T

0

-

T

C

T

B9

A8

VCCIO

F12

E10

G13

C9

C

T

C

T

C

T

C

T

B8

C

GNDIO

A7

0

-

T

C

T

C

T

0

-

T

C

T

C

T

D9

H13

D6

C7

VCCIO

C8

C

T

C

T

C

T

C

T

G12

D8

H12

GNDIO

A6

0

-

C

T

C

T

0

-

C

T

C

T

A5

A4

A3

VCCIO

C6

C

T

C

T

F10

D7

C

T

C

T

H11

D5

C

GNDIO

E6

0

T

C

T

0

T

C

T

G10

F9

PT9A

4-178

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

0

-

Dual Function

Differential

H10

VCCIO

E7

PT8B

VCCIO0

PT8A

PT7B

PT7A

PT6B

PT6A

PT5B

GNDIO0

PT5A

PT4B

VCCIO0

PT4A

PT3B

PT3A

PT2B

PT2A

VCC

0

-

C

PT8B

VCCIO0

PT8A

PT7B

PT7A

PT6B

PT6A

PT5B

GNDIO0

PT5A

PT4B

VCCIO0

PT4A

PT3B

PT3A

PT2B

PT2A

VCC

C

T

C

T

C

T

B3

C5

B2

C

T

C

T

C4

G9

C

GNDIO

F7

0

-

T

0

-

T

C3

C

VCCIO

D4

T

C

T

C

T

C

T

C

T

J10

F8

G8

G7

L12

L13

L14

L15

M11

M12

M15

M16

N11

N16

P11

P16

R11

R12

R15

R16

T12

T13

T14

T15

B12

B7

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

0

1

2

VCCIO0

VCCIO1

VCCIO2

0

1

2

F11

J13

K12

D18

F16

J14

K15

G25

L21

M17

4-179

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank Dual Function

Differential

Bank

2

3

4

5

6

7

8

-

Dual Function

Differential

M25

N18

P18

R17

R25

T21

Y25

AA16

AC18

U15

V14

AA11

V13

AE12

AE7

U12

P9

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

2

3

4

5

6

7

8

-

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

R10

R2

T6

Y2

G2

L6

M10

M2

N9

AC24

U17

J11

J12

J15

J16

L18

L9

-

M18

M9

-

R18

R9

-

T18

T9

-

V11

V12

V15

V16

A13

A19

A2

-

GND

-

GND

-

GND

-

GND

-

A25

AA2

GND

-

GND

-

GND

-

GND

-

4-180

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

AA25

AB18

AB22

AB5

AB9

AE1

AE11

AE16

AE22

AE26

AE6

AF13

AF19

AF2

AF25

B1

GND

-

GND

-

B11

B16

B22

B26

B6

E18

E22

E5

E9

F2

F25

G11

G16

J22

J5

K11

K13

K14

K16

L10

L11

L16

L17

L2

L20

L25

L7

M13

M14

N10

N12

N13

N14

4-181

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank Dual Function

Differential

Bank

Dual Function

Differential

N15

N17

P10

P12

P13

P14

P15

P17

R13

R14

T10

T11

T16

T17

T2

GND

NC

-

GND

NC

-

T20

T25

T7

U11

U13

U14

U16

V22

V5

Y11

Y16

AB3

AB4

AC1

AC2

B4

NC

B5

NC

C26

D20

D21

D22

D23

D24

D25

D26

E20

E21

E25

E26

F20

G20

K10

K17

R4

NC

4-182

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA

LFE2M35E/SE

LFE2M50E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

U10

U23

V10

W7

NC

-

NC

-

NC

-

NC

-

NC

AB21

AC20

AC21

AC22

AC23

AC25

AD26

W20

H7

PB69B

4

-

BDQ69

BDQ60

C

T

C

NC

PB58A

NC

PB63A

BDQ60

NC

PB69A

BDQS69****

BDQ69

NC

PB71A

NC

PB71B

BDQ69

NC

PB70B

BDQ69

NC

PB72B

BDQ69

NC

L_VCCPLL

R_VCCPLL

L_VCCPLL

R_VCCPLL

K6

-

P7

-

R8

-

V18

P20

J17

-

G19

-

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

*** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices

(ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100).

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-183

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

7

-

Dual Function

Differential

VCCIO

D2

D3

GNDIO

J8

VCCIO7

PL9A

PL9B

GNDIO7

PL11A

PL11B

PL12A

PL12B

GNDIO7

-

7

VCCIO7

PL9A

7

-

VREF2_7/LDQ6

VREF1_7/LDQ6

T

VREF2_7

VREF1_7

T

C

PL9B

C

GNDIO7

PL11A

PL11B

PL12A

PL12B

-

7

-

LUM0_SPLLT_IN_A

LUM0_SPLLC_IN_A

LUM0_SPLLT_FB_A

LUM0_SPLLC_FB_A

T (LVDS)*

7

-

LUM0_SPLLT_IN_A/LDQ15

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

T (LVDS)*

H7

E3

E4

GNDIO

-

C (LVDS)*

T

C

-

VCCIO7

PL13A

PL13B

PL14A

PL14B

GNDIO7

PL15A

PL15B

PL16A

VCCIO7

PL16B

PL17A

PL17B

PL18A

GNDIO7

PL18B

-

7

-

G6

F5

PL13A

PL13B

PL14A

PL14B

-

7

-

T (LVDS)*

LDQ15

T (LVDS)*

C (LVDS)*

E2

D1

-

T

C

G5

G4

K7

-

NC

-

7

-

LDQS15

LDQ15

T (LVDS)*

C (LVDS)*

T

NC

-

NC

-

K8

E1

F2

NC

-

LDQ15

C

NC

-

T (LVDS)*

C (LVDS)*

T

NC

-

F1

NC

-

G3

-

NC

-

7

-

LDQ15

C

-

VCCIO

H5

H4

J5

VCCIO7

PL15A

PL15B

PL16A

PL16B

GNDIO7

NC

7

-

VCCIO7

PL21A

PL21B

PL22A

PL22B

GNDIO7

PL24A

PL24B

PL25A

PL25B

VCCIO7

PL26A

PL26B

PL27A

PL27B

GNDIO7

PL28A

PL28B

PL29A

VCCIO7

PL29B

PL30A

-

7

-

T (LVDS)*

C (LVDS)*

T

J4

C

GNDIO

G2

G1

L9

-

7

-

LDQ28

T (LVDS)*

NC

-

C (LVDS)*

NC

-

T

L7

NC

-

C

-

K6

K5

L8

NC

-

LDQ28

T (LVDS)*

NC

-

C (LVDS)*

NC

-

T

L6

NC

-

C

-

H3

H2

N8

-

PL18A

PL18B

PL19A

-

7

-

T (LVDS)*

C (LVDS)*

T

7

-

LDQS28

LDQ28

T (LVDS)*

C (LVDS)*

T

M9

J3

PL19B

PL20A

VCCIO7

7

C

LDQ28

C

T (LVDS)*

VCCIO

4-184

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

Differential

C (LVDS)*

T

Bank

7

-

Dual Function

Differential

C (LVDS)*

T

J2

H1

PL20B

PL21A

GNDIO7

PL21B

-

PL30B

PL31A

GNDIO7

PL31B

-

LDQ28

GNDIO

J1

7

-

C

7

-

LDQ28

C

-

L5

PL23A

PL23B

PL24A

PL24B

VCCIO7

PL25A

PL25B

PL26A

PL26B

GNDIO7

PL27A

PL27B

PL28A

VCCIO7

PL28B

PL29A

PL29B

PL30A

GNDIO7

PL30B

PL32A

PL32B

PL33A

PL33B

VCCIO7

PL34A

PL34B

PL35A

PL35B

GNDIO7

PL36A

PL36B

PL37A

VCCIO7

PL37B

PL38A

PL38B

PL39A

GNDIO7

PL39B

PL41A

PL41B

PL42A

7

-

LDQ27

T (LVDS)*

PL33A

PL33B

PL34A

PL34B

VCCIO7

PL35A

PL35B

PL36A

PL36B

GNDIO7

PL37A

PL37B

PL38A

VCCIO7

PL38B

PL39A

PL39B

PL40A

GNDIO7

PL40B

PL42A

PL42B

PL43A

PL43B

VCCIO7

PL44A

PL44B

PL45A

PL45B

GNDIO7

PL46A

PL46B

PL47A

VCCIO7

PL47B

PL48A

PL48B

PL49A

GNDIO7

PL49B

PL51A

PL51B

PL52A

7

-

LDQ37

T (LVDS)*

L4

C (LVDS)*

N9

T

N7

C

VCCIO

K2

LDQ27

T (LVDS)*

LDQ37

T (LVDS)*

K1

C (LVDS)*

P9

T

P7

C

GNDIO

M6

7

-

LDQS27

LDQ27

T (LVDS)*

C (LVDS)*

T

7

-

LDQS37

LDQ37

T (LVDS)*

C (LVDS)*

T

M5

N5

VCCIO

N6

LDQ27

C

LDQ37

C

M4

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

M3

P6

GNDIO

P8

7

LDQ27

C

7

-

LDQ37

C

L3

7

-

LUM3_SPLLT_IN_A/LDQ36 T (LVDS)*

LUM3_SPLLC_IN_A/LDQ36 C (LVDS)*

LUM3_SPLLT_IN_A/LDQ46

LUM3_SPLLC_IN_A/LDQ46

LUM3_SPLLT_FB_A/LDQ46

LUM3_SPLLC_FB_A/LDQ46

T (LVDS)*

L2

C (LVDS)*

P5

LUM3_SPLLT_FB_A/LDQ36

LUM3_SPLLC_FB_A/LDQ36

T

P4

C

VCCIO

L1

LDQ36

T (LVDS)*

LDQ46

T (LVDS)*

M2

C (LVDS)*

R5

T

R4

C

GNDIO

M1

7

-

LDQS36

LDQ36

T (LVDS)*

C (LVDS)*

T

7

-

LDQS46

LDQ46

T (LVDS)*

C (LVDS)*

T

N2

R8

VCCIO

T9

LDQ36

C

LDQ46

C

P3

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

P2

LDQ36

LDQ46

N1

PCLKT7_0/LDQ36

PCLKT7_0/LDQ46

GNDIO

P1

7

6

PCLKC7_0/LDQ36

PCLKT6_0

C

7

6

PCLKC7_0/LDQ46

PCLKT6_0/LDQ55

PCLKC6_0/LDQ55

VREF2_6/LDQ55

C

T5

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

T4

PCLKC6_0

U7

VREF2_6

4-185

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

C

Bank

6

-

Dual Function

Differential

C

T8

R3

PL42B

PL43A

VCCIO6

PL43B

PL44A

PL44B

GNDIO6

-

6

-

VREF1_6

PL52B

PL53A

VCCIO6

PL53B

PL54A

PL54B

GNDIO6

VCCIO6

PL57A

PL57B

PL58A

PL58B

GNDIO6

PL60A

PL60B

PL61A

PL61B

VCCIO6

PL62A

PL62B

PL63A

PL63B

GNDIO6

PL64A

PL64B

PL65A

VCCIO6

PL65B

PL66A

PL66B

PL67A

GNDIO6

PL67B

PL69A

PL69B

PL70A

PL70B

PL71A

VCCIO6

PL71B

PL72A

PL72B

PL73A

GNDIO6

PL73B

PL74A

PL74B

VCCIO6

PL75A

VREF1_6/LDQ55

LDQ55

T (LVDS)*

VCCIO

R2

C (LVDS)*

LDQ55

C (LVDS)*

R1

T

T1

C

GNDIO

-

6

-

T3

PL45A

PL45B

PL46A

PL46B

VCCIO6

PL48A

PL48B

PL49A

PL49B

VCCIO6

PL50A

PL50B

PL51A

PL51B

GNDIO6

PL52A

PL52B

PL53A

VCCIO6

PL53B

PL54A

PL54B

PL55A

GNDIO6

PL55B

PL57A

PL57B

PL58A

PL58B

PL59A

VCCIO6

PL59B

PL60A

PL60B

NC

6

-

LLM3_SPLLT_IN_A

LLM3_SPLLC_IN_A

LLM3_SPLLT_FB_A

LLM3_SPLLC_FB_A

T (LVDS)*

LLM3_SPLLT_IN_A/LDQ55

LLM3_SPLLC_IN_A/LDQ55

LLM3_SPLLT_FB_A/LDQ55

LLM3_SPLLC_FB_A/LDQ55

T (LVDS)*

T2

C (LVDS)*

U9

T

U8

C

VCCIO

U5

LDQ52

T (LVDS)*

6

-

LDQ64

T (LVDS)*

U4

C (LVDS)*

V9

T

V7

C

VCCIO

U3

LDQ52

T (LVDS)*

LDQ64

T (LVDS)*

U2

C (LVDS)*

V8

T

U6

C

GNDIO

U1

6

-

LDQS52

LDQ52

T (LVDS)*

C (LVDS)*

T

6

-

LDQS64

LDQ64

T (LVDS)*

C (LVDS)*

T

V2

V5

VCCIO

V6

LDQ52

C

LDQ64

C

V1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

W1

W5

GNDIO

W6

6

-

LDQ52

C

6

-

LDQ64

LDQ73

C

W3

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

W4

W2

Y4

C

Y1

T (LVDS)*

VCCIO

Y2

C (LVDS)*

LDQ73

LDQS73

C (LVDS)*

Y5

T

C

Y6

C

AA1

GNDIO

AA2

Y3

T (LVDS)*

GNDIO6

NC

-

6

LDQ73

C (LVDS)*

NC

-

T

AB1

-

NC

-

C

-

Y9

NC

-

LDQ73

T (LVDS)*

4-186

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

6

Dual Function

Differential

Y8

Y7

NC

-

PL75B

PL76A

LDQ73

C (LVDS)*

6

T

AA7

-

NC

PL76B

6

C

-

GNDIO6

-

AB2

AB3

AA5

AA6

AB4

-

NC

PL78A

6

LDQ82

T (LVDS)*

C (LVDS)*

T

NC

PL78B

6

NC

PL79A

6

NC

PL79B

6

C

NC

PL80A

6

T (LVDS)*

-

VCCIO6

6

AB5

AA8

AA9

AC1

GNDIO

AC2

AC4

AC3

VCCIO

AC7

AC6

AC5

AD3

GNDIO

AB8

AD2

AD1

AE2

AE1

AF2

AF1

AG1

AH1

AK2

AJ1

AJ2

AH4

AK5

AK4

AJ5

AH5

AJ6

AH6

AK6

AH2

AJ3

AH3

AK3

NC

PL80B

6

LDQ82

C (LVDS)*

NC

PL81A

6

T

NC

PL81B

6

C

PL62A

GNDIO6

PL62B

PL63A

PL63B

VCCIO6

PL64A

PL64B

PL65A

PL65B

GNDIO6

LLM0_PLLCAP

PL67A

PL67B

TCK

6

-

LLM0_GPLLT_IN_A**

T (LVDS)*

PL82A

6

LLM0_GPLLT_IN_A**/LDQS82 T (LVDS)*

GNDIO6

-

6

-

LLM0_GPLLC_IN_A**

LLM0_GPLLT_FB_A

LLM0_GPLLC_FB_A

C (LVDS)*

PL82B

6

LLM0_GPLLC_IN_A**/LDQ82 C (LVDS)*

T

PL83A

6

LLM0_GPLLT_FB_A/LDQ82

LLM0_GPLLC_FB_A/LDQ82

T

C

PL83B

6

C

VCCIO6

6

LLM0_GDLLT_IN_A**

LLM0_GDLLC_IN_A**

LLM0_GDLLT_FB_A

LLM0_GDLLC_FB_A

T (LVDS)*

PL84A

6

LLM0_GDLLT_IN_A**/LDQ82 T (LVDS)*

LLM0_GDLLC_IN_A**/LDQ82 C (LVDS)*

C (LVDS)*

PL84B

6

T

PL85A

6

LLM0_GDLLT_FB_A/LDQ82

LLM0_GDLLC_FB_A/LDQ82

T

C

PL85B

6

C

GNDIO6

-

6

-

LLM0_PLLCAP

PL87A

6

LDQ71

T (LVDS)*

C (LVDS)*

6

T

PL87B

6

C

TCK

-

TDI

-

TDI

-

TMS

-

TMS

-

TDO

-

TDO

-

VCCJ

VCC

-

VCCJ

-

LLC_SQ_VCCRX3

LLC_SQ_HDINP3

LLC_SQ_VCCIB3

LLC_SQ_HDINN3

LLC_SQ_VCCTX3

LLC_SQ_HDOUTP3

LLC_SQ_VCCOB3

LLC_SQ_HDOUTN3

LLC_SQ_VCCTX2

LLC_SQ_HDOUTN2

LLC_SQ_VCCOB2

LLC_SQ_HDOUTP2

LLC_SQ_VCCRX2

LLC_SQ_HDINN2

LLC_SQ_VCCIB2

LLC_SQ_HDINP2

14

PB11A

NC

5

-

BDQ15

T

C

T

C

T

PB11B

VCC

5

-

PB13A

NC

5

-

PB13B

VCC

5

-

C

T

C

T

PB14B

NC

5

-

PB14A

VCC

5

-

PB12B

NC

5

-

C

T

C

T

PB12A

5

4-187

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

14

Dual Function

Differential

AH7

AG7

VCC

PB15A

PB15B

VCCAUX

PB18A

NC

LLC_SQ_VCCP

LLC_SQ_REFCLKP

LLC_SQ_REFCLKN

5

-

BDQS15

BDQ15

T

14

T

AF7

C

14

C

AJ7

LLC_SQ_VCCAUX33 14

AK11

AH11

AJ11

AH12

AK8

5

-

BDQ15

T

C

T

LLC_SQ_HDINP1

LLC_SQ_VCCIB1

LLC_SQ_HDINN1

LLC_SQ_VCCRX1

LLC_SQ_HDOUTP1

LLC_SQ_VCCOB1

LLC_SQ_HDOUTN1

LLC_SQ_VCCTX1

LLC_SQ_HDOUTN0

LLC_SQ_VCCOB0

LLC_SQ_HDOUTP0

LLC_SQ_VCCTX0

LLC_SQ_HDINN0

LLC_SQ_VCCIB0

LLC_SQ_HDINP0

LLC_SQ_VCCRX0

PB30A

14

5

T

C

T

PB18B

VCC

5

-

PB16A

NC

5

-

AH8

AJ8

PB16B

VCC

5

-

C

T

C

T

AH9

AJ9

PB17B

NC

5

-

AK10

AK9

PB17A

VCC

5

-

AH10

AJ12

AJ13

AK12

AH13

AF10

AE8

PB19B

NC

5

-

C

T

C

T

PB19A

VCC

5

-

PB3A

PB3B

PB4A

VCCIO5

PB4B

PB5A

PB5B

PB6A

GNDIO5

PB6B

PB7A

PB7B

PB8A

VCCIO5

PB8B

PB9A

PB9B

PB10A

GNDIO5

PB10B

VCCIO5

PB20A

PB20B

GNDIO5

VCCIO5

PB24A

PB24B

PB25A

-

5

-

BDQ6

T

C

T

BDQ33

T

C

T

PB30B

5

AE11

VCCIO

AD9

PB31A

5

VCCIO5

5

BDQ6

BDQS6

C

T

C

T

PB31B

5

BDQ33

BDQS33

C

T

C

T

AE10

AD10

AE13

GNDIO

AC12

AG2

PB32A

5

PB32B

5

PB33A

5

GNDIO5

-

5

-

BDQ6

C

T

C

T

PB33B

5

BDQ33

C

T

C

T

PB34A

5

AG3

PB34B

5

AD13

VCCIO

AC13

AE14

AC14

AF3

PB35A

5

VCCIO5

5

BDQ6

C

T

C

T

PB35B

5

BDQ33

C

T

C

T

PB36A

5

PB36B

5

PB37A

5

GNDIO

AF4

GNDIO5

-

5

-

BDQ6

C

PB37B

5

BDQ33

C

VCCIO

AG4

-

BDQ24

T

PB38A

5

BDQ42

T

AG5

C

PB38B

5

C

GNDIO

VCCIO

AD11

AF13

AF12

-

5

-

BDQS24****

BDQ24

T

C

T

PB39A

5

BDQ42

T

C

T

PB39B

5

BDQ24

PB40A

5

VCCIO5

5

4-188

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

BDQ24

Differential

Bank

5

-

Dual Function

Differential

AD14

AG8

PB25B

PB26A

PB26B

PB27A

-

5

-

C

T

C

T

PB40B

PB41A

PB41B

PB42A

GNDIO5

-

BDQ42

C

T

C

T

BDQ24

AF8

BDQ24

BDQ42

AE15

-

BDQ24

BDQS42****

VCCIO

AC15

VCCIO

GNDIO

AD15

AF15

AG10

AG9

VCCIO5

PB27B

VCCIO5

GNDIO5

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

VCCIO5

PB41A

PB41B

GNDIO5

PB42A

PB42B

PB43A

PB43B

PB44A

PB44B

VCCIO5

GNDIO5

PB49A

VCCIO4

PB49B

PB50A

PB50B

PB51A

GNDIO4

PB51B

PB52A

PB52B

PB53A

VCCIO4

PB53B

PB54A

PB54B

PB55A

GNDIO4

PB55B

PB56A

PB56B

PB57A

PB57B

5

-

BDQ24

C

PB42B

VCCIO5

GNDIO5

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO5

PB50A

PB50B

GNDIO5

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO5

GNDIO5

PB58A

VCCIO4

PB58B

PB59A

PB59B

PB60A

GNDIO4

PB60B

PB61A

PB61B

PB62A

VCCIO4

PB62B

PB63A

PB63B

PB64A

GNDIO4

PB64B

PB65A

PB65B

PB66A

PB66B

5

-

BDQ42

C

5

-

BDQ42

T

C

T

5

-

BDQ51

T

C

T

C

T

C

T

AH14

AG12

VCCIO

AG15

AG13

GNDIO

AF16

AH15

AC16

AE16

AG11

AF11

VCCIO

GNDIO

AJ14

C

BDQ42

T

BDQ51

T

C

5

BDQS42

BDQ42

T

C

T

5

-

BDQS51

T

C

T

BDQ51

5

-

VREF2_5/BDQ42

VREF1_5/BDQ42

PCLKT5_0/BDQ42

PCLKC5_0/BDQ42

VREF2_5/BDQ51

VREF1_5/BDQ51

PCLKT5_0/BDQ51

PCLKC5_0/BDQ51

C

T

C

T

C

4

-

PCLKT4_0/BDQ51

T

4

-

PCLKT4_0/BDQ60

T

VCCIO

AK14

AK15

AK16

AF18

GNDIO

AD16

AJ15

PCLKC4_0/BDQ51

VREF2_4/BDQ51

VREF1_4/BDQ51

BDQS51

C

T

C

T

PCLKC4_0/BDQ60

VREF2_4/BDQ60

VREF1_4/BDQ60

BDQS60

C

T

C

T

4

-

BDQ51

C

T

C

T

4

-

BDQ60

C

T

C

T

AG16

AE17

VCCIO

AC17

AH16

AK17

AG20

GNDIO

AG21

AG18

AJ16

BDQ51

C

T

C

T

BDQ60

C

T

C

T

4

BDQ51

BDQ60

C

T

4

BDQ60

BDQ69

C

T

C

T

C

T

AF21

AG22

C

4-189

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

4

Dual Function

BDQ60

Differential

Bank

4

Dual Function

Differential

AD17

AF19

VCCIO

GNDIO

AH17

AJ17

PB58A

PB58B

T

PB67A

PB67B

BDQ69

T

4

BDQ60

C

4

C

VCCIO4

4

VCCIO4

4

GNDIO4

-

GNDIO4

-

PB62A

4

BDQ60

T

PB71A

4

BDQ69

T

PB62B

4

C

PB71B

4

C

VCCIO

AF26

AE25

GNDIO

AD24

AE24

AD18

AC18

AE18

AG19

VCCIO

GNDIO

AC19

AD20

AB18

AC20

AE20

AE21

VCCIO

AC23

AD23

GNDIO

AH18

AK19

AJ18

VCCIO4

4

VCCIO4

4

PB64A

4

BDQ60

T

PB73A

4

BDQ69

T

PB64B

4

C

PB73B

4

C

GNDIO4

-

GNDIO4

-

PB65A

4

BDQ69

T

C

T

PB74A

4

BDQ78

T

C

T

PB65B

4

PB74B

4

PB66A

4

PB75A

4

PB66B

4

C

T

PB75B

4

C

T

PB67A

4

PB76A

4

PB67B

4

C

PB76B

4

C

VCCIO4

4

VCCIO4

4

GNDIO4

-

GNDIO4

-

PB69A

4

BDQS69

BDQ69

T

C

T

PB78A

4

BDQS78

BDQ78

T

C

T

PB69B

4

PB78B

4

PB70A

4

PB79A

4

PB70B

4

C

T

PB79B

4

C

T

PB71A

4

PB80A

4

PB71B

4

C

PB80B

4

C

VCCIO4

4

VCCIO4

4

PB72A

4

BDQ69

T

PB81A

4

BDQ78

T

PB72B

4

C

PB81B

4

C

GNDIO4

-

GNDIO4

-

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

LRC_SQ_VCCAUX33

LRC_SQ_HDINP1

13

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

13

T

C

T

C

T

AJ19

AH21

AK22

AK21

AJ22

C

T

C

T

AH22

AJ23

AH23

AK23

AH19

AJ20

C

T

C

T

AH20

AK20

AH24

AG24

AF24

AJ24

T

C

LRC_SQ_VCCAUX33 13

LRC_SQ_HDINP1 13

AK28

T

4-190

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

13

8

Dual Function

Differential

Bank

13

8

Dual Function

Differential

AH28

AJ28

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

C

T

C

T

AH29

AK25

AH25

AJ25

C

T

C

T

AH26

AJ26

AK27

AK26

AH27

AJ29

C

T

C

T

AJ30

AK29

AH30

AG27

AD25

AG28

AG30

AG29

AC24

AF27

GNDIO

AF28

AE26

AB23

AF29

VCCIO

AF30

AD26

AE29

GNDIO

AE30

AD29

AC25

AD30

VCCIO

AA22

CFG1

8

CFG1

8

CFG0

8

CFG0

8

PROGRAMN

CCLK

8

PROGRAMN

CCLK

8

INITN

8

INITN

8

DONE

8

DONE

8

GNDIO8

-

GNDIO8

-

WRITEN***

CS1N***

8

WRITEN***

CS1N***

8

CSN***

8

CSN***

8

D0/SPIFASTN***

VCCIO8

8

D0/SPIFASTN***

VCCIO8

8

D1***

8

D1***

8

D2***

8

D2***

8

D3***

8

D3***

8

GNDIO8

-

GNDIO8

-

D4***

8

D4***

8

D5***

8

D5***

8

D6***

8

D6***

8

D7***

8

D7***

8

VCCIO8

8

VCCIO8

8

DI/CSSPI0N***

8

DI/CSSPI0N***

8

DOUT/CSON/

CSSPI1N***

DOUT/CSON/

CSSPI1N***

AC26

8

AA23

AB22

AC27

GNDIO

AC28

AC29

AC30

AB30

VCCIO

AA30

BUSY/SISPI***

RLM0_PLLCAP

PR65B

8

3

BUSY/SISPI***

RLM0_PLLCAP

PR85B

8

3

-

3

-

RLM0_GDLLC_FB_A

C

RLM0_GDLLC_FB_A/RDQ82

RLM0_GDLLT_FB_A/RDQ82

C

T

GNDIO3

PR65A

GNDIO3

PR85A

3

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A**

RLM0_GDLLT_IN_A**

RLM0_GPLLC_IN_A**

T

3

PR64B

C (LVDS)*

T (LVDS)*

C

PR84B

RLM0_GDLLC_IN_A**/RDQ82 C (LVDS)*

RLM0_GDLLT_IN_A**/RDQ82 T (LVDS)*

PR64A

PR84A

PR63B

PR83B

RLM0_GPLLC_IN_A**/RDQ82

C

VCCIO3

PR63A

VCCIO3

PR83A

RLM0_GPLLT_IN_A**

T

RLM0_GPLLT_IN_A**/RDQ82

T

4-191

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

C (LVDS)*

T (LVDS)*

Bank

3

-

Dual Function

Differential

AB29

AB28

GNDIO

Y22

Y23

AB26

AB27

-

PR62B

PR62A

GNDIO3

PR60B

PR60A

NC

3

-

RLM0_GPLLC_FB_A

RLM0_GPLLT_FB_A

PR82B

PR82A

GNDIO3

PR81B

PR81A

PR80B

PR80A

VCCIO3

PR79B

PR79A

PR78B

PR78A

PR76B

PR76A

GNDIO3

-

RLM0_GPLLC_FB_A/RDQ82 C (LVDS)*

RLM0_GPLLT_FB_A/RDQS82 T (LVDS)*

3

-

C

T

3

-

RDQ82

C

T

C (LVDS)*

T (LVDS)*

NC

-

Y24

Y25

AA29

Y28

Y30

Y29

-

NC

-

RDQ82

RDQ73

C

NC

-

T

NC

-

C (LVDS)*

NC

-

T (LVDS)*

NC

-

C

T

NC

-

W22

V22

Y27

-

NC

-

PR75B

PR75A

PR74B

VCCIO3

PR74A

PR73B

PR73A

GNDIO3

PR72B

PR72A

PR71B

PR71A

VCCIO3

PR70B

PR70A

PR69B

PR69A

PR67B

PR67A

GNDIO3

PR66B

PR66A

PR65B

PR65A

VCCIO3

PR64B

PR64A

PR63B

GNDIO3

PR63A

PR62B

PR62A

PR61B

3

-

RDQ73

C (LVDS)*

T (LVDS)*

C

NC

-

NC

-

Y26

W30

W29

-

NC

-

RDQ73

T

NC

-

C (LVDS)*

T (LVDS)*

NC

-

RDQS73

-

W25

W26

U29

V29

VCCIO

V30

U30

W27

W28

V24

V25

GNDIO

U28

U27

U23

V23

VCCIO

V26

U26

U25

GNDIO

U24

T30

NC

-

3

-

RDQ73

C

NC

-

T

PR59B

PR59A

VCCIO3

PR58B

PR58A

PR57B

PR57A

PR55B

PR55A

GNDIO3

PR54B

PR54A

PR53B

PR53A

VCCIO3

PR52B

PR52A

PR51B

GNDIO3

PR51A

PR50B

PR50A

PR49B

3

-

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

C

RDQ73

RDQ64

C

T

C (LVDS)*

T (LVDS)*

RDQ52

C

T

C

T

3

-

RDQ52

C (LVDS)*

3

-

RDQ64

C (LVDS)*

T (LVDS)*

C

T

C

T

RDQ52

RDQS52

RDQ52

C (LVDS)*

T (LVDS)*

C

RDQ64

RDQS64

RDQ64

C (LVDS)*

T (LVDS)*

C

3

RDQ52

T

3

RDQ64

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

R30

T23

4-192

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

3

-

Dual Function

Differential

VCCIO

T22

VCCIO3

PR49A

PR48B

PR48A

PR46B

GNDIO3

VCCIO3

PR46A

PR45B

PR45A

PR44B

-

3

VCCIO3

PR61A

PR60B

PR60A

PR58B

GNDIO3

-

RDQ52

T

RDQ64

T

T29

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

T28

RDQ64

R23

3

-

RLM3_SPLLC_FB_A

RLM3_SPLLC_FB_A/RDQ55

GNDIO

VCCIO

R22

3

-

RLM3_SPLLT_FB_A

RLM3_SPLLC_IN_A

RLM3_SPLLT_IN_A

T

PR58A

PR57B

PR57A

PR56B

VCCIO3

PR56A

GNDIO3

PR53B

PR53A

VCCIO3

PR52B

PR52A

PR51B

PR51A

PR49B

PR49A

GNDIO2

PR48B

PR48A

PR47B

PR47A

VCCIO2

PR46B

PR46A

PR45B

GNDIO2

PR45A

PR44B

PR44A

PR43B

VCCIO2

PR43A

PR42B

PR42A

PR40B

PR40A

GNDIO2

PR39B

PR39A

PR38B

PR38A

VCCIO2

3

-

RLM3_SPLLT_FB_A/RDQ55

T

P30

C (LVDS)*

T (LVDS)*

C

RLM3_SPLLC_IN_A/RDQ55 C (LVDS)*

R29

RLM3_SPLLT_IN_A/RDQ55

RDQ55

T (LVDS)*

C

T27

-

T26

PR44A

GNDIO3

PR43B

PR43A

VCCIO3

PR42B

PR42A

PR41B

PR41A

PR39B

PR39A

GNDIO2

PR38B

PR38A

PR37B

PR37A

VCCIO2

PR36B

PR36A

PR35B

GNDIO2

PR35A

PR34B

PR34A

PR33B

VCCIO2

PR33A

PR32B

PR32A

PR30B

PR30A

GNDIO2

PR29B

PR29A

PR28B

PR28A

VCCIO2

3

-

T

RDQ55

T

GNDIO

N30

3

2

-

C (LVDS)*

T (LVDS)*

3

2

-

RDQ55

C (LVDS)*

T (LVDS)*

N29

VCCIO

R27

VREF2_3

VREF1_3

C

VREF2_3/RDQ55

VREF1_3/RDQ55

PCLKC3_0/RDQ55

PCLKT3_0/RDQ55

PCLKC2_0/RDQ46

PCLKT2_0/RDQ46

C

R28

T

P29

PCLKC3_0

C (LVDS)*

P28

PCLKT3_0

T (LVDS)*

M30

M29

GNDIO

P23

PCLKC2_0/RDQ36

PCLKT2_0/RDQ36

C

T

C

T

2

-

RDQ36

C (LVDS)*

2

-

RDQ46

C (LVDS)*

P24

T (LVDS)*

R26

C

T

C

T

P27

VCCIO

P25

RDQ36

RDQS36

RDQ36

C (LVDS)*

T (LVDS)*

C

RDQ46

RDQS46

RDQ46

C (LVDS)*

T (LVDS)*

C

P26

K30

GNDIO

K29

2

-

RDQ36

T

2

-

RDQ46

T

N22

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

P22

RDQ36

RDQ46

J30

RUM3_SPLLC_FB_A/RDQ36

RUM3_SPLLC_FB_A/RDQ46

VCCIO

J29

RUM3_SPLLT_FB_A/RDQ36

T

RUM3_SPLLT_FB_A/RDQ46

T

N24

RUM3_SPLLC_IN_A/RDQ36 C (LVDS)*

RUM3_SPLLT_IN_A/RDQ36 T (LVDS)*

RUM3_SPLLC_IN_A/RDQ46 C (LVDS)*

N23

RUM3_SPLLT_IN_A/RDQ46

T (LVDS)*

N25

RDQ27

C

T

RDQ37

C

T

N26

GNDIO

M27

M28

H30

2

RDQ27

C (LVDS)*

2

RDQ37

C (LVDS)*

T (LVDS)*

C

T

C

T

G30

VCCIO

4-193

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

-

Dual Function

RDQ27

Differential

C (LVDS)*

T (LVDS)*

C

Bank

2

-

Dual Function

Differential

C (LVDS)*

T (LVDS)*

C

M25

M26

L30

GNDIO

L29

L28

L27

H29

VCCIO

G29

L22

M22

F30

GNDIO

F29

-

PR27B

PR27A

PR26B

GNDIO2

PR26A

PR25B

PR25A

PR24B

VCCIO2

PR24A

PR23B

PR23A

PR21B

GNDIO2

PR21A

-

PR37B

PR37A

PR36B

GNDIO2

PR36A

PR35B

PR35A

PR34B

VCCIO2

PR34A

PR33B

PR33A

PR31B

GNDIO2

PR31A

-

RDQ37

RDQS37

RDQ37

RDQS27

RDQ27

2

-

RDQ27

T

2

-

RDQ37

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

RDQ27

T

RDQ37

RDQ28

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

2

-

T

2

-

RDQ28

T

-

E30

E29

VCCIO

L25

L26

-

PR20B

PR20A

VCCIO2

PR19B

PR19A

-

2

-

C (LVDS)*

T (LVDS)*

PR30B

PR30A

-

2

-

RDQ28

C (LVDS)*

T (LVDS)*

C

T

PR29B

PR29A

VCCIO2

PR28B

PR28A

PR27B

GNDIO2

PR27A

PR26B

PR26A

PR25B

VCCIO2

PR25A

PR24B

PR24A

PR22B

GNDIO2

PR22A

PR21B

PR21A

PR20B

VCCIO2

PR20A

GNDIO2

-

2

-

RDQ28

C

T

H28

J28

G28

GNDIO

G27

L24

L23

D30

-

PR18B

PR18A

PR16B

GNDIO2

PR16A

NC

2

-

C (LVDS)*

T (LVDS)*

C

RDQ28

RDQS28

RDQ28

C (LVDS)*

T (LVDS)*

C

2

-

T

2

-

RDQ28

T

C (LVDS)*

T (LVDS)*

C

NC

-

NC

-

D29

K24

K25

J27

-

NC

-

RDQ28

T

NC

-

C (LVDS)*

T (LVDS)*

C

NC

-

NC

-

K26

K23

K22

J22

VCCIO

J23

-

NC

-

2

-

T

PR15B

PR15A

PR14B

VCCIO2

PR14A

-

2

-

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

2

-

T

-

J26

H26

H27

G26

NC

-

PR17B

PR17A

PR16B

PR16A

2

RDQ15

C (LVDS)*

NC

-

T (LVDS)*

NC

-

C

T

NC

-

4-194

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

2

Dual Function

Differential

-

H23

H24

D28

-

VCCIO2

PR15B

NC

2

RDQ15

RDQS15

RDQ15

C (LVDS)*

T (LVDS)*

C

NC

-

PR15A

2

NC

-

PR14B

2

-

GNDIO2

-

E28

G24

H25

D27

GNDIO

E27

F26

G25

F24

VCCIO

GNDIO

F25

VCCIO

G23

C30

A29

B30

B29

C27

A26

A27

B26

C26

B25

C25

A25

C29

B28

C28

A28

B24

E24

D24

C24

A20

C20

B20

C19

A23

C23

B23

C22

B22

A21

NC

-

PR14A

2

RDQ15

T

PR13B

2

C (LVDS)*

T (LVDS)*

C

PR13B

2

C (LVDS)*

T (LVDS)*

C

PR13A

2

RDQ15

PR12B

2

RUM0_SPLLC_FB_A

PR12B

2

RUM0_SPLLC_FB_A/RDQ15

GNDIO2

-

VCCIO2

2

PR12A

2

RUM0_SPLLT_FB_A

RUM0_SPLLC_IN_A

RUM0_SPLLT_IN_A

VREF2_2

T

PR12A

2

RUM0_SPLLT_FB_A/RDQ15

T

PR11B

2

C (LVDS)*

T (LVDS)*

C

PR11B

2

RUM0_SPLLC_IN_A/RDQ15 C (LVDS)*

PR11A

2

PR11A

2

RUM0_SPLLT_IN_A/RDQ15

VREF2_2

T (LVDS)*

C

PR9B

2

PR9B

2

VCCIO2

-

GNDIO2

-

GNDIO2

-

PR9A

2

VREF1_2

T

PR9A

2

VREF1_2

T

VCCIO2

2

VCCIO2

2

XRES

-

XRES

1

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

URC_SQ_VCCAUX33

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

12

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

T

C

T

C

T

C

T

C

T

C

T

C

T

URC_SQ_VCCAUX33 12

C

T

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

12

C

T

C

T

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

T

C

T

C

4-195

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

12

1

-

Dual Function

Differential

Bank

12

1

Dual Function

Differential

A22

C21

B19

B18

A19

C18

D23

GNDIO

E21

D26

E26

E23

-

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT73B

T

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT82B

T

C

T

C

T

C

GNDIO1

PT73A

GNDIO1

PT82A

-

1

-

T

C

T

1

T

C

T

PT72B

PT81B

1

PT72A

PT81A

1

PT71B

C

PT80B

1

C

-

VCCIO1

PT80A

1

G22

VCCIO

D22

F21

PT71A

1

-

T

1

T

VCCIO1

PT70B

-

C

T

PT79B

1

C

T

PT70A

PT79A

1

G18

H18

D20

GNDIO

D21

E20

E19

D19

VCCIO

E18

D18

C17

A17

B17

GNDIO

VCCIO

J18

PT69B

C

T

PT78B

1

C

T

PT69A

PT78A

1

PT68B

C

PT77B

1

C

GNDIO1

PT68A

GNDIO1

PT77A

-

1

-

T

C

T

1

T

C

T

PT67B

PT76B

1

PT67A

PT76A

1

PT66B

C

PT75B

1

C

VCCIO1

PT66A

VCCIO1

PT75A

1

T

C

T

C

T

1

T

C

T

C

T

PT65B

PT74B

1

PT65A

PT74A

1

PT64B

PT73B

1

PT64A

PT73A

1

GNDIO1

VCCIO1

NC

GNDIO1

VCCIO1

PT66B

-

1

-

1

C

T

C

T

C

T

J19

NC

-

PT66A

1

H17

J17

NC

-

PT65B

1

NC

-

PT65A

1

F18

NC

-

PT64B

1

F17

NC

-

PT64A

1

-

GNDIO1

PT63B

-

A16

B16

G17

G16

VCCIO

H16

F16

PT54B

1

C

T

C

T

1

C

T

C

T

PT54A

PT63A

1

PT53B

PT62B

1

PT53A

PT62A

1

VCCIO1

PT52B

VCCIO1

PT61B

1

C

T

C

T

1

C

T

C

T

PT52A

PT61A

1

J16

PT51B

PT60B

1

G15

PT51A

PT60A

1

4-196

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

-

Dual Function

Differential

GNDIO

C16

GNDIO1

PT50B

PT50A

PT49B

PT49A

VCCIO1

PT48B

PT48A

PT47B

PT47A

PT46B

GNDIO0

PT46A

PT45B

PT45A

PT44B

VCCIO0

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

GNDIO0

PT41A

PT40B

VCCIO0

PT40A

PT38B

PT38A

PT37B

PT37A

GNDIO0

VCCIO0

PT34B

PT34A

GNDIO0

PT32B

PT32A

PT31B

PT31A

VCCIO0

PT30B

PT30A

PT28B

GNDIO0

PT28A

VCCIO0

GNDIO0

GNDIO1

PT59B

PT59A

PT58B

PT58A

VCCIO1

PT57B

PT57A

PT56B

PT56A

PT55B

GNDIO0

PT55A

PT54B

PT54A

PT53B

VCCIO0

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

GNDIO0

PT50A

PT49B

VCCIO0

PT49A

PT47B

PT47A

PT46B

PT46A

GNDIO0

VCCIO0

PT43B

PT43A

GNDIO0

PT41B

PT41A

PT40B

PT40A

VCCIO0

PT39B

PT39A

PT37B

GNDIO0

PT37A

VCCIO0

GNDIO0

1

0

-

C

T

C

T

1

0

-

C

T

C

T

D16

J15

H15

VCCIO

A15

VREF2_1

VREF1_1

C

T

VREF2_1

VREF1_1

C

T

B15

F15

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

E16

C15

C

GNDIO

D15

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

C14

E15

G14

VCCIO

J14

C

T

C

T

C

T

F14

H14

A14

C

T

C

T

B14

D13

C

GNDIO

F13

0

-

T

0

-

T

G13

VCCIO

J11

C

T

C

T

C

T

C

T

C

T

D4

D5

E5

F6

GNDIO

VCCIO

F7

0

-

0

-

C

T

C

T

D8

GNDIO

J13

0

-

C

T

C

T

0

-

C

T

C

T

G11

H13

H12

VCCIO

E8

C

T

C

T

D9

D12

C

GNDIO

E13

0

-

T

0

-

T

VCCIO

GNDIO

4-197

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

0

-

Dual Function

Differential

Bank

0

Dual Function

Differential

J12

GNDIO

VCCIO

H10

E12

D11

H11

F11

C13

A12

B13

B12

C10

A9

PT5B

GNDIO0

VCCIO0

PT5A

PT4B

PT4A

PT3B

PT3A

VCC

C

PT31B

-

C

-

0

-

VCCIO0

0

T

C

T

C

T

PT31A

0

T

C

T

C

T

PT30B

0

PT30A

0

PT29B

0

PT29A

0

ULC_SQ_VCCRX0

ULC_SQ_HDINP0

ULC_SQ_VCCIB0

ULC_SQ_HDINN0

ULC_SQ_VCCTX0

ULC_SQ_HDOUTP0

ULC_SQ_VCCOB0

ULC_SQ_HDOUTN0

ULC_SQ_VCCTX1

ULC_SQ_HDOUTN1

ULC_SQ_VCCOB1

ULC_SQ_HDOUTP1

ULC_SQ_VCCRX1

ULC_SQ_HDINN1

ULC_SQ_VCCIB1

ULC_SQ_HDINP1

11

PT19A

NC

0

-

T

C

T

C

T

PT19B

VCC

0

-

PT17A

NC

0

-

A10

B9

PT17B

VCC

0

-

C

T

C

T

C9

B8

PT18B

NC

0

-

C8

A8

PT18A

VCC

0

-

C12

B11

C11

A11

B7

PT16B

NC

0

-

C

T

C

T

PT16A

VCCAUX

PT15B

PT15A

VCC

0

-

ULC_SQ_VCCAUX33 11

E7

0

-

C

T

ULC_SQ_REFCLKN

ULC_SQ_REFCLKP

ULC_SQ_VCCP

ULC_SQ_HDINP2

ULC_SQ_VCCIB2

ULC_SQ_HDINN2

ULC_SQ_VCCRX2

ULC_SQ_HDOUTP2

ULC_SQ_VCCOB2

ULC_SQ_HDOUTN2

ULC_SQ_VCCTX2

ULC_SQ_HDOUTN3

ULC_SQ_VCCOB3

ULC_SQ_HDOUTP3

ULC_SQ_VCCTX3

ULC_SQ_HDINN3

ULC_SQ_VCCIB3

ULC_SQ_HDINP3

ULC_SQ_VCCRX3

VCC

11

-

C

T

D7

C7

A3

PT12A

NC

0

-

T

C

T

C

T

C3

B3

PT12B

VCC

0

-

C2

A6

PT14A

NC

0

-

C6

B6

PT14B

VCC

0

-

C

T

C

T

C5

B5

PT13B

NC

0

-

A4

A5

PT13A

VCC

0

-

C4

B2

PT11B

NC

0

-

C

T

C

T

B1

A2

PT11A

VCC

0

-

C1

L12

L13

L18

L19

M11

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

4-198

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

M12

M13

M14

M15

M16

M17

M18

M19

M20

N11

N12

N19

N20

P12

P19

R12

R19

T12

T19

U12

U19

V11

V12

V19

V20

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y12

Y13

Y18

Y19

D14

E6

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

0

1

VCCIO0

VCCIO1

0

1

E9

F12

K12

K13

D17

E22

E25

F19

4-199

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

1

2

3

4

5

6

7

Dual Function

Differential

Bank

1

2

3

4

5

6

7

Dual Function

Differential

K18

K19

F28

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

J25

K28

M21

M24

N21

N28

P21

R25

AA28

AB25

AE28

T25

U21

V21

V28

W21

W24

AA18

AA19

AE19

AF22

AG17

AG25

AA12

AA13

AE12

AF9

AG14

AG6

AA3

AB6

AE3

T6

U10

V10

V3

W10

W7

F3

J6

K3

M10

M7

N10

N3

P10

4-200

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

R6

AA25

AD28

AA10

AA11

AA20

AA21

K10

VCCIO7

VCCIO8

VCCAUX

GND

7

8

-

VCCIO7

VCCIO8

VCCAUX

GND

7

8

-

K11

K20

K21

L10

L11

L20

L21

Y10

Y11

Y20

Y21

A1

A13

GND

A18

GND

A24

GND

A30

GND

A7

GND

AA14

AA15

AA16

AA17

AA24

AA27

AA4

AB24

AB7

AD12

AD19

AD27

AE22

AE27

AE4

AE9

AF14

AF17

AF25

AF6

GND

AJ10

AJ21

AJ27

AJ4

GND

4-201

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AK1

AK13

AK18

AK24

AK30

AK7

B10

B21

B27

B4

GND

-

GND

-

D25

D6

E14

E17

F22

F27

F4

F9

G12

G19

J24

J7

K14

K15

K16

K17

K27

K4

L14

L15

L16

L17

M23

M8

N14

N15

N16

N17

N27

N4

P11

P13

P14

P15

P16

P17

P18

P20

R10

4-202

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

R11

R13

R14

R15

R16

R17

R18

R20

R21

R24

R7

GND

NC

-

6

-

GND

NC

-

T10

T11

T13

T14

T15

T16

T17

T18

T20

T21

T24

T7

U11

U13

U14

U15

U16

U17

U18

U20

V14

V15

V16

V17

V27

V4

W23

W8

Y14

Y15

Y16

Y17

AA26

AB10

AB11

AB12

AB13

AB14

PL73B

NC

LDQ71

C (LVDS)*

NC

4-203

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

-

Dual Function

Differential

Bank

Dual Function

Differential

AB15

AB16

AB17

AB19

AB20

AB21

AB9

AC10

AC11

AC21

AC22

AC8

AC9

AD21

AD22

AD4

AD5

AD6

AD7

AD8

AE23

AE5

AE6

AE7

AF20

AF23

AF5

AG23

AG26

D10

E10

NC

-

NC

-

NC

-

NC

-

NC

-

PL73A

PL74B

NC

6

-

LDQ71

T (LVDS)*

C

NC

-

NC

-

PL70B

PL74A

NC

6

-

LDQ71

C

T

NC

-

PL68A

PL68B

PL71A

PL72A

PL72B

NC

6

-

LDQ71

LDQS71

LDQ71

T

C

T (LVDS)*

T

C

PL69A

PL70A

PL71B

NC

6

-

LDQ71

T (LVDS)*

T

C (LVDS)*

NC

-

PL69B

NC

6

-

LDQ71

C (LVDS)*

NC

-

PT10A

PT9B

PT10B

PT9A

NC

0

-

T

C

T

E11

F10

F20

F23

NC

-

F8

PL6B

NC

7

-

LDQ6

C (LVDS)*

G10

G20

G21

G7

NC

-

NC

-

PL8A

PL6A

PL5A

NC

7

-

LDQ6

LDQS6****

LDQ6

T (LVDS)*

T

G8

G9

H19

H20

H21

H22

H6

NC

-

NC

-

NC

-

PL8B

PL5B

PL2A

7

LDQ6

C (LVDS)*

C

H8

H9

T (LVDS)*

4-204

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA

LFE2M50E/SE

LFE2M70E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

J10

J20

J21

J9

PL2B

NC

7

-

LDQ6

C (LVDS)*

NC

-

NC

-

NC

PL4A

PL4B

NC

7

-

LDQ6

T (LVDS)*

C (LVDS)*

NC

K9

NC

R9

NC

U22

W9

N13

N18

V13

V18

NC

-

NC

-

NC

VCCPLL

-

VCCPLL

-

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

*** These sysCONFIG pins are dedicated I/O pins for conﬁguration. The outpus are actively driven during normal device operation.

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank.The substrate pads listed in the Pin Table do not necessarily have a one to one con-

nection with a package ball or pin.

4-205

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA

LFE2M100E/SE

Ball Number

VCCIO

D2

Ball/Pad Function

VCCIO7

PL9A

Bank

7

-

Dual Function

Differential

VREF2_7

VREF1_7

T

D3

PL9B

C

GNDIO

J8

GNDIO7

PL11A

PL11B

PL12A

PL12B

-

7

-

LUM0_SPLLT_IN_A/LDQ15

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

T (LVDS)*

H7

C (LVDS)*

E3

T

E4

C

-

VCCIO

G6

VCCIO7

PL13A

PL13B

PL14A

PL14B

GNDIO7

PL15A

PL15B

PL16A

VCCIO7

PL16B

PL17A

PL17B

PL18A

GNDIO7

PL18B

GNDIO7

VCCIO7

PL25A

PL25B

PL26A

PL26B

GNDIO7

PL28A

PL28B

PL29A

PL29B

VCCIO7

PL30A

PL30B

PL31A

PL31B

GNDIO7

7

-

LDQ15

T (LVDS)*

F5

C (LVDS)*

E2

T

D1

C

GNDIO

G5

7

-

LDQS15

LDQ15

T (LVDS)*

C (LVDS)*

T

G4

K7

VCCIO

K8

LDQ15

C

E1

T (LVDS)*

C (LVDS)*

T

F2

F1

GNDIO

G3

7

-

LDQ15

C

GNDIO

VCCIO

H5

7

-

LDQ23

T (LVDS)*

H4

C (LVDS)*

J5

T

J4

C

GNDIO

G2

7

-

LDQ32

T (LVDS)*

G1

C (LVDS)*

L9

T

L7

C

VCCIO

K6

LDQ32

T (LVDS)*

K5

C (LVDS)*

L8

T

L6

C

GNDIO

4-206

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

H3

Ball/Pad Function

PL32A

PL32B

PL33A

VCCIO7

PL33B

PL34A

-

Bank

7

-

Dual Function

LDQS32

LDQ32

Differential

T (LVDS)*

C (LVDS)*

T

H2

N8

LDQ32

VCCIO

M9

LDQ32

C

J3

T (LVDS)*

-

J2

PL34B

PL35A

GNDIO7

PL35B

VCCIO7

GNDIO7

PL41A

PL41B

PL42A

PL42B

VCCIO7

PL43A

PL43B

PL44A

PL44B

GNDIO7

PL45A

PL45B

PL46A

VCCIO7

PL46B

PL47A

PL47B

PL48A

GNDIO7

PL48B

PL50A

PL50B

PL51A

PL51B

VCCIO7

PL52A

PL52B

PL53A

PL53B

GNDIO7

7

-

LDQ32

C (LVDS)*

T

H1

GNDIO

J1

7

-

LDQ32

C

VCCIO

GNDIO

L5

7

-

LDQ45

T (LVDS)*

L4

C (LVDS)*

N9

T

N7

C

VCCIO

K2

LDQ45

T (LVDS)*

K1

C (LVDS)*

P9

T

P7

C

GNDIO

M6

7

-

LDQS45

LDQ45

T (LVDS)*

C (LVDS)*

T

M5

N5

VCCIO

N6

LDQ45

C

M4

T (LVDS)*

C (LVDS)*

T

M3

P6

GNDIO

P8

7

-

LDQ45

C

L3

LUM3_SPLLT_IN_A/LDQ54

LUM3_SPLLC_IN_A/LDQ54

LUM3_SPLLT_FB_A/LDQ54

LUM3_SPLLC_FB_A/LDQ54

T (LVDS)*

L2

C (LVDS)*

P5

T

P4

C

VCCIO

L1

LDQ54

T (LVDS)*

M2

C (LVDS)*

R5

T

R4

C

GNDIO

4-207

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

M1

Ball/Pad Function

PL54A

PL54B

PL55A

VCCIO7

PL55B

PL56A

PL56B

PL57A

GNDIO7

PL57B

PL59A

PL59B

PL60A

PL60B

PL61A

VCCIO6

PL61B

PL62A

PL62B

GNDIO6

VCCIO6

PL65A

PL65B

PL66A

PL66B

GNDIO6

PL68A

PL68B

PL69A

PL69B

VCCIO6

PL70A

PL70B

PL71A

PL71B

GNDIO6

PL72A

PL72B

PL73A

VCCIO6

PL73B

PL74A

PL74B

Bank

7

-

Dual Function

LDQS54

LDQ54

Differential

T (LVDS)*

C (LVDS)*

T

N2

R8

LDQ54

VCCIO

T9

LDQ54

C

P3

T (LVDS)*

C (LVDS)*

T

P2

LDQ54

N1

PCLKT7_0/LDQ54

GNDIO

P1

7

6

-

PCLKC7_0/LDQ54

PCLKT6_0/LDQ63

PCLKC6_0/LDQ63

VREF2_6/LDQ63

VREF1_6/LDQ63

LDQ63

C

T5

T (LVDS)*

C (LVDS)*

T

T4

U7

T8

C

R3

T (LVDS)*

VCCIO

R2

LDQ63

C (LVDS)*

R1

T

T1

C

GNDIO

VCCIO

T3

6

-

LLM4_SPLLT_IN_A/LDQ63

LLM4_SPLLC_IN_A/LDQ63

LLM4_SPLLT_FB_A/LDQ63

LLM4_SPLLC_FB_A/LDQ63

T (LVDS)*

T2

C (LVDS)*

U9

T

U8

C

GNDIO

U5

6

-

LDQ72

T (LVDS)*

U4

C (LVDS)*

V9

T

V7

C

VCCIO

U3

LDQ72

T (LVDS)*

U2

C (LVDS)*

V8

T

U6

C

GNDIO

U1

6

LDQS72

LDQ72

T (LVDS)*

C (LVDS)*

T

V2

V5

VCCIO

V6

LDQ72

C

V1

T (LVDS)*

C (LVDS)*

W1

4-208

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

W5

Ball/Pad Function

PL75A

Bank

6

-

Dual Function

Differential

LDQ72

T

GNDIO

W6

GNDIO6

PL75B

6

-

LDQ72

LDQ81

C

W3

PL77A

T (LVDS)*

C (LVDS)*

T

W4

PL77B

W2

PL78A

Y4

PL78B

C

Y1

PL79A

T (LVDS)*

VCCIO

Y2

VCCIO6

PL79B

LDQ81

LDQS81

C (LVDS)*

Y5

PL80A

T

C

Y6

PL80B

AA1

GNDIO

AA2

Y3

PL81A

T (LVDS)*

GNDIO6

PL81B

6

-

LDQ81

C (LVDS)*

PL82A

T

AB1

VCCIO

Y9

PL82B

C

VCCIO6

PL83A

LDQ81

T (LVDS)*

Y8

PL83B

C (LVDS)*

Y7

PL84A

T

AA7

GNDIO

VCCIO

AB2

AB3

AA5

AA6

AB4

VCCIO

AB5

AA8

AA9

AC1

GNDIO

AC2

AC4

AC3

VCCIO

AC7

AC6

AC5

AD3

PL84B

C

GNDIO6

VCCIO6

PL95A

6

-

LDQ99

T (LVDS)*

C (LVDS)*

T

PL95B

PL96A

PL96B

C

PL97A

T (LVDS)*

VCCIO6

PL97B

LDQ99

C (LVDS)*

PL98A

T

C

PL98B

LDQ99

PL99A

LLM0_GPLLT_IN_A**/LDQS99

T (LVDS)*

GNDIO6

PL99B

6

LLM0_GPLLC_IN_A**/LDQ99

LLM0_GPLLT_FB_A/LDQ99

LLM0_GPLLC_FB_A/LDQ99

C (LVDS)*

PL100A

PL100B

VCCIO6

PL101A

PL101B

PL102A

PL102B

T

C

LLM0_GDLLT_IN_A**/LDQ99

LLM0_GDLLC_IN_A**/LDQ99

LLM0_GDLLT_FB_A/LDQ99

LLM0_GDLLC_FB_A/LDQ99

T (LVDS)*

C (LVDS)*

T

C

4-209

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

GNDIO

AB8

Ball/Pad Function

GNDIO6

Bank

-

Dual Function

Differential

LLM0_PLLCAP

PL104A

6

AD2

AD1

AE2

6

T

PL104B

6

C

TCK

-

AE1

TDI

-

AF2

TMS

-

AF1

TDO

-

AG1

AH1

AK2

VCCJ

-

LLC_SQ_VCCRX3

LLC_SQ_HDINP3

LLC_SQ_VCCIB3

LLC_SQ_HDINN3

LLC_SQ_VCCTX3

LLC_SQ_HDOUTP3

LLC_SQ_VCCOB3

LLC_SQ_HDOUTN3

LLC_SQ_VCCTX2

LLC_SQ_HDOUTN2

LLC_SQ_VCCOB2

LLC_SQ_HDOUTP2

LLC_SQ_VCCRX2

LLC_SQ_HDINN2

LLC_SQ_VCCIB2

LLC_SQ_HDINP2

LLC_SQ_VCCP

LLC_SQ_REFCLKP

LLC_SQ_REFCLKN

LLC_SQ_VCCAUX33

LLC_SQ_HDINP1

LLC_SQ_VCCIB1

LLC_SQ_HDINN1

LLC_SQ_VCCRX1

LLC_SQ_HDOUTP1

LLC_SQ_VCCOB1

LLC_SQ_HDOUTN1

LLC_SQ_VCCTX1

LLC_SQ_HDOUTN0

LLC_SQ_VCCOB0

LLC_SQ_HDOUTP0

LLC_SQ_VCCTX0

LLC_SQ_HDINN0

LLC_SQ_VCCIB0

14

T

C

T

AJ1

AJ2

AH4

AK5

AK4

AJ5

C

T

AH5

AJ6

AH6

AK6

AH2

AJ3

C

T

AH3

AK3

AH7

AG7

AF7

T

C

AJ7

AK11

AH11

AJ11

AH12

AK8

T

C

T

AH8

AJ8

C

T

AH9

AJ9

AK10

AK9

AH10

AJ12

AJ13

C

4-210

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AK12

AH13

AF10

AE8

Ball/Pad Function

LLC_SQ_HDINP0

LLC_SQ_VCCRX0

PB30A

PB30B

PB31A

VCCIO5

PB31B

PB32A

PB32B

PB33A

GNDIO5

PB33B

PB34A

PB34B

PB35A

VCCIO5

PB35B

PB36A

PB36B

PB37A

GNDIO5

PB37B

-

Bank

14

5

-

Dual Function

Differential

T

BDQ33

T

C

T

AE11

VCCIO

AD9

BDQ33

BDQS33

C

T

C

T

AE10

AD10

AE13

GNDIO

AC12

AG2

5

-

BDQ33

C

T

C

T

AG3

AD13

VCCIO

AC13

AE14

AC14

AF3

BDQ33

C

T

C

T

GNDIO

AF4

5

-

BDQ33

C

-

AG4

PB38A

PB38B

GNDIO5

-

5

-

BDQ42

T

AG5

C

GNDIO

-

AD11

AF13

AF12

VCCIO

AD14

AG8

PB48A

PB48B

PB49A

VCCIO5

PB49B

PB50A

PB50B

PB51A

GNDIO5

-

5

-

BDQ51

T

C

T

BDQ51

C

T

C

T

AF8

BDQ51

AE15

GNDIO

-

BDQS51****

-

AC15

VCCIO

GNDIO

AD15

AF15

AG10

PB51B

VCCIO5

GNDIO5

PB56A

PB56B

PB57A

5

-

BDQ51

C

5

BDQ60

T

C

T

4-211

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AG9

Ball/Pad Function

PB57B

PB58A

PB58B

VCCIO5

PB59A

PB59B

GNDIO5

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO5

GNDIO5

PB67A

VCCIO4

PB67B

PB68A

PB68B

PB69A

GNDIO4

PB69B

PB70A

PB70B

PB71A

VCCIO4

PB71B

PB72A

PB72B

PB73A

GNDIO4

PB73B

PB74A

PB74B

PB75A

PB75B

PB76A

PB76B

VCCIO4

GNDIO4

PB80A

PB80B

Bank

5

-

Dual Function

BDQ60

Differential

C

T

AH14

AG12

VCCIO

AG15

AG13

GNDIO

AF16

BDQ60

C

BDQ60

T

C

5

-

BDQS60

T

C

T

AH15

AC16

AE16

BDQ60

VREF2_5/BDQ60

VREF1_5/BDQ60

PCLKT5_0/BDQ60

PCLKC5_0/BDQ60

C

T

AG11

AF11

C

VCCIO

GNDIO

AJ14

4

-

PCLKT4_0/BDQ69

T

VCCIO

AK14

PCLKC4_0/BDQ69

VREF2_4/BDQ69

VREF1_4/BDQ69

BDQS69

C

T

C

T

AK15

AK16

AF18

GNDIO

AD16

AJ15

4

-

BDQ69

C

T

C

T

AG16

AE17

VCCIO

AC17

AH16

AK17

BDQ69

C

T

C

T

AG20

GNDIO

AG21

AG18

AJ16

4

-

BDQ69

BDQ78

C

T

C

T

AF21

AG22

AD17

AF19

C

T

C

VCCIO

GNDIO

AH17

AJ17

4

BDQ78

T

C

4-212

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

VCCIO

AF26

AE25

GNDIO

AD24

AE24

AD18

AC18

AE18

AG19

VCCIO

GNDIO

AC19

AD20

AB18

AC20

AE20

AE21

VCCIO

AC23

AD23

GNDIO

AH18

AK19

AJ18

Ball/Pad Function

VCCIO4

Bank

4

Dual Function

Differential

PB82A

4

BDQ78

T

PB82B

4

C

GNDIO4

-

PB92A

4

BDQ96

T

C

T

PB92B

4

PB93A

4

PB93B

4

C

T

PB94A

4

PB94B

4

C

VCCIO4

4

GNDIO4

-

PB96A

4

BDQS96

BDQ96

T

C

T

PB96B

4

PB97A

4

PB97B

4

C

T

PB98A

4

PB98B

4

C

VCCIO4

4

PB99A

4

BDQ96

T

PB99B

4

C

GNDIO4

-

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

LRC_SQ_VCCAUX33

LRC_SQ_HDINP1

13

T

C

T

AJ19

AH21

AK22

AK21

AJ22

C

T

AH22

AJ23

AH23

AK23

AH19

AJ20

C

T

AH20

AK20

AH24

AG24

AF24

AJ24

T

C

AK28

T

4-213

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AH28

AJ28

Ball/Pad Function

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

Bank

13

8

Dual Function

Differential

C

T

AH29

AK25

AH25

AJ25

C

T

AH26

AJ26

AK27

AK26

AH27

AJ29

C

T

AJ30

AK29

AH30

AG27

AD25

AG28

AG30

AG29

AC24

AF27

GNDIO

AF28

AE26

AB23

AF29

VCCIO

AF30

AD26

AE29

GNDIO

AE30

AD29

AC25

AD30

VCCIO

AA22

AC26

AA23

AB22

AC27

GNDIO

CFG1

8

CFG0

8

PROGRAMN

CCLK

8

INITN

8

DONE

8

GNDIO8

-

WRITEN***

8

CS1N***

8

CSN***

8

D0/SPIFASTN***

VCCIO8

8

D1***

8

D2***

8

D3***

8

GNDIO8

-

D4***

8

D5***

8

D6***

8

D7***

8

VCCIO8

8

DI/CSSPI0N***

DOUT/CSON/CSSPI1N***

BUSY/SISPI***

RLM0_PLLCAP

PR102B

8

3

RLM0_GDLLC_FB_A/RDQ99

C

GNDIO3

-

4-214

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AC28

AC29

AC30

AB30

VCCIO

AA30

AB29

AB28

GNDIO

Y22

Ball/Pad Function

PR102A

PR101B

PR101A

PR100B

VCCIO3

PR100A

PR99B

PR99A

GNDIO3

PR98B

PR98A

PR97B

PR97A

VCCIO3

PR96B

PR96A

PR95B

PR95A

PR93B

PR93A

GNDIO3

VCCIO3

PR83B

PR83A

PR82B

VCCIO3

PR82A

PR81B

PR81A

GNDIO3

PR80B

PR80A

PR79B

PR79A

VCCIO3

PR78B

PR78A

PR77B

PR77A

PR75B

PR75A

GNDIO3

PR74B

Bank

3

-

Dual Function

Differential

T

RLM0_GDLLT_FB_A/RDQ99

RLM0_GDLLC_IN_A**/RDQ99

RLM0_GDLLT_IN_A**/RDQ99

RLM0_GPLLC_IN_A**/RDQ99

C (LVDS)*

T (LVDS)*

C

RLM0_GPLLT_IN_A**/RDQ99

RLM0_GPLLC_FB_A/RDQ99

RLM0_GPLLT_FB_A/RDQS99

T

C (LVDS)*

T (LVDS)*

3

-

RDQ99

C

Y23

T

AB26

AB27

VCCIO

Y24

C (LVDS)*

T (LVDS)*

RDQ99

RDQ90

C

Y25

T

AA29

Y28

C (LVDS)*

T (LVDS)*

Y30

C

T

Y29

GNDIO

VCCIO

W22

3

-

RDQ81

C (LVDS)*

T (LVDS)*

C

V22

Y27

VCCIO

Y26

RDQ81

RDQS81

T

W30

C (LVDS)*

T (LVDS)*

W29

GNDIO

W25

3

-

RDQ81

C

W26

T

U29

C (LVDS)*

T (LVDS)*

V29

VCCIO

V30

RDQ81

RDQ72

C

U30

T

W27

C (LVDS)*

W28

T (LVDS)*

V24

C

T

V25

GNDIO

U28

3

RDQ72

C (LVDS)*

4-215

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

U27

Ball/Pad Function

PR74A

PR73B

PR73A

VCCIO3

PR72B

PR72A

PR71B

GNDIO3

PR71A

PR70B

PR70A

PR69B

VCCIO3

PR69A

PR68B

PR68A

PR66B

GNDIO3

-

Bank

3

-

Dual Function

RDQ72

Differential

T (LVDS)*

U23

RDQ72

C

T

V23

RDQ72

VCCIO

V26

RDQ72

RDQS72

RDQ72

C (LVDS)*

T (LVDS)*

C

U26

U25

GNDIO

U24

3

-

RDQ72

T

T30

C (LVDS)*

T (LVDS)*

C

R30

T23

VCCIO

T22

RDQ72

T

T29

C (LVDS)*

T (LVDS)*

C

T28

RDQ72

R23

RLM4_SPLLC_FB_A/RDQ63

GNDIO

-

R22

PR66A

PR65B

PR65A

PR64B

VCCIO3

PR64A

GNDIO3

PR61B

PR61A

VCCIO3

PR60B

PR60A

PR59B

PR59A

PR57B

PR57A

GNDIO2

PR56B

PR56A

PR55B

PR55A

VCCIO2

PR54B

PR54A

3

-

RLM4_SPLLT_FB_A/RDQ63

RLM4_SPLLC_IN_A/RDQ63

RLM4_SPLLT_IN_A/RDQ63

RDQ63

T

P30

C (LVDS)*

T (LVDS)*

C

R29

T27

VCCIO

T26

RDQ63

T

GNDIO

N30

3

2

-

RDQ63

C (LVDS)*

T (LVDS)*

N29

VCCIO

R27

VREF2_3/RDQ63

VREF1_3/RDQ63

PCLKC3_0/RDQ63

PCLKT3_0/RDQ63

PCLKC2_0/RDQ54

PCLKT2_0/RDQ54

C

R28

T

P29

C (LVDS)*

P28

T (LVDS)*

M30

C

T

M29

GNDIO

P23

2

RDQ54

C (LVDS)*

P24

T (LVDS)*

R26

C

T

P27

VCCIO

P25

RDQ54

C (LVDS)*

T (LVDS)*

P26

RDQS54

4-216

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

K30

Ball/Pad Function

PR53B

GNDIO2

PR53A

PR52B

PR52A

PR51B

VCCIO2

PR51A

PR50B

PR50A

PR48B

PR48A

GNDIO2

PR47B

PR47A

PR46B

PR46A

VCCIO2

PR45B

PR45A

PR44B

GNDIO2

PR44A

PR43B

PR43A

PR42B

VCCIO2

PR42A

PR41B

PR41A

PR40B

GNDIO2

PR40A

VCCIO2

GNDIO2

PR34B

PR34A

-

Bank

2

-

Dual Function

Differential

RDQ54

C

GNDIO

K29

2

-

RDQ54

T

N22

C (LVDS)*

T (LVDS)*

C

P22

RDQ54

J30

RUM3_SPLLC_FB_A/RDQ54

VCCIO

J29

RUM3_SPLLT_FB_A/RDQ54

RUM3_SPLLC_IN_A/RDQ54

RUM3_SPLLT_IN_A/RDQ54

RDQ45

T

N24

C (LVDS)*

N23

T (LVDS)*

N25

C

T

N26

RDQ45

GNDIO

M27

2

-

RDQ45

C (LVDS)*

M28

T (LVDS)*

H30

C

T

G30

VCCIO

M25

RDQ45

RDQS45

RDQ45

C (LVDS)*

T (LVDS)*

C

M26

L30

GNDIO

L29

2

-

RDQ45

T

L28

C (LVDS)*

T (LVDS)*

C

L27

H29

VCCIO

G29

RDQ45

T

L22

C (LVDS)*

T (LVDS)*

C

M22

F30

GNDIO

F29

2

-

T

VCCIO

GNDIO

E30

2

-

RDQ32

C (LVDS)*

T (LVDS)*

E29

-

L25

PR33B

PR33A

VCCIO2

PR32B

PR32A

2

RDQ32

C

T

L26

VCCIO

H28

RDQ32

C (LVDS)*

T (LVDS)*

J28

RDQS32

4-217

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

G28

Ball/Pad Function

PR31B

GNDIO2

PR31A

PR30B

PR30A

PR29B

VCCIO2

PR29A

PR28B

PR28A

PR26B

GNDIO2

PR26A

PR25B

PR25A

PR24B

VCCIO2

PR24A

GNDIO2

VCCIO2

PR17B

PR17A

PR16B

PR16A

VCCIO2

PR15B

PR15A

PR14B

GNDIO2

PR14A

PR13B

PR13A

PR12B

VCCIO2

PR12A

PR11B

PR11A

PR9B

Bank

2

-

Dual Function

Differential

RDQ32

C

GNDIO

G27

2

-

RDQ32

T

L24

C (LVDS)*

T (LVDS)*

C

L23

D30

VCCIO

D29

RDQ32

RDQ23

T

K24

C (LVDS)*

T (LVDS)*

C

K25

J27

GNDIO

K26

2

-

RDQ23

T

K23

C (LVDS)*

T (LVDS)*

C

K22

J22

VCCIO

J23

RDQ23

T

GNDIO

VCCIO

J26

2

-

RDQ15

C (LVDS)*

H26

T (LVDS)*

H27

C

T

G26

VCCIO

H23

RDQ15

RDQS15

RDQ15

C (LVDS)*

T (LVDS)*

C

H24

D28

GNDIO

E28

2

-

RDQ15

T

G24

C (LVDS)*

T (LVDS)*

C

H25

RDQ15

D27

RUM0_SPLLC_FB_A/RDQ15

VCCIO

E27

RUM0_SPLLT_FB_A/RDQ15

RUM0_SPLLC_IN_A/RDQ15

RUM0_SPLLT_IN_A/RDQ15

VREF2_2

T

F26

C (LVDS)*

T (LVDS)*

C

G25

F24

-

GNDIO

F25

GNDIO2

PR9A

-

2

1

VREF1_2

T

VCCIO

G23

VCCIO2

XRES

4-218

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

C30

A29

Ball/Pad Function

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

URC_SQ_VCCAUX33

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT100B

Bank

12

1

Dual Function

Differential

T

C

T

B30

B29

C27

A26

A27

B26

C

T

C26

B25

C25

A25

C29

B28

C

T

C28

A28

B24

E24

C

T

D24

C24

A20

T

C

T

C20

B20

C19

A23

C23

B23

C

T

C22

B22

A21

A22

C21

B19

C

T

B18

A19

C18

D23

GNDIO

E21

C

GNDIO1

-

PT100A

1

T

C

T

D26

E26

PT99B

1

PT99A

1

E23

PT98B

1

C

VCCIO

VCCIO1

1

4-219

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

G22

Ball/Pad Function

PT98A

-

Bank

1

-

Dual Function

Differential

T

-

D22

PT97B

PT97A

PT96B

PT96A

PT95B

GNDIO1

PT95A

PT94B

VCCIO1

PT94A

PT93B

PT93A

PT92B

PT92A

PT91B

PT91A

GNDIO1

VCCIO1

PT75B

PT75A

PT74B

PT74A

PT73B

PT73A

GNDIO1

PT72B

PT72A

PT71B

PT71A

VCCIO1

PT70B

PT70A

PT69B

PT69A

GNDIO1

PT68B

PT68A

PT67B

PT67A

VCCIO1

PT66B

1

-

C

T

F21

G18

C

T

H18

D20

C

GNDIO

D21

1

-

T

E20

C

VCCIO

E19

T

C

T

C

T

C

T

D19

E18

D18

C17

A17

B17

GNDIO

VCCIO

J18

1

-

C

T

C

T

C

T

J19

H17

J17

F18

F17

GNDIO

A16

1

-

C

T

C

T

B16

G17

G16

VCCIO

H16

C

T

C

T

F16

J16

G15

GNDIO

C16

1

C

T

C

T

D16

J15

H15

VCCIO

A15

VREF2_1

C

4-220

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

B15

Ball/Pad Function

PT66A

PT65B

PT65A

PT64B

GNDIO0

PT64A

PT63B

PT63A

PT62B

VCCIO0

PT62A

PT61B

PT61A

PT60B

PT60A

PT59B

GNDIO0

PT59A

PT58B

VCCIO0

PT58A

PT57B

PT56A

PT55B

PT55A

GNDIO0

VCCIO0

PT52B

PT52A

GNDIO0

PT50B

PT50A

PT49B

PT49A

VCCIO0

PT48B

PT48A

PT46B

GNDIO0

PT46A

VCCIO0

GNDIO0

PT31B

Bank

1

0

-

Dual Function

VREF1_1

Differential

T

C

T

F15

PCLKC1_0

PCLKT1_0

PCLKC0_0

E16

C15

C

GNDIO

D15

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

C14

E15

G14

C

VCCIO

J14

T

C

T

F14

H14

A14

C

T

B14

D13

C

GNDIO

F13

0

-

T

G13

C

VCCIO

J11

T

D4

D5

E5

C

T

F6

GNDIO

VCCIO

F7

0

-

C

T

D8

GNDIO

J13

0

-

C

T

C

T

G11

H13

H12

VCCIO

E8

C

T

D9

D12

C

GNDIO

E13

0

-

T

VCCIO

GNDIO

J12

0

C

4-221

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

-

Ball/Pad Function

-

Bank

-

Dual Function

Differential

VCCIO

H10

E12

D11

H11

F11

C13

A12

B13

B12

C10

A9

VCCIO0

0

PT31A

0

T

C

T

C

T

PT30B

0

PT30A

0

PT29B

0

PT29A

0

ULC_SQ_VCCRX0

ULC_SQ_HDINP0

ULC_SQ_VCCIB0

ULC_SQ_HDINN0

ULC_SQ_VCCTX0

ULC_SQ_HDOUTP0

ULC_SQ_VCCOB0

ULC_SQ_HDOUTN0

ULC_SQ_VCCTX1

ULC_SQ_HDOUTN1

ULC_SQ_VCCOB1

ULC_SQ_HDOUTP1

ULC_SQ_VCCRX1

ULC_SQ_HDINN1

ULC_SQ_VCCIB1

ULC_SQ_HDINP1

ULC_SQ_VCCAUX33

ULC_SQ_REFCLKN

ULC_SQ_REFCLKP

ULC_SQ_VCCP

ULC_SQ_HDINP2

ULC_SQ_VCCIB2

ULC_SQ_HDINN2

ULC_SQ_VCCRX2

ULC_SQ_HDOUTP2

ULC_SQ_VCCOB2

ULC_SQ_HDOUTN2

ULC_SQ_VCCTX2

ULC_SQ_HDOUTN3

ULC_SQ_VCCOB3

ULC_SQ_HDOUTP3

ULC_SQ_VCCTX3

ULC_SQ_HDINN3

ULC_SQ_VCCIB3

ULC_SQ_HDINP3

ULC_SQ_VCCRX3

11

T

C

T

A10

B9

C

T

C9

B8

C8

A8

C12

B11

C11

A11

B7

C

T

E7

C

T

D7

C7

A3

T

C

T

C3

B3

C2

A6

C6

B6

C

T

C5

B5

A4

A5

C4

B2

C

T

B1

A2

C1

4-222

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

L12

Ball/Pad Function

VCC

Bank

Dual Function

Differential

-

L13

L18

L19

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

N11

N12

N19

N20

P12

P19

R12

R19

T12

T19

U12

U19

V11

V12

V19

V20

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y12

Y13

Y18

4-223

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

Y19

Ball/Pad Function

VCC

Bank

-

Dual Function

Differential

D14

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

0

1

2

3

4

5

E6

E9

F12

K12

K13

D17

E22

E25

F19

K18

K19

F28

J25

K28

M21

M24

N21

N28

P21

R25

AA28

AB25

AE28

T25

U21

V21

V28

W21

W24

AA18

AA19

AE19

AF22

AG17

AG25

AA12

AA13

AE12

AF9

AG14

AG6

4-224

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AA3

AB6

AE3

T6

Ball/Pad Function

VCCIO6

VCCIO7

VCCIO8

VCCAUX

GND

Bank

Dual Function

Differential

6

7

8

-

U10

V10

V3

W10

W7

F3

J6

K3

M10

M7

N10

N3

P10

R6

AA25

AD28

AA10

AA11

AA20

AA21

K10

K11

K20

K21

L10

-

L11

-

L20

-

L21

-

Y10

Y11

Y20

Y21

A1

-

A13

A18

A24

A30

A7

GND

-

GND

-

GND

-

GND

-

GND

-

AA14

GND

-

4-225

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AA15

AA16

AA17

AA24

AA27

AA4

Ball/Pad Function

GND

Bank

Dual Function

Differential

-

AB24

AB7

AD12

AD19

AD27

AE22

AE27

AE4

AE9

AF14

AF17

AF25

AF6

AJ10

AJ21

AJ27

AJ4

AK1

AK13

AK18

AK24

AK30

AK7

B10

B21

B27

B4

D25

D6

E14

E17

F22

F27

F4

F9

G12

G19

4-226

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

J24

Ball/Pad Function

GND

Bank

Dual Function

Differential

-

J7

K14

K15

K16

K17

K27

K4

L14

L15

L16

L17

M23

M8

N14

N15

N16

N17

N27

N4

P11

P13

P14

P15

P16

P17

P18

P20

R10

R11

R13

R14

R15

R16

R17

R18

R20

R21

R24

R7

T10

T11

T13

4-227

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

T14

Ball/Pad Function

GND

NC

Bank

Dual Function

Differential

-

T15

T16

T17

T18

T20

T21

T24

T7

U11

U13

U14

U15

U16

U17

U18

U20

V14

V15

V16

V17

V27

V4

W23

W8

Y14

Y15

Y16

Y17

AA26

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB19

AB20

AB21

AB9

AC10

NC

4-228

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

AC11

AC21

AC22

AC8

AC9

AD21

AD22

AD4

AD5

AD6

AD7

AD8

AE23

AE5

AE6

AE7

AF20

AF23

AF5

AG23

AG26

D10

E10

Ball/Pad Function

NC

Bank

Dual Function

Differential

-

NC

E11

NC

F10

NC

F20

NC

F23

NC

F8

NC

G10

G20

G21

G7

NC

G8

NC

G9

NC

H19

H20

H21

H22

H6

NC

H8

NC

H9

NC

J10

NC

J20

NC

4-229

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)

LFE2M100E/SE

Ball Number

J21

Ball/Pad Function

Bank

Dual Function

Differential

NC

-

J9

K9

NC

R9

NC

U22

W9

NC

N13

N18

V13

VCCPLL

V18

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

*** These sysCONFIG pins are dedicated I/O pins for conﬁguration. The outpus are actively driven during normal device operation.

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-230

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

VCCIO

F4

VCCIO7

PL9A

7

-

VCCIO7

PL9A

7

-

VREF2_7

VREF1_7

T

VREF2_7

VREF1_7

T

F3

PL9B

C

PL9B

C

GNDIO

E1

GNDIO7

PL11A

PL11B

PL12A

PL12B

VCCIO7

PL13A

PL13B

PL14A

PL14B

GNDIO7

PL15A

PL15B

PL16A

VCCIO7

PL16B

PL17A

PL17B

PL18A

GNDIO7

PL18B

NC

GNDIO7

PL11A

PL11B

PL12A

PL12B

VCCIO7

PL13A

PL13B

PL14A

PL14B

GNDIO7

PL15A

PL15B

PL16A

VCCIO7

PL16B

PL17A

PL17B

PL18A

GNDIO7

PL18B

PL19A

PL19B

PL20A

PL20B

PL21A

VCCIO7

PL21B

PL22A

PL22B

PL23A

GNDIO7

PL23B

PL24A

PL24B

VCCIO7

PL25A

PL25B

PL26A

PL26B

GNDIO7

PL28A

PL28B

PL29A

PL29B

VCCIO7

PL30A

7

LUM0_SPLLT_IN_A/LDQ15

T (LVDS)*

7

-

LUM0_SPLLT_IN_A/LDQ15

T (LVDS)*

E2

7

-

LUM0_SPLLC_IN_A/LDQ15

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

C (LVDS)*

LUM0_SPLLC_IN_A/LDQ15 C (LVDS)*

K9

T

LUM0_SPLLT_FB_A/LDQ15

LUM0_SPLLC_FB_A/LDQ15

T

H7

C

VCCIO

F1

LDQ15

T (LVDS)*

LDQ15

T (LVDS)*

F2

C (LVDS)*

J8

T

H6

C

GNDIO

G2

7

-

LDQS15

LDQ15

T (LVDS)*

C (LVDS)*

T

7

-

LDQS15

LDQ15

T (LVDS)*

C (LVDS)*

T

G1

J7

VCCIO

L8

LDQ15

C

LDQ15

C

L9

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

L10

H5

GNDIO

J6

7

-

LDQ15

C

7

-

LDQ15

LDQ23

C

T (LVDS)*

C (LVDS)*

T

H2

H1

NC

-

G5

NC

-

G6

NC

-

C

M9

NC

-

T (LVDS)*

-

M10

H3

NC

-

LDQ23

LDQS23

C (LVDS)*

NC

-

T

C

H4

NC

-

J2

PL19A

-

7

-

T (LVDS)*

-

J1

PL19B

PL20A

PL20B

VCCIO7

PL21A

PL21B

PL22A

PL22B

GNDIO7

PL24A

PL24B

PL25A

PL25B

VCCIO7

PL26A

7

-

C (LVDS)*

7

-

LDQ23

C (LVDS)*

K2

T

K1

C

VCCIO

J4

T (LVDS)*

LDQ23

T (LVDS)*

J3

C (LVDS)*

J5

T

K5

C

GNDIO

L2

7

LDQ28

T (LVDS)*

7

LDQ32

T (LVDS)*

L1

C (LVDS)*

L7

T

K6

C

VCCIO

M2

LDQ28

T (LVDS)*

LDQ32

T (LVDS)*

4-231

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

LDQ28

Differential

Bank

7

-

Dual Function

LDQ32

Differential

M1

L6

PL26B

PL27A

PL27B

GNDIO7

PL28A

PL28B

PL29A

VCCIO7

PL29B

PL30A

PL30B

PL31A

GNDIO7

PL31B

NC

C (LVDS)*

PL30B

PL31A

PL31B

GNDIO7

PL32A

PL32B

PL33A

VCCIO7

PL33B

PL34A

PL34B

PL35A

GNDIO7

PL35B

PL37A

GNDIO7

PL37B

PL38A

PL38B

VCCIO7

PL39A

PL39B

PL40A

PL40B

GNDIO7

PL41A

PL41B

PL42A

PL42B

VCCIO7

PL43A

PL43B

PL44A

PL44B

GNDIO7

PL45A

PL45B

PL46A

VCCIO7

PL46B

PL47A

PL47B

PL48A

GNDIO7

PL48B

PL50A

PL50B

PL51A

PL51B

VCCIO7

PL52A

C (LVDS)*

LDQ28

T

LDQ32

T

L5

LDQ28

C

LDQ32

C

GNDIO

L3

7

-

LDQS28

LDQ28

T (LVDS)*

C (LVDS)*

T

7

-

LDQS32

LDQ32

T (LVDS)*

C (LVDS)*

T

L4

M3

VCCIO

M4

LDQ28

C

LDQ32

C

N1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

N2

M5

GNDIO

N6

7

-

LDQ28

C

7

-

LDQ32

C

P3

T (LVDS)*

-

P4

NC

-

7

-

C (LVDS)*

P9

NC

-

T

M7

NC

-

C

-

P1

NC

-

T (LVDS)*

P2

NC

-

C (LVDS)*

N7

NC

-

T

P7

NC

-

C

-

P5

PL33A

PL33B

PL34A

PL34B

VCCIO7

PL35A

PL35B

PL36A

PL36B

GNDIO7

PL37A

PL37B

PL38A

VCCIO7

PL38B

PL39A

PL39B

PL40A

GNDIO7

PL40B

PL42A

PL42B

PL43A

PL43B

VCCIO7

PL44A

7

-

LDQ37

T (LVDS)*

7

-

LDQ45

T (LVDS)*

N5

C (LVDS)*

P8

T

P6

C

VCCIO

R3

LDQ37

T (LVDS)*

LDQ45

T (LVDS)*

R4

C (LVDS)*

R10

P11

GNDIO

R7

T

C

7

-

LDQS37

LDQ37

T (LVDS)*

C (LVDS)*

T

7

-

LDQS45

LDQ45

T (LVDS)*

C (LVDS)*

T

R8

R5

VCCIO

T5

LDQ37

C

LDQ45

C

R1

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

R2

R11

GNDIO

T10

T1

7

LDQ37

C

7

LDQ45

C

LUM3_SPLLT_IN_A/LDQ46

T (LVDS)*

7

LUM3_SPLLT_IN_A/LDQ54

T (LVDS)*

T2

7

LUM3_SPLLC_IN_A/LDQ46

LUM3_SPLLT_FB_A/LDQ46

LUM3_SPLLC_FB_A/LDQ46

C (LVDS)*

LUM3_SPLLC_IN_A/LDQ54 C (LVDS)*

U10

U8

T

LUM3_SPLLT_FB_A/LDQ54

LUM3_SPLLC_FB_A/LDQ54

T

C

VCCIO

T6

LDQ46

T (LVDS)*

LDQ54

T (LVDS)*

4-232

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

7

-

Dual Function

LDQ46

Differential

Bank

Dual Function

LDQ54

Differential

R6

U9

PL44B

PL45A

PL45B

GNDIO7

PL46A

PL46B

PL47A

VCCIO7

PL47B

PL48A

PL48B

PL49A

GNDIO7

PL49B

PL51A

PL51B

PL52A

PL52B

PL53A

VCCIO6

PL53B

PL54A

PL54B

PL55A

GNDIO6

PL55B

PL56A

PL56B

VCCIO6

PL57A

PL57B

PL58A

PL58B

GNDIO6

PL60A

PL60B

PL61A

PL61B

VCCIO6

PL62A

PL62B

PL63A

PL63B

GNDIO6

PL64A

PL64B

PL65A

VCCIO6

PL65B

PL66A

PL66B

C (LVDS)*

PL52B

PL53A

PL53B

GNDIO7

PL54A

PL54B

PL55A

VCCIO7

PL55B

PL56A

PL56B

PL57A

GNDIO7

PL57B

PL59A

PL59B

PL60A

PL60B

PL61A

VCCIO6

PL61B

PL62A

PL62B

PL63A

GNDIO6

PL63B

PL64A

PL64B

VCCIO6

PL65A

PL65B

PL66A

PL66B

GNDIO6

PL68A

PL68B

PL69A

PL69B

VCCIO6

PL70A

PL70B

PL71A

PL71B

GNDIO6

PL72A

PL72B

PL73A

VCCIO6

PL73B

PL74A

PL74B

7

-

C (LVDS)*

LDQ46

T

LDQ54

T

T7

LDQ46

C

LDQ54

C

GNDIO

U5

7

-

LDQS46

LDQ46

T (LVDS)*

C (LVDS)*

T

7

-

LDQS54

LDQ54

T (LVDS)*

C (LVDS)*

T

U6

U7

VCCIO

V9

LDQ46

C

LDQ54

C

V11

V10

U4

T (LVDS)*

C (LVDS)*

T

T (LVDS)*

C (LVDS)*

T

LDQ46

LDQ54

PCLKT7_0/LDQ46

PCLKT7_0/LDQ54

GNDIO

U3

7

6

-

PCLKC7_0/LDQ46

PCLKT6_0/LDQ55

PCLKC6_0/LDQ55

VREF2_6/LDQ55

VREF1_6/LDQ55

LDQ55

C

T (LVDS)*

C (LVDS)*

T

7

6

-

PCLKC7_0/LDQ54

PCLKT6_0/LDQ63

PCLKC6_0/LDQ63

VREF2_6/LDQ63

VREF1_6/LDQ63

LDQ63

C

T (LVDS)*

C (LVDS)*

T

U2

U1

V5

V6

C

V7

T (LVDS)*

VCCIO

V8

LDQ55

LDQS55

C (LVDS)*

LDQ63

LDQS63

C (LVDS)*

V4

T

C

T

C

V3

V2

T (LVDS)*

GNDIO

V1

6

LDQ55

C (LVDS)*

6

-

LDQ63

C (LVDS)*

W7

T

W5

C

VCCIO

W2

LLM3_SPLLT_IN_A/LDQ55

LLM3_SPLLC_IN_A/LDQ55

T (LVDS)*

LLM4_SPLLT_IN_A/LDQ63

T (LVDS)*

W1

C (LVDS)*

LLM4_SPLLC_IN_A/LDQ63 C (LVDS)*

Y6

6

-

LLM3_SPLLT_FB_A/LDQ55

LLM3_SPLLC_FB_A/LDQ55

T

LLM4_SPLLT_FB_A/LDQ63

LLM4_SPLLC_FB_A/LDQ63

T

W6

C

GNDIO

Y1

6

-

LDQ64

T (LVDS)*

6

-

LDQ72

T (LVDS)*

Y2

C (LVDS)*

Y7

T

Y5

C

VCCIO

W10

Y8

LDQ64

T (LVDS)*

LDQ72

T (LVDS)*

C (LVDS)*

Y4

T

Y3

C

GNDIO

AA1

AA2

AA8

VCCIO

Y9

6

LDQS64

LDQ64

T (LVDS)*

C (LVDS)*

T

6

LDQS72

LDQ72

T (LVDS)*

C (LVDS)*

T

LDQ64

C

LDQ72

C

AA6

AA7

T (LVDS)*

C (LVDS)*

T (LVDS)*

C (LVDS)*

4-233

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

6

-

Dual Function

Differential

Bank

6

-

Dual Function

Differential

AA4

GNDIO

AA3

AA9

AA10

AA5

AB6

AB1

VCCIO

AB2

AC8

AB10

AC1

GNDIO

AC2

AB7

AB5

VCCIO

AC3

AC4

AC10

AC9

GNDIO

AC7

AC5

AC6

AD5

-

PL67A

GNDIO6

PL67B

PL69A

PL69B

PL70A

PL70B

PL71A

VCCIO6

PL71B

PL72A

PL72B

PL73A

GNDIO6

PL73B

PL74A

PL74B

VCCIO6

PL75A

PL75B

PL76A

PL76B

GNDIO6

NC

LDQ64

T

PL75A

GNDIO6

PL75B

PL77A

PL77B

PL78A

PL78B

PL79A

VCCIO6

PL79B

PL80A

PL80B

PL81A

GNDIO6

PL81B

PL82A

PL82B

VCCIO6

PL83A

PL83B

PL84A

PL84B

GNDIO6

PL86A

PL86B

PL87A

PL87B

VCCIO6

PL88A

PL88B

PL89A

PL89B

GNDIO6

PL90A

PL90B

PL91A

VCCIO6

PL91B

PL92A

PL92B

PL93A

GNDIO6

PL93B

PL95A

PL95B

PL96A

PL96B

PL97A

VCCIO6

PL97B

PL98A

LDQ72

T

6

-

LDQ64

LDQ73

C

T (LVDS)*

C (LVDS)*

T

6

-

LDQ72

LDQ81

C

T (LVDS)*

C (LVDS)*

T

C

T (LVDS)*

LDQ73

LDQS73

C (LVDS)*

LDQ81

LDQS81

C (LVDS)*

T

C

T

C

T (LVDS)*

6

-

LDQ73

C (LVDS)*

6

-

LDQ81

C (LVDS)*

T

C

LDQ73

T (LVDS)*

LDQ81

T (LVDS)*

C (LVDS)*

T

C

-

6

-

LDQ90

T (LVDS)*

NC

-

C (LVDS)*

NC

-

T

NC

-

C

-

AD4

AD3

AD10

AD8

-

NC

-

LDQ90

T (LVDS)*

NC

-

C (LVDS)*

NC

-

T

NC

-

C

-

AD2

AD1

AD9

-

NC

-

6

-

LDQS90

LDQ90

T (LVDS)*

C (LVDS)*

T

NC

-

NC

-

AC11

AD6

AD7

AE1

-

NC

-

LDQ90

C

NC

-

T (LVDS)*

C (LVDS)*

T

NC

-

NC

-

AE2

AF2

AF1

AE5

AE6

AF4

VCCIO

AF3

AF5

NC

-

6

LDQ90

LDQ99

C

T (LVDS)*

C (LVDS)*

T

PL78A

PL78B

PL79A

PL79B

PL80A

VCCIO6

PL80B

PL81A

6

LDQ82

T (LVDS)*

C (LVDS)*

T

C

T (LVDS)*

LDQ82

C (LVDS)*

T

LDQ99

C (LVDS)*

T

4-234

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AF6

AG1

PL81B

PL82A

6

LDQ82

C

PL98B

PL99A

6

LDQ99

C

LLM0_GPLLT_IN_A**/

LDQS99

6

-

LLM0_GPLLT_IN_A**/LDQS82

T (LVDS)*

C (LVDS)*

6

-

T (LVDS)*

C (LVDS)*

GNDIO

AG2

GNDIO6

PL82B

GNDIO6

PL99B

LLM0_GPLLC_IN_A**/

LDQ99

6

LLM0_GPLLC_IN_A**/LDQ82

6

AE9

AF7

PL83A

PL83B

VCCIO6

PL84A

6

LLM0_GPLLT_FB_A/LDQ82

LLM0_GPLLC_FB_A/LDQ82

T

PL100A

PL100B

VCCIO6

PL101A

6

LLM0_GPLLT_FB_A/LDQ99

LLM0_GPLLC_FB_A/LDQ99

T

C

VCCIO

AH1

LLM0_GDLLT_IN_A**/LDQ82

LLM0_GDLLC_IN_A**/LDQ82

T (LVDS)*

C (LVDS)*

LLM0_GDLLT_IN_A**/LDQ99 T (LVDS)*

LLM0_GDLLC_IN_A**/

C (LVDS)*

AH2

PL84B

6

PL101B

6

LDQ99

AG5

AG4

GNDIO

AG6

AJ1

PL85A

6

LLM0_GDLLT_FB_A/LDQ82

LLM0_GDLLC_FB_A/LDQ82

T

PL102A

PL102B

6

LLM0_GDLLT_FB_A/LDQ99

LLM0_GDLLC_FB_A/LDQ99

T

PL85B

6

C

6

C

GNDIO6

-

GNDIO6

-

LLM0_PLLCAP

PL87A

6

LLM0_PLLCAP

PL104A

6

T

6

T

AJ2

PL87B

6

C

PL104B

6

C

AK2

AK1

AL1

TCK

-

TCK

-

TDI

-

TDI

-

TMS

-

TMS

-

AF10

AK3

AN2

AM2

AN1

AM3

AN3

AP2

AM1

AP3

AN4

AP4

AL3

TDO

-

TDO

-

VCCJ

-

VCCJ

-

LLC_SQ_VCCRX3

LLC_SQ_HDINP3

LLC_SQ_VCCIB3

LLC_SQ_HDINN3

LLC_SQ_VCCTX3

LLC_SQ_HDOUTP3

LLC_SQ_VCCOB3

LLC_SQ_HDOUTN3

LLC_SQ_VCCTX2

LLC_SQ_HDOUTN2

LLC_SQ_VCCOB2

LLC_SQ_HDOUTP2

LLC_SQ_VCCRX2

LLC_SQ_HDINN2

LLC_SQ_VCCIB2

LLC_SQ_HDINP2

LLC_SQ_VCCP

LLC_SQ_REFCLKP

LLC_SQ_REFCLKN

LLC_SQ_VCCAUX33

LLC_SQ_HDINP1

LLC_SQ_VCCIB1

LLC_SQ_HDINN1

LLC_SQ_VCCRX1

LLC_SQ_HDOUTP1

LLC_SQ_VCCOB1

LLC_SQ_HDOUTN1

LLC_SQ_VCCTX1

LLC_SQ_HDOUTN0

14

LLC_SQ_VCCRX3

LLC_SQ_HDINP3

LLC_SQ_VCCIB3

LLC_SQ_HDINN3

LLC_SQ_VCCTX3

LLC_SQ_HDOUTP3

LLC_SQ_VCCOB3

LLC_SQ_HDOUTN3

LLC_SQ_VCCTX2

LLC_SQ_HDOUTN2

LLC_SQ_VCCOB2

LLC_SQ_HDOUTP2

LLC_SQ_VCCRX2

LLC_SQ_HDINN2

LLC_SQ_VCCIB2

LLC_SQ_HDINP2

LLC_SQ_VCCP

LLC_SQ_REFCLKP

LLC_SQ_REFCLKN

LLC_SQ_VCCAUX33

LLC_SQ_HDINP1

LLC_SQ_VCCIB1

LLC_SQ_HDINN1

LLC_SQ_VCCRX1

LLC_SQ_HDOUTP1

LLC_SQ_VCCOB1

LLC_SQ_HDOUTN1

LLC_SQ_VCCTX1

LLC_SQ_HDOUTN0

14

T

C

T

C

T

C

T

C

T

AP5

AN5

AM4

AL4

C

T

C

T

AM5

AL6

AL5

T

AK5

AK6

AM6

AL8

C

T

C

T

C

T

AM7

AN6

AP6

AK7

AP7

AN7

AP8

C

4-235

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

14

5

Dual Function

Differential

AL9

AP9

LLC_SQ_VCCOB0

14

LLC_SQ_VCCOB0

LLC_SQ_HDOUTP0

LLC_SQ_VCCTX0

LLC_SQ_HDINN0

LLC_SQ_VCCIB0

LLC_SQ_HDINP0

LLC_SQ_VCCRX0

VCCIO5

PB32A

LLC_SQ_HDOUTP0

LLC_SQ_VCCTX0

LLC_SQ_HDINN0

LLC_SQ_VCCIB0

LLC_SQ_HDINP0

LLC_SQ_VCCRX0

-

14

-

T

C

T

C

T

AN8

AM8

AN9

AM9

AL7

-

AJ12

AH12

-

NC

-

5

BDQ33

T

NC

-

PB32B

5

C

-

GNDIO5

VCCIO5

PB36A

-

5

AL13

AK13

-

NC

-

5

BDQ33

T

NC

-

PB36B

5

C

-

GNDIO5

PB38A

-

AE14

AG13

AN14

AP14

AH14

AJ15

VCCIO

GNDIO

AL14

AM14

AF14

AF13

VCCIO

AE15

AG14

AH15

AK15

GNDIO

AL15

AM15

AK16

AJ16

AN15

VCCIO

AP15

AG15

GNDIO

AE16

AF15

VCCIO

AD16

AK17

AH16

AN16

GNDIO

AP16

NC

-

5

BDQ42

T

C

T

NC

-

PB38B

5

PB30A

5

-

BDQ33

T

C

T

PB39A

5

PB30B

PB39B

5

C

T

PB31A

PB40A

5

PB31B

C

PB40B

5

C

VCCIO5

GNDIO5

PB33A

VCCIO5

GNDIO5

PB42A

5

-

5

-

BDQS33

BDQ33

T

C

T

5

BDQS42

BDQ42

T

C

T

PB33B

PB42B

5

PB35A

PB44A

5

PB35B

C

PB44B

5

C

VCCIO5

PB36A

VCCIO5

PB45A

5

BDQ33

T

C

T

5

BDQ42

T

C

T

PB36B

PB45B

5

PB37A

PB46A

5

PB37B

C

PB46B

5

C

GNDIO5

PB38A

GNDIO5

PB47A

-

5

-

BDQ42

T

C

T

C

T

5

BDQ51

T

C

T

C

T

PB38B

PB47B

5

PB39A

PB48A

5

PB39B

PB48B

5

PB40A

PB49A

5

VCCIO5

PB40B

VCCIO5

PB49B

5

BDQ42

C

T

5

BDQ51

C

T

PB42A

BDQS42

PB51A

5

BDQS51

GNDIO5

PB42B

GNDIO5

PB51B

-

5

-

BDQ42

C

T

5

BDQ51

C

T

PB44A

PB53A

5

VCCIO5

PB44B

VCCIO5

PB53B

5

BDQ42

C

T

C

T

5

BDQ51

C

T

C

T

PB45A

PB54A

5

PB45B

PB54B

5

PB46A

PB55A

5

GNDIO5

PB46B

GNDIO5

PB55B

-

5

BDQ42

C

5

BDQ51

C

4-236

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

5

-

Dual Function

BDQ51

Differential

Bank

Dual Function

BDQ60

Differential

AL17

AM17

AN17

AP17

AD17

AE17

VCCIO

AL18

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

VCCIO5

PB50A

PB50B

GNDIO5

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

VCCIO5

GNDIO5

PB58A

VCCIO4

PB58B

PB59A

PB59B

PB60A

GNDIO4

PB60B

PB61A

PB61B

PB62A

VCCIO4

PB62B

PB63A

PB63B

PB64A

GNDIO4

PB64B

PB65A

PB65B

PB66A

PB66B

PB67A

PB67B

VCCIO4

GNDIO4

PB69A

PB69B

PB71A

PB71B

VCCIO4

PB72A

PB72B

T

C

T

PB56A

PB56B

PB57A

PB57B

PB58A

PB58B

VCCIO5

PB59A

PB59B

GNDIO5

PB60A

PB60B

PB61A

PB61B

PB62A

PB62B

VCCIO5

GNDIO5

PB67A

VCCIO4

PB67B

PB68A

PB68B

PB69A

GNDIO4

PB69B

PB70A

PB70B

PB71A

VCCIO4

PB71B

PB72A

PB72B

PB73A

GNDIO4

PB73B

PB74A

PB74B

PB75A

PB75B

PB76A

PB76B

VCCIO4

GNDIO4

PB78A

PB78B

PB80A

PB80B

VCCIO4

PB81A

PB81B

5

-

T

C

T

BDQ51

BDQ60

BDQ51

BDQ60

BDQ51

C

T

BDQ60

C

T

BDQ51

BDQ60

BDQ51

C

BDQ60

C

BDQ51

T

BDQ60

T

AM18

GNDIO

AP18

AN18

AG17

AJ17

C

5

-

BDQS51

T

C

T

5

BDQS60

BDQ60

T

C

T

BDQ51

VREF2_5/BDQ51

VREF1_5/BDQ51

PCLKT5_0/BDQ51

PCLKC5_0/BDQ51

VREF2_5/BDQ60

VREF1_5/BDQ60

C

T

C

T

AF17

AH17

VCCIO

GNDIO

AF18

VCCIO

AD18

AP19

AN19

AP20

GNDIO

AM20

AN20

AM21

AG18

VCCIO

AE18

AJ18

5

-

PCLKT5_0/BDQ60

PCLKC5_0/BDQ60

C

4

-

PCLKT4_0/BDQ60

T

4

-

PCLKT4_0/BDQ69

T

PCLKC4_0/BDQ60

VREF2_4/BDQ60

VREF1_4/BDQ60

BDQS60

C

T

C

T

PCLKC4_0/BDQ69

VREF2_4/BDQ69

VREF1_4/BDQ69

BDQS69

C

T

C

T

4

-

BDQ60

C

T

C

T

4

-

BDQ69

C

T

C

T

BDQ60

C

T

C

T

BDQ69

C

T

C

T

AH18

AK18

GNDIO

AK19

AP21

AN21

AL20

4

-

BDQ60

BDQ69

C

T

4

-

BDQ69

BDQ78

C

T

C

T

C

T

AK20

AN22

AL21

C

T

C

T

C

VCCIO

GNDIO

AH19

AJ20

4

BDQS69

BDQ69

T

C

T

4

BDQS78

BDQ78

T

C

T

AD20

AF20

VCCIO

AJ19

C

BDQ69

T

BDQ78

T

AH20

C

4-237

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

BDQ69

Differential

Bank

4

Dual Function

BDQ78

Differential

AE20

AG20

GNDIO

AH22

-

PB73A

PB73B

GNDIO4

NC

4

-

T

PB82A

PB82B

T

BDQ69

C

4

BDQ78

C

GNDIO4

-

PB89A

4

BDQ87

T

-

VCCIO4

4

AH21

AG22

AG21

-

NC

-

PB89B

4

BDQ87

C

T

NC

-

PB90A

4

NC

-

PB90B

4

C

-

GNDIO4

-

AM22

AL22

VCCIO

AP23

AN23

GNDIO

AM24

AL24

AK22

AJ22

AL23

AK23

VCCIO

AJ23

AH23

GNDIO

AL28

AM26

AN26

AM27

AN27

AP26

AL26

AP27

AN28

AP28

AK28

AP29

AN29

AM28

AL27

AM29

AL29

AL30

AK30

AK29

AM30

AL31

AM31

AN30

AP30

AL32

PB74A

PB74B

VCCIO4

PB77A

PB77B

GNDIO4

PB78A

PB78B

PB79A

PB79B

PB80A

PB80B

VCCIO4

PB81A

PB81B

GNDIO4

4

-

BDQ78

T

PB92A

4

BDQ96

T

C

PB92B

4

C

VCCIO4

4

BDQ78

T

PB95A

4

BDQ96

T

C

PB95B

4

C

GNDIO4

-

4

-

BDQS78

BDQ78

T

C

T

PB96A

4

BDQS96

BDQ96

T

C

T

PB96B

4

PB97A

4

C

T

PB97B

4

C

T

PB98A

4

C

PB98B

4

C

VCCIO4

4

BDQ78

T

PB99A

4

BDQ96

T

C

PB99B

4

C

GNDIO4

-

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

13

LRC_SQ_VCCRX3

LRC_SQ_HDINP3

LRC_SQ_VCCIB3

LRC_SQ_HDINN3

LRC_SQ_VCCTX3

LRC_SQ_HDOUTP3

LRC_SQ_VCCOB3

LRC_SQ_HDOUTN3

LRC_SQ_VCCTX2

LRC_SQ_HDOUTN2

LRC_SQ_VCCOB2

LRC_SQ_HDOUTP2

LRC_SQ_VCCRX2

LRC_SQ_HDINN2

LRC_SQ_VCCIB2

LRC_SQ_HDINP2

LRC_SQ_VCCP

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

LRC_SQ_VCCAUX33

LRC_SQ_HDINP1

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

13

T

C

T

C

T

C

T

C

T

C

T

C

T

LRC_SQ_REFCLKP

LRC_SQ_REFCLKN

LRC_SQ_VCCAUX33

LRC_SQ_HDINP1

LRC_SQ_VCCIB1

LRC_SQ_HDINN1

LRC_SQ_VCCRX1

LRC_SQ_HDOUTP1

LRC_SQ_VCCOB1

T

C

T

C

T

C

T

4-238

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

13

8

Dual Function

Differential

AP31

AN31

AP32

AM34

AP33

AN32

AM32

AN34

AM33

AN33

AH28

AD24

AJ29

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

13

8

C

LRC_SQ_HDOUTN1

LRC_SQ_VCCTX1

LRC_SQ_HDOUTN0

LRC_SQ_VCCOB0

LRC_SQ_HDOUTP0

LRC_SQ_VCCTX0

LRC_SQ_HDINN0

LRC_SQ_VCCIB0

LRC_SQ_HDINP0

LRC_SQ_VCCRX0

CFG2

C

T

C

T

C

T

C

T

CFG1

8

CFG1

8

CFG0

8

CFG0

8

AF25

AJ28

PROGRAMN

CCLK

8

PROGRAMN

CCLK

8

AE25

AK31

GNDIO

AE24

AJ30

INITN

8

INITN

8

DONE

8

DONE

8

GNDIO8

-

GNDIO8

-

WRITEN***

CS1N***

8

WRITEN***

CS1N***

8

AD25

AG29

VCCIO

AG28

AG30

AH29

GNDIO

AF26

AH30

AE26

AJ31

CSN***

8

CSN***

8

D0/SPIFASTN***

VCCIO8

8

D0/SPIFASTN***

VCCIO8

8

D1***

8

D1***

8

D2***

8

D2***

8

D3***

8

D3***

8

GNDIO8

-

GNDIO8

-

D4***

8

D4***

8

D5***

8

D5***

8

D6***

8

D6***

8

D7***

8

D7***

8

VCCIO

AG27

VCCIO8

8

VCCIO8

8

DI/CSSPI0N***

8

DI/CSSPI0N***

8

DOUT/CSON/

CSSPI1N***

DOUT/CSON/

CSSPI1N***

AK32

8

AK33

AF27

BUSY/SISPI***

RLM0_PLLCAP

PR85B

8

3

-

BUSY/SISPI***

RLM0_PLLCAP

PR102B

8

3

AF28

RLM0_GDLLC_FB_A

C

3

-

RLM0_GDLLC_FB_A/RDQ99

RLM0_GDLLT_FB_A/RDQ99

C

GNDIO

AD26

GNDIO3

PR85A

3

RLM0_GDLLT_FB_A

RLM0_GDLLC_IN_A**

T

PR102A

3

T

RLM0_GDLLC_IN_A**/

RDQ99

AJ32

AJ33

PR84B

PR84A

3

C (LVDS)*

PR101B

PR101A

3

C (LVDS)*

RLM0_GDLLT_IN_A**/

RDQ99

RLM0_GDLLT_IN_A**

RLM0_GPLLC_IN_A**

T (LVDS)*

C

T (LVDS)*

C

RLM0_GPLLC_IN_A**/

RDQ99

AJ34

VCCIO

AK34

PR83B

VCCIO3

PR83A

PR82B

PR82A

GNDIO3

3

-

PR100B

VCCIO3

PR100A

PR99B

3

-

RLM0_GPLLT_IN_A**/

RDQ99

RLM0_GPLLT_IN_A**

RLM0_GPLLC_FB_A

T

AH33

C (LVDS)*

RLM0_GPLLC_FB_A/RDQ99 C (LVDS)*

RLM0_GPLLT_FB_A/

T (LVDS)*

AH34

RLM0_GPLLT_FB_A/RDQS82**** T (LVDS)*

PR99A

RDQS99

GNDIO

GNDIO3

4-239

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

3

-

Dual Function

RDQ82

Differential

C

Bank

3

-

Dual Function

RDQ99

Differential

C

AF29

AF31

AG33

AG34

VCCIO

AF30

AF32

AE29

AE30

AF33

AF34

-

PR81B

PR81A

PR80B

PR80A

VCCIO3

PR79B

PR79A

PR78B

PR78A

NC

PR98B

PR98A

PR97B

PR97A

VCCIO3

PR96B

PR96A

PR95B

PR95A

PR93B

PR93A

GNDIO3

PR92B

PR92A

PR91B

PR91A

VCCIO3

PR90B

PR90A

PR89B

GNDIO3

PR89A

PR88B

PR88A

PR87B

VCCIO3

PR87A

PR86B

PR86A

PR84B

GNDIO3

PR84A

PR83B

PR83A

PR82B

VCCIO3

PR82A

PR81B

PR81A

GNDIO3

PR80B

PR80A

PR79B

PR79A

VCCIO3

PR78B

PR78A

PR77B

PR77A

PR75B

PR75A

RDQ82

T

RDQ99

T

RDQ82

C (LVDS)*

T (LVDS)*

RDQ99

C (LVDS)*

T (LVDS)*

RDQ82

RDQ99

RDQ82

C

RDQ99

RDQ90

C

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

C

T

NC

-

AC27

AC28

AD29

AD30

-

NC

-

3

-

RDQ90

C (LVDS)*

NC

-

T (LVDS)*

NC

-

C

T

NC

-

AE33

AE34

AD32

-

NC

-

RDQ90

RDQS90

RDQ90

C (LVDS)*

T (LVDS)*

C

NC

-

NC

-

AD31

AB25

AC25

AB28

-

NC

-

3

-

RDQ90

T

NC

-

C (LVDS)*

T (LVDS)*

C

NC

-

NC

-

AA26

AD33

AD34

AC29

GNDIO

AA27

AC32

AC31

AA25

VCCIO

AC24

AC33

AC34

GNDIO

AB24

Y26

NC

-

RDQ90

RDQ81

T

NC

-

C (LVDS)*

T (LVDS)*

C

NC

-

PR76B

GNDIO3

PR76A

PR75B

PR75A

PR74B

VCCIO3

PR74A

PR73B

PR73A

GNDIO3

PR72B

PR72A

PR71B

PR71A

VCCIO3

PR70B

PR70A

PR69B

PR69A

PR67B

PR67A

3

-

RDQ73

C

3

-

RDQ73

T

3

-

RDQ81

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

RDQ73

T

RDQ81

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS73

RDQS81

3

RDQ73

C

3

RDQ81

C

T

AB33

AB34

VCCIO

Y27

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQ73

RDQ64

C

RDQ81

RDQ72

C

AB29

AA34

AA33

AA31

AA32

T

C (LVDS)*

T (LVDS)*

C

T

C

T

4-240

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

GNDIO

AA28

AA29

AA30

AB30

VCCIO

Y28

GNDIO3

PR66B

PR66A

PR65B

PR65A

VCCIO3

PR64B

PR64A

PR63B

GNDIO3

PR63A

PR62B

PR62A

PR61B

VCCIO3

PR61A

PR60B

PR60A

PR58B

GNDIO3

PR58A

PR57B

PR57A

PR56B

VCCIO3

PR56A

PR55B

PR55A

GNDIO3

PR54B

PR54A

PR53B

PR53A

VCCIO3

PR52B

PR52A

PR51B

PR51A

PR49B

PR49A

GNDIO2

PR48B

PR48A

PR47B

PR47A

VCCIO2

PR46B

PR46A

PR45B

GNDIO2

PR45A

-

GNDIO3

PR74B

PR74A

PR73B

PR73A

VCCIO3

PR72B

PR72A

PR71B

GNDIO3

PR71A

PR70B

PR70A

PR69B

VCCIO3

PR69A

PR68B

PR68A

PR66B

GNDIO3

PR66A

PR65B

PR65A

PR64B

VCCIO3

PR64A

PR63B

PR63A

GNDIO3

PR62B

PR62A

PR61B

PR61A

VCCIO3

PR60B

PR60A

PR59B

PR59A

PR57B

PR57A

GNDIO2

PR56B

PR56A

PR55B

PR55A

VCCIO2

PR54B

PR54A

PR53B

GNDIO2

PR53A

-

3

-

RDQ64

C (LVDS)*

3

-

RDQ72

C (LVDS)*

T (LVDS)*

C

T

C

T

RDQ64

RDQS64

RDQ64

C (LVDS)*

T (LVDS)*

C

RDQ72

RDQS72

RDQ72

C (LVDS)*

T (LVDS)*

C

Y29

AA24

GNDIO

Y25

3

RDQ64

T

3

RDQ72

T

Y31

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

Y30

Y24

VCCIO

W25

Y33

RDQ64

T

RDQ72

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

Y34

W28

GNDIO

V26

3

-

RLM3_SPLLC_FB_A/RDQ55

3

-

RLM4_SPLLC_FB_A/RDQ63

3

-

RLM3_SPLLT_FB_A/RDQ55

RLM3_SPLLC_IN_A/RDQ55

RLM3_SPLLT_IN_A/RDQ55

RDQ55

T

3

-

RLM4_SPLLT_FB_A/RDQ63

T

V28

C (LVDS)*

T (LVDS)*

C

RLM4_SPLLC_IN_A/RDQ63 C (LVDS)*

RLM4_SPLLT_IN_A/RDQ63 T (LVDS)*

V27

V25

RDQ63

C

VCCIO

W24

W33

W34

GNDIO

V24

RDQ55

T

RDQ63

T

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

RDQS55

RDQS63

3

2

-

RDQ55

C

3

2

-

RDQ63

C

U26

T

W29

W30

VCCIO

U27

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

VREF2_3/RDQ55

VREF1_3/RDQ55

PCLKC3_0/RDQ55

PCLKT3_0/RDQ55

PCLKC2_0/RDQ46

PCLKT2_0/RDQ46

C

VREF2_3/RDQ63

VREF1_3/RDQ63

PCLKC3_0/RDQ63

PCLKT3_0/RDQ63

PCLKC2_0/RDQ54

PCLKT2_0/RDQ54

C

V29

T

V31

C (LVDS)*

V32

T (LVDS)*

V33

C

T

C

T

V34

GNDIO

U24

2

-

RDQ46

C (LVDS)*

2

-

RDQ54

C (LVDS)*

U25

T (LVDS)*

V30

C

T

C

T

Y32

VCCIO

U28

RDQ46

RDQS46

RDQ46

C (LVDS)*

T (LVDS)*

C

RDQ54

RDQS54

RDQ54

C (LVDS)*

T (LVDS)*

C

U29

U33

GNDIO

U34

2

RDQ46

T

2

RDQ54

T

4-241

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

RDQ46

Differential

C (LVDS)*

T (LVDS)*

C

Bank

Dual Function

RDQ54

Differential

C (LVDS)*

T (LVDS)*

C

T30

U30

T29

PR44B

PR44A

PR43B

VCCIO2

PR43A

PR42B

PR42A

PR40B

PR40A

GNDIO2

PR39B

PR39A

PR38B

PR38A

VCCIO2

PR37B

PR37A

PR36B

GNDIO2

PR36A

PR35B

PR35A

PR34B

VCCIO2

PR34A

PR33B

PR33A

NC

2

PR52B

PR52A

PR51B

VCCIO2

PR51A

PR50B

PR50A

PR48B

PR48A

GNDIO2

PR47B

PR47A

PR46B

PR46A

VCCIO2

PR45B

PR45A

PR44B

GNDIO2

PR44A

PR43B

PR43A

PR42B

VCCIO2

PR42A

PR41B

PR41A

PR40B

GNDIO2

PR40A

PR39B

PR39A

PR38B

VCCIO2

PR38A

PR37B

PR37A

GNDIO2

PR35B

PR35A

GNDIO2

PR34B

PR34A

PR33B

PR33A

VCCIO2

PR32B

PR32A

PR31B

GNDIO2

PR31A

2

RDQ46

RDQ54

2

-

RUM3_SPLLC_FB_A/RDQ46

2

-

RUM3_SPLLC_FB_A/RDQ54

VCCIO

T28

RUM3_SPLLT_FB_A/RDQ46

RUM3_SPLLC_IN_A/RDQ46

RUM3_SPLLT_IN_A/RDQ46

RDQ37

T

RUM3_SPLLT_FB_A/RDQ54

T

U31

U32

T33

C (LVDS)*

RUM3_SPLLC_IN_A/RDQ54 C (LVDS)*

RUM3_SPLLT_IN_A/RDQ54 T (LVDS)*

T (LVDS)*

C

T

RDQ45

C

T

T34

RDQ37

GNDIO

R27

R28

R29

R30

VCCIO

R33

R34

R32

GNDIO

R31

P34

2

-

RDQ37

C (LVDS)*

2

-

RDQ45

C (LVDS)*

T (LVDS)*

C

T

C

T

RDQ37

RDQS37

RDQ37

C (LVDS)*

T (LVDS)*

C

RDQ45

RDQS45

RDQ45

C (LVDS)*

T (LVDS)*

C

2

-

RDQ37

T

2

-

RDQ45

T

C (LVDS)*

T (LVDS)*

C

C (LVDS)*

T (LVDS)*

C

P33

R26

VCCIO

T25

RDQ37

T

RDQ45

T

P28

C (LVDS)*

T (LVDS)*

C (LVDS)*

T (LVDS)*

C

P27

P30

-

P29

NC

-

2

-

T

P31

NC

-

C (LVDS)*

T (LVDS)*

C

P32

NC

-

R25

-

NC

-

T24

NC

-

T

N34

N33

GNDIO

M34

M33

-

NC

-

C (LVDS)*

T (LVDS)*

NC

-

GNDIO2

PR31B

PR31A

-

2

-

RDQ28

C

T

2

-

RDQ32

C

T

R24

P24

PR30B

PR30A

PR29B

PR29A

VCCIO2

PR28B

PR28A

PR27B

GNDIO2

PR27A

2

-

RDQ28

C (LVDS)*

2

-

RDQ32

C (LVDS)*

T (LVDS)*

N30

M29

VCCIO

N28

N29

N24

GNDIO

N25

C

T

C

T

RDQ28

RDQS28

RDQ28

C (LVDS)*

T (LVDS)*

C

RDQ32

RDQS32

RDQ32

C (LVDS)*

T (LVDS)*

C

2

RDQ28

T

2

RDQ32

T

4-242

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

-

Dual Function

RDQ28

Differential

C (LVDS)*

T (LVDS)*

C

Bank

2

-

Dual Function

RDQ32

Differential

C (LVDS)*

T (LVDS)*

C

M28

M27

L27

PR26B

PR26A

PR30B

PR30A

RDQ28

RDQ32

PR25B

RDQ28

PR29B

RDQ32

VCCIO

M26

M32

M31

GNDIO

-

VCCIO2

PR25A

RDQ28

T

PR29A

RDQ32

T

PR24B

C (LVDS)*

T (LVDS)*

PR28B

C (LVDS)*

T (LVDS)*

PR24A

PR28A

GNDIO2

-

VCCIO2

2

-

L34

PR22B

2

-

C

PR22B

RDQ23

C

L33

PR22A

T

PR22A

T

L32

PR21B

C (LVDS)*

T (LVDS)*

PR21B

C (LVDS)*

T (LVDS)*

L31

PR21A

VCCIO

L28

VCCIO2

PR20B

C

PR20B

RDQ23

RDQ15

C

L29

PR20A

T

PR20A

T

M30

L30

PR19B

C (LVDS)*

PR19B

C (LVDS)*

PR19A

T (LVDS)*

PR19A

T (LVDS)*

K34

PR18B

RDQ15

C

T

PR18B

C

T

K33

PR18A

GNDIO

K30

GNDIO2

PR17B

2

-

RDQ15

C (LVDS)*

PR17B

2

-

RDQ15

C (LVDS)*

K29

PR17A

T (LVDS)*

PR17A

T (LVDS)*

J34

PR16B

C

T

PR16B

C

T

J33

PR16A

VCCIO

J32

VCCIO2

PR15B

RDQ15

RDQS15

RDQ15

C (LVDS)*

T (LVDS)*

C

PR15B

RDQ15

RDQS15

RDQ15

C (LVDS)*

T (LVDS)*

C

J31

PR15A

H33

GNDIO

H34

J30

PR14B

GNDIO2

PR14A

2

RDQ15

T

PR14A

2

RDQ15

T

PR13B

C (LVDS)*

T (LVDS)*

PR13B

C (LVDS)*

T (LVDS)*

J29

PR13A

VCCIO

J27

VCCIO2

PR11B

2

RUM0_SPLLC_IN_A/RDQ15

RUM0_SPLLT_IN_A/RDQ15

VREF2_2

C (LVDS)*

T (LVDS)*

C

PR11B

2

RUM0_SPLLC_IN_A/RDQ15 C (LVDS)*

RUM0_SPLLT_IN_A/RDQ15 T (LVDS)*

J28

PR11A

H31

GNDIO

H32

VCCIO

H30

B33

PR9B

2

PR9B

2

VREF2_2

C

GNDIO2

-

GNDIO2

-

PR9A

2

VREF1_2

T

PR9A

2

VREF1_2

T

VCCIO2

2

VCCIO2

2

XRES

1

XRES

1

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

12

URC_SQ_VCCRX0

URC_SQ_HDINP0

URC_SQ_VCCIB0

URC_SQ_HDINN0

URC_SQ_VCCTX0

URC_SQ_HDOUTP0

URC_SQ_VCCOB0

URC_SQ_HDOUTN0

URC_SQ_VCCTX1

URC_SQ_HDOUTN1

12

C33

B34

T

C

T

C

T

C32

B32

A33

C34

A32

C

B31

A31

4-243

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

12

1

Dual Function

Differential

D32

A30

B30

C31

D31

C30

E29

E30

D30

D29

C29

D27

C28

B29

A29

E28

A28

B28

A27

D26

A26

B27

C27

B26

C26

D28

E23

GNDIO

F23

F24

G23

D23

VCCIO

D22

-

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

12

URC_SQ_VCCOB1

URC_SQ_HDOUTP1

URC_SQ_VCCRX1

URC_SQ_HDINN1

URC_SQ_VCCIB1

URC_SQ_HDINP1

URC_SQ_VCCAUX33

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT100B

T

C

T

C

T

URC_SQ_VCCAUX33 12

URC_SQ_REFCLKN

URC_SQ_REFCLKP

URC_SQ_VCCP

URC_SQ_HDINP2

URC_SQ_VCCIB2

URC_SQ_HDINN2

URC_SQ_VCCRX2

URC_SQ_HDOUTP2

URC_SQ_VCCOB2

URC_SQ_HDOUTN2

URC_SQ_VCCTX2

URC_SQ_HDOUTN3

URC_SQ_VCCOB3

URC_SQ_HDOUTP3

URC_SQ_VCCTX3

URC_SQ_HDINN3

URC_SQ_VCCIB3

URC_SQ_HDINP3

URC_SQ_VCCRX3

PT82B

12

1

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

GNDIO1

-

GNDIO1

-

PT82A

1

PT100A

1

T

C

T

NC

-

PT99B

1

NC

-

PT99A

1

PT80B

1

C

T

PT98B

1

C

VCCIO1

1

VCCIO1

1

PT80A

1

PT98A

1

T

-

GNDIO1

-

VCCIO1

1

C21

D21

GNDIO

B21

A21

F22

E22

VCCIO

GNDIO

J22

PT79B

1

C

T

PT88B

1

C

T

PT79A

1

PT88A

1

GNDIO1

-

GNDIO1

-

PT77B

1

C

T

C

T

PT86B

1

C

T

C

T

PT77A

1

PT86A

1

PT76B

1

PT85B

1

PT76A

1

PT85A

1

VCCIO1

1

VCCIO1

1

GNDIO1

-

NC

-

PT84B

1

C

T

G22

-

NC

-

PT84A

1

-

GNDIO1

-

H22

K22

G21

PT72B

1

C

T

PT81B

1

C

T

PT72A

1

PT81A

1

PT71B

1

C

PT80B

1

C

4-244

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

1

-

Dual Function

Differential

Bank

1

-

Dual Function

Differential

VCCIO

J21

VCCIO1

PT71A

NC

VCCIO1

PT80A

PT79B

PT79A

PT78B

PT78A

PT77B

GNDIO1

PT77A

PT76B

VCCIO1

PT76A

PT75B

PT75A

GNDIO1

PT72B

PT72A

PT71B

PT71A

VCCIO1

PT70B

PT70A

PT69B

PT69A

GNDIO1

PT68B

PT68A

PT67B

PT67A

VCCIO1

PT66B

PT66A

PT65B

PT65A

PT64B

GNDIO0

PT64A

PT63B

PT63A

VCCIO0

PT60B

PT60A

PT59B

GNDIO0

PT59A

PT58B

VCCIO0

PT58A

PT57B

-

T

C

T

H21

K21

NC

-

D20

F20

PT69B

PT69A

PT68B

GNDIO1

PT68A

PT67B

VCCIO1

PT67A

PT66B

PT66A

GNDIO1

PT63B

PT63A

PT62B

PT62A

VCCIO1

NC

1

-

C

T

C

T

C20

GNDIO

E20

C

1

-

T

1

-

T

G20

VCCIO

J20

C

T

C

T

C

T

A20

B20

GNDIO

A19

1

-

C

T

C

T

1

-

C

T

C

T

B19

K20

H20

VCCIO

L19

C

T

C

T

L20

NC

-

E19

PT60B

PT60A

GNDIO1

PT59B

PT59A

NC

1

-

C

T

C18

GNDIO

F19

1

-

C

T

1

0

-

C

T

C

T

D18

L18

K19

NC

-

VCCIO

A18

VCCIO1

PT57B

PT57A

PT56B

PT56A

PT55B

GNDIO0

PT55A

PT54B

PT54A

VCCIO0

PT53B

PT53A

PT52B

-

1

0

-

VREF2_1

VREF1_1

C

T

VREF2_1

VREF1_1

C

T

B18

G18

E18

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

PCLKC1_0

PCLKT1_0

PCLKC0_0

C

T

F18

C

GNDIO

G19

H18

K18

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

0

-

PCLKT0_0

VREF2_0

VREF1_0

T

C

T

VCCIO

J18

C

T

C

T

L17

G17

-

C

J17

PT52A

PT51B

-

0

-

T

0

-

T

H17

-

C

K17

PT51A

PT50B

GNDIO0

PT50A

0

-

T

B17

C

GNDIO

A17

0

T

PT57A

0

T

4-245

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

0

-

Dual Function

Differential

Bank

0

-

Dual Function

Differential

D17

VCCIO

F17

PT49B

VCCIO0

PT49A

PT48B

PT48A

-

C

PT56B

-

C

T

C

T

PT56A

PT55B

PT55A

GNDIO0

VCCIO0

PT52B

PT52A

PT51B

PT51A

GNDIO0

PT50B

PT50A

PT49B

PT49A

VCCIO0

PT48B

PT48A

PT47B

PT47A

PT46B

GNDIO0

PT46A

PT45B

PT45A

PT44B

VCCIO0

PT44A

PT42B

PT42A

PT41B

GNDIO0

PT41A

PT40B

VCCIO0

PT40A

PT39B

-

0

-

T

C

T

B16

A16

-

0

-

E17

PT47B

PT47A

PT46B

PT46A

GNDIO0

PT45B

PT45A

PT44B

PT44A

VCCIO0

PT43B

PT43A

PT42B

PT42A

PT41B

GNDIO0

PT41A

NC

0

-

C

T

C

T

C

T

C

T

C17

K16

J15

GNDIO

G16

H15

A15

0

-

C

T

C

T

0

-

C

T

C

T

B15

VCCIO

L16

C

T

C

T

K15

F16

C

T

C

T

E16

E15

C

GNDIO

G15

J14

0

-

T

0

-

T

C

T

L15

NC

-

H14

VCCIO

K14

NC

-

C

VCCIO0

NC

0

-

T

C

T

F15

PT38B

PT38A

PT37B

GNDIO0

PT37A

PT36B

-

0

-

C

T

G14

C15

GNDIO

D14

G13

-

C

0

-

T

0

-

T

C

J13

PT36A

PT35B

VCCIO0

PT35A

PT34B

PT34A

PT33B

PT33A

GNDIO0

PT32B

PT32A

PT31B

PT31A

VCCIO0

NC

0

-

T

B14

C

VCCIO

A14

T

C

T

C

T

PT39A

PT38B

PT38A

PT37B

PT37A

GNDIO0

PT32B

PT32A

PT31B

PT31A

VCCIO0

PT30B

0

-

T

C

T

C

T

F13

H13

D13

C14

GNDIO

E13

0

-

C

T

C

T

0

C

T

C

T

D12

G12

E12

VCCIO

F12

C

4-246

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

Dual Function

Differential

Bank

0

Dual Function

Differential

D11

F11

E11

D7

NC

-

PT30A

PT29B

T

C

T

0

PT29A

0

ULC_SQ_VCCRX0

ULC_SQ_HDINP0

ULC_SQ_VCCIB0

ULC_SQ_HDINN0

ULC_SQ_VCCTX0

ULC_SQ_HDOUTP0

ULC_SQ_VCCOB0

ULC_SQ_HDOUTN0

ULC_SQ_VCCTX1

ULC_SQ_HDOUTN1

ULC_SQ_VCCOB1

ULC_SQ_HDOUTP1

ULC_SQ_VCCRX1

ULC_SQ_HDINN1

ULC_SQ_VCCIB1

ULC_SQ_HDINP1

ULC_SQ_VCCAUX33

ULC_SQ_REFCLKN

ULC_SQ_REFCLKP

ULC_SQ_VCCP

ULC_SQ_HDINP2

ULC_SQ_VCCIB2

ULC_SQ_HDINN2

ULC_SQ_VCCRX2

ULC_SQ_HDOUTP2

ULC_SQ_VCCOB2

ULC_SQ_HDOUTN2

ULC_SQ_VCCTX2

ULC_SQ_HDOUTN3

ULC_SQ_VCCOB3

ULC_SQ_HDOUTP3

ULC_SQ_VCCTX3

ULC_SQ_HDINN3

ULC_SQ_VCCIB3

ULC_SQ_HDINP3

ULC_SQ_VCCRX3

VCC

11

-

ULC_SQ_VCCRX0

ULC_SQ_HDINP0

ULC_SQ_VCCIB0

ULC_SQ_HDINN0

ULC_SQ_VCCTX0

ULC_SQ_HDOUTP0

ULC_SQ_VCCOB0

ULC_SQ_HDOUTN0

ULC_SQ_VCCTX1

ULC_SQ_HDOUTN1

ULC_SQ_VCCOB1

ULC_SQ_HDOUTP1

ULC_SQ_VCCRX1

ULC_SQ_HDINN1

ULC_SQ_VCCIB1

ULC_SQ_HDINP1

ULC_SQ_VCCAUX33

ULC_SQ_REFCLKN

ULC_SQ_REFCLKP

ULC_SQ_VCCP

ULC_SQ_HDINP2

ULC_SQ_VCCIB2

ULC_SQ_HDINN2

ULC_SQ_VCCRX2

ULC_SQ_HDOUTP2

ULC_SQ_VCCOB2

ULC_SQ_HDOUTN2

ULC_SQ_VCCTX2

ULC_SQ_HDOUTN3

ULC_SQ_VCCOB3

ULC_SQ_HDOUTP3

ULC_SQ_VCCTX3

ULC_SQ_HDINN3

ULC_SQ_VCCIB3

ULC_SQ_HDINP3

ULC_SQ_VCCRX3

VCC

11

-

C9

T

C

T

C

T

B9

C8

B8

A9

D9

A8

C

T

C

T

B7

A7

E7

A6

B6

C7

C

T

C

T

D8

C6

E6

E5

C

T

C

T

D5

D6

C5

T

C

T

C

T

D4

C4

B5

A5

D3

A4

C

T

C

T

B4

A3

C1

A2

B3

C3

C

T

C

T

B1

C2

B2

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB14

AB15

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

4-247

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AB20

AB21

N14

N15

N20

N21

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

R13

R14

R21

R22

T14

T21

U14

U21

V14

V21

W14

W21

Y13

Y14

Y21

Y22

C12

C16

E14

H12

H16

M14

M15

C19

C23

E21

H19

H23

M20

M21

G32

K28

K32

N27

N32

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCCIO0

VCCIO1

VCCIO2

0

1

2

VCCIO0

VCCIO1

VCCIO2

0

1

2

4-248

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Ball/Pad

Function

Ball/Pad

Function

Number

Bank

2

3

4

5

6

7

8

-

Dual Function

Differential

Bank

2

3

4

5

6

7

8

-

Dual Function

Differential

P23

R23

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCAUX

T27

T32

AA23

AB27

AB32

AE28

AE32

AH32

W27

W32

Y23

AC20

AC21

AG19

AG23

AK21

AM19

AM23

AC14

AC15

AG12

AG16

AK14

AM12

AM16

AA12

AB3

AB8

AE3

AE7

AH3

W3

W8

Y12

G3

K3

K7

N3

N8

P12

R12

T3

T8

AD28

AG32

AB12

AB13

AB22

AB23

-

4-249

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AC13

AC22

M13

VCCAUX

GND

-

VCCAUX

GND

-

M22

N12

N13

N22

N23

A1

A10

GND

A13

GND

A22

GND

A25

GND

A34

GND

AB16

AB17

AB18

AB19

AB26

AB31

AB4

GND

AB9

GND

AC16

AC17

AC18

AC19

AD27

AE27

AE31

AE4

GND

AE8

GND

AF12

AF16

AF19

AF23

AG31

AH31

AH4

GND

AJ14

AJ21

AK27

AK8

GND

AL10

AL16

AL19

AL2

GND

AL25

AL33

AP1

GND

AP10

AP13

GND

4-250

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AP22

AP25

AP34

D10

D16

D19

D2

GND

-

GND

-

D25

D33

E27

E8

F14

F21

G31

G4

J12

J16

J19

J23

K27

K31

K4

K8

M16

M17

M18

M19

N16

N17

N18

N19

N26

N31

N4

N9

R16

R17

R18

R19

T12

T13

T15

T16

T17

T18

T19

T20

T22

T23

T26

T31

4-251

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

T4

T9

GND

NC

-

GND

NC

-

U12

U13

U15

U16

U17

U18

U19

U20

U22

U23

V12

V13

V15

V16

V17

V18

V19

V20

V22

V23

W12

W13

W15

W16

W17

W18

W19

W20

W22

W23

W26

W31

W4

W9

Y16

Y17

Y18

Y19

A11

A12

A23

A24

AA11

AB11

AC26

AC30

AD11

AD12

AD13

NC

4-252

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AD14

AD15

AD19

AD21

AD22

AD23

AE10

AE11

AE12

AE13

AE19

AE21

AE22

AE23

AF11

AF21

AF22

AF24

AF8

NC

-

NC

-

AF9

AG10

AG11

AG24

AG25

AG26

AG3

AG7

AG8

AG9

AH10

AH11

AH13

AH24

AH25

AH26

AH27

AH5

AH6

AH7

AH8

AH9

AJ10

AJ11

AJ13

AJ24

AJ25

AJ26

AJ27

AJ3

AJ4

AJ5

4-253

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

AJ6

AJ7

NC

-

NC

-

AJ8

AJ9

AK10

AK11

AK12

AK24

AK25

AK26

AK4

AK9

AL11

AL12

AL34

AM10

AM11

AM13

AM25

AN10

AN11

AN12

AN13

AN24

AN25

AP11

AP12

AP24

B10

B11

B12

B13

B22

B23

B24

B25

C10

C11

C13

C22

C24

C25

D1

D15

D24

D34

E10

E24

E25

E26

E3

4-254

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

E31

E32

E33

E34

E4

NC

-

NC

-

E9

F10

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F5

F6

F7

F8

F9

G10

G11

G24

G25

G26

G27

G28

G29

G30

G33

G34

G7

G8

G9

H10

H11

H24

H25

H26

H27

H28

H29

H8

H9

J10

J11

J24

J25

J26

4-255

Pinout Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA

LFE2M70E/SE

LFE2M100E/SE

Ball

Number

Ball/Pad

Function

Ball/Pad

Function

Bank

Dual Function

Differential

Bank

Dual Function

Differential

J9

NC

-

NC

-

K10

K11

K12

K13

K23

K24

K25

K26

L11

L12

L13

L14

L21

L22

L23

L24

L25

L26

M11

M24

M25

M6

NC

M8

NC

N10

N11

P10

P25

P26

R9

NC

T11

U11

W11

Y10

Y11

R15

R20

Y15

Y20

NC

VCCPLL

* Supports true LVDS. Other differential signals must be emulated with external resistors.

** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.

*** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices

(ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70, and ECP2M100).

****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.

Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the

last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one

connection with a package ball or pin.

4-256

LatticeECP2/M Family Data Sheet

Ordering Information

August 2007

Data Sheet DS1006

LatticeECP2 Part Number Description

LFE2 – XX XE – X XXXXXX X

Device Family

Grade

C = Commercial

I = Industrial

ECP2 (LatticeECP2 FPGA)

Logic Capacity

6 = 6K LUTs

Package

T144 = 144-pin TQFP

Q208 = 208-pin PQFP

F256 = 256-ball fpBGA

F484 = 484-ball fpBGA

F672 = 672-ball fpBGA

F900 = 900-ball fpBGA

12 = 12K LUTs

20 = 20K LUTs

35 = 35K LUTs

50 = 50K LUTs

70 = 70K LUTs

Encryption

TN144 = 144-pin Lead-Free TQFP

QN208 = 208-pin Lead-Free PQFP

FN256 = 256-ball Lead-Free fpBGA

FN484 = 484-ball Lead-Free fpBGA

FN672 = 672-ball Lead-Free fpBGA

FN900 = 900-ball Lead-Free fpBGA

S = Security Series (Encryption Feature)

Blank = Standard Series (No Encryption)

Supply Voltage

E = 1.2V

Speed

5 = Slowest

6

7 = Fastest

Ordering Information

Note: LatticeECP2 devices are dual marked. For example, the commercial speed grade LFE2-50E-7F672C is also

marked with industrial grade -6I (LFE2-50E-6F672I). The commercial grade is one speed grade faster than the

associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings.

The markings appear as follows:

LFE2-50E

7F672C-6I

LFE2-50SE

7F672C-6I

Datecode

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5-1

DS1006 Order Info_01.5

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Standard Series Devices, Conventional Packaging

Commercial

Part Number

LFE2-6E-5T144C

LFE2-6E-6T144C

LFE2-6E-7T144C

LFE2-6E-5F256C

LFE2-6E-6F256C

LFE2-6E-7F256C

I/Os

90

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

256

Temp.

COM

LUTs (K)

6

90

1.2V

-6

TQFP

90

1.2V

-7

TQFP

190

1.2V

-5

fpBGA

1.2V

-6

1.2V

-7

Part Number

LFE2-12E-5T144C

LFE2-12E-6T144C

LFE2-12E-7T144C

LFE2-12E-5Q208C

LFE2-12E-6Q208C

LFE2-12E-7Q208C

LFE2-12E-5F256C

LFE2-12E-6F256C

LFE2-12E-7F256C

LFE2-12E-5F484C

LFE2-12E-6F484C

LFE2-12E-7F484C

I/Os

93

Voltage

1.2V

Grade

-5

Package

TQFP

PQFP

fpBGA

Pins

144

208

256

484

Temp.

COM

LUTs (K)

12

93

-6

12

93

-7

12

131

193

297

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

Part Number

LFE2-20E-5Q208C

LFE2-20E-6Q208C

LFE2-20E-7Q208C

LFE2-20E-5F256C

LFE2-20E-6F256C

LFE2-20E-7F256C

LFE2-20E-5F484C

LFE2-20E-6F484C

LFE2-20E-7F484C

LFE2-20E-5F672C

LFE2-20E-6F672C

LFE2-20E-7F672C

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

PQFP

fpBGA

Pins

208

256

484

672

Temp.

COM

LUTs (K)

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

5-2

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-35E-5F484C

LFE2-35E-6F484C

LFE2-35E-7F484C

LFE2-35E-5F672C

LFE2-35E-6F672C

LFE2-35E-7F672C

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

COM

LUTs (K)

35

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-50E-5F484C

LFE2-50E-6F484C

LFE2-50E-7F484C

LFE2-50E-5F672C

LFE2-50E-6F672C

LFE2-50E-7F672C

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

COM

LUTs (K)

50

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-70E-5F672C

LFE2-70E-6F672C

LFE2-70E-7F672C

LFE2-70E-5F900C

LFE2-70E-6F900C

LFE2-70E-7F900C

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

900

Temp.

COM

LUTs (K)

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Industrial

Part Number

LFE2-6E-5T144I

LFE2-6E-6T144I

LFE2-6E-5F256I

LFE2-6E-6F256I

I/Os

90

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

256

Temp.

IND

LUTs (K)

6

90

1.2V

-6

TQFP

IND

190

1.2V

-5

fpBGA

IND

1.2V

-6

IND

Part Number

LFE2-12E-5T144I

LFE2-12E-6T144I

LFE2-12E-5Q208I

LFE2-12E-6Q208I

LFE2-12E-5F256I

LFE2-12E-6F256I

LFE2-12E-5F484I

LFE2-12E-6F484I

I/Os

93

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

208

256

484

Temp.

IND

LUTs (K)

12

93

-6

TQFP

131

193

297

-5

PQFP

fpBGA

-6

-5

-6

-5

-6

5-3

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-20E-5Q208I

LFE2-20E-6Q208I

LFE2-20E-5F256I

LFE2-20E-6F256I

LFE2-20E-5F484I

LFE2-20E-6F484I

LFE2-20E-5F672I

LFE2-20E-6F672I

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

PQFP

Pins

208

256

484

672

Temp.

IND

LUTs (K)

20

-6

PQFP

-5

fpBGA

-6

-5

-6

-5

-6

Part Number

LFE2-35E-5F484I

LFE2-35E-6F484I

LFE2-35E-5F672I

LFE2-35E-6F672I

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

IND

LUTs (K)

35

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2-50E-5F484I

LFE2-50E-6F484I

LFE2-50E-5F672I

LFE2-50E-6F672I

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

IND

LUTs (K)

50

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2-70E-5F672I

LFE2-70E-6F672I

LFE2-70E-5F900I

LFE2-70E-6F900I

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

900

Temp.

IND

LUTs (K)

70

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

5-4

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 Standard Series Devices, Lead-Free Packaging

Commercial

Part Number

LFE2-6E-5TN144C

LFE2-6E-6TN144C

LFE2-6E-7TN144C

LFE2-6E-5FN256C

LFE2-6E-6FN256C

LFE2-6E-7FN256C

I/Os

90

Voltage

1.2V

Grade

-5

Package

Pins

144

256

Temp.

COM

LUTs (K)

Lead-Free TQFP

Lead-Free fpBGA

6

90

1.2V

-6

90

1.2V

-7

190

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

93

Voltage

1.2V

Grade

-5

Package

Pins

144

208

256

484

Temp.

COM

LUTs (K)

12

LFE2-12E-5TN144C

LFE2-12E-6TN144C

LFE2-12E-7TN144C

LFE2-12E-5QN208C

LFE2-12E-6QN208C

LFE2-12E-7QN208C

LFE2-12E-5FN256C

LFE2-12E-6FN256C

LFE2-12E-7FN256C

LFE2-12E-5FN484C

LFE2-12E-6FN484C

LFE2-12E-7FN484C

Lead-Free TQFP

Lead-Free PQFP

Lead-Free fpBGA

93

-6

12

93

-7

12

131

193

297

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

Part Number

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

Pins

208

256

484

672

Temp.

COM

LUTs (K)

20

LFE2-20E-5QN208C

LFE2-20E-6QN208C

LFE2-20E-7QN208C

LFE2-20E-5FN256C

LFE2-20E-6FN256C

LFE2-20E-7FN256C

LFE2-20E-5FN484C

LFE2-20E-6FN484C

LFE2-20E-7FN484C

LFE2-20E-5FN672C

LFE2-20E-6FN672C

LFE2-20E-7FN672C

Lead-Free PQFP

Lead-Free fpBGA

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

5-5

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

COM

LUTs (K)

LFE2-35E-5FN484C

LFE2-35E-6FN484C

LFE2-35E-7FN484C

LFE2-35E-5FN672C

LFE2-35E-6FN672C

LFE2-35E-7FN672C

Lead-Free fpBGA

35

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

COM

LUTs (K)

LFE2-50E-5FN484C

LFE2-50E-6FN484C

LFE2-50E-7FN484C

LFE2-50E-5FN672C

LFE2-50E-6FN672C

LFE2-50E-7FN672C

Lead-Free fpBGA

50

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

Pins

672

900

Temp.

COM

LUTs (K)

LFE2-70E-5FN672C

LFE2-70E-6FN672C

LFE2-70E-7FN672C

LFE2-70E-5FN900C

LFE2-70E-6FN900C

LFE2-70E-7FN900C

Lead-Free fpBGA

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Industrial

Part Number

LFE2-6E-5TN144I

LFE2-6E-6TN144I

LFE2-6E-5FN256I

LFE2-6E-6FN256I

I/Os

90

Voltage

1.2V

Grade

-5

Package

Pins

144

256

Temp.

IND

LUTs (K)

Lead-Free TQFP

Lead-Free fpBGA

6

90

1.2V

-6

IND

190

1.2V

-5

IND

1.2V

-6

IND

Part Number

I/Os

93

Voltage

1.2V

Grade

-5

Package

Pins

144

208

256

484

Temp.

IND

LUTs (K)

LFE2-12E-5TN144I

LFE2-12E-6TN144I

LFE2-12E-5QN208I

LFE2-12E-6QN208I

LFE2-12E-5FN256I

LFE2-12E-6FN256I

LFE2-12E-5FN484I

LFE2-12E-6FN484I

Lead-Free TQFP

Lead-Free PQFP

Lead-Free fpBGA

12

93

-6

131

193

297

-5

-6

-5

-6

-5

-6

5-6

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

Pins

208

256

484

672

Temp.

IND

LUTs (K)

LFE2-20E-5QN208I

LFE2-20E-6QN208I

LFE2-20E-5FN256I

LFE2-20E-6FN256I

LFE2-20E-5FN484I

LFE2-20E-6FN484I

LFE2-20E-5FN672I

LFE2-20E-6FN672I

Lead-Free PQFP

Lead-Free fpBGA

20

-6

-5

-6

-5

-6

-5

-6

Part Number

LFE2-35E-5FN484I

LFE2-35E-6FN484I

LFE2-35E-5FN672I

LFE2-35E-6FN672I

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

IND

LUTs (K)

Lead-Free fpBGA

35

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2-50E-5FN484I

LFE2-50E-6FN484I

LFE2-50E-5FN672I

LFE2-50E-6FN672I

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

IND

LUTs (K)

Lead-Free fpBGA

50

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2-70E-5FN672I

LFE2-70E-6FN672I

LFE2-70E-5FN900I

LFE2-70E-6FN900I

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

Pins

672

900

Temp.

IND

LUTs (K)

Lead-Free fpBGA

70

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

5-7

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 S-Series Devices, Conventional Packaging

Commercial

Part Number

LFE2-6SE-5T144C

LFE2-6SE-6T144C

LFE2-6SE-7T144C

LFE2-6SE-5F256C

LFE2-6SE-6F256C

LFE2-6SE-7F256C

I/Os

90

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

256

Temp.

Com

LUTs (K)

6

90

1.2V

-6

TQFP

90

1.2V

-7

TQFP

190

1.2V

-5

fpBGA

1.2V

-6

1.2V

-7

Part Number

LFE2-12SE-5T144C

LFE2-12SE-6T144C

LFE2-12SE-7T144C

LFE2-12SE-5Q208C

LFE2-12SE-6Q208C

LFE2-12SE-7Q208C

LFE2-12SE-5F256C

LFE2-12SE-6F256C

LFE2-12SE-7F256C

LFE2-12SE-5F484C

LFE2-12SE-6F484C

LFE2-12SE-7F484C

I/Os

93

Voltage

1.2V

Grade

-5

Package

TQFP

PQFP

fpBGA

Pins

144

208

256

484

Temp.

Com

LUTs (K)

12

93

-6

12

93

-7

12

131

193

297

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

Part Number

LFE2-20SE-5Q208C

LFE2-20SE-6Q208C

LFE2-20SE-7Q208C

LFE2-20SE-5F256C

LFE2-20SE-6F256C

LFE2-20SE-7F256C

LFE2-20SE-5F484C

LFE2-20SE-6F484C

LFE2-20SE-7F484C

LFE2-20SE-5F672C

LFE2-20SE-6F672C

LFE2-20SE-7F672C

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

PQFP

fpBGA

Pins

208

256

484

672

Temp.

Com

LUTs (K)

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

5-8

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-35SE-5F484C

LFE2-35SE-6F484C

LFE2-35SE-7F484C

LFE2-35SE-5F672C

LFE2-35SE-6F672C

LFE2-35SE-7F672C

I/Os

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

Com

LUTs (K)

331

450

35

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-50SE-5F484C

LFE2-50SE-6F484C

LFE2-50SE-7F484C

LFE2-50SE-5F672C

LFE2-50SE-6F672C

LFE2-50SE-7F672C

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

Com

LUTs (K)

50

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-70SE-5F672C

LFE2-70SE-6F672C

LFE2-70SE-7F672C

LFE2-70SE-5F900C

LFE2-70SE-6F900C

LFE2-70SE-7F900C

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

900

Temp.

Com

LUTs (K)

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Industrial

Part Number

LFE2-6SE-5T144I

LFE2-6SE-6T144I

LFE2-6SE-5F256I

LFE2-6SE-6F256I

I/Os

90

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

256

Temp.

Ind

LUTs (K)

6

90

1.2V

-6

TQFP

Ind

190

1.2V

-5

fpBGA

Ind

1.2V

-6

Ind

Part Number

LFE2-12SE-5T144I

LFE2-12SE-6T144I

LFE2-12SE-5Q208I

LFE2-12SE-6Q208I

LFE2-12SE-5F256I

LFE2-12SE-6F256I

LFE2-12SE-5F484I

LFE2-12SE-6F484I

I/Os

93

Voltage

1.2V

Grade

-5

Package

TQFP

Pins

144

208

256

484

Temp.

Ind

LUTs (K)

12

93

-6

TQFP

Ind

131

193

297

-5

PQFP

fpBGA

Ind

-6

Ind

-5

Ind

-6

Ind

-5

Ind

-6

Ind

5-9

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-20SE-5Q208I

LFE2-20SE-6Q208I

LFE2-20SE-5F256I

LFE2-20SE-6F256I

LFE2-20SE-5F484I

LFE2-20SE-6F484I

LFE2-20SE-5F672I

LFE2-20SE-6F672I

I/Os

Voltage

1.2V

Grade

-5

Package

PQFP

Pins

208

256

484

672

Temp.

Ind

LUTs (K)

131

193

331

402

20

-6

PQFP

Ind

-5

fpBGA

Ind

-6

Ind

-5

Ind

-6

Ind

-5

Ind

-6

Ind

Part Number

LFE2-35SE-5F484I

LFE2-35SE-6F484I

LFE2-35SE-5F672I

LFE2-35SE-6F672I

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

Ind

LUTs (K)

35

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2-50SE-5F484I

LFE2-50SE-6F484I

LFE2-50SE-5F672I

LFE2-50SE-6F672I

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

672

Temp.

Ind

LUTs (K)

50

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2-70SE-5F672I

LFE2-70SE-6F672I

LFE2-70SE-5F900I

LFE2-70SE-6F900I

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

900

Temp.

Ind

LUTs (K)

70

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

5-10

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2 S-Series Devices, Lead-Free Packaging

Commercial

Part Number

LFE2-6SE-5TN144C

LFE2-6SE-6TN144C

LFE2-6SE-7TN144C

LFE2-6SE-5FN256C

LFE2-6SE-6FN256C

LFE2-6SE-7FN256C

I/Os

90

Voltage

1.2V

Grade

-5

Package

Pins

144

256

Temp.

Com

LUTs (K)

Lead-Free TQFP

Lead-Free fpBGA

6

90

1.2V

-6

90

1.2V

-7

190

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

93

Voltage

1.2V

Grade

-5

Package

Pins

144

208

256

484

Temp.

Com

LUTs (K)

12

LFE2-12SE-5TN144C

LFE2-12SE-6TN144C

LFE2-12SE-7TN144C

LFE2-12SE-5QN208C

LFE2-12SE-6QN208C

LFE2-12SE-7QN208C

LFE2-12SE-5FN256C

LFE2-12SE-6FN256C

LFE2-12SE-7FN256C

LFE2-12SE-5FN484C

LFE2-12SE-6FN484C

LFE2-12SE-7FN484C

Lead-Free TQFP

Lead-Free PQFP

Lead-Free fpBGA

93

-6

12

93

-7

12

131

193

297

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

-5

12

-6

12

-7

12

Part Number

I/Os

131

193

331

402

Voltage

1.2V

Grade

-5

Package

Pins

208

256

484

672

Temp.

Com

LUTs (K)

20

LFE2-20SE-5QN208C

LFE2-20SE-6QN208C

LFE2-20SE-7QN208C

LFE2-20SE-5FN256C

LFE2-20SE-6FN256C

LFE2-20SE-7FN256C

LFE2-20SE-5FN484C

LFE2-20SE-6FN484C

LFE2-20SE-7FN484C

LFE2-20SE-5FN672C

LFE2-20SE-6FN672C

LFE2-20SE-7FN672C

Lead-Free PQFP

Lead-Free fpBGA

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

-5

20

-6

20

-7

20

5-11

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-35SE-5FN484C

LFE2-35SE-6FN484C

LFE2-35SE-7FN484C

LFE2-35SE-5FN672C

LFE2-35SE-6FN672C

LFE2-35SE-7FN672C

I/Os

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

Com

LUTs (K)

331

450

Lead-Free fpBGA

35

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-50SE-5FN484C

LFE2-50SE-6FN484C

LFE2-50SE-7FN484C

LFE2-50SE-5FN672C

LFE2-50SE-6FN672C

LFE2-50SE-7FN672C

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

Com

LUTs (K)

Lead-Free fpBGA

50

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2-70SE-5FN672C

LFE2-70SE-6FN672C

LFE2-70SE-7FN672C

LFE2-70SE-5FN900C

LFE2-70SE-6FN900C

LFE2-70SE-7FN900C

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

Pins

672

900

Temp.

Com

LUTs (K)

Lead-Free fpBGA

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Industrial

Part Number

LFE2-6SE-5TN144I

LFE2-6SE-6TN144I

LFE2-6SE-5FN256I

LFE2-6SE-6FN256I

I/Os

90

Voltage

1.2V

Grade

-5

Package

Pins

144

256

Temp.

Ind

LUTs (K)

Lead-Free TQFP

Lead-Free fpBGA

6

90

1.2V

-6

Ind

190

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2-12SE-5TN144I

LFE2-12SE-6TN144I

LFE2-12SE-5QN208I

LFE2-12SE-6QN208I

LFE2-12SE-5FN256I

LFE2-12SE-6FN256I

LFE2-12SE-5FN484I

LFE2-12SE-6FN484I

I/Os

93

Voltage

1.2V

Grade

-5

Package

Pins

144

208

256

484

Temp.

Ind

LUTs (K)

Lead-Free TQFP

Lead-Free PQFP

Lead-Free fpBGA

12

93

-6

Ind

131

193

297

-5

Ind

-6

Ind

-5

Ind

-6

Ind

-5

Ind

-6

Ind

5-12

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

LFE2-20SE-5QN208I

LFE2-20SE-6QN208I

LFE2-20SE-5FN256I

LFE2-20SE-6FN256I

LFE2-20SE-5FN484I

LFE2-20SE-6FN484I

LFE2-20SE-5FN672I

LFE2-20SE-6FN672I

I/Os

Voltage

1.2V

Grade

-5

Package

Pins

208

256

484

672

Temp.

Ind

LUTs (K)

131

193

331

402

Lead-Free PQFP

Lead-Free fpBGA

20

-6

Ind

-5

Ind

-6

Ind

-5

Ind

-6

Ind

-5

Ind

-6

Ind

Part Number

LFE2-35SE-5FN484I

LFE2-35SE-6FN484I

LFE2-35SE-5FN672I

LFE2-35SE-6FN672I

I/Os

331

450

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

35

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2-50SE-5FN484I

LFE2-50SE-6FN484I

LFE2-50SE-5FN672I

LFE2-50SE-6FN672I

I/Os

339

500

Voltage

1.2V

Grade

-5

Package

Pins

484

672

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

50

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2-70SE-5FN672I

LFE2-70SE-6FN672I

LFE2-70SE-5FN900I

LFE2-70SE-6FN900I

I/Os

500

583

Voltage

1.2V

Grade

-5

Package

Pins

672

900

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

70

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

5-13

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Part Number Description

LFE2M XXX XE – X XXXXXX X

Device Family

Grade

ECP2M (LatticeECP2 FPGA + SERDES)

C = Commercial

I = Industrial

Logic Capacity

20 = 20K LUTs

35 = 35K LUTs

50 = 50K LUTs

70 = 70K LUTs

100 = 100K LUTs

Package

F256 = 256-ball fpBGA

F484 = 484-ball fpBGA

F672 = 672-ball fpBGA

F900 = 900-ball fpBGA

F1152 = 1152-ball fpBGA

F1156 = 1156-ball fpBGA

Encryption

S = Security Series (Encryption Feature)

Blank = Standard Series (No Encryption)

FN256 = 256-ball Lead-free fpBGA

FN484 = 484-ball Lead-free fpBGA

FN672 = 672-ball Lead-free fpBGA

FN900 = 900-ball Lead-free fpBGA

FN1152 = 1152-ball Lead-free fpBGA

FN1156 = 1156-ball Lead-free fpBGA

Supply Voltage

E = 1.2V

Speed

5 = Slowest

6

7 = Fastest

Ordering Information

Note: LatticeECP2M devices are dual marked. For example, the commercial speed grade LFE2M50E-7F672C is

also marked with industrial grade -6I (LFE2M50E-6F672I). The commercial grade is one speed grade faster than

the associated dual mark industrial grade. The slowest commercial grade does not have industrial markings. The

markings appear as follows:

LFE2M35E

7F672C-6I

LFE2M35SE

7F672C-6I

Datecode

ContactYour Local Lattice Sales Representative for Product Availability.

5-14

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Standard Series Devices, Conventional Packaging

Commercial

Part Number

LFE2M20E-5F484C

LFE2M20E-6F484C

LFE2M20E-7F484C

LFE2M20E-5F256C

LFE2M20E-6F256C

LFE2M20E-7F256C

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

256

Temp.

COM

LUTs (K)

20

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

LFE2M35E-5F672C

LFE2M35E-6F672C

LFE2M35E-7F672C

LFE2M35E-5F484C

LFE2M35E-6F484C

LFE2M35E-7F484C

LFE2M35E-5F256C

LFE2M35E-6F256C

LFE2M35E-7F256C

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

484

256

Temp.

COM

LUTs (K)

35

-6

35

-7

35

-5

35

-6

35

-7

35

-5

35

-6

35

-7

35

Part Number

LFE2M50E-5F900C

LFE2M50E-6F900C

LFE2M50E-7F900C

LFE2M50E-5F672C

LFE2M50E-6F672C

LFE2M50E-7F672C

LFE2M50E-5F484C

LFE2M50E-6F484C

LFE2M50E-7F484C

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

900

672

484

Temp.

COM

LUTs (K)

50

-6

50

-7

50

-5

50

-6

50

-7

50

-5

50

-6

50

-7

50

Part Number

LFE2M70E-5F1152C

LFE2M70E-6F1152C

LFE2M70E-7F1152C

LFE2M70E-5F900C

LFE2M70E-6F900C

LFE2M70E-7F900C

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

COM

LUTs (K)

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

900

1.2V

-7

900

5-15

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

COM

LUTs (K)

100

LFE2M100E-5F1152C

LFE2M100E-6F1152C

LFE2M100E-7F1152C

LFE2M100E-5F900C

LFE2M100E-6F900C

LFE2M100E-7F900C

520

416

1.2V

-6

100

1.2V

-7

100

1.2V

-5

100

1.2V

-6

900

100

1.2V

-7

900

100

5-16

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Industrial

Part Number

LFE2M20E-5F484I

LFE2M20E-6F484I

LFE2M20E-5F256I

LFE2M20E-6F256I

I/Os

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

256

Temp.

IND

LUTs (K)

304

140

20

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2M35E-5F672I

LFE2M35E-6F672I

LFE2M35E-5F484I

LFE2M35E-6F484I

LFE2M35E-5F256I

LFE2M35E-6F256I

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

484

256

Temp.

IND

LUTs (K)

35

1.2V

-6

1.2V

-5

1.2V

-6

1.2V

-5

1.2V

-6

Grade

Part Number

LFE2M50E-5F900I

LFE2M50E-6F900I

LFE2M50E-5F672I

LFE2M50E-6F672I

LFE2M50E-5F484I

LFE2M50E-6F484I

I/Os

410

372

270

Voltage

1.2V

Package

fpBGA

Pins

900

672

484

Temp.

IND

LUTs (K)

-5

-6

-5

-6

-5

-6

50

1.2V

Part Number

LFE2M70E-5F1152I

LFE2M70E-6F1152I

LFE2M70E-5F900I

LFE2M70E-6F900I

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

IND

LUTs (K)

70

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

900

IND

Part Number

LFE2M100E-5F1152I

LFE2M100E-6F1152I

LFE2M100E-5F900I

LFE2M100E-6F900I

I/Os

520

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

IND

LUTs (K)

100

1.2V

-6

IND

100

1.2V

-5

IND

100

1.2V

-6

900

IND

100

5-17

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M Standard Series Devices, Lead-Free Packaging

Commercial

Part Number

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

Pins

484

256

Temp.

COM

LUTs (K)

LFE2M20E-5FN484C

LFE2M20E-6FN484C

LFE2M20E-7FN484C

LFE2M20E-5FN256C

LFE2M20E-6FN256C

LFE2M20E-7FN256C

Lead-Free fpBGA

20

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

Pins

672

484

256

Temp.

COM

LUTs (K)

35

LFE2M35E-5FN672C

LFE2M35E-6FN672C

LFE2M35E-7FN672C

LFE2M35E-5FN484C

LFE2M35E-6FN484C

LFE2M35E-7FN484C

LFE2M35E-5FN256C

LFE2M35E-6FN256C

LFE2M35E-7FN256C

Lead-Free fpBGA

-6

35

-7

35

-5

35

-6

35

-7

35

-5

35

-6

35

-7

35

Part Number

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

Pins

900

672

484

Temp.

COM

LUTs (K)

50

LFE2M50E-5FN900C

LFE2M50E-6FN900C

LFE2M50E-7FN900C

LFE2M50E-5FN672C

LFE2M50E-6FN672C

LFE2M50E-7FN672C

LFE2M50E-5FN484C

LFE2M50E-6FN484C

LFE2M50E-7FN484C

Lead-Free fpBGA

-6

50

-7

50

-5

50

-6

50

-7

50

-5

50

-6

50

-7

50

Part Number

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

COM

LUTs (K)

LFE2M70E-5FN1152C

LFE2M70E-6FN1152C

LFE2M70E-7FN1152C

LFE2M70E-5FN900C

LFE2M70E-6FN900C

LFE2M70E-7FN900C

Lead-Free fpBGA

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

900

1.2V

-7

900

5-18

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

COM

LUTs (K)

100

LFE2M100E-5FN1152C

LFE2M100E-6FN1152C

LFE2M100E-7FN1152C

LFE2M100E-5FN900C

LFE2M100E-6FN900C

LFE2M100E-7FN900C

520

416

Lead-Free fpBGA

1.2V

-6

100

1.2V

-7

100

1.2V

-5

100

1.2V

-6

900

100

1.2V

-7

900

100

Industrial

Part Number

LFE2M20E-5FN484I

LFE2M20E-6FN484I

LFE2M20E-5FN256I

LFE2M20E-6FN256I

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

Pins

484

256

Temp.

IND

LUTs (K)

Lead-Free fpBGA

20

1.2V

-6

IND

1.2V

-5

IND

1.2V

-6

IND

Part Number

LFE2M35E-5FN672I

LFE2M35E-6FN672I

LFE2M35E-5FN484I

LFE2M35E-6FN484I

LFE2M35E-5FN256I

LFE2M35E-6FN256I

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

Pins

672

484

256

Temp.

IND

LUTs (K)

Lead-Free fpBGA

35

1.2V

-6

1.2V

-5

1.2V

-6

1.2V

-5

1.2V

-6

Part Number

LFE2M50E-5FN900I

LFE2M50E-6FN900I

LFE2M50E-5FN672I

LFE2M50E-6FN672I

LFE2M50E-5FN484I

LFE2M50E-6FN484I

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

Pins

900

672

484

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

50

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

Ind

LUTs (K)

LFE2M70E-5FN1152I

LFE2M70E-6FN1152I

LFE2M70E-5FN900I

LFE2M70E-6FN900I

Lead-Free fpBGA

70

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

900

Ind

5-19

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

Ind

LUTs (K)

100

LFE2M100E-5FN1152I

LFE2M100E-6FN1152I

LFE2M100E-5FN900I

LFE2M100E-6FN900I

520

416

Lead-Free fpBGA

1.2V

-6

Ind

100

1.2V

-5

Ind

100

1.2V

-6

900

Ind

100

LatticeECP2M S-Series Devices, Conventional Packaging

Commercial

Part Number

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

Temp.

Com

LUTs (K)

LFE2M20SE-5F484C

LFE2M20SE-6F484C

LFE2M20SE-7F484C

LFE2M20SE-5F256C

LFE2M20SE-6F256C

LFE2M20SE-7F256C

484

256

20

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

484

256

Temp.

Com

LUTs (K)

35

LFE2M35SE-5F672C

LFE2M35SE-6F672C

LFE2M35SE-7F672C

LFE2M35SE-5F484C

LFE2M35SE-6F484C

LFE2M35SE-7F484C

LFE2M35SE-5F256C

LFE2M35SE-6F256C

LFE2M35SE-7F256C

-6

35

-7

35

-5

35

-6

35

-7

35

-5

35

-6

35

-7

35

Part Number

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

900

672

484

Temp.

Com

LUTs (K)

50

LFE2M50SE-5F900C

LFE2M50SE-6F900C

LFE2M50SE-7F900C

LFE2M50SE-5F672C

LFE2M50SE-6F672C

LFE2M50SE-7F672C

LFE2M50SE-5F484C

LFE2M50SE-6F484C

LFE2M50SE-7F484C

-6

50

-7

50

-5

50

-6

50

-7

50

-5

50

-6

50

-7

50

5-20

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

Com

LUTs (K)

LFE2M70SE-5F1152C

LFE2M70SE-6F1152C

LFE2M70SE-7F1152C

LFE2M70SE-5F900C

LFE2M70SE-6F900C

LFE2M70SE-7F900C

436

416

70

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

900

1.2V

-7

900

Part Number

I/Os

520

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

Com

LUTs (K)

100

LFE2M100SE-5F1152C

LFE2M100SE-6F1152C

LFE2M100SE-7F1152C

LFE2M100SE-5F900C

LFE2M100SE-6F900C

LFE2M100SE-7F900C

1.2V

-6

100

1.2V

-7

100

1.2V

-5

100

1.2V

-6

900

100

1.2V

-7

900

100

5-21

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Industrial

Part Number

LFE2M20SE-5F484I

LFE2M20SE-6F484I

LFE2M20SE-5F256I

LFE2M20SE-6F256I

I/Os

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

484

256

Temp.

Ind

LUTs (K)

304

140

20

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2M35SE-5F672I

LFE2M35SE-6F672I

LFE2M35SE-5F484I

LFE2M35SE-6F484I

LFE2M35SE-5F256I

LFE2M35SE-6F256I

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

672

484

256

Temp.

Ind

LUTs (K)

35

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2M50SE-5F900I

LFE2M50SE-6F900I

LFE2M50SE-5F672I

LFE2M50SE-6F672I

LFE2M50SE-5F484I

LFE2M50SE-6F484I

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

900

672

484

Temp.

Ind

LUTs (K)

50

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2M70SE-5F1152I

LFE2M70SE-6F1152I

LFE2M70SE-5F900I

LFE2M70SE-6F900I

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

Ind

LUTs (K)

70

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

900

Ind

Part Number

I/Os

520

416

Voltage

1.2V

Grade

-5

Package

fpBGA

Pins

1152

900

Temp.

Ind

LUTs (K)

100

LFE2M100SE-5F1152I

LFE2M100SE-6F1152I

LFE2M100SE-5F900I

LFE2M100SE-6F900I

1.2V

-6

Ind

100

1.2V

-5

Ind

100

1.2V

-6

900

Ind

100

5-22

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

LatticeECP2M S-Series Devices, Lead-Free Packaging

Commercial

Part Number

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

Pins

484

256

Temp.

Com

LUTs (K)

LFE2M20SE-5FN484C

LFE2M20SE-6FN484C

LFE2M20SE-7FN484C

LFE2M20SE-5FN256C

LFE2M20SE-6FN256C

LFE2M20SE-7FN256C

Lead-Free fpBGA

20

1.2V

-6

1.2V

-7

1.2V

-5

1.2V

-6

1.2V

-7

Part Number

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

Pins

672

484

256

Temp.

Com

LUTs (K)

35

LFE2M35SE-5FN672C

LFE2M35SE-6FN672C

LFE2M35SE-7FN672C

LFE2M35SE-5FN484C

LFE2M35SE-6FN484C

LFE2M35SE-7FN484C

LFE2M35SE-5FN256C

LFE2M35SE-6FN256C

LFE2M35SE-7FN256C

Lead-Free fpBGA

-6

35

-7

35

-5

35

-6

35

-7

35

-5

35

-6

35

-7

35

Part Number

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

Pins

900

672

484

Temp.

Com

LUTs (K)

50

LFE2M50SE-5FN900C

LFE2M50SE-6FN900C

LFE2M50SE-7FN900C

LFE2M50SE-5FN672C

LFE2M50SE-6FN672C

LFE2M50SE-7FN672C

LFE2M50SE-5FN484C

LFE2M50SE-6FN484C

LFE2M50SE-7FN484C

Lead-Free fpBGA

-6

50

-7

50

-5

50

-6

50

-7

50

-5

50

-6

50

-7

50

Part Number

I/Os

436

416

Voltage

1.2V

416

Grade

-5

Package

Pins

1152

900

Temp.

Com

LUTs (K)

LFE2M70SE-5FN1152C

LFE2M70SE-6FN1152C

LFE2M70SE-7FN1152C

LFE2M70SE-5FN900C

LFE2M70SE-6FN900C

LFE2M70SE-7FN900C

Lead-Free fpBGA

70

-6

-7

-5

-6

900

416

-7

900

5-23

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Part Number

I/Os

520

416

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

Com

LUTs (K)

100

LFE2M100SE-5FN1152C

LFE2M100SE-6FN1152C

LFE2M100SE-7FN1152C

LFE2M100SE-5FN900C

LFE2M100SE-6FN900C

LFE2M100SE-7FN900C

Lead-Free fpBGA

1.2V

-6

100

1.2V

-7

100

1.2V

-5

100

1.2V

-6

900

100

1.2V

-7

900

100

5-24

Ordering Information

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Industrial

Part Number

LFE2M20SE-5FN484I

LFE2M20SE-6FN484I

LFE2M20SE-5FN256I

LFE2M20SE-6FN256I

I/Os

304

140

Voltage

1.2V

Grade

-5

Package

Pins

484

256

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

20

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2M35SE-5FN672I

LFE2M35SE-6FN672I

LFE2M35SE-5FN484I

LFE2M35SE-6FN484I

LFE2M35SE-5FN256I

LFE2M35SE-6FN256I

I/Os

410

303

140

Voltage

1.2V

Grade

-5

Package

Pins

672

484

256

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

35

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

LFE2M50SE-5FN900I

LFE2M50SE-6FN900I

LFE2M50SE-5FN672I

LFE2M50SE-6FN672I

LFE2M50SE-5FN484I

LFE2M50SE-6FN484I

I/Os

410

372

270

Voltage

1.2V

Grade

-5

Package

Pins

900

672

484

Temp.

Ind

LUTs (K)

Lead-Free fpBGA

50

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

Ind

Part Number

I/Os

436

416

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

Ind

LUTs (K)

LFE2M70SE-5FN1152I

LFE2M70SE-6FN1152I

LFE2M70SE-5FN900I

LFE2M70SE-6FN900I

Lead-Free fpBGA

70

1.2V

-6

Ind

1.2V

-5

Ind

1.2V

-6

900

Ind

Part Number

I/Os

520

416

Voltage

1.2V

Grade

-5

Package

Pins

1152

900

Temp.

Ind

LUTs (K)

100

LFE2M100SE-5FN1152I

LFE2M100SE-6FN1152I

LFE2M100SE-5FN900I

LFE2M100SE-6FN900I

Lead-Free fpBGA

1.2V

-6

Ind

100

1.2V

-5

Ind

100

1.2V

-6

900

Ind

100

5-25

LatticeECP2/M Family Data Sheet

Supplemental Information

Data Sheet DS1006

September 2006

For Further Information

A variety of technical notes for the LatticeECP2 family are available on the Lattice web site at www.latticesemi.com.

• LatticeECP2M SERDES/PCS Usage Guide (TN1124)

• LatticeECP2/M sysIO Usage Guide (TN1102)

• LatticeECP2/M sysCLOCK PLL Design and Usage Guide (TN1103)

• LatticeECP2/M Memory Usage Guide (TN1104)

• LatticeECP2/M High-Speed I/O Interface (TN1105)

• Power Estimation and Management for LatticeECP2/M Devices (TN1106)

• LatticeECP2/M sysDSP Usage Guide (TN1107)

• LatticeECP2/M sysCONFIG Usage Guide (TN1108)

• LatticeECP2/M Conﬁguration Encryption Usage Guide (TN1109)

• LatticeECP2/M Soft Error Detection (SED) Usage Guide (TN1113)

For further information about interface standards refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• PCI: www.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

6-1

DS1006 Further Info_01.0

LatticeECP2/M Family Data Sheet

Revision History

August 2008

Data Sheet DS1006

Date

Version

01.0

Section

—

Change Summary

February 2006

August 2006

Initial release.

01.1

Introduction

Updated Table 1-1 “LatticeECP2 Family Selection Guide”

Architecture

Updated ﬁgure 2-2 “PFU Diagram”

Updated ﬁgure 2-13 “Secondary Clock Regions ECP2-50”

Updated ﬁgure 2-25 “PIC Diagram”

Updated ﬁgure 2-26 “Input Register Block for Left, Right and Bottom

Edges”

Updated ﬁgure 2-28 “Output Register Block for Left, Right and Bottom

Edges”

Updated ﬁgure 2-30 “DQS Input Routing for Left and Right Edges”

Updated ﬁgure 2-32 “Edge Clock, DLL Calibration and DQS Local Bus

Distribution”

Table 2-15 Selectable Master clock (CCLK) frequencies Removed fre-

quencies 15,20,21,22,23,30,34,41,45,51,55,60

Replaced “CLKINDEL” with “CLKO”

Updated SED section

Qualiﬁed device migration capability when using DQS banks for DDR

interfaces

DC and Switching

Characteristics

Added VCCPLL to the Recommended Operating Conditions Table

Remove Note 5 from “Hot Speciﬁcations” section

Added note 7 & 8 to “Initialization Supply current Table

Change Note 6 - “...down to 95MHz” to “...down to 95MHz for DDR and

133MHz for DDR2”

New “Typical Building Block Function Performance” numbers

New External Switching Characteristics numbers

New Internal Switching Characteristics numbers

New Family Timing Adders numbers

Updated Timings for GPLLs, SPLLs and DLLs

Added sysConﬁg waveforms.

Remove HSTL15D_II from sysIO Recommended Operating Condition

Table

Updated Supply and initialization currents for ECP2-50

Added VCCPLL to the Signal Descriptions Table

Pinout Information

Updated Logic signal Connections tables to include 484-fpBGA for the

ECP2-50.

Added Logic signal Connections tables for ECP2-12 devices.

Updated Pin Information Summary table to include ECP2-12.

Updated Power Supply and NC Connections table to include ECP2-12.

Added Note 2 to DDR Strobe (DQS) Pin Table

Added Information on: PCI, DDR & SPI4.2 Capabilities of the device-

Package combination

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

7-1

DS1006 Revision History

Revision History

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

August 2006

(cont.)

01.1

(cont.)

Pinout Information

(cont.)

Added Information on: Available Device Resources per Packaged

Device table

Ordering Information Updated ordering part number table to include ECP2-12.

Updated topside mark drawing

September 2006

02.0

02.1

Multiple

Added information regarding LatticeECP2M support throughout.

Added Receiver Total Jitter Tolerance Speciﬁcation table.

DC and Switching

Characteristics

Removed power-up requirements for proper conﬁguration footnote in

Recommended Operating Conditions table.

December 2006

02.2

Introduction

Architecture

LatticeECP2M Selection Guide table has been updated.

Figure 2-16. Per Region Secondary Clock Selection has been updated.

Figure 2-39. Simpliﬁed Channel Block Diagram for SERDES and PCS

has been updated.

DC and Switching

Footnotes have been added to Recommended Operating Conditions

DC Electrical Characteristics table has been updated.

Supply Current (Standby) tables have been updated.

Initialization Supply Current table have been updated.

Updated timing numbers to include LFE2-12E (rev A 0.08)

Pinout Information

Updated to include the entire ECP2 device information as well as 256-

fpBGA and 484-fpBGA pin information for the ECP2M35E.

Ordering Information Updated to include the entire ECP2 and ECP2M device ordering infor-

mation.

February 2007

March 2007

02.3

02.4

Architecture

Updated EBR Asynchronous Reset section.

DC and Switching

Characteristics

Power-sequencing footnotes have been added to the Recommended

Operating Conditions. DDR2 performance has been updated to

266MHz.

March 2007

02.5

Introduction

Added “Security Series” to the LatticeECP2 and LatticeECP2M

families.

Architecture

Enhanced Conﬁguration Option section updated.

DC and Switching

Recommended Operating Conditions table - footnote 4 updated.

Ordering Information “Security Series” ordering part numbers added.

April 2007

July 2007

02.6

02.7

Introduction

LatticeECP2M family table has been updated for user I/O counts.

Ordering Information LatticeECP2M family ordering part number section has been updated to

add 1152-fpBGA package for the ECP2M70 and ECP2M100.

Architecture

Updated text in Ripple Mode section.

DC and Switching

ECP2/M Supply Current information has been updated.

Typical Building Block Function Performance, External Switching Char-

acteristics, Internal Switching Characteristics, Family Timing Adders,

sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Timing and

sysCONFIG Port Timing Speciﬁcations have been updated (timing rev.

A 0.10).

SERDES timing information has been updated.

PCI Express timing information has been updated.

Pinout Information

Introduction

Added LatticeECP2M20 pinout information.

August 2007

02.8

1156-fpBGA package option has been removed from the LatticeECP2M

family.

Architecture

Table 2-16. Selectable Master Clock (CCLK) Frequencies During Con-

ﬁguration table has been updated.

DC and Switching

Supply Current (Standby) table has been updated.

DSP Function timing has been updated.

7-2

Revision History

LatticeECP2/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

August 2007

(cont.)

02.8

(cont.)

DC and Switching

(cont.)

sysCLOCK GPLL timing has been updated.

Pinout Information

Added ECP2M50 (484/672/900-fpBGA), ECP2M70 (900-fpBGA) and

ECP2M100 (900-fpBGA) pinout information.

Ordering Information 1156-fpBGA package option has been removed from the LatticeECP2M

family.

September 2007

February 2008

02.9

03.0

Pinout Information

Architecture

Added Thermal Management text section.

Added LVCMOS33D description.

DC and Switching

LatticeECP2M Supply Current has been updated.

Typical Building Block Function Performance, External Switching

Characteristics, Internal Switching Characteristics, Family Timing

Adders, sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Tim-

ing and sysCONFIG Port Timing Speciﬁcations have been updated (tim-

ing rev. A 0.11).

Figure 3-9. Read/Write Mode (Normal) and Figure 3-10. Read/Write

Mode with Input and Output Registers have been updated.

Table 3-8. Channel output Jitter (Max) has been updated.

Signal description has been updated.

Pinout Information

Added 1152-fpBGA pinouts for the ECP2M70 and ECP2M100.

April 2008

June 2008

03.1

03.2

Pinout Information

Introduction

Available DDR Interfaces per I/O Bank for the LFE2M35 (484/672-

fpBGA) have been updated.

Family Selection Guide table - Updated number of EBR SRAM Blocks

for the ECP2-70 device.

Architecture

Removed Read-Before-Write sysMEM EBR mode.

Clariﬁcation of the operation of the secondary clock regions.

Removed Read-Before-Write sysMEM EBR mode.

DC and Switching

Characteristics

August 2008

03.3

Architecture

Clariﬁcation of the operation of the secondary clock regions.

Added information for [LOC]DQ[num] to Signal Descriptions table.

Pinout Information

7-3


型号：	LFE250E-7F256C
厂家：	LATTICE SEMICONDUCTOR
描述：	LatticeECP2/M Family Data Sheet LatticeECP2 / M系列数据表
文件：	总386页 (文件大小：2475K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LFE250E-7F256C [LATTICE]

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