LFX1200EC-04FE680C_技术文档

ispXPGA^®Device Datasheet

June 2010

Select Devices Discontinued!

Product Change Notifications (PCNs) have been issued to discontinue select devices in

this data sheet.

The original datasheet pages have not been modified and do not reflect those changes.

Please refer to the table below for reference PCN and current product status.

Product Line

LFX125B

Ordering Part Number

LFX125B-03F256C

LFX125B-03FN256C

LFX125B-04F256C

LFX125B-04FN256C

LFX125B-05F256C

LFX125B-05FN256C

LFX125B-03F516C

LFX125B-04F516C

LFX125B-05F516C

LFX125C-03F256C

LFX125C-03FN256C

LFX125C-04F256C

LFX125C-04FN256C

LFX125C-03F516C

LFX125C-04F516C

LFX200B-03F256C

LFX200B-03FN256C

LFX200B-04F256C

LFX200B-04FN256C

LFX200B-05F256C

LFX200B-05FN256C

LFX200B-03F516C

LFX200B-04F516C

LFX200B-05F516C

LFX200C-03F256C

LFX200C-03FN256C

LFX200C-04F256C

LFX200C-04FN256C

LFX200C-03F516C

LFX200C-04F516C

Product Status

Discontinued

Reference PCN

PCN#09-10

LFX125C

LFX200B

LFX200C

Discontinued

PCN#09-10

Active / Orderable

Discontinued

PCN#09-10

5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347

Internet: http://www.latticesemi.com

Product Line

LFX500B

Ordering Part Number

LFX500B-03F516C

LFX500B-04F516C

LFX500B-05F516C

LFX500B-03F900C

LFX500B-03FN900C

LFX500B-04F900C

LFX500B-04FN900C

LFX500B-05F900C

LFX500B-05FN900C

LFX500C-03F516C

LFX500C-04F516C

LFX500C-03F900C

LFX500C-03FN900C

LFX500C-04F900C

LFX500C-04FN900C

LFX1200B-03FE680C

LFX1200B-04FE680C

LFX1200B-05FE680C

LFX1200B-03F900C

LFX1200B-04F900C

LFX1200B-05F900C

LFX1200C-03FE680C

LFX1200C-04FE680C

LFX1200C-03F900C

LFX1200C-04F900C

LFX125EB-03F256C

LFX125EB-03FN256C

LFX125EB-04F256C

LFX125EB-04FN256C

LFX125EB-05F256C

LFX125EB-05FN256C

LFX125EB-03F256I

LFX125EB-03FN256I

LFX125EB-04F256I

LFX125EB-04FN256I

LFX125EB-03F516C

LFX125EB-04F516C

LFX125EB-05F516C

LFX125EB-03F516I

LFX125EB-04F516I

LFX125EC-03F256C

LFX125EC-03FN256C

LFX125EC-04F256C

LFX125EC-04FN256C

LFX125EC-03F256I

LFX125EC-03FN256I

Product Status

Discontinued

Reference PCN

PCN#09-10

LFX500C

Discontinued

PCN#09-10

LFX1200B

LFX1200C

Discontinued

PCN#03A-10

Active / Orderable

LFX125EB

Discontinued

PCN#09-10

LFX125EC

5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347

Internet: http://www.latticesemi.com

Product Line

Ordering Part Number

LFX125EC-03F516C

LFX125EC-04F516C

LFX125EC-03F516I

LFX200EB-03F256C

LFX200EB-03FN256C

LFX200EB-04F256C

LFX200EB-04FN256C

LFX200EB-05F256C

LFX200EB-05FN256C

LFX200EB-03F256I

LFX200EB-03FN256I

LFX200EB-04F256I

LFX200EB-04FN256I

LFX200EB-03F516C

LFX200EB-04F516C

LFX200EB-05F516C

LFX200EB-03F516I

LFX200EB-04F516I

LFX200EC-03F256C

LFX200EC-03FN256C

LFX200EC-04F256C

LFX200EC-04FN256C

LFX200EC-03F256I

LFX200EC-03FN256I

LFX200EC-03F516C

LFX200EC-04F516C

LFX200EC-03F516I

LFX500EB-03F516C

LFX500EB-04F516C

LFX500EB-05F516C

LFX500EB-03F516I

LFX500EB-04F516I

LFX500EB-03F900C

LFX500EB-03FN900C

LFX500EB-04F900C

LFX500EB-04FN900C

LFX500EB-05F900C

LFX500EB-05FN900C

LFX500EB-03F900I

LFX500EB-03FN900I

LFX500EB-04F900I

LFX500EB-04FN900I

LFX500EC-03F516C

LFX500EC-04F516C

LFX500EC-03F516I

Product Status

Discontinued

Reference PCN

LFX125EC

(Cont’d)

PCN#09-10

Active / Orderable

LFX200EB

Discontinued

PCN#09-10

LFX200EC

LFX500EB

Discontinued

PCN#09-10

LFX500EC

Discontinued

PCN#09-10

5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347

Internet: http://www.latticesemi.com

Product Line

Ordering Part Number

LFX500EC-03F900C

LFX500EC-03FN900C

LFX500EC-04F900C

LFX500EC-04FN900C

LFX500EC-03F900I

Product Status

Discontinued

Reference PCN

LFX500EC

(Cont’d)

PCN#09-10

LFX500EC-03FN900I

LFX1200EB-03FE680C

LFX1200EB-04FE680C

LFX1200EB-05FE680C

LFX1200EB-03FE680I

LFX1200EB-04FE680I

LFX1200EB-03F900C

LFX1200EB-04F900C

LFX1200EB-05F900C

LFX1200EB-03F900I

LFX1200EB-04F900I

LFX1200EC-03FE680C

LFX1200EC-04FE680C

LFX1200EC-03FE680I

LFX1200EC-03F900C

LFX1200EC-04F900C

LFX1200EC-03F900I

LFX1200EB

LFX1200EC

Discontinued

PCN#03A-10

5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347

Internet: http://www.latticesemi.com

®

ispXPGA Family

February 2010

Data Sheet DS1026

• Microprocessor configuration interface

 Non-volatile, Infinitely Reconfigurable

• Instant-on - Powers up in microseconds via

on-chip E²CMOS^®based memory

• Program E²CMOS while operating from SRAM

 Eight sysCLOCK™ Phase Locked Loops

(PLLs) for Clock Management

• True PLL technology

• No external configuration memory

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

• 10MHz to 320MHz operation

• Clock multiplication and division

• Phase adjustment

 High Logic Density for System-level

Integration

• 139K to 1.25M functional gates

• 160 to 496 I/O

• Shift clocks in 250ps steps

 sysIO™ for High System Performance

• High speed memory support through SSTL and

HSTL

• 1.8V, 2.5V, and 3.3V V operation

CC

• Up to 414Kb sysMEM™ embedded memory

 High Performance Programmable Function

Unit (PFU)

• Advanced buses supported through PCI, GTL+,

LVDS, BLVDS, and LVPECL

• Standard logic supported through LVTTL,

LVCMOS 3.3, 2.5 and 1.8

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL

interfaces

• Programmable drive strength for series termination

• Programmable bus maintenance

• Four LUT-4 per PFU supports wide and narrow

functions

• Dual flip-flops per LUT-4 for extensive pipelining

• Dedicated logic for adders, multipliers, multiplex-

ers, and counters

 Flexible Memory Resources

• Multiple sysMEM Embedded RAM Blocks

– Single port, Dual port, and FIFO operation

• 64-bit distributed memory in each PFU

– Single port, Double port, FIFO, and Shift

Register operation

 Two Options Available

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

 sysHSI™ Capability for Ultra Fast Serial

Communications

 Flexible Programming, Reconfiguration,

and Testing

• Up to 800Mbps performance

• Up to 20 channels per device

• Supports IEEE 1532 and 1149.1

• Built in Clock Data Recovery (CDR) and

Serialization and De-serialization (SERDES)

Table 1. ispXPGA Family Selection Guide

ispXPGA 125/E

ispXPGA 200/E

ispXPGA 500/E

476K

1764

ispXPGA 1200/E³

Functional Gates

PFUs

139K

484

210K

676

1.25M

3844

15376

30.7K

414K

246K

90

LUT-4s

1936

3.8K

92K

2704

5.4K

111K

43K

7056

Logic FFs

14.1K

184K

112K

40

sysMEM Memory

Distributed Memory

EBR

30K

20

24

sysHSI Channels¹

4

8

12

20

User I/O

160/176

160/208

336

496

Packaging

256 fpBGA

516 fpBGA²

256 fpBGA

516 fpBGA²

900 fpBGA

680 fpSBGA

900 fpBGA

1. “E-Series” does not support sysHSI.

2. FH516 package was converted to F516 via PCN #09A-08.

3. Discontinued via PCN #03A-10.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

1

DS1026_15.0

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Family Overview

The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that

are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-

programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-

tures required for today’s system-level design.

The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial

communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the sys-

HSI Block.

Electrically Erasable CMOS (E²CMOS) memory cells provide the ispXPGA family with non-volatile capability.

These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-

tions. This capability also means that expensive external configuration memories are not required and that designs

can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if

desired. Both the SRAM and E²CMOS cells can be programmed and verified through the IEEE 1532 industry stan-

dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.

The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M func-

tional gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies,

providing easy integration into the overall system.

System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO

advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-

ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization

(SERDES).

The ispLEVER™ design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-

thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these

common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor

planning and the management of other constraints within the device. The tool also provides outputs to common

timing analysis tools for timing analysis.

To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the

ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using

pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,

and memory controllers.

Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-

ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.

Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly

used by logic designers.

Table 2. ispXPGA Speed Performance for Typical Building Blocks

Function

8:1 Asynch MUX

Performance

150 MHz

125 MHz

225 MHz

290 MHz

360 MHz

1:32 Asynch Demultiplexer

8 x 8 2-LL Pipelined Multiplier

32-bit Up/Down Counter

32-bit Shift Register

2

Lattice Semiconductor

ispXPGA Family Data Sheet

Architecture Overview

The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units

(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-

uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO

blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the

sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-

ily implement their designs, since any logic function can be placed in any section of the device.

The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are

optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.

The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered

quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic

elements for fast access to combinatorial functions.

The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-

age types. They are designed to facilitate both single and dual-port memory for high-speed applications.

These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing

array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional

routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.

The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can

be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices

without the need for external transceivers.

The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to

800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery

(CDR) logic.

The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased

performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for

each global clock tree in the device.

3

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 1. ispXPGA Block Diagram

PFU

PIC

sysMEM Block

sysCLOCK PLL

sysHSI Block

sysIO Buffer

Programmable Function Unit

The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are

arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of

four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-

erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of

the function capabilities of the PFU.

There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-

trol logic from which six control signals are derived for the PFU.

Table 3. Function Capability of ispXPGA PFU

Function

Look-up table

Capability

LUT-4, LUT-5, LUT-6

Wide logic functions

Multiplexing

Up to 20 input logic functions

2:1, 4:1, 8:1

Arithmetic logic

Single-port RAM

Double-port RAM

Shift register

Dedicated carry chain and booth multiplication logic

16X1, 16X2, 16X4, 32X1, 32X2, 64X1

16X1, 16X2, 32X1

8-bit shift registers (up to 32-bit shift capability)

4

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 2. ispXPGA PFU

COUT(r,c)

OE

PFUCLK0

OE

Control

Logic

PFUCLK1

CEB0

CEB1

SR

COUT

4A

WLGW0

WLGW1

WLGX0

WLGX1

WLGY0

WLGY1

WLGZ0

WLGZ1

D

S

R

WIN0

WIN1

W0

W1

X0

X1

Y0

Y1

Z0

Z1

Q

COUT

LUT-4 SUM

S3

LUT-4

WIN2

WIN3

CCG

CLK/LE

CE

IN

WIN2

WIN3

D

S

R

Q

CLK/LE

CE

SEL0

D

XIN0

XIN1

XIN2

XIN3

4B

S2

D

S

Q

S

COUT

LUT-4 SUM

R

LUT-4

CCG

CLK/LE

SEL0

CE

IN

XIN2

XIN3

D

S

R

Q

CLK/LE

CE

SEL1

D

YIN0

YIN1

YIN2

YIN3

4C

S1

D

S

Q

S

COUT

LUT-4 SUM

SYNC/ASYNC

R

LUT-4

CCG

CLK/LE

CE

IN

YIN2

YIN3

D

S

R

Q

CLK/LE

CE

SEL2

D

ZIN0

ZIN1

ZIN2

ZIN3

4D

S0

D

S

Q

S

COUT

LUT-4 SUM

R

LUT-4

CCG

CLK/LE

CE

IN

ZIN2

ZIN3

D

S

R

Q

CLK/LE

CE

SEL3

CIN(r,c) from

COUT(r-1,c)

5

Lattice Semiconductor

ispXPGA Family Data Sheet

Configurable Logic Element

The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND

gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder,

and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of

the AND gate to one of the inputs of the CCG.

Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the remaining three take on

varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Feed-Thru to the

CSE via the WLG. The fifth input can be a data port when the LUT is configured as Distributed Memory, a select

line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figure 2).

Look-Up Table – Combinatorial Mode

In combinatorial mode, the LUT-4 can implement any logic function up to four inputs. By using the carry chain and

the WLG, each LUT-4 can be combined to form the enhanced functions listed in Table 3.

Look-Up Table – Distributed Memory Mode

In the distributed memory mode, the LUT functions as a memory element. The inputs to the LUT function as

Address and Data. Each PFU is capable of implementing up to 64 SRAM bits. Both single and double port RAM

can be performed in the PFU (Table 3). Furthermore, the distributed memory can be configured as either synchro-

nous or asynchronous memory. Figure 3 illustrates the LUT while in distributed memory mode. When using any

LUT in the PFU in memory mode, the Set/Reset signal will be used for Write Enable (WE(SR)) and the CLK0 signal

will be used as the clock for synchronous read and write.

Figure 3. LUT in Distributed Memory Mode

PFUCLK0

CEB0

WE (SR)

ADDR[0] (IN0)

ADDR[1] (IN1)

ADDR[2] (IN2)

ADDR[3] (IN3)

DIN (SEL)

LUT-4

DOUT (4A)

Look-Up Table – Shift Register Mode

In the shift register mode, the LUT functions as a 1-bit to 8-bit shift register. This means that each PFU can imple-

ment up to four 8-bit shift registers or any cascaded combination. Figure 4 illustrates the LUT when configured in

shift register mode.

6

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 4. LUT in Shift Register Mode

PFUCLK0

CEB0

SEL (SHIFTIN)

LUT-4

SHIFTOUT (4A)

Carry Chain Generator

The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a two-

input XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the

carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0. The sum

output of the CCG can be fed to the CSE through the WLG. The carryout must propagate to CLE0 for use outside

the PFU. The carryout from the PFU can feed the W0 input of CSE0. The CCG also helps to effectively implement

wider functions by using its logic elements to expand the capabilities of the LUT-4.

Figure 5. Carry Chain Generator

COUT(r,c)

COUT to

CSE0

SUM3

SUM2

SUM1

SUM0

CLE0

CLE1

CLE2

CLE3

A

B

COUT

SUM

CIN

CIN from

Routing

COUT(r+1,c)

Wide Logic Generator

The WLG contains the logic necessary to implement wide gate functions. This is made up of a set of multiplexers

that are located between the CLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU.

The outputs of each CLE can be cascaded in the WLG to build wide gating functions. Wide multiplexing functions

are also possible with a similar use of the WLG. Figure 6 illustrates the WLG.

7

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 6. ispXPGA Wide Logic Generator

COUT

WIN2

WIN3

4A

S3

SEL0

WLGW0

WLGW1

4B

XIN2

XIN3

WLGX0

WLGX1

S2

SEL1

SEL3

4C

SEL2

4D

YIN2

YIN3

S1

WLGY0

WLGY1

ZIN2

ZIN3

WLGZ0

WLGZ1

S0

Configurable Sequential Element

There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in

implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch

or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the

register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the

accompanying LUT is occupied.

Control Logic

The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the

various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX

with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or

complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common

8

Lattice Semiconductor

ispXPGA Family Data Sheet

Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical

OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not

controllable inside the PFU. The polarity of the Global Set/Reset signal (GSR) is programmable. Figure 9 shows

the Clock Enable and Output Enable selection for each PFU.

Figure 7. Clock Selection per PFU

CLK0

CLK1

CLK2

CLK3

PFUCLK0

CLK4

CLK5

CLK6

CLK7

PFUCLK1

From routing

4

Figure 8. Set/Reset Selection per PFU

8

From routing

Set/Reset

GSR

Figure 9. Clock Enable and Output Enable Selection per PFU

8

From routing

CEB0

8

CEB1

OE

From routing

Programmable Input/Output Cell

The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA

Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device.

Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18

inputs from routing, two inputs from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC

connect to routing and two outputs are available as Output Enables for the tri-statable Long Lines. The remaining

four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a

sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four additional

inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from the

PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the block

diagram of the PIC with the sysHSI block inputs and outputs.

9

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 10. ispXPGA PIC

GSR

sysIO

9

2

From routing

PIO0

To routing

2

From sysHSI block

To sysHSI block

To routing

Only for PICs

associated with

sysHSI blocks

Only for PICs

associated with

sysHSI blocks

To routing

PIC

2

From sysHSI block

To sysHSI block

2

9

To routing

PIO1

From routing

sysIO

OE1 OE0

Programmable Input/Output

The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are

generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock

Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable

(OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/

Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO

buffer directly as the output and output enable of the sysIO output buffer.

PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two

inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the

inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass,

and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same sig-

nals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable).

Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input

register path of the PIO has a ‘delay’ option, which slows the data-flow. A two-input OR function of the Global Set/

Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO

has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is com-

mon for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the

polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch

or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output.

10

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 11. ispXPGA PIO

Only for PIOs associated with sysHSI Blocks

From sysHSI block

To Routing

Feed-through (FT)

From sysIO Input

OUT0

OUT1

D

Q

R

Delay

CLK/LE

Clock (CLK)

Input Clock Enable (ICEN)

CE

S

Input Set/Reset (ISR)

Global Set/Reset(GSR)

To sysIO

Output

PIO Input (IN)

D

Q

R

To sysHSI

block

CLK/LE

Only for PIOs

Associated with

sysHSI Blocks

Output Clock Enable (OCEN)

Output Set/Reset (OSR)

CE

S

To sysHSI

block

To sysIO

Output

Enable

PIO Output Enable(OEN)

D

Q

R

CLK/LE

CE

S

PIO Input Enable (IEN)

OE

VLI Routing Resources

The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs,

PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Inter-

connect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in

the device with the optimal delay.

The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in

the device. They are specifically designed for high speed, predictable timing regardless of fan-out. The global clock

lines can also be used as dedicated inputs.

The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable

lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions.

The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two

plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element).

The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback

Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adja-

cent elements.

The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI

Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to

any input or output of the logic element.

11

Lattice Semiconductor

ispXPGA Family Data Sheet

Memory

The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded

Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see Look-

Up Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM

or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and

other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 for memory resources per

device.

sysMEM Blocks

The sysMEM blocks are organized in columns distributed throughout the device. Each EBR contains 4.6K bits of

dual-port RAM with dedicated control, address, and data lines for each port. Each column of sysMEM blocks has

dedicated address and control lines that can be used by each block separately or cascaded to form larger memory

elements. The memory cells are symmetrical and contain two sets of identical control signals. Each port has a

read/write clock, clock enable, write enable, and output enable. Figure 12 illustrates the sysMEM block.

The ispXPGA memory block can operate as single-port or dual-port RAM. Supported configurations are:

• 512 x 9 bits single-port

• 256 x 18 bits single-port

• 512 x 9 bits dual-port

• 256 x18 bits dual-port

(8 bits data / 1 bit parity)

(16 bits data / 2 bits parity)

(8 bits data / 1 bit parity)

(16 bits data / 2 bits parity)

The data widths of “9” and “18” are ideal for applications where parity is necessary. This allows 9 data bits, 8 data

bits plus a parity bit, 18 data bits, or 16 data bits plus two parity bits. The logic for generating and checking the par-

ity must be customized separately.

Figure 12. sysMEM Block Diagram

ADDRA

DATAA

CLKA

CEA

ADDRB

DATAB

CLKB

CE B

sysMEM Block

WEA

WEB

OEA

OEB

Read and Write Operations

The ispXPGA EBR has fully synchronous read and write operations as well as an asynchronous read operation.

These operations allow several different types of memory to be implemented in the device.

Synchronous Read: The Clock Enable (CE) and Write Enable (WE) signals control the synchronous read opera-

tion. When the CE signal is low, the clock is enabled. When the WE signal is low the read operation begins. Once

the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data

to be available on the DATA port. Figure 13 illustrates the synchronous read timing.

12

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 13. EBR Synchronous Read Timing Diagram

t_EBCPW

CLK

t_EBCES

t_EBCEH

CE

t_EBWES

t_EBWEH

WE

t_EBOEDIS

t_EBOEEN

OE

Invalid Data

t_EBWEEN

t_EBCO

Valid Data

DATA

t_EBWEDIS

t_EBADDS

ADDR

t_EBADDH

Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high, the

write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock

edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the

synchronous write timing.

Figure 14. EBR Synchronous Write Timing Diagram

CLK

t_EBPW

t_EBWES

t_EBWEH

WE

DATA

t_EBDATAH

t_EBDATAS

t_EBADDH

t_EBADDS

ADDR

WRITE

Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the

read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15

illustrates the asynchronous read timing. For more information about the EBR, refer to TN1028 ispXPGA Memory

Usage Guidelines.

Figure 15. EBR Asynchronous Read Timing Diagram

WE

t_EBOEDIS

t_EBOEEN

OE

DATA

Invalid Data

t_EBWEEN

t_EBWEDIS

DATA0

DATA1

ADDR0

ADDR1

ADDR2

t_{EBARAD_H}

ADDR

t_EBARADO

13

Lattice Semiconductor

ispXPGA Family Data Sheet

sysCLOCK PLL Description

The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback

signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-

ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned

either at the board level or the device level.

The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its associated global clock

pin, and its output is routed to the associated global clock net. For example, PLL0 receives its clock input from the

GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLL also has the ability to output a

secondary clock that is a division of the primary clock output. When using the secondary clock, the secondary

clock will be routed to the neighboring global clock net. For example, PLL0 will drive its primary clock output on the

CLK0 global clock net and its secondary clock output will drive the CLK1 global clock net. Additionally, each PLL

has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST signal can be generated through routing

or a dedicated dual-function I/O pin. The PLL_FBK signal can be generated through a dedicated dual-function I/O

pin or internally from the Global Clock net associated with the PLL. The PLL_LOCK signal feeds routing directly

from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RST and PLL_FBK signals are generated.

Each PLL has four dividers associated with it, M, N, V, and K. The M divider is used to divide the clock signal,

while the N divider is used to multiply the clock signal. The V divider allows the VCO frequency to operate at

higher frequencies than the clock output, thereby increasing the frequency range. The K divider is only used when

a secondary clock output is needed. This divider divides the primary clock output and feeds to the adjacent global

clock net. Different combinations of these dividers allow the user to synthesize clock frequencies. Figure 16 shows

the ispXPGA PLL block diagram.

The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and

clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the

PLL. For more information on the PLL, please refer to TN1003, sysCLOCK PLL Usage and Design Guidelines.

Figure 16. ispXPGA PLL Block Diagram

PLL_LOCK

CLK_OUT

GCLK_IN

Input Clock

Programmable

(M) Divider

+Delay

Post-scalar

÷ 1 to 32

(V) Divider

--------------------

PLL (n)

Clock Net

÷

1, 2, 4, 8,

16, 32

Programmable

-Delay

PLL_RST

Clock (K)

Divider

÷

2, 4, 8,

16, 32

To Adjacent_PLL

From

Adjacent_PLL

Feedback

Divider (N)

X 1 to 32

PLL_FBK

14

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 17. ispXPGA PLL_RST and PLL_FBK Generation

I/O/PLL_RST

From Routing

To PLL

I/O/PLL_FBK

To PLL

From Clock Net

Clock Routing

The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illus-

trates the generation of the Global Clock Lines.

Figure 18. Global Clock Line Generation

From Routing

GCLK0

GCLK1

GCLK2

GCLK3

GCLK7

GCLK6

GCLK5

GCLK4

CLK_OUT0

SEC_OUT0

CLK_OUT7

SEC_OUT7

CLK0

CLK7

PLL0

PLL1

PLL2

PLL3

PLL7

PLL6

PLL5

PLL4

From Routing

CLK_OUT1

SEC_OUT1

CLK_OUT6

SEC_OUT6

CLK1

CLK6

From Routing

CLK_OUT2

SEC_OUT2

CLK_OUT5

SEC_OUT5

CLK2

CLK5

CLK4

From Routing

CLK_OUT3

SEC_OUT3

CLK_OUT4

SEC_OUT4

CLK3

sysIO Capability

All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards.

Each sysIO bank has its own I/O supply voltage (V ) and reference voltage (V ) resources allowing each

CCO

REF

bank complete independence from the others. Each I/O is individually configurable based on the bank’s V

and

CCO

V

settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper

REF

latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant

inputs are specified within an I/O bank that is connected to V

interfaces.

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI

CCO

Table 5 lists the sysIO standards with the typical values for V

V

and V

CCO, REF TT.

The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not

have the sysIO capabilities. The TOE and CFG0 pins operate off the V of the device, supporting only the LVC-

CC

MOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (V

which determines the LVCMOS standard corresponding to that supply voltage.

),

CCJ

There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the un-

terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVC-

MOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface.

15

Lattice Semiconductor

ispXPGA Family Data Sheet

The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-

faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-

lar I/O interfaces requires an additional V

signal. At the system level a termination voltage, V , is also required.

REF

TT

Typically an output will be terminated to V at the receiving end of the transmission line it is driving.

TT

The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential

standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the

two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices.

For more information on sysIO capability, refer to TN1000, sysIO Usage Guidelines for Lattice Devices.

Figure 19. sysIO Banks per Device

Bank 7

Bank 6

I/O 0

I/O N

V_CCO0

V_REF0

V_CCO5

V_REF5

GND

I/O N

I/O 0

I/O N

V_CCO1

V_REF1

V_CCO4

V_REF4

GND

I/O N

I/O 0

Bank 2

Bank 3

Table 4. Number of I/Os per Bank

Device

Max. Number of I/Os per Bank (N)

XPGA 1200

XPGA 500

XPGA 200

XPGA 125

62

42

26

22

16

Lattice Semiconductor

ispXPGA Family Data Sheet

Table 5. ispXPGA Supported I/O Standards

sysIO Standard

V_CCO

3.3V

2.5V

1.8V

3.3V

2.5V

1.5V

N/A

V_REF

N/A

V_TT

N/A

LVTTL

LVCMOS-3.3

LVCMOS-2.5

LVCMOS-1.8

PCI

N/A

AGP-1X

N/A

SSTL3, Class I, II

SSTL2, Class I, II

HSTL, Class I

HSTL, Class III

GTL+

1.5V

1.25V

0.75V

0.9V

1.0V

N/A

1.5V

1.25V

0.75V

1.5V

N/A

LVPECL

3.3V

2.5V

LVDS¹

N/A

BLVDS

N/A

1. V_CCOmust be 2.5V for high speed serial operations (sysHSI block).

Table 6. Differential Interface Standard Support¹

sysIO Buffer Not Using sysHSI Block

Supported with external resistor network

sysIO Buffer Using sysHSI Block

Driver

Supported

LVDS

Receiver

Driver

Supported with standard termination

Supported with external resistor network

Supported (may need termination)

Supported with external resistor network

Supported with termination

Supported with standard termination

Not supported

BLVDS

LVPECL

Receiver

Driver

Supported (may need termination)

Not supported

Receiver

Supported with termination

1. For more information, refer to TN1000, sysIO Usage Guidelines for Lattice Devices.

17

Lattice Semiconductor

ispXPGA Family Data Sheet

High Speed Serial Interface Block (sysHSI Block)¹

The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The

ispXPGA devices have multiple sysHSI blocks.

Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and

Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full

duplex channel. The two SERDES in sysHSI blocks share a common clock and must operate at the same nominal

frequency. Figure 20 shows the sysHSI block.

Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see

Lattice’s sysHSI technical notes). The encoding and decoding of the 10B/12B standard are performed within the

sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decod-

ing are performed outside the sysHSI block.

Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,

and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, SERDES

converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output.

Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 chan-

nels.

For more information on the SERDES/CDR, refer to TN1020, sysHSI Usage Guidelines.

Figure 20. sysHSI Block Diagram

SERDES(HSI#A)

10

SOUT

SIN

TXD

RXD

From PICs

Serializer

10

To PICs

RECCLK

Deserializer and Clock/Data Recovery

SYDT

To PICs

sysIO

CDRRST

From PICs

CAL

From PICs

To PICs

CSLOCK

SS_CLKOUT

SS_CLKIN

CSPLL

From Global

Clock Tree

REFCLK

CDRRST

SYDT

From PICs

To PICs

Deserializer and Clock/Data Recovery

SIN

RECCLK

To PICs

10

RXD

10

TXD

SOUT

Serializer

From PICs

SERDES(HSI#B)

1. “E-Series” does not support sysHSI.

18

Lattice Semiconductor

ispXPGA Family Data Sheet

Configuration and Programming

The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of

memory, Static RAM and non-volatile E²CMOS cells. The static RAM is used to control the functionality of the

device during normal operation and the E²CMOS memory cells are used to load the SRAM. The E²CMOS memory

module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-

tion memory. There is a one-to-one relationship between SRAM memory and the E²CMOS cells. The SRAM can

be configured either from the E²CMOS memory or from an external source, as shown in Figure 21.

Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA

devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which

supports the IEEE 1149.1 Test Access Port (TAP) Std., accommodates bit-wide configuration. The sysCONFIG

port allows byte-wide configuration of the SRAM configuration memory. When programming the E²CMOS memory,

only the 1149.1 TAP can be used.

Configuration and programming done through the 1149.1 Test Access Port (TAP) supports both the IEEE Std.

1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification. To config-

ure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the SRAM mem-

ory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM

memory can be configured either from the E²CMOS memory or from an external source through the sysCONFIG

mode. Additionally, the SRAM can be re-configured from the E²CMOS memory by executing a “REFRESH.” See

TN1026, ispXP Configuration Usage Guidelines, for more in depth information on the different programming

modes, timing and wake-up.

Figure 21. ispXP Block Diagram

ISP 1149.1 TAP Port

sysCONFIG Peripheral Port

sysCONFIG

Port

ISP

Mode

BACKGND

1532

Programming

in seconds

Configuration

in milliseconds

Power-up

Refresh

E²CMOS

Memory Space

SRAM

Memory Space

Download in

microseconds

Memory Space

Supports IEEE 1149.1 Boundary Scan Testability

All ispXPGA devices have boundary scan cells and supports the IEEE 1149.1 standard. This allows functional test-

ing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic

notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly

onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be

linked into a board-level serial scan path for more board level testing.

Security Scheme

A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of

the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed

19

Lattice Semiconductor

ispXPGA Family Data Sheet

pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased

in order to erase the security scheme.

Density Shifting

The ispXPGA family has been designed to ensure that different density devices in the same package have the

same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from

lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted

for a high-density device to a lower density device. However, the exact details of the final resource utilization will

impact the likely success in each case.

Temperature Sensing Diode

The built-in temperature-sensing diodes allow junction temperature to be measured during device operation. A pair

of pins (DXp and DXn) are dedicated for monitoring device junction temperature. The measurement is done by

forcing 10 µA and 100 µA current in the forward direction, and then measuring the resulting voltage. The voltage

decreases with increasing temperature at approximately 1.64 mV/°C. A typical device with a 85°C junction temper-

ature will measure approximately 593 mV.

The temperature-sensing diode works for the entire operating range as shown in Figure 22 - Sensing Diode Volt-

age-Temperature Relationship. Refer to the Lattice Thermal Management document for thermal coefficients. Also

refer to TN1043, Power Estimation in ispXPGA Devices.

Figure 22. Sensing Diode Voltage-Temperature Relationship

0.85

0.80

100 uA

10 uA

0.75

0.70

0.65

0.60

0.55

0.50

-50

0

25

50

100

125

-25

75

Junction Temperature (°C)

20

Lattice Semiconductor

ispXPGA Family Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

1.8V

2.5V/3.3V

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V

CC

PLL Supply Voltage (V

) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V

CCP

Output Supply Voltage (V

) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V

CCO

IEEE 1149.1 TAP Supply Voltage (V

). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V

CCJ

Input Voltage Applied^{4, 5}. . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150C. . . . . . . . . -65 to 150C

Junction Temperature (T ) with Power Applied . .-55 to 150C. . . . . . . . . -55 to 150C

J

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, following the programming specifications).

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V_IH(MAX) + 2) volts not to exceed 6V is permitted for a duration of <20ns.

5. A maximum of 64 I/Os per device with V_IN> 3.6V is allowed.

Recommended Operating Conditions

Symbol

Parameter

Min

1.65

2.3

3.0

1.65

2.3

3.0

1.65

2.3

3.0

0

Max

1.95

2.7

Units

V

Supply Voltage for 1.8V device¹

Supply Voltage for 2.5V device

Supply Voltage for 3.3V device

V_CC

V

3.6

V

Supply Voltage for PLL and sysHSI blocks, 1.8V devices¹

Supply Voltage for PLL and sysHSI blocks, 2.5V devices

Supply Voltage for PLL and sysHSI blocks, 3.3V devices

Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 1.8V

Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 2.5V

Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 3.3V

Junction Temperature Commercial Operation

1.95

2.7

V

V_CCP

V

3.6

V

1.95

2.7

V

V_CCJ

V

3.6

V

T_J(COM)

T_J(IND)

85

C

Junction Temperature Industrial Operation

-40

105

C

1. sysHSI specification is valid for V_CCand V_CCP= 1.7V to 1.9V.

E²CMOS Erase Reprogram Specifications

Parameter

Erase/Reprogram Cycle¹

Min

Max

Units

1,000

—

Cycles

1. Valid over commercial temperature range.

Hot Socketing Characteristics^{1, 2, 3, 4}

Symbol

Parameter

Condition

Min

Typ

+/-50

Max

+/-800

Units

I_DK

Input or Tristated I/O Leakage Current 0 ð V_INð 3.0V

—

A

1. Insensitive to sequence of V_CCand V_CCOwhen V_CCOð 1.0V. For V_CCO> 1.0V, V_CCmin must be present. However, assumes monotonic

rise/fall rates for V_CCand V_CCO, provided (V_IN- V_CCO) ð 3.6V.

2. LVTTL, LVCMOS only.

3. 0 < V_CCð V_CC(MAX), 0 < V_CCOð V_CCO(MAX).

4. I_DKis additive to I_PU, I_PDor I_BH. Device defaults to pull-up until non-volatile cells are active.

21

Lattice Semiconductor

ispXPGA Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

0 ð V_IN< (V_CCO- 0.2V)

(V_CCO- 0.2V) ð V_INð 3.6V

Min

—

Typ

—

Max

10

Units

A

1

I_IL, I_IH

Input or I/O Low Leakage

Input High Leakage Current

—

300

A

3.6V < V_INð 5.5V and

3.0V ð V_CCOð 3.6V

2

I_IH

—

3

mA

I_PU

I/O Active Pull-up Current

0 ð V_INð 0.7 V_CCO

-30

—

-150

A

V

I_PD

I/O Active Pull-down Current

V_IL(MAX) ð V_INð V_IH(MAX)

30

150

I_BHLS

I_BHHS

I_BHLO

I_BHHO

V_BHT

Bus Hold Low Sustaining Current V_IN= V_IL(MAX)

Bus Hold High Sustaining Current V_IN= 0.7 V_CCO

Bus Hold Low Overdrive Current 0 ð V_INð V_IH(MAX)

Bus Hold High Overdrive Current 0 ð V_INð V_IH(MAX)

Bus Hold Trip Points

30

—

-30

—

150

—

-150

V_CCO* 0.35

V_CCO* 0.65

V_CCO= 3.3V, 2.5V, 1.8V

I/O Capacitance³

—

C₁

C₂

C₃

8

6

pf

V

_CC= 1.8V, V_IO= 0 to V_IH(MAX)

V_CCO= 3.3V, 2.5V, 1.8V

V_CC= 1.8V, V_IO= 0 to V_IH(MAX)

V_CCO= 3.3V, 2.5V, 1.8V

Clock Capacitance³

Global Input Capacitance³

V_CC= 1.8V, V_IO= 0 to V_IH(MAX)

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ð V_CCOð 3.6V. The JTAG and sysCONFIG ports are not included for the

5V tolerant interface.

3. T_A= 25C, f = 1.0MHz.

22

Lattice Semiconductor

ispXPGA Family Data Sheet

Supply Current

Over Recommended Operating Conditions

Symbol

Parameter

Device

Condition

V_CC= 3.3V

Min.

—

Typ.

60

Max.

—

Units

mA

LFX125

V

_CC= 2.5V

60

_CC= 1.8V

_CC= 3.3V

_CC= 2.5V

_CC= 1.8V

_CC= 3.3V

_CC= 2.5V

_CC= 1.8V

_CC= 3.3V

40

70

LFX200

LFX500

70

50

1, 2

I_CC

Standby Core Operating Power Supply Current

120

100

220

200

2.0

17.0

15.0

2.0

1.5

1.0

LFX1200 V_CC= 2.5V

_CC= 1.8V

V

V_CCO= 3.3V

V_CCO= 2.5V

3

I_CCO

Standby Output Power Supply Current

V

_CCO= 1.8V

_CCO= 1.5V

V

V_CCP= 3.3V

4

I_CCP

Standby PLL Operating Supply Current

V

_CCP= 2.5V

_CCP= 1.8V

V

V_CCJ= 3.3V

5

I_CCJ

Standby IEEE 1149.1 TAP Power Supply Current

V

_CCJ= 2.5V

_CCJ= 1.8V

V

1. T_A= 25°C, frequency = 1.0 MHz, device configured with 16-bit counters.

2. I_CCvaries with specific device configuration and operating frequency. For more accurate power calculation, see TN1043, Power Estimation

in ispXPGA Devices.

3. T_A= 25°C, per bank, no DC load, frequency = 0 MHz.

4. T_A= 25°C, per PLL, frequency = 10 MHz.

5. T_A= 25°C

23

Lattice Semiconductor

ispXPGA Family Data Sheet

sysIO Recommended Operating Conditions

V_CCO(V)¹

V_REF(V)

Standard

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8²

LVTTL

Min.

3.0

2.3

1.65

3.0

3.15

2.3

3.0

2.3

1.4

-

Typ.

3.3

2.5

1.8

3.3

2.5

3.3

2.5

1.5

-

Max.

3.6

2.7

1.95

3.6

3.45

2.7

3.6

2.7

1.6

-

Min.

Typ.

Max.

-

PCI 3.3

-

AGP-1X

-

1.15

1.3

1.35

0.68

-

1.35

1.7

1.65

0.9

-

SSTL 2

1.25

1.5

0.75

0.9

1.0

-

SSTL 3

CTT 3.3

CTT 2.5

HSTL Class I

HSTL Class III

GTL+

0.882

-

1.122

-

LVDS

2.3

3.0

2.3

2.5

3.3

2.5

2.7

3.6

2.7

LVPECL

-

BLVDS

-

1. Inputs independent of V_CCO.

2. Design tool default setting.

24

Lattice Semiconductor

ispXPGA Family Data Sheet

sysIO DC Electrical Characteristics

Over Recommended Operating Conditions

V_IL

V_IH

V_OL

Max. (V)

V_OH

Min. (V)

Standard

Min. (V)

Max. (V)

Min. (V)

Max. (V)

I_OL(mA)

I_OH(mA)

20, 16, 12, -20, -16,-12,

8, 5.33, 4 -8, -5.33, -4

0.4

0.2

0.4

0.2

0.4

V

_CCO- 0.4

V_CCO- 0.2

V_CCO- 0.4

LVCMOS 3.3

-0.3

0.8

2.0

5.5

0.1

-0.1

16, 12, 8, -16, -12, -8,

5.33, 4

0.1

12, 8¹, 5.33,

-5.33, -4

-0.1

-12, -8¹,

LVCMOS 2.5

LVCMOS 1.8¹

-0.3

0.7

1.7

3.6

V

_CCO- 0.2

0.68³

1.07³

V_CCO- 0.4

4

-5.33, -4

0.35V_CC

0.65V_CC

0.2

0.4

0.2

V_CCO- 0.2

V_CCO- 0.4

0.1

4

-0.1

-4

LVTTL

-0.3

0.8

2.0

5.5

3.6

V

_CCO- 0.2

0.1

-0.1

1.08³

0.3V_CCO

1.08³

1.5³

PCI 3.3

AGP-1X

0.1 V_CCO

0.9 V_CCO

1.5

-0.5

0.5 V_CCO

1.5³

0.3 V_CCO

0.5 V_CCO

SSTL 3 Class I

SSTL 3 Class II

SSTL 2 Class I

SSTL 2 Class II

CTT 3.3

-0.3

V_REF- 0.2 V_REF+ 0.2

_REF- 0.2 V_REF+ 0.2

_REF- 0.18 V_REF+ 0.18

V_REF- 0.18 V_REF+ 0.18

3.6

0.7

0.5

V_CCO- 1.1

V_CCO- 0.9

V_CCO- 0.62

V_CCO- 0.43

8

16

7.6

15.2

8

-8

-16

-7.6

-15.2

-8

V

0.54

0.35

V

_REF- 0.2 V_REF+ 0.2

V_REF- 0.4 V_REF+ 0.4

CTT 2.5

V

8

-8

HSTL Class I

HSTL Class III

GTL+

V_REF- 0.1 V_REF+ 0.1

0.4

0.6

V_CCO- 0.4

N/A

8

-8

V

_REF- 0.1 V_REF+ 0.1

_REF- 0.2 V_REF+ 0.2

24

36

-8

V

N/A

1. Design tool default setting.

2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the

I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND con-

nections or between the last GND in a bank and the end of a bank

3. Applicable for ispXPGA B devices.

25

Lattice Semiconductor

ispXPGA Family Data Sheet

sysIO Differential Standards DC Electrical Characteristics¹

Parameter

LVDS²

V_INP,V_INM

V_THD

I_IN

Description

Test Conditions

Min.

Typ.

Max.

Input voltage

0V

+/-100mV

—

2.4V

—

Differential input threshold

Input current

0.2V ð V_CMð 1.8V

Power on

—

+/-10uA

1.60V

—

V_OH

Output High Voltage for V_OPor V_OM

Output Low Voltage for V_OPor V_OM

Output Voltage Differential

Change in V_ODbetween high and low

Output Voltage Offset

RT = 100 Ohm

—

1.38V

1.03V

350mV

—

V_OL

RT = 100 Ohm

0.9V

250mV

—

V_OD

|V_OP- V_OM|, R_T= 100 ohm

450mV

50mV

1.375V

50mV

24mA

V_OD

V_OS

|V_OP+ V_OM|/2, R_T= 100 ohm

1.125V

—

1.25V

—

V_OS

I_OSD

Change in V_OSbetween H and L

Output short circuit current

V_OD= 0V Driver outputs

shorted

—

BLVDS¹

V_INP,V_INM

V_THD

I_IN

Input voltage

0V

+/-100mV

—

2.4V

—

Differential input threshold

Input current

0.2V ð V_CMð 1.8V

Power on

—

+/-10uA

1.80V

—

V_OH

Output High Voltage for V_OPor V_OM

Output Low Voltage for V_OPor V_OM

Output Voltage Differential

Change in V_ODBetween H and L

Output Voltage Offset

R_T= 27

—

1.4V

1.1V

300mV

V_OL

R_T= 27

0.95V

240mV

V_OD

|V_OP- V_OM|, RT = 27

460mV

27mV

1.5V

V_OD

V_OS

|V_OP+ V_OM| /2, RT = 27

1.1V

1.3V

V_OS

I_OSD

Change in V_OSBetween H and L

Output Short Circuit Current

27mV

V_OD= 0. Driver Outputs

Shorted.

36mA

65mA

1. Refer to TN1000, sysIO Usage Guidelines for Lattice Devices.

2. V_OPand V_OMare the two outputs of the LVDS/BLVDS output buffer.

LVPECL¹

DC

Parameter

Parameter Description

Input Voltage High

Min.

Max.

Min.

Max.

Min.

Max.

Units

V_CCO

3.0

3.3

3.6

V

V_IH

1.49

0.86

1.8

2.72

2.125

2.11

1.27

—

1.49

0.86

1.92

1.06

0.3

2.72

2.125

2.28

1.43

—

1.49

0.86

2.13

1.3

2.72

2.125

2.41

1.57

—

V_IL

Input Voltage Low

V_OH

V_OL

V_DIFF

Output Voltage High

Output Voltage Low

Differential Input threshold

0.96

0.3

2

0.3

1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 23).

The V_OHlevels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.

2. Valid for 0.2 ð V_CMð 1.8V.

26

Lattice Semiconductor

ispXPGA Family Data Sheet

Figure 23. LVPECL Driver with Three Resistor Pack

1/4 of Bourns P/N

ispXPLD Emulated

CAT 16-PC4F12

LVPECL Buffer

A

Zo

Rs

to LVPECL

differential

receiver

Rs

ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characteristics

Over Recommended Operating Conditions

-5¹

Min. Max. Min. Max. Min. Max. Units

-4

-3

Parameter

Description

Conditions

Global Clock Input to

Output

PIO Output Register

t_CO

—

-1.9

2.7

5.3

—

-1.8

2.9

5.7

—

-1.5

3.3

6.6

—

ns

PIO Input Register without input

delay

t_S

Global Clock Input Setup

Global Clock Input Hold

PIO Input Register without input

delay

t_H

t_SINDLY

t_HINDLY

t_COPLL

—

ns

Global Clock Input Setup PIO Input Register with input delay 3.1

—

3.3

0.0

—

3.8

0.0

—

Global Clock Input Hold

PIO Input Register with input delay 0.0

Global Clock Input to

Output

PIO Output Register using PLL

without delay

—

3.6

—

0.1

1.0

5.5

-2.8

3.9

—

0.3

1.2

6.3

-2.4

4.5

—

ns

PIO Input Register without input

delay using PLL without delay

t_SPLL

Global Clock Input Setup

Global Clock Input Hold

0

PIO Input Register without input

0.9

t_HPLL

delay using PLL without delay

PIO Input Register with input delay

5.1

t_SINDLYPLLGlobal Clock Input Setup

t_HINDLYPLLGlobal Clock Input Hold

using PLL without delay

PIO Input Register with input delay

-3.0

ns

using PLL without delay

1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.

Timing v.0.3

27

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Functional Delays

LUTs

Description

Min. Max. Min. Max. Min. Max. Units

t_LUT4

t_LUT5

t_LUT6

4-Input LUT Delay

—

0.41

0.73

0.86

—

0.44

0.79

0.93

—

0.51

0.91

1.07

ns

5-Input LUT Delay

6-Input LUT Delay

Shift Register (LUT)

t_{LSR_S}

t_{LSR_H}

t_{LSR_CO}

Shift Register Setup Time

Shift Register Hold Time

Shift Register Clock to Output Delay

-0.64

0.61

—

-0.62

0.63

—

-0.53

0.72

—

ns

0.70

0.75

0.86

Arithmetic Functions

t_LCTHRURMC (Macro Cell) Carry In to MC Carry Out Delay (Ripple)

—

0.08

0.05

0.42

0.29

0.36

0.26

—

0.09

0.05

0.45

0.31

0.39

0.28

—

0.10

0.06

0.52

0.36

0.45

0.32

ns

2

t_LCTHRUL

t_LSTHRU

MC Carry In to MC Carry Out Delay (Look Ahead)

MC Sum In to MC Sum Out Delay

t_LSINCOUT

MC Sum In to MC Carry Out Delay

t_LCINSOUTRMC Carry In to MC Sum Out Delay (Ripple)

t_LCINSOUTLMC Carry In to MC Sum Out Delay (Look Ahead)

Feed-thru

t_LFT

PFU Feed-Thru Delay

—

0.15

—

0.16

—

0.18

ns

Distributed RAM

t_{LRAM_CO}

t_{LRAMAD_S}

t_{LRAMD_S}

Clock to RAM Output

—

1.24

—

1.33

—

1.53

—

ns

Address Setup Time

Data Setup Time

-0.41

0.21

0.45

0.58

0.11

0.12

2.91

—

-0.40

0.22

0.46

0.60

0.11

0.12

3.00

—

-0.34

0.25

0.53

0.69

0.13

0.14

3.45

—

t_{LRAMWE_S}Write Enable Setup Time

—

t_{LRAMAD_H}

t_{LRAMD_H}

Address Hold Time

Data Hold Time

—

t_{LRAMWE_H}Write Enable Hold Time

t_LRAMCPWClock Pulse Width (High or Low)

t_LRAMADOAddress to Output Delay

—

0.86

0.93

1.07

Register/Latch Delays

Registers

t_{L_CO}

t_{L_S}

Register Clock to Output Delay

—

0.58

—

0.62

—

0.71

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

0.14

-0.12

-0.11

0.11

0.14

-0.12

-0.11

0.11

0.16

-0.10

-0.09

0.13

t_{L_H}

—

t_{LCE_S}

t_{LCE_H}

Latches

t_{L_GO}

t_{LL_S}

—

Latch Gate to Output Delay

Latch Setup Time

—

0.14

-0.12

—

0.09

—

0.14

-0.12

—

0.10

—

0.16

-0.10

—

0.12

—

ns

t_{LL_H}

Latch Hold Time

—

t_LLPD

Latch Propagation Delay (Transparent Mode)

0.09

0.10

0.12

28

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Reset/Set

t_LASSRO

Description

Min. Max. Min. Max. Min. Max. Units

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery

Synchronous Set/Reset Setup Time

Synchronous Set/Reset Hold Time

—

4.19

—

1.09

—

4.50

—

1.17

—

5.18

—

1.35

—

ns

t_LASSRPW

t_LASSRR

0.51

—

0.55

—

0.63

—

ns

t_{LSSR_S}

-0.03

0.03

-0.03

0.03

-0.03

0.03

ns

t_{LSSR_H}

—

ns

1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.

2. t_LCTHRULquoted bit by bit.

Timing v.0.3

ispXPGA 125B/C & ispXPGA 125EB/EC PIC Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Register/Latch Delays

t_{IO_CO}

t_{IO_S}

Register Clock to Output Delay

—

0.05

0.06

-0.03

0.13

—

0.89

—

0.05

0.06

-0.03

0.13

—

0.96

—

0.06

0.07

-0.03

0.15

—

1.10

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

Latch Gate to Output Delay

t_{IO_H}

—

t_{IOCE_S}

t_{IOCE_H}

t_{IO_GO}

t_{IOL_S}

—

0.68

—

0.73

—

0.84

—

Latch Setup Time

0.05

0.06

—

0.05

0.06

—

0.06

0.07

—

t_{IOL_H}

Latch Hold Time

—

t_IOLPD

t_IOASRO

t_IOASRPW

t_IOASRR

Latch Propagation Delay (Transparent Mode)

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery Time

0.09

1.00

—

0.10

1.08

—

0.12

1.24

—

4.19

—

4.50

—

5.18

—

0.23

0.25

0.29

Input/Output Delays

t_IOBUFOutput Buffer Delay

t_IOIN

—

0.97

0.57

0.53

-0.14

0.19

—

1.04

0.61

0.57

-0.13

0.20

—

1.20

0.70

0.66

-0.11

0.23

ns

Input Buffer Delay

Output Enable Delay

Output Disable Delay

Feed-thru Delay

t_IOEN

t_IODIS

t_IOFT

1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.

Timing v.0.3

29

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 125B/C & ispXPGA 125EB/EC EBR Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Synchronous Write

t_{EBSWAD_S}Address Setup Delay

t_{EBSWAD_H}Address Hold Delay

0.59

-0.40

3.16

-0.12

0.16

0.27

-0.27

—

0.61

-0.39

3.40

-0.12

0.16

0.28

-0.26

—

0.70

-0.33

3.91

-0.10

0.18

0.32

-0.22

—

ns

t_EBSWCPW

Clock Pulse Width

t_{EBSWWE_S}Write Enable Setup Time

t_{EBSWWE_H}Write Enable Hold Time

t_{EBSWD_S}

t_{EBSWD_H}

Data Setup Time

Data Hold Time

Synchronous Read

t_{EBSR_CO}

t_{EBSRAD_S}

t_{EBSRAD_H}

t_EBSRCPW

t_{EBSRCE_S}

t_{EBSRCE_H}

Clock to Data Delay

—

0.10

-0.07

3.16

-1.76

1.64

-0.18

0.12

—

2.04

—

0.10

-0.07

3.40

-1.71

1.69

-0.17

0.12

—

2.19

—

0.12

-0.06

3.91

-1.45

1.94

-0.14

0.14

—

2.52

—

ns

Address Setup Delay

Address Hold Delay

Clock Pulse Width

—

Clock Enable Setup Time

Clock Enable Hold Time

—

t_{EBSRWE_S}Write Enable Setup Time

—

t_{EBSRWE_H}Write Enable Hold Time

—

t_EBSRWEENWrite Enable to Data Enable Time

t_EBSRWEDISWrite Enable to Data Disable Time

1.02

0.99

1.02

0.83

1.05

1.02

1.05

0.86

1.21

1.17

1.21

0.99

—

t_EBSREN

t_EBSRDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

—

Asynchronous Read

t_EBARADOAddress to New Valid Data Delay

t_{EBARAD_H}Address to Previous Valid Data Delay

—

2.39

2.10

1.01

0.98

1.02

0.83

—

2.46

2.17

1.04

1.01

1.05

0.86

—

2.83

2.50

1.20

1.16

1.21

0.99

ns

t_EBARWEENWrite Enable to Data Enable Time

t_EBARWEDISWrite Enable to Data Disable Time

t_EBAREN

t_EBARDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

ns

1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.

Timing v.0.3

30

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders

-5¹

-4

-3

Base

Parameter

Optional Adders

t_IOINDLY

Description

Input Delay

Parameter Min. Max. Min. Max. Min. Max. Units

—

4.28

—

4.6

—

5.29

ns

t_IOIInput Adjusters

LVTTL_in

Using 3.3V TTL

t_IOIN

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

ns

LVCMOS_18_in

LVCMOS_25_in

LVCMOS_33_in

AGP_1X_in

CTT25_in

Using 1.8V CMOS

Using 2.5V CMOS

Using 3.3V CMOS

Using AGP 1x

Using CTT 2.5V

CTT33_in

Using CTT 3.3V

GTL+_in

Using GTL+

HSTL_I_in

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

HSTL_III_in

LVDS_in

Using Low Voltage

Differential Signaling (LVDS)

BLVDS_in

Using Bus Low Voltage

Differential Signaling (BLVDS)

t_IOIN

—

0.8

—

0.8

—

0.8

ns

LVPECL_in

PCI_in

Using Low Voltage PECL

Using PCI

t_IOIN

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

ns

SSTL2_I_in

SSTL2_II_in

SSTL3_I_in

SSTL3_II_in

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t_IOOOutput Adjusters

Slow Slew

Using Slow Slew (LVTTL and t_IOBUF, t_IOEN

LVCMOS Outputs only)

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

ns

LVTTL_out

Using 3.3V TTL Drive

t_{IOBUF, IOEN,}

t

t_IODIS

LVCMOS_18_4mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33mA Drive t_IODIS

LVCMOS_18_8mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_18_12mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_4mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33 mA Drive t_IODIS

LVCMOS_25_8mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_25_12mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_16mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

31

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders (Cont.)

-5¹

Parameter Min. Max. Min. Max. Min. Max. Units

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

4mA Drive t_IODIS

_IOBUF,t_IOEN,

t_IODIS

-4

-3

Base

Parameter

Description

LVCMOS_33_4mA_out

t

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

ns

LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,

5.33mA Drive

t

LVCMOS_33_8mA_out

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_33_12mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_33_16mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

LVCMOS_33_24mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

24mA Drive

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

AGP_1X_out

CTT25_out

CTT33_out

GTL+_out

Using AGP 1x Standard

t

Using CTT 2.5V

t

Using CTT 3.3V

t

Using GTL+

t

HSTL_I_out

HSTL_III_out

LVDS_out

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

t

Using Low Voltage Differen-

tial Signaling (LVDS)

t

BLVDS_out

LVPECL_out

PCI_out

Using Bus Low Voltage Differ- t_IOBUF,t_IOEN,

ential Signaling (BLVDS)

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

Using Low Voltage PECL

t

Using PCI Standard

t

SSTL2_I_out

SSTL2_II_out

SSTL3_I_out

SSTL3_II_out

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t

1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.

Timing v.0.3

32

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC External Switching Characteristics

Over Recommended Operating Conditions

-5¹

Min. Max. Min. Max. Min. Max. Units

-4

-3

Parameter

Description

Conditions

Global Clock Input to Out- PIO Output Register

put

t_CO

—

-2.0

3.7

5.5

—

-2.0

3.8

5.9

—

-1.7

4.4

6.8

—

ns

PIO Input Register without input

delay

t_S

Global Clock Input Setup

Global Clock Input Hold

PIO Input Register without input

delay

t_H

t_SINDLY

t_HINDLY

t_COPLL

—

ns

Global Clock Input Setup PIO Input Register with input delay 3.8

—

3.8

0.0

—

4.4

0.0

—

Global Clock Input Hold

PIO Input Register with input delay 0.0

Global Clock Input to

Output

PIO Output Register using PLL

without delay

—

3.3

—

3.6

—

0.1

1.8

7.3

-2.2

4.2

—

ns

PIO Input Register without input

-0.2

t_SPLL

Global Clock Input Setup

Global Clock Input Hold

-0.2

1.5

6.3

-2.6

delay using PLL without delay

PIO Input Register without input

1.5

t_HPLL

delay using PLL without delay

PIO Input Register with input delay

6.3

t_SINDLYPLLGlobal Clock Input Setup

t_HINDLYPLLGlobal Clock Input Hold

using PLL without delay

PIO Input Register with input delay

-2.7

ns

using PLL without delay

1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.

Timing v.0.2

33

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Functional Delays

LUTs

Description

Min. Max. Min. Max. Min. Max. Units

t_LUT4

t_LUT5

t_LUT6

4-Input LUT Delay

—

0.41

0.73

0.86

—

0.44

0.79

0.93

—

0.51

0.91

1.07

ns

5-Input LUT Delay

6-Input LUT Delay

Shift Register (LUT)

t_{LSR_S}

t_{LSR_H}

t_{LSR_CO}

Shift Register Setup Time

Shift Register Hold Time

Shift Register Clock to Output Delay

-0.64

0.61

—

-0.62

0.63

—

-0.53

0.72

—

ns

0.70

0.75

0.86

Arithmetic Functions

t_LCTHRURMC (Macro Cell) Carry In to MC Carry Out Delay (Ripple)

—

0.08

0.05

0.42

0.29

0.36

0.26

—

0.09

0.05

0.45

0.31

0.39

0.28

—

0.10

0.06

0.52

0.36

0.45

0.32

ns

2

t_LCTHRUL

t_LSTHRU

MC Carry In to MC Carry Out Delay (Look Ahead)

MC Sum In to MC Sum Out Delay

t_LSINCOUT

MC Sum In to MC Carry Out Delay

t_LCINSOUTRMC Carry In to MC Sum Out Delay (Ripple)

t_LCINSOUTLMC Carry In to MC Sum Out Delay (Look Ahead)

Feed-thru

t_LFT

PFU Feed-Thru Delay

—

0.15

—

0.16

—

0.18

ns

Distributed RAM

t_{LRAM_CO}

t_{LRAMAD_S}

t_{LRAMD_S}

Clock to RAM Output

—

1.24

—

1.33

—

1.53

—

ns

Address Setup Time

Data Setup Time

-0.41

0.21

0.45

0.58

0.11

0.12

2.91

—

-0.40

0.22

0.46

0.60

0.11

0.12

3.00

—

-0.34

0.25

0.53

0.69

0.13

0.14

3.45

—

t_{LRAMWE_S}Write Enable Setup Time

—

t_{LRAMAD_H}

t_{LRAMD_H}

Address Hold Time

Data Hold Time

—

t_{LRAMWE_H}Write Enable Hold Time

t_LRAMCPWClock Pulse Width (High or Low)

t_LRAMADOAddress to Output Delay

—

0.86

0.93

1.07

Register/Latch Delays

Registers

t_{L_CO}

t_{L_S}

Register Clock to Output Delay

—

0.58

—

0.62

—

0.71

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

0.14

-0.12

-0.11

0.11

0.14

-0.12

-0.11

0.11

0.16

-0.10

-0.09

0.13

t_{L_H}

—

t_{LCE_S}

t_{LCE_H}

Latches

t_{L_GO}

t_{LL_S}

—

Latch Gate to Output Delay

Latch Setup Time

—

0.14

-0.12

—

0.09

—

0.14

-0.12

—

0.10

—

0.16

-0.10

—

0.12

—

ns

t_{LL_H}

Latch Hold Time

—

t_LLPD

Latch Propagation Delay (Transparent Mode)

0.09

0.10

0.12

34

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Reset/Set

t_LASSRO

Description

Min. Max. Min. Max. Min. Max. Units

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery

Synchronous Set/Reset Setup Time

Synchronous Set/Reset Hold Time

—

4.19

—

1.09

—

4.50

—

1.17

—

5.18

—

1.35

—

ns

t_LASSRPW

t_LASSRR

0.51

—

0.55

—

0.63

—

ns

t_{LSSR_S}

-0.03

0.03

-0.03

0.03

-0.03

0.03

ns

t_{LSSR_H}

—

ns

1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.

2. t_LCTHRULquoted bit by bit.

Timing v.0.3

ispXPGA 200B/C & ispXPGA 200EB/EC PIC Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Register/Latch Delays

t_{IO_CO}

t_{IO_S}

Register Clock to Output Delay

—

0.05

0.06

-0.03

0.13

—

0.93

—

0.05

0.06

-0.03

0.13

—

1.00

—

0.06

0.07

-0.03

0.15

—

1.15

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

Latch Gate to Output Delay

t_{IO_H}

—

t_{IOCE_S}

t_{IOCE_H}

t_{IO_GO}

t_{IOL_S}

—

0.72

—

0.77

—

0.89

—

Latch Setup Time

0.05

0.06

—

0.05

0.06

—

0.06

0.07

—

t_{IOL_H}

Latch Hold Time

—

t_IOLPD

t_IOASRO

t_IOASRPW

t_IOASRR

Latch Propagation Delay (Transparent Mode)

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery Time

0.09

1.04

—

0.10

1.12

—

0.12

1.29

—

4.19

—

4.50

—

5.18

—

0.23

0.25

0.29

Input/Output Delays

t_IOBUFOutput Buffer Delay

t_IOIN

—

0.97

0.60

0.53

-0.13

0.19

—

1.04

0.64

0.57

-0.12

0.20

—

1.20

0.74

0.66

-0.10

0.23

ns

Input Buffer Delay

Output Enable Delay

Output Disable Delay

Feed-thru Delay

t_IOEN

t_IODIS

t_IOFT

1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.

Timing v.0.3

35

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC EBR Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Synchronous Write

t_{EBSWAD_S}Address Setup Delay

t_{EBSWAD_H}Address Hold Delay

0.59

-0.40

3.16

-0.12

0.16

0.27

-0.27

—

0.61

-0.39

3.40

-0.12

0.16

0.28

-0.26

—

0.70

-0.33

3.91

-0.10

0.18

0.32

-0.22

—

ns

t_EBSWCPW

Clock Pulse Width

t_{EBSWWE_S}Write Enable Setup Time

t_{EBSWWE_H}Write Enable Hold Time

t_{EBSWD_S}

t_{EBSWD_H}

Data Setup Time

Data Hold Time

Synchronous Read

t_{EBSR_CO}

t_{EBSRAD_S}

t_{EBSRAD_H}

t_EBSRCPW

t_{EBSRCE_S}

t_{EBSRCE_H}

Clock to Data Delay

—

0.10

-0.07

3.16

-1.76

1.64

-0.18

0.12

—

2.04

—

0.10

-0.07

3.40

-1.71

1.69

-0.17

0.12

—

2.19

—

0.12

-0.06

3.91

-1.45

1.94

-0.14

0.14

—

2.52

—

ns

Address Setup Delay

Address Hold Delay

Clock Pulse Width

—

Clock Enable Setup Time

Clock Enable Hold Time

—

t_{EBSRWE_S}Write Enable Setup Time

—

t_{EBSRWE_H}Write Enable Hold Time

—

t_EBSRWEENWrite Enable to Data Enable Time

t_EBSRWEDISWrite Enable to Data Disable Time

1.02

0.99

1.02

0.83

1.05

1.02

1.05

0.86

1.21

1.17

1.21

0.99

—

t_EBSREN

t_EBSRDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

—

Asynchronous Read

t_EBARADOAddress to New Valid Data Delay

t_{EBARAD_H}Address to Previous Valid Data Delay

—

2.39

2.10

1.01

0.98

1.02

0.83

—

2.46

2.17

1.04

1.01

1.05

0.86

—

2.83

2.50

1.20

1.16

1.21

0.99

ns

t_EBARWEENWrite Enable to Data Enable Time

t_EBARWEDISWrite Enable to Data Disable Time

t_EBAREN

t_EBARDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

ns

1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.

Timing v.0.3

36

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders

-5¹

-4

-3

Base

Parameter

Optional Adders

t_IOINDLY

Description

Input Delay

Parameter Min. Max. Min. Max. Min. Max. Units

—

4.84

—

5.2

—

5.98

ns

t_IOIInput Adjusters

LVTTL_in

Using 3.3V TTL

t_IOIN

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

ns

LVCMOS_18_in

LVCMOS_25_in

LVCMOS_33_in

AGP_1X_in

CTT25_in

Using 1.8V CMOS

Using 2.5V CMOS

Using 3.3V CMOS

Using AGP 1x

Using CTT 2.5V

CTT33_in

Using CTT 3.3V

GTL+_in

Using GTL+

HSTL_I_in

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

HSTL_III_in

LVDS_in

Using Low Voltage

Differential Signaling (LVDS)

BLVDS_in

Using Bus Low Voltage

Differential Signaling (BLVDS)

t_IOIN

—

0.8

—

0.8

—

0.8

ns

LVPECL_in

PCI_in

Using Low Voltage PECL

Using PCI

t_IOIN

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

ns

SSTL2_I_in

SSTL2_II_in

SSTL3_I_in

SSTL3_II_in

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t_IOOOutput Adjusters

Slow Slew

Using Slow Slew (LVTTL and t_IOBUF, t_IOEN

LVCMOS Outputs only)

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

ns

LVTTL_out

Using 3.3V TTL Drive

t_{IOBUF, IOEN,}

t

t_IODIS

LVCMOS_18_4mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33mA Drive t_IODIS

LVCMOS_18_8mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_18_12mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_4mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33 mA Drive t_IODIS

LVCMOS_25_8mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_25_12mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_16mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

37

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders (Cont.)

-5¹

Parameter Min. Max. Min. Max. Min. Max. Units

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

4mA Drive t_IODIS

_IOBUF,t_IOEN,

t_IODIS

-4

-3

Base

Parameter

Description

LVCMOS_33_4mA_out

t

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

ns

LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,

5.33mA Drive

t

LVCMOS_33_8mA_out

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_33_12mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_33_16mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

LVCMOS_33_24mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

24mA Drive

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

AGP_1X_out

CTT25_out

CTT33_out

GTL+_out

Using AGP 1x Standard

t

Using CTT 2.5V

t

Using CTT 3.3V

t

Using GTL+

t

HSTL_I_out

HSTL_III_out

LVDS_out

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

t

Using Low Voltage Differen-

tial Signaling (LVDS)

t

BLVDS_out

LVPECL_out

PCI_out

Using Bus Low Voltage Differ- t_IOBUF,t_IOEN,

ential Signaling (BLVDS)

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

Using Low Voltage PECL

t

Using PCI Standard

t

SSTL2_I_out

SSTL2_II_out

SSTL3_I_out

SSTL3_II_out

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t

1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.

Timing v.0.3

38

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC External Switching Characteristics

Over Recommended Operating Conditions

-5¹

Min. Max. Min. Max. Min. Max. Units

-4

-3

Parameter

Description

Conditions

Global Clock Input to Out- PIO Output Register

put

t_CO

—

-2.9

3.6

6.4

—

-2.7

3.9

6.9

—

-2.3

4.5

7.9

—

ns

PIO Input Register without input

delay

t_S

Global Clock Input Setup

Global Clock Input Hold

PIO Input Register without input

delay

t_H

t_SINDLY

t_HINDLY

t_COPLL

—

ns

Global Clock Input Setup PIO Input Register with input delay 3.3

—

3.6

0.0

—

4.1

0.0

—

Global Clock Input Hold

PIO Input Register with input delay 0.0

Global Clock Input to

Output

PIO Output Register using PLL

without delay

—

3.2

—

0.2

0.9

7.2

-4.0

3.4

—

0.3

1.0

8.3

-3.4

3.9

—

ns

PIO Input Register without input

0.1

t_SPLL

Global Clock Input Setup

Global Clock Input Hold

delay using PLL without delay

PIO Input Register without input

0.8

t_HPLL

delay using PLL without delay

PIO Input Register with input delay

6.7

t_SINDLYPLLGlobal Clock Input Setup

t_HINDLYPLLGlobal Clock Input Hold

using PLL without delay

PIO Input Register with input delay

-4.3

ns

using PLL without delay

1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.

Timing v.0.3

39

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Functional Delays

LUTs

Description

Min. Max. Min. Max. Min. Max. Units

t_LUT4

t_LUT5

t_LUT6

4-Input LUT Delay

—

0.41

0.73

0.86

—

0.44

0.79

0.93

—

0.51

0.91

1.07

ns

5-Input LUT Delay

6-Input LUT Delay

Shift Register (LUT)

t_{LSR_S}

t_{LSR_H}

t_{LSR_CO}

Shift Register Setup Time

Shift Register Hold Time

Shift Register Clock to Output Delay

-0.64

0.61

—

-0.62

0.63

—

-0.53

0.72

—

ns

0.70

0.75

0.86

Arithmetic Functions

t_LCTHRURMC (Macro Cell) Carry In to MC Carry Out Delay (Ripple)

—

0.08

0.05

0.42

0.29

0.36

0.26

—

0.09

0.05

0.45

0.31

0.39

0.28

—

0.10

0.06

0.52

0.36

0.45

0.32

ns

2

t_LCTHRUL

t_LSTHRU

MC Carry In to MC Carry Out Delay (Look Ahead)

MC Sum In to MC Sum Out Delay

t_LSINCOUT

MC Sum In to MC Carry Out Delay

t_LCINSOUTRMC Carry In to MC Sum Out Delay (Ripple)

t_LCINSOUTLMC Carry In to MC Sum Out Delay (Look Ahead)

Feed-thru

t_LFT

PFU Feed-Thru Delay

—

0.15

—

0.16

—

0.18

ns

Distributed RAM

t_{LRAM_CO}

t_{LRAMAD_S}

t_{LRAMD_S}

Clock to RAM Output

—

1.24

—

1.33

—

1.53

—

ns

Address Setup Time

Data Setup Time

-0.41

0.21

0.45

0.58

0.11

0.12

2.91

—

-0.40

0.22

0.46

0.60

0.11

0.12

3.00

—

-0.34

0.25

0.53

0.69

0.13

0.14

3.45

—

t_{LRAMWE_S}Write Enable Setup Time

—

t_{LRAMAD_H}

t_{LRAMD_H}

Address Hold Time

Data Hold Time

—

t_{LRAMWE_H}Write Enable Hold Time

t_LRAMCPWClock Pulse Width (High or Low)

t_LRAMADOAddress to Output Delay

—

0.86

0.93

1.07

Register/Latch Delays

Registers

t_{L_CO}

t_{L_S}

Register Clock to Output Delay

—

0.58

—

0.62

—

0.71

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

0.14

-0.12

-0.11

0.11

0.14

-0.12

-0.11

0.11

0.16

-0.10

-0.09

0.13

t_{L_H}

—

t_{LCE_S}

t_{LCE_H}

Latches

t_{L_GO}

t_{LL_S}

—

Latch Gate to Output Delay

Latch Setup Time

—

0.14

-0.12

—

0.09

—

0.14

-0.12

—

0.10

—

0.16

-0.10

—

0.12

—

ns

t_{LL_H}

Latch Hold Time

—

t_LLPD

Latch Propagation Delay (Transparent Mode)

0.09

0.10

0.12

40

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Reset/Set

t_LASSRO

Description

Min. Max. Min. Max. Min. Max. Units

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery

Synchronous Set/Reset Setup Time

Synchronous Set/Reset Hold Time

—

4.19

—

1.09

—

4.50

—

1.17

—

5.18

—

1.35

—

ns

t_LASSRPW

t_LASSRR

0.51

—

0.55

—

0.63

—

t_{LSSR_S}

-0.03

0.03

-0.03

0.03

-0.03

0.03

t_{LSSR_H}

—

ns

1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.

2. t_LCTHRULquoted bit by bit.

Timing v.0.3

ispXPGA 500B/C & ispXPGA 500EB/EC PIC Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Register/Latch Delays

t_{IO_CO}

t_{IO_S}

Register Clock to Output Delay

—

0.05

0.06

-0.03

0.13

—

1.00

—

0.05

0.06

-0.03

0.13

—

1.07

—

0.06

0.07

-0.03

0.15

—

1.23

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

Latch Gate to Output Delay

t_{IO_H}

—

t_{IOCE_S}

t_{IOCE_H}

t_{IO_GO}

t_{IOL_S}

—

0.78

—

0.84

—

0.97

—

Latch Setup Time

0.05

0.06

—

0.05

0.06

—

0.06

0.07

—

t_{IOL_H}

Latch Hold Time

—

t_IOLPD

t_IOASRO

t_IOASRPW

t_IOASRR

Latch Propagation Delay (Transparent Mode)

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery Time

0.09

1.11

—

0.10

1.19

—

0.12

1.37

—

4.19

—

4.50

—

5.18

—

0.23

0.25

0.29

Input/Output Delays

t_IOBUFOutput Buffer Delay

t_IOIN

—

0.98

0.65

0.52

-0.12

0.19

—

1.05

0.70

0.56

-0.11

0.20

—

1.21

0.81

0.64

-0.09

0.23

ns

Input Buffer Delay

Output Enable Delay

Output Disable Delay

Feed-thru Delay

t_IOEN

t_IODIS

t_IOFT

1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.

Timing v.0.3

41

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC EBR Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Synchronous Write

t_{EBSWAD_S}Address Setup Delay

t_{EBSWAD_H}Address Hold Delay

0.59

-0.40

3.16

-0.12

0.16

0.27

-0.27

—

0.61

-0.39

3.40

-0.12

0.16

0.28

-0.26

—

0.70

-0.33

3.91

-0.10

0.18

0.32

-0.22

—

ns

t_EBSWCPW

Clock Pulse Width

t_{EBSWWE_S}Write Enable Setup Time

t_{EBSWWE_H}Write Enable Hold Time

t_{EBSWD_S}

t_{EBSWD_H}

Data Setup Time

Data Hold Time

Synchronous Read

t_{EBSR_CO}

t_{EBSRAD_S}

t_{EBSRAD_H}

t_EBSRCPW

t_{EBSRCE_S}

t_{EBSRCE_H}

Clock to Data Delay

—

0.10

-0.07

3.16

-1.76

1.64

-0.18

0.12

—

2.04

—

0.10

-0.07

3.40

-1.71

1.69

-0.17

0.12

—

2.19

—

0.12

-0.06

3.91

-1.45

1.94

-0.14

0.14

—

2.52

—

ns

Address Setup Delay

Address Hold Delay

Clock Pulse Width

—

Clock Enable Setup Time

Clock Enable Hold Time

—

t_{EBSRWE_S}Write Enable Setup Time

—

t_{EBSRWE_H}Write Enable Hold Time

—

t_EBSRWEENWrite Enable to Data Enable Time

t_EBSRWEDISWrite Enable to Data Disable Time

1.02

0.99

1.02

0.83

1.05

1.02

1.05

0.86

1.21

1.17

1.21

0.99

—

t_EBSREN

t_EBSRDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

—

Asynchronous Read

t_EBARADOAddress to New Valid Data Delay

t_{EBARAD_H}Address to Previous Valid Data Delay

—

2.39

2.10

1.01

0.98

1.02

0.83

—

2.46

2.17

1.04

1.01

1.05

0.86

—

2.83

2.50

1.20

1.16

1.21

0.99

ns

t_EBARWEENWrite Enable to Data Enable Time

t_EBARWEDISWrite Enable to Data Disable Time

t_EBAREN

t_EBARDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

ns

1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.

Timing v.0.3

42

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders

-5¹

-4

-3

Base

Parameter

Optional Adders

t_IOINDLY

Description

Input Delay

Parameter Min. Max. Min. Max. Min. Max. Units

—

5.21

—

5.60

—

6.44

ns

t_IOIInput Adjusters

LVTTL_in

Using 3.3V TTL

t_IOIN

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

ns

LVCMOS_18_in

LVCMOS_25_in

LVCMOS_33_in

AGP_1X_in

CTT25_in

Using 1.8V CMOS

Using 2.5V CMOS

Using 3.3V CMOS

Using AGP 1x

Using CTT 2.5V

CTT33_in

Using CTT 3.3V

GTL+_in

Using GTL+

HSTL_I_in

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

HSTL_III_in

LVDS_in

Using Low Voltage

Differential Signaling (LVDS)

BLVDS_in

Using Bus Low Voltage

Differential Signaling (BLVDS)

t_IOIN

—

0.8

—

0.8

—

0.8

ns

LVPECL_in

PCI_in

Using Low Voltage PECL

Using PCI

t_IOIN

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

ns

SSTL2_I_in

SSTL2_II_in

SSTL3_I_in

SSTL3_II_in

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t_IOOOutput Adjusters

Slow Slew

Using Slow Slew (LVTTL and t_IOBUF, t_IOEN

LVCMOS Outputs only)

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

ns

LVTTL_out

Using 3.3V TTL Drive

t_{IOBUF, IOEN,}

t

t_IODIS

LVCMOS_18_4mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33mA Drive t_IODIS

LVCMOS_18_8mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_18_12mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_4mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33 mA Drive t_IODIS

LVCMOS_25_8mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_25_12mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_16mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

43

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders (Cont.)

-5¹

Parameter Min. Max. Min. Max. Min. Max. Units

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

4mA Drive t_IODIS

_IOBUF,t_IOEN,

t_IODIS

-4

-3

Base

Parameter

Description

LVCMOS_33_4mA_out

t

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

ns

LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,

5.33mA Drive

t

LVCMOS_33_8mA_out

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_33_12mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_33_16mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

LVCMOS_33_24mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

24mA Drive

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

AGP_1X_out

CTT25_out

CTT33_out

GTL+_out

Using AGP 1x Standard

t

Using CTT 2.5V

t

Using CTT 3.3V

t

Using GTL+

t

HSTL_I_out

HSTL_III_out

LVDS_out

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

t

Using Low Voltage Differen-

tial Signaling (LVDS)

t

BLVDS_out

LVPECL_out

PCI_out

Using Bus Low Voltage Differ- t_IOBUF,t_IOEN,

ential Signaling (BLVDS)

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

Using Low Voltage PECL

t

Using PCI Standard

t

SSTL2_I_out

SSTL2_II_out

SSTL3_I_out

SSTL3_II_out

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t

1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.

Timing v.0.3

44

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC External Switching

Characteristics

Over Recommended Operating Conditions

-5¹

Min. Max. Min. Max. Min. Max. Units

-4

-3

Parameter

Description

Conditions

Global Clock Input to Out- PIO Output Register

put

t_CO

—

-2.7

4.5

6.6

—

-2.7

4.6

7.1

—

-2.3

5.3

8.2

—

ns

PIO Input Register without input

delay

t_S

Global Clock Input Setup

Global Clock Input Hold

PIO Input Register without input

delay

t_H

t_SINDLY

t_HINDLY

t_COPLL

—

ns

Global Clock Input Setup PIO Input Register with input delay 3.8

—

3.8

0.0

—

4.4

0.0

—

Global Clock Input Hold

PIO Input Register with input delay 0.0

Global Clock Input to

Output

PIO Output Register using PLL

without delay

—

3.1

—

0.5

0.8

7.6

-4.0

3.3

—

0.6

1.0

8.8

-3.4

3.8

—

ns

PIO Input Register without input

0.5

t_SPLL

Global Clock Input Setup

Global Clock Input Hold

delay using PLL without delay

PIO Input Register without input

0.8

t_HPLL

delay using PLL without delay

PIO Input Register with input delay

7.6

t_SINDLYPLLGlobal Clock Input Setup

t_HINDLYPLLGlobal Clock Input Hold

using PLL without delay

PIO Input Register with input delay

-4.1

ns

using PLL without delay

1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.

Timing v.0.2

45

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Functional Delays

LUTs

Description

Min. Max. Min. Max. Min. Max. Units

t_LUT4

t_LUT5

t_LUT6

4-Input LUT Delay

—

0.41

0.73

0.86

—

0.44

0.79

0.93

—

0.51

0.91

1.07

ns

5-Input LUT Delay

6-Input LUT Delay

Shift Register (LUT)

t_{LSR_S}

t_{LSR_H}

t_{LSR_CO}

Shift Register Setup Time

Shift Register Hold Time

Shift Register Clock to Output Delay

-0.64

0.61

—

-0.62

0.63

—

-0.53

0.72

—

ns

0.70

0.75

0.86

Arithmetic Functions

t_LCTHRURMC (Macro Cell) Carry In to MC Carry Out Delay (Ripple)

—

0.08

0.05

0.42

0.29

0.36

0.26

—

0.09

0.05

0.45

0.31

0.39

0.28

—

0.10

0.06

0.52

0.36

0.45

0.32

ns

2

t_LCTHRUL

t_LSTHRU

MC Carry In to MC Carry Out Delay (Look Ahead)

MC Sum In to MC Sum Out Delay

t_LSINCOUT

MC Sum In to MC Carry Out Delay

t_LCINSOUTRMC Carry In to MC Sum Out Delay (Ripple)

t_LCINSOUTLMC Carry In to MC Sum Out Delay (Look Ahead)

Feed-thru

t_LFT

PFU Feed-Thru Delay

—

0.15

—

0.16

—

0.18

ns

Distributed RAM

t_{LRAM_CO}

t_{LRAMAD_S}

t_{LRAMD_S}

Clock to RAM Output

—

1.24

—

1.33

—

1.53

—

ns

Address Setup Time

Data Setup Time

-0.41

0.21

0.45

0.58

0.11

0.12

2.91

—

-0.40

0.22

0.46

0.60

0.11

0.12

3.00

—

-0.34

0.25

0.53

0.69

0.13

0.14

3.45

—

t_{LRAMWE_S}Write Enable Setup Time

—

t_{LRAMAD_H}

t_{LRAMD_H}

Address Hold Time

Data Hold Time

—

t_{LRAMWE_H}Write Enable Hold Time

t_LRAMCPWClock Pulse Width (High or Low)

t_LRAMADOAddress to Output Delay

—

0.86

0.93

1.07

Register/Latch Delays

Registers

t_{L_CO}

t_{L_S}

Register Clock to Output Delay

—

0.58

—

0.62

—

0.71

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

0.14

-0.12

-0.11

0.11

0.14

-0.12

-0.11

0.11

0.16

-0.10

-0.09

0.13

t_{L_H}

—

t_{LCE_S}

t_{LCE_H}

Latches

t_{L_GO}

t_{LL_S}

—

Latch Gate to Output Delay

Latch Setup Time

—

0.14

-0.12

—

0.09

—

0.14

-0.12

—

0.10

—

0.16

-0.10

—

0.12

—

ns

t_{LL_H}

Latch Hold Time

—

t_LLPD

Latch Propagation Delay (Transparent Mode)

0.09

0.10

0.12

46

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5¹

-4

-3

Parameter

Reset/Set

t_LASSRO

Description

Min. Max. Min. Max. Min. Max. Units

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery

Synchronous Set/Reset Setup Time

Synchronous Set/Reset Hold Time

—

4.19

—

1.09

—

4.50

—

1.17

—

5.18

—

1.35

—

ns

t_LASSRPW

t_LASSRR

0.51

—

0.55

—

0.63

—

t_{LSSR_S}

-0.03

0.03

-0.03

0.03

-0.03

0.03

t_{LSSR_H}

—

ns

1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.

2. t_LCTHRULquoted bit by bit.

Timing v.2.1

ispXPGA 1200B/C & ispXPGA 1200EB/EC PIC Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Register/Latch Delays

t_{IO_CO}

t_{IO_S}

Register Clock to Output Delay

—

0.05

0.06

-0.03

0.13

—

1.01

—

0.05

0.06

-0.03

0.13

—

1.09

—

0.06

0.07

-0.03

0.15

—

1.25

—

ns

Register Setup Time (Data before Clock)

Register Hold Time (Data after Clock)

Register Clock Enable Setup Time

Register Clock Enable Hold Time

Latch Gate to Output Delay

t_{IO_H}

—

t_{IOCE_S}

t_{IOCE_H}

t_{IO_GO}

t_{IOL_S}

—

0.85

—

0.91

—

1.05

—

Latch Setup Time

0.05

0.06

—

0.05

0.06

—

0.06

0.07

—

t_{IOL_H}

Latch Hold Time

—

t_IOLPD

t_IOASRO

t_IOASRPW

t_IOASRR

Latch Propagation Delay (Transparent Mode)

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Pulse Width

Asynchronous Set/Reset Recovery Time

0.09

1.17

—

0.10

1.26

—

0.12

1.45

—

4.19

—

4.50

—

5.18

—

0.23

0.25

0.29

Input/Output Delays

t_IOBUFOutput Buffer Delay

t_IOIN

—

0.99

0.71

0.52

-0.11

0.19

—

1.06

0.76

0.56

-0.10

0.20

—

1.22

0.87

0.64

-0.09

0.23

ns

Input Buffer Delay

Output Enable Delay

Output Disable Delay

Feed-thru Delay

t_IOEN

t_IODIS

t_IOFT

1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.

Timing v.2.1

47

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC EBR Timing Parameters

-5¹

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Synchronous Write

t_{EBSWAD_S}Address Setup Delay

t_{EBSWAD_H}Address Hold Delay

0.59

-0.40

3.16

-0.12

0.16

0.27

-0.27

—

0.61

-0.39

3.40

-0.12

0.16

0.28

-0.26

—

0.70

-0.33

3.91

-0.10

0.18

0.32

-0.22

—

ns

t_EBSWCPW

Clock Pulse Width

t_{EBSWWE_S}Write Enable Setup Time

t_{EBSWWE_H}Write Enable Hold Time

t_{EBSWD_S}

t_{EBSWD_H}

Data Setup Time

Data Hold Time

Synchronous Read

t_{EBSR_CO}

t_{EBSRAD_S}

t_{EBSRAD_H}

t_EBSRCPW

t_{EBSRCE_S}

t_{EBSRCE_H}

Clock to Data Delay

—

0.10

-0.07

3.16

-1.76

1.64

-0.18

0.12

—

2.04

—

0.10

-0.07

3.40

-1.71

1.69

-0.17

0.12

—

2.19

—

0.12

-0.06

3.91

-1.45

1.94

-0.14

0.14

—

2.52

—

ns

Address Setup Delay

Address Hold Delay

Clock Pulse Width

—

Clock Enable Setup Time

Clock Enable Hold Time

—

t_{EBSRWE_S}Write Enable Setup Time

—

t_{EBSRWE_H}Write Enable Hold Time

—

t_EBSRWEENWrite Enable to Data Enable Time

t_EBSRWEDISWrite Enable to Data Disable Time

1.02

0.99

1.02

0.83

1.05

1.02

1.05

0.86

1.21

1.17

1.21

0.99

—

t_EBSREN

t_EBSRDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

—

Asynchronous Read

t_EBARADOAddress to New Valid Data Delay

t_{EBARAD_H}Address to Previous Valid Data Delay

—

2.39

2.10

1.01

0.98

1.02

0.83

—

2.46

2.17

1.04

1.01

1.05

0.86

—

2.83

2.50

1.20

1.16

1.21

0.99

ns

t_EBARWEENWrite Enable to Data Enable Time

t_EBARWEDISWrite Enable to Data Disable Time

t_EBAREN

t_EBARDIS

Output Enable to Data Enable Time

Output Enable to Data Disable Time

ns

1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.

Timing v.2.1

48

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders

-5¹

-4

-3

Base

Parameter

Optional Adders

t_IOINDLY

Description

Input Delay

Parameter Min. Max. Min. Max. Min. Max. Units

—

5.58

—

6.0

—

6.90

ns

t_IOIInput Adjusters

LVTTL_in

Using 3.3V TTL

t_IOIN

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

—

0.5

0.0

0.3

0.5

1.0

0.5

0.8

ns

LVCMOS_18_in

LVCMOS_25_in

LVCMOS_33_in

AGP_1X_in

CTT25_in

Using 1.8V CMOS

Using 2.5V CMOS

Using 3.3V CMOS

Using AGP 1x

Using CTT 2.5V

CTT33_in

Using CTT 3.3V

GTL+_in

Using GTL+

HSTL_I_in

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

HSTL_III_in

LVDS_in

Using Low Voltage

Differential Signaling (LVDS)

BLVDS_in

Using Bus Low Voltage

Differential Signaling (BLVDS)

t_IOIN

—

0.8

—

0.8

—

0.8

ns

LVPECL_in

PCI_in

Using Low Voltage PECL

Using PCI

t_IOIN

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

—

0.8

1.0

0.8

0.5

0.8

ns

SSTL2_I_in

SSTL2_II_in

SSTL3_I_in

SSTL3_II_in

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t_IOOOutput Adjusters

Slow Slew

Using Slow Slew (LVTTL and t_IOBUF, t_IOEN

LVCMOS Outputs only)

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

—

0.7

1.0

0.8

0.6

0.0

0.2

0.7

0.5

ns

LVTTL_out

Using 3.3V TTL Drive

t_{IOBUF, IOEN,}

t

t_IODIS

LVCMOS_18_4mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33mA Drive t_IODIS

LVCMOS_18_8mA_out

Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_18_12mA_out Using 1.8V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_4mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

4mA Drive t_IODIS

LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

5.33 mA Drive t_IODIS

LVCMOS_25_8mA_out

Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_25_12mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_25_16mA_out Using 2.5V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

49

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders (Cont.)

-5¹

Parameter Min. Max. Min. Max. Min. Max. Units

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

4mA Drive t_IODIS

_IOBUF,t_IOEN,

t_IODIS

-4

-3

Base

Parameter

Description

LVCMOS_33_4mA_out

t

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

—

1.0

0.7

0.5

1.0

0.5

ns

LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,

5.33mA Drive

t

LVCMOS_33_8mA_out

Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

8mA Drive t_IODIS

LVCMOS_33_12mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

12mA Drive t_IODIS

LVCMOS_33_16mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

16mA Drive t_IODIS

LVCMOS_33_24mA_out Using 3.3V CMOS Standard, t_{IOBUF, IOEN,}

t

24mA Drive

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

AGP_1X_out

CTT25_out

CTT33_out

GTL+_out

Using AGP 1x Standard

t

Using CTT 2.5V

t

Using CTT 3.3V

t

Using GTL+

t

HSTL_I_out

HSTL_III_out

LVDS_out

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

t

Using Low Voltage Differen-

tial Signaling (LVDS)

t

BLVDS_out

LVPECL_out

PCI_out

Using Bus Low Voltage Differ- t_IOBUF,t_IOEN,

ential Signaling (BLVDS)

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

t_{IOBUF, IOEN,}

t_IODIS

Using Low Voltage PECL

t

Using PCI Standard

t

SSTL2_I_out

SSTL2_II_out

SSTL3_I_out

SSTL3_II_out

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

t

1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.

Timing v.2.1

50

Lattice Semiconductor

ispXPGA Family Data Sheet

sysHSI Block Timing

Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on

a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N

input skew tolerance.

Figure 24. Receive Data Eye Diagram Template (Differential)

Bit Time

V_THD

200 mV Differential

+/- 100 mV Single Ended

jt_TH

eo_SIN

jt_TH

jt_TH: Optimum Threshold Crossing Jitter

The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal

quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye

closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s

ability to transfer error-free data.

Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital

links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery

(CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the clock

recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data

error free, with eye openings significantly less than that shown in Figure 24.

51

Lattice Semiconductor

ispXPGA Family Data Sheet

sysHSI Block AC Specifications

Operating Frequency Ranges

Test

-5¹

-4

-3

Symbol

Description

Mode

Condition

Device

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

LFX125B/C

LFX200B/C

LFX500B/C

LFX1200B/C

Min. Max. Min. Max. Min. Max. Units

50

200

188

175

67

50

200

188

175

67

50

200

188

175

67

SS:CAL

MHz

50

33

63

33

63

33

63

Reference Clock

Frequency

f_CLK

10B12B

8B10B

SS:CAL

10B12B

8B10B

LVDS

33

63

33

63

33

63

33

58

33

58

33

58

40

80

40

80

40

80

40

75

40

75

40

75

MHz

40

75

40

75

40

75

40

70

40

70

40

70

400

800

750

700

800

750

700

800

750

700

800

750

700

400

800

750

700

800

750

700

800

750

700

800

750

700

400

800

750

700

800

750

700

800

750

700

800

750

700

with eoSIN

Mbps

2

f_SIN

Serial Input

CL = 5 pF,

RL = 100¾

2

f_OUT

Serial Out

f

_CLKwith no jit-

ter

1. Only available for ispXPGA 125B, 200B, 500B and 1200B (2.5V/3.3V) devices.

2. f_SINand f_SOUTspeeds are supported at V_CCand V_CCPat 1.7V to 1.9V for ispXPGA 1.8V devices.

LOCKIN Time

Symbol

t_SCLOCK

Description

CSPLL Lock Time

Mode

All

Condition

Min

Max

Unit

After input is stabilized

25

S

1

SS

With SS mode sync pattern

1024

960

t_RCP

t_CDRLOCK

CDRPLL Lock-in Time

10B12B With 10B12B sync pattern

t_RCP

8B10B

SS

With 8B10B idle pattern

t_SYNC

SyncPat Length

1200

1100

50

t_CAL

CAL Duration

SS

t_SUSYNC

t_HDSYNC

SyncPat Set-up Time to CAL

SyncPat Hold Time from CAL

SS

50

1. REFCLK clock period.

52

Lattice Semiconductor

ispXPGA Family Data Sheet

REFCLK and SS_CLKIN Timing

Symbol

t_DREFCLK

t_JPPREFCLK

Description

Mode

Condition

Min

Max

100

Unit

Frequency Deviation Between TX REFCLK and

CDRX REFCLK on One Link

8B10B/

10B12B

-100

ppm

REFCLK, SS_CLKIN Peak-to-Peak Period Jitter

All

Random Jitter

40-100MHz

0.01

UIPP

ns

REFCLK, SS_CLKIN Pulse Width, (80% to 80% or

20% to 20%).

2

1

t_PWREFCLK

All

100-200MHz

REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or

80% to 20%)

t_RFREFCLK

All

2

ns

Serializer Timing²

Symbol

Description

Mode

All

Condition

Min

Max

Unit

UIPP

ps

t_JPPSOUT

t_JPP8B10B

t_RFSOUT

t_COSOUT

SOUT Peak-to-Peak Output Data Jitter

SOUT Peak-to-Peak Random Jitter

SOUT Peak-to-Peak Deterministic Jitter

f_CLKwith no jitter

0.25

130

160

8B10B

800 Mbps w/K28.7-

8B10B 800 Mbps w/K28.5+

ps

SOUT Output Data Rise/Fall Time (20%,

80%)

LVDS

700

ps

SS/8B10B

10B12B

2Bt¹+ 2

1Bt¹+ 2

2Bt¹+10

1Bt¹+10

ns

REFCLK to SOUT Delay

Skew of SOUT with Respect to

SS_CLKOUT

t_SKTX

SS

300

ps

t_CKOSOUT

SS_CLKOUT to bit0 of SOUT

SS

2Bt¹- t_SKTX2Bt¹+ t_SKTX

ns

t_HSITXDDATASTXD Data Setup Time

t_HSITXDDATAHTXD Data Hold Time

All

Note 3

1.5

1.0

1. Bt: Bit Time Period. High Speed Serial Bit Time.

2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in

sysCLOCK PLL BYPASS mode.

3. Internal timing for reference only.

Deserializer Timing

Symbol

f_DSIN

Description

Mode

Conditions

Min

-100

0.45

Max

Units

8B10B/

10B12B

SIN Frequency Deviation from REFCLK

100

ppm

eo_SIN

ber

SIN Eye Opening Tolerance

Bit Error Rate

All

Notes 1, 2

UIPP

Bits

10^-12

RXD, SYDT Valid Time Before RECCLK Fall-

ing Edge

t_{HSIOUTVALIDPRE}

t_{HSIOUTVALIDPOST}

t_DSIN

All

Note 3

t_RCP/2 - 0.7

ns

RXD, SYDT Valid Time

After RECCLK Falling Edge

Bit 0 of SIN Delay to RXD Valid at RECCLK

Falling edge

1.5 t_RCP

+

1.5 t_RCP+

4.5Bt + 15

4.5Bt + 3

1. Eye opening based on jitter frequency of 100KHz.

2. Lower frequency operation assumes maximum eye closure of 800ps.

3. Internal timing for reference only.

53

Lattice Semiconductor

Lock-in Timing

ispXPGA Family Data Sheet

CDRX_SS LOCK-IN (DE-SKEW) TIMING

SIN

MIN. 1200 SYNCPAT

MIN. 1100 LS CYCLE

DATA (SERIAL)

CAL

t_HDSYNC

t_SUSYNC

SYDT

RXD(0:7)

SYNCPAT

TRAINING SEQUENCE

DATA (PARALLEL)

SS MODE DATA TRANSFER

CDR_10B12B LOCK-IN TIMING

SIN

1024 SYNCPAT

DATA (SERIAL)

SYDT

RXD(0:9)

SYNCPAT

DATA (PARALLEL)

CDR_8B10B LOCK-IN TIMING

SIN

240 Idle Pattern(960 TRCP)

DATA (SERIAL)

SYDT

RXD(0:9)

Idle Pattern

DATA (PARALLEL)

SYDT Timing

SYDT TIMING FOR CDRX_10B12B

RECCLK

SYDT

RXD(0:9)

Data0 Data1 Data2 Data3 Data4

Parallel Data

SYNC PATTERN

SYDT TIMING FOR CDRX_8B10B

RECCLK

SYDT

RXD(0:9)

K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5

D0

D2

D1

IDLE PATTERN

Data

54

Lattice Semiconductor

Serializer Timing

ispXPGA Family Data Sheet

8B/10B SERIALIZER DELAY TIMING

SYMBOL N

t_COSOUT

SYMBOL N+1

TXD

REFCLK

SOUT

b4

b4 b5 b6 b7 b8 b9 b0 b1 b2 b3

b5 b6 b7 b8 b9 b0 b1 b2

SYMBOL N

SYMBOL N-1

SYMBOL N+1

10B/12B SERIALIZER DELAY TIMING

SYMBOL N

t_COSOUT

SYMBOL N+1

TXD

REFCLK

SOUT

b4

b5 b6 b7 b8 b9

"0" "1"

b4 b5 b6 b7 b8 b9

SYMBOL N-1

b0 b1 b2 b3

"0"

"1"

SYMBOL N

SS Mode SERIALIZER DELAY TIMING

SYMBOL N

SYMBOL N+1

TXD

t_COSOUT

REFCLK

SS_CLKOUT

SOUT

t_CKOSOUT

t_SKTX

b4

b5

b6

b7

b0

b2

SYMBOL N

b5

b1

b3

b6

b7

b0

SYMBOL

N+1

SYMBOL N-1

INTERNAL TIMING FOR sysHSI BLOCK

RECCLK

t_{HSIOUTVALIDPRE}

t_{HSIOUTVALIDPOST}

SYDT, RXD

55

Lattice Semiconductor

Deserializer Timing

ispXPGA Family Data Sheet

8B/10B DESERIALIZER DELAY TIMING

SYMBOL N+1

b4

SYMBOL N

SYMBOL N+2

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3

T_DSIN

b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5

SIN

RECCLK

RXD

SYMBOL N

SYMBOL N-1

10B/12B DESERIALIZER DELAY TIMING

SYMBOL N+2

SYMBOL N

b0 b1 b2 b3 b4 b5

SYMBOL N+1

SIN

b8 b9

b6 b7

"0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9

b4

"1"

"0" "1" b0 b1 b2 b3

T_TDSIN

RECCLK

RXD

SYMBOL N-1

SYMBOL N-2

SYMBOL N

CDRX_SS DESERIALIZER DELAY TIMING

SYMBOL N

SYMBOL N+2

SYMBOL N+1

b7

b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6

T_DSIN

b0 b1 b2 b3 b4

SIN

RECCLK

RXD

SYMBOL N-2

SYMBOL N

SYMBOL N-1

INTERNAL TIMING FOR sysHSI BLOCK

T_PWREFCLK

REFCLK

TXD

t_HSITXDDATAS

t_HSITXDDATAH

56

Lattice Semiconductor

ispXPGA Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Symbol

t_PWH

Parameter

Conditions

Min

1.2

—

Max

—

Units

ns

Input clock, high time

80% to 80%

20% to 20%

20% to 80%

t_PWL

Input clock, low time

—

ns

t_R, t_F

Input Clock, rise and fall time

Input clock stability, cycle to cycle (peak)

M Divider input, frequency range

M Divider output, frequency range

N Divider input, frequency range

N Divider output, frequency range

V Divider input, frequency range

V Divider output, frequency range

output clock, duty cycle

3.0

ns

t_INSTB

—

+/- 250

320

400

320

60

ps

f_MDIVIN

f_MDIVOUT

f_NDIVIN

f_NDIVOUT

f_VDIVIN

f_VDIVOUT

t_OUTDUTY

10

MHz

%

10

100

10

40

Clean reference¹

10MHz ð f_MDIVOUTð 40MHz or

100MHz ð f _VDIVINð 160MHz

Clean reference¹

40MHz ð f_MDIVOUTð 320MHz and

160MHz ð f_VDIVINð 400MHz

Clean reference¹

10MHz ð f_MDIVOUTð 40MHz or

100MHz ð f_VDIVINð 160MHz

Clean reference¹

40MHz ð f_MDIVOUTð 320MHz and

160MHz ð f_VDIVINð 400MHz

—

+/- 600

+/- 150

+/- 600

+/- 150

ps

t_JIT(CC)

Output clock, cycle to cycle jitter (peak)

Output clock, period jitter (peak)

2

t_JIT(PER)

t_{CLK_OUT_DELAY}Input clock to CLK_OUT delay

Internal feedback

External feedback

—

3.0

1.5

25

ns

us

ps

ns

t_PHASE

Input clock to external feedback delta

Time to acquire phase lock after input stable

Delay increment (Lead/Lag)

t_LOCK

t_{PLL_DELAY}

t_RANGE

Typical = +/- 250ps

+/- 120 +/- 550

+/- 0.84 +/- 3.85

Total output delay range (lead/lag)

Minimum reset pulse width

t_{PLL_RSTW}

1.8

—

3

t_{CLK_IN}

Global clock input delay

1.0

1.5

t_{PLL_SEC_DELAY}Secondary PLL output delay

—

1. This condition assures that the output phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings

determined by the ispLEVER software.

2. Accumulated jitter measured over 10,000 waveform samples

3. Internal timing for reference only.

57

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXP sysCONFIG Port Timing Specifications

Symbol

Timing Parameter

Min.

Typ.

Max.

Units

sysCONFIG Write Cycle Timing

t_SUCS

t_HCS

t_SUWD

t_HWD

Input setup time of CS to CCLK rise

Hold time of CS to CCLK Rise

Input setup time of write data to CCLK rise

Hold time of write data to CCLK rise

Low time to reset device SRAM

INIT pulse width

10

0

—

50

5

ns

12

0

ns

t_PRGM

t_WINIT

t_IODISS

t_IOENSS

t_WH

5

ns

—

12

—

ms

ns

User I/O disable

30

—

33

User I/O enable

ns

Write clock High pulse width

Write clock Low pulse width

Write f_MAX

ns

t_WL

ns

f_MAXW

MHz

sysCONFIG Read Cycle Timing

t_HREAD

t_SUREAD

t_RH

Hold time of READ to CCLK rise

0

—

33

25

ns

Input setup time of READ High to CCLK rise

READ clock high pulse width

READ clock low pulse width

Read f_MAX

30

12

15

—

ns

t_RL

ns

f_MAXR

t_CORD

MHz

ns

Clock to out for read data

Boundary Scan Timing

Parameter

Description

TCK [BSCAN] Clock Pulse Width

TCK [BSCAN] Clock Pulse Width High

Min.

40

20

8

Max.

Units

ns

t_BTCP

—

18

—

45

20

t_BTCPH

t_BTCPL

t_BTS

ns

TCK [BSCAN] Clock Pulse Width Low

TCK [BSCAN] Setup Time

ns

t_BTH

TCK [BSCAN] Hold Time

10

50

—

8

ns

t_BTRF

TCK [BSCAN] Rise/Fall Time

mV/ns

ns

t_BTCO

TAP Controller Falling Edge of Clock to Valid Output

TAP Controller Falling Edge of Clock to Valid Disable

TAP Controller Falling Edge of Clock to Valid Enable

BSCAN Test Capture Register Setup Time

BSCAN Test Capture Register Hold Time

t_BTCODIS

t_BTCOEN

t_BTCRS

t_BTCRH

t_BUTCO

t_BTUODIS

t_BTUPOEN

ns

25

—

ns

BSCAN Test Update Register, Falling Edge of Clock to Valid Output

BSCAN Test Update Register, Falling Edge of Clock to Valid Disable

BSCAN Test Update Register, Falling Edge of Clock to Valid Enable

ns

58

Lattice Semiconductor

ispXPGA Family Data Sheet

Switching Test Conditions

Figure 25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Table 7.

Figure 25. Output Test Load, LVTTL and LVCMOS Standards

V_CCO

R

1

Test

Point

Device

Output

R

C *

L

2

*C includes test fixture and probe capacitance.

L

Table 7. Text Fixture Required Components

Test Condition

R₁

R₂

C_L

Timing Reference

LVCMOS 3.3 = V_CCO/2

LVCMOS 2.5 = V_CCO/2

LVCMOS 1.8 = V_CCO/2

0.9V

VCCO

LVCMOS 3.3 = 3.0V

LVCMOS 2.5 = 2.3V

LVCMOS 1.8 = 1.65V

1.65V

LVCMOS I/O, (L -> H, H -> L)

106

35pF

Default LVCMOS 1.8 I/O (Z -> H)

Default LVCMOS 1.8 I/O (Z -> L)

Default LVCMOS 1.8 I/O (H -> Z)

Default LVCMOS 1.8 I/O (L -> Z)

×

106

×

35pF

5pF

106

×

0.9V

1.65V

106

×

V_OH- 0.3

1.65V

106

5pF

V_OL+ 0.3

1.65V

Note: Output test conditions for all other interfaces are determined by the respective standards.

59

Lattice Semiconductor

ispXPGA Family Data Sheet

Signal Descriptions¹

Signal Name

Signal Type

Description

General Purpose

BKy_IOx^1,2

GCLKn/In ⁷

GSR

Input/Output General purpose I/O number x in I/O Bank y

Input

—

Global clock/input⁸

Global Set/Reset

NC

No Connect

GND

VCC

Input

Output

Ground

V_CC

Core logic power supply

IEEE 1149.1 TAP power supply

I/O Bank y power supply

I/O Bank y reference voltage

V_CCJ

2

V_CCOy

2

V_REFy

D_XN,D_XP

Temperature Sensing Diodes, provide a differential voltage, which

corresponds to the temperature of the device.

Test and Program/Configuration

TMS

TCK

TDI

Input

Output

Input

Test Mode Select

Test Clock

Test Data In

TDO

TOE

CFG0

Test Data Out

Test Output Enable tri-states all I/O pins when driven low

Selects the SRAM memory configuration type (Peripheral or

E²CMOS Refresh)

PROGRAMb

Input

Initiates download from E²CMOS or the peripheral port to SRAM

memory (active low)

DONE

Bi-directional Indicates when configuration is complete

INITb

Bi-directional Indicates the device is ready for programming (active low)

READ

Input

Selects the READ operation when in sysCONFIG mode

sysCONFIG Configuration Clock

CCLK

CSb

sysCONFIG Chip Select (active low)

DATA[0:7]

Bi-directional sysCONFIG Peripheral Port Data I/O

sysCLOCK PLL³

PLL_FBKz

Input

Optional external feedback

PLL_RSTz

Optional external M divider reset

CLK_OUTz

Internal Signal Clock output (routable to any I/O)

Internal Signal Lock output (routable to any I/O)

PLL_LOCKz

GND_P0

GND

VCC

Left side PLL Ground

GND_P1

Right side PLL Ground

Left side PLL power supply

Right side PLL power supply

V_CCP0

V_CCP1

sysHSI Block^{4, 5}

HSImA_SINP, HSImB_SINP

HSImA_SINN, HSImB_SINN

HSImA_SOUTP, HSImB_SOUTP

HSImA_SOUTN, HSImB_SOUTN

HSImA_SYDT, HSImB_SYDT

HSImA_RECCLK, HSImB_RECCLK

Input

P-side of differential serial data input

N-side of differential serial data input

P-side of differential serial data output

N-side of differential serial data output

Output

Internal Signal Symbol alignment detect

Internal Signal Recovered clock

60

Lattice Semiconductor

ispXPGA Family Data Sheet

Signal Descriptions¹(Cont.)

Signal Name

Signal Type

Input

Internal Signal Indicates when the CSPLL circuit is locked

Description

HSImA_CDRRST, HSImB_CDRRST

CDR Reset

HSIm_CSLOCK, HSIm_CSLOCK

sysHSI Block (Source Synchronous Mode)⁶

SS_CLKIN0P, SS_CLKIN1P

SS_CLKIN0N, SS_CLKIN1N

SS_CLKOUT0P, SS_CLKOUT1P

SS_CLKOUT0N, SS_CLKOUT1N

CAL0, CAL1

Input

P-side of differential clock input

N-side of differential clock input

Output

Input

P-side of differential clock output

N-side of differential clock output

Initiates source synchronous calibration sequence

1. x is a variable for the I/O number.

2. y is a variable for the I/O Bank.

3. z is a variable for the PLL number.

4. m is a variable for the sysHSI block number.

5. A and B refer to the sysHSI block channels.

6. 0 and 1 refer to Source Synchronous group 0 and 1

7. n is a variable for the GCLK and Input number

8. See Logic Signal Connections Table for differential pairing.

61

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Power Supply and NC Connections¹

Signal

256-Ball fpBGA³

516-Ball fpBGA³

V_CC

C3, C14, D4, D13, E5, E12, F6, F11, A9, A22, D4, D27, J1, J30, L11, L12, L15, L16, L19, L20, M11, M20, R11,

L6, L11, M5, M12, N4, N13, P3, P14 R20, T11, T20, W11, W20, Y11, Y12, Y15, Y16, Y19, Y20, AB1, AB30, AG4,

AG27, AK9, AK22

V_CCO0F5, G5

V_CCO1K5, L5

F4, J4, M4, N11, P4, P11

U4, U11, V11, W4, AB4, AE4

Y13, Y14, AG6, AG9, AG12, AG14

Y17, Y18, AG17, AG19, AG22, AG25

U20, U27, V20, W27, AB27, AE27

F27, J27, M27, N20, P20, P27

D17, D19, D22, D25, L17, L18

D6, D9, D12, D14, L13, L14

R4, T30

V_CCO2M6, M7

V_CCO3M10, M11

V_CCO4K12, L12

V_CCO5G12, F12

V_CCO6E10, E11

V_CCO7E6, E7

V_CCP

V_CCJ

GND

H3, J15

A2

C4

A1, A16, B2, B15, F7, F8, F9, F10,

A1, A30, B2, B29, C3, C28, M12, M13, M14, M15, M16, M17, M18, M19,

G6, G7, G8, G9, G10, G11, H6, H7, N12, N13, N14, N15, N16, N17, N18, N19, P12, P13, P14, P15, P16, P17,

H8, H9, H10, H11, J6, J7, J8, J9, J10, P18, P19, R12, R13, R14, R15, R16, R17, R18, R19, T12, T13, T14, T15,

J11, K6, K7, K8, K9, K10, K11, L7,

L8, L9, L10, R2, R15, T1, T16

T16, T17, T18, T19, U12, U13, U14, U15, U16, U17, U18, U19, V12, V13,

V14, V15, V16, V17, V18, V19, W12, W13, W14, W15, W16, W17, W18,

W19, AH3, AH28, AJ2, AJ29, AK1, AK30

GND_P

NC²

H15, J4

—

R29, T4

LFX125: A10, A13, A16, A17, A24, A25, A26, A4, A5, A6, A7, AA1, AA2,

AA28, AA29, AA3, AB28, AC1, AC28, AD1, AD27, AD4, AE28, AE29, AE3,

AE30, AF27, AF28, AF29, AF3, AF4, AG1, AG10, AG11, AG15, AG2, AG20,

AG23, AG24, AG29, AG3, AG8, AH1, AH15, AH19, AH2, AH20, AH23, AH24,

AH30, AH7, AH8, AH9, AJ1, AJ12, AJ14, AJ15, AJ19, AJ20, AJ21, AJ23,

AJ24, AJ25, AJ27, AJ30, AJ6, AJ7, AJ8, AK11, AK14, AK15, AK20, AK21,

AK23, AK24, AK25, AK27, AK5, AK6, AK7, B10, B13, B16, B17, B18, B23,

B24, B25, B5, B6, B7, C11, C13, C14, C16, C17, C22, C23, C24, C25, C6,

C7, C8, D11, D16, D23, D24, D28, D29, D3, D7, D8, E30, E4, F1, F29, F30,

G1, G2, G27, G28, G29, G30, H1, H2, H27, H28, H29, H30, J2, J28, J29, J3,

K1, K2, K27, K28, K3, K4, L1, L2, L27, L3, L4, M1, M2, M29, M3, M30, V27,

V28, V3, V4, W1, W30, Y1, Y27, Y28, Y3, Y30

LFX200: A26, A25, A24, A17, A10, A7, A6, A5, A4, B25, B24, B23, B17, B10,

B7, B6, B5, C25, C24, C23, C22, C16, C11, C8, C7, C6, D24, D23, D16,

D11, D8, D7, E30, F30, F29, F1, G30, G29, G28, G27, G2, G1, H30, H29,

H28, H27, H2, H1, J29, J28, J3, J2, K28, K27, K4, K3, K2, K1, L27, L4, L3,

L2, L1, M3, V28, V27, V4, V3, W30, W1, Y30, Y28, Y27, Y3, Y1, AA29,

AA28, AA3, AA2, AA1, AD27, AD4, AE28, AE3, AF29, AF28, AF27, AF3,

AG29, AG24, AG23, AG20, AG11, AG10, AG8, AG2, AG1, AH30, AH24,

AH23, AH20, AH9, AH8, AH7, AH2, AH1, AJ30, AJ27, AJ25, AJ24, AJ23,

AJ21, AJ15, AJ12, AJ8, AJ7, AJ6, AJ1, AK27, AK25, AK24, AK23, AK21,

AK15, AK11, AK7, AK6, AK5

1. All grounds must be electrically connected at the board level.

2. NC pins should not be connected to any active signals, V_CCor GND.

3. Balls for GND, V_CCand V_CCOxare connected within the substrate to their respective common signals. Pin orientation A1 starts from the

upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.

62

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Power Supply and NC Connections¹(Continued)

Signal

680-Ball fpBGA³

900-Ball fpBGA³

V

AE35, AE5, AL5, AR15, AR25, AR31, AR35, AR5, L11, L20, M12, M13, M14, M17, M18, M19, N12, N19, P12, P19,

AT36, AT4, AU3, AU37, C3, C37, D36, D4, E15, E25, U12, U19, V12, V19, W12, W13, W14, W17, W18, W19, Y11, Y20

E35, E5, E9, J35, R35, R5

CC

V

E11, E12, E13, E17, E18, E7

E22, E23, E27, E29, E31, E33

G35, L35, M35, N35, U35, V35

AB35, AC35, AG35, AJ35, AL35, AN35

AR22, AR23, AR27, AR28, AR29, AR33

AR11, AR13, AR17, AR18, AR7, AR9

AB5, AC5, AG5, AH5, AJ5, AN5

G5, J5, L5, N5, U5, V5

K3, L10, M11, N11, N5, P11, R11, R12

AA3, T11, T12, U11, V11, V5, W11, Y10

AA11, AF13, AH10, W15, Y12, Y13, Y14, Y15

AA20, AF18, AH21, W16, Y16, Y17, Y18, Y19

AA28, T19, T20, U20, V20, V26, W20, Y21

K28, L21, M20, N20, N26, P20, R19, R20

C21, E18, K20, L16, L17, L18, L19, M16

C10, E13, K11, L12, L13, L14, L15, M15

R5, T26

CCO0

CCO1

CCO2

CCO3

CCO4

CCO5

CCO6

CCO7

CCP

E20, AW22

D3

B3

CCJ

GND

A1, A2, A20, A38, A39, AE3, AE37, AK3, AK37,

AR36, AR4, AT20, AT35, AT5, AU10, AU14, AU20,

AU26, AU30, AV1, AV2, AV20, AV38, AV39, AW1,

A1, A2, A29, A30, AB28, AB3, AG27, AG4, AH22, AH28, AH3, AH9,

AJ1, AJ2, AJ29, AJ30, AK1, AK2, AK29, AK30, B1, B2, B29, B30,

C22, C28, C3, C9, D27, D4, J28, J3, N13, N14, N15, N16, N17, N18,

AW2, AW20, AW38, AW39, B1, B2, B20, B38, B39, P13, P14, P15, P16, P17, P18, R13, R14, R15, R16, R17, R18, T13,

C10, C14, C20, C26, C30, D20, D35, D5, E36, E4, T14, T15, T16, T17, T18, U13, U14, U15, U16, U17, U18, V13, V14,

K3, K37, P37, R3, Y1, Y2, Y3, Y36, Y37, Y38, Y39, V15, V16, V17, V18

Y4

GND

AR20, A21

R28, T3

P

63

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Power Supply and NC Connections¹(Continued)

Signal

NC²

680-Ball fpBGA³

900-Ball fpBGA³

A3, B29, AW3, AV3, AW11, AV11, AV29, AW29,

AW37, B3, AV37, C39, C38, AU39, AU38, AJ39,

LFX500: A8, A9, A10, A11, A19, A20, A21, A22, B8, B9, B10, B11,

B19, B20, B21, B22, C1, C2, C11, C12, C19, C20, C23, D3, D10,

AJ38, N38, N39, C2, C1, AU1, AU2, AJ2, AJ1, N2, D11, D12, D19, D20, D21, D22, D23, E3, E5, E6, E10, E11, E12,

N1, B11, A11, A37, B37, A29

E21, E22, E25, E26, E28, E29, E30, F1, F2, F6, F9, F10, F11, F12,

F21, F22, F25, F26, F29, F30, G1, G2, G3, G4, G7, G8, G9, G10,

G11, G12, G14, G15, G16, G17, G19, G20, G21, G22, G23, G24,

G25, G26, G27, G28, G29, G30, H1, H2, H3, H4, H5, H6, H7, H8,

H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H20, H21,

H22, H23, H24, H27, H28, H29, H30, J1, J2, J4, J5, J6, J7, J8, J9,

J10, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, J21, J22, J23,

J24, J25, J26, J27, K6, K7, K8, K9, K10, K12, K13, K14, K15, K16,

K17, K18, K19, K21, K22, K23, K24, K25, L7, L8, L9, L22, L23, L24,

M7, M8, M9, M10, M21, M22, M23, M24, N8, N9, N10, N21, N22,

N23, P7, P8, P9, P10, P21, P22, P23, P24, R8, R9, R10, R21, R22,

R23, R24, R25, T6, T7, T8, T9, T10, T21, T22, T23, T24, T25, U7,

U8, U9, U10, U21, U22, U23, U24, V8, V9, V10, V21, V22, V23, W7,

W8, W9, W10, W21, W22, W23, W24, W25, W26, Y3, Y4, Y5, Y6,

Y7, Y8, Y9, Y22, Y23, Y24, Y25, Y26, Y27, Y28, AA4, AA5, AA6,

AA7, AA8, AA9, AA10, AA12, AA13, AA14, AA15, AA16, AA17,

AA18, AA19, AA21, AA22, AA23, AA24, AA25, AA26, AA27, AB1,

AB2, AB4, AB5, AB6, AB7, AB8, AB9, AB10, AB11, AB12, AB13,

AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AB23,

AB24, AB25, AB26, AB27, AC1, AC2, AC3, AC4, AC5, AC6, AC7,

AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17’

AC18’ AC19, AC20, AC21, AC22, AC23, AC24, AC27, AC28, AC29,

AC30, AD1, AD2, AD7, AD8, AD9, AD10, AD11, AD12, AD14,

AD15, AD16, AD17, AD19, AD20, AD21, AD22, AD23, AD24, AD29,

AD30, AE6, AE9, AE10, AE11, AE12, AE19, AE20, AE21, AE22,

AE25, AE29, AE30, AF5, AF6, AF10, AF11, AF12, AF19, AF20,

AF21, AF22, AF25, AF26, AG10, AG11, AG12, AG19, AG20, AG21,

AG22, AH11, AH12, AH19, AH20, AJ8, AJ9, AJ10, AJ11, AJ20,

AJ21, AJ22, AK8, AK9, AK10, AK11, AK20, AK21, AK22

LFX1200: AA22, AA23, AA24, AA25, AB23, AC24, T21, T22, T23,

T24, T25, U21, U22, U23, U24, V21, V22, V23, W21, W22, W23,

W24, Y22, Y23, Y24, AA16, AA17, AA18, AA19, AA21, AB16, AB17,

AB18, AB19, AB20, AB21, AB22, AC16, AC17, AC18, AC19, AC20,

AC21, AC22, AC23, AD16, AD17, AD19, AD20, AD22, AD23, AD24,

AE22, AE25, AF25, AF26, AA10, AA12, AA13, AA14, AA15, AB10,

AB11, AB12, AB13, AB14, AB15, AB9, AC10, AC11, AC12, AC13,

AC14, AC15, AC8, AC9, AD11, AD12, AD14, AD15, AD7, AD8,

AD9, AE6, AE9, AF5, AF6, H24, J23, K22, K23, K24, K25, L22, L23,

L24, M21, M22, M23, M24, N21, N22, N23, P21, P22, P23, P24,

R21, R22, R23, R24, R25, AA6, AA7, AA8, AA9, AB8, AC7, T10, T6,

T7, T8, T9, U10, U7, U8, U9, V10, V8, V9, W10, W7, W8, W9, Y7,

Y8, Y9, H5, H6, H7, J8, K6, K7, K8, K9, L7, L8, L9, M10, M7, M8,

M9, N10, N8, N9, P10, P7, P8, P9, R10, R8, R9, E25, E26, F22,

F25, G16, G17, G19, G20, G22, G23, G24, H16, H17, H18, H19,

H20, H21, H22, H23, J16, J17, J18, J19, J20, J21, J22, K16, K17,

K18, K19, K21, E5, E6, F6, F9, G11, G12, G14, G15, G7, G8, G9,

H10, H11, H12, H13, H14, H15, H8, H9, J10, J11, J12, J13, J14,

J15, J9, K10, K12, K13, K14, K15

1. All grounds must be electrically connected at the board level.

2. NC pins should not be connected to any active signals, V_CCor GND.

3. Balls for GND, V_CCand V_CCOxare connected within the substrate to their respective common signals. Pin orientation A1 starts from the

upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.

64

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK0_IO2

GND (Bank 0)

BK0_IO3

BK0_IO6

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

C2

-

HSI0A_SOUTP

1P/HSI0

BK0_IO0

-

HSI0A_SOUTP

0P

-

D2

B1

-

HSI0A_SOUTN

1N/HSI0

BK0_IO1

BK0_IO4

GND (Bank 0)

BK0_IO5

BK0_IO6

BK0_IO7

BK0_IO8

-

HSI0A_SOUTN

0N

HSI0A_SINP

3P/HSI0

HSI0A_SINP

2P/HSI0

-

C1

D3

E3

D1

-

BK0_IO7

BK0_IO8

BK0_IO9

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

-

HSI0A_SINN

3N/HSI0

HSI0A_SINN

2N/HSI0

-

4P/HSI0

-

3P/HSI0

VREF0

4N/HSI0

VREF0

3N/HSI0

HSI0B_SOUTP

5P/HSI0

HSI0B_SOUTP

4P/HSI0

-

E1

E2

F2

F1

-

HSI0B_SOUTN

5N/HSI0

BK0_IO9

BK0_IO10

BK0_IO11

BK0_IO12

GND (Bank 0)

BK0_IO13

BK0_IO14

-

HSI0B_SOUTN

4N/HSI0

-

6P/HSI0

-

5P/HSI0

-

6N/HSI0

-

5N/HSI0

HSI0B_SINP

7P/HSI0

HSI0B_SINP

6P/HSI0

-

G1

F3

-

BK0_IO15

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

-

HSI0B_SINN

7N/HSI0

HSI0B_SINN

6N/HSI0

PLL_FBK0

9P

PLL_FBK0

7P/HSI0

-

G2

E4

F4

H1

-

PLL_RST1

9N

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

-

PLL_RST1

7N/HSI0

-

10P

-

8P/HSI0

PLL_FBK1

10N

PLL_FBK1

8N/HSI0

PLL_RST0

11P

PLL_RST0

9P

-

J1

H2

G3

-

BK0_IO23

BK0_IO24

BK0_IO25

GND (Bank 0)

GCLK0

-

11N

-

9N

CLK_OUT0

12P

CLK_OUT0

10P

CLK_OUT1

12N

CLK_OUT1

10N

-

G4

H4

H3

J4

J2

J3

-

LVDS Pair0P

GCLK0

-

LVDS Pair0P

GCLK1

-

LVDS Pair0N

GCLK1

-

LVDS Pair0N

VCCP0

-

VCCP0

-

GNDP0

-

GNDP0

-

GCLK2

-

LVDS Pair1P

GCLK2

-

LVDS Pair1P

GCLK3

LVDS Pair1N

GCLK3

LVDS Pair1N

GND (Bank 1)

BK1_IO0

BK1_IO1

BK1_IO2

-

H5

J5

K1

-

CLK_OUT2

CLK_OUT3

SS_CLKOUT0P

-

13P

13N

14P

-

BK1_IO0

BK1_IO1

BK1_IO2

GND (Bank 1)

BK1_IO3

BK1_IO4

BK1_IO5

BK1_IO6

CLK_OUT2

CLK_OUT3

SS_CLKOUT0P

-

11P

11N

12P

-

L1

K4

L4

K3

BK1_IO3

BK1_IO4

BK1_IO5

BK1_IO6

SS_CLKOUT0N

PLL_FBK2

PLL_FBK3

SS_CLKIN0P

14N

15P

15N

16P

SS_CLKOUT0N

PLL_FBK2

PLL_FBK3

SS_CLKIN0P

12N

13P

13N

14P

65

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

GND (Bank 1)

BK1_IO7

BK1_IO8

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

-

L3

K2

-

SS_CLKIN0N

16N

BK1_IO7

BK1_IO8

GND (Bank 1)

BK1_IO9

BK1_IO10

BK1_IO11

BK1_IO12

BK1_IO13

-

BK1_IO14¹

BK1_IO16

GND (Bank 1)

BK1_IO17

BK1_IO18¹

BK1_IO20

-

SS_CLKIN0N

14N

15P

-

17P

-

L2

M1

N1

M3

M4

-

BK1_IO9

BK1_IO10

BK1_IO11

BK1_IO12

BK1_IO13

GND (Bank 1)

BK1_IO16¹

BK1_IO18

-

17N

-

15N

16P

16N

17P

17N

-

HSI1A_SOUTP

18P/HSI1

-

HSI1A_SOUTN

18N/HSI1

-

PLL_RST2

19P/HSI1

PLL_RST2

PLL_RST3

19N/HSI1

PLL_RST3

-

M2

P1

-

VREF1

-

VREF1

-

HSI1B_SOUTP

22P/HSI1

-

19P

-

R1

N3

N2

-

BK1_IO19

BK1_IO20¹

BK1_IO22

GND (Bank 1)

BK1_IO23

TCK

HSI1B_SOUTN

22N/HSI1

-

19N

-

24P/HSI1

-

HSI1B_SINP

-

21P

-

P2

P4

T2

T3

R3

R4

N5

-

HSI1B_SINN

24N/HSI1

-

BK1_IO21

TCK

-

21N

-

TMS

-

TMS

-

TOE

-

TOE

-

BK2_IO0

BK2_IO1

BK2_IO2

GND (Bank 2)

BK2_IO3

-

26P

26N

27P

-

BK2_IO0

BK2_IO1

BK2_IO2

-

22P

22N

23P

-

P5

-

27N

-

BK2_IO3

GND (Bank 2)

BK2_IO6

BK2_IO7

BK2_IO8

BK2_IO9

BK2_IO10

-

23N

-

T4

T5

N6

P6

R5

-

BK2_IO6

BK2_IO7

BK2_IO8

BK2_IO9

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO12

-

29P

29N

30P

30N

31P

-

25P

25N

26P

26N

27P

-

VREF2

-

R6

N7

-

31N

32P

-

BK2_IO11

BK2_IO12

GND (Bank 2)

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

27N

28P

-

P7

T6

T7

M8

M9

R7

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

32N

33P

33N

34P

34N

35P

28N

29P

29N

30P

30N

31P

66

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

GND (Bank 2)

BK2_IO19

BK2_IO20

BK2_IO21

GND (Bank 2)

GND (Bank 3)

BK3_IO0

BK3_IO1

BK3_IO2

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

-

GND (Bank 2)

BK2_IO19

BK2_IO20

BK2_IO21

-

R8

N8

P8

-

35N

-

31N

32P

32N

-

36P

-

36N

-

T8

-

39P

BK3_IO0

BK3_IO1

BK3_IO2

GND (Bank 3)

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

-

33P

33N

34P

-

T9

-

39N

-

R9

-

40P

-

R10

P9

N9

T10

-

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

GND (Bank 3)

BK3_IO7

BK3_IO8

-

40N

-

34N

35P

35N

36P

-

41P

-

41N

-

42P

-

T11

P10

-

42N

BK3_IO7

BK3_IO8

GND (Bank 3)

BK3_IO9

BK3_IO10

-

36N

37P

-

43P

-

N10

R11

-

BK3_IO9

BK3_IO14

GND (Bank 3)

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

BK3_IO19

BK3_IO20

-

43N

-

37N

38P

-

46P

-

R12

P11

N11

T12

T13

R13

-

46N

BK3_IO11

BK3_IO12

BK3_IO13

BK3_IO14

BK3_IO15

BK3_IO16

GND (Bank 3)

BK3_IO17

BK3_IO18

-

38N

39P

39N

40P

40N

41P

-

VREF3

47P

VREF3

-

47N

-

48P

-

48N

-

49P

-

R14

P12

-

BK3_IO21

BK3_IO22

GND (Bank 3)

BK3_IO23

GSR

-

49N

41N

42P

-

50P

-

N12

T14

T15

P13

P15

N14

R16

-

50N

BK3_IO19

GSR

42N

-

DXP

-

DXP

-

DXN

-

DXN

-

BK4_IO0

BK4_IO1

BK4_IO2

GND (Bank 4)

BK4_IO3

BK4_IO4

-

52P/HSI2

52N/HSI2

53P/HSI2

-

BK4_IO0

BK4_IO1

BK4_IO2

-

44P

44N

45P

-

HSI2A_SINP

-

P16

N15

-

HSI2A_SINN

53N/HSI2

54P/HSI2

-

BK4_IO3

BK4_IO4

GND (Bank 4)

45N

46P

-

67

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK4_IO5

BK4_IO8

BK4_IO9

GND (Bank 4)

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

M15

M14

M13

-

54N/HSI2

BK4_IO5

BK4_IO6

BK4_IO7

-

46N

-

56P/HSI2

-

47P

VREF4

56N/HSI2

VREF4

47N

-

L13

L14

N16

M16

-

PLL_RST4

58P/HSI2

BK4_IO8

BK4_IO9

BK4_IO10

BK4_IO11

GND (Bank 4)

BK4_IO14

-

PLL_RST4

48P

PLL_RST5

58N/HSI2

PLL_RST5

48N

HSI2B_SOUTP

59P/HSI2

-

49P

HSI2B_SOUTN

59N/HSI2

-

49N

-

L15

-

BK4_IO18

GND (Bank 4)

BK4_IO19

BK4_IO20

BK4_IO21

BK4_IO22

-

SS_CLKIN1P

61P

SS_CLKIN1P

51P

-

K15

K14

K13

L16

-

SS_CLKIN1N

61N

BK4_IO15

BK4_IO16

BK4_IO17

BK4_IO18

GND (Bank 4)

BK4_IO19

BK4_IO20

BK4_IO21

-

SS_CLKIN1N

51N

PLL_FBK4

62P

PLL_FBK4

52P

PLL_FBK5

62N

PLL_FBK5

52N

SS_CLKOUT1P

63P

SS_CLKOUT1P

53P

-

K16

J13

J12

-

BK4_IO23

BK4_IO24

BK4_IO25

GND (Bank 4)

GCLK4

SS_CLKOUT1N

63N

SS_CLKOUT1N

53N

CLK_OUT4

64P

CLK_OUT4

54P

CLK_OUT5

64N

CLK_OUT5

54N

-

J14

H14

J15

H15

J16

H16

-

LVDS Pair2P

GCLK4

-

LVDS Pair2P

GCLK5

-

LVDS Pair2N

GCLK5

-

LVDS Pair2N

VCCP1

-

VCCP1

-

GNDP1

-

GNDP1

-

GCLK6

-

LVDS Pair3P

GCLK6

-

LVDS Pair3P

GCLK7

-

LVDS Pair3N

GCLK7

-

LVDS Pair3N

GND (Bank 5)

BK5_IO0

BK5_IO1

BK5_IO2

-

55P

H12

H13

G14

-

CLK_OUT6

65P

BK5_IO0

BK5_IO1

BK5_IO2

GND (Bank 5)

BK5_IO3

BK5_IO6

-

CLK_OUT6

CLK_OUT7

65N

CLK_OUT7

55N

-

66P

-

56P

-

G15

G13

-

BK5_IO3

BK5_IO6

GND (Bank 5)

BK5_IO7

BK5_IO10

-

PLL_RST7

66N

PLL_RST7

56N

PLL_RST6

68P

PLL_RST6

58P/HSI1

-

F13

G16

-

PLL_FBK7

68N

BK5_IO7

BK5_IO8

GND (Bank 5)

BK5_IO9

BK5_IO10

BK5_IO11

BK5_IO12

-

PLL_FBK7

58N/HSI1

59P/HSI1

-

HSI3A_SINP

70P

HSI1A_SINP

-

F16

F14

F15

E16

-

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

GND (Bank 5)

HSI3A_SINN

70N/HSI3

71P/HSI3

71N/HSI3

72P/HSI3

-

HSI1A-SINN

59N/HSI1

60P/HSI1

60N/HSI1

61P/HSI1

-

HSI3A_SOUTP

-

HSI1A_SOUTP

-

68

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

D16

E13

E14

E15

-

HSI3A_SOUTN

72N/HSI3

BK5_IO13

BK5_IO14

BK5_IO15

BK5_IO16

GND (Bank 5)

BK5_IO17

BK5_IO20

-

HSI1A_SOUTN

61N/HSI1

VREF5

73P/HSI3

VREF5

62P/HSI1

-

73N/HSI3

-

62N/HSI1

HSI3B_SINP

74P/HSI3

HSI1B_SINP

63P/HSI1

-

D15

C16

-

BK5_IO19

BK5_IO22

GND (Bank 5)

BK5_IO23

BK5_IO24

BK5_IO25

CFG0

HSI3B_SINN

74N/HSI3

HSI1B_SINN

63N/HSI1

HSI3B_SOUTP

76P/HSI3

HSI1B_SOUTP

65P/HSI1

-

B16

D14

C15

C13

A15

A14

D12

C12

B14

-

HSI3B_SOUTN

76N/HSI3

BK5_IO21

BK5_IO18

BK5_IO19

CFG0

HSI1B_SOUTN

65N/HSI1

-

77P/HSI3

77N/HSI3

-

64P/HSI1

64N/HSI1

-

DONE

-

DONE

-

PROGRAMb

BK6_IO0

BK6_IO1

BK6_IO2

GND (Bank 6)

BK6_IO3

BK6_IO4

-

PROGRAMb

BK6_IO0

BK6_IO1

BK6_IO2

-

INITb

78P

78N

79P

-

INITb

66P

66N

67P

-

CCLK

-

B13

A13

-

79N

80P

-

BK6_IO3

BK6_IO4

GND (Bank 6)

BK6_IO5

BK6_IO6

BK6_IO7

BK6_IO8

BK6_IO9

BK6_IO10

-

67N

68P

-

CSb

-

A12

D11

C11

B12

B11

D10

-

BK6_IO5

BK6_IO6

BK6_IO7

BK6_IO8

BK6_IO9

BK6_IO10

GND (Bank 6)

BK6_IO11

-

Read

80N

81P

81N

82P

82N

83P

-

READ

68N

69P

69N

70P

70N

71P

-

DATA7

DATA6

-

VREF6

DATA5

-

C10

-

DATA4

83N

-

BK6_IO11

GND (Bank 6)

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

-

DATA4

71N

-

A11

A10

D9

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

GND (Bank 6)

GND (Bank 7)

BK7_IO0

DATA3

85P

85N

86P

86N

87P

-

DATA3

73P

73N

74P

74N

75P

-

DATA2

-

C9

-

B10

-

DATA1

-

B9

DATA0

87N

88P

88N

-

DATA0

75N

76P

76N

-

E9

-

E8

-

D8

91P

BK7_IO0

77P

69

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)

LFX200

LFX125

256-fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK7_IO1

BK7_IO2

BK7_IO3

BK7_IO6

GND (Bank 7)

BK7_IO7

BK7_IO10

BK7_IO11

BK7_IO12

-

Function

sysHSI Reserved²Signal Name

Function

sysHSI Reserved²

C8

B8

B7

A9

-

91N

92P

92N

94P

-

BK7_IO1

BK7_IO2

BK7_IO3

BK7_IO4

-

77N

78P

78N

79P

-

A8

C7

D7

D6

-

94N

96P

96N

97P

-

BK7_IO5

BK7_IO6

BK7_IO7

BK7_IO8

GND (Bank 7)

BK7_IO9

BK7_IO10

-

79N

80P

80N

81P

-

C6

B6

-

BK7_IO13

BK7_IO14

GND (Bank 7)

BK7_IO15

BK7_IO16

BK7_IO17

BK7_IO18

BK7_IO19

BK7_IO20

-

97N

98P

-

81N

82P

-

B5

A7

A6

D5

C5

A5

-

98N

99P

99N

100P

100N

101P

-

BK7_IO11

BK7_IO12

BK7_IO13

BK7_IO14

BK7_IO15

BK7_IO16

GND (Bank 7)

BK7_IO17

BK7_IO18

-

82N

83P

83N

84P

84N

85P

-

VREF7

-

A4

B4

-

BK7_IO21

BK7_IO22

GND (Bank 7)

BK7_IO23

TDO

101N

102P

-

85N

86P

-

B3

A3

A2

C4

102N

-

BK7_IO19

TDO

86N

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

1. Not available for differential pairs.

2. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use.

70

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

516-Ball

Second

sysHSI

BGA Ball

Signal Name

BK0_IO0

Function

Reserved¹

Signal Name

BK0_IO0

BK0_IO1

BK0_IO2

GND (Bank 0)

BK0_IO3

BK0_IO4

BK0_IO5

BK0_IO6

-

Function

Reserved¹

Signal Name

NC

Function

Reserved¹

E4

D3

E3

-

0P

0N

-

0P/HSI0

-

BK0_IO1

-

0N/HSI0

NC

-

BK0_IO2

HSI0A_SOUTP

1P/HSI0

-

HSI0A_SOUTP

1P/HSI0

BK0_IO0

-

HSI0A_SOUTP

0P

GND (Bank 0)

BK0_IO3

-

F3

C2

B1

G4

-

HSI0A_SOUTN

1N/HSI0

2P/HSI0

2N/HSI0

3P/HSI0

-

HSI0A_SOUTN

1N/HSI0

BK0_IO1

BK0_IO2

BK0_IO3

BK0_IO4

GND (Bank 0)

BK0_IO5

BK0_IO6

BK0_IO7

BK0_IO8

-

HSI0A_SOUTN

0N

BK0_IO4

-

2P/HSI0

-

1P/HSI0

BK0_IO5

-

2N/HSI0

-

1N/HSI0

BK0_IO6

HSI0A_SINP

3P/HSI0

HSI0A_SINP

2P/HSI0

-

G3

C1

D2

H4

-

BK0_IO7

HSI0A_SINN

3N/HSI0

4P/HSI0

4N/HSI0

5P/HSI0

-

BK0_IO7

BK0_IO8

BK0_IO9

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

-

HSI0A_SINN

3N/HSI0

HSI0A_SINN

2N/HSI0

BK0_IO8

-

4P/HSI0

-

3P/HSI0

BK0_IO9

VREF0

4N/HSI0

VREF0

3N/HSI0

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

-

HSI0B_SOUTP

-

5P/HSI0

HSI0B_SOUTP

4P/HSI0

-

H3

D1

E1

E2

-

HSI0B_SOUTN

5N/HSI0

6P/HSI0

6N/HSI0

7P/HSI0

-

HSI0B_SOUTN

5N/HSI0

BK0_IO9

BK0_IO10

BK0_IO11

BK0_IO12

GND (Bank 0)

BK0_IO13

NC

HSI0B_SOUTN

4N/HSI0

-

6P/HSI0

-

5P/HSI0

-

6N/HSI0

-

5N/HSI0

HSI0B_SINP

7P/HSI0

HSI0B_SINP

6P/HSI0

-

F2

G2

F1

J3

-

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

BK0_IO23

BK0_IO24

BK0_IO25

BK0_IO26

GND (Bank 0)

BK0_IO27

BK0_IO28

BK0_IO29

BK0_IO30

BK0_IO31

BK0_IO32

BK0_IO33

BK0_IO34

GND (Bank 0)

BK0_IO35

BK0_IO36

BK0_IO37

BK0_IO38

-

HSI0B_SINN

7N/HSI0

8P/HSI0

8N/HSI0

9P

BK0_IO15

NC

HSI0B_SINN

7N/HSI0

HSI0B_SINN

6N/HSI0

-

NC

-

NC

-

HSI1A_SOUTP

NC

-

NC

-

K3

K4

L4

H2

J2

G1

H1

L3

-

HSI1A_SOUTN

9N

NC

-

NC

-

10P

NC

-

NC

-

10N

NC

-

NC

-

HSI1A_SINP

11P

NC

-

NC

-

HSI1A_SINN

11N

NC

-

NC

-

12P

NC

-

NC

-

12N

NC

-

NC

-

HSI1B_SOUTP

13P

NC

-

NC

-

M3

K2

L2

K1

L1

M2

M1

N3

-

HSI1B_SOUTN

13N

NC

-

NC

-

14P

NC

-

NC

-

14N

NC

-

NC

-

HSI1B_SINP

15P

NC

-

NC

-

HSI1B_SINN

15N

NC

-

NC

-

16P

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

-

8P

8N

9P

-

NC

-

16N

-

NC

-

PLL_FBK0

17P

PLL_FBK0

BK0_IO14

-

PLL_FBK0

7P/HSI0

-

7N/HSI0

8P/HSI0

8N/HSI0

9P

N4

N2

N1

P1

-

PLL_RST1

17N

PLL_RST1

9N

10P

10N

11P

-

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

-

PLL_RST1

-

18P

-

PLL_FBK1

18N

PLL_FBK1

PLL_RST0

19P

PLL_RST0

-

R1

P3

-

BK0_IO39

BK0_IO40

GND (Bank 0)

BK0_IO41

-

19N

BK0_IO23

BK0_IO24

-

11N

12P

-

9N

CLK_OUT0

-

20P

CLK_OUT0

-

CLK_OUT0

-

10P

-

P2

CLK_OUT1

20N

BK0_IO25

CLK_OUT1

12N

BK0_IO21

CLK_OUT1

10N

71

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

-

Function

Reserved¹

Signal Name

GND (Bank 0)

GCLK0

Function

Reserved¹

Signal Name

-

Function

Reserved¹

-

R2

R3

R4

T4

T3

T2

-

GCLK0

GCLK1

VCCP0

GNDP0

GCLK2

GCLK3

-

LVDS Pair0P

-

LVDS Pair0P

GCLK0

GCLK1

VCCP0

GNDP0

GCLK2

GCLK3

-

LVDS Pair0P

-

LVDS Pair0N

GCLK1

-

LVDS Pair0N

-

LVDS Pair0N

-

VCCP0

-

GNDP0

GCLK2

-

LVDS Pair1P

-

LVDS Pair1P

-

LVDS Pair1P

-

LVDS Pair1N

GCLK3

-

LVDS Pair1N

-

LVDS Pair1N

-

GND (Bank 1)

BK1_IO0

-

T1

-

BK1_IO0

GND (Bank 1)

BK1_IO1

BK1_IO2

-

CLK_OUT2

-

21P

-

CLK_OUT2

13P

-

BK1_IO0

-

CLK_OUT2

11P

-

CLK_OUT3

SS_CLKOUT0P

-

CLK_OUT3

SS_CLKOUT0P

-

U1

U2

-

CLK_OUT3

SS_CLKOUT0P

-

21N

22P

-

BK1_IO1

BK1_IO2

-

13N

14P

-

BK1_IO1

BK1_IO2

GND (Bank 1)

BK1_IO3

11N

12P

-

U3

BK1_IO3

SS_CLKOUT0N

22N

BK1_IO3

SS_CLKOUT0

N

14N

SS_CLKOUT0

N

12N

V1

V2

BK1_IO4

BK1_IO5

BK1_IO6

GND (Bank 1)

BK1_IO7

BK1_IO8

BK1_IO9

BK1_IO10

-

PLL_FBK2

23P

23N

BK1_IO4

BK1_IO5

NC

PLL_FBK2

15P

BK1_IO4

BK1_IO5

NC

PLL_FBK2

13P

PLL_FBK3

15N

PLL_FBK3

13N

V3

-

24P

-

V4

-

24N

NC

-

NC

-

W1

Y1

-

25P

NC

-

NC

-

25N

NC

-

NC

-

W2

-

SS_CLKINOP

26P

BK1_IO6

GND (Bank 1)

BK1_IO7

BK1_IO8

-

SS_CLKIN0P

16P

BK1_IO6

-

SS_CLKIN0P

14P

-

W3

Y2

BK1_IO11

BK1_IO12

-

SS_CLKINON

26N

SS_CLKIN0N

16N

BK1_IO7

BK1_IO8

GND (Bank 1)

BK1_IO9

NC

SS_CLKIN0N

14N

15P

-

27P

-

17P

-

Y4

BK1_IO13

BK1_IO14

GND (Bank 1)

BK1_IO15

BK1_IO16

BK1_IO17

BK1_IO18

BK1_IO19

BK1_IO20

BK1_IO21

BK1_IO22

GND (Bank 1)

BK1_IO23

BK1_IO24

BK1_IO25

BK1_IO26

-

27N

BK1_IO9

NC

-

17N

-

15N

-

Y3

-

28P

-

AA1

AA2

AA3

AB2

AC2

AB3

AA4

AC1

-

28N

NC

-

NC

-

29P

NC

-

NC

-

29N

NC

-

NC

-

HSI2A_SOUTP

30P

BK1_IO10

BK1_IO11

BK1_IO12

BK1_IO13

BK1_IO14

GND (Bank 1)

BK1_IO15

BK1_IO16

BK1_IO17

BK1_IO18

-

HSI1A_SOUTP

18P/HSI1

18N/HSI1

19P/HSI1

19N/HSI1

20P/HSI1

-

BK1_IO10

BK1_IO11

BK1_IO12

BK1_IO13

NC

-

16P

16N

17P

17N

-

HSI2A_SOUTN

30N

HSI1A_SOUTN

-

PLL_RST2

31P

PLL_RST2

PLL_RST3

31N

PLL_RST3

HSI2A_SINP

32P

HSI1A_SINP

-

AD1

AE1

AF1

AC3

-

HSI2A_SINN

32N

HSI1A_SINN

20N/HSI1

21P/HSI1

21N/HSI1

22P/HSI1

-

NC

-

VREF1

33P/HSI2

33N/HSI2

34P/HSI2

-

VREF1

BK1_IO14

BK1_IO15

BK1_IO16

GND (Bank 1)

BK1_IO17

BK1_IO18

BK1_IO19

BK1_IO20

-

VREF1

18P

18N

19P

-

HSI2B_SOUTP

HSI1B_SOUTP

-

AC4

AD2

AD3

AE2

-

BK1_IO27

BK1_IO28

BK1_IO29

BK1_IO30

GND (Bank 1)

BK1_IO31

BK1_IO32

HSI2B_SOUTN

34N/HSI2

35P/HSI2

35N/HSI2

36P/HSI2

-

BK1_IO19

BK1_IO20

BK1_IO21

BK1_IO22

GND (Bank 1)

BK1_IO23

NC

HSI1B_SOUTN

22N/HSI1

23P/HSI1

23N/HSI1

24P/HSI1

-

19N

20P

20N

21P

-

HSI2B_SINP

HSI1B_SINP

-

AF2

AD4

HSI2B_SINN

-

36N/HSI2

37P/HSI2

HSI1B_SINN

-

24N/HSI1

-

BK1_IO21

NC

21N

-

72

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK1_IO33

BK1_IO34

BK1_IO35

BK1_IO36

BK1_IO37

BK1_IO38

GND (Bank 1)

BK1_IO39

BK1_IO40

BK1_IO41

TCK

Function

Reserved¹

Signal Name

NC

Function

Reserved¹

Signal Name

Function

Reserved¹

AE3

AG1

AH1

AG2

AF3

AJ1

-

37N/HSI2

38P/HSI2

38N/HSI2

39P/HSI2

39N/HSI2

40P/HSI2

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AH2

AG3

AF4

AK2

AJ3

AG5

AH4

AK3

AJ4

-

40N/HSI2

41P

41N

-

NC

-

NC

-

BK1_IO24

BK1_IO25

TCK

-

25P/HSI1

NC

-

25N/HSI1

NC

-

TCK

-

TMS

-

TMS

-

TMS

-

TOE

-

TOE

-

TOE

-

BK2_IO0

BK2_IO1

BK2_IO2

GND (Bank 2)

BK2_IO3

BK2_IO4

-

42P

42N

43P

-

BK2_IO0

BK2_IO1

BK2_IO2

GND (Bank 2)

BK2_IO3

BK2_IO4

-

26P

BK2_IO0

BK2_IO1

BK2_IO2

-

22P

-

26N

-

22N

-

27P

-

23P

-

AH5

AK4

-

43N

44P

-

27N

BK2_IO3

BK2_IO4

GND (Bank 2)

BK2_IO5

BK2_IO6

BK2_IO7

NC

-

23N

-

28P

-

24P

-

AJ5

AG7

AH6

AK5

AJ6

AG8

-

BK2_IO5

BK2_IO6

BK2_IO7

BK2_IO8

BK2_IO9

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

GND (Bank 2)

BK2_IO19

BK2_IO20

BK2_IO21

BK2_IO22

-

44N

45P

45N

46P

46N

47P

-

BK2_IO5

BK2_IO6

BK2_IO7

NC

-

28N

-

24N

-

29P

-

25P

-

29N

-

25N

-

NC

-

NC

-

NC

-

NC

-

AH7

AK6

AJ7

AH8

AG10

AK7

AJ8

AH9

-

47N

48P

48N

49P

49N

50P

50N

51P

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AG11

AK8

AJ9

AH10

-

51N

52P

52N

53P

-

NC

-

NC

-

BK2_IO8

BK2_IO9

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO12

BK2_IO13

BK2_IO14

-

30P

30N

31P

-

BK2_IO8

BK2_IO9

BK2_IO10

-

26P

26N

27P

-

VREF2

-

AH11

AJ10

AK10

AH12

-

BK2_IO23

BK2_IO24

BK2_IO25

BK2_IO26

GND (Bank 2)

BK2_IO27

BK2_IO28

BK2_IO29

BK2_IO30

BK2_IO31

53N

54P

54N

55P

-

31N

32P

32N

33P

-

BK2_IO11

BK2_IO12

BK2_IO13

BK2_IO14

-

27N

28P

28N

29P

-

AJ11

AK11

AJ12

AG13

AH13

55N

56P

56N

57P

57N

BK2_IO15

NC

33N

-

BK2_IO15

NC

29N

-

NC

-

NC

-

BK2_IO16

BK2_IO17

34P

34N

BK2_IO16

BK2_IO17

30P

30N

73

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK2_IO32

-

Function

Reserved¹

Signal Name

BK2_IO18

GND (Bank 2)

BK2_IO19

BK2_IO20

-

Function

Reserved¹

Signal Name

Function

Reserved¹

AJ13

-

58P

-

35P

-

BK2_IO18

-

31P

-

GND (Bank 2)

-

AK12

AK13

-

BK2_IO33

BK2_IO34

GND (Bank 2)

BK2_IO35

BK2_IO36

BK2_IO37

BK2_IO38

BK2_IO39

BK2_IO40

BK2_IO41

GND (Bank 2)

GND (Bank 3)

BK3_IO0

-

58N

59P

-

35N

36P

-

BK2_IO19

-

31N

-

BK2_IO20

-

32P

-

AH14

AJ14

AK14

AG15

AH15

AJ15

AK15

-

59N

60P

60N

61P

61N

62P

62N

-

BK2_IO21

BK2_IO22

BK2_IO23

BK2_IO24

BK2_IO25

NC

36N

37P

37N

38P

38N

-

BK2_IO21

-

32N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

GND (Bank 2)

GND (Bank 3)

BK3_IO0

BK3_IO1

BK3_IO2

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

GND (Bank 3)

BK3_IO7

BK3_IO8

-

AK16

AJ16

AH16

AG16

AK17

AJ17

AH17

-

63P

63N

64P

64N

65P

65N

66P

-

39P

39N

40P

40N

41P

41N

42P

-

BK3_IO0

BK3_IO1

BK3_IO2

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

-

33P

BK3_IO1

-

33N

BK3_IO2

-

34P

BK3_IO3

-

34N

BK3_IO4

-

35P

BK3_IO5

-

35N

BK3_IO6

-

36P

GND (Bank 3)

BK3_IO7

-

AJ18

AH18

-

66N

67P

-

42N

43P

-

BK3_IO7

BK3_IO8

GND (Bank 3)

BK3_IO9

BK3_IO10

BK3_IO11

NC

-

36N

BK3_IO8

-

37P

-

AG18

AK18

AK19

AJ19

AH19

AK20

-

BK3_IO9

-

67N

68P

68N

69P

69N

70P

-

BK3_IO9

BK3_IO10

BK3_IO11

BK3_IO12

BK3_IO13

BK3_IO14

GND (Bank 3)

BK3_IO15

NC

43N

44P

44N

45P

45N

46P

-

37N

BK3_IO10

BK3_IO11

BK3_IO12

BK3_IO13

BK3_IO14

GND (Bank 3)

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

BK3_IO19

BK3_IO20

BK3_IO21

BK3_IO22

GND (Bank 3)

BK3_IO23

BK3_IO24

BK3_IO25

BK3_IO26

BK3_IO27

BK3_IO28

BK3_IO29

BK3_IO30

GND (Bank 3)

BK3_IO31

-

38P

-

38N

-

NC

-

NC

-

AJ20

AH20

AG20

AK21

AJ21

AH21

AG21

AJ22

-

70N

71P

71N

72P

72N

73P

73N

74P

-

46N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

VREF3

BK3_IO16

BK3_IO17

BK3_IO18

-

VREF3

47P

47N

48P

-

BK3_IO12

BK3_IO13

BK3_IO14

-

VREF3

39P

-

39N

40P

-

AH22

AK23

AJ23

AH23

AK24

AJ24

AG23

AH24

-

74N

75P

75N

76P

76N

77P

77N

78P

-

BK3_IO19

NC

48N

-

BK3_IO15

NC

40N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AK25

78N

NC

-

NC

74

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK3_IO32

BK3_IO33

BK3_IO34

-

Function

Reserved¹

Signal Name

NC

Function

Reserved¹

Signal Name

NC

Function

Reserved¹

AJ25

AG24

AK26

-

79P

-

79N

NC

-

NC

-

80P

BK3_IO20

-

49P

BK3_IO16

GND (Bank 3)

BK3_IO17

BK3_IO18

-

41P

-

AH25

AJ26

-

BK3_IO35

BK3_IO36

-

80N

BK3_IO21

BK3_IO22

GND (Bank 3)

BK3_IO23

NC

-

49N

-

41N

-

81P

-

50P

-

42P

-

81N

-

AH26

AK27

-

BK3_IO37

BK3_IO38

GND (Bank 3)

BK3_IO39

BK3_IO40

BK3_IO41

GSR

-

50N

BK3_IO19

NC

-

42N

-

82P

-

AJ27

AG26

AH27

AK28

AJ28

AK29

AH29

AG28

AF27

-

82N

NC

-

NC

-

83P

BK3_IO24

BK3_IO25

GSR

-

51P

BK3_IO20

BK3_IO21

GSR

-

43P

-

83N

-

51N

-

43N

-

DXP

-

DXP

-

DXP

-

DXN

-

DXN

-

DXN

-

BK4_IO0

BK4_IO1

BK4_IO2

GND (Bank 4)

BK4_IO3

BK4_IO4

BK4_IO5

BK4_IO6

BK4_IO7

BK4_IO8

BK4_IO9

BK4_IO10

GND (Bank 4)

BK4_IO11

BK4_IO12

-

84P

BK4_IO0

BK4_IO1

NC

-

52P/HSI2

BK4_IO0

BK4_IO1

NC

-

44P

-

84N

-

52N/HSI2

-

44N

-

85P/HSI3

-

AF28

AJ30

AH30

AG29

AF29

AE28

AD27

AG30

-

85N/HSI3

86P/HSI3

86N/HSI3

87P/HSI3

87N/HSI3

88P/HSI3

88N/HSI3

89P/HSI3

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

HSI3A_SINP

BK4_IO2

GND (Bank 4)

BK4_IO3

BK4_IO4

-

HSI2A_SINP

53P/HSI2

BK4_IO2

-

45P

-

AF30

AD28

-

HSI3A_SINN

89N/HSI3

90P/HSI3

-

HSI2A_SINN

53N/HSI2

BK4_IO3

BK4_IO4

GND (Bank 4)

BK4_IO5

NC

-

45N

-

54P/HSI2

-

46P

-

AC27

AE29

AE30

AD29

AD30

AC28

-

BK4_IO13

BK4_IO14

BK4_IO15

BK4_IO16

BK4_IO17

BK4_IO18

GND (Bank 4)

BK4_IO19

BK4_IO20

BK4_IO21

BK4_IO22

BK4_IO23

BK4_IO24

BK4_IO25

BK4_IO26

GND (Bank 4)

BK4_IO27

BK4_IO28

-

90N/HSI3

91P/HSI3

91N/HSI3

92P/HSI3

92N/HSI3

93P

BK4_IO5

BK4_IO6

BK4_IO7

BK4_IO8

BK4_IO9

BK4_IO10

GND (Bank 4)

BK4_IO11

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15

NC

-

54N/HSI2

-

46N

HSI3A_SOUTP

HSI2A_SOUTP

55P/HSI2

-

HSI3A_SOUTN

HSI2A_SOUTN

55N/HSI2

NC

-

56P/HSI2

BK4_IO6

BK4_IO7

NC

-

47P

VREF4

56N/HSI2

VREF4

47N

HSI3B_SINP

HSI2B_SINP

57P/HSI2

-

AB28

AA27

AB29

AC29

AC30

AA28

Y27

HSI3B_SINN

93N

HSI2B_SINN

57N/HSI2

NC

-

PLL_RST4

94P

PLL_RST4

58P/HSI2

BK4_IO8

BK4_IO9

BK4_IO10

BK4_IO11

NC

PLL_RST4

48P

PLL_RST5

94N

PLL_RST5

58N/HSI2

PLL_RST5

48N

HSI3B_SOUTP

95P

HSI2B_SOUTP

59P/HSI2

-

49P

HSI3B_SOUTN

95N

HSI2B_SOUTN

59N/HSI2

49N

-

96P

-

96N

NC

-

NC

-

Y28

97P

NC

-

NC

-

AA29

Y29

97N

NC

-

60P

-

NC

-

50P

-

98P

BK4_IO16

-

BK4_IO12

GND (Bank 4)

-

75

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK4_IO29

BK4_IO30

-

Function

Reserved¹

Signal Name

BK4_IO17

BK4_IO18

GND (Bank 4)

BK4_IO19

NC

Function

Reserved¹

Signal Name

BK4_IO13

BK4_IO14

-

Function

Reserved¹

AA30

W28

-

98N

99P

-

60N

-

50N

SS_CLKIN1P

61P

SS_CLKIN1P

51P

-

W29

Y30

W30

V27

-

BK4_IO31

BK4_IO32

BK4_IO33

BK4_IO34

GND (Bank 4)

BK4_IO35

BK4_IO36

BK4_IO37

BK4_IO38

BK4_IO39

BK4_IO40

GND (Bank 4)

BK4_IO41

-

SS_CLKIN1N

99N

SS_CLKIN1N

61N

BK4_IO15

NC

SS_CLKIN1N

51N

-

100P

-

100N

NC

-

NC

-

101P

NC

-

NC

-

V28

V29

V30

U30

U29

U28

-

101N

NC

-

NC

-

PLL_FBK4

102P

BK4_IO20

BK4_IO21

BK4_IO22

BK4_IO23

BK4_IO24

-

PLL_FBK4

62P

BK4_IO16

BK4_IO17

BK4_IO18

BK4_IO19

BK4_IO20

-

PLL_FBK4

52P

PLL_FBK5

102N

PLL_FBK5

62N

PLL_FBK5

52N

SS_CLKOUT1P

103P

SS_CLKOUT1P

63P

SS_CLKOUT1P

53P

SS_CLKOUT1N

103N

SS_CLKOUT1N

63N

SS_CLKOUT1N

53N

CLK_OUT4

104P

CLK_OUT4

64P

CLK_OUT4

54P

-

T27

-

CLK_OUT5

104N

BK4_IO25

GND (Bank 4)

GCLK4

GCLK5

VCCP1

GNDP1

GCLK6

GCLK7

GND (Bank 5)

BK5_IO0

-

CLK_OUT5

64N

BK4_IO21

-

CLK_OUT5

54N

-

T28

T29

T30

R29

R28

R27

-

GCLK4

-

LVDS Pair2P

LVDS Pair2N

-

LVDS Pair2P

GCLK4

GCLK5

VCCP1

GNDP1

GCLK6

GCLK7

-

LVDS Pair2P

GCLK5

-

LVDS Pair2N

-

LVDS Pair2N

VCCP1

-

GNDP1

-

GCLK6

-

LVDS Pair3P

LVDS Pair3N

-

LVDS Pair3P

-

LVDS Pair3P

GCLK7

-

LVDS Pair3N

-

LVDS Pair3N

-

R30

-

BK5_IO0

GND (Bank 5)

BK5_IO1

BK5_IO2

-

CLK_OUT6

105P

CLK_OUT6

65P

BK5_IO0

-

CLK_OUT6

55P

-

P30

P29

-

CLK_OUT7

105N

BK5_IO1

BK5_IO2

-

CLK_OUT7

65N

BK5_IO1

BK5_IO2

GND (Bank 5)

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

-

CLK_OUT7

55N

-

106P

-

66P

-

56P

-

P28

N30

N29

N28

-

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

GND (Bank 5)

BK5_IO7

BK5_IO8

BK5_IO9

BK5_IO10

-

PLL_RST7

106N

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

GND (Bank 5)

BK5_IO7

BK5_IO8

BK5_IO9

BK5_IO10

-

PLL_RST7

66N

PLL_RST7

56N

PLL_FBK6

107P

PLL_FBK6

67P

PLL_FBK6

57P/HSI1

-

107N

-

67N

-

57N/HSI1

PLL-RST6

108P

PLL_RST6

68P

PLL_RST6

58P//HSI1

-

N27

M30

M29

L30

-

PLL_FBK7

108N

PLL_FBK7

68N

BK5_IO7

NC

PLL_FBK7

58N/HSI1

-

109P/HSI4

109N/HSI4

110P/HSI4

-

69P

-

69N

NC

-

HSI4A_SINP

HSI3A_SINP

70P/HSI3

BK5_IO8

GND (Bank 5)

BK5_IO9

BK5_IO10

BK5_IO11

BK5_IO12

-

HSI1A_SINP

59P/HSI1

-

L29

M28

L28

K30

-

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

GND (Bank 5)

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

BK5_IO19

BK5_IO20

BK5_IO21

HSI4A_SINN

110N/HSI4

111P/HSI4

111N/HSI4

112P/HSI4

-

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

GND (Bank 5)

BK5_IO15

NC

HSI3A_SINN

-

70N/HSI3

HSI1A_SINN

59N/HSI1

-

71P/HSI3

-

60P/HSI1

-

71N/HSI3

-

60N/HSI1

HSI4A_SOUTP

HSI3A_SOUTP

72P/HSI3

HSI1A_SOUTP

61P/HSI1

-

K29

L27

K28

H30

G30

J28

K27

HSI4A_SOUTN

112N/HSI4

113P/HSI4

113N/HSI4

114P/HSI4

114N/HSI4

115P/HSI4

115N/HSI4

HSI3A_SOUTN

72N/HSI3

BK5_IO13

NC

HSI1A_SOUTN

61N/HSI1

-

NC

HSI4B_SINP

NC

HSI4B_SINN

NC

-

NC

76

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK5_IO22

GND (Bank 5)

BK5_IO23

BK5_IO24

BK5_IO25

BK5_IO26

BK5_IO27

BK5_IO28

BK5_IO29

BK5_IO30

GND (Bank 5)

BK5_IO31

BK5_IO32

BK5_IO33

BK5_IO34

-

Function

Reserved¹

Signal Name

Function

Reserved¹

Signal Name

Function

Reserved¹

J29

-

HSI4B_SOUTP

116P/HSI4

-

NC

-

NC

-

NC

-

H29

F30

G29

H28

H27

E30

F29

G28

-

HSI4B_SOUTN

116N/HSI4

117P/HSI5

117N/HSI5

118P/HSI5

118N/HSI5

119P/HSI5

119N/HSI5

120P/HSI5

-

NC

-

NC

-

NC

-

NC

-

NC

-

HSI5A_SINP

NC

-

NC

-

HSI5A_SINN

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

HSI5A_SOUTP

NC

-

NC

-

G27

E29

F28

D30

-

HSI5A_SOUTN

120N/HSI5

121P/HSI5

121N/HSI5

122P/HSI5

-

NC

-

NC

-

VREF5

BK5_IO16

BK5_IO17

BK5_IO18

-

VREF5

73P/HSI3

BK5_IO14

BK5_IO15

BK5_IO16

GND (Bank 5)

BK5_IO17

NC

VREF5

62P/HSI1

-

73N/HSI3

-

62N/HSI1

HSI5B_SINP

HSI3B_SINP

-

74P/HSI3

HSI1B_SINP

63P/HSI1

-

C30

D29

D28

E28

-

BK5_IO35

BK5_IO36

BK5_IO37

BK5_IO38

GND (Bank 5)

BK5_IO39

BK5_IO40

BK5_IO41

CFG0

HSI5B_SINN

122N/HSI5

123P/HSI5

123N/HSI5

124P/HSI5

-

BK5_IO19

BK5_IO20

BK5_IO21

BK5_IO22

GND (Bank 5)

BK5_IO23

BK5_IO24

BK5_IO25

CFG0

DONE

PROGRAMb

BK6_IO0

BK6_IO1

BK6_IO2

GND (Bank 6)

BK6_IO3

BK6_IO4

-

HSI3B_SINN

74N/HSI3

HSI1B_SINN

63N/HSI1

-

75P/HSI3

-

75N/HSI3

NC

-

HSI5B_SOUTP

HSI3B_SOUTP

76P/HSI3

BK5_IO20

-

HSI1B_SOUTP

65P/HSI1

-

E27

C29

B30

A29

B28

A28

D26

C27

B27

-

HSI5B_SOUTN

124N/HSI5

125P

HSI3B_SOUTN

76N/HSI3

BK5_IO21

BK5_IO18

BK5_IO19

CFG0

DONE

PROGRAMb

BK6_IO0

BK6_IO1

BK6_IO2

-

HSI1B_SOUTN

65N/HSI1

-

77P/HSI3

-

64P/HSI1

-

125N

-

77N/HSI3

-

64N/HSI1

-

DONE

-

PROGRAMb

BK6_IO0

-

INITb

126P

INITb

78P

INITb

66P

BK6_IO1

CCLK

126N

CCLK

78N

CCLK

66N

BK6_IO2

-

127P

-

79P

-

67P

GND (Bank 6)

BK6_IO3

-

A27

C26

-

127N

-

79N

BK6_IO3

BK6_IO4

GND (Bank 6)

BK6_IO5

NC

-

67N

BK6_IO4

CSb

128P

CSb

80P

CSb

68P

-

B26

A26

C25

D24

B25

A25

-

BK6_IO5

Read

128N

BK6_IO5

NC

Read

80N

Read

68N

BK6_IO6

-

129P

-

BK6_IO7

-

129N

NC

-

NC

-

BK6_IO8

-

130P

NC

-

NC

-

BK6_IO9

-

130N

NC

-

NC

-

BK6_IO10

GND (Bank 6)

BK6_IO11

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

-

131P

NC

-

NC

-

C24

D23

B24

C23

A24

C22

B23

B22

-

131N

NC

-

NC

-

132P

NC

-

NC

-

132N

NC

-

NC

-

133P

NC

-

NC

-

133N

NC

-

NC

-

134P

NC

-

NC

-

134N

NC

-

NC

-

DATA7

-

135P

BK6_IO6

-

DATA7

-

81P

-

BK6_IO6

-

DATA7

-

69P

-

A23

DATA6

135N

BK6_IO7

DATA6

81N

BK6_IO7

DATA6

69N

77

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK6_IO20

BK6_IO21

BK6_IO22

-

Function

Reserved¹

Signal Name

BK6_IO8

BK6_IO9

BK6_IO10

GND (Bank 6)

BK6_IO11

BK6_IO12

-

Function

Reserved¹

Signal Name

BK6_IO8

BK6_IO9

BK6_IO10

-

Function

Reserved¹

D21

C21

B21

-

136P

136N

137P

-

82P

82N

83P

-

70P

VREF6

70N

DATA5

71P

-

A21

D20

-

BK6_IO23

BK6_IO24

-

DATA4

137N

138P

-

DATA4

83N

84P

-

BK6_IO11

BK6_IO12

GND (Bank 6)

BK6_IO13

BK6_IO14

-

DATA4

71N

-

72P

-

C20

B20

-

BK6_IO25

BK6_IO26

GND (Bank 6)

BK6_IO27

BK6_IO28

BK6_IO29

BK6_IO30

-

138N

139P

-

BK6_IO13

BK6_IO14

-

84N

85P

-

72N

DATA3

-

DATA3

73P

-

A20

C19

B19

A19

-

DATA2

139N

140P

140N

141P

-

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

BK6_IO22

-

DATA2

85N

86P

86N

87P

-

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

NC

DATA2

73N

-

74P

-

74N

DATA1

-

DATA1

75P

-

A18

D18

C18

B18

-

BK6_IO31

BK6_IO32

BK6_IO33

BK6_IO34

GND (Bank 6)

BK6_IO35

BK6_IO36

BK6_IO37

BK6_IO38

BK6_IO39

BK6_IO40

BK6_IO41

GND (Bank 6)

GND (Bank 7)

BK7_IO0

BK7_IO1

BK7_IO2

-

DATA0

141N

142P

142N

143P

-

DATA0

87N

88P

88N

89P

-

DATA0

75N

-

76P

76N

-

C17

B17

A17

D16

C16

B16

A16

-

143N

144P

144N

145P

145N

146P

146N

-

BK6_IO23

NC

89N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

BK6_IO24

BK6_IO25

GND (Bank 6)

GND (Bank 7)

BK7_IO0

BK7_IO1

BK7_IO2

-

90P

90N

-

NC

-

NC

-

77P

77N

78P

-

A15

B15

C15

-

147P

147N

148P

-

91P

91N

92P

-

BK7_IO0

BK7_IO1

BK7_IO2

GND (Bank 7)

BK7_IO3

BK7_IO4

BK7_IO5

NC

D15

A14

B14

C14

-

BK7_IO3

BK7_IO4

BK7_IO5

BK7_IO6

GND (Bank 7)

BK7_IO7

BK7_IO8

BK7_IO9

BK7_IO10

BK7_IO11

BK7_IO12

-

148N

149P

149N

150P

-

BK7_IO3

BK7_IO4

BK7_IO5

BK7_IO6

GND (Bank 7)

BK7_IO7

BK7_IO8

BK7_IO9

BK7_IO10

BK7_IO11

BK7_IO12

-

92N

93P

93N

94P

-

78N

79P

79N

-

A13

B13

C13

D13

B12

C12

-

150N

151P

151N

152P

152N

153P

-

94N

95P

95N

96P

96N

97P

-

NC

-

NC

-

NC

-

BK7_IO6

BK7_IO7

BK7_IO8

GND (Bank 7)

BK7_IO9

BK7_IO10

-

80P

80N

81P

-

A12

A11

-

BK7_IO13

BK7_IO14

GND (Bank 7)

BK7_IO15

BK7_IO16

BK7_IO17

153N

154P

-

BK7_IO13

BK7_IO14

GND (Bank 7)

BK7_IO15

NC

97N

98P

-

81N

82P

-

B11

C11

D11

154N

155P

155N

98N

-

BK7_IO11

NC

82N

-

NC

-

NC

-

78

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)

LFX500

LFX200

LFX125

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

LVDS Pair/

sysHSI

516-Ball

Second

BGA Ball

Signal Name

BK7_IO18

BK7_IO19

BK7_IO20

BK7_IO21

BK7_IO22

GND (Bank 7)

BK7_IO23

BK7_IO24

-

Function

Reserved¹

Signal Name

Function

Reserved¹

Signal Name

Function

Reserved¹

A10

B10

C10

D10

B9

-

156P

156N

157P

157N

158P

-

NC

-

NC

-

VREF7

BK7_IO16

BK7_IO17

BK7_IO18

-

VREF7

99P

BK7_IO12

BK7_IO13

BK7_IO14

-

VREF7

83P

-

99N

-

83N

100P

84P

-

C9

A8

-

158N

159P

-

BK7_IO19

BK7_IO20

-

100N

BK7_IO15

BK7_IO16

GND (Bank 7)

BK7_IO17

NC

84N

101P

85P

-

B8

C8

D8

A7

B7

C7

-

BK7_IO25

BK7_IO26

BK7_IO27

BK7_IO28

BK7_IO29

BK7_IO30

GND (Bank 7)

BK7_IO31

BK7_IO32

BK7_IO33

BK7_IO34

BK7_IO35

BK7_IO36

BK7_IO37

BK7_IO38

GND (Bank 7)

BK7_IO39

BK7_IO40

BK7_IO41

TDO

159N

160P

160N

161P

161N

162P

-

BK7_IO21

NC

101N

85N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

D7

A6

B6

B5

C6

A5

A4

B4

-

162N

163P

163N

164P

164N

165P

165N

166P

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

86P

-

BK7_IO22

GND (Bank 7)

BK7_IO23

BK7_IO24

BK7_IO25

TDO

102P

BK7_IO18

-

C5

A3

A2

D5

C4

B3

166N

167P

167N

-

102N

BK7_IO19

BK7_IO20

BK7_IO21

TDO

86N

87P

87N

-

103P

103N

-

VCCJ

-

VCCJ

TDI

VCCJ

TDI

-

TDI

-

1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use.

79

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA

LFX1200

680-Ball fpBGA

Signal Name

BK0_IO0

Second Function

LVDS Pair/sysHSI Reserved¹

C4

B4

E6

-

0P

0N

1P

BK0_IO1

-

BK0_IO2

-

GND (Bank 0)

BK0_IO3

-

D6

A4

E8

C5

C6

A6

A5

B6

-

1N

BK0_IO4

-

2P

BK0_IO5

-

2N

BK0_IO6

HSI0A_SOUTP

3P

BK0_IO7

HSI0A_SOUTN

3N

BK0_IO8

-

4P

BK0_IO9

-

4N

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

BK0_IO23

BK0_IO24

BK0_IO25

BK0_IO26

GND (Bank 0)

BK0_IO27

BK0_IO28

BK0_IO29

BK0_IO30

BK0_IO31

BK0_IO32

BK0_IO33

BK0_IO34

GND (Bank 0)

BK0_IO35

BK0_IO36

HSI0A_SINP

5P/HSI0

-

B5

B7

A7

D8

D7

D9

E10

C8

-

HSI0A_SINN

5N/HSI0

6P/HSI0

6N/HSI0

7P/HSI0

7N/HSI0

8P/HSI0

8N/HSI0

9P/HSI0

-

VREF0

-

HSI0B_SOUTP

HSI0B_SOUTN

-

HSI0B_SINP

-

C7

A8

A9

C9

B8

B9

B10

D11

-

HSI0B_SINN

9N/HSI0

10P/HSI0

10N/HSI0

11P/HSI0

11N/HSI0

12P/HSI0

12N/HSI0

13P/HSI1

-

HSI1A_SOUTP

HSI1A_SOUTN

-

HSI1A_SINP

-

D10

A10

C12

D12

C11

A12

A13

B13

-

HSI1A_SINN

13N/HSI1

14P/HSI1

14N/HSI1

15P/HSI1

15N/HSI1

16P/HSI1

16N/HSI1

17P/HSI1

-

HSI1B_SOUTP

HSI1B_SOUTN

-

HSI1B_SINP

-

B12

E14

HSI1B_SINN

-

17N/HSI1

18P/HSI1

80

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

D14

C13

D13

B14

A14

C15

-

Signal Name

BK0_IO37

BK0_IO38

BK0_IO39

BK0_IO40

BK0_IO41

BK0_IO42

GND (Bank 0)

BK0_IO43

BK0_IO44

BK0_IO45

BK0_IO46

BK0_IO47

BK0_IO48

BK0_IO49

BK0_IO50

GND (Bank 0)

BK0_IO51

BK0_IO52

BK0_IO53

BK0_IO54

BK0_IO55

BK0_IO56

BK0_IO57

BK0_IO58

GND (Bank 0)

BK0_IO59

BK0_IO60

BK0_IO61

GND (Bank 0)

GCLK0

Second Function

LVDS Pair/sysHSI Reserved¹

-

18N/HSI1

19P/HSI1

19N/HSI1

20P/HSI1

20N/HSI1

21P/HSI2

-

HSI2A_SOUTP

HSI2A_SOUTN

-

HSI2A_SINP

-

D15

A15

C16

B15

B16

A16

B17

D16

-

HSI2A_SINN

21N/HSI2

22P/HSI2

22N/HSI2

23P/HSI2

23N/HSI2

24P/HSI2

24N/HSI2

25P/HSI2

-

HSI2B_SOUTP

HSI2B_SOUTN

-

HSI2B_SINP

-

E16

D17

C17

A18

D18

A17

E19

A19

-

HSI2B_SINN

25N/HSI2

26P/HSI2

26N/HSI2

27P/HSI2

27N/HSI2

28P/HSI2

28N/HSI2

29P

-

PLL_RST0

PLL_RST1

-

PLL_FBK0

-

B19

C18

B18

-

PLL_FBK1

29N

CLK_OUT0

30P

CLK_OUT1

30N

-

D19

C19

E20

A21

B21

C21

B23

C23

B22

-

LVDS Pair0P

LVDS Pair0N

-

GCLK1

-

VCCP0

-

GNDP0

-

GCLK2

LVDS Pair1P

LVDS Pair1N

31P

GCLK3

-

BK1_IO0

CLK_OUT2

CLK_OUT3

SS_CLKOUT0P

-

BK1_IO1

31N

BK1_IO2

32P

GND (Bank 1)

BK1_IO3

-

C22

D21

E21

B24

SS_CLKOUT0N

PLL_FBK2

PLL_FBK3

SS_CLKIN0P

32N

BK1_IO4

33P

BK1_IO5

33N

BK1_IO6

34P

81

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

C24

A22

D22

A23

-

Signal Name

BK1_IO7

Second Function

LVDS Pair/sysHSI Reserved¹

34N

SS_CLKIN0N

BK1_IO8

-

35P

BK1_IO9

-

35N

BK1_IO10

GND (Bank 1)

BK1_IO11

BK1_IO12

BK1_IO13

BK1_IO14

BK1_IO15

BK1_IO16

BK1_IO17

BK1_IO18

GND (Bank 1)

BK1_IO19

BK1_IO20

BK1_IO21

BK1_IO22

BK1_IO23

BK1_IO24

BK1_IO25

BK1_IO26

GND (Bank 1)

BK1_IO27

BK1_IO28

BK1_IO29

BK1_IO30

BK1_IO31

BK1_IO32

BK1_IO33

BK1_IO34

GND (Bank 1)

BK1_IO35

BK1_IO36

BK1_IO37

BK1_IO38

BK1_IO39

BK1_IO40

BK1_IO41

BK1_IO42

GND (Bank 1)

BK1_IO43

BK1_IO44

-

36P

-

B25

D23

A24

A25

E24

D24

A26

D25

-

36N

PLL_RST2

37P

PLL_RST3

37N

-

38P

-

38N

-

39P

-

39N

-

40P

-

C25

B26

B27

D26

A27

A28

E26

C27

-

40N

-

41P/HSI3

41N/HSI3

42P/HSI3

42N/HSI3

43P/HSI3

43N/HSI3

44P/HSI3

-

HSI3A_SOUTP

-

D27

B28

A30

C28

D28

A31

B30

E28

-

HSI3A_SOUTN

44N/HSI3

45P/HSI3

45N/HSI3

46P/HSI3

46N/HSI3

47P/HSI3

47N/HSI3

48P/HSI3

-

HSI3A_SINP

HSI3A_SINN

-

HSI3B_SOUTP

-

D29

C29

B31

D30

E30

A32

C31

D31

-

HSI3B_SOUTN

48N/HSI3

49P/HSI4

49N/HSI4

50P/HSI4

50N/HSI4

51P/HSI4

51N/HSI4

52P/HSI4

-

HSI3B_SINP

HSI3B_SINN

-

HSI4A_SOUTP

-

C32

B32

HSI4A_SOUTN

-

52N/HSI4

53P/HSI4

82

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

A33

C33

B33

A34

A35

D32

-

Signal Name

BK1_IO45

BK1_IO46

BK1_IO47

BK1_IO48

BK1_IO49

BK1_IO50

GND (Bank 1)

BK1_IO51

BK1_IO52

BK1_IO53

BK1_IO54

BK1_IO55

BK1_IO56

BK1_IO57

BK1_IO58

GND (Bank 1)

BK1_IO59

BK1_IO60

BK1_IO61

TCK

Second Function

LVDS Pair/sysHSI Reserved¹

-

53N/HSI4

54P/HSI4

54N/HSI4

55P/HSI4

55N/HSI4

56P/HSI4

-

HSI4A_SINP

HSI4A_SINN

-

VREF1

HSI4B_SOUTP

-

D33

E32

C34

B34

B35

A36

D34

C35

-

HSI4B_SOUTN

56N/HSI4

57P

-

57N

58P

HSI4B_SINP

HSI4B_SINN

58N

59P

-

59N

60P

-

E34

B36

C36

D39

D37

D38

E37

F35

E39

-

60N

61P

-

61N

-

TMS

-

TOE

-

BK2_IO0

-

62P

BK2_IO1

-

62N

63P

BK2_IO2

-

GND (Bank 2)

BK2_IO3

-

F39

F36

E38

G38

F37

G36

G39

H35

-

63N

64P

BK2_IO4

-

BK2_IO5

-

64N

65P

BK2_IO6

-

BK2_IO7

-

65N

66P

BK2_IO8

-

BK2_IO9

-

66N

67P

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

-

F38

J37

-

67N

68P

VREF2

H36

G37

H37

H39

K35

J36

-

68N

69P

69N

70P

70N

71P

83

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

-

Signal Name

GND (Bank 2)

BK2_IO19

BK2_IO20

BK2_IO21

BK2_IO22

BK2_IO23

BK2_IO24

BK2_IO25

BK2_IO26

GND (Bank 2)

BK2_IO27

BK2_IO28

BK2_IO29

BK2_IO30

BK2_IO31

BK2_IO32

BK2_IO33

BK2_IO34

GND (Bank 2)

BK2_IO35

BK2_IO36

BK2_IO37

BK2_IO38

BK2_IO39

BK2_IO40

BK2_IO41

BK2_IO42

GND (Bank 2)

BK2_IO43

BK2_IO44

BK2_IO45

BK2_IO46

BK2_IO47

BK2_IO48

BK2_IO49

BK2_IO50

GND (Bank 2)

BK2_IO51

BK2_IO52

BK2_IO53

BK2_IO54

BK2_IO55

BK2_IO56

Second Function

LVDS Pair/sysHSI Reserved¹

-

K36

H38

J38

J39

L36

K38

M36

L37

-

71N

72P

72N

73P

73N

74P

74N

75P

-

K39

L38

P35

N36

M37

L39

M38

M39

-

75N

76P

76N

77P

77N

78P

78N

79P

-

P36

R36

N37

P38

T35

R37

R38

P39

-

79N

80P

80N

81P

81N

82P

82N

83P

-

R39

T38

T36

T37

U36

U37

T39

V36

-

83N

84P

84N

85P

85N

86P

86N

87P

-

U38

U39

V38

V37

W36

W35

87N

88P

88N

89P

89N

90P

84

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

V39

Signal Name

BK2_IO57

BK2_IO58

GND (Bank 2)

BK2_IO59

BK2_IO60

BK2_IO61

GND (Bank 2)

GND (Bank 3)

BK3_IO0

Second Function

LVDS Pair/sysHSI Reserved¹

-

90N

91P

-

W37

-

W38

W39

AA39

-

91N

92P

92N

-

AA38

Y35

93P

93N

94P

-

BK3_IO1

AA37

-

BK3_IO2

GND (Bank 3)

BK3_IO3

AA35

AB39

AB38

AA36

AB37

AC39

AC38

AB36

-

94N

95P

95N

96P

96N

97P

97N

98P

-

BK3_IO4

BK3_IO5

BK3_IO6

BK3_IO7

BK3_IO8

BK3_IO9

BK3_IO10

GND (Bank 3)

BK3_IO11

BK3_IO12

BK3_IO13

BK3_IO14

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

GND (Bank 3)

BK3_IO19

BK3_IO20

BK3_IO21

BK3_IO22

BK3_IO23

BK3_IO24

BK3_IO25

BK3_IO26

GND (Bank 3)

BK3_IO27

BK3_IO28

BK3_IO29

BK3_IO30

AC37

AC36

AD39

AD37

AD36

AD35

AE38

AD38

-

98N

99P

99N

100P

100N

101P

101N

102P

-

AE39

AF38

AF37

AF39

AE36

AF36

AG38

AG39

-

102N

103P

103N

104P

104N

105P

105N

106P

-

AG37

AH37

AH38

AG36

106N

107P

107N

108P

85

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

AH39

AK39

AK38

AF35

-

Signal Name

BK3_IO31

BK3_IO32

BK3_IO33

BK3_IO34

GND (Bank 3)

BK3_IO35

BK3_IO36

BK3_IO37

BK3_IO38

BK3_IO39

BK3_IO40

BK3_IO41

BK3_IO42

GND (Bank 3)

BK3_IO43

BK3_IO44

BK3_IO45

BK3_IO46

BK3_IO47

BK3_IO48

BK3_IO49

BK3_IO50

GND (Bank 3)

BK3_IO51

BK3_IO52

BK3_IO53

BK3_IO54

BK3_IO55

BK3_IO56

BK3_IO57

BK3_IO58

GND (Bank 3)

BK3_IO59

BK3_IO60

BK3_IO61

GSR

Second Function

LVDS Pair/sysHSI Reserved¹

-

108N

109P

109N

110P

-

AJ37

AH36

AM39

AL38

AL39

AJ36

AH35

AL37

-

110N

111P

111N

112P

112N

113P

113N

114P

-

AN38

AM38

AK36

AM37

AN37

AN39

AL36

AK35

-

114N

115P

115N

116P

116N

117P

117N

118P

-

VREF3

-

AP39

AM36

AP38

AR39

AN36

AM35

AR38

AP37

-

118N

119P

119N

120P

120N

121P

121N

122P

-

AT39

AR37

AP36

AT38

AP35

AT37

AU36

AV36

AR34

-

122N

123P

123N

-

DXP

-

DXN

-

BK4_IO0

124P

124N

125P

-

BK4_IO1

BK4_IO2

GND (Bank 4)

BK4_IO3

AW36

125N

86

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

AW35

AV35

AV34

AU34

AT34

AU35

AT33

-

Signal Name

BK4_IO4

Second Function

LVDS Pair/sysHSI Reserved¹

126P

-

BK4_IO5

-

126N

BK4_IO6

HSI5A_SINP

127P

BK4_IO7

HSI5A_SINN

127N

BK4_IO8

-

128P

BK4_IO9

-

128N

BK4_IO10

GND (Bank 4)

BK4_IO11

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15

BK4_IO16

BK4_IO17

BK4_IO18

GND (Bank 4)

BK4_IO19

BK4_IO20

BK4_IO21

BK4_IO22

BK4_IO23

BK4_IO24

BK4_IO25

BK4_IO26

GND (Bank 4)

BK4_IO27

BK4_IO28

BK4_IO29

BK4_IO30

BK4_IO31

BK4_IO32

BK4_IO33

BK4_IO34

GND (Bank 4)

BK4_IO35

BK4_IO36

BK4_IO37

BK4_IO38

BK4_IO39

BK4_IO40

BK4_IO41

BK4_IO42

HSI5A_SOUTP

129P/HSI5

-

AU33

AW34

AV33

AR32

AT32

AU32

AW33

AV32

-

HSI5A_SOUTN

129N/HSI5

130P/HSI5

130N/HSI5

131P/HSI5

131N/HSI5

132P/HSI5

132N/HSI5

133P/HSI5

-

VREF4

-

HSI5B_SINP

HSI5B_SINN

-

HSI5B_SOUTP

-

AV31

AU31

AW32

AR30

AT31

AW31

AV30

AT30

-

HSI5B_SOUTN

133N/HSI5

134P/HSI5

134N/HSI5

135P/HSI5

135N/HSI5

136P/HSI5

136N/HSI5

137P/HSI6

-

HSI6A_SINP

HSI6A_SINN

-

HSI6A_SOUTP

-

AT29

AW30

AU29

AT28

AU28

AV28

AT27

AU27

-

HSI6A_SOUTN

137N/HSI6

138P/HSI6

138N/HSI6

139P/HSI6

139N/HSI6

140P/HSI6

140N/HSI6

141P/HSI6

-

HSI6B_SINP

HSI6B_SINN

-

HSI6B_SOUTP

-

AV27

AW28

AR26

AW27

AT26

AV26

AR24

AT25

HSI6B_SOUTN

141N/HSI6

142P/HSI6

142N/HSI6

143P/HSI6

143N/HSI6

144P/HSI6

144N/HSI6

145P/HSI6

-

87

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

-

Signal Name

GND (Bank 4)

BK4_IO43

BK4_IO44

BK4_IO45

BK4_IO46

BK4_IO47

BK4_IO48

BK4_IO49

BK4_IO50

GND (Bank 4)

BK4_IO51

BK4_IO52

BK4_IO53

BK4_IO54

BK4_IO55

BK4_IO56

BK4_IO57

BK4_IO58

GND (Bank 4)

BK4_IO59

BK4_IO60

BK4_IO61

GND (Bank 4)

GCLK4

Second Function

LVDS Pair/sysHSI Reserved¹

-

145N

AW26

AV25

AT24

AU24

AU25

AW25

AW24

AU23

-

146P

-

146N

-

147P

-

147N

PLL_RST4

148P

PLL_RST5

148N

-

149P

-

AT23

AV24

AW23

AV23

AU22

AR21

AT22

AV22

-

149N

-

150P

-

150N

SS_CLKIN1P

151P

SS_CLKIN1N

151N

PLL_FBK4

152P

PLL_FBK5

152N

SS_CLKOUT1P

153P

-

AV21

AT21

AU21

-

SS_CLKOUT1N

153N

CLK_OUT4

154P

CLK_OUT5

154N

-

AT19

AU19

AW22

AR20

AU18

AT18

-

LVDS Pair2P

LVDS Pair2N

-

GCLK5

-

VCCP1

-

GNDP1

-

GCLK6

-

LVDS Pair3P

LVDS Pair3N

-

GCLK7

-

GND (Bank 5)

BK5_IO0

-

AV17

AV18

AW21

-

CLK_OUT6

155P

BK5_IO1

CLK_OUT7

155N

BK5_IO2

PLL_FBK6

156P

GND (Bank 5)

BK5_IO3

-

AV19

AR19

AW19

AW18

AW17

AT17

AV16

AU17

-

PLL_FBK7

156N

BK5_IO4

-

157P/HSI7

157N/HSI7

158P/HSI7

158N/HSI7

159P/HSI7

159N/HSI7

160P/HSI7

-

BK5_IO5

-

BK5_IO6

PLL_RST6

BK5_IO7

PLL_RST7

BK5_IO8

-

BK5_IO9

-

BK5_IO10

GND (Bank 5)

HSI7A_SINP

-

88

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

AT16

AW16

AU16

AV14

AV15

AU15

AW15

AT15

-

Signal Name

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

GND (Bank 5)

BK5_IO19

BK5_IO20

BK5_IO21

BK5_IO22

BK5_IO23

BK5_IO24

BK5_IO25

BK5_IO26

GND (Bank 5)

BK5_IO27

BK5_IO28

BK5_IO29

BK5_IO30

BK5_IO31

BK5_IO32

BK5_IO33

BK5_IO34

GND (Bank 5)

BK5_IO35

BK5_IO36

BK5_IO37

BK5_IO38

BK5_IO39

BK5_IO40

BK5_IO41

BK5_IO42

GND (Bank 5)

BK5_IO43

BK5_IO44

BK5_IO45

BK5_IO46

BK5_IO47

BK5_IO48

BK5_IO49

Second Function

LVDS Pair/sysHSI Reserved¹

160N/HSI7

161P/HSI7

161N/HSI7

162P/HSI7

162N/HSI7

163P/HSI7

163N/HSI7

164P/HSI7

-

HSI7A_SINN

-

HSI7A_SOUTP

HSI7A_SOUTN

-

HSI7B_SINP

-

AR16

AW14

AW13

AR14

AT14

AT13

AV13

AU12

-

HSI7B_SINN

164N/HSI7

165P/HSI8

165N/HSI8

166P/HSI8

166N/HSI8

167P/HSI8

167N/HSI8

168P/HSI8

-

HSI7B_SOUTP

HSI7B_SOUTN

-

HSI8A_SINP

-

AU13

AV12

AT12

AR12

AT11

AW12

AU11

AV9

HSI8A_SINN

168N/HSI8

169P/HSI8

169N/HSI8

170P/HSI8

170N/HSI8

171P/HSI8

171N/HSI8

172P/HSI8

-

HSI8A_SOUTP

HSI8A_SOUTN

-

HSI8B_SINP

-

AV10

AW10

AW9

AT10

AU9

HSI8B_SINN

172N/HSI8

173P/HSI9

173N/HSI9

174P/HSI9

174N/HSI9

175P/HSI9

175N/HSI9

176P/HSI9

-

HSI8B_SOUTP

HSI8B_SOUTN

AT9

-

AR10

AU8

-

HSI9A_SINP

-

AV8

HSI9A_SINN

176N/HSI9

177P/HSI9

177N/HSI9

178P/HSI9

178N/HSI9

179P/HSI9

179N/HSI9

AW8

AW7

AU7

-

HSI9A_SOUTP

HSI9A_SOUTN

-

AT8

AV7

AW6

VREF5

89

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

AU6

-

Signal Name

BK5_IO50

GND (Bank 5)

BK5_IO51

BK5_IO52

BK5_IO53

BK5_IO54

BK5_IO55

BK5_IO56

BK5_IO57

BK5_IO58

GND (Bank 5)

BK5_IO59

BK5_IO60

BK5_IO61

CFG0

Second Function

LVDS Pair/sysHSI Reserved¹

HSI9B_SINP

180P/HSI9

-

AV6

AR8

AT7

AU5

AV5

AW5

AW4

AT6

-

HSI9B_SINN

180N/HSI9

181P

181N

182P

182N

183P

183N

184P

-

HSI9B_SOUTP

HSI9B_SOUTN

-

AV4

AR6

AU4

AT1

AT3

AT2

AP4

AP5

AR3

-

184N

185P

185N

-

DONE

-

PROGRAMb

BK6_IO0

-

INITb

186P

186N

187P

-

BK6_IO1

CCLK

BK6_IO2

-

GND (Bank 6)

BK6_IO3

-

AR2

AP3

AR1

AP2

AP1

AN4

AM5

AN3

-

187N

188P

188N

189P

189N

190P

190N

191P

-

BK6_IO4

CSb

BK6_IO5

Read

BK6_IO6

-

BK6_IO7

-

BK6_IO8

-

BK6_IO9

-

BK6_IO10

GND (Bank 6)

BK6_IO11

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

BK6_IO22

-

AN2

AM4

AM3

AN1

AM2

AL4

AK5

AM1

-

191N

192P

192N

193P

193N

194P

194N

195P

-

VREF6

-

AK4

AL3

AL2

AL1

195N

196P

196N

197P

90

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

AK2

AK1

AJ4

AJ3

-

Signal Name

BK6_IO23

BK6_IO24

BK6_IO25

BK6_IO26

GND (Bank 6)

BK6_IO27

BK6_IO28

BK6_IO29

BK6_IO30

BK6_IO31

BK6_IO32

BK6_IO33

BK6_IO34

GND (Bank 6)

BK6_IO35

BK6_IO36

BK6_IO37

BK6_IO38

BK6_IO39

BK6_IO40

BK6_IO41

BK6_IO42

GND (Bank 6)

BK6_IO43

BK6_IO44

BK6_IO45

BK6_IO46

BK6_IO47

BK6_IO48

BK6_IO49

BK6_IO50

GND (Bank 6)

BK6_IO51

BK6_IO52

BK6_IO53

BK6_IO54

BK6_IO55

BK6_IO56

BK6_IO57

BK6_IO58

GND (Bank 6)

BK6_IO59

BK6_IO60

Second Function

LVDS Pair/sysHSI Reserved¹

-

197N

198P

198N

199P

-

AH4

AH3

AH2

AH1

AG4

AF5

AG3

AG2

-

199N

200P

200N

201P

201N

202P

202N

203P

-

DATA7

DATA6

-

AF4

AF3

AG1

AE2

AF1

AF2

AE1

AE4

-

203N

204P

204N

205P

205N

206P

206N

207P

-

DATA5

DATA4

-

AD4

AD5

AD3

AD2

AD1

AC4

AC3

AC2

-

207N

208P

208N

209P

209N

210P

210N

211P

-

DATA3

-

AC1

AB3

AB4

AB2

AB1

AA3

AA4

AA5

-

DATA2

211N

212P

212N

213P

213N

214P

214N

215P

-

DATA1

DATA0

-

AA2

AA1

215N

216P

91

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

Signal Name

BK6_IO61

GND (Bank 6)

GND (Bank 7)

BK7_IO0

Second Function

LVDS Pair/sysHSI Reserved¹

Y5

-

216N

-

W3

W1

W2

-

217P

217N

218P

-

BK7_IO1

BK7_IO2

GND (Bank 7)

BK7_IO3

W4

V1

V2

V3

V4

W5

U1

U2

-

218N

219P

219N

220P

220N

221P

221N

222P

-

BK7_IO4

BK7_IO5

BK7_IO6

BK7_IO7

BK7_IO8

BK7_IO9

BK7_IO10

GND (Bank 7)

BK7_IO11

BK7_IO12

BK7_IO13

BK7_IO14

BK7_IO15

BK7_IO16

BK7_IO17

BK7_IO18

GND (Bank 7)

BK7_IO19

BK7_IO20

BK7_IO21

BK7_IO22

BK7_IO23

BK7_IO24

BK7_IO25

BK7_IO26

GND (Bank 7)

BK7_IO27

BK7_IO28

BK7_IO29

BK7_IO30

BK7_IO31

BK7_IO32

BK7_IO33

BK7_IO34

GND (Bank 7)

U3

U4

T1

T2

T3

R1

R2

T4

-

222N

223P

223N

224P

224N

225P

225N

226P

-

P1

P2

P3

R4

T5

M1

M2

N3

-

226N

227P

227N

228P

228N

229P

229N

230P

-

P4

L1

M3

L2

N4

K1

K2

P5

-

230N

231P

231N

232P

232N

233P

233N

234P

-

92

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)

LFX1200

680-Ball fpBGA

Signal Name

BK7_IO35

BK7_IO36

BK7_IO37

BK7_IO38

BK7_IO39

BK7_IO40

BK7_IO41

BK7_IO42

GND (Bank 7)

BK7_IO43

BK7_IO44

BK7_IO45

BK7_IO46

BK7_IO47

BK7_IO48

BK7_IO49

BK7_IO50

GND (Bank 7)

BK7_IO51

BK7_IO52

BK7_IO53

BK7_IO54

BK7_IO55

BK7_IO56

BK7_IO57

BK7_IO58

GND (Bank 7)

BK7_IO59

BK7_IO60

BK7_IO61

TDO

Second Function

LVDS Pair/sysHSI Reserved¹

L3

J1

J2

M4

H1

J3

L4

M5

-

234N

235P

235N

236P

236N

237P

237N

238P

-

H2

K4

G1

H3

J4

K5

G3

H4

-

238N

239P

239N

240P

240N

241P

241N

242P

-

VREF7

-

F2

G2

H5

F3

F1

G4

E1

F4

-

242N

243P

243N

244P

244N

245P

245N

246P

-

E2

F5

E3

D2

D3

D1

246N

247P

247N

-

VCCJ

-

TDI

-

1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use.

93

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK0_IO0

Function

sysHSI Reserved¹

Signal Name

Function

sysHSI Reserved¹

D3

E3

C2

-

0P

0N

NC

-

BK0_IO1

-

NC

-

BK0_IO2

-

1P

NC

-

GND (Bank 0)

BK0_IO3

-

C1

E4

F5

D2

-

1N

NC

-

BK0_IO4

-

2P

BK0_IO0

BK0_IO1

BK0_IO2

GND (Bank 0)

BK0_IO3

BK0_IO4

BK0_IO5

BK0_IO6

-

0P

BK0_IO5

-

2N

-

0N

BK0_IO6

HSI0A_SOUTP

3P

HSI0A_SOUTP

1P/HSI0

-

D1

F4

F3

E2

-

BK0_IO7

HSI0A_SOUTN

3N

HSI0A_SOUTN

1N/HSI0

BK0_IO8

-

4P

-

2P/HSI0

BK0_IO9

-

4N

-

2N/HSI0

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

BK0_IO23

BK0_IO24

BK0_IO25

BK0_IO26

GND (Bank 0)

BK0_IO27

BK0_IO28

BK0_IO29

BK0_IO30

-

HSI0A_SINP

5P/HSI0

-

HSI0A_SINP

3P/HSI0

-

E1

G6

G5

F1

F2

G4

G3

G2

-

HSI0A_SINN

5N/HSI0

6P/HSI0

6N/HSI0

7P/HSI0

7N/HSI0

8P/HSI0

8N/HSI0

9P/HSI0

-

BK0_IO7

BK0_IO9

BK0_IO8

NC

HSI0A_SINN

3N/HSI0

VREF0

4N/HSI0

-

4P/HSI0

HSI0B_SOUTP

-

HSI0B_SOUTN

NC

-

NC

-

NC

-

HSI0B_SINP

NC

-

G1

H3

H4

H1

H2

J7

J6

J1

-

HSI0B_SINN

9N/HSI0

10P/HSI0

10N/HSI0

11P/HSI0

11N/HSI0

12P/HSI0

12N/HSI0

13P/HSI1

-

NC

-

NC

-

NC

-

HSI1A_SOUTP

NC

-

HSI1A_SOUTN

NC

-

NC

-

NC

-

HSI1A_SINP

NC

-

J2

J4

J5

K1

-

HSI1A_SINN

13N/HSI1

14P/HSI1

14N/HSI1

15P/HSI1

-

NC

-

NC

-

NC

-

HSI1B_SOUTP

BK0_IO10

GND (Bank 0)

BK0_IO11

BK0_IO12

BK0_IO13

BK0_IO14

-

HSI0B_SOUTP

5P/HSI0

-

K2

K5

K4

L1

-

BK0_IO31

BK0_IO32

BK0_IO33

BK0_IO34

GND (Bank 0)

HSI1B_SOUTN

15N/HSI1

16P/HSI1

16N/HSI1

17P/HSI1

-

HSI0B_SOUTN

5N/HSI0

6P/HSI0

6N/HSI0

7P/HSI0

-

HSI1B_SINP

-

HSI0B_SINP

-

94

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK0_IO35

BK0_IO36

BK0_IO37

BK0_IO38

-

Function

sysHSI Reserved¹

Signal Name

BK0_IO15

BK0_IO16

BK0_IO17

BK0_IO18

GND (Bank 0)

BK0_IO19

BK0_IO20

BK0_IO21

BK0_IO22

-

Function

sysHSI Reserved¹

L2

L6

L5

M1

-

HSI1B_SINN

17N/HSI1

18P/HSI1

18N/HSI1

19P/HSI1

-

HSI0B_SINN

7N/HSI0

8P/HSI0

8N/HSI0

9P/HSI1

-

HSI2A_SOUTP

HSI1A_SOUTP

-

M2

L3

L4

M6

-

BK0_IO39

BK0_IO40

BK0_IO41

BK0_IO42

GND (Bank 0)

BK0_IO43

BK0_IO44

BK0_IO45

BK0_IO46

-

HSI2A_SOUTN

19N/HSI1

20P/HSI1

20N/HSI1

21P/HSI2

-

HSI1A_SOUTN

9N/HSI1

10P/HSI1

10N/HSI1

11P/HSI1

-

HSI2A_SINP

HSI1A_SINP

-

M5

M4

M3

N1

-

HSI2A_SINN

21N/HSI2

22P/HSI2

22N/HSI2

23P/HSI2

-

BK0_IO23

BK0_IO24

BK0_IO25

BK0_IO26

GND (Bank 0)

BK0_IO27

BK0_IO28

BK0_IO29

BK0_IO30

-

HSI1A_SINN

11N/HSI1

12P/HSI1

12N/HSI1

13P/HSI1

-

HSI2B_SOUTP

HSI1B_SOUTP

-

N2

N7

N6

P1

-

BK0_IO47

BK0_IO48

BK0_IO49

BK0_IO50

GND (Bank 0)

BK0_IO51

BK0_IO52

BK0_IO53

BK0_IO54

BK0_IO55

BK0_IO56

BK0_IO57

BK0_IO58

GND (Bank 0)

BK0_IO59

BK0_IO60

-

HSI2B_SOUTN

23N/HSI2

24P/HSI2

24N/HSI2

25P/HSI2

-

HSI1B_SOUTN

13N/HSI1

14P/HSI1

14N/HSI1

15P/HSI1

-

HSI2B_SINP

HSI1B_SINP

-

P2

N3

N4

P6

P5

P3

P4

R7

-

HSI2B_SINN

25N/HSI2

26P/HSI2

26N/HSI2

27P/HSI2

27N/HSI2

28P/HSI2

28N/HSI2

29P

BK0_IO31

BK0_IO32

BK0_IO33

BK0_IO38

BK0_IO35

BK0_IO36

BK0_IO39

BK0_IO34

GND (Bank 0)

BK0_IO37

BK0_IO40

GND (Bank 0)

BK0_IO41

-

HSI1B_SINN

15N/HSI1

16P/HSI1

16N/HSI1

19P

-

PLL_RST0

PLL_RST1

17N

-

18P

-

19N

PLL_FBK0

17P

-

R6

R1

-

PLL_FBK1

29N

PLL_FBK1

18N

CLK_OUT0

30P

CLK_OUT0

20P

-

R2

-

BK0_IO61

GND (Bank 0)

GCLK0

CLK_OUT1

30N

CLK_OUT1

20N

-

R3

R4

R5

T3

T4

T5

-

LVDS Pair0P

LVDS Pair0N

-

GCLK0

-

LVDS Pair0P

LVDS Pair0N

-

GCLK1

-

GCLK1

-

VCCP0

-

VCCP0

-

GNDP0

-

GNDP0

-

GCLK2

-

LVDS Pair1P

LVDS Pair1N

-

GCLK2

-

LVDS Pair1P

LVDS Pair1N

-

GCLK3

-

GCLK3

-

GND (Bank 1)

BK1_IO0

-

T2

CLK_OUT2

31P

BK1_IO0

CLK_OUT2

21P

95

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

-

Function

sysHSI Reserved¹

Signal Name

GND (Bank 1)

BK1_IO1

BK1_IO2

-

Function

sysHSI Reserved¹

-

31N

-

21N

22P

-

T1

U2

-

BK1_IO1

BK1_IO2

GND (Bank 1)

BK1_IO3

BK1_IO4

BK1_IO5

BK1_IO6

BK1_IO7

BK1_IO8

BK1_IO9

BK1_IO10

GND (Bank 1)

BK1_IO11

BK1_IO12

BK1_IO13

BK1_IO14

BK1_IO15

BK1_IO16

-

CLK_OUT3

SS_CLKOUT0P

32P

SS_CLKOUT0P

-

U1

U3

U4

V1

V2

U5

U6

V4

-

SS_CLKOUT0N

32N

BK1_IO3

BK1_IO4

BK1_IO5

BK1_IO10

BK1_IO11

BK1_IO12

BK1_IO13

BK1_IO6

GND (Bank 1)

BK1_IO7

BK1_IO20

BK1_IO21

BK1_IO8

BK1_IO9

BK1_IO14

GND (Bank 1)

BK1_IO15

BK1_IO16

-

SS_CLKOUT0N

22N

23P

23N

26P

26N

27P

27N

24P

-

PLL_FBK2

33P

PLL_FBK2

PLL_FBK3

33N

PLL_FBK3

SS_CLKIN0P

34P

SS_CLKIN0P

SS_CLKIN0N

34N

SS_CLKIN0N

-

35P

-

35N

-

36P

-

V3

V6

V7

W1

W2

W3

-

36N

-

24N

31P

31N

25P

25N

28P

-

PLL_RST2

37P

PLL_RST2

PLL_RST3

37N

PLL_RST3

-

38P

-

38N

-

39P

-

W4

W5

-

BK1_IO17

BK1_IO18

GND (Bank 1)

BK1_IO19

BK1_IO20

BK1_IO21

BK1_IO22

BK1_IO23

BK1_IO24

BK1_IO25

BK1_IO26

GND (Bank 1)

BK1_IO27

BK1_IO28

BK1_IO29

BK1_IO30

-

39N

-

28N

29P

-

40P

-

W6

Y6

Y5

Y4

Y3

AA5

AA4

Y2

-

40N

BK1_IO17

NC

-

29N

-

41P/HSI3

41N/HSI3

42P/HSI3

42N/HSI3

43P/HSI3

43N/HSI3

44P/HSI3

-

NC

-

NC

-

NC

-

NC

-

NC

-

HSI3A_SOUTP

BK1_IO18

-

HSI2A_SOUTP

30P

-

Y1

AB7

AB6

AA2

-

HSI3A_SOUTN

44N/HSI3

45P/HSI3

45N/HSI3

46P/HSI3

-

BK1_IO19

NC

HSI2A_SOUTN

30N

-

NC

-

HSI3A_SINP

BK1_IO22

GND (Bank 1)

BK1_IO23

NC

HSI2A_SINP

32P

-

AA1

AB5

AB4

AB2

-

BK1_IO31

BK1_IO32

BK1_IO33

BK1_IO34

GND (Bank 1)

HSI3A_SINN

46N/HSI3

47P/HSI3

47N/HSI3

48P/HSI3

-

HSI2A_SINN

32N

-

NC

-

HSI3B_SOUTP

-

NC

-

96

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK1_IO35

BK1_IO36

BK1_IO37

BK1_IO38

BK1_IO39

BK1_IO40

BK1_IO41

BK1_IO42

GND (Bank 1)

BK1_IO43

BK1_IO44

BK1_IO45

BK1_IO46

BK1_IO47

BK1_IO48

BK1_IO49

BK1_IO50

GND (Bank 1)

BK1_IO51

BK1_IO52

BK1_IO53

BK1_IO54

-

Function

sysHSI Reserved¹

Signal Name

NC

Function

sysHSI Reserved¹

AB1

AC6

AC5

AC2

AC1

AC4

AC3

AD2

-

HSI3B_SOUTN

48N/HSI3

49P/HSI4

49N/HSI4

50P/HSI4

50N/HSI4

51P/HSI4

51N/HSI4

52P/HSI4

-

NC

-

NC

-

HSI3B_SINP

NC

-

HSI3B_SINN

NC

-

NC

-

NC

-

HSI4A_SOUTP

NC

-

AD1

AD3

AD4

AE2

AE1

AD5

AD6

AF2

-

HSI4A_SOUTN

52N/HSI4

53P/HSI4

53N/HSI4

54P/HSI4

54N/HSI4

55P/HSI4

55N/HSI4

56P/HSI4

-

NC

-

BK1_IO32

BK1_IO33

BK1_IO34

BK1_IO35

BK1_IO25

BK1_IO24

BK1_IO26

-

37P/HSI3

37N

38P

38N

33N

33P

34P

-

HSI4A_SINP

-

HSI4A_SINN

-

VREF1

HSI4B_SOUTP

HSI2B_SOUTP

-

AF1

AE3

AE4

AG1

-

HSI4B_SOUTN

56N/HSI4

57P

BK1_IO27

BK1_IO28

BK1_IO29

BK1_IO30

GND (Bank 1)

BK1_IO31

BK1_IO36

BK1_IO37

BK1_IO38

GND (Bank 1)

BK1_IO39

BK1_IO40

BK1_IO41

TCK

HSI2B_SOUTN

34N

35P

35N

36P

-

57N

-

HSI4B_SINP

58P

HSI2B_SINP

-

AG2

AE5

AF4

AH1

-

BK1_IO55

BK1_IO56

BK1_IO57

BK1_IO58

GND (Bank 1)

BK1_IO59

BK1_IO60

BK1_IO61

TCK

HSI4B_SINN

58N

HSI2B_SINN

36N

39P

39N

40P

-

59P

-

59N

60P

-

AH2

AF3

AG3

AH4

AJ3

AK3

AG5

AH5

AJ4

-

60N

40N

41P

41N

-

61P

61N

-

TMS

-

TMS

-

TOE

-

TOE

-

BK2_IO0

BK2_IO1

BK2_IO2

GND (Bank 2)

BK2_IO3

BK2_IO4

BK2_IO5

BK2_IO6

62P

BK2_IO0

BK2_IO1

BK2_IO2

GND (Bank 2)

BK2_IO3

BK2_IO4

BK2_IO5

BK2_IO6

42P

42N

43P

-

62N

63P

-

AK4

AG6

AH6

AJ5

63N

43N

44P

44N

45P

64P

64N

65P

97

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK2_IO7

Function

sysHSI Reserved¹

Signal Name

BK2_IO7

BK2_IO8

BK2_IO9

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO21

BK2_IO20

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

-

Function

sysHSI Reserved¹

AK5

AE7

AF7

AG7

-

65N

66P

66N

67P

-

45N

BK2_IO8

-

46P

BK2_IO9

-

46N

BK2_IO10

GND (Bank 2)

BK2_IO11

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

GND (Bank 2)

BK2_IO19

BK2_IO20

-

47P

-

AH7

AE8

AF8

AJ6

AK6

AG8

AH8

AJ7

-

67N

68P

68N

69P

69N

70P

70N

71P

-

47N

VREF2

52N

-

52P

48P

48N

49P

49N

50P

-

AK7

AF9

-

71N

72P

-

BK2_IO17

BK2_IO18

GND (Bank 2)

BK2_IO19

NC

50N

51P

-

AG9

AJ8

AK8

AD10

AE10

AJ9

-

BK2_IO21

BK2_IO22

BK2_IO23

BK2_IO24

BK2_IO25

BK2_IO26

GND (Bank 2)

BK2_IO27

BK2_IO28

BK2_IO29

BK2_IO30

BK2_IO31

BK2_IO32

BK2_IO33

BK2_IO34

GND (Bank 2)

BK2_IO35

BK2_IO36

BK2_IO37

BK2_IO38

BK2_IO39

BK2_IO40

BK2_IO41

BK2_IO42

GND (Bank 2)

72N

73P

73N

74P

74N

75P

-

51N

-

NC

-

NC

-

NC

-

NC

-

AK9

AF10

AG10

AK10

AJ10

AE11

AF11

AG11

-

75N

76P

76N

77P

77N

78P

78N

79P

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AH11

AE12

AF12

AJ11

AK11

AG12

AH12

AK12

-

79N

80P

80N

81P

81N

82P

82N

83P

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

53P

-

BK2_IO22

-

98

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK2_IO43

BK2_IO44

BK2_IO45

BK2_IO46

-

Function

sysHSI Reserved¹

Signal Name

BK2_IO23

BK2_IO24

BK2_IO25

BK2_IO26

GND (Bank 2)

BK2_IO27

BK2_IO28

BK2_IO29

BK2_IO30

-

Function

sysHSI Reserved¹

AJ12

AD13

AE13

AK13

-

83N

84P

84N

85P

-

53N

54P

54N

55P

-

AJ13

AG13

AH13

AE14

-

BK2_IO47

BK2_IO48

BK2_IO49

BK2_IO50

GND (Bank 2)

BK2_IO51

BK2_IO52

BK2_IO53

BK2_IO54

-

85N

86P

86N

87P

-

55N

56P

56N

57P

-

AF14

AG14

AH14

AJ14

-

87N

88P

88N

89P

-

BK2_IO31

BK2_IO32

BK2_IO33

BK2_IO34

GND (Bank 2)

BK2_IO35

BK2_IO36

BK2_IO37

BK2_IO38

-

57N

58P

58N

59P

-

AK14

AE15

AF15

AG15

-

BK2_IO55

BK2_IO56

BK2_IO57

BK2_IO58

GND (Bank 2)

BK2_IO59

BK2_IO60

BK2_IO61

GND (Bank 2)

GND (Bank 3)

BK3_IO0

BK3_IO1

BK3_IO2

GND (Bank 3)

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

-

89N

90P

90N

91P

-

59N

60P

60N

61P

-

AH15

AJ15

AK15

-

91N

92P

92N

-

BK2_IO39

BK2_IO40

BK2_IO41

GND (Bank 2)

GND (Bank 3)

BK3_IO0

BK3_IO1

BK3_IO2

-

61N

62P

62N

-

AK16

AJ16

AH16

-

93P

93N

94P

-

63P

63N

64P

-

AG16

AF16

AE16

AK17

-

94N

95P

95N

96P

-

BK3_IO3

BK3_IO4

BK3_IO5

BK3_IO6

GND (Bank 3)

BK3_IO7

BK3_IO8

BK3_IO9

BK3_IO10

-

64N

65P

65N

66P

-

AJ17

AH17

AG17

AF17

-

BK3_IO7

BK3_IO8

BK3_IO9

BK3_IO10

GND (Bank 3)

BK3_IO11

BK3_IO12

BK3_IO13

96N

97P

97N

98P

-

66N

67P

67N

68P

-

AE17

AH18

AG18

98N

99P

99N

BK3_IO11

BK3_IO12

BK3_IO13

68N

69P

69N

99

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK3_IO14

-

Function

sysHSI Reserved¹

Signal Name

BK3_IO14

GND (Bank 3)

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

-

Function

sysHSI Reserved¹

AJ18

-

100P

-

70P

-

AK18

AE18

AD18

AJ19

-

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

GND (Bank 3)

BK3_IO19

BK3_IO20

BK3_IO21

BK3_IO22

BK3_IO23

BK3_IO24

BK3_IO25

BK3_IO26

GND (Bank 3)

BK3_IO27

BK3_IO28

BK3_IO29

BK3_IO30

BK3_IO31

BK3_IO32

BK3_IO33

BK3_IO34

GND (Bank 3)

BK3_IO35

BK3_IO36

BK3_IO37

BK3_IO38

BK3_IO39

BK3_IO40

-

100N

101P

101N

102P

-

70N

-

71P

-

71N

-

72P

-

AK19

AH19

AG19

AK20

AJ20

AF19

AE19

AH20

-

102N

103P

103N

104P

104N

105P

105N

106P

-

BK3_IO19

NC

-

72N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AG20

AF20

AE20

AJ21

AK21

AG21

AF21

AK22

-

106N

107P

107N

108P

108N

109P

109N

110P

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

AJ22

AE21

AD21

AG22

AF22

AG23

-

110N

111P

111N

112P

112N

113P

-

NC

-

NC

-

NC

-

NC

-

NC

-

BK3_IO22

GND (Bank 3)

BK3_IO23

BK3_IO24

-

74P

-

AH23

AJ23

-

BK3_IO41

BK3_IO42

GND (Bank 3)

BK3_IO43

BK3_IO44

BK3_IO45

BK3_IO46

BK3_IO47

BK3_IO48

BK3_IO49

-

113N

114P

-

74N

75P

-

AK23

AF23

AE23

AJ24

AK24

AH24

AG24

-

114N

115P

115N

116P

116N

117P

117N

BK3_IO25

BK3_IO26

BK3_IO27

BK3_IO28

BK3_IO29

BK3_IO21

BK3_IO20

-

75N

76P

76N

77P

77N

73N

73P

-

VREF3

100

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK3_IO50

GND (Bank 3)

BK3_IO51

BK3_IO52

BK3_IO53

BK3_IO54

BK3_IO55

BK3_IO56

BK3_IO57

BK3_IO58

GND (Bank 3)

BK3_IO59

BK3_IO60

BK3_IO61

GSR

Function

sysHSI Reserved¹

Signal Name

BK3_IO30

GND (Bank 3)

BK3_IO31

BK3_IO32

BK3_IO33

BK3_IO34

BK3_IO35

BK3_IO36

BK3_IO37

BK3_IO38

GND (Bank 3)

BK3_IO39

BK3_IO40

BK3_IO41

GSR

Function

sysHSI Reserved¹

AJ25

-

118P

-

78P

-

AK25

AF24

AE24

AK26

AJ26

AH25

AG25

AK27

-

118N

119P

-

78N

-

79P

-

119N

120P

-

79N

-

80P

-

120N

121P

-

80N

-

81P

-

121N

122P

-

81N

-

82P

-

AJ27

AG26

AH26

AK28

AJ28

AH27

AG28

AF27

AF28

-

122N

123P

-

82N

-

83P

-

123N

-

83N

-

DXP

-

DXP

-

DXN

-

DXN

-

BK4_IO0

BK4_IO1

BK4_IO2

GND (Bank 4)

BK4_IO3

BK4_IO4

BK4_IO5

BK4_IO6

-

124P

BK4_IO0

BK4_IO1

BK4_IO2

GND (Bank 4)

BK4_IO3

BK4_IO4

BK4_IO5

BK4_IO10

GND (Bank 4)

BK4_IO11

BK4_IO12

BK4_IO13

BK4_IO14

-

84P

-

124N

125P

-

84N

-

85P/HSI3

-

AE26

AE27

AE28

AH30

-

125N

126P

-

85N/HSI3

86P/HSI3

86N/HSI3

89P/HSI3

-

126N

127P

-

HSI5A_SINP

HSI3A_SINP

-

AH29

AD25

AD26

AG29

-

BK4_IO7

BK4_IO8

BK4_IO9

BK4_IO10

GND (Bank 4)

BK4_IO11

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15

BK4_IO16

BK4_IO17

BK4_IO18

GND (Bank 4)

BK4_IO19

BK4_IO20

HSI5A_SINN

127N

128P

HSI3A_SINN

89N/HSI3

90P/HSI3

90N/HSI3

91P/HSI3

-

128N

129P/HSI5

-

HSI5A_SOUTP

HSI3A_SOUTP

-

AG30

AD27

AD28

AF29

AF30

AC25

AC26

AE29

-

HSI5A_SOUTN

129N/HSI5

130P/HSI5

130N/HSI5

131P/HSI5

131N/HSI5

132P/HSI5

132N/HSI5

133P/HSI5

-

BK4_IO15

BK4_IO17

BK4_IO16

BK4_IO6

BK4_IO7

BK4_IO8

BK4_IO9

NC

HSI3A_SOUTN

91N/HSI3

92N/HSI3

92P/HSI3

87P/HSI3

87N/HSI3

88P/HSI3

88N/HSI3

-

VREF4

-

HSI5B_SINP

HSI5B_SINN

-

HSI5B_SOUTP

-

AE30

AC28

HSI5B_SOUTN

-

133N/HSI5

134P/HSI5

NC

-

NC

-

101

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK4_IO21

BK4_IO22

BK4_IO23

BK4_IO24

BK4_IO25

BK4_IO26

GND (Bank 4)

BK4_IO27

BK4_IO28

BK4_IO29

BK4_IO30

-

Function

sysHSI Reserved¹

Signal Name

NC

Function

sysHSI Reserved¹

AC27

AD29

AD30

AB24

AB25

AC29

-

134N/HSI5

135P/HSI5

135N/HSI5

136P/HSI5

136N/HSI5

137P/HSI6

-

HSI6A_SINP

NC

-

HSI6A_SINN

NC

-

NC

-

NC

-

HSI6A_SOUTP

NC

-

AC30

AB27

AB26

AB30

-

HSI6A_SOUTN

137N/HSI6

138P/HSI6

138N/HSI6

139P/HSI6

-

NC

-

NC

-

NC

-

HSI6B_SINP

BK4_IO18

GND (Bank 4)

BK4_IO19

NC

HSI3B_SINP

93P

-

AB29

AA26

AA27

AA30

-

BK4_IO31

BK4_IO32

BK4_IO33

BK4_IO34

GND (Bank 4)

BK4_IO35

BK4_IO36

BK4_IO37

BK4_IO38

BK4_IO39

BK4_IO40

BK4_IO41

BK4_IO42

GND (Bank 4)

BK4_IO43

BK4_IO44

-

HSI6B_SINN

139N/HSI6

140P/HSI6

140N/HSI6

141P/HSI6

-

HSI3B_SINN

93N

-

NC

-

HSI6B_SOUTP

BK4_IO22

-

HSI3B_SOUTP

95P

-

AA29

Y25

Y26

Y28

Y27

W25

W26

W27

-

HSI6B_SOUTN

141N/HSI6

142P/HSI6

142N/HSI6

143P/HSI6

143N/HSI6

144P/HSI6

144N/HSI6

145P

BK4_IO23

NC

HSI3B_SOUTN

95N

-

NC

-

NC

-

NC

-

NC

-

NC

-

BK4_IO24

-

96P

-

W28

V24

-

145N

BK4_IO25

BK4_IO26

GND (Bank 4)

BK4_IO27

BK4_IO32

BK4_IO33

BK4_IO20

BK4_IO21

BK4_IO34

GND (Bank 4)

BK4_IO35

BK4_IO28

BK4_IO29

BK4_IO30

BK4_IO31

BK4_IO36

-

96N

97P

-

146P

-

V25

Y29

Y30

V27

V28

W29

-

BK4_IO45

BK4_IO46

BK4_IO47

BK4_IO48

BK4_IO49

BK4_IO50

GND (Bank 4)

BK4_IO51

BK4_IO52

BK4_IO53

BK4_IO54

BK4_IO55

BK4_IO56

-

146N

-

97N

100P

100N

94P

94N

101P

-

147P

-

147N

-

PLL_RST4

148P

PLL_RST4

PLL_RST5

148N

PLL_RST5

-

149P

-

W30

U25

U26

V29

V30

U28

-

149N

-

101N

98P

98N

99P

99N

102P

-

150P

-

150N

-

SS_CLKIN1P

SS_CLKIN1N

PLL_FBK4

151P

SS_CLKIN1P

SS_CLKIN1N

PLL_FBK4

151N

152P

102

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK4_IO57

BK4_IO58

GND (Bank 4)

BK4_IO59

BK4_IO60

-

Function

sysHSI Reserved¹

Signal Name

BK4_IO37

BK4_IO38

-

Function

sysHSI Reserved¹

U27

U29

-

PLL_FBK5

152N

153P

PLL_FBK5

102N

SS_CLKOUT1P

103P

--

-

103N

U30

T30

-

SS_CLKOUT1N

153N

BK4_IO39

BK4_IO40

GND (Bank 4)

BK4_IO41

-

SS_CLKOUT1N

CLK_OUT4

154P

CLK_OUT4

104P

-

T29

-

BK4_IO61

GND (Bank 4)

GCLK4

CLK_OUT5

154N

CLK_OUT5

104N

-

T28

T27

T26

R28

R27

R26

-

LVDS Pair2P

LVDS Pair2N

-

GCLK4

-

LVDS Pair2P

LVDS Pair2N

-

GCLK5

-

GCLK5

-

VCCP1

-

VCCP1

-

GNDP1

-

GNDP1

-

GCLK6

-

LVDS Pair3P

LVDS Pair3N

-

GCLK6

-

LVDS Pair3P

LVDS Pair3N

-

GCLK7

-

GCLK7

-

GND (Bank 5)

BK5_IO0

-

R29

-

CLK_OUT6

155P

BK5_IO0

GND (Bank 5)

BK5_IO1

BK5_IO4

GND (Bank 5)

BK5_IO7

BK5_IO2

BK5_IO5

BK5_IO6

BK5_IO3

BK5_IO8

BK5_IO9

BK5_IO10

-

CLK_OUT6

105P

-

R30

P30

-

BK5_IO1

BK5_IO2

GND (Bank 5)

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

BK5_IO7

BK5_IO8

BK5_IO9

BK5_IO10

GND (Bank 5)

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

-

CLK_OUT7

155N

CLK_OUT7

105N

PLL_FBK6

156P

PLL_FBK6

107P

-

P29

P27

P28

P26

P25

N27

N28

N29

-

PLL_FBK7

156N

PLL_FBK7

108N

-

157P/HSI7

157N/HSI7

158P/HSI7

158N/HSI7

159P/HSI7

159N/HSI7

160P/HSI7

-

106P

-

107N

PLL_RST6

108P

PLL_RST7

106N

-

109P/HSI4

109N/HSI4

110P/HSI4

-

HSI7A_SINP

HSI4A_SINP

-

N30

N25

N24

M29

-

HSI7A_SINN

160N/HSI7

161P/HSI7

161N/HSI7

162P/HSI7

-

BK5_IO11

BK5_IO12

BK5_IO13

BK5_IO14

GND (Bank 5)

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

-

HSI4A_SINN

110N/HSI4

111P/HSI4

111N/HSI4

112P/HSI4

-

HSI7A_SOUTP

HSI4A_SOUTP

-

M30

M28

M27

L30

-

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

GND (Bank 5)

BK5_IO19

BK5_IO20

BK5_IO21

HSI7A_SOUTN

162N/HSI7

163P/HSI7

163N/HSI7

164P/HSI7

-

HSI4A_SOUTN

112N/HSI4

113P/HSI4

113N/HSI4

114P/HSI4

-

HSI7B_SINP

HSI4B_SINP

-

L29

M26

M25

HSI7B_SINN

164N/HSI7

165P/HSI8

165N/HSI8

BK5_IO19

BK5_IO20

BK5_IO21

HSI4B_SINN

114N/HSI4

115P/HSI4

115N/HSI4

-

103

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK5_IO22

-

Function

sysHSI Reserved¹

Signal Name

BK5_IO22

GND (Bank 5)

BK5_IO23

BK5_IO24

BK5_IO25

BK5_IO26

-

Function

sysHSI Reserved¹

K30

-

HSI7B_SOUTP

166P/HSI8

-

HSI4B_SOUTP

116P/HSI4

-

K29

L28

L27

L26

-

BK5_IO23

BK5_IO24

BK5_IO25

BK5_IO26

GND (Bank 5)

BK5_IO27

BK5_IO28

BK5_IO29

BK5_IO30

-

HSI7B_SOUTN

166N/HSI8

167P/HSI8

167N/HSI8

168P/HSI8

-

HSI4B_SOUTN

116N/HSI4

-

117P/HSI5

-

117N/HSI5

HSI8A_SINP

HSI5A_SINP

118P/HSI5

-

L25

K27

K26

J30

-

HSI8A_SINN

168N/HSI8

169P/HSI8

169N/HSI8

170P/HSI8

-

BK5_IO27

BK5_IO28

BK5_IO29

BK5_IO30

GND (Bank 5)

BK5_IO31

NC

HSI5A_SINN

118N/HSI5

-

119P/HSI5

-

119N/HSI5

HSI8A_SOUTP

HSI5A_SOUTP

120P/HSI5

-

J29

J26

J27

H30

-

BK5_IO31

BK5_IO32

BK5_IO33

BK5_IO34

GND (Bank 5)

BK5_IO35

BK5_IO36

BK5_IO37

BK5_IO38

BK5_IO39

BK5_IO40

BK5_IO41

BK5_IO42

GND (Bank 5)

BK5_IO43

BK5_IO44

BK5_IO45

BK5_IO46

BK5_IO47

BK5_IO48

BK5_IO49

BK5_IO50

GND (Bank 5)

BK5_IO51

BK5_IO52

BK5_IO53

BK5_IO54

-

HSI8A_SOUTN

170N/HSI8

171P/HSI8

171N/HSI8

172P/HSI8

-

HSI5A_SOUTN

120N/HSI5

-

NC

-

HSI8B_SINP

NC

-

H29

J25

J24

G30

G29

H27

H28

F30

-

HSI8B_SINN

172N/HSI8

173P/HSI9

173N/HSI9

174P/HSI9

174N/HSI9

175P/HSI9

175N/HSI9

176P/HSI9

-

NC

-

NC

-

NC

-

HSI8B_SOUTP

NC

-

HSI8B_SOUTN

NC

-

NC

-

NC

-

HSI9A_SINP

NC

-

F29

G27

G28

E30

E29

H26

H25

D30

-

HSI9A_SINN

176N/HSI9

177P/HSI9

177N/HSI9

178P/HSI9

178N/HSI9

179P/HSI9

179N/HSI9

180P/HSI9

-

NC

-

NC

-

NC

-

HSI9A_SOUTP

NC

-

HSI9A_SOUTN

NC

-

BK5_IO33

BK5_IO32

BK5_IO34

-

121N/HSI5

121P/HSI5

122P/HSI5

-

VREF5

HSI9B_SINP

HSI5B_SINP

-

D29

F28

F27

C30

-

HSI9B_SINN

180N/HSI9

181P

BK5_IO35

BK5_IO36

BK5_IO37

BK5_IO38

GND (Bank 5)

BK5_IO39

NC

HSI5B_SINN

122N/HSI5

123P/HSI5

123N/HSI5

124P/HSI5

-

181N

-

HSI9B_SOUTP

182P

HSI5B_SOUTP

-

C29

G26

BK5_IO55

BK5_IO56

HSI9B_SOUTN

-

182N

HSI5B_SOUTN

-

124N/HSI5

-

183P

104

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK5_IO57

BK5_IO58

GND (Bank 5)

BK5_IO59

BK5_IO60

BK5_IO61

CFG0

Function

sysHSI Reserved¹

Signal Name

NC

Function

sysHSI Reserved¹

G25

F26

-

183N

184P

-

NC

-

E28

E27

D28

C27

B28

A28

D26

C26

B27

-

184N

185P

185N

-

NC

-

BK5_IO40

BK5_IO41

CFG0

-

125P

-

125N

-

DONE

-

DONE

-

PROGRAMb

BK6_IO0

-

PROGRAMb

BK6_IO0

BK6_IO1

BK6_IO2

GND (Bank 6)

BK6_IO3

BK6_IO4

BK6_IO5

BK6_IO6

BK6_IO7

BK6_IO8

BK6_IO9

BK6_IO10

GND (Bank 6)

BK6_IO11

BK6_IO21

BK6_IO20

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15

BK6_IO16

-

INITb

186P

186N

187P

-

INITb

126P

126N

127P

-

BK6_IO1

CCLK

BK6_IO2

-

GND (Bank 6)

BK6_IO3

-

A27

D25

C25

B26

A26

F24

E24

A25

-

187N

188P

188N

189P

189N

190P

190N

191P

-

127N

128P

128N

129P

129N

130P

130N

131P

-

BK6_IO4

CSb

BK6_IO5

Read

READ

BK6_IO6

-

BK6_IO7

-

BK6_IO8

-

BK6_IO9

-

BK6_IO10

GND (Bank 6)

BK6_IO11

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

GND (Bank 6)

BK6_IO19

BK6_IO20

BK6_IO21

BK6_IO22

BK6_IO23

BK6_IO24

BK6_IO25

BK6_IO26

GND (Bank 6)

BK6_IO27

BK6_IO28

-

B25

D24

C24

A24

B24

F23

E23

A23

-

191N

192P

192N

193P

193N

194P

194N

195P

-

131N

136N

136P

132P

132N

133P

133N

134P

-

VREF6

-

B23

C23

D23

E22

D22

G21

F21

B22

-

195N

196P

196N

197P

197N

198P

198N

199P

-

BK6_IO17

NC

134N

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

A22

E21

199N

200P

NC

-

NC

-

105

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK6_IO29

BK6_IO30

BK6_IO31

BK6_IO32

-

Function

sysHSI Reserved¹

Signal Name

NC

Function

sysHSI Reserved¹

D21

A21

B21

F20

-

200N

201P

201N

202P

-

NC

-

NC

-

DATA7

BK6_IO18

GND (Bank 6)

BK6_IO19

NC

DATA7

135P

-

E20

D20

-

BK6_IO33

BK6_IO34

GND (Bank 6)

BK6_IO35

BK6_IO36

BK6_IO37

BK6_IO38

BK6_IO39

BK6_IO40

BK6_IO41

BK6_IO42

GND (Bank 6)

BK6_IO43

BK6_IO44

BK6_IO45

BK6_IO46

BK6_IO47

BK6_IO48

-

DATA6

202N

203P

-

DATA6

135N

-

C20

F19

E19

B20

A20

D19

C19

A19

-

203N

204P

204N

205P

205N

206P

206N

207P

-

NC

-

DATA5

BK6_IO22

BK6_IO23

NC

DATA5

137P

137N

-

DATA4

-

NC

-

NC

-

NC

-

NC

-

B19

G18

F18

A18

B18

D18

-

207N

208P

208N

209P

209N

210P

-

NC

-

BK6_IO24

BK6_IO25

BK6_IO32

BK6_IO33

BK6_IO34

GND (Bank 6)

BK6_IO35

BK6_IO26

GND (Bank 6)

BK6_IO27

BK6_IO28

BK6_IO29

BK6_IO30

BK6_IO31

BK6_IO36

BK6_IO37

BK6_IO38

-

138P

138N

142P

142N

143P

-

C18

F17

-

BK6_IO49

BK6_IO50

GND (Bank 6)

BK6_IO51

BK6_IO52

BK6_IO53

BK6_IO54

BK6_IO55

BK6_IO56

BK6_IO57

BK6_IO58

GND (Bank 6)

BK6_IO59

BK6_IO60

BK6_IO61

GND (Bank 6)

GND (Bank 7)

BK7_IO0

-

210N

211P

-

143N

139P

-

DATA3

-

E17

D17

C17

B17

A17

F16

E16

D16

-

DATA2

211N

212P

212N

213P

213N

214P

214N

215P

-

DATA2

139N

140P

140N

141P

141N

144P

144N

145P

-

DATA1

DATA0

-

C16

B16

A16

-

215N

216P

216N

-

BK6_IO39

BK6_IO40

BK6_IO41

GND (Bank 6)

GND (Bank 7)

BK7_IO0

145N

146P

146N

-

A15

217P

147P

106

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK7_IO1

Function

sysHSI Reserved¹

Signal Name

BK7_IO1

Function

sysHSI Reserved¹

B15

C15

-

217N

218P

-

147N

BK7_IO2

148P

GND (Bank 7)

BK7_IO3

-

D15

E15

F15

A14

-

218N

219P

219N

220P

-

BK7_IO3

BK7_IO4

BK7_IO5

BK7_IO6

GND (Bank 7)

BK7_IO7

BK7_IO8

BK7_IO9

BK7_IO10

-

148N

BK7_IO4

149P

BK7_IO5

149N

BK7_IO6

150P

-

B14

C14

D14

E14

-

BK7_IO7

220N

221P

221N

222P

-

150N

BK7_IO8

151P

BK7_IO9

151N

BK7_IO10

GND (Bank 7)

BK7_IO11

BK7_IO12

BK7_IO13

BK7_IO14

-

152P

-

F14

C13

D13

B13

-

222N

223P

223N

224P

-

BK7_IO11

BK7_IO12

BK7_IO13

BK7_IO14

GND (Bank 7)

BK7_IO15

BK7_IO16

BK7_IO17

BK7_IO18

-

152N

153P

153N

154P

-

A13

F13

G13

A12

-

BK7_IO15

BK7_IO16

BK7_IO17

BK7_IO18

GND (Bank 7)

BK7_IO19

BK7_IO20

BK7_IO21

BK7_IO22

BK7_IO23

BK7_IO24

BK7_IO25

BK7_IO26

GND (Bank 7)

BK7_IO27

BK7_IO28

BK7_IO29

BK7_IO30

BK7_IO31

BK7_IO32

BK7_IO33

BK7_IO34

GND (Bank 7)

BK7_IO35

224N

225P

225N

226P

-

154N

155P

155N

156P

-

B12

C12

D12

A11

B11

E12

F12

C11

-

226N

227P

227N

228P

228N

229P

229N

230P

-

BK7_IO19

NC

156N

-

NC

-

D11

E11

F11

B10

A10

D10

E10

A9

230N

231P

231N

232P

232N

233P

233N

234P

-

NC

-

B9

234N

NC

107

Lattice Semiconductor

ispXPGA Family Data Sheet

ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)

LFX1200

LFX500

900 fpBGA

Ball

Second

LVDS Pair/

Second

LVDS Pair/

Signal Name

BK7_IO36

BK7_IO37

BK7_IO38

BK7_IO39

BK7_IO40

-

Function

sysHSI Reserved¹

Signal Name

NC

Function

sysHSI Reserved¹

F10

G10

A8

B8

D9

-

235P

235N

236P

236N

237P

-

NC

-

NC

-

NC

-

BK7_IO22

GND (Bank 7)

BK7_IO23

BK7_IO24

-

158P

-

E9

A7

-

BK7_IO41

BK7_IO42

GND (Bank 7)

BK7_IO43

BK7_IO44

BK7_IO45

BK7_IO46

BK7_IO47

BK7_IO48

BK7_IO49

BK7_IO50

GND (Bank 7)

BK7_IO51

BK7_IO52

BK7_IO53

BK7_IO54

BK7_IO55

BK7_IO56

BK7_IO57

BK7_IO58

GND (Bank 7)

BK7_IO59

BK7_IO60

BK7_IO61

TDO

-

237N

238P

-

158N

159P

-

B7

C8

D8

A6

B6

E8

F8

C7

-

238N

239P

239N

240P

240N

241P

241N

242P

-

BK7_IO25

BK7_IO26

BK7_IO27

BK7_IO21

BK7_IO20

BK7_IO28

BK7_IO29

BK7_IO30

GND (Bank 7)

BK7_IO31

BK7_IO32

BK7_IO33

BK7_IO34

BK7_IO35

BK7_IO36

BK7_IO37

BK7_IO38

GND (Bank 7)

BK7_IO39

BK7_IO40

BK7_IO41

TDO

-

159N

160P

160N

157N

157P

161P

161N

162P

-

VREF7

-

D7

E7

F7

A5

B5

C6

D6

D5

-

242N

243P

243N

244P

244N

245P

245N

246P

-

162N

163P

163N

164P

164N

165P

165N

166P

-

C5

B4

A4

A3

B3

C4

246N

247P

247N

-

166N

167P

167N

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use.

108

Lattice Semiconductor

ispXPGA Family Data Sheet

Part Number Description

LFX XXXX X X – XX XXXXX X

Device Family

LFX

Grade

C = Commercial

I = Industrial

Gates

Package

125 = 139K Gates

200 = 210K Gates

500 = 476K Gates

1200 = 1.25M Gates¹

F256 = 256-Ball fpBGA

FH516 = 516-Ball fpBGA (with Heat Spreader)

F516 = 516-Ball fpBGA (without Heat Spreader)

FE680 = 680-Ball fpSBGA

F900 = 900-Ball fpBGA

FN256 = Lead-Free 256-Ball fpBGA

FN900 = Lead-Free 900-Ball fpBGA²

sysHSI Support

Blank = Supports sysHSI

E = No sysHSI Support

Power Supply Voltage

B = 2.5/3.3V

C = 1.8V

Speed

5 = Fastest

4

3 = Slowest

1. Discontinued via PCN #03A-10.

2. Select products only. See Ordering Information tables below for specific support.

Ordering Information

Conventional Packaging

Commercial

Part Number

LFX125B-05F256C

LFX125B-04F256C

LFX125B-03F256C

LFX125C-04F256C

LFX125C-03F256C

LFX125B-05F516C

LFX125B-04F516C

LFX125B-03F516C

LFX125C-04F516C

LFX125C-03F516C

LFX125B-05FH516C¹

LFX125B-04FH516C¹

LFX125B-03FH516C¹

LFX125C-04FH516C¹

LFX125C-03FH516C¹

LFX200B-05F256C

LFX200B-04F256C

LFX200B-03F256C

LFX200C-04F256C

LFX200C-03F256C

Gates

139K

210K

Voltage

2.5/3.3

1.8

Speed Grade

Package

fpBGA

Balls

256

516

256

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

109

Lattice Semiconductor

ispXPGA Family Data Sheet

Commercial (Cont.)

Part Number

LFX200B-05F516C

LFX200B-04F516C

LFX200B-03F516C

LFX200C-04F516C

LFX200C-03F516C

LFX200B-05FH516C¹

LFX200B-04FH516C¹

LFX200B-03FH516C¹

LFX200C-04FH516C¹

LFX200C-03FH516C¹

LFX500B-05F516C

LFX500B-04F516C

LFX500B-03F516C

LFX500C-04F516C

LFX500C-03F516C

LFX500B-05FH516C¹

LFX500B-04FH516C¹

LFX500B-03FH516C¹

LFX500C-04FH516C¹

LFX500C-03FH516C¹

LFX500B-05F900C

LFX500B-04F900C

LFX500B-03F900C

LFX500C-04F900C

LFX500C-03F900C

LFX1200B-05F900C²

LFX1200B-04F900C²

LFX1200B-03F900C²

LFX1200C-04F900C²

LFX1200C-03F900C²

LFX1200B-05FE680C²

LFX1200B-04FE680C²

LFX1200B-03FE680C²

LFX1200C-04FE680C²

LFX1200C-03FE680C²

Gates

210K

476K

1.25M

Voltage

2.5/3.3

1.8

Speed Grade

Package

fpBGA

fpSBGA

Balls

516

900

680

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

1. FH516 package was converted to F516 via PCN #09A-08.

2. Discontinued via PCN #03A-10.

110

Lattice Semiconductor

ispXPGA Family Data Sheet

“E-Series” Commercial

Part Number

LFX125EB-05F256C

LFX125EB-04F256C

LFX125EB-03F256C

LFX125EC-04F256C

LFX125EC-03F256C

LFX125EB-05F516C

LFX125EB-04F516C

LFX125EB-03F516C

LFX125EC-04F516C

LFX125EC-03F516C

LFX125EB-05FH516C¹

LFX125EB-04FH516C¹

LFX125EB-03FH516C¹

LFX125EC-04FH516C¹

LFX125EC-03FH516C¹

LFX200EB-05F256C

LFX200EB-04F256C

LFX200EB-03F256C

LFX200EC-04F256C

LFX200EC-03F256C

LFX200EB-05F516C

LFX200EB-04F516C

LFX200EB-03F516C

LFX200EC-04F516C

LFX200EC-03F516C

LFX200EB-05FH516C¹

LFX200EB-04FH516C¹

LFX200EB-03FH516C¹

LFX200EC-04FH516C¹

LFX200EC-03FH516C¹

LFX500EB-05F516C

LFX500EB-04F516C

LFX500EB-03F516C

LFX500EC-04F516C

LFX500EC-03F516C

LFX500EB-05FH516C¹

LFX500EB-04FH516C¹

LFX500EB-03FH516C¹

LFX500EC-04FH516C¹

LFX500EC-03FH516C¹

LFX500EB-05F900C

LFX500EB-04F900C

LFX500EB-03F900C

LFX500EC-04F900C

Gates

139K

210K

476K

Voltage

2.5/3.3

1.8

Speed Grade

Package

fpBGA

Balls

256

516

256

516

900

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

111

Lattice Semiconductor

ispXPGA Family Data Sheet

“E-Series” Commercial (Cont.)

Part Number

Gates

476K

Voltage

1.8

Speed Grade

Package

fpBGA

Balls

900

680

LFX500EC-03F900C

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

LFX1200EB-05F900C²

LFX1200EB-04F900C²

LFX1200EB-03F900C²

LFX1200EC-04F900C²

LFX1200EC-03F900C²

LFX1200EB-05FE680C²

LFX1200EB-04FE680C²

LFX1200EB-03FE680C²

LFX1200EC-04FE680C²

LFX1200EC-03FE680C²

1.25M

2.5/3.3

1.8

fpBGA

1.8

fpBGA

2.5/3.3

1.8

fpSBGA

1.8

1. FH516 package was converted to F516 via PCN #09A-08.

2. Discontinued via PCN #03A-10.

“E-Series” Industrial

Part Number

LFX125EB-04F256I

LFX125EB-03F256I

LFX125EC-03F256I

LFX125EB-04F516I

LFX125EB-03F516I

LFX125EC-03F516I

LFX125EB-04FH516I¹

LFX125EB-03FH516I¹

LFX125EC-03FH516I¹

LFX200EB-04F256I

LFX200EB-03F256I

LFX200EC-03F256I

LFX200EB-04F516I

LFX200EB-03F516I

LFX200EC-03F516I

LFX200EB-04FH516I¹

LFX200EB-03FH516I¹

LFX200EC-03FH516I¹

LFX500EB-04F516I

LFX500EB-03F516I

LFX500EC-03F516I

LFX500EB-04FH516I¹

LFX500EB-03FH516I¹

LFX500EC-03FH516I¹

LFX500EB-04F900I

LFX500EB-03F900I

LFX500EC-03F900I

Gates

139K

210K

476K

Voltage

2.5/3.3

1.8

Speed Grade

Package

fpBGA

Balls

256

516

256

516

900

-4

-3

-4

-3

-4

-3

-4

-3

-4

-3

-4

-3

-4

-3

-4

-3

-4

-3

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

2.5/3.3

1.8

112

Lattice Semiconductor

ispXPGA Family Data Sheet

“E-Series” Industrial (Cont.)

Part Number

Gates

1.25M

Voltage

2.5/3.3

1.8

Speed Grade

Package

fpBGA

Balls

900

680

LFX1200EB-04F900I²

LFX1200EB-03F900I²

LFX1200EC-03F900I²

LFX1200EB-04FE680I²

LFX1200EB-03FE680I²

LFX1200EC-03FE680I²

-4

-3

-4

-3

fpBGA

2.5/3.3

1.8

fpSBGA

1. FH516 package was converted to F516 via PCN #09A-08.

2. Discontinued via PCN #03A-10.

Lead-Free Packaging

Commercial

Part Number

LFX125B-05FN256C

LFX125B-04FN256C

LFX125B-03FN256C

LFX125C-04FN256C

LFX125C-03FN256C

LFX200B-05FN256C

LFX200B-04FN256C

LFX200B-03FN256C

LFX200C-04FN256C

LFX200C-03FN256C

LFX500B-05FN900C

LFX500B-04FN900C

LFX500B-03FN900C

LFX500C-04FN900C

LFX500C-03FN900C

Gates

139K

210K

476K

Voltage

2.5/3.3

1.8

Speed Grade

Package

Balls

256

900

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

Lead-Free fpBGA

1.8

2.5/3.3

1.8

2.5/3.3

1.8

“E-Series” Commercial

Part Number

LFX125EB-05FN256C

LFX125EB-04FN256C

LFX125EB-03FN256C

LFX125EC-04FN256C

LFX125EC-03FN256C

LFX200EB-05FN256C

LFX200EB-04FN256C

LFX200EB-03FN256C

LFX200EC-04FN256C

LFX200EC-03FN256C

LFX500EB-05FN900C

LFX500EB-04FN900C

LFX500EB-03FN900C

Gates

139K

210K

476K

Voltage

2.5/3.3

1.8

Speed Grade

Package

Balls

256

900

-5

-4

-3

-4

-3

-5

-4

-3

-4

-3

-5

-4

-3

Lead-Free fpBGA

1.8

2.5/3.3

1.8

2.5/3.3

113

Lattice Semiconductor

ispXPGA Family Data Sheet

“E-Series” Commercial (Cont.)

Part Number

LFX500EC-04FN900C

LFX500EC-03FN900C

Gates

476K

Voltage

1.8

Speed Grade

Package

Balls

900

-4

-3

Lead-Free fpBGA

1.8

900

“E-Series” Industrial

Part Number

LFX125EB-04FN256I

LFX125EB-03FN256I

LFX125EC-03FN256I

LFX200EB-04FN256I

LFX200EB-03FN256I

LFX200EC-03FN256I

LFX500EB-04FN900I

LFX500EB-03FN900I

LFX500EC-03FN900I

Gates

139K

210K

476K

Voltage

2.5/3.3

1.8

Speed Grade

Package

Balls

256

900

-4

-3

-4

-3

-4

-3

Lead-Free fpBGA

2.5/3.3

1.8

2.5/3.3

1.8

For Further Information

In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispXPGA

Family:

• TN1028, ispXPGA Memory Usage Guidelines

• TN1003, sysCLOCK PLL Usage and Design Guidelines

• TN1000, sysIO Usage Guidelines for Lattice Devices

• TN1026, ispXP Configuration Usage Guidelines

• TN1020, sysHSI Usage Guidelines

• TN1043, Power Estimation in ispXPGA Devices

Revision History

Date

Version

Change Summary

—

Previous Lattice releases.

September 2003

07

Improved typical Icc data for LFX125B/C and LFX500B/C.

Improved external switching characteristics timing numbers for LFX125B/C.

Improved PIC timing numbers for LFX125B/C.

Improved t_IOINDLYtiming numbers for LFX125B/C.

Improved external switching characteristics timing numbers for LFX500B/C.

Improved PIC timing numbers for LFX500B/C.

Improved t_IOINDLYtiming numbers for LFX500B/C.

Enhanced CDR functionality description.

Logic Signal Connections and Signal Descriptions - removed CDRLOCK, LOSS and EXLOSS

descriptions.

January 2004

June 2004

07.1

08.0

Added lead-free package designators.

Updated CDR specifications and reference notes. Removed Source Synchronous (SS:No CAL)

mode references for the sysHSI blocks.

Revised Figures 16 and 24 for clarification.

Clarification of VCC sysHSI Block for 1.8V devices.

Updated IIL and IIH max specification.

Updated LVTTL and PCI 3.3 to support 5V tolerance.

114

Lattice Semiconductor

ispXPGA Family Data Sheet

Revision History (Cont.)

Date

Version

Change Summary

Updated Global Clock Input Setup time specifications.

Clarification of Serial Out LVDS test condition.

June 2004

(cont.)

08.0

(cont.)

Clarification of REFCLK, SS_CLKIN peak-to-peak period jitter condition.

Added sysHSI Reserved pins and footnote.

Removed industrial ordering part numbers.

Added “E” Series product family.

July 2004

August 2004

December 2004

April 2005

09.0

10.0

10.1

10.2

11.0

12.0

13.0

Final release.

Updated NC Connections table.

Clarification of IDK specification.

April 2005

Select lead-free packages release.

July 2005

Added lead-free 516 fpBGA ordering part numbers.

April 2007

Removed lead-free 680 fpSBGA information from Part Number Description and Ordering Part

Number tables. Removed lead-free 516 fpBGA for LFX125 from Ordering Part Number tables.

November 2007

July 2008

14.0

14.1

15.0

Removed lead-free 516 fpBGA information from Part Number Description and Ordering Part

Number tables.

Added 516 fpBGA package without heat spreader to Part Number Description and Ordering Part

Number tables.

February 2010

Ordering part numbers and ispXPGA Family Selection Guide table have been updated per PCN

#03A-10 (discontinuation of the ispXPGA 1200 devices).

References to "system gates" changed to "functional gates."

115


型号：	LFX1200EC-04FE680C
厂家：	LATTICE SEMICONDUCTOR
描述：	Field Programmable Gate Array, 3844 CLBs, 1250000 Gates, 320MHz, 15376-Cell, CMOS, PBGA680, FPSBGA-680 栅
文件：	总119页 (文件大小：1504K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LFX1200EC-04FE680C [LATTICE]

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