LFXP10C-4F256NI [LATTICE]
Field Programmable Gate Array, 1216 CLBs, 375MHz, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, FPBGA-256;
| 型号： | LFXP10C-4F256NI |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Field Programmable Gate Array, 1216 CLBs, 375MHz, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, FPBGA-256 栅 |
| 文件： | 总397页 (文件大小：9665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LatticeXP Family Handbook
HB1001 Version 03.6, October 2011
LatticeXP Family Handbook
Table of Contents
September 2011
Section I. LatticeXP Family Data Sheet
Introduction
Features............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture
Architecture Overview........................................................................................................................................ 2-1
PFU and PFF Blocks................................................................................................................................. 2-2
Slice .......................................................................................................................................................... 2-3
Routing...................................................................................................................................................... 2-6
Clock Distribution Network................................................................................................................................. 2-6
Primary Clock Sources.............................................................................................................................. 2-6
Secondary Clock Sources......................................................................................................................... 2-7
Clock Routing............................................................................................................................................ 2-8
sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-9
Dynamic Clock Select (DCS) ........................................................................................................................... 2-11
sysMEM Memory ............................................................................................................................................. 2-11
sysMEM Memory Block........................................................................................................................... 2-11
Bus Size Matching .................................................................................................................................. 2-12
RAM Initialization and ROM Operation ................................................................................................... 2-12
Memory Cascading ................................................................................................................................. 2-12
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-12
Memory Core Reset................................................................................................................................ 2-13
EBR Asynchronous Reset....................................................................................................................... 2-14
Programmable I/O Cells (PICs)........................................................................................................................ 2-14
PIO.......................................................................................................................................................... 2-16
DDR Memory Support...................................................................................................................................... 2-20
DLL Calibrated DQS Delay Block ........................................................................................................... 2-20
Polarity Control Logic.............................................................................................................................. 2-22
sysIO Buffer ..................................................................................................................................................... 2-22
Hot Socketing.......................................................................................................................................... 2-25
Sleep Mode...................................................................................................................................................... 2-25
SLEEPN Pin Characteristics................................................................................................................... 2-26
Configuration and Testing................................................................................................................................ 2-26
IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-26
Device Configuration............................................................................................................................... 2-26
Internal Logic Analyzer Capability (ispTRACY)....................................................................................... 2-27
Oscillator ................................................................................................................................................. 2-27
Density Shifting ................................................................................................................................................ 2-28
DC and Switching Characteristics
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions................................................................................................................ 3-1
Hot Socketing Specifications.............................................................................................................................. 3-2
DC Electrical Characteristics.............................................................................................................................. 3-3
Supply Current (Sleep Mode)............................................................................................................................. 3-3
Supply Current (Standby)................................................................................................................................... 3-4
Initialization Supply Current ............................................................................................................................... 3-5
Programming and Erase Flash Supply Current ................................................................................................. 3-6
sysIO Recommended Operating Conditions...................................................................................................... 3-7
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-8
sysIO Differential Electrical Characteristics ....................................................................................................... 3-9
LVDS......................................................................................................................................................... 3-9
Differential HSTL and SSTL............................................................................................................................. 3-10
LVDS25E ................................................................................................................................................ 3-10
BLVDS .................................................................................................................................................... 3-10
LVPECL .................................................................................................................................................. 3-12
RSDS ...................................................................................................................................................... 3-12
Typical Building Block Function Performance.................................................................................................. 3-14
Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ............................................................................... 3-14
Register to Register Performance........................................................................................................... 3-14
Derating Logic Timing ...................................................................................................................................... 3-15
LatticeXP External Switching Characteristics .................................................................................................. 3-16
LatticeXP Internal Timing Parameters ............................................................................................................. 3-18
Timing Diagrams.............................................................................................................................................. 3-20
PFU Timing Diagrams............................................................................................................................. 3-20
EBR Memory Timing Diagrams........................................................................................................................ 3-21
LatticeXP Family Timing Adders...................................................................................................................... 3-23
sysCLOCK PLL Timing .................................................................................................................................... 3-25
LatticeXP sysCONFIG Port Timing Specifications........................................................................................... 3-26
Flash Download Time ...................................................................................................................................... 3-27
JTAG Port Timing Specifications ..................................................................................................................... 3-27
Switching Test Conditions................................................................................................................................ 3-28
Pinout Information
Signal Descriptions ............................................................................................................................................ 4-1
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3
Pin Information Summary................................................................................................................................... 4-4
Power Supply and NC Connections................................................................................................................... 4-6
LFXP3 Logic Signal Connections: 100 TQFP.................................................................................................... 4-7
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP................................................................................... 4-10
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP .................................................................................. 4-14
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA................................................................................ 4-19
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA.............................................................................. 4-26
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA............................................................... 4-34
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA.............................................................................. 4-43
Thermal Management...................................................................................................................................... 4-56
For Further Information ........................................................................................................................... 4-56
Ordering Information
Part Number Description.................................................................................................................................... 5-1
Ordering Information (Contact Factory for Specific Device Availability)............................................................. 5-1
Conventional Packaging ........................................................................................................................... 5-2
Lead-free Packaging................................................................................................................................. 5-8
Supplemental Information
For Further Information ...................................................................................................................................... 6-1
LatticeXP Family Data Sheet Revision History
Revision History ................................................................................................................................................. 7-1
Section II. LatticeXP Family Technical Notes
LatticeECP/EC and LatticeXP sysIO Usage Guide
Introduction ........................................................................................................................................................ 8-1
sysIO Buffer Overview ....................................................................................................................................... 8-1
Supported sysIO Standards............................................................................................................................... 8-1
sysIO Banking Scheme...................................................................................................................................... 8-2
V
(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-3
CCIO
2
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
V
V
(3.3V)........................................................................................................................................... 8-3
(1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-3
CCAUX
CCJ
Input Reference Voltage (V
V
)................................................................................................... 8-3
REF1, REF2
V
for DDR Memory Interface ............................................................................................................. 8-3
REF1
Mixed Voltage Support in a Bank.............................................................................................................. 8-4
sysIO Standards Supported in Each Bank......................................................................................................... 8-5
LVCMOS Buffer Configurations ......................................................................................................................... 8-5
Programmable Pull-up/Pull-Down/Buskeeper........................................................................................... 8-5
Programmable Drive ................................................................................................................................. 8-5
Programmable Slew Rate ......................................................................................................................... 8-7
Open Drain Control ................................................................................................................................... 8-7
Differential SSTL and HSTL Support ................................................................................................................. 8-7
PCI Support with Programmable PCICLAMP .................................................................................................... 8-7
5V Interface with PCI Clamp Diode.................................................................................................................... 8-8
Programmable Input Delay ................................................................................................................................ 8-9
Software sysIO Attributes................................................................................................................................... 8-9
IO_TYPE................................................................................................................................................... 8-9
OPENDRAIN........................................................................................................................................... 8-10
DRIVE ..................................................................................................................................................... 8-10
PULLMODE ............................................................................................................................................ 8-11
PCICLAMP.............................................................................................................................................. 8-11
SLEWRATE ............................................................................................................................................ 8-11
FIXEDDELAY.......................................................................................................................................... 8-11
DIN/DOUT............................................................................................................................................... 8-11
LOC......................................................................................................................................................... 8-12
Design Considerations and Usage................................................................................................................... 8-12
Banking Rules......................................................................................................................................... 8-12
Differential I/O Rules............................................................................................................................... 8-12
Assigning V
/ V
Groups for Referenced Inputs............................................................................. 8-12
REF
REF
Differential I/O Implementation......................................................................................................................... 8-13
LVDS....................................................................................................................................................... 8-13
BLVDS .................................................................................................................................................... 8-13
RSDS ...................................................................................................................................................... 8-13
LVPECL .................................................................................................................................................. 8-13
Differential SSTL and HSTL.................................................................................................................... 8-13
Technical Support Assistance.......................................................................................................................... 8-13
Appendix A. HDL Attributes for Synplify® and Precision® RTL Synthesis ........................................................ 8-15
VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-15
Syntax ..................................................................................................................................................... 8-15
Examples ................................................................................................................................................ 8-15
Verilog for Synplify ........................................................................................................................................... 8-18
Syntax ..................................................................................................................................................... 8-18
Examples ................................................................................................................................................ 8-18
Verilog for Precision RTL Synthesis................................................................................................................. 8-20
Syntax ..................................................................................................................................................... 8-20
Example .................................................................................................................................................. 8-20
Appendix B. sysIO Attributes Using Preference Editor User Interface............................................................. 8-22
Appendix C. sysIO Attributes Using Preference File (ASCII File).................................................................... 8-23
IOBUF ..................................................................................................................................................... 8-23
LOCATE.................................................................................................................................................. 8-23
USE DIN CELL........................................................................................................................................ 8-24
USE DOUT CELL.................................................................................................................................... 8-24
PGROUP VREF...................................................................................................................................... 8-24
3
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
Memory Usage Guide for LatticeECP/EC and LatticeXP Devices
Introduction ........................................................................................................................................................ 9-1
Memories in LatticeECP/EC and LatticeXP Devices ......................................................................................... 9-1
Utilizing IPexpress.............................................................................................................................................. 9-3
IPexpress Flow.......................................................................................................................................... 9-3
Memory Modules................................................................................................................................................ 9-7
Single Port RAM (RAM_DQ) – EBR Based .............................................................................................. 9-7
True Dual Port RAM (RAM_DP_TRUE) – EBR Based........................................................................... 9-13
Pseudo Dual Port RAM (RAM_DP) – EBR-Based.................................................................................. 9-22
Read Only Memory (ROM) – EBR Based............................................................................................... 9-25
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................... 9-28
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-44
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based............................................................ 9-46
Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-49
Initializing Memory ........................................................................................................................................... 9-51
Initialization File Format .......................................................................................................................... 9-51
Technical Support Assistance.......................................................................................................................... 9-53
Revision History ............................................................................................................................................... 9-53
Appendix A. Attribute Definitions...................................................................................................................... 9-54
DATA_WIDTH......................................................................................................................................... 9-54
REGMODE.............................................................................................................................................. 9-54
RESETMODE ......................................................................................................................................... 9-54
CSDECODE............................................................................................................................................ 9-54
WRITEMODE.......................................................................................................................................... 9-54
GSR ........................................................................................................................................................ 9-54
LatticeECP/EC and LatticeXP DDR Usage Guide
Introduction ...................................................................................................................................................... 10-1
DDR SDRAM Interfaces Overview................................................................................................................... 10-1
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices........................................................ 10-2
DQS Grouping......................................................................................................................................... 10-2
DDR Software Primitives......................................................................................................................... 10-5
Memory Read Implementation................................................................................................................ 10-9
Data Read Critical Path......................................................................................................................... 10-12
DQS Postamble .................................................................................................................................... 10-13
Memory Write Implementation .............................................................................................................. 10-14
Design Rules/Guidelines....................................................................................................................... 10-16
QDR II Interface .................................................................................................................................... 10-17
FCRAM (Fast Cycle Random Access Memory) Interface..................................................................... 10-17
Generic High Speed DDR Implementation .................................................................................................... 10-17
Board Design Guidelines ............................................................................................................................... 10-17
References..................................................................................................................................................... 10-18
Technical Support Assistance........................................................................................................................ 10-18
Revision History ............................................................................................................................................. 10-18
Appendix A. Using IPexpress™ to Generate DDR Modules.......................................................................... 10-19
DDR Generic......................................................................................................................................... 10-19
DDR Memory Interface ......................................................................................................................... 10-20
Appendix B. Verilog Example for DDR Input and Output Modules ................................................................ 10-21
Appendix C. VHDL Example for DDR Input and Output Modules.................................................................. 10-24
Appendix D. Generic (Non-Memory) High-Speed DDR Interface.................................................................. 10-29
VHDL Implementation........................................................................................................................... 10-29
Verilog Example.................................................................................................................................... 10-31
Preference File...................................................................................................................................... 10-32
Appendix E. List of Compatible DDR SDRAM ............................................................................................... 10-33
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board.......................................................... 10-36
4
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide
Introduction ...................................................................................................................................................... 11-1
Features........................................................................................................................................................... 11-1
Functional Description...................................................................................................................................... 11-1
PLL Divider and Delay Blocks................................................................................................................. 11-1
PLL Inputs and Outputs .......................................................................................................................... 11-2
PLL Attributes.......................................................................................................................................... 11-3
LatticeECP/EC and LatticeXP PLL Primitive Definitions.................................................................................. 11-4
PLL Attributes Definitions........................................................................................................................ 11-4
Dynamic Delay Adjustment..................................................................................................................... 11-6
PLL Usage in IPexpress................................................................................................................................... 11-7
Including sysCLOCK PLLs in a Design................................................................................................... 11-7
IPexpress Usage..................................................................................................................................... 11-7
EHXPLLB Example Projects................................................................................................................... 11-9
Equations for Generating Input and Output Frequency Ranges.................................................................... 11-10
f
f
Constraint ..................................................................................................................................... 11-10
Constraint...................................................................................................................................... 11-10
VCO
PFD
Clock Distribution in LatticeECP/EC and LatticeXP....................................................................................... 11-11
Primary Clock Sources and Distribution................................................................................................ 11-11
Clock Net Preferences ................................................................................................................................... 11-12
Primary-Pure and Primary-DCS............................................................................................................ 11-12
Global Primary Clock and Quadrant Primary Clock.............................................................................. 11-12
Secondary Clock Sources and Distribution........................................................................................... 11-13
Limitations on Secondary Clock Availability.......................................................................................... 11-13
Dynamic Clock Selection (DCS) .................................................................................................................... 11-14
DCS Waveforms ................................................................................................................................... 11-15
Use of DCS with PLL ............................................................................................................................ 11-17
Other Design Considerations......................................................................................................................... 11-17
Jitter Considerations ............................................................................................................................. 11-17
Simulation Limitations ........................................................................................................................... 11-17
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available ................. 11-18
DCS Usage with Verilog........................................................................................................................ 11-18
DCS Usage with VHDL .................................................................................................................................. 11-18
Technical Support Assistance........................................................................................................................ 11-19
Revision History ............................................................................................................................................. 11-19
Appendix A. Clock Preferences ..................................................................................................................... 11-20
ASIC...................................................................................................................................................... 11-20
FREQUENCY........................................................................................................................................ 11-20
MAXSKEW............................................................................................................................................ 11-20
MULTICYCLE ....................................................................................................................................... 11-20
PERIOD ................................................................................................................................................ 11-20
PROHIBIT ............................................................................................................................................. 11-20
CLOCK_TO_OUT ................................................................................................................................. 11-20
INPUT_SETUP ..................................................................................................................................... 11-21
PLL_PHASE_BACK.............................................................................................................................. 11-21
Power Estimation and Management for LatticeECP/EC and LatticeXP Devices
Introduction ...................................................................................................................................................... 12-1
Power Supply Sequencing and Hot Socketing................................................................................................. 12-1
Power Calculator Hardware Assumptions........................................................................................................ 12-1
Power Calculator.............................................................................................................................................. 12-1
Power Calculator Equations.................................................................................................................... 12-2
Starting the Power Calculator ................................................................................................................. 12-3
Starting a Power Calculator Project ........................................................................................................ 12-5
Power Calculator Main Window .............................................................................................................. 12-6
5
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
Power Calculator Wizard......................................................................................................................... 12-8
Power Calculator – Creating a New Project Without the NCD File....................................................... 12-13
Power Calculator – Creating a New Project With the NCD File............................................................ 12-14
Power Calculator – Open Existing Project ............................................................................................ 12-16
Power Calculator – Total Power............................................................................................................ 12-17
Activity Factor................................................................................................................................................. 12-17
Ambient and Junction Temperature and Airflow ............................................................................................ 12-18
Managing Power Consumption...................................................................................................................... 12-18
Power Calculator Assumptions ...................................................................................................................... 12-19
Revision History ............................................................................................................................................. 12-20
Technical Support Assistance........................................................................................................................ 12-20
Appendix A. Power Calculator Project Example ............................................................................................ 12-21
LatticeXP sysCONFIG Usage Guide
Introduction ...................................................................................................................................................... 13-1
Programming Overview.................................................................................................................................... 13-1
Configuration Pins............................................................................................................................................ 13-2
Dedicated Pins........................................................................................................................................ 13-3
Dual-Purpose sysCONFIG Pins.............................................................................................................. 13-7
ispJTAG Pins .......................................................................................................................................... 13-9
Configuration and JTAG Voltage Levels................................................................................................. 13-9
Configuration Modes and Options.................................................................................................................... 13-9
Configuration Options ........................................................................................................................... 13-10
Slave Serial Mode................................................................................................................................. 13-11
Master Serial Mode............................................................................................................................... 13-11
Slave Parallel Mode .............................................................................................................................. 13-12
Self Download Mode............................................................................................................................. 13-14
ispJTAG Mode ...................................................................................................................................... 13-14
Wake Up Options........................................................................................................................................... 13-15
Wake Up Sequence .............................................................................................................................. 13-15
Software Selectable Options.......................................................................................................................... 13-16
PERSISTENT Bit .................................................................................................................................. 13-17
Configuration Mode............................................................................................................................... 13-17
DONE Open Drain ................................................................................................................................ 13-17
DONE External...................................................................................................................................... 13-17
Master Clock Selection ......................................................................................................................... 13-18
Security ................................................................................................................................................. 13-18
Wake Up Sequence .............................................................................................................................. 13-18
Start_Up Clock Selection ...................................................................................................................... 13-18
INBUF ................................................................................................................................................... 13-19
Technical Support Assistance........................................................................................................................ 13-19
Revision History ............................................................................................................................................. 13-19
Lattice ispTRACY Usage Guide
Introduction ...................................................................................................................................................... 14-1
ispTRACY IP Core Features............................................................................................................................ 14-1
ispTRACY IP Module Generator...................................................................................................................... 14-1
ispTRACY Core Generator .............................................................................................................................. 14-2
ispTRACY Core Linker..................................................................................................................................... 14-4
ispTRACY ispLA Program................................................................................................................................ 14-6
Conclusion ....................................................................................................................................................... 14-9
References....................................................................................................................................................... 14-9
Technical Support Assistance.......................................................................................................................... 14-9
HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs
Introduction ...................................................................................................................................................... 15-1
General Coding Styles for FPGA ..................................................................................................................... 15-1
6
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
Hierarchical Coding................................................................................................................................. 15-1
Design Partitioning.................................................................................................................................. 15-2
State Encoding Methodologies for State Machines ................................................................................ 15-3
Coding Styles for FSM ............................................................................................................................ 15-5
Using Pipelines in the Designs................................................................................................................ 15-6
Comparing IF statement and CASE statement....................................................................................... 15-7
Avoiding Non-intentional Latches............................................................................................................ 15-8
HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 15-8
Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 15-8
Implementing Multiplexers .................................................................................................................... 15-10
Clock Dividers ....................................................................................................................................... 15-10
Register Control Signals ....................................................................................................................... 15-12
Use PIC Features.................................................................................................................................. 15-14
Implementation of Memories................................................................................................................. 15-16
Preventing Logic Replication and Limited Fanout................................................................................. 15-16
Use ispLEVER Project Navigator Results for Device Utilization and Performance .............................. 15-17
Technical Support Assistance........................................................................................................................ 15-17
Lattice Semiconductor FPGA Successful Place and Route
Introduction ...................................................................................................................................................... 16-1
ispLEVER Place and Route Software (PAR) ................................................................................................... 16-1
Placement ............................................................................................................................................... 16-1
Routing.................................................................................................................................................... 16-1
Timing Driven PAR Process.................................................................................................................... 16-2
General Strategy Guidelines............................................................................................................................ 16-2
Typical Design Preferences .................................................................................................................... 16-2
Proper Preferences................................................................................................................................. 16-3
Translating Board Requirements into FPGA Preferences ...................................................................... 16-4
Analyzing Timing Reports ................................................................................................................................ 16-6
Example 1. Multicycle Between Two Different Clocks ............................................................................ 16-6
Example 2. CLOCK_TO_OUT with PLL Feedback................................................................................. 16-8
ispLEVER Controlled Place and Route.......................................................................................................... 16-10
Running Multiple Routing Passes ......................................................................................................... 16-10
Using Multiple Placement Iterations (Cost Tables) ............................................................................... 16-11
Clock Boosting ...................................................................................................................................... 16-12
Guided Map and PAR .................................................................................................................................... 16-14
Notes on Guided Mapping .................................................................................................................... 16-15
Notes on Guided PAR........................................................................................................................... 16-15
Conclusion ..................................................................................................................................................... 16-15
Technical Support Assistance........................................................................................................................ 16-16
Board Timing Guidelines for the DDR SDRAM Controller IP Core
Introduction ...................................................................................................................................................... 17-1
Read Operation................................................................................................................................................ 17-2
Set-up Time Calculation for the Data Input (Max. Case) ........................................................................ 17-3
Hold Time Calculation for the Data Input (Min. Case)............................................................................. 17-3
Write Operation................................................................................................................................................ 17-4
Write Set-up ............................................................................................................................................ 17-4
Write Hold ............................................................................................................................................... 17-5
Address and Command Signals....................................................................................................................... 17-5
Set-up Calculation................................................................................................................................... 17-6
Hold Calculation...................................................................................................................................... 17-7
Board Design Guidelines ................................................................................................................................. 17-7
Technical Support Assistance.......................................................................................................................... 17-8
Appendix A. Example Extractions of Delays from Timing Reports .................................................................. 17-9
7
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
PCB Layout Recommendations for BGA Packages
Introduction ...................................................................................................................................................... 18-1
BGA Board Layout Recommendations ............................................................................................................ 18-1
BGA Breakout and Routing Examples............................................................................................................. 18-2
64-ball csBGA BGA Breakout and Routing Example.............................................................................. 18-4
64-ball ucBGA BGA Breakout and Routing Example.............................................................................. 18-5
100-ball csBGA BGA Breakout and Routing Examples.......................................................................... 18-6
132-ball csBGA BGA Breakout Examples .............................................................................................. 18-8
144-ball csBGA BGA Breakout Examples ............................................................................................ 18-10
256-ball caBGA BGA Breakout Examples ............................................................................................ 18-12
PCB Fabrication Cost and Design Rule Considerations................................................................................ 18-13
Advantages and Disadvantages of BGA Packaging...................................................................................... 18-14
BGA Package Test and Assembly................................................................................................................. 18-15
PCB Design Support...................................................................................................................................... 18-18
Technical Support Assistance........................................................................................................................ 18-18
Revision History ............................................................................................................................................. 18-19
Section III. LatticeXP Family Handbook Revision History
Revision History ............................................................................................................................................... 20-1
8
Section I. LatticeXP Family Data Sheet
DS1001 Version 05.1, November 2007
LatticeXP Family Data Sheet
Introduction
July 2007
Data Sheet DS1001
Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
Features
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• No external configuration memory
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
– SSTL 18 Class I
SSTL 3/2 Class I, II
– HSTL15 Class I, III
HSTL 18 Class I, II, III
PCI
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
through system configuration and JTAG ports
Sleep Mode
LVDS, Bus-LVDS, LVPECL, RSDS
• Allows up to 1000x static current reduction
Dedicated DDR Memory Support
TransFR™ Reconfiguration (TFR)
• Implements interface up to DDR333 (166MHz)
• In-field logic update while system operates
sysCLOCK™ PLLs
Extensive Density and Package Options
• 3.1K to 19.7K LUT4s
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
• 62 to 340 I/Os
• Density migration supported
System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• Onboard oscillator for configuration
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
Embedded and Distributed Memory
• 54 Kbits to 396 Kbits sysMEM™ Embedded
Block RAM
• Up to 79 Kbits distributed RAM
• Flexible memory resources:
Distributed and block memory
Table 1-1. LatticeXP Family Selection Guide
Device
PFU/PFF Rows
LFXP3
16
LFXP6
24
LFXP10
32
LFXP15
40
LFXP20
44
PFU/PFF Columns
PFU/PFF (Total)
LUTs (K)
24
30
38
48
56
384
3
720
6
1216
10
1932
15
2464
20
Distributed RAM (KBits)
EBR SRAM (KBits)
EBR SRAM Blocks
12
23
39
61
79
54
72
216
24
324
36
396
44
6
8
VCC Voltage
1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V
PLLs
2
2
4
4
4
Max. I/O
136
188
244
300
340
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
388-ball fpBGA (23 x 23 mm)
484-ball fpBGA (23 x 23 mm)
62
100
136
100
142
188
188
244
188
268
300
188
268
340
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1001 Introduction_01.5
Introduction
Lattice Semiconductor
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
LatticeXP Family Data Sheet
Architecture
July 2007
Data Sheet DS1001
Architecture Overview
The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-
1.
On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this non-
volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,
the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this
technology, expensive external configuration memories are not required and designs are secured from unauthor-
ized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in
microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeXP architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from
3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1001 Architecture_02.0
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-1. LatticeXP Top Level Block Diagram
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
Non-volatile Memory
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 3
Slice 0
Slice 1
Slice 2
D
D
D
D
FF/
D
D
FF/
D
D
FF/
FF/
FF/
FF/
FF/
FF/
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
To
Routing
2-2
Architecture
Lattice Semiconductor
Slice
LatticeXP Family Data Sheet
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Figure 2-3. Slice Diagram
To / From
Different slice / PFU Fast Carry In (FCI)
Slice
OFX1
F1
A1
B1
C1
D1
CO
F
LUT4 &
CARRY
D
SUM
FF/
Latch
Q1
CI
To
From
Routing
Routing
M1
M0
OFX0
F0
LUT
Expansion
Mux
CO
A0
B0
C0
LUT4 &
CARRY
F
D0
OFX0
SUM
D
FF/
Latch
Q0
CI
Control Signals
selected and
inverted per
CE
CLK
LSR
slice in routing
Note: Some interslice signals
are not shown.
To / From
Different slice / PFU Fast Carry Out (FCO)
2-3
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-1. Slice Signal Descriptions
Function
Input
Type
Signal Names
Description
Data signal
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Input
Data signal
Input
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0
M1
Multipurpose Input
Multipurpose Input
Clock Enable
Input
Input
CE
Input
LSR
Local Set/Reset
Input
CLK
System Clock
Fast Carry In1
Input
FCIN
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Output
Output
Output
Output
Output
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
For the right most PFU the fast carry chain output1
1. See Figure 2-2 for connection details.
2. Requires two PFUs.
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic
Ripple
RAM
SP 16x2
N/A
ROM
PFU Slice
PFF Slice
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
2-bit Arithmetic Unit
ROM 16x1 x 2
ROM 16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Ripple mode multiplier building block
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
2-4
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode
in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required for Implementing Distributed RAM
SPR16x2
DPR16x2
Number of Slices
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
Figure 2-4. Distributed Memory Primitives
SPR16x2
DPR16x2
AD0
AD1
AD2
AD3
RAD0
RAD1
RAD2
RAD3
WAD0
WAD1
WAD2
WAD3
DO0
DO1
DI0
DI1
WRE
DI0
DI1
WCK
WRE
RDO0
RDO1
WDO0
WDO1
CK
ROM16x1
AD0
AD1
AD2
AD3
DO0
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
2-5
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-4. PFU Modes of Operation
Logic
Ripple
RAM1
ROM
LUT 4x8 or
MUX 2x1 x 8
SPR16x2 x 4
DPR16x2 x 2
2-bit Add x 4
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
SPR16x4 x 2
DPR16x4 x 1
2-bit Sub x 4
2-bit Counter x 4
2-bit Comp x 4
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
LUT 6x 2 or
MUX 8x1 x 2
SPR16x8 x 1
LUT 7x1 or
MUX 16x1 x 1
1. These modes are not available in PFF blocks
Routing
There are many resources provided in the LatticeXP devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The
x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-
ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four
dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.
2-6
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-5. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
PLL Input
PLL
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Clock Input
Clock Input
PLL
PLL
PLL Input
PLL Input
From Routing
Clock Input
From Routing
Note: Smaller devices have two PLLs.
Secondary Clock Sources
LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at
every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary
clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.
2-7
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-6. Secondary Clock Sources
Clock
Input
From
Routing
From
Routing
From
Routing
From
Routing
From Routing
From Routing
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
Clock
Input
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS2
DCS2
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
2-8
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-8. Per Quadrant Secondary Clock Selection
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
4 Secondary Clocks per Quadrant
Figure 2-9. Slice Clock Selection
Primary Clock
Secondary Clock
Routing
Clock to Each Slice
GND
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nals to the feedback divider: from CLKOP (PLL internal), from clock net (CLKOP or CLKOS) or from a user clock
(PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-
10 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the t
parameter has been satisfied. Additionally, the phase and duty cycle block
LOCK
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
2-9
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-10. PLL Diagram
Dynamic Delay Adjustment
LOCK
RST
Input Clock
Divider
(CLKI)
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
Voltage
Controlled
Oscillator
CLKOS
Delay
Adjust
CLKI
(from routing or
external pin)
CLKOP
Secondary
Clock
CLKOK
Divider
Feedback
Divider
(CLKFB)
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
from a user
(CLKOK)
clock (PIN or logic)
Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.
Figure 2-11. PLL Primitive
CLKOP
RST
CLKI
CLKI
CLKOP
LOCK
CLKOS
CLKOK
LOCK
EPLLB
CLKFB
CLKFB
DDA MODE
DDAIZR
EHXPLLB
DDAOZR
DDAILAG
DDAOLAG
DDAODEL[2:0]
DDAIDEL[2:0]
Table 2-5. PLL Signal Descriptions
Signal
I/O
Description
CLKI
I
I
Clock input from external pin or routing
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
CLKFB
RST
I
“1” to reset input clock divider
CLKOS
O
O
O
O
I
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
Dynamic Delay Input
I
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
I
I
O
O
O
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
2-10
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
the DCS Block Macro.
Figure 2-12. DCS Block Primitive
CLK0
DCS
CLK1
SEL
DCSOUT
Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-13. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of
a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
2-11
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-6. sysMEM Block Configurations
Memory Mode
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
True Dual Port
Pseudo Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-14 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
2-12
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-14. sysMEM Memory Primitives
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
AD[12:0]
DI[35:0]
CLK
DO[35:0]
CE
EBR
EBR
RST
WE
CS[2:0]
True Dual Port RAM
Single Port RAM
ADW[12:0]
DI[35:0]
CLKW
CEW
ADR[12:0]
DO[35:0]
AD[12:0]
CLK
DO[35:0]
CE
EBR
EBR
WE
RST
CS[2:0]
CER
RST
CS[2:0]
CLKR
ROM
Pseudo-Dual Port RAM
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through -þa copy of the input data appears at the output of the same port during a write cycle.þThis
mode is supported for all data widths.
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-15.
2-13
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-15. Memory Core Reset
SET
Q
Memory Core
Port A[17:0]
Port B[17:0]
LCLR
Output Data
Latches
SET
D
Q
LCLR
RSTA
RSTB
GSRN
Programmable Disable
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
(EBR clock). The reset
MAX
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
2-14
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-17. PIC Diagram
PIO A
TD
D0
TD
OPOS1
ONEG1
D1
DDRCLK
IOLT0
DO
Tristate
Register Block
(2 Flip Flops)
PADA
"T"
D0
D1
OPOS0
ONEG0
DDRCLK
IOLD0
Output
Register Block
(2 Flip Flops)
sysIO
Buffer
INCK
INDD
INCK
INDD
INFF
INFF
IPOS0
IPOS1
IPOS0
IPOS1
DI
Control
Muxes
Input
Register Block
(5 Flip Flops)
CLKO
CEO
LSR
CLK
CE
LSR
GSR
CLKI
CEI
GSRN
DQS
DDRCLKPOL
PADB “C”
PIO B
In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs,
one PIC pair and one single I/O, as shown in Figure 2-18.
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”). The PAD Labels “T” and
“C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as
LVDS transmit/receive pairs.
One of every 14 PIOs (a group of 8 PICs) contains a delay element to facilitate the generation of DQS signals as
shown in Figure 2-19. The DQS signal feeds the DQS bus which spans the set of 13 PIOs (8 PICs). The DQS sig-
nal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is
designed for memories that support one DQS strobe per eight bits of data.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table in this data sheet.
2-15
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-18. Group of Seven PIOs
PADA “T”
LVDS Pair
PADB “C”
PIO A
PIO B
PIO A
PIO B
PIO A
PADA “T”
One PIO Pair
PADB “C”
Four PICs
PADA “T”
LVDS Pair
PIO B
PIO A
PADB “C”
PADA “T”
Figure 2-19. DQS Routing
PADA “T”
LVDS Pair
PADB “C”
PIO A
PIO B
PADA “T”
PADB “C”
PIO A
PIO B
PADA “T”
LVDS Pair
PADB “C”
PIO A
PIO B
PADA “T”
PIO A
PADB “C”
PIO B
PIO A
PIO B
sysIO
Buffer
Assigned DQS Pin
PADA “T”
LVDS Pair
DQS
Delay
PADB “C”
PADA “T”
PADB “C”
PIO A
PIO B
PADA “T”
LVDS Pair
PADB “C”
PIO A
PIO B
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
2-16
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-
ment when using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,
see the DDR memory section of this data sheet.
Figure 2-20. Input Register Diagram
DI
(From sysIO
Buffer)
INCK
INDD
Delay Block
Fixed Delay
SDR & Sync
Registers
DDR Registers
D0
D2
To Routing
Q
D
Q
D
D
IPOS0
IPOS1
D-Type
/LATCH
D-Type
D1
Q
D
Q
Q
D
D-Type
/LATCH
D-Type
D-Type
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR Polarity
Control Bus)
2-17
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-21. Input Register DDR Waveforms
DI
F
A
B
C
D
E
(In DDR Mode)
DQS
DQS
Delayed
B
A
D
C
D0
D2
Figure 2-22. INDDRXB Primitive
D
ECLK
QA
QB
LSR
SCLK
IDDRXB
CE
DDRCLKPOL
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-23 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
2-18
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-23. Output Register Block
OUTDDN
Q
D
D-Type
/LATCH
ONEG0
0
DO
0
1
1
From
Routing
To sysIO
Buffer
OPOS0
Q
D
LATCH
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Figure 2-24. ODDRXB Primitive
DA
DB
ODDRXB
Q
CLK
LSR
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
2-19
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-25. Tristate Register Block
TD
OUTDDN
Q
D
D-Type
/LATCH
ONEG1
0
TO
0
1
From
Routing
1
To sysIO
Buffer
OPOS1
Q
D
LATCH
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeXP
devices provide this capability. In addition to these registers, the LatticeXP devices contain two elements to simplify
the design of input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing
resource. The DQS signal also feeds the polarity control logic which controls the polarity of the clock to the sync
registers in the input register blocks. Figures 2-26 and 2-27 show how the polarity control logic are routed to the
PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-27. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
2-20
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-26. DQS Local Bus
Delay
Control
Bus
PIO
DDR
Datain
PAD
sysIO
Buffer
Input
Register Block
( 5 Flip Flops)
Polarity
Control
Bus
To Sync.
Reg.
DI
GSR
CLKI
CEI
DQS
Bus
To DDR
Reg.
DQS
DQS
PIO
DQS
Strobe
PAD
sysIO
Buffer
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration Bus
from DLL
Figure 2-27. DLL Calibration Bus and DQS/DQS Transition Distribution
Delay Control Bus
Polarity Control Signal Bus
DQS Signal Bus
DLL
DLL
2-21
Architecture
Lattice Semiconductor
Polarity Control Logic
LatticeXP Family Data Sheet
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeXP family contains dedicated circuits to transfer data between these domains. To prevent setup and
hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of the each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each sysIO
bank has its own I/O supply voltage (V
), and two voltage references V
and V
resources allowing each
CCIO
REF1
REF2
bank to be completely independent from each other. Figure 2-28 shows the eight banks and their associated sup-
plies.
In the LatticeXP devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-X) are
powered using V
independent of V
. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as a fixed threshold input
CCIO
In addition to the bank V
supplies, the LatticeXP devices have a V core logic power sup-
CCIO.
CCIO
CC
ply, and a V
supply that power all differential and referenced buffers.
CCAUX
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be configured to be a reference voltage
supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.
2-22
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-28. LatticeXP Banks
1
1
N
1
N
1
Bank 0
Bank 1
VCCIO7
VCCIO2
VREF1(2)
VREF2(2)
GND
VREF1(7)
VREF2(7)
GND
M
1
M
1
VCCIO6
VCCIO3
VREF1(6)
VREF2(6)
VREF1(3)
VREF2(3)
GND
GND
M
N
M
Bank 5
Bank 4
1
N
1
Note: N and M are the maximum number of I/Os per bank.
LatticeXP devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamps. Note that the PCI clamp is enabled after V
CC,
V
and V
are at valid operating levels and the device has been configured.
CCAUX
CCIO
2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Select I/Os in the left and right banks have LVDS differential output drivers. Refer to the Logic Signal Connec-
tions tables for more information.
2-23
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V and V
have reached satisfactory levels.
CCAUX
CC
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other V banks are active with valid input logic levels to properly control the output logic states of all the
CCIO
I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state
with a weak pull-up to VCCIO. The I/O pins will not take on the user configuration until VCC, VCCAUX and VCCIO
have reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The V and V
supply the power to the FPGA core fabric, whereas the V
supplies power to the I/O buf-
CC
CCAUX
CCIO
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V supplies should be powered up before or
CCIO
together with the V and V
supplies.
CC
CCAUX
Supported Standards
The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,
1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for
drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other sin-
gle-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS,
LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their
supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO
buffer to support a variety of standards please see the details of additional technical documentation at the end of
this data sheet.
Table 2-7. Supported Input Standards
Input Standard
Single Ended Interfaces
LVTTL
LVCMOS332
LVCMOS252
VREF (Nom.)
VCCIO1 (Nom.)
—
—
—
—
—
1.8
1.5
—
3.3
—
—
—
—
—
—
—
—
LVCMOS18
—
LVCMOS15
LVCMOS122
—
—
PCI
—
HSTL18 Class I, II
HSTL18 Class III
HSTL15 Class I
0.9
1.08
0.75
0.9
1.5
1.25
0.9
HSTL15 Class III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BLVDS
1. When not specified VCCIO can be set anywhere in the valid operating range.
2. JTAG inputs do not have a fixed threshold option and always follow VCCJ.
2-24
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-8. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
Drive
VCCIO (Nom.)
4mA, 8mA, 12mA, 16mA, 20mA
3.3
3.3
2.5
1.8
1.5
1.2
—
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
LVCMOS25
4mA, 8mA, 12mA 16mA, 20mA
LVCMOS18
4mA, 8mA, 12mA 16mA
LVCMOS15
4mA, 8mA
LVCMOS12
2mA, 6mA
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
—
4mA, 8mA, 12mA 16mA
—
4mA, 8mA
2mA. 6mA
N/A
—
—
3.3
1.8
1.5
3.3
2.5
1.8
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
N/A
N/A
N/A
SSTL2 Class I, II
N/A
SSTL18 Class I
N/A
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
BLVDS1
LVPECL1
1. Emulated with external resistors.
Hot Socketing
The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os
remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits, which allows easy integration with the rest of the system.
These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications.
Sleep Mode
The LatticeXP “C” devices (V = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up
CC
to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the
SLEEPN pin.
During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os
are tri-stated. Do not enter Sleep Mode during device programming or configuration operation. In Sleep Mode,
power supplies can be maintained in their normal operating range, eliminating the need for external switching of
power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes.
2-25
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-9. Characteristics of Normal, Off and Sleep Modes
Characteristic
SLEEPN Pin
Normal
High
Off
—
Sleep
Low
Static Icc
Typical <100mA
<10µA
0
Typical <100uA
<10µA
I/O Leakage
<1mA
Off
Power Supplies VCC/VCCIO/VCCAUX
Logic Operation
Normal Range
User Defined
User Defined
Operational
Maintained
Normal Range
Non Operational
Tri-state
Non operational
Tri-state
I/O Operation
JTAG and Programming circuitry
EBR Contents and Registers
Non-operational
Non-maintained
Non-operational
Non-maintained
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up typically in the order of 10µA along with a Schmidt trigger and glitch filter
to prevent false triggering. An external pull-up to V is recommended when Sleep Mode is not used to ensure the
CC
device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN
is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC
specifications portion of this data sheet show a detailed timing diagram.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeXP family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
and can
CCJ
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The
test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide
and serial configuration.
The non-volatile memory in the LatticeXP can be configured in three different modes:
• In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.
• In 1532 mode via the 1149.1 port.
• In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes
place.
The SRAM configuration memory can be configured in three different ways:
• At power-up via the on-chip non-volatile memory.
• In 1532 mode via the 1149.1 port SRAM direct configuration.
• In sysCONFIG mode via the sysCONFIG port SRAM direct configuration.
2-26
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lattic-
eXP devices.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port.
Leave Alone I/O
When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or
held at current value. This provides excellent flexibility for implementing systems where reprogramming occurs on-
the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Configuration Using TransFR Technology, for details.
Security
The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-29. ispXP Block Diagram
ISP 1149.1 TAP Port
sysCONFIG Peripherial Port
Port
sysCONFIG
BACKGND
1532
Mode
Configure in milliseconds
Program in seconds
Power-up
Refresh
SRAM
Memory Space
Memory Space
Download in microseconds
Memory Space
Internal Logic Analyzer Capability (ispTRACY)
All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-
ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-
ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile
time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
Oscillator
Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configura-
tion. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the
2-27
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
master serial clock is 2.5MHz. Table 2-10 lists all the available Master Serial Clock frequencies. When a different
Master Serial Clock is selected during the design process, the following sequence takes place:
1. User selects a different Master Serial Clock frequency for configuration.
2. During configuration the device starts with the default (2.5MHz) Master Serial Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Serial Clock frequency changes to the selected frequency once the clock configuration bits are
received.
For further information on the use of this oscillator for configuration, please see details of additional technical docu-
mentation at the end of this data sheet.
Table 2-10. Selectable Master Serial Clock (CCLK) Frequencies During Configuration
CCLK (MHz)
CCLK (MHz)
CCLK (MHz)
2.51
13
15
20
26
30
34
41
45
51
55
60
130
—
4.3
5.4
6.9
8.1
9.2
10.0
—
1. Default
Density Shifting
The LatticeXP family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from
lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design tar-
geted for a high-density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
2-28
LatticeXP Family Data Sheet
DC and Switching Characteristics
Data Sheet DS1001
November 2007
Absolute Maximum Ratings1, 2, 3, 4
XPE (1.2V)
XPC (1.8V/2.5V/3.3V)
Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
CC
Supply Voltage V
Supply Voltage V
Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
CCP
. . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
CCAUX
. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
CCJ
Output Supply Voltage V
. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
CCIO
I/O Tristate Voltage Applied5 . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Dedicated Input Voltage Applied 5 . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V
Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C . . . . . . . . . . . . . . . . . . . +125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions outside of those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All chip grounds are connected together to a common package GND plane.
5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Recommended Operating Conditions3
Symbol
Parameter
Core Supply Voltage for 1.2V Devices
Min.
1.14
1.71
1.14
1.71
3.135
1.14
1.14
0
Max.
1.26
3.465
1.26
3.465
3.465
3.465
3.465
85
Units
V
VCC
Core Supply Voltage for 1.8V/2.5V/3.3V Devices
Supply Voltage for PLL for 1.2V Devices
Supply Voltage for PLL for 1.8V/2.5V/3.3V Devices
Auxiliary Supply Voltage
V
V
VCCP
V
4
VCCAUX
V
1, 2
VCCIO
I/O Driver Supply Voltage
V
1
VCCJ
Supply Voltage for IEEE 1149.1 Test Access Port
Junction Temperature, Commercial Operation
Junction Temperature, Industrial Operation
V
tJCOM
tJIND
C
-40
100
C
tJFLASHCOM Junction Temperature, Flash Programming, Commercial
tJFLASHIND Junction Temperature, Flash Programming, Industrial
0
85
C
0
85
C
1. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. For the XPE devices (1.2V VCC), if VCCIO or
CCJ is set to 1.2V, they must be connected to the same power supply as VCC
2. See recommended voltages by I/O standard in subsequent table.
V
.
3. The system designer must ensure that the FPGA design stays within the specified junction temperature and package thermal capabilities of
the device based on the expected operating frequency, activity factor and environment conditions of the system.
4. VCCAUX ramp rate must not exceed 30mV/µs during power up when transitioning between 0V and 3.3V.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
3-1
DS1001 DC and Switching_02.7
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Hot Socketing Specifications1, 2, 3, 4, 5, 6
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
IDK
Input or I/O Leakage Current
0 VIN VIH (MAX.)
—
—
+/-1000
µA
1. Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO.
2. 0 VCC VCC (MAX) or 0 VCCAUX VCCAUX (MAX).
3. 0 VCCIO VCCIO (MAX) for top and bottom I/O banks.
4. 0.2 VCCIO VCCIO (MAX) for left and right I/O banks.
5. IDK is additive to IPU, IPW or IBH
.
6. LVCMOS and LVTTL only.
3-2
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
0 VIN (VCCIO - 0.2V)
(VCCIO - 0.2V) < VIN 3.6V
0 VIN 0.7 VCCIO
Min.
Typ.
—
—
—
—
—
—
—
—
—
Max.
10
Units
µA
µA
µA
µA
µA
µA
µA
µA
V
—
—
1, 2, 4
I
IL, IIH
Input or I/O Leakage
40
IPU
I/O Active Pull-up Current
-30
-150
150
IPD
I/O Active Pull-down Current
VIL (MAX) VIN VIH (MAX)
30
IBHLS
IBHHS
IBHLO
IBHHO
VBHT
Bus Hold Low sustaining current VIN = VIL (MAX)
Bus Hold High sustaining current VIN = 0.7VCCIO
Bus Hold Low Overdrive current 0 VIN VIH (MAX)
Bus Hold High Overdrive current 0 VIN VIH (MAX)
30
—
-30
—
—
150
—
-150
VIH (MIN)
Bus Hold trip Points
I/O Capacitance3
0 VIN VIH (MAX)
VIL (MAX)
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
C1
C2
—
—
8
8
—
—
pf
pf
VCC = 1.2V, VIO = 0 to VIH (MAX)
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
CC = 1.2V, VIO = 0 to VIH (MAX)
Dedicated Input Capacitance3
V
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. Not applicable to SLEEPN/TOE pin.
3. TA 25°C, f = 1.0MHz
4. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can be expected on the
high-to-low transition.
Supply Current (Sleep Mode)1, 2, 3
Symbol
Parameter
Device
LFXP3C
Typ.4
12
14
16
18
20
1
Max
65
Units
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
LFXP6C
75
ICC
Core Power Supply
LFXP10C
LFXP15C
LFXP20C
All LFXP ‘C’ Devices
LFXP3C
85
95
105
5
ICCP
PLL Power Supply (per PLL)
Auxiliary Power Supply
2
90
LFXP6C
2
100
110
120
130
20
ICCAUX
LFXP10C
LFXP15C
LFXP20C
LFXP3C
2
3
4
2
LFXP6C
2
22
ICCIO
Bank Power Supply5
VCCJ Power Supply
LFXP10C
LFXP15C
LFXP20C
All LFXP ‘C’ Devices
2
24
3
27
4
30
ICCJ
1
5
1. Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND.
2. Frequency 0MHz.
3. User pattern: blank.
4. TA=25°C, power supplies at nominal voltage.
5. Per bank.
3-3
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol
Parameter
Device
LFXP3E
LFXP6E
LFXP10E
LFXP15E
LFXP20E
LFXP3C
LFXP6C
LFXP10C
LFXP15C
LFXP20C
Typ.5
15
20
35
45
55
35
40
70
80
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICC
Core Power Supply
PLL Power Supply
(per PLL)
ICCP
All
8
mA
LFXP3E/C
LFXP6E/C
LFXP10E/C
LFXP15E/C
LFXP20E/C
All
22
22
30
30
30
2
mA
mA
mA
mA
mA
mA
mA
Auxiliary Power Supply
ICCAUX
VCCAUX = 3.3V
ICCIO
ICCJ
Bank Power Supply6
VCCJ Power Supply
All
1
1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. Frequency 0MHz.
4. User pattern: blank.
5. TA=25°C, power supplies at nominal voltage.
6. Per bank.
3-4
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Initialization Supply Current1, 2, 3, 4, 5, 6
Over Recommended Operating Conditions
Symbol
Parameter
Device
LFXP3E
Typ.7
40
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFXP6E
50
LFXP10E
LFXP15E
LFXP20E
LFXP3C
110
140
250
60
ICC
Core Power Supply
LFXP6C
70
LFXP10C
LFXP15C
LFXP20C
LFXP3E/C
LFXP6E/C
LFXP10E/C
LFXP15 /C
LFXP20E/C
All
150
180
290
50
60
Auxiliary Power Supply
CCAUX = 3.3V
ICCAUX
90
V
110
130
2
ICCJ
VCCJ Power Supply
1. Until DONE signal is active.
2. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
4. Frequency 0MHz.
5. Typical user pattern.
6. Assume normal bypass capacitor/decoupling capacitor across the supply.
7. TA=25°C, power supplies at nominal voltage.
3-5
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Programming and Erase Flash Supply Current1, 2, 3, 4, 5
Symbol
Parameter
Device
LFXP3E
Typ.6
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
30
LFXP6E
40
LFXP10E
LFXP15E
LFXP20E
LFXP3C
50
60
70
ICC
Core Power Supply
50
LFXP6C
60
LFXP10C
LFXP15C
LFXP20C
LFXP3E/C
LFXP6E/C
LFXP10E/C
LFXP15E/C
LFXP20E/C
All
90
100
110
50
60
Auxiliary Power Supply
CCAUX = 3.3V
ICCAUX
90
V
110
130
2
ICCJ
VCCJ Power Supply7
1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. Blank user pattern; typical Flash pattern.
4. Bypass or decoupling capacitor across the supply.
5. JTAG programming is at 1MHz.
6. TA=25°C, power supplies at nominal voltage.
7. When programming via JTAG.
3-6
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
sysIO Recommended Operating Conditions
VCCIO
VREF (V)
Standard
LVCMOS 3.3
Min.
3.135
2.375
1.71
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.8
2.5
3.3
1.5
1.5
1.8
1.8
2.5
3.3
2.5
Max.
3.465
2.625
1.89
Min.
—
Typ.
—
Max.
—
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
LVTTL
—
—
—
—
—
—
1.425
1.14
1.575
1.26
—
—
—
—
—
—
3.135
3.135
1.71
3.465
3.465
1.89
—
—
—
PCI33
—
—
—
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL15 Class III
HSTL 18 Class I, II
HSTL 18 Class III
LVDS
0.833
1.15
1.3
0.68
—
0.9
1.25
1.5
0.75
0.9
0.9
1.08
—
0.969
1.35
1.7
0.9
—
2.375
3.135
1.425
1.425
1.71
2.625
3.465
1.575
1.575
1.89
—
—
1.71
1.89
—
—
2.375
3.135
2.375
2.625
3.465
2.625
—
—
LVPECL1
BLVDS1
—
—
—
—
—
—
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
3-7
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
sysIO Single-Ended DC Electrical Characteristics
VIL
VIH
Min. (V)
Input/Output
Standard
VOL Max.
(V)
VOH Min.
(V)
IOL
(mA)
IOH
(mA)
Min. (V) Max. (V)
Max. (V)
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.4
0.2
0.4
0.2
0.4
V
CCIO - 0.4
VCCIO - 0.2
VCCIO - 0.4
LVCMOS 3.3
LVTTL
-0.3
-0.3
-0.3
0.8
0.8
0.7
2.0
2.0
1.7
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
3.6
3.6
V
V
CCIO - 0.2
CCIO - 0.4
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
LVCMOS 2.5
0.2
0.4
VCCIO - 0.2
0.1
-0.1
-16, -12, -8, -4
-0.1
VCCIO - 0.4 16, 12, 8, 4
LVCMOS 1.8
LVCMOS 1.5
-0.3
-0.3
-0.3
-0.3
0.35VCCIO
0.35VCCIO
0.42
0.65VCCIO
0.65VCCIO
0.78
3.6
3.6
3.6
3.6
0.2
V
CCIO - 0.2
VCCIO - 0.4
CCIO - 0.2
0.1
8, 4
0.1
6, 2
0.1
6, 2
0.1
1.5
8
0.4
-8, -4
-0.1
0.2
V
0.4
VCCIO - 0.4
VCCIO - 0.2
VCCIO - 0.4
-6, -2
-0.1
LVCMOS 1.2
(“C” Version)
0.2
0.4
-6, -2
-0.1
LVCMOS 1.2
(“E” Version)
0.35VCC
0.3VCCIO
0.65VCC
0.2
VCCIO - 0.2
PCI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
0.5VCCIO
VREF + 0.2
VREF + 0.2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1VCCIO
0.7
0.9VCCIO
VCCIO - 1.1
VCCIO - 0.9
VCCIO - 0.62
VCCIO - 0.43
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
-0.5
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
SSTL18 class I
HSTL15 class I
HSTL15 class III
HSTL18 class I
HSTL18 class II
HSTL18 class III
V
V
REF - 0.2
REF - 0.2
-8
0.5
16
-16
VREF - 0.18 VREF + 0.18
REF - 0.18 VREF + 0.18
REF - 0.125 VREF + 0.125
0.54
0.35
0.4
7.6
15.2
6.7
8
-7.6
V
-15.2
-6.7
V
VREF - 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
0.4
-8
V
REF - 0.1
REF - 0.1
0.4
24
-8
V
0.4
9.6
16
-9.6
VREF - 0.1
REF - 0.1
0.4
-16
V
0.4
24
-8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
3-8
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
sysIO Differential Electrical Characteristics
LVDS
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
Input Voltage
Test Conditions
Min.
0
Typ.
—
Max.
2.4
Units
V
VINP, VINM
VTHD
Differential Input Threshold
Input Common Mode Voltage
Input current
+/-100
VTHD/2
VTHD/2
VTHD/2
—
—
—
mV
V
100mV VTHD
1.2
1.2
1.2
—
1.8
VCM
200mV VTHD
1.9
V
350mV VTHD
2.0
V
IIN
Power on or power off
+/-10
1.60
—
µA
V
VOH
VOL
VOD
Output high voltage for VOP or VOM RT = 100 ohms
Output low voltage for VOP or VOM RT = 100 ohms
—
1.38
1.03
350
0.9V
250
V
Output voltage differential
(VOP - VOM), RT = 100 ohms
450
mV
Change in VOD between high and
low
VOD
—
—
50
mV
VOS
Output voltage offset
(VOP - VOM)/2, RT = 100 ohms
1.125
—
1.25
—
1.375
50
V
VOS
Change in VOS between H and L
mV
VOD = 0V Driver outputs
shorted
IOSD
Output short circuit current
—
—
6
mA
3-9
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
LVDS25E
The top and bottom side of LatticeXP devices support LVDS outputs via emulated complementary LVCMOS out-
puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi-
ble solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Bourns
CAT16-LV4F12
VCCIO = 2.5V ( 5ꢀ%
RS=165 ohms
( 1ꢀ%
+
-
RD = 140 ohms
( 1ꢀ%
RD = 100 ohms
( 1ꢀ%
VCCIO = 2.5V ( 5ꢀ%
RS=165 ohms
( 1ꢀ%
Transmission line, Zo = 100 ohm differential
ON-chip
OFF-chip
OFF-chip ON-chip
Table 3-1. LVDS25E DC Conditions
Over Recommended Operating Conditions
Parameter
Description
Output high voltage
Output low voltage
Typical
1.43
1.07
0.35
1.25
100
Units
VOH
VOL
V
V
VOD
VCM
ZBACK
IDC
Output differential voltage
Output common mode voltage
Back impedance
V
V
ohms
mA
DC output current
3.66
BLVDS
The LatticeXP devices support BLVDS standard. This standard is emulated using complementary LVCMOS out-
puts in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-
drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible
solution for bi-directional multi-point differential signals.
3-10
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
2.5V
100
100
45-90 ohms, +/- 1%
45-90 ohms, +/- 1%
100
100
2.5V
. . .
+
-
+
-
2.5V
100
2.5V
100
2.5V
100
2.5V
100
Table 3-2. BLVDS DC Conditions1
Over Recommended Operating Conditions
Typical
Symbol
Description
Zo = 45 Zo = 90
Units
ohms
ohms
ohms
V
ZOUT
RTLEFT
RTRIGHT
VOH
Output impedance
100
45
100
90
Left end termination
Right end termination
Output high voltage
45
90
1.375
1.125
0.25
1.25
11.2
1.48
1.02
0.46
1.25
10.2
VOL
Output low voltage
V
VOD
Output differential voltage
Output common mode voltage
DC output current
V
VCM
V
IDC
mA
1. For input buffer, see LVDS table.
3-11
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LVPECL
The LatticeXP devices support differential LVPECL standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-
to-point signals.
Figure 3-3. Differential LVPECL
3.3V
RS = 100 ohms
+
= 187 ohms
= 100 ohms
RT
RP
3.3V
-
= 100 ohms
RS
Transmission line, Zo = 100 ohm differential
Off-chip
Table 3-3. LVPECL DC Conditions1
Over Recommended Operating Conditions
Symbol
ZOUT
Description
Output impedance
Typical
100
Units
ohms
ohms
ohms
ohms
V
RP
Driver parallel resistor
Driver series resistor
Receiver termination
Output high voltage
Output low voltage
187
RS
100
RT
100
VOH
VOL
VOD
VCM
ZBACK
IDC
2.03
1.27
0.76
1.65
85.7
12.7
V
Output differential voltage
Output common mode voltage
Back impedance
V
V
ohms
mA
DC output current
1. For input buffer, see LVDS table.
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-
cal documentation at the end of the data sheet.
RSDS
The LatticeXP devices support differential RSDS standard. This standard is emulated using complementary LVC-
MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in
Figure 3-4 are industry standard values for 1% resistors.
3-12
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Figure 3-4. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V
RS
Zo = 100
+
VCCIO = 2.5V
RP
RT
-
RS
On-chip
Off-chip
Emulated
RSDS Buffer
Table 3-4. RSDS DC Conditions
Parameter
ZOUT
Description
Output impedance
Typical
20
Units
ohms
ohms
ohms
ohms
V
RS
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
300
RP
121
RT
100
VOH
VOL
VOD
VCM
ZBACK
IDC
1.35
1.15
0.20
1.25
101.5
3.66
V
Output differential voltage
V
Output common mode voltage
Back impedance
V
ohms
mA
DC output current
3-13
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Typical Building Block Function Performance1
Pin-to-Pin Performance (LVCMOS25 12 mA Drive)
Function
Basic Functions
-5 Timing
Units
16-bit decoder
32-bit decoder
64-bit decoder
4:1 MUX
6.1
7.3
8.2
4.9
5.3
5.7
6.3
ns
ns
ns
ns
ns
ns
ns
8:1 MUX
16:1 MUX
32:1 MUX
Register to Register Performance
Function
Basic Functions
16-bit decoder
-5 Timing
Units
351
248
237
590
523
434
355
343
292
130
388
295
200
164
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
32-bit decoder
64-bit decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
8-bit adder
16-bit adder
64-bit adder
16-bit counter
32-bit counter
64-bit counter
64-bit accumulator
Embedded Memory Functions
Single Port RAM 256x36 bits
True-Dual Port RAM 512x18 bits
Distributed Memory Functions
16x2 SP RAM
254
254
MHz
MHz
434
332
235
322
291
MHz
MHz
MHz
MHz
MHz
64x2 SP RAM
128x4 SP RAM
32x2 PDP RAM
64x4 PDP RAM
1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
Timing v.F0.11
3-14
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Derating Logic Timing
Logic timing provided in the following sections of this data sheet and in the ispLEVER design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process can be
much better than the values given in the tables. The ispLEVER design tool from Lattice can provide logic timing
numbers at a particular temperature and voltage.
3-15
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP External Switching Characteristics
Over Recommended Operating Conditions
-5
Min. Max. Min. Max. Min. Max. Units
-4
-3
Parameter
Description
Device
General I/O Pin Parameters (Using Primary Clock without PLL)1
LFXP3
LFXP6
—
5.12
5.30
5.52
5.72
5.97
—
—
6.12
6.34
6.60
6.84
7.14
—
—
7.43
7.69
8.00
8.29
8.65
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
tCO
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
LFXP10
LFXP15
LFXP20
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
All
—
—
—
—
—
—
—
—
—
-0.40
-0.33
-0.61
-0.71
-0.95
2.10
2.28
3.02
2.70
2.95
2.38
2.92
2.72
2.99
4.47
-0.70
-0.47
-0.60
-1.05
-0.80
—
-0.28
-0.32
-0.71
-0.77
-1.14
2.50
2.72
3.51
3.22
3.52
2.49
3.18
2.75
3.13
4.56
-0.80
-0.38
-0.47
-0.98
-0.58
—
-0.16
-0.30
-0.81
-0.87
-1.35
2.98
3.24
3.71
3.85
4.21
2.66
3.42
2.84
3.18
4.80
-0.92
-0.31
-0.32
-1.01
-0.31
—
—
—
—
tSU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Clock to Data Setup - PIO Input Register
with Input Data Delay
tSU_DEL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Clock to Data Hold - PIO Input Register with
Input Data Delay
tH_DEL
—
—
—
—
—
—
—
—
—
fMAX_IO
Clock Frequency of I/O and PFU Register
400
360
320 MHz
DDR I/O Pin Parameters2
tDVADQ
tDVEDQ
tDQVBS
tDQVAS
Data Valid After DQS (DDR Read)
All
All
All
All
All
—
0.19
—
—
0.19
—
—
0.19
—
UI
UI
UI
UI
Data Hold After DQS (DDR Read)
Data Valid Before DQS
0.67
0.20
0.20
95
0.67
0.20
0.20
95
0.67
0.20
0.20
95
—
—
—
Data Valid After DQS
—
—
—
fMAX_DDR DDR Clock Frequency
166
133
100 MHz
Primary and Secondary Clocks
fMAX_PRI
tW_PRI
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock
All
—
1.19
—
450
—
—
1.19
—
412
—
—
1.19
—
375 MHz
All
—
ns
ps
ps
LFXP3/6/10/15
LFXP20
250
300
300
350
350
400
tSKEW_PRI Primary Clock Skew within an I/O Bank
—
—
—
1. General timing numbers based on LVCMOS 2.5, 12mA.
2. DDR timing numbers based on SSTL I/O.
Timing v.F0.11
3-16
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Figure 3-5. DDR Timings
DQ and DQS Read Timings
DQS
DQ
tDVADQ
tDVEDQ
DQ and DQS Write Timings
DQS
DQ
tDQVBS
tDQVAS
3-17
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP Internal Timing Parameters1
Over Recommended Operating Conditions
-5
Description Min. Max. Min. Max. Min. Max. Units
-4
-3
Parameter
PFU/PFF Logic Mode Timing
tLUT4_PFU
tLUT6_PFU
tLSR_PFU
tSUM_PFU
tHM_PFU
LUT4 Delay (A to D Inputs to F Output)
LUT6 Delay (A to D Inputs to OFX Output)
Set/Reset to Output of PFU
—
—
0.28
0.44
0.90
—
—
—
0.34
0.53
1.08
—
—
—
0.40
0.63
1.29
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D Input Setup Time
0.13
-0.04
0.13
-0.03
—
0.15
-0.03
0.16
-0.02
—
0.19
-0.03
0.19
-0.02
—
—
—
—
tSUD_PFU
tHD_PFU
—
—
—
Clock to D Input Hold Time
—
—
—
tCK2Q_PFU
tLE2Q_PFU
tLD2Q_PFU
Clock to Q Delay, D-type Register Configuration
Clock to Q Delay Latch Configuration
D to Q Throughput Delay when Latch is Enabled
0.40
0.53
0.55
0.48
0.64
0.66
0.58
0.76
0.79
—
—
—
—
—
—
PFU Dual Port Memory Mode Timing
tCORAM_PFU
tSUDATA_PFU
tHDATA_PFU
Clock to Output
—
0.40
—
—
0.48
—
—
0.58
—
ns
ns
ns
ns
ns
ns
ns
Data Setup Time
-0.18
0.28
-0.46
0.71
-0.22
0.33
-0.14
0.34
-0.37
0.85
-0.17
0.40
-0.11
0.40
-0.30
1.02
-0.14
0.48
Data Hold Time
—
—
—
tSUADDR_PFU
tHADDR_PFU
tSUWREN_PFU
tHWREN_PFU
PIC Timing
Address Setup Time
Address Hold Time
—
—
—
—
—
—
Write/Read Enable Setup Time
Write/Read Enable Hold Time
—
—
—
—
—
—
PIO Input/Output Buffer Timing
tIN_PIO
Input Buffer Delay
Output Buffer Delay
—
—
0.62
2.12
—
—
0.72
2.54
—
—
0.85
3.05
ns
ns
tOUT_PIO
IOLOGIC Input/Output Timing
tSUI_PIO
Input Register Setup Time (Data Before Clock)
1.35
0.05
—
—
—
1.83
0.05
—
—
—
2.37
0.05
—
—
—
ns
ns
ns
ns
ns
ns
ns
tHI_PIO
Input Register Hold Time (Data After Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
tCOO_PIO
0.36
—
0.44
—
0.52
—
tSUCE_PIO
tHCE_PIO
-0.09
0.13
0.19
-0.14
-0.07
0.16
0.23
-0.11
-0.06
0.19
0.28
-0.09
—
—
—
tSULSR_PIO
tHLSR_PIO
EBR Timing
tCO_EBR
—
—
—
Set/Reset Hold Time
—
—
—
Clock to Output from Address or Data
Clock to Output from EBR Output Register
Setup Data to EBR Memory
—
4.01
0.81
—
—
4.81
0.97
—
—
5.78
1.17
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOO_EBR
tSUDATA_EBR
tHDATA_EBR
tSUADDR_EBR
tHADDR_EBR
tSUWREN_EBR
tHWREN_EBR
tSUCE_EBR
tHCE_EBR
—
—
—
-0.26
0.41
-0.26
0.41
-0.17
0.26
-0.21
0.49
-0.21
0.49
-0.13
0.31
0.23
-0.10
-0.17
0.59
-0.17
0.59
-0.11
0.37
0.28
-0.08
Hold Data to EBR Memory
—
—
—
Setup Address to EBR Memory
—
—
—
Hold Address to EBR Memory
—
—
—
Setup Write/Read Enable to EBR Memory
Hold Write/Read Enable to EBR Memory
—
—
—
—
—
—
Clock Enable Setup Time to EBR Output Register 0.19
—
—
—
Clock Enable Hold Time to EBR Output Register
-0.13
—
—
—
3-18
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
tRSTO_EBR
Description
Min. Max. Min. Max. Min. Max. Units
Reset To Output Delay Time from EBR Output
Register
—
1.61
—
1.94
—
2.32
ns
PLL Parameters
tRSTREC
Reset Recovery to Rising Clock
Reset Signal Setup Time
1.00
1.00
—
—
1.00
1.00
—
—
1.00
1.00
—
—
ns
ns
tRSTSU
1. Internal parameters are characterized but not tested on every device.
Timing v.F0.11
3-19
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Timing Diagrams
PFU Timing Diagrams
Figure 3-6. Slice Single/Dual Port Write Cycle Timing
CK
WRE
AD
AD[3:0]
D
DI[1:0]
DO[1:0]
Old Data
D
Figure 3-7. Slice Single /Dual Port Read Cycle Timing
WRE
AD
AD[3:0]
DO[1:0]
Old Data
D
3-20
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
EBR Memory Timing Diagrams
Figure 3-8. Read Mode (Normal)
CLKA
CSA
WEA
ADA
DIA
A0
A1
D1
A0
A1
A0
tSU tH
D0
tACCESS
tACCESS
D0
D0
D1
DOA
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
Figure 3-9. Read Mode with Input and Output Registers
CLKA
CSA
WEA
ADA
A1
A0
A1
D1
A0
A0
t
t
H
SU
DIA
D0
D1
DOA
D0
Mem(n) data from previous read
D0
DOA
t
t
ACCESS
ACCESS
DOA
(Registered)
D1
D0
Mem(n) data from previous read
output is only updated during a read cycle
3-21
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only)
CLKA
CSA
WEA
ADA
A0
A1
D1
A0
A1
A0
t
t
H
SU
D2
D3
D1
D0
DIA
t
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
ACCESS
old A0 Data
old A1 Data
D0
D1
DOA
D2
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only)
CLKA
CSA
WEA
Three consecutive writes to A0
ADA
A0
A1
D1
A0
t
t
H
SU
D2
D3
D2
D4
D0
DIA
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
Data from Prev Read
or Write
D0
D1
D3
DOA
D4
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
3-22
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP Family Timing Adders1
Over Recommended Operating Conditions
Buffer Type
Input Adjusters
LVDS25E
Description
-5
-4
-3
Units
LVDS 2.5 Emulated
LVDS
0.5
0.4
0.5
0.6
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.6
0.6
0.5
0.5
0.5
0.5
0.5
0.5
0.2
0.2
0.0
0.1
0.1
0.1
0.2
0.5
0.4
0.5
0.6
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.6
0.6
0.5
0.5
0.5
0.5
0.5
0.5
0.2
0.2
0.0
0.1
0.1
0.1
0.2
0.5
0.4
0.5
0.6
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.6
0.6
0.5
0.5
0.5
0.5
0.5
0.5
0.2
0.2
0.0
0.1
0.1
0.1
0.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS25
BLVDS25
BLVDS
LVPECL33
HSTL18_I
LVPECL
HSTL_18 class I
HSTL_18 class II
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
HSTL_15 class I
HSTL_15 class III
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL15_I
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I
SSTL33_II
SSTL33D_I
SSTL33D_II
SSTL25_I
SSTL_3 class II
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL_2 class II
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_18 class I
Differential SSTL_18 class I
LVTTL
SSTL18D_I
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
PCI
Output Adjusters
LVDS25E
LVDS 2.5 Emulated
LVDS 2.5
0.3
0.3
0.3
0.1
0.1
0.1
0.2
0.1
-0.1
0.2
0.3
0.3
0.3
0.1
0.1
0.1
0.2
0.1
-0.1
0.2
0.3
0.3
0.3
0.1
0.1
0.1
0.2
0.1
-0.1
0.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS25
BLVDS25
BLVDS 2.5
LVPECL33
HSTL18_I
LVPECL 3.3
HSTL_18 class I
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL_18 class II
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
3-23
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP Family Timing Adders1 (Continued)
Over Recommended Operating Conditions
Description -5 -4
HSTL_15 class I 0.2 0.2
Buffer Type
HSTL15_I
-3
0.2
0.2
0.2
0.2
0.1
0.3
0.1
0.3
-0.1
0.3
-0.1
0.3
0.1
0.1
0.8
0.5
0.3
0.4
0.3
0.8
0.8
0.5
0.3
0.4
0.3
0.7
0.7
0.4
0.0
0.2
0.4
0.6
0.6
0.4
0.2
0.2
0.6
0.6
0.2
0.4
0.4
0.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I
HSTL_15 class III
0.2
0.2
0.2
0.1
0.3
0.1
0.3
-0.1
0.3
-0.1
0.3
0.1
0.1
0.8
0.5
0.3
0.4
0.3
0.8
0.8
0.5
0.3
0.4
0.3
0.7
0.7
0.4
0.0
0.2
0.4
0.6
0.6
0.4
0.2
0.2
0.6
0.6
0.2
0.4
0.4
0.3
0.2
0.2
0.2
0.1
0.3
0.1
0.3
-0.1
0.3
-0.1
0.3
0.1
0.1
0.8
0.5
0.3
0.4
0.3
0.8
0.8
0.5
0.3
0.4
0.3
0.7
0.7
0.4
0.0
0.2
0.4
0.6
0.6
0.4
0.2
0.2
0.6
0.6
0.2
0.4
0.4
0.3
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
SSTL33_II
SSTL_3 class II
SSTL33D_I
SSTL33D_II
SSTL25_I
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL25_II
SSTL_2 class II
SSTL25D_I
SSTL25D_II
SSTL18_I
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_1.8 class I
SSTL18D_I
LVTTL33_4mA
LVTTL33_8mA
LVTTL33_12mA
LVTTL33_16mA
LVTTL33_20mA
Differential SSTL_1.8 class I
LVTTL 4mA drive
LVTTL 8mA drive
LVTTL 12mA drive
LVTTL 16mA drive
LVTTL 20mA drive
LVCMOS33_2mA LVCMOS 3.3 2mA drive
LVCMOS33_4mA LVCMOS 3.3 4mA drive
LVCMOS33_8mA LVCMOS 3.3 8mA drive
LVCMOS33_12mA LVCMOS 3.3 12mA drive
LVCMOS33_16mA LVCMOS 3.3 16mA drive
LVCMOS33_20mA LVCMOS 3.3 20mA drive
LVCMOS25_2mA LVCMOS 2.5 2mA drive
LVCMOS25_4mA LVCMOS 2.5 4mA drive
LVCMOS25_8mA LVCMOS 2.5 8mA drive
LVCMOS25_12mA LVCMOS 2.5 12mA drive
LVCMOS25_16mA LVCMOS 2.5 16mA drive
LVCMOS25_20mA LVCMOS 2.5 20mA drive
LVCMOS18_2mA LVCMOS 1.8 2mA drive
LVCMOS18_4mA LVCMOS 1.8 4mA drive
LVCMOS18_8mA LVCMOS 1.8 8mA drive
LVCMOS18_12mA LVCMOS 1.8 12mA drive
LVCMOS18_16mA LVCMOS 1.8 16mA drive
LVCMOS15_2mA LVCMOS 1.5 2mA drive
LVCMOS15_4mA LVCMOS 1.5 4mA drive
LVCMOS15_8mA LVCMOS 1.5 8mA drive
LVCMOS12_2mA LVCMOS 1.2 2mA drive
LVCMOS12_6mA LVCMOS 1.2 6mA drive
PCI33
PCI33
1. General timing numbers based on LVCMOS 2.5, 12mA.
Timing v.F0.11
3-24
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
fIN
Descriptions
Conditions
Min.
25
Typ.
—
Max.
375
375
187.5
750
—
Units
MHz
MHz
MHz
MHz
MHz
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
fOUT
fOUT2
fVCO
fPFD
25
—
0.195
375
25
—
—
Phase Detector Input Frequency
—
AC Characteristics
tDT Output Clock Duty Cycle
Default duty cycle elected3
fOUT Š 100MHz
45
—
50
—
—
—
—
—
—
250
—
—
—
—
—
55
0.05
+/- 125
0.02
+/- 200
—
%
UI
4
tPH
Output Phase Accuracy
—
ps
1
tOPJIT
Output Clock Period Jitter
f
OUT < 100MHz
—
UIPP
ps
tSK
tW
tLOCK
tPA
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Divider ratio = integer
At 90% or 10%3
—
1
ns
2
—
150
400
+/- 200
10
us
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
100
—
ps
tIPJIT
ps
tFBKDLY
tHI
—
ns
90% to 90%
10% to 10%
0.5
0.5
10
—
ns
tLO
—
ns
tRST
—
ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. As compared to CLKOP output.
Timing v.F0.11
LatticeXP “C” Sleep Mode Timing
Parameter
tPWRDN
Descriptions
SLEEPN Low to I/O Tristate
Min.
—
Typ.
Max.
Units
20
1.4
1.7
1.1
1.4
1.7
—
32
2.1
2.4
1.8
2.1
2.4
—
ns
ms
ms
ms
ms
ms
ns
LFXP3
—
LFXP6
—
tPWRUP
SLEEPN High to Power Up
LFXP10
LFXP15
LFXP20
—
—
—
tWSLEEPN
tWAWAKE
SLEEPN Pulse Width to Initiate Sleep Mode
SLEEPN Pulse Rejection
400
—
—
120
ns
Sleep Mode
I/O
tPWRUP
tPWRDN
SLEEPN
3-25
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
LatticeXP sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min.
Max.
Units
sysCONFIG Byte Data Flow
tSUCBDI
tHCBDI
tCODO
tSUCS
tHCS
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
7
3
—
—
12
—
—
—
—
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
—
7
2
tSUWD
tHWD
7
2
tDCB
—
—
tCORD
Clock to Out for Read Data
sysCONFIG Byte Slave Clocking
tBSCH Byte Slave Clock Minimum High Pulse
tBSCL
6
8
—
—
—
ns
ns
ns
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
tBSCYC
15
sysCONFIG Serial (Bit) Data Flow
tSUSCDI
tHSCDI
tCODO
DI (Data In) Setup Time to CCLK
7
2
—
—
12
ns
ns
ns
DI (Data In) Hold Time to CCLK
Clock to Dout in Flowthrough Mode
—
sysCONFIG Serial Slave Clocking
tSSCH Serial Slave Clock Minimum High Pulse
tSSCL Serial Slave Clock Minimum Low Pulse
sysCONFIG POR, Initialization and Wake Up
6
6
—
—
ns
ns
tICFG
Minimum Vcc to INIT High
—
—
50
2
ms
us
tVMC
Time from tICFG to Valid Master Clock
tPRGMRJ
Program Pin Pulse Rejection
—
7
ns
2
tPRGM
PROGRAMN Low Time to Start Configuration
INIT Low Time
25
—
—
1
ns
tDINIT
ms
ns
tDPPINIT
tDINITD
tIODISS
tIOENSS
tMWC
Delay Time from PROGRAMN Low to INIT Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after Done Pin High
—
37
37
25
25
—
—
ns
—
ns
—
ns
120
cycles
Configuration Master Clock (CCLK)
Selected Selected
Frequency1
Value -
30%
Value +
30%
MHz
%
Duty Cycle
40
60
1. See Table 2-10 for available CCLK frequencies.
2. The threshold level for PROGRAMN, as well as for CFG[1] and CFG[0], is determined by VCC, such that the threshold = VCC/2.
Timing v.F0.11
3-26
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Flash Download Time
Symbol
Parameter
LFXP3
LFXP6
Min.
—
Typ.
1.1
1.4
0.9
1.1
1.3
Max.
1.7
2.0
1.5
Units
ms
—
ms
PROGRAMN Low-to-
tREFRESH
High. Transition to Done LFXP10
—
ms
High.
LFXP15
—
1.7
ms
LFXP20
—
1.9
ms
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
fMAX
Parameter
Min.
—
40
20
20
10
8
Max.
Units
MHz
ns
25
—
—
—
—
—
—
10
10
10
—
—
25
25
25
tBTCP
TCK [BSCAN] clock pulse width
tBTCPH
tBTCPL
TCK [BSCAN] clock pulse width high
ns
TCK [BSCAN] clock pulse width low
ns
tBTS
TCK [BSCAN] setup time
ns
tBTH
TCK [BSCAN] hold time
ns
tBTRF
TCK [BSCAN] rise/fall time
50
—
—
—
8
ns
tBTCO
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
ns
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
tBUTCO
tBTUODIS
tBTUPOEN
Timing v.F0.11
ns
ns
ns
BSCAN test capture register hold time
25
—
—
—
ns
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
ns
ns
ns
Figure 3-12. JTAG Port Timing Waveforms
TMS
TDI
t
t
BTH
BTS
t
t
BTCP
t
BTCPL
BTCPH
TCK
t
t
BTCODIS
t
BTCO
BTCOEN
TDO
Valid Data
Valid Data
t
BTCRH
t
BTCRS
Data to be
captured
from I/O
Data Captured
t
t
t
BTUPOEN
BUTCO
BTUODIS
Data to be
driven out
to I/O
Valid Data
Valid Data
3-27
DC and Switching Characteristics
LatticeXP Family Data Sheet
Lattice Semiconductor
Switching Test Conditions
Figure 3-13 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Figure 3-5.
Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Point
CL
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R1
CL
Timing Ref.
LVCMOS 3.3 = 1.5V
VT
—
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
LVCMOS 1.2 = VCCIO/2
—
LVTTL and other LVCMOS settings (L -> H, H -> L)
0pF
—
—
—
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
V
CCIO/2
VOL
VOH
VOL
VOH
VCCIO/2
188
0pF
VOH - 0.15
VOL + 0.15
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-28
LatticeXP Family Data Sheet
Pinout Information
Data Sheet DS1001
November 2007
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
P[Edge] [Row/Column Number*]_[A/B]
I/O
Some of these user programmable pins are shared with special function pins.
These pin when not used as special purpose pins can be programmed as I/
Os for user logic.
During configuration, the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
Global RESET signal. (Active low). Any I/O pin can be configured to be
GSRN.
GSRN
I
NC
—
—
—
No connect.
GND
VCC
GND - Ground. Dedicated Pins.
VCC - The power supply pins for core logic. Dedicated Pins.
VCCAUX - The Auxiliary power supply pin. It powers all the differential and ref-
erenced input buffers. Dedicated Pins.
VCCAUX
—
VCCP0
—
—
—
—
—
Voltage supply pins for ULM0PLL (and LLM1PLL1).
Voltage supply pins for URM0PLL (and LRM1PLL1).
Ground pins for ULM0PLL (and LLM1PLL1).
VCCP1
GNDP0
GNDP1
VCCIOx
Ground pins for URM0PLL (and LRM1PLL1).
VCCIO - The power supply pins for I/O bank x. Dedicated Pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
VREF1(x), VREF2(x)
—
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
[LOC]DQS[num]
—
—
—
—
Optional feedback (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
Primary Clock Pads, T = true and C = complement, n per side, indexed by
bank and 0,1, 2, 3 within bank.
DQS input Pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = Ball
function number. Any pad can be configured to be DQS output.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
DS1001 Pinouts_02.5
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Signal Descriptions (Cont.)
Signal Name
I/O
Descriptions
Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.)
TMS
TCK
I
I
Test Mode Select input, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data in pin, used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence).
TDI
I
TDO
VCCJ
O
Output pin -Test Data out pin used to shift data out of device using 1149.1.
VCCJ - The power supply pin for JTAG Test Access Port.
—
Configuration Pads (used during sysCONFIG)
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled.
CFG[1:0]
I
Open Drain pin - Indicates the FPGA is ready to be configured. During con-
I/O figuration, a pull-up is enabled. If CFG1 and CFG0 are high (SDM) then this
pin is pulled low.
INITN
Initiates configuration sequence when asserted low. This pin always has an
active pull-up.
PROGRAMN
DONE
I
Open Drain pin - Indicates that the configuration sequence is complete, and
the startup sequence is in progress.
I/O
CCLK
BUSY
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Generally not used. After configuration it is a user-programmable I/O pin.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled. After configuration it is user a programmable I/O pin.
CSN
I
sysCONFIG chip select (Active Low). During configuration, a pull-up is
enabled. After configuration it is user programmable I/O pin
CS1N
I
Write Data on Parallel port (Active low). After configuration it is a user pro-
grammable I/O pin
WRITEN
D[7:0]
I
sysCONFIG Port Data I/O. After configuration these are user programmable
I/O pins.
I/O
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port. After configuration, it is a user-programmable I/O pin.
DOUT, CSON
O
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. After configuration it is a
user-programmable I/O pin.
DI
I
I
I
Sleep Mode pin - Active low sleep pin.þ When this pin is held high, the device
operates normally.þ When driven low, the device moves into Sleep Mode
after a specified time.This pin has a weak internal pull-up, but when not used
an external pull-up to VCC is recommended.
SLEEPN2
TOE3
Test Output Enable tri-states all I/O pins when driven low. This pin has a
weak internal pull-up, but when not used an external pull-up to VCC is recom-
mended.
1. Applies toþ LFXP10, LFXP15 and LFXP20 only.
2. Applies to LFXP “C” devices only.
3. Applies to LFXP “E” devices only.
4-2
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
DDR Strobe (DQS)
and Data (DQ) Pins
PIO within PIC
Polarity
True
A
B
A
B
A
B
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
P[Edge] [n-4]
Complement
True
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
Complement
True
Complement
True
B
A
B
A
B
A
B
Complement
True
DQ
[Edge]DQSn
DQ
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Complement
True
DQ
Complement
True
DQ
DQ
Complement
DQ
Notes:
1. “n” is a row/column PIC number.
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR
data (DQ) pins may not be available.
3. The definition of the PIC numbering is provided in the Signal Names column of the Signal Descriptions table in this data sheet.
4-3
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Pin Information Summary1
XP3
XP6
Pin Type
Single Ended User I/O
Differential Pair User I/O2
100 TQFP 144 TQFP 208 PQFP 144 TQFP 208 PQFP 256 fpBGA
62
19
11
14
5
100
35
11
14
5
136
56
11
14
5
100
35
11
14
5
142
58
11
14
5
188
80
Dedicated
11
Configuration
Muxed
14
TAP
5
Dedicated (total without supplies)
6
6
6
6
6
6
VCC
2
4
8
4
8
8
VCCAUX
VCCPLL
Bank0
Bank1
Bank2
2
2
2
2
2
4
2
2
2
2
2
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
2
1
2
2
Bank3
1
1
2
1
2
2
VCCIO
Bank4
1
2
2
2
2
2
Bank5
1
1
2
1
2
2
Bank6
1
1
2
1
2
2
Bank7
1
1
2
1
2
2
GND
10
2
13
2
24
2
13
2
24
2
24
GNDPLL
NC
2
0
0
6
0
0
0
Bank0
Bank1
Bank2
8/2
9/0
8/3
6/2
5/2
12/4
4/2
10/4
1
12/3
12/2
12/5
13/5
14/6
12/4
13/5
12/5
1
20/8
18/6
14/6
14/6
21/9
21/9
14/6
14/6
1
12/3
12/2
12/5
13/5
14/6
12/4
13/5
12/5
1
20/8
18/6
17/7
14/6
21/9
21/9
17/7
14/6
1
26/11
26/11
21/9
21/9
26/11
26/11
21/9
21/9
1
Bank3
Bank4
Bank5
Bank6
Bank7
SingleEnded/Differential
I/O per Bank2
VCCJ
1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table
for more information.
4-4
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Pin Information Summary1 (Cont.)
XP10
XP15
XP20
Pin Type
256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA
Single Ended User I/O
Differential Pair User I/O2
188
76
11
14
5
244
104
11
188
76
11
14
5
268
112
11
300
128
11
188
76
11
14
5
268
112
11
340
144
11
Dedicated
Configuration
Muxed
14
14
14
14
14
TAP
5
5
5
5
5
Dedicated
(total without supplies)
6
6
6
6
6
6
6
6
VCC
8
14
8
14
28
12
8
14
28
VCCAUX
VCCPLL
Bank0
Bank1
Bank2
4
2
4
4
2
4
4
2
4
12
2
5
2
2
2
2
2
2
5
4
2
5
4
2
5
2
5
4
4
2
5
4
4
4
2
4
2
4
2
Bank3
VCCIO
2
4
2
4
4
2
4
4
Bank4
2
5
2
5
4
2
5
4
Bank5
2
5
2
5
4
2
5
4
Bank6
2
4
2
4
4
2
4
4
Bank7
2
4
2
4
4
2
4
4
GND
24
50
24
50
56
24
50
56
GNDPLL
NC
2
2
2
2
2
2
2
2
0
24
0
0
40
0
0
0
Bank0
Bank1
Bank2
26/11
26/11
21/8
21/8
26/11
26/11
21/8
21/8
1
33/14
33/14
28/12
28/12
33/14
33/14
28/12
28/12
1
26/11
26/11
21/8
21/8
26/11
26/11
21/8
21/8
1
39/16
39/16
28/12
28/12
39/16
39/16
28/12
28/12
1
40/17
40/17
35/15
35/15
40/17
40/17
35/15
35/15
1
26/11
26/11
21/8
21/8
26/11
26/11
21/8
21/8
1
39/16
39/16
28/12
28/12
39/16
39/16
28/12
28/12
1
47/20
47/20
38/16
38/16
47/20
47/20
38/16
38/16
1
Single Ended/
Differential I/O
Bank3
per Bank2
Bank4
Bank5
Bank6
Bank7
VCCJ
1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for
more information.
4-5
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Power Supply and NC Connections
Signals
100 TQFP
28, 77
144 TQFP
208 PQFP
256 fpBGA
388 fpBGA
484 fpBGA
V
14, 39, 73, 112
19, 35, 53, 80, 107, D4, D13, E5, E12, H9, J8, J15, K8,
F10, F13, G9, G10,
CC
151, 158, 182
M5, M12, N4, N13 K15, L8, L15, M8, G13, G14, H8,
M15, N8, N15, P8, H15, J7, J16, K6,
P15, R9
K7, K16, K17, N6,
N7, N16, N17, P7,
P16, R8, R15, T9,
T10, T13, T14,
U10, U13
V
V
94
82
133
119
189, 199
167, 177
F7, F8
G8, G9, G10, G11, F11, G11, H10,
CCIO0
CCIO1
H8
H11
F9, F10
G12, G13, G14,
G15, H15
F12, G12, H12,
H13
V
V
65
58
98
88
140, 149
115, 125
G11, H11
J11, K11
H16, J16, K16, L16 K15, L15, L16, L17
CCIO2
CCIO3
M16, N16, P16,
R16
M15, M16, M17,
N15
V
V
47
38
61, 68
49
87, 97
64, 74
L9, L10
L7, L8
R15, T12, T13,
T14, T15
R12, R13, T12,
U12
CCIO4
CCIO5
R8, T8, T9, T10,
T11
R10, R11, T11,
U11
V
V
V
V
V
V
22
21
28, 41
13, 23
154
J6, K6
G6, H6
D16
M7, N7, P7, R7
M6, M7, M8, N8
CCIO6
CCIO7
CCJ
7
8
H7, J7, K7, L7
K8, L6, L7, L8
73
108
19
E20
M2
E20
L5
17
25
H4
CCP0
CCP1
CCAUX
60
91
128
J12
M21
L18
25, 71
36, 106
50, 152
E4, E13, M4, M13 G7, G16, T7, T16 G7, G8, G15, G16,
H7, H16, R7, R16,
T7, T8, T15, T16
GND1
10, 18, 21, 33, 43, 3, 11, 20, 28, 44,
44, 52, 59, 68, 84, 54, 56, 64, 75, 85, 49, 59, 69, 79, 82, G7, G8, G9, G10, H12, H13, H14, J9, B1, B22, H9, H14,
5, 7, 16, 26, 38, 47, A1, A16, F6, F11, A1, A22, H10, H11, A1, A2, A21, A22,
90, 99
90, 101, 121, 127, 92, 106, 109, 118, H5, H7, H8, H9,
J10, J11, J12, J13, J8, J9, J10, J11,
J14, K9, K10, K11, J12, J13, J14, J15,
K12, K13, K14, L9, K9, K10, K11, K12,
136
121, 127, 130, 135, H10, J7, J8, J9,
143, 163, 172, 181, J10, J13, K7, K8,
184, 194, 207
K9, K10, L6, L11, L10, L11, L12, L13, K13, K14, L9, L10,
T1, T16
L14, M9, M10,
M11, M12, M13,
L11, L12, L13, L14,
M9, M10, M11,
M14, N1, N9, N10, M12, M13, M14,
N11, N12, N13, M20, N2, N9, N10,
N14, N22, P9, P10, N11, N12, N13,
P11, P12, P13,
P14, R10, R11,
R12, R13, R14,
AB1, AB22
N14, P8, P9, P10,
P11, P12, P13,
P14, P15, R9, R14,
AA1, AA22, AB1,
AB2, AB21, AB22
NC2
—
—
XP3: 27, 33, 34,
129, 133, 134
—
XP10: C2, C15,
XP15: B21, C4, C5,
C16, C17, D4, D5, C6, C18, C19, C20,
D6, D7, D16, D17, C21, D6, D18, E4,
E4, E19, W3, W4, E6, E18, F6, L1,
W7, W17, W18,
W19, W20, Y3,
Y15, Y16, AA1,
AA2
L19, L20, M1, M2,
M19, M21, N1,
N21, N22, P1, P2,
U5, U6, U17, U18,
V5, V6, V17, V18,
W17, W18, W19,
Y3, Y4, Y5
1. All grounds must be electrically connected at the board level.
2. NC pins should not be connected to any active signals, V or GND.
CC
4-6
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 Logic Signal Connections: 100 TQFP
Pin Number
Pin Function
Bank
0
0
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
Differential
Dual Function
1
CFG1
-
-
-
2
DONE
PROGRAMN
CCLK
-
3
-
-
4
-
-
5
PL3A
T
C
-
LUM0_PLLT_FB_A
6
PL3B
LUM0_PLLC_FB_A
7
VCCIO7
PL5A
-
8
-
VREF1_7
9
PL6B
-
VREF2_7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GNDIO7
PL7A
-
-
T3
C3
T
C
T3
C3
-
DQS
PL7B
-
PL8A
LUM0_PLLT_IN_A
PL8B
LUM0_PLLC_IN_A
PL9A
-
PL9B
-
VCCP0
GNDP0
PL12A
PL12B
GNDIO6
VCCIO6
PL18A
PL18B
VCCAUX
SLEEPN1/TOE2
INITN
-
-
-
-
6
6
6
6
6
6
-
T
C
-
PCLKT6_0
PCLKC6_0
-
-
-
T3
C3
-
-
-
-
-
-
-
5
-
-
-
VCC
-
-
PB2B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
VREF1_5
PB5B
-
VREF2_5
PB8A
T
C
-
-
PB8B
-
GNDIO5
PB9A
-
-
-
PB10B
PB11A
PB11B
VCCIO5
PB12A
PB12B
PB13A
PB13B
GND
-
-
T
C
-
DQS
-
-
-
-
-
-
-
T
C
T
C
-
4-7
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 Logic Signal Connections: 100 TQFP (Cont.)
Pin Number
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Pin Function
GNDIO4
PB15A
PB15B
VCCIO4
PB19A
PB19B
PB24A
PR18B
GNDIO3
PR18A
PR15B
PR14A
PR13B
PR13A
VCCIO3
GNDP1
VCCP1
PR9B
Bank
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
-
Differential
Dual Function
-
T
C
-
-
PCLKT4_0
PCLKC4_0
-
T
C
-
DQS
VREF1_4
VREF2_4
C3
-
-
-
T3
-
-
VREF1_3
-
VREF2_3
C
T
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
2
2
-
C
T
C
T
-
PCLKC2_0
PR9A
PCLKT2_0
PR8B
RUM0_PLLC_IN_A
PR8A
RUM0_PLLT_IN_A
VCCIO2
PR6B
-
-
VREF1_2
PR5A
-
VREF2_2
GNDIO2
PR3B
-
-
C
T
-
RUM0_PLLC_FB_A
PR3A
RUM0_PLLT_FB_A
VCCAUX
TDO
-
-
-
-
VCCJ
-
-
-
TDI
-
-
-
TMS
-
-
-
TCK
-
-
-
VCC
-
-
-
PT24A
PT23A
PT22B
PT21A
VCCIO1
PT20B
GNDIO1
PT17A
PT16A
PT15B
1
1
1
1
1
1
1
1
1
1
-
-
-
D0
D1
D2
-
-
-
-
-
D3
-
-
-
D4
D5
D6
-
-
4-8
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 Logic Signal Connections: 100 TQFP (Cont.)
Pin Number
Pin Function
PT14B
PT13B
GNDIO0
PT13A
PT12B
PT12A
VCCIO0
PT9A
Bank
Differential
Dual Function
88
89
90
91
92
93
94
95
96
97
98
99
100
1
0
0
0
0
0
0
0
0
0
0
-
-
C
-
D7
BUSY
-
T
C
T
-
CS1N
PCLKC0_0
PCLKT0_0
-
-
DOUT
PT8A
-
WRITEN
PT6A
-
DI
PT5A
-
CSN
GND
-
-
-
CFG0
0
-
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-9
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PROGRAMN
CCLK
Bank Differential
Dual Function
1
PROGRAMN
CCLK
7
7
-
-
-
-
7
7
-
-
-
-
2
-
-
3
GND
-
-
GND
-
-
4
PL2A
7
7
7
7
7
7
7
7
7
7
-
T3
C3
T
C
-
-
PL2A
7
7
7
7
7
7
7
7
7
7
-
T3
C3
T
C
-
-
5
PL2B
-
PL2B
-
6
PL3A
LUM0_PLLT_FB_A
PL3A
LUM0_PLLT_FB_A
7
PL3B
LUM0_PLLC_FB_A
PL3B
LUM0_PLLC_FB_A
8
VCCIO7
PL5A
-
VCCIO7
PL5A
-
9
-
VREF1_7
-
VREF1_7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PL6B
-
VREF2_7
PL6B
-
VREF2_7
GNDIO7
PL7A
-
-
GNDIO7
PL7A
-
-
T3
C3
-
DQS
T3
C3
-
DQS
PL7B
-
PL7B
-
VCC
-
VCC
-
PL8A
7
7
7
7
-
T
C
T3
C3
-
LUM0_PLLT_IN_A
PL8A
7
7
7
7
-
T
C
T3
C3
-
LUM0_PLLT_IN_A
PL8B
LUM0_PLLC_IN_A
PL8B
LUM0_PLLC_IN_A
PL9A
-
PL9A
-
PL9B
-
PL9B
-
VCCP0
GNDP0
VCCIO6
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
GNDIO6
PL14A
PL15B
PL16A
PL16B
PL17A
PL18A
PL18B
VCCAUX
SLEEPN1/TOE2
INITN
-
VCCP0
GNDP0
VCCIO6
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
GNDIO6
PL22A
PL23B
PL24A
PL24B
PL25A
PL26A
PL26B
VCCAUX
SLEEPN1/TOE2
INITN
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
T3
C3
T
C
T3
C3
-
-
T3
C3
T
C
T3
C3
-
-
-
-
PCLKT6_0
PCLKT6_0
PCLKC6_0
PCLKC6_0
-
-
-
-
-
-
-
VREF1_6
-
VREF1_6
-
VREF2_6
-
VREF2_6
T3
C3
-
T3
C3
-
DQS
T3
C3
-
T3
C3
-
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
5
-
-
-
VCC
-
-
VCC
-
-
PB2B
5
5
5
5
5
5
5
-
VREF1_5
PB5B
5
5
5
5
5
5
5
-
VREF1_5
PB5B
VREF2_5
PB8B
-
VREF2_5
-
PB7A
T
C
-
-
-
-
-
-
PB10A
PB10B
GNDIO5
PB12A
PB13B
T
C
-
-
-
-
-
-
PB7B
GNDIO5
PB9A
-
-
PB10B
-
-
4-10
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PB14A
PB14B
VCCIO5
PB15A
PB15B
PB16A
PB16B
GND
Bank Differential
Dual Function
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
PB11A
PB11B
VCCIO5
PB12A
PB12B
PB13A
PB13B
GND
5
5
5
5
5
5
5
-
T
C
-
DQS
5
5
5
5
5
5
5
-
T
C
-
DQS
-
-
-
-
T
C
T
C
-
-
T
C
T
C
-
-
-
-
-
-
-
-
-
-
PB14A
GNDIO4
PB14B
PB15A
PB15B
PB16A
VCCIO4
PB16B
PB19A
GNDIO4
PB19B
PB20A
PB20B
VCCIO4
PB22A
PB24A
PB24B
PB25A
VCC
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
T
-
-
PB17A
GNDIO4
PB17B
PB18A
PB18B
PB19A
VCCIO4
PB19B
PB22A
GNDIO4
PB22B
PB23A
PB23B
VCCIO4
PB25A
PB27A
PB27B
PB28A
VCC
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
T
-
-
-
-
C
T
C
T
-
-
C
T
C
T
-
-
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
-
-
-
-
C
T
-
-
C
T
-
-
DQS
DQS
-
-
C
T
C
-
VREF1_4
C
T
C
-
VREF1_4
-
-
-
-
-
-
-
-
-
-
T
C
-
VREF2_4
T
C
-
VREF2_4
-
-
-
-
-
C3
-
-
C3
-
PR18B
GNDIO3
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR14A
PR13B
PR13A
GND
3
3
3
3
3
3
3
3
3
3
3
-
-
PR26B
GNDIO3
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR22A
PR21B
PR21A
GND
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
T3
C
T
C3
T3
-
-
T3
C
T
C3
T3
-
-
-
-
-
-
-
-
DQS
DQS
VREF1_3
VREF1_3
-
VREF2_3
-
VREF2_3
C
T
-
-
C3
T3
-
-
-
-
-
-
PR12A
PR11B
VCCIO3
PR11A
GNDP1
VCCP1
PR9B
3
3
3
3
-
-
PR20A
PR19B
VCCIO3
PR19A
GNDP1
VCCP1
PR12B
3
3
3
3
-
-
C3
-
-
C
-
-
-
-
-
-
T
-
-
T3
-
-
-
-
-
-
-
-
-
-
2
C
PCLKC2_0
2
C
PCLKC2_0
4-11
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PR12A
PR8B
Bank Differential
Dual Function
93
PR9A
PR8B
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
C3
T3
-
PCLKT2_0
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
C3
T3
-
PCLKT2_0
94
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
95
PR8A
RUM0_PLLT_IN_A
PR8A
RUM0_PLLT_IN_A
96
PR7B
-
PR7B
-
97
PR7A
DQS
PR7A
DQS
98
VCCIO2
PR6B
-
VCCIO2
PR6B
-
99
-
VREF1_2
-
VREF1_2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
PR5A
-
VREF2_2
PR5A
-
VREF2_2
GNDIO2
PR3B
-
-
GNDIO2
PR3B
-
-
C
T
C3
T3
-
RUM0_PLLC_FB_A
C
T
C3
T3
-
RUM0_PLLC_FB_A
PR3A
RUM0_PLLT_FB_A
PR3A
RUM0_PLLT_FB_A
PR2B
-
PR2B
-
PR2A
-
PR2A
-
VCCAUX
TDO
-
VCCAUX
TDO
-
-
-
-
-
-
-
VCCJ
-
-
-
VCCJ
-
-
-
TDI
-
-
-
TDI
-
-
-
TMS
-
-
-
TMS
-
-
-
TCK
-
-
-
TCK
-
-
-
VCC
-
-
-
VCC
-
-
-
PT25A
PT24A
PT23A
PT22B
PT22A
PT21A
VCCIO1
PT20B
GNDIO1
PT17A
PT16A
PT15B
PT15A
PT14B
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
VREF1_1
PT28A
PT27A
PT26A
PT25B
PT25A
PT24A
VCCIO1
PT23B
GNDIO1
PT20A
PT19A
PT18B
PT18A
PT17B
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
VREF1_1
-
-
-
-
-
D0
-
D0
C
T
-
D1
C
T
-
D1
VREF2_1
VREF2_1
D2
D2
-
-
-
-
D3
-
D3
-
-
-
-
-
D4
-
D4
-
D5
-
D5
-
C
T
-
D6
C
T
-
D6
-
-
D7
D7
-
-
BUSY
CS1N
PCLKC0_0
PCLKT0_0
-
-
-
BUSY
CS1N
PCLKC0_0
PCLKT0_0
-
PT13B
PT13A
PT12B
PT12A
PT11B
VCCIO0
PT11A
PT9A
0
0
0
0
0
0
0
0
0
0
0
C
T
C
T
C
-
PT16B
PT16A
PT15B
PT15A
PT14B
VCCIO0
PT14A
PT12A
GNDIO0
PT11A
PT10A
0
0
0
0
0
0
0
0
0
0
0
C
T
C
T
C
-
-
-
T
-
DQS
T
-
DQS
DOUT
-
DOUT
-
GNDIO0
PT8A
-
-
-
WRITEN
VREF1_0
-
WRITEN
VREF1_0
PT7A
-
-
4-12
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PT9A
Bank Differential
Dual Function
139
140
141
142
143
144
PT6A
PT5A
PT3B
CFG0
CFG1
DONE
0
0
0
0
0
0
-
DI
0
0
0
0
0
0
-
-
-
-
-
-
DI
-
CSN
PT8A
CSN
-
-
-
-
VREF2_0
PT6B
VREF2_0
-
-
-
CFG0
-
-
-
CFG1
DONE
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-13
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
CFG1
Bank Differential
Dual Function
1
CFG1
DONE
PROGRAMN
CCLK
GND
0
0
7
7
-
-
-
-
0
0
7
7
-
-
-
-
2
-
DONE
PROGRAMN
CCLK
-
3
-
-
-
-
4
-
-
-
-
5
-
T3
-
GND
-
T3
-
6
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
7
GNDIO7
PL2B
-
-
GNDIO7
PL2B
-
-
8
C3
T
C
T3
C3
-
-
C3
T
C
T3
C3
-
-
9
PL3A
LUM0_PLLT_FB_A
PL3A
LUM0_PLLT_FB_A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PL3B
LUM0_PLLC_FB_A
PL3B
LUM0_PLLC_FB_A
PL4A
-
PL4A
-
PL4B
-
PL4B
-
VCCIO7
PL5A
-
VCCIO7
PL5A
-
-
VREF1_7
-
VREF1_7
PL6B
-
VREF2_7
PL6B
-
VREF2_7
GNDIO7
PL7A
-
-
GNDIO7
PL7A
-
-
T3
C3
-
DQS
T3
C3
-
DQS
PL7B
-
PL7B
-
VCC
-
VCC
-
PL8A
7
7
7
7
7
-
T
C
T3
-
LUM0_PLLT_IN_A
PL8A
7
7
7
7
7
-
T
C
T3
-
LUM0_PLLT_IN_A
PL8B
LUM0_PLLC_IN_A
PL8B
LUM0_PLLC_IN_A
PL9A
-
PL9A
-
VCCIO7
PL9B
-
VCCIO7
PL9B
-
C3
-
C3
-
VCCP0
GNDP0
NC
-
-
VCCP0
GNDP0
PL15B
VCCIO6
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
VCC
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
-
-
-
VCCIO6
PL11A
PL11B
PL12A
PL12B
NC
6
6
6
6
6
-
-
-
-
-
T3
C3
T
C
-
-
T3
C3
T
C
T3
C3
-
T3
C3
-
-
-
-
PCLKT6_0
PCLKT6_0
PCLKC6_0
PCLKC6_0
-
-
NC
-
-
-
-
VCC
-
-
-
-
PL13A
PL13B
GNDIO6
PL14A
PL15B
VCCIO6
PL16A
PL16B
PL17A
PL17B
PL18A
6
6
6
6
6
6
6
6
6
6
6
T3
C3
-
-
PL21A
PL21B
GNDIO6
PL22A
PL23B
VCCIO6
PL24A
PL24B
PL25A
PL25B
PL26A
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
VREF1_6
-
VREF1_6
-
VREF2_6
-
VREF2_6
-
-
-
-
T3
C3
T
C
T3
DQS
T3
C3
T
C
T3
DQS
-
-
-
-
-
-
-
-
4-14
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
GNDIO6
PL26B
GND
Bank Differential
Dual Function
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
GNDIO6
PL18B
GND
6
6
-
-
C3
-
-
6
6
-
-
C3
-
-
-
-
-
-
VCCAUX
SLEEPN1/TOE2
INITN
-
-
-
VCCAUX
SLEEPN1/TOE2
INITN
-
-
-
-
-
-
-
-
-
5
-
-
-
5
-
-
-
VCC
-
-
VCC
-
-
PB2B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
VREF1_5
PB5B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
VREF1_5
PB3A
T
C
T
C
-
-
PB6A
T
C
T
C
-
DQS
PB3B
-
PB6B
-
PB4A
-
PB7A
-
PB4B
-
PB7B
-
GNDIO5
PB5A
-
GNDIO5
PB8A
-
T
C
T
C
-
-
T
C
T
C
-
-
PB5B
VREF2_5
PB8B
VREF2_5
PB6A
-
PB9A
-
PB6B
-
PB9B
-
VCCIO5
PB7A
-
VCCIO5
PB10A
PB10B
PB11A
PB11B
GNDIO5
PB12A
PB13B
PB14A
PB14B
VCCIO5
PB15A
PB15B
PB16A
PB16B
GND
-
T
C
T
C
-
-
T
C
T
C
-
-
PB7B
-
-
PB8A
-
-
PB8B
-
-
GNDIO5
PB9A
-
-
-
-
-
-
PB10B
PB11A
PB11B
VCCIO5
PB12A
PB12B
PB13A
PB13B
GND
-
-
-
-
T
C
-
DQS
T
C
-
DQS
-
-
-
-
T
C
T
C
-
-
T
C
T
C
-
-
-
-
-
-
-
-
-
-
VCC
-
-
-
VCC
-
-
-
PB14A
GNDIO4
PB14B
PB15A
PB15B
PB16A
VCCIO4
PB16B
PB17A
PB18B
PB19A
GNDIO4
4
4
4
4
4
4
4
4
4
4
4
4
T
-
-
PB17A
GNDIO4
PB17B
PB18A
PB18B
PB19A
VCCIO4
PB19B
PB20A
PB21B
PB22A
GNDIO4
4
4
4
4
4
4
4
4
4
4
4
4
T
-
-
-
-
C
T
C
T
-
-
C
T
C
T
-
-
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
-
-
-
-
C
-
-
C
-
-
-
-
-
-
DQS
-
-
-
DQS
-
T
-
T
-
4-15
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PB22B
PB23A
PB23B
PB24A
VCCIO4
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB30A
PB30B
GND
Bank Differential
Dual Function
93
PB19B
PB20A
PB20B
PB21A
VCCIO4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND
4
4
4
4
4
4
4
4
4
4
4
4
4
-
C
T
C
T
-
VREF1_4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
C
T
C
T
-
VREF1_4
94
-
-
95
-
-
96
-
-
97
-
-
98
C
T
C
T
C
T
C
-
-
C
T
C
T
C
-
-
99
-
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
-
-
-
-
-
-
VREF2_4
VREF2_4
-
T
C
-
DQS
-
-
-
-
-
VCC
-
-
C3
-
VCC
-
-
C3
-
PR18B
GNDIO3
PR18A
PR17B
PR17A
PR16B
PR16A
VCCIO3
PR15B
PR14A
GNDIO3
PR13B
PR13A
GND
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
PR26B
GNDIO3
PR26A
PR25B
PR25A
PR24B
PR24A
VCCIO3
PR23B
PR22A
GNDIO3
PR21B
PR21A
GND
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
T3
C
T
C3
T3
-
-
T3
C
T
C3
T3
-
-
-
-
-
-
-
-
DQS
DQS
-
-
-
VREF1_3
-
VREF1_3
-
VREF2_3
-
VREF2_3
-
-
-
-
C
T
-
-
C3
T3
-
-
-
-
-
-
PR12B
PR12A
PR11B
VCCIO3
PR11A
GNDP1
VCCP1
NC
3
3
3
3
3
-
C
T
C
-
-
PR20B
PR20A
PR19B
VCCIO3
PR19A
GNDP1
VCCP1
PR13A
GND
3
3
3
3
3
-
C
T
C3
-
-
-
-
-
-
-
-
T
-
-
T3
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
GND
-
-
-
-
-
PR9B
2
2
-
C
T
-
PCLKC2_0
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR8B
2
2
2
2
2
2
2
2
C
T
C3
T3
-
PCLKC2_0
PR9A
PCLKT2_0
PCLKT2_0
NC
-
-
NC
-
-
-
-
GNDIO2
PR8B
2
2
2
2
-
-
-
C
T
C3
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
-
C
T
C3
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
-
PR8A
PR8A
PR7B
PR7B
4-16
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PR7A
Bank Differential
Dual Function
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
PR7A
VCCIO2
PR6B
2
2
2
2
2
2
2
2
2
2
2
2
-
T3
DQS
2
2
2
2
2
2
2
2
2
2
2
2
-
T3
DQS
-
-
VCCIO2
PR6B
-
-
-
VREF1_2
-
VREF1_2
PR5A
-
VREF2_2
PR5A
-
VREF2_2
GNDIO2
PR4B
-
-
GNDIO2
PR4B
-
-
C3
T3
C
T
C3
-
-
C3
T3
C
T
C3
-
-
PR4A
-
PR4A
-
PR3B
RUM0_PLLC_FB_A
PR3B
RUM0_PLLC_FB_A
PR3A
RUM0_PLLT_FB_A
PR3A
RUM0_PLLT_FB_A
PR2B
-
PR2B
-
VCCIO2
PR2A
-
VCCIO2
PR2A
-
T3
-
T3
-
VCC
-
-
VCC
-
-
VCCAUX
TDO
-
-
-
VCCAUX
TDO
-
-
-
-
-
-
-
-
-
VCCJ
-
-
-
VCCJ
-
-
-
TDI
-
-
-
TDI
-
-
-
TMS
-
-
-
TMS
-
-
-
TCK
-
-
-
TCK
-
-
-
VCC
-
-
-
VCC
-
-
-
PT25A
PT24B
PT24A
PT23A
GNDIO1
PT22B
PT22A
PT21A
VCCIO1
PT20B
PT20A
PT19B
PT19A
GNDIO1
PT18B
PT17A
PT16B
PT16A
VCCIO1
PT15B
PT15A
PT14B
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
VREF1_1
PT28A
PT27B
PT27A
PT26A
GNDIO1
PT25B
PT25A
PT24A
VCCIO1
PT23B
PT23A
PT22B
PT22A
GNDIO1
PT21B
PT20A
PT19B
PT19A
VCCIO1
PT18B
PT18A
PT17B
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
VREF1_1
C
T
-
-
C
T
-
-
-
-
D0
D0
-
-
-
-
C
T
-
D1
C
T
-
D1
VREF2_1
VREF2_1
D2
D2
-
-
-
-
C
T
C
T
-
D3
C
T
C
T
-
D3
-
-
-
-
DQS
DQS
-
-
-
-
-
-
-
D4
-
D4
C
T
-
-
C
T
-
-
D5
D5
-
-
C
T
-
D6
C
T
-
D6
-
-
D7
D7
-
-
-
-
VCC
-
-
-
BUSY
-
VCC
-
-
-
BUSY
-
PT13B
GNDIO0
0
0
C
-
PT16B
GNDIO0
0
0
C
-
4-17
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)
LFXP3
LFXP6
Pin
Number Pin Function
Bank Differential
Dual Function
Pin Function
PT16A
PT15B
PT15A
PT14B
VCCIO0
PT14A
PT13B
PT12A
PT11B
GNDIO0
PT11A
PT10B
PT10A
PT9B
Bank Differential
Dual Function
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
PT13A
PT12B
PT12A
PT11B
VCCIO0
PT11A
PT10B
PT9A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
-
CS1N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
-
CS1N
PCLKC0_0
PCLKC0_0
PCLKT0_0
PCLKT0_0
-
-
-
-
T
-
DQS
T
-
DQS
-
-
-
DOUT
-
DOUT
PT8B
C
-
-
C
-
-
GNDIO0
PT8A
-
-
T
C
T
C
-
WRITEN
T
C
T
C
-
WRITEN
PT7B
-
-
PT7A
VREF1_0
VREF1_0
PT6B
-
-
VCCIO0
PT6A
-
VCCIO0
PT9A
-
T
C
T
C
T
-
DI
T
C
T
C
T
-
DI
PT5B
-
PT8B
-
PT5A
CSN
PT8A
CSN
PT4B
-
PT7B
-
PT4A
-
PT7A
-
PT3B
VREF2_0
PT6B
VREF2_0
PT2B
-
-
-
-
PT5B
-
-
-
-
GND
-
GND
-
CFG0
0
-
CFG0
0
-
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-18
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
C2
C1
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
GNDIO7
PL3A
-
-
GNDIO7
PL3A
-
-
D2
D3
D1
E2
-
T
LUM0_PLLT_FB_A
T
C
-
LUM0_PLLT_FB_A
PL3B
C
T3
-
LUM0_PLLC_FB_A
PL3B
LUM0_PLLC_FB_A
PL2A
-
PL5A
-
PL5A
VREF1_7
PL6B
-
VREF1_7
GNDIO7
PL7A
-
-
GNDIO7
PL7A
-
-
E1
F1
E3
F4
F3
F2
-
T3
C3
T
DQS
T3
C3
T
C
T3
C3
-
DQS
PL7B
-
PL7B
-
PL12A
PL12B
PL4A
-
PL8A
-
C
T3
C3
-
-
PL8B
-
-
PL9A
-
PL4B
-
PL9B
-
GNDIO7
PL2B
-
GNDIO7
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL15B
GNDIO7
PL16A
PL16B
PL18A
PL18B
VCCP0
GNDP0
PL20A
PL20B
GNDIO6
PL22A
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
GNDIO6
PL26B
PL28A
-
G1
G3
G2
H1
H2
G4
G5
-
C3
-
-
-
PL8A
T
LUM0_PLLT_IN_A
T
C
T3
C3
-
LUM0_PLLT_IN_A
PL8B
C
T3
C3
-
LUM0_PLLC_IN_A
LUM0_PLLC_IN_A
PL9A
-
-
PL9B
-
-
PL6B
VREF2_7
VREF2_7
PL14A
GNDIO7
PL11A
PL11B
PL13A
PL13B
VCCP0
GNDP0
PL17A
PL17B
GNDIO6
PL15B
PL22A
PL16A
PL16B
PL18A
PL18B
PL19A
GNDIO6
PL19B
PL21A
-
-
-
-
-
-
-
-
J1
J2
H3
J3
H4
H5
K1
K2
-
T3
C3
T3
C3
-
-
T3
C3
T3
C3
-
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
6
T
PCLKT6_0
6
6
6
6
6
6
6
6
6
6
6
6
6
T
C
-
PCLKT6_0
C
-
PCLKC6_0
PCLKC6_0
-
-
J4
J5
L1
L2
M1
M2
K3
-
-
-
-
-
-
VREF1_6
-
VREF1_6
T3
C3
T3
C3
T3
-
-
-
-
-
-
-
-
-
T3
C3
T
C
T3
-
DQS
-
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
-
-
-
-
L3
L4
C3
T3
C3
-
4-19
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
K4
K5
-
PL20A
PL20B
GNDIO6
PL23B
PL21B
PL24A
PL24B
PL25A
PL25B
PL26A
GNDIO6
PL26B
SLEEPN1/TOE2
INITN
6
6
6
6
6
6
6
6
6
6
6
6
-
T
C
-
-
PL29A
PL29B
GNDIO6
PL31A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GNDIO6
PL35B
SLEEPN1/TOE2
INITN
6
6
6
6
6
6
6
6
6
6
6
6
-
T
C
-
-
-
-
-
-
N1
N2
P1
P2
L5
M6
M3
-
-
VREF2_6
-
VREF2_6
C3
T3
C3
T
C
T3
-
-
-
-
DQS
T3
C3
T
C
T3
-
DQS
-
-
-
LLM0_PLLT_FB_A
-
LLM0_PLLC_FB_A
-
-
-
-
N3
P4
P3
-
C3
-
C3
-
-
-
-
-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
GNDIO5
PB2A
-
-
GNDIO5
PB6A
-
-
R4
N5
-
T
C
-
-
T
C
-
-
PB2B
-
PB6B
-
GNDIO5
PB5B
-
GNDIO5
PB7A
-
P5
R1
N6
M7
R2
T2
R3
T3
-
-
VREF1_5
T
C
-
VREF1_5
PB3B
C
-
-
PB7B
-
PB4A
-
PB8A
-
PB3A
T
T
C
T
C
-
-
PB9B
-
-
PB6A
DQS
PB10A
PB10B
PB11A
PB11B
GNDIO5
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
GNDIO5
PB16A
PB17B
PB18A
PB18B
PB19A
PB19B
T
C
T
C
-
DQS
PB6B
-
-
PB7A
-
-
PB7B
-
-
GNDIO5
PB8A
-
-
T4
R5
N7
M8
T5
P6
T6
R6
-
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
PB8B
VREF2_5
VREF2_5
PB9A
-
-
PB9B
-
-
PB10A
PB10B
PB11A
PB11B
GNDIO5
PB12A
PB13B
PB14A
PB14B
PB15A
PB15B
-
-
-
-
-
-
-
-
-
-
P7
N8
R7
T7
P8
T8
-
-
-
-
-
-
-
-
T
C
T
C
DQS
T
C
T
C
DQS
-
-
-
-
-
-
4-20
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
R8
T9
PB16A
PB16B
PB17A
GNDIO4
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB21B
PB22A
GNDIO4
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB26A
GNDIO4
PB26B
PB27A
PB27B
PB28A
PB29B
PB30A
PB30B
PB31A
GNDIO4
PB31B
GNDIO3
PR26B
PR26A
PR24B
PR24A
PR15B
PR23B
GNDIO3
PR25B
PR25A
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
T
C
T
-
-
PB20A
PB20B
PB21A
GNDIO4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB25B
PB26A
GNDIO4
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
PB29B
PB30A
GNDIO4
PB30B
PB31A
PB31B
PB32A
PB33B
PB34A
PB34B
PB35A
GNDIO4
PB35B
GNDIO3
PR34B
PR34A
PR33B
PR33A
PR32B
PR31A
GNDIO3
PR29B
PR29A
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
T
C
T
-
-
-
-
R9
-
-
-
-
-
P9
C
T
C
T
C
-
-
C
T
C
T
C
-
-
T10
T11
R10
P10
N9
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
-
-
-
-
-
-
M9
-
-
-
-
R12
-
T
-
DQS
T
-
DQS
-
-
T12
P13
R13
M11
N11
N10
M10
T13
-
C
T
C
T
C
T
C
T
-
VREF1_4
C
T
C
T
C
T
C
T
-
VREF1_4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P14
R11
P12
T14
R14
P11
N12
T15
-
C
T
C
-
-
C
T
C
-
-
VREF2_4
VREF2_4
-
-
-
-
-
-
-
-
T
C
T
-
DQS
T
C
T
-
DQS
-
-
-
-
-
-
R15
-
C
-
-
C
-
-
-
-
P15
N15
P16
R16
M15
N14
-
C3
T3
C3
T3
-
-
C
T
C3
T3
-
RLM0_PLLC_FB_A
-
RLM0_PLLT_FB_A
-
-
DQS
DQS
-
-
-
VREF1_3
-
VREF1_3
-
-
-
-
-
-
-
-
M14
L13
C
T
C
T
4-21
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
L15
L14
-
PR21B
PR21A
GNDIO3
PR17B
PR20B
PR20A
PR19B
PR19A
PR17A
PR22A
GNDIO3
PR18B
PR18A
PR16B
PR16A
GNDP1
VCCP1
GNDIO2
PR12B
PR12A
PR13B
PR13A
PR2B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C3
T3
-
-
PR28B
PR28A
GNDIO3
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR22A
GNDIO3
PR21B
PR21A
PR19B
PR19A
GNDP1
VCCP1
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
PR14A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
GNDIO2
PR8B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C3
T3
-
-
-
-
-
-
L12
M16
N16
K14
K15
K12
K13
-
C
C
T
C3
T3
T
-
-
-
-
C
T
C3
T3
-
RLM0_PLLC_IN_A
-
RLM0_PLLT_IN_A
-
-
-
DQS
-
-
-
VREF2_3
-
VREF2_3
-
-
-
-
L16
K16
J15
J14
J13
J12
-
C3
T3
C3
T3
-
-
C3
T3
C3
T3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
J16
H16
H13
H12
H15
H14
-
C
PCLKC2_0
C
T
C3
T3
-
PCLKC2_0
T
PCLKT2_0
PCLKT2_0
C3
T3
C3
-
-
-
-
DQS
-
-
PR6B
VREF1_2
-
VREF1_2
GNDIO2
PR11B
PR11A
PR8B
-
-
-
-
G15
G14
G16
F16
G13
-
C3
T3
C
T
-
C3
T3
C
T
-
-
-
-
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
PR8A
RUM0_PLLT_IN_A
RUM0_PLLT_IN_A
PR2A
T3
-
-
GNDIO2
PR9B
-
-
-
-
G12
F13
B16
C16
F15
E15
-
C3
T3
C3
T3
-
-
C
T
C3
T3
-
-
PR9A
-
PR8A
-
PR7B
-
PR7B
-
PR7A
DQS
PR7A
DQS
PR14A
PR5A
-
PR6B
-
-
VREF2_2
PR5A
-
VREF2_2
GNDIO2
PR4B
-
-
GNDIO2
PR4B
-
-
F14
E14
D15
C15
C3
T3
C
T
-
C3
T3
C
T
-
PR4A
-
PR4A
-
PR3B
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
PR3B
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
PR3A
PR3A
4-22
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
E16
D16
D14
C14
B14
-
TDO
VCCJ
-
-
-
-
TDO
VCCJ
-
-
-
-
-
-
-
-
TDI
-
-
-
TDI
-
-
-
TMS
-
-
-
TMS
-
-
-
TCK
-
-
-
TCK
-
-
-
GNDIO1
PT31B
PT31A
GNDIO1
PT28A
PT30A
PT29B
PT30B
PT27B
PT27A
PT26B
PT26A
GNDIO1
PT25B
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
GNDIO1
PT21B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
PT17A
PT16B
GNDIO0
PT16A
PT15B
PT15A
PT14B
PT14A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
-
-
GNDIO1
PT35B
PT35A
GNDIO1
PT34B
PT34A
PT33B
PT32A
PT31B
PT31A
PT30B
PT30A
GNDIO1
PT29B
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
GNDIO1
PT25B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
PT21A
PT20B
GNDIO0
PT20A
PT19B
PT19A
PT18B
PT18A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
-
-
A15
B15
-
C
T
-
-
C
T
-
-
-
-
-
-
D12
C11
A14
B13
F12
E11
A13
C13
-
-
VREF1_1
C
T
-
VREF1_1
T
-
DQS
DQS
-
-
C
C
T
C
T
-
-
-
-
-
C
T
C
T
-
-
-
-
-
-
D0
D0
-
-
C10
E10
A12
B12
C12
A11
B11
D11
-
C
T
C
T
C
T
C
T
-
D1
C
T
C
T
C
T
C
T
-
D1
VREF2_1
VREF2_1
-
-
D2
D2
D3
D3
-
-
-
-
DQS
DQS
-
-
B9
-
-
-
-
D9
-
D4
-
D4
A10
B10
D10
A9
C
T
C
T
C
T
C
-
-
C
T
C
T
C
T
C
-
-
D5
D5
D6
D6
-
-
C9
D7
D7
C8
-
BUSY
-
-
BUSY
-
E9
-
B8
T
C
T
C
T
CS1N
PCLKC0_0
PCLKT0_0
-
T
C
T
C
T
CS1N
PCLKC0_0
PCLKT0_0
-
A8
A7
B7
C7
DQS
DQS
4-23
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
E8
D8
A6
-
PT13B
PT12A
PT11B
GNDIO0
PT11A
PT10B
PT10A
PT9B
PT9A
PT8B
PT8A
PT7B
GNDIO0
PT7A
PT6B
PT6A
PT5B
PT4A
PT3B
PT3A
PT2B
GNDIO0
PT2A
CFG0
CFG1
DONE
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
PT17B
PT16A
PT15B
GNDIO0
PT15A
PT14B
PT14A
PT13B
PT13A
PT12B
PT12A
PT11B
GNDIO0
PT11A
PT10B
PT10A
PT9B
PT8A
PT7B
PT7A
PT6B
GNDIO0
PT6A
CFG0
CFG1
DONE
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
DOUT
DOUT
C
-
-
C
-
-
-
-
C6
E7
D7
A5
B5
A4
B6
E6
-
T
C
T
C
T
C
T
C
-
WRITEN
T
C
T
C
T
C
T
C
-
WRITEN
-
-
VREF1_0
VREF1_0
-
-
DI
DI
-
-
CSN
CSN
-
-
-
-
D6
D5
A3
B3
B2
A2
B1
F5
-
T
C
T
-
-
T
C
T
-
-
VREF2_0
VREF2_0
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
T
C
-
C
T
C
-
C5
C4
B4
C3
A1
A16
F11
F6
G10
G7
G8
G9
H10
H7
H8
H9
J10
J7
T
-
T
-
-
-
-
-
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
J8
GND
-
-
GND
-
-
J9
GND
-
-
GND
-
-
4-24
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP6
LFXP10
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
K10
K7
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K8
GND
-
GND
-
K9
GND
-
GND
-
L11
L6
GND
-
GND
-
GND
-
GND
-
T1
GND
-
GND
-
T16
D13
D4
GND
-
GND
-
VCC
-
VCC
-
VCC
-
VCC
-
E12
E5
VCC
-
VCC
-
VCC
-
VCC
-
M12
M5
N13
N4
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
E13
E4
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
-
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
-
-
-
M13
M4
F7
-
-
-
-
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
F8
F10
F9
G11
H11
J11
K11
L10
L9
L7
L8
J6
K6
G6
H6
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-25
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
C2
C1
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
GNDIO7
GNDIO7
PL7A
-
-
GNDIO7
GNDIO7
PL7A
-
-
-
-
-
-
-
D2
D3
D1
E2
E1
F1
-
T
C
-
LUM0_PLLT_FB_A
T
C
-
LUM0_PLLT_FB_A
PL7B
LUM0_PLLC_FB_A
PL7B
LUM0_PLLC_FB_A
PL9A
-
PL9A
-
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL22A
PL22B
VCCP0
GNDP0
PL24A
GNDIO6
PL24B
PL26A
PL27B
PL28A
PL28B
GNDIO6
PL29A
PL29B
PL30A
PL30B
-
VREF1_7
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL22A
PL22B
VCCP0
GNDP0
PL28A
GNDIO6
PL28B
PL30A
PL31B
PL32A
PL32B
GNDIO6
PL33A
PL33B
PL34A
PL34B
-
VREF1_7
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
E3
F4
F3
F2
G1
-
T
C
T3
C3
-
-
T
C
T3
C3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G3
G2
H1
H2
G4
G5
J1
-
T
C
T3
C3
-
LUM0_PLLT_IN_A
T
C
T3
C3
-
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLC_IN_A
-
-
-
-
VREF2_7
VREF2_7
-
T3
-
-
T3
-
DQS
DQS
-
-
-
-
J2
H3
J3
H4
H5
K1
-
C3
T3
C3
-
-
C3
T3
C3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
T
-
PCLKT6_0
6
6
6
6
6
6
6
6
6
6
6
6
T
-
PCLKT6_0
-
-
K2
J4
J5
L1
L2
-
C
-
PCLKC6_0
C
-
PCLKC6_0
-
-
-
VREF1_6
-
VREF1_6
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
M1
M2
K3
L3
T
C
T3
C3
LLM0_PLLT_IN_A
T
C
T3
C3
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLC_IN_A
-
-
-
-
4-26
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
L4
-
PL32A
GNDIO6
PL33A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
PL36A
GNDIO6
PL37A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
K4
K5
N1
N2
P1
P2
-
T
C
-
-
T
C
-
-
PL33B
-
PL37B
-
PL35A
VREF2_6
PL39A
VREF2_6
PL36B
-
-
PL40B
-
-
PL37A
T3
C3
-
DQS
PL41A
T3
C3
-
DQS
PL37B
-
PL41B
-
GNDIO6
PL38A
-
GNDIO6
PL42A
-
L5
M6
M3
N3
-
T
C
T3
C3
-
LLM0_PLLT_FB_A
T
C
T3
C3
-
LLM0_PLLT_FB_A
PL38B
LLM0_PLLC_FB_A
PL42B
LLM0_PLLC_FB_A
PL39A
-
PL43A
-
PL39B
-
PL43B
-
GNDIO6
SLEEPN1/TOE2
INITN
-
GNDIO6
SLEEPN1/TOE2
INITN
-
P4
P3
-
-
-
-
-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
GNDIO5
GNDIO5
GNDIO5
PB11A
PB11B
PB12A
GNDIO5
PB12B
PB13A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
GNDIO5
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB22B
PB23A
-
-
GNDIO5
GNDIO5
GNDIO5
PB15A
PB15B
PB16A
GNDIO5
PB16B
PB17A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
GNDIO5
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB26B
PB27A
-
-
-
-
-
-
-
-
-
-
-
-
R4
N5
P5
-
T
C
T
-
-
T
C
T
-
-
-
-
VREF1_5
VREF1_5
-
-
R1
N6
M7
R2
T2
R3
T3
T4
R5
N7
-
C
-
-
C
-
-
-
-
-
-
-
-
T
C
T
C
T
C
T
-
DQS
T
C
T
C
T
C
T
-
DQS
-
-
-
-
-
-
-
-
VREF2_5
VREF2_5
-
-
-
-
M8
T5
P6
T6
R6
P7
N8
R7
C
T
C
T
C
-
-
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T
DQS
T
DQS
4-27
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
T7
-
PB23B
GNDIO5
PB24A
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
GNDIO4
PB28A
PB28B
PB29A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GNDIO4
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
PB38B
GNDIO4
PB39A
PB39B
PB40A
PB40B
GNDIO4
GNDIO4
GNDIO4
GNDIO3
GNDIO3
PR38B
PR38A
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
C
-
-
PB27B
GNDIO5
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
GNDIO4
PB32A
PB32B
PB33A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GNDIO4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
PB42B
GNDIO4
PB43A
PB43B
PB44A
PB44B
GNDIO4
GNDIO4
GNDIO4
GNDIO3
GNDIO3
PR42B
PR42A
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
C
-
-
-
-
P8
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
T8
-
-
R8
T9
-
-
-
-
R9
P9
-
-
-
-
T10
T11
-
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
-
-
R10
P10
N9
M9
R12
T12
P13
R13
M11
-
T
C
-
-
T
C
-
-
-
-
-
-
-
-
-
-
T
C
T
C
T
-
DQS
T
C
T
C
T
-
DQS
VREF1_4
VREF1_4
-
-
-
-
-
-
-
-
N11
N10
M10
T13
P14
R11
P12
T14
R14
-
C
T
C
T
C
T
C
-
-
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
VREF2_4
VREF2_4
-
-
-
-
-
-
-
-
-
-
-
-
P11
N12
T15
R15
-
T
C
T
C
-
DQS
T
C
T
C
-
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P15
N15
C
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
C
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
4-28
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
P16
R16
M15
N14
-
PR37B
PR37A
PR36B
PR35A
GNDIO3
PR33B
PR33A
PR32B
PR32A
PR30A
PR29B
PR29A
GNDIO3
PR28B
PR28A
PR27B
PR26A
PR25B
PR25A
GNDIO3
PR23B
PR23A
GNDP1
VCCP1
GNDIO2
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
GNDIO2
PR12B
PR12A
PR11B
PR11A
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C3
T3
-
-
PR41B
PR41A
PR40B
PR39A
GNDIO3
PR37B
PR37A
PR36B
PR36A
PR34A
PR33B
PR33A
GNDIO3
PR32B
PR32A
PR31B
PR30A
PR29B
PR29A
GNDIO3
PR27B
PR27A
GNDP1
VCCP1
GNDIO2
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
GNDIO2
PR12B
PR12A
PR11B
PR11A
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C3
T3
-
-
DQS
DQS
-
-
-
VREF1_3
-
VREF1_3
-
-
-
-
M14
L13
L15
L14
L12
M16
N16
-
C
T
C3
T3
-
-
C
T
C3
T3
-
-
-
-
-
-
-
-
-
-
C
T
-
C3
T3
-
RLM0_PLLC_IN_A
C
T
-
C3
T3
-
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
RLM0_PLLT_IN_A
-
-
K14
K15
K12
K13
L16
K16
-
-
-
DQS
DQS
-
-
-
VREF2_3
-
VREF2_3
C3
T3
-
C3
T3
-
-
C3
T3
-
C3
T3
-
-
-
-
-
-
J15
J14
J13
J12
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
J16
H16
H13
H12
H15
H14
-
C
T
C3
T3
-
PCLKC2_0
C
T
C3
T3
-
PCLKC2_0
PCLKT2_0
PCLKT2_0
-
-
DQS
DQS
-
-
-
VREF1_2
-
VREF1_2
-
-
-
-
G15
G14
G16
F16
G13
-
C3
T3
C
T
-
-
C3
T3
C
T
-
-
-
-
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
RUM0_PLLT_IN_A
-
-
-
-
-
-
G12
F13
B16
C16
C
T
C3
T3
-
C
T
C3
T3
-
-
-
-
-
DQS
DQS
4-29
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
-
GNDIO2
PR10B
PR9A
2
2
2
2
2
2
2
2
-
-
-
-
GNDIO2
PR10B
PR9A
2
2
2
2
2
2
2
2
-
-
-
-
F15
E15
F14
E14
D15
C15
-
-
-
-
VREF2_2
-
VREF2_2
PR8B
C3
T3
C
T
-
-
PR8B
C3
T3
C
T
-
-
PR8A
-
PR8A
-
PR7B
RUM0_PLLC_FB_A
PR7B
RUM0_PLLC_FB_A
PR7A
RUM0_PLLT_FB_A
PR7A
RUM0_PLLT_FB_A
GNDIO2
TDO
-
GNDIO2
TDO
-
E16
D16
D14
C14
B14
-
-
-
-
-
VCCJ
-
-
-
VCCJ
-
-
-
TDI
-
-
-
TDI
-
-
-
TMS
-
-
-
TMS
-
-
-
TCK
-
-
-
TCK
-
-
-
GNDIO1
GNDIO1
GNDIO1
PT40B
PT40A
PT39B
GNDIO1
PT39A
PT38B
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
PT33A
GNDIO1
PT32B
PT32A
PT31B
PT31A
PT30B
PT29A
PT28B
PT28A
GNDIO1
PT27B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
GNDIO1
GNDIO1
GNDIO1
PT44B
PT44A
PT43B
GNDIO1
PT43A
PT42B
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
PT37A
GNDIO1
PT36B
PT36A
PT35B
PT35A
PT34B
PT33A
PT32B
PT32A
GNDIO1
PT31B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
A15
B15
D12
-
C
T
C
-
-
C
T
C
-
-
-
-
VREF1_1
VREF1_1
-
-
C11
A14
B13
F12
E11
A13
C13
C10
E10
A12
B12
-
T
-
DQS
T
-
DQS
-
-
-
-
-
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
-
-
-
-
D0
D0
D1
D1
VREF2_1
VREF2_1
-
D2
-
-
D2
-
C12
A11
B11
D11
B9
C
T
C
T
-
D3
-
C
T
C
T
-
D3
-
-
-
DQS
-
DQS
-
D9
-
D4
-
-
D4
-
A10
B10
-
C
T
-
C
T
-
D5
-
D5
-
D10
C
D6
C
D6
4-30
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
A9
C9
C8
E9
-
PT27A
PT26B
PT26A
PT25B
GNDIO0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT21A
PT20B
GNDIO0
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT13A
GNDIO0
PT12B
PT12A
PT11B
PT11A
GNDIO0
GNDIO0
GNDIO0
CFG0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
-
-
PT31A
PT30B
PT30A
PT29B
GNDIO0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT25A
PT24B
GNDIO0
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT17A
GNDIO0
PT16B
PT16A
PT15B
PT15A
GNDIO0
GNDIO0
GNDIO0
CFG0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
-
-
D7
D7
-
-
BUSY
BUSY
-
-
B8
A8
A7
B7
C7
E8
D8
A6
-
T
C
T
C
T
-
CS1N
T
C
T
C
T
-
CS1N
PCLKC0_0
PCLKC0_0
PCLKT0_0
PCLKT0_0
-
-
DQS
DQS
-
-
-
DOUT
-
DOUT
C
-
-
C
-
-
-
-
C6
E7
D7
A5
B5
A4
B6
E6
D6
D5
A3
B3
B2
-
T
C
T
C
T
C
T
C
T
C
T
-
WRITEN
T
C
T
C
T
C
T
C
T
C
T
-
WRITEN
-
-
VREF1_0
VREF1_0
-
-
DI
DI
-
-
CSN
CSN
-
-
-
-
VREF2_0
VREF2_0
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A2
B1
F5
C5
-
C
T
C
T
-
C
T
C
T
-
-
-
-
-
-
-
C4
B4
C3
A1
A16
F11
F6
-
-
CFG1
-
CFG1
-
DONE
GND
-
DONE
GND
-
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
4-31
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
G10
G7
G8
G9
H10
H7
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
H8
GND
-
GND
-
H9
GND
-
GND
-
J10
J7
GND
-
GND
-
GND
-
GND
-
J8
GND
-
GND
-
J9
GND
-
GND
-
K10
K7
GND
-
GND
-
GND
-
GND
-
K8
GND
-
GND
-
K9
GND
-
GND
-
L11
L6
GND
-
GND
-
GND
-
GND
-
T1
GND
-
GND
-
T16
D13
D4
GND
-
GND
-
VCC
-
VCC
-
VCC
-
VCC
-
E12
E5
VCC
-
VCC
-
VCC
-
VCC
-
M12
M5
N13
N4
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
E13
E4
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
-
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
-
-
-
M13
M4
F7
-
-
-
-
0
0
1
1
2
2
3
3
4
4
0
0
1
1
2
2
3
3
4
4
F8
F10
F9
G11
H11
J11
K11
L10
L9
4-32
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
L7
L8
J6
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
5
5
6
6
7
7
-
-
-
-
-
-
-
-
-
-
-
-
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
5
5
6
6
7
7
-
-
-
-
-
-
-
-
-
-
-
-
K6
G6
H6
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-33
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
F4
G4
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
-
GNDIO7
PL2A
-
-
GNDIO7
PL6A
-
-
GNDIO7
PL6A
-
-
D2
D1
-
T3
C3
-
-
T3
C3
-
-
T3
C3
-
-
PL2B
-
PL6B
-
PL6B
-
GNDIO7
PL3A
-
GNDIO7
PL7A
-
GNDIO7
PL7A
-
E2
E3
F3
F2
H4
H3
G3
G2
-
T
LUM0_PLLT_FB_A
T
LUM0_PLLT_FB_A
T
LUM0_PLLT_FB_A
PL3B
C
T3
C3
-
LUM0_PLLC_FB_A
PL7B
C
T3
C3
-
LUM0_PLLC_FB_A
PL7B
C
T3
C3
-
LUM0_PLLC_FB_A
PL4A
-
PL8A
-
PL8A
-
PL4B
-
PL8B
-
PL8B
-
PL5A
-
PL9A
-
PL9A
-
PL6B
-
VREF1_7
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL21A
PL21B
PL22A
PL22B
VCCP0
GNDP0
PL23A
PL23B
PL24A
GNDIO6
PL24B
PL25A
PL25B
PL26A
PL27B
PL28A
PL28B
GNDIO6
-
VREF1_7
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL21A
PL21B
PL22A
PL22B
VCCP0
GNDP0
PL27A
PL27B
PL28A
GNDIO6
PL28B
PL29A
PL29B
PL30A
PL31B
PL32A
PL32B
GNDIO6
-
VREF1_7
PL7A
T3
C3
-
DQS
T3
C3
-
DQS
T3
C3
-
DQS
PL7B
-
-
-
GNDIO7
PL8A
-
-
-
F1
E1
J4
K4
G1
H2
-
T
-
T
-
T
-
PL8B
C
T3
C3
T3
C3
-
-
C
T3
C3
T3
C3
-
-
C
T3
C3
T3
C3
-
-
PL9A
-
-
-
PL9B
-
-
-
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL14A
PL15B
PL16A
GNDIO7
PL16B
PL17A
PL17B
PL18A
PL18B
VCCP0
GNDP0
PL19A
PL19B
PL20A
GNDIO6
PL20B
PL21A
PL21B
PL22A
PL23B
PL24A
PL24B
GNDIO6
-
-
-
-
-
-
-
-
-
J2
H1
J1
K2
K3
J3
K1
-
T
LUM0_PLLT_IN_A
T
LUM0_PLLT_IN_A
T
LUM0_PLLT_IN_A
C
T3
C3
-
LUM0_PLLC_IN_A
C
T3
C3
-
LUM0_PLLC_IN_A
C
T3
C3
-
LUM0_PLLC_IN_A
-
-
-
-
-
-
VREF2_7
VREF2_7
VREF2_7
-
T3
-
-
T3
-
-
T3
-
DQS
DQS
DQS
-
-
-
-
-
-
L2
L3
L4
L1
M1
M2
N1
M3
M4
P1
-
C3
T
-
C3
T
-
C3
T
-
-
-
-
C
T3
C3
-
-
C
T3
C3
-
-
C
T3
C3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
T3
C3
T
-
6
6
6
6
6
6
6
6
6
6
6
6
T3
C3
T
-
6
6
6
6
6
6
6
6
6
6
6
6
T3
C3
T
-
-
-
-
PCLKT6_0
PCLKT6_0
PCLKT6_0
-
-
-
-
-
-
N2
R1
P2
N3
N4
T1
R2
-
C
T3
C3
-
PCLKC6_0
C
T3
C3
-
PCLKC6_0
C
T3
C3
-
PCLKC6_0
-
-
-
-
-
-
-
-
-
-
VREF1_6
-
VREF1_6
-
VREF1_6
T3
C3
-
DQS
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
-
-
4-34
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
U1
T2
V1
U2
W1
V2
-
PL25A
PL25B
PL26A
PL26B
PL28A
PL28B
GNDIO6
PL29A
PL29B
PL30A
PL30B
PL31A
PL32B
PL33A
PL33B
GNDIO6
PL34A
PL34B
PL35A
PL35B
GNDIO6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
C
T3
C3
T3
C3
-
LLM0_PLLT_IN_A
PL29A
PL29B
PL30A
PL30B
PL32A
PL32B
GNDIO6
PL33A
PL33B
PL34A
PL34B
PL35A
PL36B
PL37A
PL37B
GNDIO6
PL38A
PL38B
PL39A
PL39B
GNDIO6
6
6
6
6
6
6
-
T
C
T3
C3
T3
C3
-
LLM0_PLLT_IN_A
PL33A
PL33B
PL34A
PL34B
PL36A
PL36B
GNDIO6
PL37A
PL37B
PL38A
PL38B
PL39A
PL40B
PL41A
PL41B
GNDIO6
PL42A
PL42B
PL43A
PL43B
GNDIO6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
C
T3
C3
T3
C3
-
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLC_IN_A
LLM0_PLLC_IN_A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P3
P4
Y1
W2
R3
R4
T3
T4
-
T
-
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
-
T
-
C
T3
C3
-
-
C
T3
C3
-
-
C
T3
C3
-
-
-
-
-
-
-
-
VREF2_6
VREF2_6
VREF2_6
-
-
-
-
-
-
T3
C3
-
DQS
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
-
-
V4
V3
U4
U3
-
T
LLM0_PLLT_FB_A
T
LLM0_PLLT_FB_A
T
LLM0_PLLT_FB_A
C
T3
C3
-
LLM0_PLLC_FB_A
C
T3
C3
-
LLM0_PLLC_FB_A
C
T3
C3
-
LLM0_PLLC_FB_A
-
-
-
-
-
-
-
-
-
SLEEPN1/
SLEEPN1/
SLEEPN1/
TOE2
TOE2
TOE2
W5
-
-
-
-
-
-
-
-
-
Y2
-
INITN
GNDIO5
GNDIO5
-
5
5
5
-
-
-
-
INITN
GNDIO5
GNDIO5
PB3B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
INITN
GNDIO5
GNDIO5
PB7B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
Y3
-
-
-
-
-
-
W3
W4
AA2
AA1
W6
W7
Y4
-
-
-
-
PB4A
T
C
-
-
PB8A
T
C
-
-
-
-
-
-
PB4B
-
PB8B
-
-
-
-
-
PB5A
-
PB9A
-
-
-
-
-
PB6B
-
-
PB10B
PB11A
PB11B
PB12A
GNDIO5
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
GNDIO5
PB16B
PB17A
PB18B
PB19A
PB19B
PB20A
-
-
PB2A
-
5
-
-
-
PB7A
T
C
T
-
DQS
T
C
T
-
DQS
-
-
PB7B
-
-
PB3A
GNDIO5
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
GNDIO5
PB7B
PB8A
PB9B
PB10A
PB10B
PB11A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
-
-
PB8A
-
-
-
-
GNDIO5
PB8B
-
-
Y5
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
AB2
AA3
AB3
AA4
W8
W9
AB4
-
-
PB9A
-
-
-
PB9B
-
-
-
PB10A
PB10B
PB11A
PB11B
PB12A
GNDIO5
PB12B
PB13A
PB14B
PB15A
PB15B
PB16A
-
-
-
-
-
-
-
-
-
-
-
VREF1_5
VREF1_5
VREF1_5
-
-
-
AA5
AB5
Y6
C
-
-
C
-
-
C
-
-
-
-
-
-
-
-
-
-
-
AA6
AB6
Y9
T
C
T
DQS
T
C
T
DQS
T
C
T
DQS
-
-
-
-
-
-
4-35
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Y10
AA7
AB7
Y7
PB11B
PB12A
PB12B
PB13A
GNDIO5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB17B
PB18A
PB18B
GNDIO5
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
GNDIO4
PB23A
PB23B
PB24A
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
GNDIO4
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB33B
GNDIO4
PB34A
PB34B
PB35A
PB35B
PB36A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
C
T
-
-
PB16B
PB17A
PB17B
PB18A
GNDIO5
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB22B
PB23A
PB23B
GNDIO5
PB24A
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
GNDIO4
PB28A
PB28B
PB29A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GNDIO4
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
PB38B
GNDIO4
PB39A
PB39B
PB40A
PB40B
PB41A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
C
T
-
-
PB20B
PB21A
PB21B
PB22A
GNDIO5
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB26B
PB27A
PB27B
GNDIO5
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
GNDIO4
PB32A
PB32B
PB33A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GNDIO4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
PB42B
GNDIO4
PB43A
PB43B
PB44A
PB44B
PB45A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
C
T
-
-
-
-
-
VREF2_5
VREF2_5
VREF2_5
-
-
-
-
-
-
-
AA8
AB8
Y8
C
T
C
T
C
-
-
C
T
C
T
C
-
-
C
T
C
T
C
-
-
-
-
-
-
-
-
AB9
AA9
W10
W11
AB10
AA10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T
C
-
DQS
T
C
-
DQS
T
C
-
DQS
-
-
-
-
-
-
AA11
AB11
Y11
Y12
AB12
AA12
AB13
AA13
-
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCLKT4_0
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
PCLKC4_0
-
-
-
AA14
AB14
W12
W13
AA15
AB15
AA16
AB16
Y17
-
T
C
-
-
T
C
-
-
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T
C
T
C
T
-
DQS
T
C
T
C
T
-
DQS
T
C
T
C
T
-
DQS
VREF1_4
VREF1_4
VREF1_4
-
-
-
-
-
-
-
-
-
-
-
-
AA17
Y13
Y14
AB17
Y18
AA18
AB18
Y19
AB19
-
C
T
C
T
C
T
C
-
-
C
T
C
T
C
T
C
-
-
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF2_4
VREF2_4
VREF2_4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AA19
Y20
W14
W15
AB20
T
C
T
C
T
DQS
T
C
T
C
T
DQS
T
C
T
C
T
DQS
-
-
-
-
-
-
-
-
-
-
-
-
4-36
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
AA20
AB21
AA21
AA22
Y21
-
PB36B
PB37A
PB37B
PB38A
PB38B
GNDIO4
PB39A
-
4
4
4
4
4
4
4
-
C
T
C
T
C
-
-
PB41B
PB42A
PB42B
PB43A
PB43B
GNDIO4
PB44A
PB44B
PB45A
PB46B
PB47A
PB47B
PB48A
GNDIO4
GNDIO4
GNDIO3
PR39B
PR39A
GNDIO3
PR38B
PR38A
PR37B
PR37A
PR36B
PR35A
PR34B
PR34A
GNDIO3
PR33B
PR33A
PR32B
PR32A
PR30B
PR30A
PR29B
PR29A
GNDIO3
PR28B
PR28A
PR27B
PR26A
PR25B
PR25A
PR24B
PR24A
GNDIO3
PR23B
PR23A
GNDP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
C
T
C
-
-
PB45B
PB46A
PB46B
PB47A
PB47B
GNDIO4
PB48A
PB48B
PB49A
PB50B
PB51A
PB51B
PB52A
GNDIO4
GNDIO4
GNDIO3
PR43B
PR43A
GNDIO3
PR42B
PR42A
PR41B
PR41A
PR40B
PR39A
PR38B
PR38A
GNDIO3
PR37B
PR37A
PR36B
PR36A
PR34B
PR34A
PR33B
PR33A
GNDIO3
PR32B
PR32A
PR31B
PR30A
PR29B
PR29A
PR28B
PR28A
GNDIO3
PR27B
PR27A
GNDP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
-
-
-
-
-
-
C
T
-
-
-
-
-
-
C
-
-
-
-
-
W16
W17
Y15
Y16
W19
W18
W20
-
-
-
T
C
-
-
T
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T
C
-
DQS
T
DQS
-
-
-
-
-
C
-
-
-
-
-
-
-
-
GNDIO4
GNDIO4
GNDIO3
PR35B
PR35A
GNDIO3
PR34B
PR34A
PR33B
PR33A
PR32B
PR31A
PR30B
PR30A
GNDIO3
PR29B
PR29A
PR28B
PR28A
PR26B
PR26A
PR25B
PR25A
GNDIO3
PR24B
PR24A
PR23B
PR22A
PR21B
PR21A
PR20B
PR20A
GNDIO3
PR19B
PR19A
GNDP1
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T20
T19
-
C3
T3
-
-
C3
T3
-
-
C3
T3
-
-
-
-
-
-
-
-
U19
U20
V19
V20
R19
R20
W21
Y22
-
C
T
C3
T3
-
RLM0_PLLC_FB_A
C
T
C3
T3
-
RLM0_PLLC_FB_A
C
T
C3
T3
-
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLT_FB_A
RLM0_PLLT_FB_A
-
-
-
DQS
DQS
DQS
-
-
-
-
VREF1_3
-
VREF1_3
-
VREF1_3
C3
T3
-
-
C3
T3
-
-
C3
T3
-
-
-
-
-
-
-
-
P19
P20
V21
W22
U21
V22
T21
U22
-
C
T
C3
T3
C3
T3
C
T
-
-
C
T
C3
T3
C3
T3
C
T
-
-
C
T
-
-
-
-
-
-
C3
T3
C3
T3
C
T
-
-
-
-
-
-
-
-
-
-
RLM0_PLLC_IN_A
RLM0_PLLC_IN_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
RLM0_PLLT_IN_A
RLM0_PLLT_IN_A
-
-
-
-
R21
T22
N19
N20
R22
P22
P21
N21
-
C3
T3
-
-
C3
T3
-
-
C3
T3
-
-
DQS
DQS
DQS
-
-
-
-
VREF2_3
-
VREF2_3
-
VREF2_3
C3
T3
C
T
-
C3
T3
-
-
-
-
-
-
-
-
-
C3
T3
C
T
-
C3
T3
-
-
-
-
-
-
-
-
-
C3
T3
C
T
-
-
-
-
-
-
-
-
-
M20
M19
N22
C3
T3
-
4-37
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
M21
-
VCCP1
GNDIO2
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR14A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR9B
PR9A
PR8B
PR8A
PR7B
PR7A
GNDIO2
PR6B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
PR2A
GNDIO2
TDO
-
-
-
-
VCCP1
GNDIO2
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR10B
PR9A
-
-
-
-
VCCP1
GNDIO2
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR10B
PR9A
-
-
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
M22
L22
K22
K21
L19
K20
L20
L21
-
C3
T3
C
T
C3
T3
-
-
C3
T3
C
T
C3
T3
-
-
C3
T3
C
T
C3
T3
-
-
-
-
-
PCLKC2_0
PCLKC2_0
PCLKC2_0
PCLKT2_0
PCLKT2_0
PCLKT2_0
-
-
-
DQS
DQS
DQS
-
-
-
-
VREF1_2
-
VREF1_2
-
VREF1_2
-
-
-
-
-
-
J22
J21
H22
H21
K19
J19
-
C3
T3
C
T
C3
T3
-
C3
T3
C
T
C3
T3
-
-
C3
T3
C
T
C3
T3
-
C3
T3
C
T
C3
T3
-
-
C3
T3
C
T
C3
T3
-
C3
T3
C
T
C3
T3
-
-
-
-
-
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
RUM0_PLLT_IN_A
RUM0_PLLT_IN_A
-
-
-
-
-
-
-
-
-
J20
H20
H19
G19
G22
G21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQS
DQS
DQS
-
-
-
F20
G20
F22
F21
E22
E21
D22
D21
-
-
-
-
-
-
-
-
VREF2_2
-
VREF2_2
-
VREF2_2
C3
T3
C
T
C3
T3
-
-
PR8B
C3
T3
C
T
C3
T3
-
-
PR8B
C3
T3
C
T
C3
T3
-
-
-
PR8A
-
PR8A
-
RUM0_PLLC_FB_A
PR7B
RUM0_PLLC_FB_A
PR7B
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
PR7A
RUM0_PLLT_FB_A
PR7A
RUM0_PLLT_FB_A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PR6B
-
PR6B
-
PR6A
-
PR6A
-
GNDIO2
TDO
-
GNDIO2
TDO
-
F19
E20
D20
D19
D18
-
-
-
-
-
-
VCCJ
TDI
-
-
-
-
-
VCCJ
-
-
-
-
-
-
VCCJ
-
-
-
-
-
-
-
TDI
-
-
TDI
-
-
TMS
-
TMS
-
-
TMS
-
-
TCK
-
TCK
-
-
TCK
-
-
GNDIO1
-
1
-
GNDIO1
PT48A
PT47B
PT47A
PT46B
PT45A
PT44B
PT44A
PT43B
GNDIO1
1
1
1
1
1
1
1
1
1
1
-
-
GNDIO1
PT52A
PT51B
PT51A
PT50B
PT49A
PT48B
PT48A
PT47B
GNDIO1
1
1
1
1
1
1
1
1
1
1
-
-
E19
D17
D16
C16
C15
C17
C18
C19
-
-
-
-
-
-
-
-
-
-
C
T
-
-
C
T
-
-
-
-
-
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
T
C
-
C
T
C
-
PT39A
PT38B
GNDIO1
1
1
1
-
C
-
4-38
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
C20
C21
C22
B22
A21
D15
D14
B21
-
PT38A
PT37B
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
GNDIO1
PT34A
PT33B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
PT29A
PT28B
PT28A
GNDIO1
PT27B
PT27A
PT26B
PT26A
PT25B
PT24A
PT23B
PT23A
GNDIO1
PT22B
PT22A
PT21B
PT21A
PT20B
GNDIO0
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
PT16A
PT15B
GNDIO0
PT15A
PT14B
PT14A
PT13B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
C
-
-
PT43A
PT42B
PT42A
PT41B
PT41A
PT40B
PT40A
PT39B
GNDIO1
PT39A
PT38B
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
PT33A
GNDIO1
PT32B
PT32A
PT31B
PT31A
PT30B
PT29A
PT28B
PT28A
GNDIO1
PT27B
PT27A
PT26B
PT26A
PT25B
GNDIO0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT21A
PT20B
GNDIO0
PT20A
PT19B
PT19A
PT18B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
C
-
-
PT47A
PT46B
PT46A
PT45B
PT45A
PT44B
PT44A
PT43B
GNDIO1
PT43A
PT42B
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
PT37A
GNDIO1
PT36B
PT36A
PT35B
PT35A
PT34B
PT33A
PT32B
PT32A
GNDIO1
PT31B
PT31A
PT30B
PT30A
PT29B
GNDIO0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT25A
PT24B
GNDIO0
PT24A
PT23B
PT23A
PT22B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF1_1
VREF1_1
VREF1_1
-
-
-
A20
B20
A19
B19
A18
C14
C13
B18
A17
B17
A16
-
T
-
DQS
T
-
DQS
T
-
DQS
-
-
-
-
-
-
-
-
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
D0
D0
D0
D1
D1
D1
VREF2_1
VREF2_1
VREF2_1
-
-
-
D2
D2
D2
-
-
-
B16
A15
B15
A14
D13
D12
B14
A13
-
C
T
C
T
-
D3
C
T
C
T
-
D3
C
T
C
T
-
D3
-
-
-
-
-
-
DQS
DQS
DQS
-
-
-
-
D4
-
D4
-
D4
C
T
-
-
C
T
-
-
C
T
-
-
D5
D5
D5
-
-
-
B13
A12
B12
C12
C11
-
C
T
C
T
C
-
D6
C
T
C
T
C
-
D6
C
T
C
T
C
-
D6
-
-
-
D7
D7
D7
-
-
-
BUSY
BUSY
BUSY
-
-
-
B11
A11
A10
B10
B9
T
C
T
C
T
-
CS1N
T
C
T
C
T
-
CS1N
T
C
T
C
T
-
CS1N
PCLKC0_0
PCLKC0_0
PCLKC0_0
PCLKT0_0
PCLKT0_0
PCLKT0_0
-
-
-
DQS
DQS
DQS
D11
D10
A9
-
-
-
-
DOUT
-
DOUT
-
DOUT
C
-
-
C
-
-
C
-
-
-
-
-
-
C8
T
C
T
C
WRITEN
T
C
T
C
WRITEN
T
C
T
C
WRITEN
B8
-
-
-
A8
VREF1_0
-
VREF1_0
-
VREF1_0
-
C7
4-39
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
A7
B7
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
PT8A
GNDIO0
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
GNDIO0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
T
C
T
-
DI
PT18A
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT13A
GNDIO0
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
PT9A
PT8B
PT8A
GNDIO0
PT7B
PT7A
PT6B
PT5A
PT4B
PT4A
PT3B
GNDIO0
GNDIO0
CFG0
CFG1
DONE
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
T
C
T
-
DI
PT22A
PT21B
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT17A
GNDIO0
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
PT13A
PT12B
PT12A
GNDIO0
PT11B
PT11A
PT10B
PT9A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
T
C
T
-
DI
-
-
-
C6
C10
C9
A6
CSN
CSN
CSN
-
-
-
-
-
-
VREF2_0
VREF2_0
VREF2_0
B6
DQS
DQS
DQS
A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B5
-
-
-
-
-
-
-
-
-
-
-
C5
A4
C
T
C
T
C
T
C
T
C
T
-
C
T
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
C
T
-
-
-
-
D9
D8
B4
-
-
-
-
-
-
A2
-
-
A3
-
-
B3
-
-
C4
C3
-
-
-
-
-
-
-
C2
D3
D7
D6
E4
-
C
T
-
-
C
T
-
-
PT2A
-
0
-
-
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
T
-
PT8B
C
T
-
D4
D5
-
-
-
-
PT8A
-
-
-
PT7B
GNDIO0
GNDIO0
CFG0
CFG1
DONE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
0
0
0
0
-
-
-
GNDIO0
GNDIO0
CFG0
CFG1
DONE
GND
-
-
-
-
-
C1
B2
-
-
-
-
-
-
B1
-
-
-
A1
-
-
-
A22
AB1
AB22
H10
H11
H12
H13
H14
J10
J11
J12
J13
J14
J9
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
K10
-
-
GND
-
-
GND
-
-
4-40
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
K11
K12
K13
K14
K9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCAUX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCAUX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCAUX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
N10
N11
N12
N13
N14
N9
P10
P11
P12
P13
P14
P9
R10
R11
R12
R13
R14
H9
J15
J8
K15
K8
L15
L8
M15
M8
N15
N8
P15
P8
R9
G16
4-41
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
LFXP10
LFXP15
LFXP20
Ball
Number
Ball
Function
Ball
Function
Ball
Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
Bank Diff.
Dual Function
G7
T16
T7
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G10
G11
G8
0
0
0
0
0
1
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
7
7
7
7
0
0
0
0
0
1
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
7
7
7
7
0
0
0
0
0
1
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
7
7
7
7
G9
H8
G12
G13
G14
G15
H15
H16
J16
K16
L16
M16
N16
P16
R16
R15
T12
T13
T14
T15
R8
T10
T11
T8
T9
M7
N7
P7
R7
H7
J7
K7
L7
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-42
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
F5
E3
C1
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
PROGRAMN
CCLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
PL2B
-
-
PL2B
-
-
GNDIO7
PL3A
-
-
GNDIO7
PL3A
-
-
G5
G6
F4
F3
G4
G3
D1
D2
-
T3
C3
T
-
T3
C3
T
-
PL3B
-
PL3B
-
PL4A
-
PL4A
-
PL4B
C
T3
C3
T3
C3
-
-
PL4B
C
T3
C3
T3
C3
-
-
PL5A
-
PL5A
-
PL5B
-
PL5B
-
PL6A
-
PL6A
-
PL6B
-
PL6B
-
GNDIO7
PL7A
-
GNDIO7
PL7A
-
E1
E2
H5
H6
H4
H3
F1
F2
-
T
LUM0_PLLT_FB_A
T
LUM0_PLLT_FB_A
PL7B
C
T3
C3
-
LUM0_PLLC_FB_A
PL7B
C
T3
C3
-
LUM0_PLLC_FB_A
PL8A
-
PL8A
-
PL8B
-
PL8B
-
PL9A
-
PL9A
-
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL21A
PL21B
PL22A
PL22B
-
VREF1_7
PL10B
PL11A
PL11B
GNDIO7
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
GNDIO7
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
GNDIO7
PL20B
PL21A
PL21B
PL22A
PL22B
-
VREF1_7
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
J5
J6
G1
G2
J4
J3
-
T
-
T
-
C
T3
C3
T3
C3
-
-
C
T3
C3
T3
C3
-
-
-
-
-
-
-
-
-
-
-
-
H1
H2
J1
J2
K3
K2
K4
-
T
LUM0_PLLT_IN_A
T
LUM0_PLLT_IN_A
C
T3
C3
-
LUM0_PLLC_IN_A
C
T3
C3
-
LUM0_PLLC_IN_A
-
-
-
-
VREF2_7
VREF2_7
-
T3
-
-
T3
-
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K5
K1
L2
L4
L3
C3
T
C3
T
C
T3
C3
C
T3
C3
4-43
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
L1
M1
M2
L5
N2
N1
P2
P1
M4
M3
R2
-
-
-
-
-
-
PL23A
PL23B
PL24A
VCCP0
GNDP0
PL25B
PL26A
PL26B
PL27A
PL27B
PL28A
GNDIO6
PL28B
PL29A
PL29B
PL30A
PL31B
PL32A
PL32B
GNDIO6
PL33A
PL33B
PL34A
PL34B
PL36A
PL36B
GNDIO6
PL37A
PL37B
PL38A
PL38B
PL39A
PL40B
PL41A
PL41B
GNDIO6
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
7
7
7
-
T3
C3
-
-
-
-
-
-
-
-
-
-
-
VCCP0
GNDP0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
T3
C3
T3
C3
T
-
-
-
-
-
-
PL23A
PL23B
PL24A
GNDIO6
PL24B
PL25A
PL25B
PL26A
PL27B
PL28A
PL28B
GNDIO6
PL29A
PL29B
PL30A
PL30B
PL32A
PL32B
GNDIO6
PL33A
PL33B
PL34A
PL34B
PL35A
PL36B
PL37A
PL37B
GNDIO6
PL38A
PL38B
PL39A
PL39B
PL40A
PL40B
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T3
C3
T
-
-
-
-
PCLKT6_0
PCLKT6_0
-
-
-
-
R1
N3
N4
M5
N5
T2
T1
-
C
T3
C3
-
PCLKC6_0
C
T3
C3
-
PCLKC6_0
-
-
-
-
-
-
-
VREF1_6
-
VREF1_6
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
U2
U1
P3
P4
P6
P5
-
T
LLM0_PLLT_IN_A
T
LLM0_PLLT_IN_A
C
T3
C3
T3
C3
-
LLM0_PLLC_IN_A
C
T3
C3
T3
C3
-
LLM0_PLLC_IN_A
-
-
-
-
-
-
-
-
-
-
V2
V1
W2
W1
R3
R4
R6
R5
-
T
-
T
-
C
T3
C3
-
-
C
T3
C3
-
-
-
-
-
-
VREF2_6
VREF2_6
-
-
-
-
T3
C3
-
DQS
T3
C3
-
DQS
-
-
-
-
Y2
Y1
T3
T4
W3
V3
T
LLM0_PLLT_FB_A
T
LLM0_PLLT_FB_A
C
T3
C3
T3
C3
LLM0_PLLC_FB_A
C
T3
C3
T3
C3
LLM0_PLLC_FB_A
-
-
-
-
-
-
-
-
4-44
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
T6
T5
-
PL41A
PL41B
GNDIO6
PL42A
PL42B
PL43A
6
6
6
6
6
6
T
C
-
T3
C3
-
-
-
-
-
-
-
PL45A
PL45B
GNDIO6
PL46A
PL46B
PL47A
6
6
6
6
6
6
T
C
-
T3
C3
-
-
-
-
-
-
-
U3
U4
V4
SLEEPN1/
SLEEPN1/
W4
-
-
-
-
-
-
TOE2
TOE2
W5
Y3
-
INITN
-
5
-
-
-
-
INITN
PB3B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
GNDIO5
-
5
-
-
-
GNDIO5
PB4A
-
-
U5
V5
Y4
Y5
V6
-
-
-
T
C
T
C
T
-
-
-
-
-
-
PB4B
-
-
-
-
-
PB5A
-
-
-
-
-
PB5B
-
-
-
-
-
PB6A
-
GNDIO5
-
5
-
-
-
GNDIO5
PB6B
-
U6
W6
Y6
AA2
AA3
V7
U7
Y7
W7
AA4
-
-
-
C
T
C
T
C
-
-
PB3A
PB3B
PB4A
PB4B
PB5A
PB6B
PB7A
PB7B
PB8A
GNDIO5
PB8B
PB9A
PB9B
PB10A
PB10B
PB11A
PB11B
PB12A
GNDIO5
PB12B
PB13A
PB14B
PB15A
PB15B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
-
-
PB7A
-
-
PB7B
-
-
PB8A
-
-
PB8B
-
-
PB9A
-
-
-
PB10B
PB11A
PB11B
PB12A
GNDIO5
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
GNDIO5
PB16B
PB17A
PB18B
PB19A
PB19B
-
-
T
C
T
-
DQS
T
C
T
-
DQS
-
-
-
-
-
-
AA5
AB3
AB4
AA6
AA7
U8
V8
Y8
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF1_5
VREF1_5
-
-
W8
V9
U9
Y9
W9
C
-
-
C
-
-
-
-
-
-
DQS
-
-
-
DQS
-
T
C
T
C
4-45
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
AB5
AB6
AA8
AA9
W10
-
PB16A
PB16B
PB17A
PB17B
PB18A
GNDIO5
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB22B
PB23A
PB23B
GNDIO5
PB24A
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
GNDIO4
PB28A
PB28B
PB29A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GNDIO4
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
-
-
PB20A
PB20B
PB21A
PB21B
PB22A
GNDIO5
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB26B
PB27A
PB27B
GNDIO5
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
GNDIO4
PB32A
PB32B
PB33A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GNDIO4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
-
-
-
-
-
-
VREF2_5
VREF2_5
-
-
-
-
V10
AB7
AB8
AB9
AB10
Y10
AA10
W11
V11
-
C
T
C
T
C
-
-
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T
C
-
DQS
T
C
-
DQS
-
-
-
-
Y11
AA11
AB11
AB12
Y12
AA12
W12
V12
-
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
PCLKT4_0
PCLKT4_0
PCLKC4_0
PCLKC4_0
-
-
AB13
AB14
AA13
Y13
AB15
AB16
V13
W13
AA14
-
T
C
-
-
T
C
-
-
-
-
-
-
-
-
-
-
T
C
T
C
T
-
DQS
T
C
T
C
T
-
DQS
VREF1_4
VREF1_4
-
-
-
-
-
-
-
-
AA15
AB17
AB18
W14
Y14
U14
V14
C
T
C
T
C
T
C
-
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
VREF2_4
-
VREF2_4
-
4-46
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
AB19
AB20
-
PB37A
PB38B
GNDIO4
PB39A
PB39B
PB40A
PB40B
PB41A
PB41B
PB42A
PB42B
PB43A
PB43B
GNDIO4
PB44A
PB44B
PB45A
PB46B
PB47A
PB47B
PB48A
PB48B
GNDIO4
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
-
-
-
PB41A
PB42B
GNDIO4
PB43A
PB43B
PB44A
PB44B
PB45A
PB45B
PB46A
PB46B
PB47A
PB47B
GNDIO4
PB48A
PB48B
PB49A
PB50B
PB51A
PB51B
PB52A
PB52B
GNDIO4
PB53A
PB53B
PB54A
PB54B
PB55A
PB55B
GNDIO4
PB56A
GNDIO3
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
PR44A
PR43B
PR43A
GNDIO3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
-
-
V15
U15
Y15
W15
AA16
AA17
AA18
AA19
Y16
W16
-
T
C
T
C
T
C
T
C
T
C
-
DQS
T
C
T
C
T
C
T
C
T
C
-
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AA20
AA21
Y17
Y18
Y19
Y20
V16
U16
-
T
C
-
-
T
C
-
-
-
-
-
-
-
-
-
-
T
C
T
C
-
DQS
T
C
T
C
-
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
U18
V18
W19
W18
U17
V17
-
-
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GNDIO4
-
4
-
-
W17
-
-
-
GNDIO3
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
PR39A
GNDIO3
3
3
3
3
3
3
3
3
3
3
3
-
-
V19
U20
U19
V20
W20
T17
T18
T19
T20
-
-
-
C3
T3
C
T
C3
T3
C3
T3
-
C3
T3
C
T
C3
T3
C3
T3
-
4-47
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
R18
R17
Y22
Y21
W22
W21
P17
P18
-
PR38B
PR38A
PR37B
PR37A
PR36B
PR35A
PR34B
PR34A
GNDIO3
PR33B
PR33A
PR32B
PR32A
PR30B
PR30A
PR29B
PR29A
GNDIO3
PR28B
PR28A
PR27B
PR26A
PR25B
PR25A
PR24B
PR24A
GNDIO3
PR23B
PR23A
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
C3
T3
-
RLM0_PLLC_FB_A
PR42B
PR42A
PR41B
PR41A
PR40B
PR39A
PR38B
PR38A
GNDIO3
PR37B
PR37A
PR36B
PR36A
PR34B
PR34A
PR33B
PR33A
GNDIO3
PR32B
PR32A
PR31B
PR30A
PR29B
PR29A
PR28B
PR28A
GNDIO3
PR27B
PR27A
PR26B
PR26A
PR25B
GNDP1
VCCP1
PR24A
PR23B
PR23A
GNDIO2
PR22B
PR22A
PR21B
PR21A
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
C3
T3
-
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLT_FB_A
-
-
DQS
DQS
-
-
-
VREF1_3
-
VREF1_3
C3
T3
-
-
C3
T3
-
-
-
-
-
-
R19
R20
V22
V21
U22
U21
P19
P20
-
C
T
C3
T3
C3
T3
C
T
-
-
C
-
-
T
-
-
C3
T3
C3
T3
C
T
-
-
-
-
-
-
-
RLM0_PLLC_IN_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
RLM0_PLLT_IN_A
-
-
-
T22
T21
R22
R21
N19
N20
N18
M18
-
C3
T3
-
-
C3
T3
-
-
DQS
DQS
-
-
-
VREF2_3
-
VREF2_3
C3
T3
C
T
-
C3
T3
-
-
C3
T3
C
T
-
-
-
-
-
-
-
-
-
-
P22
P21
N22
N21
M19
M20
L18
M21
M22
L22
-
-
C3
T3
C3
T3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GNDP1
VCCP1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
-
-
PR22B
PR22A
GNDIO2
-
2
2
2
-
C3
T3
-
-
C3
T3
-
C3
T3
C
T
-
-
-
-
-
L19
L20
L21
K22
-
-
-
-
-
-
-
-
PR21B
PR21A
2
2
C
T
PCLKC2_0
PCLKT2_0
PCLKC2_0
PCLKT2_0
4-48
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
J21
J22
K18
K19
-
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR10B
PR9A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C3
T3
-
-
PR20B
PR20A
PR19B
PR18A
GNDIO2
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
GNDIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GNDIO2
PR10B
PR9A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C3
T3
-
-
DQS
DQS
-
-
-
VREF1_2
-
VREF1_2
-
-
-
-
K21
K20
H21
H22
J20
J19
-
C3
T3
C
T
C3
T3
-
C3
T3
C
T
C3
T3
-
-
C3
T3
C
T
C3
T3
-
C3
T3
C
T
C3
T3
-
-
-
-
RUM0_PLLC_IN_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
RUM0_PLLT_IN_A
-
-
-
-
-
-
J17
J18
G21
G22
F21
F22
-
-
-
-
-
-
-
-
-
-
-
DQS
DQS
-
-
H20
H19
H17
H18
E21
E22
D21
D22
G20
G19
G17
G18
-
-
-
-
-
-
VREF2_2
-
VREF2_2
PR8B
C3
T3
C
T
C3
T3
C3
T3
C
T
-
PR8B
C3
T3
C
T
C3
T3
C3
T3
C
T
-
PR8A
-
PR8A
-
PR7B
RUM0_PLLC_FB_A
PR7B
RUM0_PLLC_FB_A
PR7A
RUM0_PLLT_FB_A
PR7A
RUM0_PLLT_FB_A
PR6B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PR6B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PR6A
PR6A
PR5B
PR5B
PR5A
PR5A
PR4B
PR4B
PR4A
PR4A
GNDIO2
PR3B
-
GNDIO2
PR3B
-
F18
F19
C22
F20
E20
D19
E19
D20
C20
-
C3
T3
-
C3
T3
-
PR3A
PR3A
PR2B
PR2B
TDO
-
TDO
-
VCCJ
-
-
VCCJ
-
-
TDI
-
-
TDI
-
-
TMS
-
-
TMS
-
-
TCK
-
-
TCK
-
-
-
-
-
PT56A
GNDIO1
1
1
-
GNDIO1
1
-
-
4-49
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
D18
E18
C19
C18
C21
-
-
-
-
-
-
PT55B
PT55A
PT54B
PT54A
PT53B
GNDIO1
PT53A
PT52B
PT52A
PT51B
PT51A
PT50B
PT49A
PT48B
PT48A
PT47B
GNDIO1
PT47A
PT46B
PT46A
PT45B
PT45A
PT44B
PT44A
PT43B
GNDIO1
PT43A
PT42B
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
PT37A
GNDIO1
PT36B
PT36A
PT35B
PT35A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GNDIO1
-
1
-
-
-
-
B21
E17
E16
C17
D17
F17
F16
C16
D16
A20
-
-
-
T
C
T
C
T
-
-
PT48B
PT48A
PT47B
PT47A
PT46B
PT45A
PT44B
PT44A
PT43B
GNDIO1
PT43A
PT42B
PT42A
PT41B
PT41A
PT40B
PT40A
PT39B
GNDIO1
PT39A
PT38B
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
PT33A
GNDIO1
PT32B
PT32A
PT31B
PT31A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
-
-
-
-
-
-
-
DQS
DQS
-
-
-
-
-
-
C
T
C
-
-
C
T
C
-
-
-
-
-
-
-
-
B20
A19
B19
C15
D15
A18
B18
F15
-
T
C
T
C
T
C
T
C
-
-
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF1_1
VREF1_1
-
-
E15
A17
B17
E14
F14
D14
C14
A16
B16
A15
B15
-
T
-
DQS
T
-
DQS
-
-
-
-
-
-
C
T
C
T
C
T
C
T
-
-
C
T
C
T
C
T
C
T
-
-
-
-
-
-
D0
D0
D1
D1
VREF2_1
VREF2_1
-
D2
-
-
D2
-
E13
D13
C13
B13
C
T
C
T
D3
-
C
T
C
T
D3
-
-
-
DQS
DQS
4-50
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
A14
B14
C12
B12
-
PT30B
PT29A
PT28B
PT28A
GNDIO1
PT27B
PT27A
PT26B
PT26A
PT25B
GNDIO0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT21A
PT20B
GNDIO0
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT13A
GNDIO0
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
PT34B
PT33A
PT32B
PT32A
GNDIO1
PT31B
PT31A
PT30B
PT30A
PT29B
GNDIO0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT25A
PT24B
GNDIO0
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT17A
GNDIO0
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
PT13A
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
D4
-
D4
C
T
-
-
C
T
-
-
D5
D5
-
-
D12
E12
A13
A12
A11
-
C
T
C
T
C
-
D6
C
T
C
T
C
-
D6
-
-
D7
D7
-
-
BUSY
BUSY
-
-
A10
D11
E11
B11
C11
B9
T
C
T
C
T
-
CS1N
T
C
T
C
T
-
CS1N
PCLKC0_0
PCLKC0_0
PCLKT0_0
PCLKT0_0
-
-
DQS
DQS
-
-
A9
-
DOUT
-
DOUT
B8
C
-
-
C
-
-
-
-
-
A8
T
C
T
C
T
C
T
C
T
C
T
-
WRITEN
T
C
T
C
T
C
T
C
T
C
T
-
WRITEN
E10
D10
C10
B10
B7
-
-
VREF1_0
VREF1_0
-
-
DI
DI
-
-
A7
CSN
CSN
C9
D9
B6
-
-
-
-
VREF2_0
VREF2_0
A6
DQS
DQS
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E9
-
-
-
-
-
B5
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
A5
C8
D8
B4
A4
F8
E8
PT9A
4-51
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
B3
A3
PT8B
PT8A
GNDIO0
PT7B
PT7A
PT6B
PT5A
PT4B
PT4A
PT3B
PT3A
GNDIO0
-
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
-
-
PT12B
PT12A
GNDIO0
PT11B
PT11A
PT10B
PT9A
PT8B
PT8A
PT7B
PT7A
GNDIO0
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
GNDIO0
PT3B
CFG0
CFG1
DONE
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
-
-
-
-
-
-
-
D7
C
T
-
-
C
T
-
-
C7
DQS
DQS
B2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C2
-
-
C3
C
T
C
T
-
C
T
C
T
-
D3
F7
E7
-
C6
-
C
T
C
T
C
T
-
D6
-
-
-
C5
-
-
-
C4
-
-
-
F6
-
-
-
E6
-
-
-
-
GNDIO0
-
0
-
-
E4
-
-
E5
CFG0
CFG1
DONE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
0
0
-
-
-
D4
-
-
D5
-
-
A1
-
-
A2
-
-
GND
-
-
A21
A22
AA1
AA22
AB1
AB2
AB21
AB22
B1
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
B22
H14
H9
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
J10
J11
J12
J13
J14
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
-
-
GND
-
-
4-52
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
J15
J8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J9
K10
K11
K12
K13
K14
K9
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
N10
N11
N12
N13
N14
N9
P10
P11
P12
P13
P14
P15
P8
P9
R14
R9
F10
F13
G10
G13
G14
4-53
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
G9
H15
H8
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC
-
VCC
-
J16
J7
VCC
-
VCC
-
VCC
-
VCC
-
K16
K17
K6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
K7
VCC
-
VCC
-
N16
N17
N6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
N7
VCC
-
VCC
-
P16
P7
VCC
-
VCC
-
VCC
-
VCC
-
R15
R8
VCC
-
VCC
-
VCC
-
VCC
-
T10
T13
T14
T9
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
U10
U13
G15
G16
G7
VCC
-
VCC
-
VCC
-
VCC
-
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
-
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
-
-
-
-
-
G8
-
-
H16
H7
-
-
-
-
R16
R7
-
-
-
-
T15
T16
T7
-
-
-
-
-
-
T8
-
-
F11
G11
H10
H11
F12
G12
H12
0
0
0
0
1
1
1
0
0
0
0
1
1
1
4-54
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
LFXP15
LFXP20
Ball
Number
Ball
Function
Dual
Function
Ball
Function
Dual
Function
Bank Differential
Bank Differential
H13
K15
L15
L16
L17
M15
M16
M17
N15
R12
R13
T12
U12
R10
R11
T11
U11
M6
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M7
M8
N8
K8
L6
L7
L8
1. Applies to LFXP “C” only.
2. Applies to LFXP “E” only.
3. Supports dedicated LVDS outputs.
4-55
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following located on the Lattice website at
www.latticesemi.com.
• Thermal Management document
• Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices
• Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from
www.latticesemi.com/software
4-56
LatticeXP Family Data Sheet
Ordering Information
Data Sheet DS1001
December 2005
Part Number Description
LFXP XX X – X XXXXXX X
Device Family
Grade
LatticeXP FPGA
C = Commercial
I = Industrial
Logic Capacity
3K LUTs = 3
Package
T100 = 100-pin TQFP
T144 = 144-pin TQFP
Q208 = 208-pin PQFP
F256 = 256-ball fpBGA
F388 = 388-ball fpBGA
F484 = 484-ball fpBGA
6K LUTs = 6
10K LUTs = 10
15K LUTs = 15
20K LUTs = 20
Supply Voltage
C = 1.8V/2.5V/3.3V
E = 1.2V
TN100 = 100-pin Lead-free TQFP
TN144 = 144-pin Lead-free TQFP
QN208 = 208-pin Lead-free PQFP
FN256 = 256-ball Lead-free fpBGA
FN388 = 388-ball Lead-free fpBGA
FN484 = 484-ball Lead-free fpBGA
Note: Parts dual marked per table below.
Speed
3 = Slowest
4
5 = Fastest
Ordering Information (Contact Factory for Specific Device Availability)
Note:þLatticeXP devices are dual marked. For example, the commercial speed grade LFXP10E-4F256C is also
marked with industrial grade -3I (LFXP10E-3F256I). The commercial grade is one speed grade faster than the
associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings.
The markings appear as follows:
LFXP10E-
4F256C-3I
Datecode
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
5-1
DS1001 Ordering Information_03.0
Ordering Information
Lattice Semiconductor
Conventional Packaging
LatticeXP Family Data Sheet
Commercial
Part Number
LFXP3C-3Q208C
LFXP3C-4Q208C
LFXP3C-5Q208C
LFXP3C-3T144C
LFXP3C-4T144C
LFXP3C-5T144C
LFXP3C-3T100C
LFXP3C-4T100C
LFXP3C-5T100C
I/Os
Voltage
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
136
136
136
100
100
100
62
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
62
-4
62
-5
Part Number
LFXP6C-3F256C
LFXP6C-4F256C
LFXP6C-5F256C
LFXP6C-3Q208C
LFXP6C-4Q208C
LFXP6C-5Q208C
LFXP6C-3T144C
LFXP6C-4T144C
LFXP6C-5T144C
I/Os
188
188
188
142
142
142
100
100
100
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP10C-3F388C
LFXP10C-4F388C
LFXP10C-5F388C
LFXP10C-3F256C
LFXP10C-4F256C
LFXP10C-5F256C
I/Os
244
244
244
188
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
9.7K
9.7K
9.7K
9.7K
9.7K
9.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
5-2
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Commercial (Cont.)
Part Number
LFXP15C-3F484C
LFXP15C-4F484C
LFXP15C-5F484C
LFXP15C-3F388C
LFXP15C-4F388C
LFXP15C-5F388C
LFXP15C-3F256C
LFXP15C-4F256C
LFXP15C-5F256C
I/Os
300
300
300
268
268
268
188
188
188
Voltage
Grade
-3
Package
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP20C-3F484C
LFXP20C-4F484C
LFXP20C-5F484C
LFXP20C-3F388C
LFXP20C-4F388C
LFXP20C-5F388C
LFXP20C-3F256C
LFXP20C-4F256C
LFXP20C-5F256C
I/Os
340
340
340
268
268
268
188
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP3E-3Q208C
LFXP3E-4Q208C
LFXP3E-5Q208C
LFXP3E-3T144C
LFXP3E-4T144C
LFXP3E-5T144C
LFXP3E-3T100C
LFXP3E-4T100C
LFXP3E-5T100C
I/Os
136
136
136
100
100
100
62
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-5
-3
-4
-5
-3
62
-4
62
-5
5-3
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Commercial (Cont.)
Part Number
LFXP6E-3F256C
LFXP6E-4F256C
LFXP6E-5F256C
LFXP6E-3Q208C
LFXP6E-4Q208C
LFXP6E-5Q208C
LFXP6E-3T144C
LFXP6E-4T144C
LFXP6E-5T144C
I/Os
188
188
188
142
142
142
100
100
100
Voltage
Grade
-3
Package
Pins
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP10E-3F388C
LFXP10E-4F388C
LFXP10E-5F388C
LFXP10E-3F256C
LFXP10E-4F256C
LFXP10E-5F256C
I/Os
244
244
244
188
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
9.7K
9.7K
9.7K
9.7K
9.7K
9.7K
-4
-5
-3
-4
-5
Part Number
LFXP15E-3F484C
LFXP15E-4F484C
LFXP15E-5F484C
LFXP15E-3F388C
LFXP15E-4F388C
LFXP15E-5F388C
LFXP15E-3F256C
LFXP15E-4F256C
LFXP15E-5F256C
I/Os
300
300
300
268
268
268
188
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
-4
-5
-3
-4
-5
-3
-4
-5
5-4
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Commercial (Cont.)
Part Number
LFXP20E-3F484C
LFXP20E-4F484C
LFXP20E-5F484C
LFXP20E-3F388C
LFXP20E-4F388C
LFXP20E-5F388C
LFXP20E-3F256C
LFXP20E-4F256C
LFXP20E-5F256C
I/Os
340
340
340
268
268
268
188
188
188
Voltage
Grade
-3
Package
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-5
-3
-4
-5
-3
-4
-5
Industrial
Part Number
LFXP3C-3Q208I
LFXP3C-4Q208I
LFXP3C-3T144I
LFXP3C-4T144I
LFXP3C-3T100I
LFXP3C-4T100I
I/Os
136
136
100
100
62
Voltage
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
62
-4
Part Number
LFXP6C-3F256I
LFXP6C-4F256I
LFXP6C-3Q208I
LFXP6C-4Q208I
LFXP6C-3T144I
LFXP6C-4T144I
I/Os
188
188
142
142
100
100
Voltage
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
-4
TQFP
Part Number
LFXP10C-3F388I
LFXP10C-4F388I
LFXP10C-3F256I
LFXP10C-4F256I
I/Os
244
244
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
256
256
Temp.
IND
LUTs
9.7K
9.7K
9.7K
9.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
IND
-3
IND
-4
IND
5-5
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Industrial (Cont.)
Part Number
LFXP15C-3F484I
LFXP15C-4F484I
LFXP15C-3F388I
LFXP15C-4F388I
LFXP15C-3F256I
LFXP15C-4F256I
I/Os
300
300
268
268
188
188
Voltage
Grade
-3
Package
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-3
-4
-3
-4
Part Number
LFXP20C-3F484I
LFXP20C-4F484I
LFXP20C-3F388I
LFXP20C-4F388I
LFXP20C-3F256I
LFXP20C-4F256I
I/Os
340
340
268
268
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
-4
Part Number
LFXP3E-3Q208I
LFXP3E-4Q208I
LFXP3E-3T144I
LFXP3E-4T144I
LFXP3E-3T100I
LFXP3E-4T100I
I/Os
136
136
100
100
62
Voltage
1.2V
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
1.2V
-4
1.2V
1.2V
1.2V
1.2V
-3
-4
-3
62
-4
Part Number
LFXP6E-3F256I
LFXP6E-4F256I
LFXP6E-3Q208I
LFXP6E-4Q208I
LFXP6E-3T144I
LFXP6E-4T144I
I/Os
188
188
142
142
100
100
Voltage
1.2V
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.2V
-4
1.2V
-3
1.2V
-4
1.2V
1.2V
-3
-4
TQFP
Part Number
LFXP10E-3F388I
LFXP10E-4F388I
LFXP10E-3F256I
LFXP10E-4F256I
I/Os
244
244
188
188
Voltage
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
256
256
Temp.
IND
LUTs
9.7K
9.7K
9.7K
9.7K
1.2V
-4
IND
1.2V
-3
IND
1.2V
-4
IND
5-6
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Industrial (Cont.)
Part Number
LFXP15E-3F484I
LFXP15E-4F484I
LFXP15E-3F388I
LFXP15E-4F388I
LFXP15E-3F256I
LFXP15E-4F256I
I/Os
300
300
268
268
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-3
-4
-3
-4
Part Number
LFXP20E-3F484I
LFXP20E-4F484I
LFXP20E-3F388I
LFXP20E-4F388I
LFXP20E-3F256I
LFXP20E-4F256I
I/Os
340
340
268
268
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-3
-4
-3
-4
5-7
Ordering Information
Lattice Semiconductor
Lead-free Packaging
LatticeXP Family Data Sheet
Commercial
Part Number
LFXP3C-3QN208C
LFXP3C-4QN208C
LFXP3C-5QN208C
LFXP3C-3TN144C
LFXP3C-4TN144C
LFXP3C-5TN144C
LFXP3C-3TN100C
LFXP3C-4TN100C
LFXP3C-5TN100C
I/Os
136
136
136
100
100
100
62
Voltage
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
62
-4
62
-5
Part Number
LFXP6C-3FN256C
LFXP6C-4FN256C
LFXP6C-5FN256C
LFXP6C-3QN208C
LFXP6C-4QN208C
LFXP6C-5QN208C
LFXP6C-3TN144C
LFXP6C-4TN144C
LFXP6C-5TN144C
I/Os
188
188
188
142
142
142
100
100
100
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP10C-3FN388C
LFXP10C-4FN388C
LFXP10C-5FN388C
LFXP10C-3FN256C
LFXP10C-4FN256C
LFXP10C-5FN256C
I/Os
244
244
244
188
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
9.7K
9.7K
9.7K
9.7K
9.7K
9.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
Part Number
LFXP15C-3FN484C
LFXP15C-4FN484C
LFXP15C-5FN484C
LFXP15C-3FN388C
LFXP15C-4FN388C
LFXP15C-5FN388C
LFXP15C-3FN256C
LFXP15C-4FN256C
LFXP15C-5FN256C
I/Os
300
300
300
268
268
268
188
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-5
-3
-4
-5
-3
-4
-5
5-8
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Commercial (Cont.)
Part Number
LFXP20C-3FN484C
LFXP20C-4FN484C
LFXP20C-5FN484C
LFXP20C-3FN388C
LFXP20C-4FN388C
LFXP20C-5FN388C
LFXP20C-3FN256C
LFXP20C-4FN256C
LFXP20C-5FN256C
I/Os
340
340
340
268
268
268
188
188
188
Voltage
Grade
-3
Package
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP3E-3QN208C
LFXP3E-4QN208C
LFXP3E-5QN208C
LFXP3E-3TN144C
LFXP3E-4TN144C
LFXP3E-5TN144C
LFXP3E-3TN100C
LFXP3E-4TN100C
LFXP3E-5TN100C
I/Os
136
136
136
100
100
100
62
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-5
-3
-4
-5
-3
62
-4
62
-5
Part Number
LFXP6E-3FN256C
LFXP6E-4FN256C
LFXP6E-5FN256C
LFXP6E-3QN208C
LFXP6E-4QN208C
LFXP6E-5QN208C
LFXP6E-3TN144C
LFXP6E-4TN144C
LFXP6E-5TN144C
I/Os
188
188
188
142
142
142
100
100
100
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP10E-3FN388C
LFXP10E-4FN388C
LFXP10E-5FN388C
LFXP10E-3FN256C
LFXP10E-4FN256C
LFXP10E-5FN256C
I/Os
244
244
244
188
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
9.7K
9.7K
9.7K
9.7K
9.7K
9.7K
-4
-5
-3
-4
-5
5-9
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Commercial (Cont.)
Part Number
LFXP15E-3FN484C
LFXP15E-4FN484C
LFXP15E-5FN484C
LFXP15E-3FN388C
LFXP15E-4FN388C
LFXP15E-5FN388C
LFXP15E-3FN256C
LFXP15E-4FN256C
LFXP15E-5FN256C
I/Os
300
300
300
268
268
268
188
188
188
Voltage
Grade
-3
Package
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFXP20E-3FN484C
LFXP20E-4FN484C
LFXP20E-5FN484C
LFXP20E-3FN388C
LFXP20E-4FN388C
LFXP20E-5FN388C
LFXP20E-3FN256C
LFXP20E-4FN256C
LFXP20E-5FN256C
I/Os
340
340
340
268
268
268
188
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
388
388
388
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-5
-3
-4
-5
-3
-4
-5
Industrial
Part Number
LFXP3C-3QN208I
LFXP3C-4QN208I
LFXP3C-3TN144I
LFXP3C-4TN144I
LFXP3C-3TN100I
LFXP3C-4TN100I
I/Os
136
136
100
100
62
Voltage
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
62
-4
Part Number
LFXP6C-3FN256I
LFXP6C-4FN256I
LFXP6C-3QN208I
LFXP6C-4QN208I
LFXP6C-3TN144I
LFXP6C-4TN144I
I/Os
188
188
142
142
100
100
Voltage
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
-4
TQFP
5-10
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Industrial (Cont.)
Part Number
LFXP10C-3FN388I
LFXP10C-4FN388I
LFXP10C-3FN256I
LFXP10C-4FN256I
I/Os
244
244
188
188
Voltage
Grade
-3
Package
Pins
388
388
256
256
Temp.
IND
LUTs
9.7K
9.7K
9.7K
9.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
fpBGA
fpBGA
fpBGA
fpBGA
-4
IND
-3
IND
-4
IND
Part Number
LFXP15C-3FN484I
LFXP15C-4FN484I
LFXP15C-3FN388I
LFXP15C-4FN388I
LFXP15C-3FN256I
LFXP15C-4FN256I
I/Os
300
300
268
268
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
-4
Part Number
LFXP20C-3FN484I
LFXP20C-4FN484I
LFXP20C-3FN388I
LFXP20C-4FN388I
LFXP20C-3FN256I
LFXP20C-4FN256I
I/Os
340
340
268
268
188
188
Voltage
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
1.8/2.5/3.3V
-4
-3
-4
-3
-4
Part Number
LFXP3E-3QN208I
LFXP3E-4QN208I
LFXP3E-3TN144I
LFXP3E-4TN144I
LFXP3E-3TN100I
LFXP3E-4TN100I
I/Os
136
136
100
100
62
Voltage
1.2V
1.2V
1.2V
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-3
1.2V
-4
1.2V
-3
62
1.2V
-4
Part Number
LFXP6E-3FN256I
LFXP6E-4FN256I
LFXP6E-3QN208I
LFXP6E-4QN208I
LFXP6E-3TN144I
LFXP6E-4TN144I
I/Os
188
188
142
142
100
100
Voltage
1.2V
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
LUTs
5.8K
5.8K
5.8K
5.8K
5.8K
5.8K
1.2V
-4
1.2V
1.2V
1.2V
-3
-4
-3
1.2V
-4
TQFP
5-11
Ordering Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Industrial (Cont.)
Part Number
LFXP10E-3FN388I
LFXP10E-4FN388I
LFXP10E-3FN256I
LFXP10E-4FN256I
I/Os
244
244
188
188
Voltage
1.2V
Grade
-3
Package
Pins
388
388
256
256
Temp.
IND
LUTs
9.7K
9.7K
9.7K
9.7K
fpBGA
fpBGA
fpBGA
fpBGA
1.2V
-4
IND
1.2V
-3
IND
1.2V
-4
IND
Part Number
LFXP15E-3FN484I
LFXP15E-4FN484I
LFXP15E-3FN388I
LFXP15E-4FN388I
LFXP15E-3FN256I
LFXP15E-4FN256I
I/Os
300
300
268
268
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
15.5K
15.5K
15.5K
15.5K
15.5K
15.5K
-4
-3
-4
-3
-4
Part Number
LFXP20E-3FN484I
LFXP20E-4FN484I
LFXP20E-3FN388I
LFXP20E-4FN388I
LFXP20E-3FN256I
LFXP20E-4FN256I
I/Os
340
340
268
268
188
188
Voltage
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
388
388
256
256
Temp.
IND
IND
IND
IND
IND
IND
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-3
-4
-3
-4
5-12
LatticeXP Family Data Sheet
Supplemental Information
Data Sheet DS1001
November 2007
For Further Information
A variety of technical notes for the LatticeXP family are available on the Lattice website at www.latticesemi.com.
• LatticeECP/EC and LatticeXP sysIO Usage Guide (TN1056)
• Lattice ispTRACY Usage Guide (TN1054)
• LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide (TN1049)
• Memory Usage Guide for LatticeECP/EC and LatticeXP Devices (TN1051)
• LatticeECP/EC and XP DDR Usage Guide (TN1050)
• Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052)
• LatticeXP sysCONFIG Usage Guide (TN1082)
For further information on interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
DS1001 Further Information_01.3
LatticeXP Family Data Sheet
Revision History
Data Sheet DS1001
November 2007
Revision History
Date
Version
01.0
Section
—
Change Summary
February 2005
April 2005
May 2005
Initial release.
01.1
Architecture
Introduction
Architecture
Pinout Information
Introduction
Architecture
EBR memory support section updated with clarification.
Added TransFR Reconfiguration to Features section.
Added TransFR section.
01.2
June 2005
July 2005
01.3
02.0
Added pinout information for LFXP3, LFXP6, LFXP15 and LFXP20.
Updated XP6, XP15 and XP20 EBR SRAM Bits and Block numbers.
Updated Per Quadrant Primary Clock Selection figure.
Added Typical I/O Behavior During Power-up section.
Updated Device Configuration section under Configuration and Testing.
Clarified Hot Socketing Specification
DC and Switching
Characteristics
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Added Programming and Erase Flash Supply Current table
Added LVDS Emulation section. Updated LVDS25E Output Termination
Example figure and LVDS25E DC Conditions table.
Updated Differential LVPECL diagram and LVPECL DC Conditions
table.
Deleted 5V Tolerant Input Buffer section. Updated RSDS figure and
RSDS DC Conditions table.
Updated sysCONFIG Port Timing Specifications
Updated JTAG Port Timing Specifications. Added Flash Download
Time table.
Pinout Information
Updated Signal Descriptions table.
Updated Logic Signal Connections Dual Function column.
Ordering Information Added lead-free ordering part numbers.
July 2005
02.1
02.2
DC and Switching
Characteristics
Clarification of Flash Programming Junction Temperature
August 2005
Introduction
Architecture
Added Sleep Mode feature.
Added Sleep Mode section.
DC and Switching
Characteristics
Added Sleep Mode Supply Current Table
Added Sleep Mode Timing section
Pinout Information
Added SLEEPN and TOE signal names, descriptions and footnotes.
Added SLEEPN and TOE to pinout information and footnotes.
Added footnote 3 to Logic Signal Connections tables for clarification on
emulated LVDS output.
September 2005
03.0
Architecture
Added clarification of PCI clamp.
Added clarification to SLEEPN Pin Characteristics section.
DC and Switching
Characteristics
DC Characteristics, added footnote 4 for clarification. Updated Supply
Current (Sleep Mode), Supply Current (Standby), Initialization Supply
Current, and Programming and Erase Flash Supply Current typical
numbers.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
Lattice Semiconductor
LatticeXP Family Data Sheet
Date
Version
Section
Change Summary
September 2005
(cont.)
03.0
(cont.)
DC and Switching
Characteristics (cont.)
Updated Typical Building Block Function Performance timing numbers.
Updated External Switching Characteristics timing numbers.
Updated Internal Timing Parameters.
Updated LatticeXP Family timing adders.
Updated LatticeXP "C" Sleep Mode timing numbers.
Updated JTAG Port Timing numbers.
Pinout Information
Added clarification to SLEEPN and TOE description.
Clarification of dedicated LVDS outputs.
Supplemental
Information
Updated list of technical notes.
September 2005
December 2005
03.1
04.0
Pinout Information
Power Supply and NC Connections table corrected VCCP1 pin number
for 208 PQFP.
Introduction
Architecture
Moved data sheet from Advance to Final.
Added clarification to Typical I/O Behavior During Power-up section.
Added clarification to Recommended Operating Conditions.
DC and Switching
Characteristics
Updated timing numbers.
Pinout Information
Updated Signal Descriptions table.
Added clarification to Differential I/O Per Bank.
Updated Differential dedicated LVDS output support.
Ordering Information Added 208 PQFP lead-free package and ordering part numbers.
February 2006
March 2006
04.1
04.2
Pinout Information
Corrected description of Signal Names VREF1(x) and VREF2(x).
Corrected condition for IIL and IIH.
DC and Switching
Characteristics
March 2006
04.3
DC and Switching
Characteristics
Added clarification to Recommended Operating Conditions for
VCCAUX.
April 2006
May 2006
04.4
04.5
Pinout Information
Removed Bank designator "5" from SLEEPN/TOE ball function.
DC and Switching
Characteristics
Added footnote 2 regarding threshold level for PROGRAMN to sysCON-
FIG Port Timing Specifications table.
June 2006
04.6
04.7
DC and Switching
Characteristics
Corrected LVDS25E Output Termination Example.
August 2006
Architecture
Added clarification to Typical I/O Behavior During Power-Up section.
Added clarification to Left and Right sysIO Buffer Pair section.
Changes to LVDS25E Output Termination Example diagram.
DC and Switching
Characteristics
December 2006
February 2007
July 2007
04.8
04.9
05.0
Architecture
Architecture
Introduction
Architecture
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated LatticeXP Family Selection Guide table.
Updated Typical I/O Behavior During Power-up text section.
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics table. Split
out LVCMOS 1.2 by supply voltage.
November 2007
05.1
DC and Switching
Characteristics
Added JTAG Port Timing Waveforms diagram.
Pinout Information
Added Thermal Management text section.
Updated title list.
Supplemental
Information
7-2
Section II. LatticeXP Family Technical Notes
LatticeECP/EC and LatticeXP
sysIO Usage Guide
March 2006
Technical Note TN1056
Introduction
The LatticeECP™, LatticeEC™ and LatticeXP™ sysIO™ buffers give the designer the ability to easily interface
with other devices using advanced system I/O standards. This technical note describes the sysIO standards avail-
able and how they can be implemented using Lattice’s design software.
sysIO Buffer Overview
The LatticeECP/EC and LatticeXP sysIO interfaces contain multiple Programmable I/O Cells (PIC) blocks. In the
case of the LatticeEC and LatticeECP devices, each PIC contains two Programmable I/Os (PIO), PIOA and PIOB,
connected to their respective sysIO buffers. In the LatticeXP device, each PIC also contains two PIOs, PIOA and
PIOB, but every fourth PIC will have only PIOA. Two adjacent PIOs can be joined to provide a differential I/O pair
(labeled as “T” and “C”).
Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeECP/EC and Lattic-
eXP sysIO buffers support a variety of single-ended and differential signaling standards. The sysIO buffer also sup-
ports the DQS strobe signal that is required for interfacing with the DDR memory. One of every 16 PIOs in the
LatticeECP/EC and one of every 14 PIOs in the case of the LatticeXP contains a delay element to facilitate the
generation of DQS signals. The DQS signal from the bus is used to strobe the DDR data from the memory into
input register blocks. For more information on the architecture of the sysIO buffer, please refer to the device data
sheets.
The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more details in Lattice technical note number TN1050, LatticeECP/EC
DDR Usage Guide.
Supported sysIO Standards
The LatticeECP/EC and LatticeXP sysIO buffer supports both single-ended and differential standards. Single-
ended standards can be further subdivided into LVCMOS, LVTTL, PCI and other standards. The buffers support
the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has indi-
vidually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper
latch). Other single-ended standards supported include SSTL and HSTL. Differential standards supported include
LVDS, RSDS, BLVDS, LVPECL, differential SSTL and differential HSTL. Table 8-1 lists the sysIO standards sup-
ported in the Lattice EC/ECP and LatticeXP devices.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
8-1
tn1056_03.3
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Table 8-1. Supported sysIO Standards
VCCIO
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
2.5
2.5
3.3
1.5
1.5
1.8
1.8
2.5
3.3
2.5
2.5
VREF (V)
Standard
LVCMOS 3.3
Min.
3.135
2.375
1.71
Max.
3.465
2.625
1.89
Min.
—
Typ.
—
Max.
—
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
LVTTL
—
—
—
—
—
—
1.425
1.14
1.575
1.26
—
—
—
—
—
—
3.135
3.135
1.71
3.465
3.465
1.89
—
—
—
PCI
—
—
—
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL15 Class III
HSTL 18 Class I, II
HSTL 18 Class III
LVDS
0.833
1.15
1.3
0.68
—
0.9
1.25
1.5
0.75
0.9
0.9
1.08
—
0.969
1.35
1.7
0.9
—
2.375
3.135
1.425
1.425
1.71
2.625
3.465
1.575
1.575
1.89
—
—
1.71
1.89
—
—
2.375
3.135
2.375
2.375
2.625
3.465
2.625
2.625
—
—
LVPECL1
BLVDS1
RSDS1
—
—
—
—
—
—
—
—
—
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
sysIO Banking Scheme
LatticeECP/EC and LatticeXP devices have eight programmable sysIO banks, two per side. Each sysIO bank has
a V supply voltage and two reference voltages, V and V On the top and bottom banks, the sysIO buf-
CCIO
REF1
REF2.
fer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and ref-
erenced). The left and right side sysIO buffer pair along with the two single-ended output and input drivers will also
have a differential driver. The referenced input buffer can also be configured as a differential input. The two pads in
the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differen-
tial input buffer and the comp (complementary) pad is associated with the negative side of the differential input buf-
fer. Figure 8-1 shows the eight banks and their associated supplies.
8-2
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Figure 8-1. sysIO Banking
Bank 0
Bank 1
VCCIO7
VREF1(7)
VREF2(7)
VCCIO2
VREF1(2)
VREF2(2)
GND
GND
VCCIO6
VCCIO3
VREF1(6)
VREF2(6)
VREF1(3)
VREF2(3)
GND
GND
Bank 5
Bank 4
V
(1.2V/1.5V/1.8V/2.5V/3.3V)
CCIO
Each bank has a separate V
supply that powers the single-ended output drivers and the ratioed input buffers
CCIO
such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3, LVCMOS2.5 and LVCMOS1.2 also have fixed threshold
options allowing them to be placed in any bank. The VCCIO voltage applied to the bank determines the ratioed
input standards that can be supported in that bank. It is also used to power the differential output drivers.
V
(3.3V)
CCAUX
In addition to the bank V
supplies, devices have a V core logic power supply, and a V auxiliary supply
CCAUX
CCIO
CC
that powers the differential and referenced input buffers. V
is required because V does not have enough
CCAUX
CC
headroom to satisfy the common-mode range requirements of these drivers and input buffers.
V
(1.2V/1.5V/1.8V/2.5V/3.3V)
CCJ
The JTAG pins have a separate V
power supply that is independent of the bank V
supplies. V
deter-
CCJ
CCIO
CCJ
mines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Input Reference Voltage (V
V
)
REF1, REF2
Each bank can support up to two separate V
input voltages, V
and V
, that are used to set the thresh-
REF2
REF
REF1
old for the referenced input buffers. The location of these V
can be used as regular I/Os if the bank does not require a V
pins is pre-determined within the bank. These pins
voltage.
REF
REF
V
for DDR Memory Interface
REF1
When interfacing to DDR memory, the V
input must be used as the reference voltage for the DQS and DQ
REF1
input from the memory. A voltage divider between V
and GND is used to generate an on-chip reference volt-
REF1
8-3
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
age that is used by the DQS transition detector circuit. This voltage divider is only present on V
it is not avail-
REF1
able on V
For more information on the DQS transition detect logic and its implementation please refer to
REF2.
Lattice technical note number TN1050, LatticeECP/EC DDR Usage Guide.
Mixed Voltage Support in a Bank
The LatticeECP/EC and LatticeXP sysIO buffer is connected to three parallel ratioed input buffers. These three par-
allel buffers are connected to V and to V giving support for thresholds that track with V as well
V
CCIO, CCAUX
CC
CCIO
as fixed thresholds for 3.3V (V
) and 1.2V (V ) inputs. This allows the input threshold for ratioed buffers to be
CCAUX
CC
assigned on a pin-by-pin basis, rather than tracking it with V
This option is available for all 1.2V, 2.5V and 3.3V
CCIO.
ratioed inputs and is independent of the bank V
voltage. For example, if the bank V
is 1.8V, it is possible to
CCIO
CCIO
have 1.2V and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresh-
olds.
Prior to device configuration, the ratioed input thresholds always track the bank V
this option only takes effect
CCIO,
after configuration. Output standards within a bank are always set by V
that the user can mix in the same bank.
Table 8-2 shows the sysIO standards
CCIO.
Table 8-2. Mixed Voltage Support
Input sysIO Standards
Output sysIO Standards
VCCIO
1.2V
1.5V
1.8V
2.5V
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
1.5V
1.8V
2.5V
Yes
Yes
Yes
Yes
Yes
3.3V
Yes
Yes
Yes
Yes
Yes
1.2V
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8-4
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
sysIO Standards Supported in Each Bank
Table 8-3. I/O Standards Supported by Various Banks
Top Side
Banks 0-1
Right Side
Banks 2-3
Bottom Side
Banks 4-5
Left Side
Banks 6-7
Description
Single-ended and Differ-
ential
Single-ended and Differ-
ential
Types of I/O Buffers
Single-ended
Single-ended
LVTTL
LVTTL
LVTTL
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18_I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
Output standards
supported
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I, III,
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
PCI33
PCI33
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS25E1
LVPECL1
BLVDS1
RSDS1
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
PCI Support
PCI33 with clamp
PCI33 no clamp
PCI33 with clamp
PCI no clamp
LVDS Output Buffers
LVDS (3.5mA) Buffers
LVDS (3.5mA) Buffers
1. These differential standards are implemented by using complementary LVCMOS driver with external resistor pack.
LVCMOS Buffer Configurations
All LVCMOS buffers have programmable pull, programmable drive and programmable slew configurations that can
be set in the software.
Programmable Pull-up/Pull-Down/Buskeeper
When configured as LVCMOS or LVTTL, each sysIO buffer has a weak pull-up, a weak pull-down resistor and a
weak buskeeper (bus hold latch) available. Each I/O can independently be configured to have one of these features
or none of them.
Programmable Drive
Each LVCMOS or LVTTL output buffer pin has a programmable drive strength option. This option can be set for
each I/O independently. The drive strength setting available are 2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA.
Actual options available vary by the I/O voltage. The user must consider the maximum allowable current per bank
and the package thermal limit current when selecting the drive strength.
8-5
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
The programmable drive feature also allows the user to match to the impedance of the transmission line.
Table 8-4 shows the drive current setting required to match 50¾ transmission line with 50¾ and 200¾ termina-
tions.
Table 8-4. Impedance Matching Using Programmable Drive Strength
50¾ Transmission
Line Termination
(¾)
I/O Standard
LVCMOS18
LVCMOS33
LVCMOS18
LVCMOS33
Drive Strength (mA)
8
200
12
16
20
50
The actual impedance matching may vary on the transmission line design and the load. To find the best matching,
it is recommended to drive the transmission line with different combinations of I/O standards and drive strengths
that best match the line impedance. Lattice provides IBIS buffer models for the users to further analyze the imped-
ance matching.
The figure below shows how this impedance matching is done for a 50¾ transmission line with 200¾ termination
using LVCMOS18 I/O buffers programmed to drive 16mA, 12mA, 8mA and 4mA. From this experiment it is empiri-
cal that the best matching is achieved with the 8mA drive setting.
Figure 8-2. Impedance Matching for a 50¾ Transmission Line with 200¾ Termination
LVCMOS18 16mA
LVCMOS18 12mA
8-6
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Figure 7-2. Impedance Matching for a 50¾ Transmission Line with 200¾ Termination (Cont.)
LVCMOS18 8mA
LVCMOS18 4mA
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows slew
rate control to be specified on pin-by-pin basis. This slew rate control affects both the rising edges and the falling
edges.
Open Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can imple-
ment an open drain output by turning on the OPENDRAIN attribute in the software.
The software implements open drain in the LatticeECP/EC and LatticeXP devices by connecting the data and
tristate input of the output buffer. Software will implement open drain using this method for simple output buffers. If
the user wants to assign open drain functionality to a bidirectional I/O, a similar implementation is required in the
HDL design. This can be accomplished by combining the equations for the output enable with the output data. The
function of an open drain output is to drive a high Z when the data to the output buffer is driven high and drive a low
when the data to the output buffer is driven low.
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv-
ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn-
chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with off-
chip resistors to emulate LVPECL and BLVDS output drivers.
PCI Support with Programmable PCICLAMP
Each sysIO buffer can be configured to support PCI33. The buffers on the top and bottom of the device have an
optional PCI clamp diode that may optionally be specified in the ispLEVER® design tool.
The programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the
top and bottom banks.
8-7
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
5V Interface with PCI Clamp Diode
All the I/Os on the top and bottom sides of the device (Banks 0, 1, 4, and 5) have a clamp diode that is used to
clamp the voltage at the input to V . This is especially used for PCI I/O standards. This clamp diode can be
CCIO
used along with an external resistor to make an input 5V tolerant.
Figure 8-3. 5V Tolerant Input Buffer
VCCIO
PCI Clamp
Diode
5V Input
External
Resistor
The value of this external resistor will depend on the PCI clamp diode characteristics. You can find the voltage vs.
current data across this diode in the device IBIS model.
In order to interface to 5V input, it is recommended to set the V
between 2.5V to 3.3V.
CCIO
Below is an example for calculating the value of this external resistor when V
is 2.75V.
CCIO
• Maximum voltage at input pin, V
= 3.75V (see device data sheet for more details)
INMAX
• Bank V
= 2.75V
CCIO
• Maximum voltage drop across clamp diode, V = V
- V
= 3.75 - 2.75 =1V
CCIO
D
INMAX
• The current across the clamp diode at V can be found in the power clamp data of the IBIS file. Below is the
D
power clamp portion of the IBIS file for a LVCMOS3.3 input model with PCI Clamp turned on. When V is 1V, the
D
clamp diode current is I = 27.4mA.
D
Table 8-5. Power Clamp Data from IBIS Model
Voltage
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
I (Max.)
72.5
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
61.2
49.9
38.6
27.4
16.9
9.52
5.35
2.31
550.8
58.0
3.61
µA
µA
0.07917
0.0009129
0.0001432
µA
µA
µA
• Assume the maximum output voltage of the driving device is V
then be calculated as follows:
= 5.25V. The value of the external resistor can
EXT
8-8
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
R
= (V
- V
)/I = (5.25V - 3.75V)/27.4 = 54.8 ohm
INMAX D
EXT
EXT
If the V
bank V
of the bank is increased, it will also increase the value of the external resistor required. Changing the
will also change the value of the input threshold voltage.
CCIO
CCIO
Programmable Input Delay
Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the
input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at
zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This
option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This
attribute is described in more detail in the Software sysIO Attributes section. Appendix A shows how this feature
can be enabled in the software using HDL attributes.
Software sysIO Attributes
sysIO attributes can be specified in the HDL, using the Preference Editor GUI or in the ASCII Preference file (.prf)
file directly. Appendices A, B and C list examples of how these can be assigned using each of the methods men-
tioned above. This section describes in detail each of these attributes.
IO_TYPE
This is used to set the sysIO standard for an I/O. The V
required to set these I/O standards are embedded in
CCIO
the attribute names itself. There is no separate attribute to set the V
I/O types.
requirements. Table 8-6 lists the available
CCIO
8-9
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Table 8-6. I/O_TYPE Attribute Values
sysIO Signaling Standard
IO_TYPE
LVCMOS12
DEFAULT (for LatticeECP/EC)
DEFAULT (for LatticeXP)
LVDS 2.5V
LVCMOS25
LVDS25
RSDS
RSDS
Emulated LVDS 2.5V
Bus LVDS 2.5V
LVDS25E1
BLVDS251
LVPECL331
LVPECL 3.3V
HSTL18_I,
HSTL18_II,
HSTL18_III
HSTL18 Class I, II and III
HSTL18D_I
HSTL18D_II
HSTL18D_III
Differential HSTL 18 Class I, II and III
HSTL15_I
HSTL15_III
HSTL 15 Class I and III
HSTL15D_I
HSTL15D_III
Differential HSTL 15 Class I and III
SSTL 33 Class I and II
SSTL33_I,
SSTL33_II
SSTL33D_I
SSTL3D_II
Differential SSTL 33 Class I and II
SSTL 25 Class I and II
SSTL25_I
SSTL25_II
SSTL25D_I
SSTL25D_II
Differential SSTL 25 Class I and II
SSTL 18 Class I
Differential SSTL 18 Class I
LVTTL
SSTL18_I
SSTL18D_I
LVTTL33
3.3V LVCMOS
2.5V LVCMOS
1.8V LVCMOS
1.5V LVCMOS
1.2V LVCMOS
3.3V PCI
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
1. These differential standards are implemented by using complementary
LVCMOS driver with external resistor pack.
OPENDRAIN
LVCMOS and LVTTL I/O standards can be set to Open Drain configuration by using the OPENDRAIN attribute.
Values: ON, OFF
Default: OFF
DRIVE
The drive strength attribute is available for LVTTL and LVCMOS output standards. These can be set or each I/O pin
individually.
8-10
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Values: NA, 2, 4, 8, 12, 16, 20
LatticeECP/EC Default: 6
LatticeXP Default: 8
The programmable drive available on a pad will depend on the V
Table 8-7 shows the drive strength available
CCIO.
for different V
CCIO.
Table 8-7. Programmable Drive Strength Values at Various V
Voltages
CCIO
VCCIO
1.8 V
Drive
2
1.2 V
1.5 V
X
2.5 V
3.3 V
X
4
X
X
X
6
X
8
X
X
X
X
X
X
X
X
X
X
X
X
12
16
20
PULLMODE
The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs. This attribute can be
enabled for each I/O independently.
Values: UP, DOWN, NONE, KEEPER
Default: UP
PCICLAMP
PCI33 inputs and outputs on the top and bottom of the device have an optional PCI clamp that is enabled via the
PCICLAMP attribute. The PCICLAMP is also available for all LVCMOS33 and LVTTL inputs and outputs.
Values: ON, OFF
Default: OFF
SLEWRATE
The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual
slew rate control. This allows the designer to specify the slew rate control on a pin-by-pin basis.
Values: FAST, SLOW
Default: FAST
FIXEDDELAY
The FIXEDDELAY attribute is available to each input pin. When enabled, this attribute is used to achieve zero hold
time for the input registers when using global clock.
Values: TRUE, FALSE
Default: FALSE
DIN/DOUT
This attribute can be used when I/O registers need to be assigned. Using DIN will assert an input register and
using the DOUT attribute will assert an output register in the design. By default the software will try to assign the
I/O registers if applicable. The user can turn this OFF by using the synthesis attribute or using the preference editor
of the software. These attributes can only be applied on registers.
8-11
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attribute is only used when
the pin assignments are made in HDL source. Pins assignments can be made directly using the GUI in the Prefer-
ence Editor of the software. The appendices explain this in more detail.
Design Considerations and Usage
This section discusses some of design rules and considerations that need to be taken into account when designing
with the LatticeECP/ECP and LatticeXP sysIO buffer.
Banking Rules
• If V
or V
for any bank is set to 3.3V, it is recommended that it be connected to the same power sup-
CCJ
CCIO
ply as V
thus minimizing leakage.
CCAUX,
• If V
or V
for any bank is set to 1.2V, it is recommended that it be connected to the same power sup-
CCJ
CCIO
ply as V
thus minimizing leakage.
CC,
• When implementing DDR memory interfaces, the V
of the bank is used to provide reference to the
REF1
interface pins and cannot be used to power any other referenced inputs.
• Only the top and bottom banks (Banks 0, 1, 4, and 5) will support PCI clamps. The left and right side (Banks
2, 3, 6 and 7) do not support PCI Clamp, but will support True LVDS output.
Differential I/O Rules
• All the banks can support LVDS input buffers. Only the banks on the right and left side (Banks 2, 3, 6 and 7)
will support True Differential output buffers. The banks on the top and bottom will support the LVDS input
buffers but will not support True LVDS outputs. The user can use emulated LVDS output buffers on these
banks.
• All banks support emulated differential buffers using external resistor pack and complementary LVCMOS
drivers.
• In LatticeXP devices, not all PIOs have LVDS capability. Only four out of every seven I/Os can provide LVDS
buffer capability. In LatticeECP/EC devices, there are no restrictions on the number of I/Os that can support
LVDS. In both cases LVDS can only be assigned to the TRUE pad. Refer to the device data sheets to see
the pin listing for all the LVDS pairs.
Assigning V
/ V
Groups for Referenced Inputs
REF
REF
Each bank has two dedicated V
input pins, V
and V
Buffers can be grouped to a particular V
rail,
REF
REF1
REF2.
REF
V
or V
This grouping is done by assigning a PGROUP VREF preference along with the LOCATE
REF1
REF2.
PGROUP preference.
Preference Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example of VREF Groups
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)”
COMP “ah(4)” COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)”
COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
LOCATE VREF “ref2” SITE PR48B;
8-12
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
or
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
The second example show V
groups, “vref_pg1” assigned to V
“ref1” and “vref_pg2” assigned to “ref2”.
REF
REF
V
must then be locked to either V
or V
using LOCATE preference. Or, the user can simply designate to
REF
REF1
REF2
which bank V
bank.
group should be located. The software will then assign these to either V
or V
of the
REF2
REF
REF1
If the PGROUP VREF is not used, the software will automatically group all pins that need the same V
reference
REF
voltage. This preference is most useful when there is more than one bus using the same reference voltage and the
user wants to associate each of these buses to different V
resources.
REF
Differential I/O Implementation
The LatticeECP/EC and LatticeXP devices support a variety of differential standards as detailed in the following
section.
LVDS
True LVDS (LVDS25) drivers are available on the left and right side of the devices. LVDS input support is provided
on all sides of the device. All four sides support LVDS using complementary LVCMOS drivers with external resis-
tors (LVDS25E).
Please refer to the LatticeECP/EC and LatticeXP data sheets for a more detailed explanation of these LVDS imple-
mentations.
BLVDS
All single-ended sysIO buffer pairs in the LatticeECP family support the Bus-LVDS standard using complementary
LVCMOS drivers with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets to learn more about BLVDS implementation.
RSDS
All single-ended sysIO buffers pairs in the LatticeECP family support the RSDS standard using complementary
LVCMOS drivers with external resistors. This mode uses LVDS25E with an alternative resistor pack.
Please refer to the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of RSDS implementation.
LVPECL
All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using a complementary LVCMOS
driver with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets for further information on LVPECL implementation.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs in the LatticeECP family support differential SSTL and HSTL. Please refer to
the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of Differential HSTL and SSTL implemen-
tation.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
8-13
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Internet: www.latticesemi.com
8-14
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Appendix A. HDL Attributes for Synplify® and Precision® RTL Synthesis
Using these HDL attributes, you can assign sysIO attributes directly in your source. You will need to use the attri-
bute definition and syntax for the synthesis vendor you are planning to use. Below are a list of all the sysIO attri-
butes syntax and examples for Precision RTL Synthesis and Synplify. This section only lists the sysIO buffer
attributes for these devices. You can refer to the Precision RTL Synthesis and Synplify user manuals for a complete
list of synthesis attributes. These manuals are available through ispLEVER Software Help.
VHDL Synplify/Precision RTL Synthesis
This section lists syntax and examples for all the sysIO attributes in VHDL when using Precision RTL Synthesis or
Synplicity synthesis tools.
Syntax
Table 8-8. VHDL Attribute Syntax for Synplify and Precision RTL Synthesis
Attribute
IO_TYPE
Syntax
attribute IO_TYPE: string;
attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”;
attribute OPENDRAIN: string;
attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”;
OPENDRAIN
DRIVE
attribute DRIVE: string;
attribute DRIVE of Pinname: signal is “Drive Value”;
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Pullmode Value”;
PULLMODE
PCICLAMP
SLEWRATE
FIXEDDELAY
attribute PCICLAMP: string;
attribute PCICLAMP of Pinname: signal is “PCIClamp Value”;
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Slewrate Value”;
attribute FIXEDDELAY: string;
attribute FIXEDDELAY of Pinname: signal is “Fixeddelay Value”;
DIN
attribute DIN: string; attribute DIN of Pinname: signal is “ ”;
DOUT
LOC
attribute DOUT: string; attribute DOUT of Pinname: signal is “ ”;
attribute LOC: string; attribute LOC of Pinname: signal is “pin_locations”;
Examples
IO_TYPE
--***Attribute Declaration***
ATTRIBUTE IO_TYPE: string;
--***IO_TYPE assignment for I/O Pin***
ATTRIBUTE IO_TYPE OF portA: SIGNAL IS “PCI33”;
ATTRIBUTE IO_TYPE OF portB: SIGNAL IS “LVCMOS33”;
ATTRIBUTE IO_TYPE OF portC: SIGNAL IS “LVDS25”;
8-15
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
OPENDRAIN
--***Attribute Declaration***
ATTRIBUTE OPENDRAIN: string;
--***DRIVE assignment for I/O Pin***
ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS "ON";
DRIVE
--***Attribute Declaration***
ATTRIBUTE DRIVE: string;
--***DRIVE assignment for I/O Pin***
ATTRIBUTE DRIVE OF portB: SIGNAL IS “20”;
PULLMODE
--***Attribute Declaration***
ATTRIBUTE PULLMODE : string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PULLMODE OF portA: SIGNAL IS "DOWN";
ATTRIBUTE PULLMODE OF portB: SIGNAL IS "UP";
PCICLAMP
--***Attribute Declaration***
ATTRIBUTE PCICLAMP: string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PCICLAMP OF portA: SIGNAL IS "ON";
SLEWRATE
--***Attribute Declaration***
ATTRIBUTE SLEWRATE : string;
--*** SLEWRATE assignment for I/O Pin***
ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”;
FIXEDDELAY
--***Attribute Declaration***
ATTRIBUTE FIXEDDELAY: string;
--*** SLEWRATE assignment for I/O Pin***
ATTRIBUTE FIXEDDELAY OF portB: SIGNAL IS “TRUE”;
8-16
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
DIN/DOUT
--***Attribute Declaration***
ATTRIBUTE din : string;
ATTRIBUTE dout : string;
--*** din/dout assignment for I/O Pin***
ATTRIBUTE din OF input_vector: SIGNAL IS “ “;
ATTRIBUTE dout OF output_vector: SIGNAL IS “ “;
LOC
--***Attribute Declaration***
ATTRIBUTE LOC : string;
--*** LOC assignment for I/O Pin***
ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “;
8-17
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Verilog for Synplify
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplify synthesis tool.
Syntax
Table 8-9. Verilog Synplify Attribute Syntax
Attribute
IO_TYPE
Syntax
PinType PinName /* synthesis IO_TYPE=”IO_Type Value”*/;
PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/;
PinType PinName /* synthesis DRIVE=”Drive Value”*/;
PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/;
PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/;
PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/;
PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/;
PinType PinName /* synthesis DIN=” “*/;
OPENDRAIN
DRIVE
PULLMODE
PCICLAMP
SLEWRATE
FIXEDDELAY
DIN
DOUT
PinType PinName /* synthesis DOUT=” “*/;
LOC
PinType PinName /* synthesis LOC=”pin_locations “*/;
Examples
//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment
output portB /*synthesis IO_TYPE="LVCMOS33" PULLMODE =”UP” SLEWRATE =”FAST”
DRIVE =”20”*/;
output portC /*synthesis IO_TYPE="LVDS25" */;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//PCICLAMP
output portA /*synthesis IO_TYPE="PCI33" PULLMODE =”PCICLAMP”*/;
// Fixeddelay
input load /* synthesis FIXEDDELAY="TRUE" */;
// Place the flip-flops near the load input
input load /* synthesis din=”” */;
// Place the flip-flops near the outload output
output outload /* synthesis dout=”” */;
8-18
LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
//I/O pin location
input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/;
//Register pin location
reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */;
//Vectored internal bus
reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */;
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LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Verilog for Precision RTL Synthesis
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Precision RTL Synthesis syn-
thesis tool.
Syntax
Table 8-10. Verilog Precision RTL Synthesis Attribute Syntax
ATTRIBUTE
IO_TYPE
SYNTAX
//pragma attribute PinName IO_TYPE IO_TYPE Value
//pragma attribute PinName OPENDRAIN OpenDrain Value
//pragma attribute PinName DRIVE Drive Value
//pragma attribute PinName IO_TYPE Pullmode Value
//pragma attribute PinName PCICLAMP PCIClamp Value
//pragma attribute PinName IO_TYPE Slewrate Value
//pragma attribute PinName IO_TYPE Fixeddelay Value
//pragma attribute PinName LOC pin_location
OPENDRAIN
DRIVE
PULLMODE
PCICLAMP
SLEWRATE
FIXEDDELAY
LOC
Example
//****IO_TYPE ***
//pragma attribute portA IO_TYPE PCI33
//pragma attribute portB IO_TYPE LVCMOS33
//pragma attribute portC IO_TYPE SSTL25_II
//*** Opendrain ***
//pragma attribute portB OPENDRAIN ON
//pragma attribute portD OPENDRAIN OFF
//*** Drive ***
//pragma attribute portB DRIVE 20
//pragma attribute portD DRIVE 8
//*** Pullmode***
//pragma attribute portB PULLMODE UP
//*** PCIClamp***
//pragma attribute portB PCICLAMP ON
//*** Slewrate ***
//pragma attribute portB SLEWRATE FAST
//pragma attribute portD SLEWRATE SLOW
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sysIO Usage Guide
Lattice Semiconductor
// ***Fixeddelay***
// pragma attribute load FIXEDDELAY TRUE
//***LOC***
//pragma attribute portB loc E3
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LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Appendix B. sysIO Attributes Using Preference Editor User Interface
You can also assign the sysIO buffer attributes using the Pre Map Preference Editor GUI available in the ispLEVER
tools. The Pin Attribute Sheet list all the ports in your design and all the available sysIO attributes as preferences.
Clicking on each of these cells will produce a list of all the valid I/O preference for that port. Each column takes pre-
cedence over the next. Hence, when a particular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE
columns will only list the valid combinations for that IO_TYPE. The user can lock the pin locations using the pin
location column of the Pin Attribute sheet. Right-clicking on a cell will list all the available pin locations. The Prefer-
ence Editor will also conduct a DRC check to look for incorrect pin assignments.
You can enter the DIN/ DOUT preferences using the Cell Attributes Sheet of the Preference Editor. All the prefer-
ences assigned using the Preference Editor are written into the logical preference file (.lpf).
Figure 8-4 and Figure 8-5 show the Pin Attribute Sheet and the Cell Attribute Sheet views of the Preference Editor.
For further information on how to use the Preference Editor, refer to the ispLEVER Help documentation located in
the Help menu option of the software.
Figure 8-4. Pin Attributes Tab
Figure 8-5. Cell Attributes Tab
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LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
Appendix C. sysIO Attributes Using Preference File (ASCII File)
You can also enter the sysIO attributes directly in the preference (.prf) file as sysIO buffer preferences. The PRF file
is an ASCII file containing two sections: a schematic section for preferences created by the Mapper or translator,
and a user section for preferences entered by the user. You can write user preferences directly into this file. The
synthesis attributes appear between the schematic start and schematic end of the file. You can enter the sysIO buf-
fer preferences after the schematic end line using the preference file syntax. Below are a list of sysIO buffer prefer-
ence syntax and examples.
IOBUF
This preference is used to assign the attribute IO_TYPE, PULLMODE, SLEWRATE and DRIVE.
Syntax
IOBUF [ALLPORTS | PORT <port_name> | GROUP <group_name>] (keyword=<value>)+;
where:
<port_name> = These are not the actual top-level port names, but should be the signal name attached to the port.
PIOs in the physical design (.ncd) file are named using this convention. Any multiple listings or wildcarding should
be done using GROUPs
Keyword = IO_TYPE, OPENDRAIN, DRIVE, PULLMODE, PCICLAMP, SLEWRATE.
Example
IOBUF PORT "port1" IO_TYPE=LVTTL33 OPENDRAIN=ON DRIVE=8 PULLMODE=UP
PCICLAMP =OFF SLEWRATE=FAST;
DEFINE GROUP "bank1" "in*" "out_[0-31]";
IOBUF GROUP "bank1" IO_TYPE=SSTL18_II;
LOCATE
When this preference is applied to a specified component it places the component at a specified site and locks the
component to the site. If applied to a specified macro instance it places the macro’s reference component at a
specified site, places all of the macro’s pre-placed components (that is, all components that were placed in the
macro’s library file) in sites relative to the reference component, and locks all of these placed components at their
sites. This can also be applied to a specified PGROUP.
Syntax
LOCATE [COMP <comp_name> | MACRO <macro_name>] SITE <site_name>;
LOCATE PGROUP <pgroup_name> [SITE <site_name>; | REGION <region_name>;]
LOCATE PGROUP <pgroup_name> RANGE <site_1> [<site_2> | <count>] [<direction>] | RANGE <chip_side>
[<direction>];
LOCATE BUS < bus_name> ROW|COL <number>;
<bus_name> := string
<number> := integer
Note: If the comp_name, macro_name, or site_name begins with anything other than an alpha character (for exam-
ple, “11C7”), you must enclose the name in quotes. Wildcard expressions are allowed in <comp_name>.
Example
This command places the port Clk0 on the site A4:
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LatticeECP/EC and LatticeXP
sysIO Usage Guide
Lattice Semiconductor
LOCATE COMP “Clk0” SITE “A4”;
This command places the component PFU1 on the site named R1C7:
LOCATE COMP “PFU1” SITE “R1C7”;
This command places bus1 on ROW 3 and bus2 on COL4
LOCATE BUS “bus1” ROW 3;
LOCATE BUS “bus2” COL 4;
USE DIN CELL
This preference specifies the given register to be used as an input Flip Flop.
Syntax
USE DIN CELL <cell_name>;
where:
<cell_name> := string
Example
USE DIN CELL “din0”;
USE DOUT CELL
Specifies the given register to be used as an output Flip Flop.
Syntax
USE DOUT CELL <cell_name>;
where:
<cell_name> := string
Examples
USE DOUT CELL “dout1”;
PGROUP VREF
This preference is used to group all the components that need to be associated to one VREF pin within a bank.
Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)” COMP “ah(4)”
COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)” COMP “al(4)” COMP
“al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
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sysIO Usage Guide
Lattice Semiconductor
LOCATE VREF “ref2” SITE PR48B;
or
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
8-25
Memory Usage Guide for
LatticeECP/EC and LatticeXP Devices
October 2006
Technical Note TN1051
Introduction
This technical note discusses memory usage in the LatticeEC™, LatticeECP™ and LatticeXP™ device families. It
is intended to be used as a guide for integrating the EBR and PFU based memories for these device families using
the ispLEVER® design tool.
The architecture of the LatticeECP/EC and LatticeXP devices provides a large amount of resources for memory
intensive applications. The sysMEM™ Embedded Block RAM (EBR) complements its distributed PFU-based mem-
ory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM and ROM memories can be constructed using the
EBR. LUTs and PFU can implement Distributed Single-Port RAM, Dual-Port RAM and ROM. The internal logic of
the device can be used to configure the memory elements as FIFO and other storage types.
The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and described later in this doc-
ument. Designers can generate the memory primitives using the IPexpress™ tool in the ispLEVER software. The
IPexpress GUI allows users to specify the memory type and size required. IPexpress takes this specification and
constructs a netlist to implement the desired memory by using one or more of the memory primitives.
The remainder of this document discusses how to utilize IPexpress, memory modules and memory primitives.
Memories in LatticeECP/EC and LatticeXP Devices
The LatticeECP/EC and LatticeXP architectures contain an array of logic blocks called PFUs or PFFs surrounded
by Programmable I/O Cells (PICs). Interspersed between the rows of logic blocks are rows of sysMEM Embedded
Block RAM (EBR) as shown in Figures 9-1, 9-2 and 9-3.
The PFU contains the building blocks for logic, and Distributed RAM and ROM. The PFF provides the logic building
blocks without the distributed RAM
This document describes the memory usage and implementation for both embedded memory blocks (EBR) and
distributed RAM of the PFU. Refer to the device data sheet for details on the hardware implementation of the EBR
and Distributed RAM.
The logic blocks are arranged in a two-dimensional grid with rows and columns as shown in the figures below. The
physical location of the EBR and Distributed RAM follows the row and column designation. The Distributed RAM,
since it is part of the PFU resource, follows the PFU/PFF row and column designation. The EBR occupies two col-
umns per block to account for the wider port interface.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
9-1
tn1051_01.8
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-1. Simplified Block Diagram, LatticeEC Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (Fast PFU
without RAM/ROM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
Figure 9-2. Simplified Block Diagram, LatticeECP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (Fast PFU
without RAM/ROM)
sysDSP Block
sysCLOCK PLL
Programmable
Functional Unit (PFU)
9-2
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-3. Simplified Block Diagram, LatticeXP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
Non-volatile Memory
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
Utilizing IPexpress
Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules will be con-
structed using one or more memory primitives along with general purpose routing and LUTs as required. The avail-
able modules are:
• Single Port RAM (RAM_DQ) – EBR based
• Dual PORT RAM (RAM_DP_TRUE) – EBR based
• Pseudo Dual Port RAM (RAM_DP) – EBR based
• Read Only Memory (ROM) – EBR Based
• First In First Out Memory (FIFO and FIFO_DC) – EBR Based
• Distributed Single Port RAM (Distributed_SPRAM) – PFU based
• Distributed Dual Port RAM (Distributed_DPRAM) – PFU based
• Distributed ROM (Distributed_ROM) – PFU/PFF based
IPexpress Flow
For generating any of these memories, create (or open) a project for the LatticeECP/EC or LatticeXP devices.
From the Project Navigator, select Tools > IPexpress. Alternatively, users can also click on the button in the tool-
bar when the LatticeECP/EC and LatticeXP devices are targeted in the project.
This opens the IPexpress window as shown in Figure 9-4.
9-3
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-4. IPexpress - Main Window
The left pane of this window has the Module Tree. The EBR-based Memory Modules are under the Module >
Memory- Module > Distributed RAM and EBR_Components and the PFU-based Distributed Memory Modules
are under Storage_Components as shown in Figure 9-4.
Let us look at an example of the generating an EBR-based Pseudo Dual Port RAM of size 512 x 16. Select
RAM_DP under the EBR_Components. The right pane changes, as shown in Figure 9-5.
9-4
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-5. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress
In the right-hand pane, options like Macro Type, Version, and Module_Name are device and selected module
dependent. These cannot be changed in IPexpress.
Users can change the directory where the generated module files will be placed by clicking the browse button in
the Project Path.
The File Name text box allows users to specify the entity and file name for the module they are about to generate.
Users must provide this name.
Design Entry, Verilog or VHDL, by default is the same as the project type. If the project is a VHDL project, the
selected Design Entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
Then click the Customize button. This opens another window where the RAM can be customized.
The the left-hand side of this window shows the block diagram of the module. The right-hand side includes the
Configuration tab.
9-5
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-6. Generating Pseudo Dual Port RAM (RAM_DP) Module Customization – Configuration Tab
Users can specify the Address Depth and Data width for the Read Port and the Write Port in the text boxes pro-
vided. In this example we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs of
different port widths in the case of Pseudo Dual Port and True Dual Port RAMs.
The check box Enable Output Registers inserts the output registers in the Read Data Port, as the output registers
are optional for the EBR-based RAMs.
The Reset Mode can be selected to be Asynchronous Reset or Synchronous Reset. GSR or Global Set Reset can
be checked to be Enabled or Disabled.
The Input Data and the Address Control is always registered, as the hardware only supports synchronous opera-
tion for the EBR based RAMs
Users can also pre-initialize their memory with the contents they specify in the Memory file. It is optional to provide
this file in the RAMs. However, in the case of ROM, it is required to provide the Memory file. These files can be of
Binary, Hex or Addresses Hex format. The details of these formats are discussed in the Initialization File section of
this technical note.
At this point, users can click the Generate button to generate the module that they have customized. A netlist in the
desired format is then generated and placed in the specified location. Users can incorporate this netlist in their
designs.
Users can check the Import LPC to ispLEVER project check box to automatically import the file in the Project Nav-
igator.
Once the Module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in the top level
module of their design.
The various memory modules, both EBR and Distributed, are discussed in detail later in this document.
9-6
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Memory Modules
Single Port RAM (RAM_DQ) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Single Port RAM or RAM_DQ.
IPexpress allows users to generate the Verilog-HDL or VHDL along an EDIF netlist for the memory size as per the
design requirements.
IPexpress generates the memory module as shown in Figure 9-7.
Figure 9-7. Single Port Memory Module generated by IPexpress
Clock
ClockEn
RAM_DQ
Reset
WE
Q
EBR-based Single Port
Memory
Address
Data
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks or primitives
and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes
smaller than an EBR block, the module will be created in one EBR block. In cases where the specified memory is
larger than one EBR block, multiple EBR block can be cascaded, in depth or width (as required to create these
sizes).
The memory primitive for RAM_DQ for LatticeECP/EC and LatticeXP devices is shown in Figure 9-8.
Figure 9-8. Single Port RAM Primitive or RAM_DQ for LatticeECP/EC and LatticeXP Devices
AD[x:0]
DI[y:0]
CLK
CE
DO[y:0]
EBR
RST
WE
CS[2:0]
In Single Port RAM mode the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered.
9-7
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The various ports and their definitions for the Single Port Memory are included in Table 9-1. The table lists the cor-
responding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.
Table 9-1. EBR-based Single Port Memory Port Definitions
Port Name in
Generated Module
Port Name in the
EBR Block Primitive
Description
Active State
Clock
CLK
Clock
Rising Clock Edge
ClockEn
Address
Data
Q
CE
Clock Enable
Address Bus
Data In
Active High
AD[x:0]
DI[y:0]
DO[y:0]
WE
—
—
Data Out
—
WE
Write Enable
Reset
Active High
Active High
—
Reset
—
RST
CS[2:0]
Chip Select
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can easily cascade eight memories. If the memory size specified by the user requires more than eight
EBR blocks, the software automatically generates the additional address decoding logic which is implemented in
the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-2.
Table 9-2. Single Port Memory Sizes for 9K Memories for LatticeECP/EC Devices
Single Port
Memory Size
Input Data
DI
Output Data
DO
Address [MSB:LSB]
AD[12:0]
8K x 1
4K x 2
DI[1:0]
DI[3:0]
DI[8:0]
DI[17:0]
DI[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO[17:0]
DO[35:0]
AD[11:0]
2K x 4
AD[10:0]
1K x 9
AD[9:0]
512 x 18
256 x 36
AD[8:0]
AD[7:0]
Table 9-3 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Table 9-3. Single Port RAM Attributes for LatticeECP/EC Devices
User Selectable
Through
Attribute
DATA_WIDTH Data Word Width
REGMODE Register Mode (Pipelining) NOREG, OUTREG
RESETMODE Selects the Reset type
Description
Values
Default Value
IPexpress
1, 2, 4, 9, 18, 36
1
YES
NOREG
ASYNC
YES
ASYNC, SYNC
YES
000, 001, 010, 011, 100, 101, 110,
111
CSDECODE Chip Select Decode
000
NO
NORMAL, WRITETHROUGH,
WRITEMODE Read / Write Mode
GSR Global Set Reset
NORMAL
ENABLED
YES
YES
READBEFOREWRITE
ENABLED, DISABLED
9-8
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The Single Port RAM (RAM_DQ) can be configured as NORMAL, READ BEFORE WRITE or WRITE THROUGH
modes. Each of these modes affects what data comes out of the port Q of the memory during the write operation
followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is supported for
x9, x18 and x36 data widths.
Additionally users can select to enable the output registers for RAM_DQ. Figures 8-7 through 8-12 show the inter-
nal timing waveforms for the Single Port RAM (RAM_DQ) with these options.
Figure 9-9. Single Port RAM Timing Waveform – NORMAL Mode, without Output Registers
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
WrEn
Address
Data
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_1
Add_0
Add_0
Add_1
Add_2
Data_0
Data_1
tHDATA_EBR
Invalid Data
tSUDATA_EBR
Q
Data_0
Data_1
Data_2
tCO_EBR
9-9
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-10. Single Port RAM Timing Waveform – NORMAL Mode, with Output Registers
Reset
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
tSUWREN_EBR
tHWREN_EBR
WrEn
tSUADDR_EBR
tHADDR_EBR
Add_1
Address
Data
Q
Add_0
Add_0
Add_1
Add_2
Data_0
Data_1
tHDATA_EBR
Invalid Data
tSUDATA_EBR
Data_0
tCOO_EBR
Data_1
Figure 9-11. Single Port RAM Timing Waveform – READ BEFORE WRITE Mode, without Output Registers
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
WrEn
Address
Data
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_0
Add_0
Add_1
Add_1
Add_2
New
Data_0
New
Data_1
tSUDATA_EBR
tHDATA_EBR
Old_Data_0
Q
Invalid Data
New_Data_0
tCO_EBR
Old_Data_1
New_Data_1
9-10
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-12. Single Port RAM Timing Waveform – READ BEFORE WRITE Mode, with Output Registers
Reset
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
WrEn
Address
Data
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_0
Add_0
Add_1
Add_1
Add_2
New
Data_0
New
Data_1
tSUDATA_EBR
tHDATA_EBR
New
Data_1
Q
Invalid Data
Old_Data_0
New_Data_0
tCOO_EBR
Old_Data_1
Figure 9-13. Single Port RAM Timing Waveform – WRITE THROUGH Mode, without Output Registers
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
WrEn
Address
Data
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_1
Add_0
Add_0
Data_0
Data_1
tHDATA_EBR
Data_0
Data_2
Data_1
Data_3
Data_2
Data_4
Data_3
tSUDATA_EBR
Q
Invalid Data
Data_4
tCO_EBR
9-11
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-14. Single Port RAM Timing Waveform – WRITE THROUGH Mode, with Output Registers
Reset
Clock
tSUCE_EBR
tHCE_EBR
ClockEn
WrEn
Address
Data
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_1
Add_0
Add_0
Data_0
Data_1
tHDATA_EBR
Data_2
Data_0
Data_3
Data_4
Data_2
tSUDATA_EBR
Q
Invalid Data
Data_1
Data_3
tCOO_EBR
9-12
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
True Dual Port RAM (RAM_DP_TRUE) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as True-Dual Port RAM or
RAM_DP_TRUE. IPexpress allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size
as per design requirements.
IPexpress generates the memory module as shown in Figure 9-15.
Figure 9-15. True Dual Port Memory Module Generated by IPexpress
ClockA
ClockEnA
ResetA
WEA
ClockB
ClockEnB
ResetB
WEB
RAM_DP_TRUE
EBR-based True
Dual Port Memory
WrAddressA
DataA
WrAddressB
DataB
QA
QB
The generated module makes use of the RAM_DP_TRUE primitive. For memory sizes smaller than one EBR
block, the module will be created in one EBR block. In cases where the specified memory is larger than one EBR
block, multiple EBR blocks can be cascaded, in depth or width (as required to create these sizes).
The basic memory primitive for the LatticeECP/EC and LatticeXP devices, RAM_DP_TRUE, is shown in Figure 9-
16.
Figure 9-16. True Dual Port RAM Primitive or RAM_DP_TRUE for LatticeECP/EC and LatticeXP Devices
ADA[x:0]
ADB[x:0]
DIA[y:0]
CLKA
CEA
DIB[y:0]
CLKB
CEB
EBR
RSTA
RSTB
WEA
CSA[2:0]
DOA[y:0]
WEB
CSB[2:0]
DOB[y:0]
In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
9-13
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The various ports and their definitions for the True Dual Memory are included in Table 9-4. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive.
Table 9-4. EBR-based True Dual Port Memory Port Definitions
Port Name in
Generated Module
Port Name in the EBR
Block Primitive
Description
Clock for PortA and PortB
Active State
ClockA, ClockB
ClockEnA, ClockEnB
AddressA, AddressB
DataA, DataB
QA, QB
CLKA, CLKB
Rising Clock Edge
CEA, CEB
Clock Enables for Port CLKA and CLKB
Address Bus Port A and Port B
Input Data Port A and Port B
Output Data Port A and Port B
Write Enable Port A and Port B
Reset for Port A and Port B
Chip Selects for Each Port
Active High
ADA[x:0], ADB[x:0]
DIA[y:0], DIB[y:0]
DOA[y:0], DOB[y:0]
WEA, WEB
—
—
—
WEA, WEB
Active High
Active High
—
ResetA, ResetB
—
RSTA, RSTB
CSA[2:0], CSB[2:0]
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal would form the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-
bit bus, so it can easily cascade eight memories. However, if the memory size specified by the user requires more
than eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU external to the EBR blocks.
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-5.
Table 9-5. True Dual Port Memory Sizes for 9K Memory for LatticeECP/EC and LatticeXP Devices
Dual Port
Memory Size
Input Data
Port A
Input Data
Port B
Output Data
Port A
Output Data
Port B
Address Port A Address Port B
[MSB:LSB]
ADA[12:0]
ADA[11:0]
ADA[10:0]
ADA[9:0]
[MSB:LSB]
ADB[12:0]
ADB[11:0]
ADB[10:0]
ADB[9:0]
8K x 1
4K x 2
DIA
DIB
DOA
DOB
DIA[1:0]
DIA[3:0]
DIA[8:0]
DIA[17:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
DIB[17:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
DOA[17:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
DOB[17:0]
2K x 4
1K x 9
512 x 18
ADA[8:0]
ADB[8:0]
Table 9-6 shows the various attributes available for True Dual Port Memory (RAM_DP_TRUE). Some of these attri-
butes are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
9-14
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Table 9-6. True Dual Port RAM Attributes for LatticeECP/EC and LatticeXP
User Selectable
Through
Default
Value
Attribute
Description
Values
1, 2, 4, 9, 18
1, 2, 4, 9, 18
IPexpress
DATA_WIDTH_A Data Word Width Port A
DATA_WIDTH_B Data Word Width Port B
1
YES
YES
YES
YES
YES
1
REGMODE_A
REGMODE_B
RESETMODE
Register Mode (Pipelining) for Port A NOREG, OUTREG
Register Mode (Pipelining) for Port B NOREG, OUTREG
NOREG
NOREG
ASYNC
Selects the Reset type
ASYNC, SYNC
000, 001, 010, 011, 100, 101,
110, 111
CSDECODE_A
CSDECODE_B
Chip Select Decode for Port A
000
000
NO
NO
000, 001, 010, 011, 100, 101,
110, 111
Chip Select Decode for Port B
NORMAL,WRITETHROUGH,
READBEFOREWRITE
WRITEMODE_A Read / Write Mode for Port A
WRITEMODE_B Read / Write Mode for Port B
NORMAL
YES
NORMAL,WRITETHROUGH,
READBEFOREWRITE
NORMAL
ENABLED
YES
YES
GSR
Global Set Reset
ENABLED, DISABLED
The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL, READ BEFORE WRITE or WRITE
THROUGH modes. Each of these modes affects what data comes out of the port Q of the memory during the write
operation followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is
supported for x9 and x18 data widths. Detailed discussions of the WRITE modes and the constraints of the True
Dual Port can be found in Appendix A.
Additionally users can select to enable the output registers for RAM_DP_TRUE. Figures 8-15 through 8-20 show
the internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options.
9-15
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-17. True Dual Port RAM Timing Waveform – NORMAL Mode, without Output Registers
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
WrEnA
AddressA
DataA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_A1
Add_A0
Add_A0
Add_A1
Add_A2
Data_A0
Data_A1
t HDATA_EBR
Invalid Data
tSUDATA_EBR
Data_A0
tCO_EBR
Data_A1
Data_A2
QA
ClockB
ClockEnB
WrEnB
AddressB
DataB
tSUCE_EBR
tHCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_B1
Add_B0
Add_B0
Add_B1
Data_B0
Add_B2
Data_B0
Data_B1
tHDATA_EBR
Invalid Data
tSUDATA_EBR
Data_B1
Data_B2
QB
tCO_EBR
9-16
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-18. True Dual Port RAM Timing Waveform – NORMAL Mode with Output Registers
Reset
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
tSUWREN_EBR
tHWREN_EBR
WrEnA
tSUADDR_EBR
tHADDR_EBR
Add_A1
Add_A0
Data_A0
Add_A0
Add_A1
Add_A2
Data_A0
AddressA
DataA
QA
Data_A1
tHDATA_EBR
tSUDATA_EBR
Invalid Data
Data_A1
tCOO_EBR
ClockB
ClockEnB
WrEnB
AddressB
DataB
tSUCE_EBR
tHCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_B1
Add_B0
Add_B0
Add_B1
Add_B2
Data_B0
Data_B0
Data_B1
tHDATA_EBR
tSUDATA_EBR
Invalid Data
Data_B1
QB
tCOO_EBR
9-17
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-19. True Dual Port RAM Timing Waveform – READ BEFORE WRITE Mode, without Output Regis-
ters
Reset
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
WrEnA
AddressA
DataA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_A0
Add_A0
Add_A1
Add_A1
Add_A2
New
Data_A0
New
Data_A1
tSUDATA_EBR
tHDATA_EBR
Old_Data_A0
Invalid Data
New_Data_A0
CO_EBR
Old_Data_A1
New_Data_A1
QA
t
ClockB
ClockEnB
WrEnB
AddressB
DataB
tSUCE_EBR
tHCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_B0
Add_B0
Add_B1
Add_B1
Add_B2
New
Data_B0
New
Data_B1
tSUDATA_EBR
tHDATA_EBR
Old_Data_B0
Invalid Data
New_Data_B0
tCO_EBR
Old_Data_B1
New_Data_B1
QB
9-18
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-20. True Dual Port RAM Timing Waveform – READ BEFORE WRITE Mode, with Output Registers
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
WrEnA
AddressA
DataA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_A0
Add_A0
Add_A1
Add_A1
Add_A2
New
Data_A0
New
Data_A1
tSUDATA_EBR
tHDATA_EBR
New
Data_A1
Invalid Data
Old_Data_A0
New_Data_A0
Old_Data_A1
QA
tCOO_EBR
ClockB
ClockEnB
WrEnB
AddressB
DataB
tSUCE_EBR
tHCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_B0
Add_B0
Add_B1
Add_B1
Add_B2
New
Data_B0
New
Data_B1
tSUDATA_EBR
tHDATA_EBR
Invalid Data
New
Data_B1
QB
Old_Data_B0
New_Data_B0
Old_Data_B1
tCOO_EBR
9-19
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-21. True Dual Port RAM Timing Waveform – WRITE THROUGH Mode, without Output Registers
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
WrEnA
AddressA
DataA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_A1
Add_A0
Data_A0
Add_A0
Data_A1
tHDATA_EBR
Data_A0
Data_A2
Data_A1
Data_A3
Data_A2
Data_A4
Data_A3
tSUDATA_EBR
Data_A4
QA
Invalid Data
tCO_EBR
ClockB
ClockEnB
WrEnB
AddressB
DataB
tSUCE_EBR
tHCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_B0
Data_B0
Add_B1
Add_B0
Data_B3
Data_B2
Data_B1
Data_B2
Data_B1
Data_B4
Data_B3
tSUDATA_EBR
tHDATA_EBR
Data_B0
QB
Invalid Data
Data_B4
tCO_EBR
9-20
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-22. True Dual Port RAM Timing Waveform – WRITE THROUGH Mode, with Output Registers
Reset
ClockA
tSUCE_EBR
tHCE_EBR
ClockEnA
WrEnA
AddressA
DataA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_1
Add_0
Add_0
Data_0
Data_1
tHDATA_EBR
Data_2
Data_0
Data_3
Data_4
Data_2
tSUDATA_EBR
QA
Invalid Data
Data_1
Data_3
tCOO_EBR
ClockB
ClockEnB
WrEnB
AddressB
DataB
tHCE_EBR
tSUCE_EBR
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
Add_0
Add_1
Add_0
Data_0
Data_1
Data_2
Data_0
Data_3
Data_4
Data_2
tSUDATA_EBR
tHDATA_EBR
Invalid Data
QB
Data_1
Data_3
tCOO_EBR
9-21
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Pseudo Dual Port RAM (RAM_DP) – EBR-Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Pseudo-Dual Port RAM or
RAM_DP. IPexpress allows users to generate the Verilog-HDL or VHDL along with an EDIF netlist for the memory
size as per design requirements.
IPexpress generates the memory module, as shown in Figure 9-23.
Figure 9-23. Pseudo Dual Port Memory Module Generated by IPexpress
WrClock
WrClockEn
Reset
RdClock
RdClockEn
RAM_DP
EBR based Pseudo
Dual Port Memory
WE
WrAddress
Data
RdAddress
Q
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
block can be cascaded, in depth or width (as required to create these sizes).
The basic Pseudo Dual Port memory primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-
24.
Figure 9-24. Pseudo Dual Port RAM primitive or RAM_DP for LatticeECP/EC and LatticeXP Devices
ADW[x:0]
DI[y:0]
ADR[x:0]
CLKW
CLKR
CEW
EBR
CER
DO[y:0]
RST
WE
CS[2:0]
In the Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the
memory array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for the Single Port Memory are included in Table 9-7. The table lists the cor-
responding ports for the module generated by IPexpress and for the EBR RAM_DP primitive.
9-22
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Table 9-7. EBR based Pseudo-Dual Port Memory Port Definitions
Port Name in
Generated Module
Port Name in the EBR
Block Primitive
Description
Read Address
Active State
RdAddress
ADR[x:0]
ADW[x:0]
CLKR
CLKW
CER
—
—
WrAddress
RdClock
WrClock
RdClockEn
WrClockEn
Q
Write Address
Read Clock
Write Clock
Rising Clock Edge
Rising Clock Edge
Active High
Active High
—
Read Clock Enable
Write Clock Enable
Read Data
CEW
DO[y:0]
DI[y:0]
WE
Data
Write Data
—
WE
Write Enable
Reset
Active High
Active High
—
Reset
RST
—
CS[2:0]
Chip Select
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can cascade eight memories easily. However, if the memory size specified by the user requires more than
eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-8.
Table 9-8. Pseudo-Dual Port Memory Sizes for 9K Memory for LatticeECP/EC and LatticeXP Devices
Pseudo-Dual
Port Memory
Size
Read Address Write Address
Input Data
Port A
Input Data
Port B
Output Data
Port A
Output Data
Port B
Port A
Port B
[MSB:LSB]
[MSB:LSB]
8K x 1
4K x 2
DIA
DIB
DOA
DOB
RAD[12:0]
RAD[11:0]
RAD[10:0]
RAD[9:0]
RAD[9:0]
WAD[12:0]
WAD[11:0]
WAD[10:0]
WAD[9:0]
WAD[9:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
DIA[17:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
DIB[17:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
DOA[17:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
DOB[17:0]
2K x 4
1K x 9
512 x 18
Table 9-9 shows the various attributes available for the Pseudo Dual Port Memory (RAM_DP). Some of these attri-
butes are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
9-23
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Table 9-9. Pseudo-Dual Port RAM Attributes for LatticeECP/EC and LatticeXP Devices
User Selectable
Through
Default
Value
Attribute
Description
Values
IPexpress
DATA_WIDTH_W Write Data Word Width
DATA_WIDTH_R Read Data Word Width
1, 2, 4, 9, 18, 36
1, 2, 4, 9, 18, 36
1
YES
YES
YES
YES
NO
1
REGMODE
Register Mode (Pipelining)
Selects the Reset type
NOREG, OUTREG
ASYNC, SYNC
NOREG
ASYNC
000
RESETMODE
CSDECODE_W Chip Select Decode for Write 000, 001, 010, 011, 100, 101, 110, 111
CSDECODE_R
GSR
Chip Select Decode for Read 000, 001, 010, 011, 100, 101, 110, 111
Global Set Reset ENABLED, DISABLED
000
NO
ENABLED
YES
Users have the option of enabling the output registers for Pseudo-Dual Port RAM (RAM_DP). Figures 8-23 and 8-
24 show the internal timing waveforms for the Pseudo-Dual Port RAM (RAM_DP) with these options.
Figure 9-25. PSEUDO DUAL PORT RAM Timing Diagram – without Output Registers
WrClock
tSUCE_EBR
tHCE_EBR
WrClockEn
RdClock
tSUCE_EBR
tHCE_EBR
RdClockEn
WrAddress
RdAddress
tSUADDR_EBR
tHADDR_EBR
Add_1
tHADDR_EBR
Add_0
Add_2
tSUADDR_EBR
Add_0
Add_1
Add_2
Data_0
Data_1
tHDATA_EBR
Invalid Data
Data
Q
Data_2
tSUDATA_EBR
Dat
a_2
Data_0
tCO_EBR
Data_1
9-24
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-26. PSEUDO DUAL PORT RAM Timing Diagram – with Output Registers
WrClock
tSUCE_EBR
tHCE_EBR
WrClockEn
RdClock
tSUCE_EBR
tHCE_EBR
RdClockEn
WrAddress
RdAddress
tSUADDR_EBR
tHADDR_EBR
Add_1
tHADDR_EBR
Add_0
Add_2
tSUADDR_EBR
Add_0
Add_1
Add_2
Data_0
Data_1
tHDATA_EBR
Data_2
Data
Q
tSUDATA_EBR
Dat
a_1
Invalid Data
Data_0
tCOO_EBR
Read Only Memory (ROM) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Read Only Memory or ROM.
IPexpress allows users to generate the Verilog-HDL or VHDL along with an EDIF netlist for the memory size as per
design requirements. Users are required to provide the ROM memory content in the form of an initialization file.
IPexpress generates the memory module as shown in Figure 9-27.
Figure 9-27. ROM - Read Only Memory Module Generated by IPexpress
OutClock
ROM
OutClockEn
Reset
Q
EBR based Read Only
Memory
Address
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
blocks can be cascaded, in depth or width (as required to create these sizes).
The basic ROM primitive for the LatticeECP/EC and LatticeXP devices is as shown in Figure 9-28.
9-25
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-28. ROM Primitive for LatticeECP/EC and LatticeXP Devices
AD[x:0]
CLK
CE
DO[y:0]
EBR
RST
CS[2:0]
In the ROM mode the address for the port is registered at the input of the memory array. The output data of the
memory is optionally registered at the output.
The various ports and their definitions for the ROM are included in Table 9-10. The table lists the corresponding
ports for the module generated by IPexpress and for the ROM primitive.
Table 9-10. EBR-based ROM Port Definitions
Port Name in generated Port Name in the EBR
Module
block primitive
Description
Read Address
Active State
Address
AD[x:0]
—
OutClock
CLK
Clock
Rising Clock Edge
Active High
Active High
—
OutClockEn
Reset
CE
Clock Enable
Reset
RST
CS[2:0]
—
Chip Select
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can cascade eight memories easily. However, if the memory size specified by the user requires more than
eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU (external to the EBR blocks).
While generating the ROM using IPexpress, the user is required to provide an initialization file to pre-initialize the
contents of the ROM. These file are the *.mem files and they can be of Binary, Hex or the Addressed Hex formats.
The initialization files are discussed in detail in the Initializing Memory section of this technical note.
Users have the option of enabling the output registers for Read Only Memory (ROM). Figures 8-27 and 8-28 show
the internal timing waveforms for the Read Only Memory (ROM) with these options.
9-26
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-29. ROM Timing Waveform – without Output Registers
OutClock
tSUCE_EBR
tHCE_EBR
OutClockEn
Address
Q
Add_0
Add_1
Add_2
Add_3
Add_4
tSUADDR_EBR
tHADDR_EBR
Invalid Data
Data_0
Data_1
Data_2
Data_3
Data_4
tCO_EBR
Figure 9-30. ROM Timing Waveform – with Output Registers
OutClock
tSUCE_EBR
tHCE_EBR
OutClockEn
Address
Q
Add_0
Add_1
tHADDR_EBR
Invalid Data
Add_2
Add_3
Add_4
tSUADDR_EBR
Data_0
Data_1
tCOO_EBR
Data_2
Data_3
9-27
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
First In First Out (FIFO, FIFO_DC) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as First In First Out Memories –
FIFO and FIFO_DC. FIFO has a common clock for both read and write ports and FIFO_DC (or Dual Clock FIFO)
has separate clocks for these ports. IPexpress allows users to generate the Verilog-HDL or VHDL along with an
EDIF netlist for the memory size as per design requirement.
IPexpress generates the FIFO and FIFO_DC memory module as shown in Figures 9-31 and 9-32.
Figure 9-31. FIFO Module Generated by IPexpress
Clock
WrEn
RdEn
Reset
Data
Q
Full
FIFO
Almost Full
Empty
EBR based First-In First-Out
Memory
Almost Empty
Figure 9-32. FIFO_DC Module Generated by IPexpress
RdClock
WrClock
Q
Full
FIFO
WrEn
RdEn
Reset
Data
Almost Full
Empty
EBR based First-In First-Out
Memory
Almost Empty
LatticeECP/EC and LatticeXP devices do not have a built in FIFO. These devices have an emulated FIFO and
FIFO_DC. These are emulated by creating a wrapper around the existing RAMs (like RAM_DP). This wrapper also
includes address pointer generation and FIFO flag generation logic which will be implemented external to the EBR
block. Therefore, in addition to the regular EBR usage, there is extra logic for the address pointer generation and
FIFO flag generation.
A clock is always required as only synchronous write is supported. The various ports and their definitions for the
FIFO and FIFO_DC are included in Table 11.
9-28
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Table 9-11. EBR-based FIFO and FIFO_DC Memory Port Definitions
Port Name in Generated
Module
CLK
CLKR
CLKW
WE
Description
Clock (FIFO)
Rising Clock Edge
Rising Clock Edge
Rising Clock Edge
Active High
Active High
Active High
—
Read Port Clock (FIFO_DC)
Write Port Clock (FIFO_DC)
Write Enable
RE
Read Enable
RST
DI
Reset
Data Input
DO
Data Output
—
FF
Full Flag
Active High
Active High
Active High
Active High
AF
Almost Full Flag
Empty Flag
EF
AE
Almost Empty
Reset (or RST) only resets the output registers of the FIFO and FIFO_DC. It does not reset the contents of the
memory.
The various supported sizes for the FIFO and FIFO_DC in LatticeECP/EC and LatticeXP devices are shown in
Table 9-12.
Table 9-12. FIFO and FIFO_DC Data Widths Sizes for LatticeECP/EC and LatticeXP Devices
FIFO Size
8K x 1
Input Data
DI
Output Data
DO
4K x 2
DI[1:0]
DI[3:0]
DI[8:0]
DI[17:0]
DI[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO[17:0]
DO[35:0]
2K x 4
1K x 9
512 x 18
256 x 36
FIFO Flags
The FIFO and FIFO_DC have four flags available: Empty, Almost Empty, Almost Full and Full. The Almost Empty
and Almost Full flags have a programmable range.
The program ranges for the four FIFO flags are specified in Table 9-13.
Table 9-13. FIFO Flag Settings
FIFO Attribute Name
Description
Full flag setting
Programming Range
Program Bits
FF
AFF
AEF
EF
2N - 1
1 to (FF-1)
1 to (FF-1)
0
14
14
14
5
Almost full setting
Almost empty setting
Empty setting
The only restriction on the flag setting is that the values must be in a specific order (Empty=0, Almost Empty next,
followed by Almost Full and Full, respectively). The value of Empty is not equal to the value of Almost Empty (or
Full is equal to Almost Full). In this case, a warning is generated and the value of Empty (or Full) is used in place of
Almost Empty (or Almost Full). When coming out of reset, the Active High Flags empty and Almost Empty are set
to high, since they are true.
9-29
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The user should specify the absolute value of the address at which the Almost Empty and Almost Full Flags will go
true. For example, if the Almost Full Flag is required to go true at the address location 500 for a FIFO of depth 512,
the user should specify the value 500 in the IPexpress.
The Empty and Almost Empty Flags are always registered with the read clock and the Full and Almost Full Flags
are always registered to the write clock.
FIFO Operation
FIFOs are not supported in the hardware. The hardware has Embedded block RAMs (EBR) which can be config-
ured in Single Port (RAM_DQ), Pseudo-Dual Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The
FIFOs in these devices are emulated FIFOs that are built around these RAMs.
Each of these FIFOs can be configured with (pipelined) and without (non-pipelined) output registers. In the pipe-
lined mode users have an extra option for these output registers to be enabled by the RdEn signal. We will discuss
the operation in the following sections.
Let us take a look at the operation of these FIFOs.
First In First Out (FIFO) Memory: The FIFO or the single clock FIFO is an emulated FIFO. The address logic and
the flag logic is implemented in the FPGA fabric around the RAM.
The ports available on the FIFO are:
• Reset
• Clock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
Let us first discuss the non-pipelined or the FIFO without output registers. Figure 9-33 shows the operation of the
FIFO when it is empty and the data starts to get written into it.
9-30
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-33. FIFO Without Output Registers, Start of Data Write Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
The WrEn signal has to be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin
and Full and Almost full are low.
When the first data gets written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer
empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag gets de-asserted when the 3rd address location gets filled.
Now let is assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full
Flags are asserted. Figure 9-34 shows the behavior of these flags. In this figure we assume that FIFO depth is ‘N’.
9-31
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-34. FIFO Without Output Registers, End of Data Write Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Data_N-2
Data_N-1
Data_N
Data_X
Data_X
Invalid Q
Empty
Almost
Empty
Full
Almost Full
In this case, as seen above, the Almost Full flag is IN location 2 before the FIFO is filled. The Almost Full flag is
asserted when N-2 location is written, and Full flag is asserted when the last word is written into the FIFO.
Data_X data inputs do not get written as the FIFO is full (Full flag is high).
Now let us look at the waveforms when the contents of the FIFO are read out. Figure 9-35 shows the start of the
read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags gets de-asserted as shown.
9-32
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-35. FIFO Without Output Registers, Start of Data Read Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Empty
Almost
Empty
Full
Almost Full
Similarly as the data is read out, and FIFO is emptied, the Almost Empty and Empty flags are asserted. Below is
the
Figure 9-36. FIFO Without Output Registers, End of Data Read Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Data_N-4
Data_N-3
Data_N-2
Data_N-1
Data_N
Empty
Almost
Empty
Full
Almost Full
9-33
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figures 9-33 to 9-36 show the behavior of non-pipelined FIFO or FIFO without output registers. When we pipeline
the registers, the output data is delayed by one clock cycle. There is an extra option of output registers being
enabled by RdEn signal.
Figures 9-37 to 9-40 show the similar waveforms for the FIFO with output register and without output register
enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO with-
out output registers. However it is only the data out 'Q' that gets delayed by one clock cycle.
Figure 9-37. FIFO with Output Registers, Start of Data Write Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
9-34
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-38. FIFO with Output Registers, End of Data Write Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Data_N-2
Data_N-1
Data_N
Data_X
Data_X
Invalid Q
Empty
Almost
Empty
Full
Almost Full
Figure 9-39. FIFO with Output Registers, Start of Data Read Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Invalid Data
Data_1
Data_2
Data_3
Data_4
Empty
Almost
Empty
Full
Almost Full
9-35
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-40. FIFO with Output Registers, End of Data Read Cycle
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Data_N-5
Data_N-4
Data_N-3
Data_N-2
Data_N-1
Data_N
Empty
Almost
Empty
Full
Almost Full
And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle
(as compared to the non-pipelined FIFO), and the RdEn should be high also during that clock cycle, otherwise the
data takes an extra clock cycle when the RdEn goes true.
Figure 9-41. FIFO with Output Registers and RdEn on Output Registers
Reset
Clock
WrEn
RdEn
Data
Q
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Invalid Data
Data_1
Data_2
Empty
Almost
Empty
Full
Almost
Full
9-36
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Dual Clock First In First Out (FIFO_DC) Memory: The FIFO_DC or the dual clock FIFO is also an emulated
FIFO. Again the address logic and the flag logic is implemented in the FPGA fabric around the RAM.
The ports available on the FIFO_DC are:
• Reset
• RPReset
• WrClock
• RdClock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
FIFO_DC Flags: FIFO_DC, as an emulated FIFO, required the flags to be implemented in the FPGA logic around
the block RAM. Because of the two clocks, the flags are required to change clock domains from read clock to write
clock and vice versa. This adds latency to the flags either during assertion or during de-assertion. The latency can
be avoided only in one of the cases (either assertion or de-assertion).
In the current emulated FIFO, there is no latency during assertion of these flags. Thus, when these flag go true,
there is no latency. However this causes the latency during the de-assertion.
Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and
WrEn, however it takes extra RdClock cycles for de-assertion of Empty and Almost Empty flags.
On the other hand, de-assertion of Full and Almost Full result in reading out the data from the FIFO_DC. It takes
extra WrClock cycles after reading the data for these flags to come out.
With this in mind, let us look at the FIFO_DC without output register waveforms. Figure 9-42 shows the operation of
the FIFO_DC when it is empty and the data starts to get written into it.
9-37
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-42. FIFO_DC Without Output Registers, Start of Data Write Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
The WrEn signal has to be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to
begin and Full and Almost full are low.
When the first data gets written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no
longer empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So
the Almost Empty flag gets de-asserted when the third address location gets filled.
Now let is assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full
and Full Flags are asserted. Figure 9-43 shows the behavior of these flags. In this figure we assume that FIFO_DC
depth is ‘N’.
9-38
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-43. FIFO_DC Without Output Registers, End of Data Write Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Data_N-2
Data_N-1
Data_N
Data_X
Data_X
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
In this case, the Almost Full flag is in location 2 before the FIFO_DC is filled. The Almost Full flag is asserted when
N-2 location is written, and Full flag is asserted when the last word is written into the FIFO_DC.
Data_X data inputs do not get written as the FIFO_DC is full (Full flag is high).
Note that the assertion of these flags is immediate and there is no latency when they go true.
Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 9-44 shows the start of
the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags get de-asserted as shown.
In this case, note that the de-assertion is delayed by two clock cycles.
9-39
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-44. FIFO_DC Without Output Registers, Start of Data Read Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Invalid Q
Data_1
Data_2
Data_3
Data_4
Data_5
Data_6
Empty
Almost
Empty
Full
Almost
Full
Similarly, as the data is read out and FIFO_DC is emptied, the Almost Empty and Empty flags are asserted. Below
is the
Figure 9-45. FIFO_DC Without Output Registers, End of Data Read Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Data_N-3
Data_N-2
Data_N-1
Data_N
Data_N
Empty
Almost
Empty
Full
Almost
Full
9-40
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figures 9-42 to 9-45 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we
pipeline the registers, the output data is delayed by one clock cycle. There is an extra option for output registers to
be enabled by the RdEn signal.
Figures 9-46 to 9-49 show similar waveforms for the FIFO_DC with output register and without output register
enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO_DC
without output registers. However it is only the data out ‘Q’ that is delayed by one clock cycle.
Figure 9-46. FIFO_DC With Output Registers, Start of Data Write Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Data_1
Data_2
Data_3
Data_4
Data_5
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
9-41
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-47. FIFO_DC With Output Registers, End of Data Write Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Invalid
Data
Invalid
Data
Data
Q
Data_N-2
Data_N-1
Data_N
Invalid Q
Empty
Almost
Empty
Full
Almost
Full
Figure 9-48. FIFO_DC With Output Registers, Start of Data Read Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Invalid Q
Data_1
Data_2
Data_3
Data_4
Data_5
Empty
Almost
Empty
Full
Almost
Full
9-42
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-49. FIFO_DC With Output Registers, End of Data Read Cycle
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Data_N-4
Data_N-3
Data_N-2
Data_1
Data_N
Empty
Almost
Empty
Full
Almost
Full
Finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle (as
compared to the non-pipelined FIFO_DC), and the RdEn should be high also during that clock cycle. Otherwise the
data takes an extra clock cycle when the RdEn is goes true.
Figure 9-50. FIFO_DC With Output Registers and RdEn on Output Registers
Reset
WrClock
RdClock
RPReset
WrEn
RdEn
Data
Q
Invalid Data
Invalid Q
Data_1
Data_2
Data_3
Empty
Almost
Empty
Full
Almost
Full
9-43
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based
PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger distributed memory sizes. The memory’s address and output regis-
ters are optional.
Figure 9-51 shows the Distributed Single Port RAM module as generated by the IPexpress.
Figure 9-51. Distributed Single Port RAM Module Generated by IPexpress
Clock
ClockEn
Reset
PFU based
Distributed Single Port
Memory
Q
WE
Address
Data
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock, ClockEn and
Reset is generated by utilizing the resources available in the PFU. The basic Distributed Single Port RAM primitive
for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-52.
Figure 9-52. Distributed Single Port RAM (Distributed_SPRAM) for LatticeECP/EC and LatticeXP Devices
AD[3:0]
DI[1:0]
DO[1:0]
PFU
CK
WRE
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-
uration.
The various ports and their definitions for the memory are included in Table 9-14. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
9-44
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Table 9-14. PFU based Distributed Single port RAM Port Definitions
Port Name in
Generated Module
Port Name in the EBR
Block Primitive
Description
Active State
Clock
CK
Clock
Rising Clock Edge
ClockEn
Reset
WE
-
Clock Enable
Reset
Active High
-
Active High
WRE
AD[3:0]
DI[1:0]
DO[1:0]
Write Enable
Address
Active High
Address
Data
—
—
—
Data In
Q
Data Out
Users have an option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 8-35 and 8-36 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM)
with these options.
Figure 9-53. PFU Based Distributed Single Port RAM Timing Waveform - Without Output Registers
Clock
ClockEn
tSUWREN_PFU
tHWREN_PFU
WE
Address
Data
tSUADDR_PFU
tHADDR_PFU
Add_0
Add_1
Add_0
Add_1
Add_2
Data_0
Data_1
tSUDATA_PFU
tHDATA_PFU
Q
Invalid Data
Data_0
Data_1
Data_2
tCORAM_PFU
9-45
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-54. PFU Based Distributed Single Port RAM Timing Waveform – with Output Registers
Reset
Clock
ClockEn
tSUWREN_PFU
tHWREN_PFU
WE
Address
Data
tSUADDR_PFU
tHADDR_PFU
Add_0
Add_1
Add_0
Add_1
Add_2
Data_0
Data_1
tSUDATA_PFU
tHDATA_PFU
Q
Invalid Data
Data_0
Data_1
Data_2
tCO?
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the four input LUT (Look-Up Table) available in the
PFU. These LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-55 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-55. Distributed Dual Port RAM Module Generated by IPexpress
WrAddress
RdAddress
RdClock
RdClockEn
PFU based
Reset
WrClock
WrClockEn
WE
Distributed Dual Port
Memory
Q
Data
The generated module makes use of a 4-input LUT available in the PFU. Additional logic for Clocks, Clock Enables
and Reset is generated by utilizing the resources available in the PFU. The basic Distributed Dual Port RAM primi-
tive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-56.
9-46
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-56. PFU-based Distributed Dual Port RAM for LatticeECP/EC and LatticeXP Devices
RAD[3:0]
WAD[3:0]
WDO[1:0]
RDO[1:0]
DI[1:0]
PFU
WCK
WRE
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for the memory are included in Table 9-15. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 9-15. PFU-based Distributed Dual-Port RAM Port Definitions
Port Name in
Generated Module
Port Name in
EBR Block Primitive
Description
Write Address
Active State
WrAddress
WAD[23:0]
—
—
RdAddress
RdClock
RdClockEn
WrClock
WrClockEn
WE
RAD[3:0]
—
Read Address
Read Clock
Rising Clock Edge
Active High
Rising Clock Edge
Active High
Active High
—
—
Read Clock Enable
Write Clock
WCK
—
Write Clock Enable
Write Enable
Data Input
WRE
DI[1:0]
RDO[1:0]
Data
Q
Data Out
—
Users have the option of enabling the output registers for Distributed Dual Port RAM (Distributed_DPRAM). Fig-
ures 8-39 and 8-40 show the internal timing waveforms for the Distributed Dual Port RAM (Distributed_DPRAM)
with these options.
9-47
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-57. PFU Based Distributed Dual Port RAM Timing Waveform - Without Output Registers (Non-
Pipelined)
WrClock
tSUCE_EBR
tHCE_EBR
WrClockEn
WE
tSUADDR_EBR
tHADDR_EBR
WrAddress
RdAddress
Add_0
Add_1
Add_2
Add_0
Add_1
Add_2
Data
Q
Data_0
Data_1
Data_2
tSUDATA_EBR
tHDATA_EBR
Invalid Data
Data_0 Data_1
Data_2
tCORAM_PFU
9-48
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-58. PFU Based Distributed Dual Port RAM Timing Waveform – With Output Registers
Reset
WrClock
tSUWREN_PFU
tHWREN_PFU
WrClockEn
RdClock
tSUCE_PFU
tHCE_PFU
RdClockEn
WE
tSUWREN_PFU
tHWREN_PFU
tSUADDR_PFU
tHADDR_PFU
WrAddress
RdAddress
Data
Add_0
Add_1
Add_0
Add_1
Data_0
Data_1
tSUDATA_PFU
tHDATA_PFU
Q
Invalid Data
Data_0
Data_1
tCORAM_PFU
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-59 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-59. Distributed ROM Generated by IPexpress
Address
OutClock
PFU-based
Q
Distributed ROM
OutClockEn
Reset
The generated module makes use of the 4-input LUT available in the PFU. The basic Distributed Dual Port RAM
primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-60.
9-49
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-60. PFU-based Distributed ROM (Sync_ROM) for LatticeECP/EC and LatticeXP Devices
AD[3:0]
DO
PFU
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for the memory are included in Table 9-16. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 9-16. PFU-based Distributed ROM Port Definitions
Port Name in Generated Port Name in the EBR
Module
Block Primitive
Description
Address
Active State
Address
AD[3:0]
—
OutClock
—
Out Clock
Out Clock Enable
Reset
Rising Clock Edge
Active High
Active High
—
OutClockEn
Reset
—
—
Q
DO
Data Out
Users have the option of enabling the output registers for Distributed ROM (Distributed_ROM). Figures 8-43 and 8-
44 show the internal timing waveforms for the Distributed ROM with these options.
Figure 9-61. PFU Based ROM Timing Waveform – without Output Registers
tSUADDR_PFU
tHADDR_PFU
Address
Q
Add_0
Add_1
Add_2
Invalid Data
Data_0
Data_1
Data_2
tCORAM_PFU
9-50
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-62. PFU Based ROM Timing Waveform – with Output Registers
Reset
OutClock
OutClockEn
tSUADDR_PFU
tHADDR_PFU
Address
Q
Add_0
Add_1
Add_2
Invalid Data
Data_0
Data_1
tCORAM_PFU
Initializing Memory
In the EBR based ROM or RAM memory modes and the PFU based ROM memory mode, it is possible to specify
the power-on state of each bit in the memory array. Each bit in the memory array can have one of two values: 0 or
1.
Initialization File Format
The initialization file is an ASCII file, which a user can create or edit using any ASCII editor. IPexpress supports
three types of memory file formats:
1. Binary file
2. Hex File
3. Addressed Hex
The file name for the memory initialization file is *.mem (<file_name>.mem). Each row depicts the value to be
stored in a particular memory location. The number of characters (or the number of columns) represents the num-
ber of bits for each address (or the width of the memory module).
The Initialization File is primarily used for configuring the ROMs. The EBR in RAM mode can optionally use this Ini-
tialization File also to preload the memory contents.
9-51
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Binary File
The file is essentially a text file of 0’s and 1’s. The rows indicate the number of words and columns indicate the
width of the memory.
Memory Size 20x32
00100000010000000010000001000000
00000001000000010000000100000001
00000010000000100000001000000010
00000011000000110000001100000011
00000100000001000000010000000100
00000101000001010000010100000101
00000110000001100000011000000110
00000111000001110000011100000111
00001000010010000000100001001000
00001001010010010000100101001001
00001010010010100000101001001010
00001011010010110000101101001011
00001100000011000000110000001100
00001101001011010000110100101101
00001110001111100000111000111110
00001111001111110000111100111111
00010000000100000001000000010000
00010001000100010001000100010001
00010010000100100001001000010010
00010011000100110001001100010011
Hex File
The Hex file is essentially a text file of Hex characters arranged in a similar row-column arrangement. The number
of rows in the file is same as the number of address locations, with each row indicating the content of the memory
location.
Memory Size 8x16
A001
0B03
1004
CE06
0007
040A
0017
02A4
Addressed Hex (ORCA)
Addressed Hex consists of lines of address and data. Each line starts with an address, followed by a colon, and
any number of data. The format of memfile is address: data data data data ... where address and data are hexa-
decimal numbers.
-A0 : 03 F3 3E 4F
-B2 : 3B 9F
The first line puts 03 at address A0, F3 at address A1, 3E at address A2,and 4F at address A3. The second line
puts 3B at address B2 and 9F at address B3.
There is no limitation on the values of address and data. The value range is automatically checked based on the
values of addr_width and data_width. If there is an error in an address or data value, an error message is printed.
Users need not specify data at all address locations. If data is not specified at a certain address, the data at that
9-52
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
location is initialized to 0. IPexpress makes memory initialization possible both through the synthesis and simula-
tion flows.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
01.0
Change Summary
June 2004
Initial release.
July 2004
01.1
Minor updates only.
Minor updates only.
October 2004
February 2005
01.2
01.3
Replace LatticeEC™ and LatticeECP™ LatticeEC™, LatticeECP™ and LatticeXP™
Replace LatticeECP/ECLatticeEC/ECP and LatticeXP
Replace LatticeEC or LatticeECP LatticeEC, LatticeECP or LatticeXP
Added Hardware related information for the LatticeEC/ECP/XP devices
Update Figure 8-4
Figure 8-40 Replace “_EBR” with “_PFU” in the figure’s timing parameters.
Updated the Trual Dual Port RAM and Module Manager Flow sections.
April 2005
01.4
01.5
Updated the block diagrams of modules generated by the Module Manager. Added
section for Module Manager flow example. Added section for PMI flow.
October 2005
February 2006
April 2006
01.6
01.7
01.8
Removed the PMI support section
Updated the Initializing Memory section
October 2006
Updated the FIFO section. Added dual port memory access notes in Appendix A.
9-53
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Appendix A. Attribute Definitions
DATA_WIDTH
Data width is associated with the RAM and FIFO elements. The DATA_WIDTH attribute will define the number of
bits in each word. It takes the values as defined in the RAM size tables in each memory module.
REGMODE
REGMODE or the Register mode attribute is used to enable pipelining in the memory. This attribute is associated
with the RAM and FIFO elements. The REGMODE attribute takes the NOREG or OUTREG mode parameter that
disables and enables the output pipeline registers.
RESETMODE
The RESETMODE attribute allows users to select the mode of reset in the memory. This attribute is associated
with the block RAM elements. RESETMODE takes two parameters: SYNC and ASYNC. SYNC means that the
memory reset is synchronized with the clock. ASYNC means that the memory reset is asynchronous to clock.
CSDECODE
CSDECODE or the Chip select decode attributes are associated to block RAM elements. CS, or Chip Select, is the
port available in the EBR primitive that is useful when memory requires multiple EBR blocks cascaded. The CS sig-
nal would form the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus, so it can cas-
cade 8 memories easily. CSDECODE takes the following parameters: “000”, “001”, “010”, “011”, “100”, “101”,
“110”, and “111”. CSDECODE values determine the decoding value of CS[2:0]. CSDECODE_W is chip select
decode for write and CSDECODE_R is chip select decode for read for Pseudo Dual Port RAM. CSDECODE_A
and CSDECODE_B are used for true dual port RAM elements and refer to the A and B ports.
WRITEMODE
The WRITEMODE attribute is associated with the block RAM elements. It takes the NORMAL, WRITETHROUGH,
and READBEFOREWRITE mode parameters.
In NORMAL mode, the output data does not change or get updated, during the write operation. This mode is sup-
ported for all data widths.
In WRITETHROUGH mode, the output data is updated with the input data during the write cycle. This mode is sup-
ported for all data widths.
In READBEFOREWRITE mode, the output data port is updated with the existing data stored in the write address,
during a write cycle. This mode is supported for x9, x18 and x36 data widths.
WRITEMODE_A and WRITEMODE_B are used for dual port RAM elements and refer to the A and B ports in case
of a True Dual Port RAM.
For all modes (of the True Dual Port module), simultaneous read access from one port and write access from the
other port to the same memory address is not recommended. The read data may be unknown in this situation.
Also, simultaneous write access to the same address from both ports is not recommended. (When this occurs, the
data stored in the address becomes undetermined when one port tries to write a 'H' and the other tries to write a
'L'. )
It is recommended that the designer implements control logic to identify this situation if it occurs and either:
1. Implement status signals to flag the read data as possibly invalid, or
2. Implement control logic to prevent the simultaneous access from both ports.
GSR
GSR or Global Set/ Reset attribute is used to enable or disable the global set/reset for RAM element.
9-54
LatticeECP/EC and LatticeXP
DDR Usage Guide
February 2007
Technical Note TN1050
Introduction
LatticeECP™, LatticeEC™ and LatticeXP™ devices support various Double Data Rate (DDR) and Single Data
Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one
edge of a clock while the DDR interfaces capture data on both the rising and falling edges of the clock, thus dou-
bling the performance. This document will address in detail how to utilize the capabilities of the LatticeECP/EC and
LatticeXP devices to implement both generic DDR and DDR memory interfaces.
DDR SDRAM Interfaces Overview
DDR SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed operation. When read-
ing data from the external memory device, data coming into the device is edge aligned with respect to the DQS sig-
nal. This DQS strobe signal needs to be phase shifted 90 degrees before FPGA logic can sample the read data.
When writing to a DDR SDRAM the memory controller (FPGA) must shift the DQS by 90 degrees to center align
with the data signals (DQ). DQ and DQS are bi-directional ports. The same two signals are used for both write and
read operations. A clock signal is also provided to the memory. This clock is provided as a differential clock (CLKP
and CLKN) to minimize duty cycle variations. The memory also uses these clock signals to generate the DQS sig-
nal during a read via a DLL inside the memory. The skew between CLKP or CLKN and the SDRAM-generated
DQS signal is specified in the DDR SDRAM data sheet. Figures 10-1 and 10-2 show DQ and DQS relationships for
read and write cycles.
During read, the DQS signal is LOW for some duration after it comes out of tristate. This state is called Preamble.
The state when the DQS is LOW before it goes into Tristate is the Postamble state. This is the state after the last
valid data transition.
DDR SDRAM also require a Data Mask (DM) signals to mask data bits during write cycles. SDRAM interfaces typ-
ically are implemented with x8, x16 and x32 bits for each DQS signal. Note that the ratio of DQS to data bits is
independent of the overall width of the memory. An 8-bit interface will have one strobe signal.
Figure 10-1. Typical DDR Interface
FPGA
DDR Memory
(DDR Memory
Controller)
DQ<7:0>
8
DQ<7:0>
DQ<7:0>
DQS
DM
DQS
DM
DQS
DM
ADDRESS
X
Y
Z
ADDRESS
ADDRESS
COMMAND
CONTROL
COMMAND
CONTROL
COMMAND
CONTROL
CLK/CLKN
CLK/CLKN
CLK/CLKN
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
10-1
tn1050_03.2
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-2. DQ-DQS During READ
DQS
(at PIN)
Preamble
Postamble
DQ
(at PIN)
DQS
(at REG)
DQ
(at REG)
DQS PIN to
REG and 90
Degree
Phase Shift
Figure 10-3. DQ-DQS During WRITE
DQS
(at PIN)
DQ
(at PIN)
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices
This section describes how to implement the read and write sections of a DDR memory interface. It also provides
details of the DQ and DQS grouping rules associated with the LatticeECP/EC and LatticeXP devices.
DQS Grouping
Each DQS group generally consists of at least 10 I/Os (1DQS, 8DQ and 1DM) to implement a complete 8-bit DDR
memory interface. In the LatticeECP/EC devices each DQS signal will span across 16 I/Os and in the LatticeXP
devices the DQS will span 14 I/Os. Any 10 of these 16 I/Os can be used to implement an 8-bit DDR memory inter-
face. In addition to the DQS grouping, the user must also assign one reference voltage VREF1 for a given I/O bank.
The tables below show the total number of DQS groups available per I/O bank for each device and package.
10-2
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Table 10-1. Number of DQS Banks in the LatticeECP/EC Device
Number of DQS Groups per I/O Bank
Total x8
Package
Device
DQS Groups
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
4
2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
3
3
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
4
5
6
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
4
7
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
3
LFEC1
LFEC3
LFEC1
LFEC3
3
3
1
0
100-pin TQFP
1
0
6
1
1
144-pin TQFP
208-pin TQFP
6
1
1
LFEC6/LFECP6
LFEC1
6
1
1
6
1
1+11
1+11
1+11
1
1+11
1+11
1+11
LFEC3
8+21
8+21
8+21
10
12
12
12
14
18
20
22
22
24
30
LFEC6/LFECP6
LFEC10/LFECP10
LFEC3
2
2
LFEC6/LFECP6
LFEC10/LFECP10
LFEC15/LFECP15
LFEC6/LFECP6
LFEC10/LFECP10
LFEC15/LFECP15
LFEC20/LFECP20
LFEC33/LFECP33
LFEC20/LFECP20
LFEC33/LFECP33
2
2
256-ball fpBGA
2
2
2
2
2
2
3
3
484-ball fpBGA
672-ball fpBGA
3
3
3
3
3
3
4
4
4
4
1. 10 I/Os (1 DQS + 8 DQs + Bank VREF1) can function as a DDR interface in which the FPGA can have a DM output but not a DQS aligned
input (in the same DDR bank as the rest of the system).
Table 10-2. Number of DQS Banks in the LatticeXP Device
Number of DQS Groups per I/O Bank
Total x8
Package
Device
DQS Groups
0
0
0
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
1
0
0
0
0
1
1
2
2
2
2
3
2
3
3
3
3
4
2
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
4
0
0
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
5
1
1
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
6
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
7
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
LFXP3C/LFXP3E
LFXP6C LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP10C/LFXP10E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP10C/LFXP10E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP20C/LFXP20E
2
100-pin TQFP
2
7
144-pin TQFP
208-pin PQFP
7
8
8
12
12
16
16
20
16
20
20
20
20
24
256-ball fpBGA
388-ball fpBGA
484-ball fpBGA
672-ball fpBGA
10-3
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-4. DQ-DQS Grouping
n* I/O PADS
DQ, DM or VREF1
DQS PAD
(Ninth I/O Pad)
*For LatticeECP/EC: n = 16, for LatticeXP: n = 14.
Figure 10-4 shows a typical DQ-DQS group for both the LatticeECP/EC device and the LatticeXP device. The ninth
I/O of this group of 16 I/Os (for LatticeECP/EC) or 14 I/Os (for LatticeXP) is the dedicated DQS pin. All eight pads
before the DQS and seven (for LatticeECP/EC) or four (for LatticeXP) pads after the DQS are covered by this DQS
bus span. The user can assign any eight of these I/O pads to be DQ data pins. Hence, to implement a 32-bit wide
memory interface you would need to use four such DQ-DQS groups.
When not interfacing with the memory, the dedicated DQS pin can be used as a general purpose I/O. Each of the
dedicated DQS pin is internally connected to the DQS phase shift circuitry. The pinout information contained in the
LatticeECP/EC and LatticeXP device data sheets shows pin locations for the DQS pads. Table 10-2 shows an
extract from the LatticeECP/EC data sheet. In this case, the DQS is marked as LDQS6 (L=left side, 6 =associated
PFU row/column). Since DQS is always the fifth true pad in the DQ-DQS group, counting from low to high PFU
row/column number, LDQS6 will cover PL2A to PL9B. Following this convention, there are eight pads before and
seven pads after DQS for DQ available following counter-clockwise for the left and bottom sides of the device, and
following clockwise for the top and right sides of the device. The user can assign any eight of these pads to be DQ
data signals. The LatticeXP device follows the same method.
Table 10-3. EC20 Pinout (from LatticeECP/EC Family Data Sheet)
Ball Function
PL2A
Bank
LVDS
T
Dual Function
484 fpBGA
D4
672 fpBGA
E3
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
VREF2_7
PL2B
PL3A
C
T
VREF1_7
E4
E4
—
C3
B1
PL3B
C
T
—
B2
C1
PL4A
—
E5
F3
PL4B
C
T
—
F5
G3
D2
PL5A
—
D3
PL5B
C
T
—
C2
E2
PL6A
LDQS6
F4
D1
PL6B
C
T
—
G4
E3
E1
PL7A
—
F2
PL7B
C
T
—
D2
G2
F6
PL8A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
LUM0_PLLC_FB_A
—
B1
PL8B
C
T
C1
G6
H4
PL9A
F3
PL9B
C
T
E2
G4
J4
PL11A
G5
10-4
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Table 10-3. EC20 Pinout (from LatticeECP/EC Family Data Sheet)
Ball Function
PL11B
Bank
LVDS
Dual Function
484 fpBGA
672 fpBGA
7
7
C
T
—
—
H6
G3
J5
PL12A
K4
DDR Software Primitives
This section describes the software primitives that can be used to implement DDR interfaces and provides details
about how to instantiate them in the software. The primitives described include:
• DQSDLL The DQS delay calibration DLL
• DQSBUF The DQS delay function and the clock polarity selection logic
• INDDRXB The DDR input and DQS to system clock transfer registers
• ODDRXB The DDR output registers
An HDL usage example for each of these primitives is listed in Appendices B and C.
DQSDLL
The DQSDLL will generate a 90-degree phase shift required for the DQS signal. This primitive will implement the
on-chip DQSDLL. Only one DQSDLL should be instantiated for all the DDR implementations on one half of the
device. The clock input to this DLL should be at the same frequency as the DDR interface. The DLL will generate
the delay based on this clock frequency and the update control input to this block. The DLL will update the dynamic
delay control to the DQS delay block when this update control (UDDCNTL) input is asserted. Figure 10-5 shows
the primitive symbol. The active low signal on UDDCNTL updates the DQS phase alignment and should be initi-
ated at the beginning of READ cycles.
Figure 10-5. DQSDLL Symbol
DQSDLL
CLK
LOCK
RST
DQSDEL
UDDCNTL
Table 10-4 provides a description of the ports.
Table 10-4. DQSDLL Ports
Port Name
CLK
I/O
Definition
I
I
System CLK should be at frequency of the DDR interface, from the FPGA core.
Resets the DQSDLL
RST
UDDCNTL
Provides an update signal to the DLL that will update the dynamic delay. When held low
this signal will update the DQSDEL.
I
LOCK
O
O
Indicates when the DLL is in phase
DQSDEL
The digital delay generated by the DLL should be connected to the DQSBUF primitive.
DQSDLL Configuration Attributes
By default this DLL will generate a 90-degree phase shift for the DQS strobe based on the frequency of the input
reference clock to the DLL. The user can control the sensitivity to jitter by using the LOCK_SENSITIVITY attribute.
This configuration bit can be programmed to be either “HIGH” or “LOW”.
10-5
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
The DLL Lock Detect circuit has two modes of operation controlled by the LOCK_SENSITIVITY bit, which selects
more or less sensitivity to jitter. If this DLL is operated at or above 150 MHz, it is recommended that the
LOCK_SENSITIVITY bit be programmed “HIGH” (more sensitive). For operation running at or under 100 MHz it is
recommended that the bit be programmed “LOW” (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can
go either way.
DQSBUF
This primitive implements the DQS Delay and the DQS transition detector logic. Figure 10-6 shows the DQSBUFB
function. The preamble detect signal is also generated within this primitive.
Figure 10-6. DQSBUFB Function
DQSDEL
DQSBUFB
+
-
DQSI
DQSO
VREF
DQSDEL
PRMBDET
+
-
VREF - DV
(DV ~ 170mV)
DQSC
DQS
TRANSITION
DETECT
PRMBDET
DDRCLKPOL
READ
CLK
Figure 10-7 shows the primitive symbol and its ports. DQSI is the DQS signal from the memory. PRMBDET is the
preamble detect signal that is generated from the DQSI input. READ and CLK are user interface signals coming
from the FPGA logic. The DQSDLL block sends digital control line DQSDEL to this block. The DQS is delayed
based on this input from the DQSDLL. DQSO is the delayed DQS and is connected to the clock input of the first set
of DDR registers.
Figure 10-7. DQSBUFB Symbol
DQSBUFB
DQSI
DQSO
CLK
DDRCLKPOL
DQSC
READ
DQSDEL
PRMBDET
Table 10-5 provides a description of the I/O ports associated with the DQSBUFB primitive.
10-6
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Table 10-5. DQSBUFB Ports
Port Name
DQSI
I/O
I
Definition
DQS strobe signal from memory
CLK
I
System CLK
READ
I
Read generated from the FPGA core
DQS delay from the DQSDLL primitive
DQSDEL
DQSO
I
O
O
O
O
Delayed DQS Strobe signal, to the input capture register block
DQS Strobe signal before delay, going to the FPGA core logic
DDR Clock Polarity signal
DQSC
DDRCLKPOL
PRMBDET
Preamble detect signal, going to the FPGA core logic
Notes:
1. The DDR Clock Polarity output from this block should be connected to the DDCLKPOL inputs of the input
register blocks (IDDRXB).
READ Pulse Generation
The READ signal to the DQSBUFB block is internally generated in the FPGA core. The Read signal will go high
when the READ command to control the DDR SDRAM is initially asserted. This should normally precede the DQS
preamble by one cycle yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry of the Lat-
ticeECP/EC and LatticeXP devices require the falling edge of the READ signal to be placed within the preamble
stage.
The preamble state of the DQS can be detected using the CAS latency and the round trip delay for the signals
between the FPGA and the memory device. Note that the internal FPGA core generates the READ pulse. The rise
of the READ pulse needs to coincide with the initial READ Command of the Read Burst and needs to go low before
the Preamble goes high.
Figure 10-8 shows the READ Pulse Timing Example with respect to the PRMBDET signal.
Figure 10-8. READ Pulse Generation
POSTAMBLE PREAMBLE
FIRST DQS
TRANSITION
POSTAMBLE
PRIOR READ CYCLE
DQS
VTH
PRMBDET
READ
OK
FAIL
READ
READ
READ
FAIL
OK
10-7
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
IDDRXB
This primitive will implement the input register block. The software defaults to CE Enabled unless otherwise speci-
fied. The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFB primi-
tive). The SCLK input should be connected to the system (FPGA) clock. The SCLK and CE inputs to this primitive
will be used primarily to synchronize the DDR inputs. DDRCLKPOL is an input from the DQS Clock Polarity tree.
This signal is generated by the DQS Transition detect circuit in the hardware. Figure 10-9 shows the primitive sym-
bol and the I/O ports.
Figure 10-9. IDDRXB Symbol
IDDRXB
D
ECLK
QA
LSR
QB
SCLK
CE
DDRCLKPOL
Table 10-6 provides a description of all I/O ports associated with the IDDRXB primitive.
Table 10-6. IDDRXB Ports
Port Name
I/O
Definition
D
I
I
DDR data
ECLK
LSR
The phase shifted DQS should be connected to this input
Reset
I
SCLK
CE
I
System CLK
I
Clock enable
DDRCLKPOL
QA
I
DDR clock polarity signal
Data at the positive edge of the CLK
Data at the negative edge of the CLK
O
O
QB
Note:
1. The DDRCLKPOL input to IDDRXB should be connected to the DDRCLKPOL output of DQSBUFB.
ODDRXB
The ODDRXB primitive implements both the write and the tristate functions. This primitive is used to output DDR
data and the DQS strobe to the memory. The CKP and CKN can also be generated using this primitive. All the
DDR output tristate implementations are also implemented using the same primitive.
Figure 10-10 shows the ODDRXB primitive symbol and its I/O ports.
10-8
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-10. ODDRXB Symbol
ODDRXB
CLK
DA
Q
DB
LSR
Table 10-7 provides a description of all I/O ports associated with the ODDRXB primitive.
Table 10-7. ODDRXB Ports
Port Name
CLK
I/O
Definition
I
I
I
I
I
System CLK
DA
DB
LSR
Q
Data at the positive edge of the clock
Data at the negative edge of the clock
Reset
DDR data to the memory
Notes:
1. LSR should be held low during DDR Write operation. By default, the software will be implemented CE High
and LSR low.
2. DDR output and tristate registers do not have CE support. LSR is available for the tristate DDRX mode
(while reading). The LSR will default to set when used in the tristate mode.
3. CE and LSR support is available for the regular (non-DDR) output mode.
4. When asserting reset during DDR writes, it is important to keep in mind that this would only reset the FFs
and not the latches.
Memory Read Implementation
The LatticeECP/EC and LatticeXP devices contain a variety of features to simplify implementation of the read por-
tion of a DDR interface:
• DLL compensated DQS delay elements
• DDR input registers
• Automatic DQS to system clock domain transfer circuitry
The LatticeECP/EC and LatticeXP device data sheets detail these circuit elements.
Three primitives in the Lattice ispLEVER® design tools represent the capability of these three elements. The DQS-
DLL represents the DLL used for calibration. The IDDRXB primitive represents the DDR input registers and clock
domain transfer registers. Finally, the DQSBUFB represents the DQS delay block and the clock polarity control
logic. These primitives are explained in more detail in the following sections of this document. Figure 10-11 illus-
trates how to hook these primitives together to implement the read portion of a DDR memory interface. The DDR
Software Primitives section describes each of the primitives and its instantiation in more detail. Appendices A and B
provide example code to implement the complete I/O section of a memory interface within a LatticeECP/EC or Lat-
ticeXP device.
10-9
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-11. Software Primitive Implementation for Memory READ
IDDRXB
dq
D
QA
QB
datain_p
datain_n
DQSBUFB
DQSO
ECLK
dqs
DQSI
CLK
DDRCLKPOL
DQSC
DDRCLKPOL
clk
LSR
CE
READ
read
PRMBDET
DQSDEL
SCLK
6
dqsc
prmbdet
DQSDEL
DQSDLL
RST
reset
LOCK
lock
UDDCNTL
uddcntl
ce
Read Timing Waveforms
Figure 10-12 and Figure 10-13 show READ data transfer for two cases based on the results of the DQS Transition
detector logic. This circuitry decides whether or not to invert the phase of FPGA system CLK to the synchronization
registers based on the relative phases of PRMBDET and CLK.
• Case 1 – If CLK = 0 on the 1st PRMBDET transition, then DDRCLKPOL = 0, hence no inversion required.
(Figure 10-12)
• Case 2 – If CLK=1 on the 1st PRMBDET then DDRCLKPOL = 1, the system clock (CLK) needs to be
inverted before it is used for synchronization. (Figure 10-13)
The signals A, B and C illustrate the Read Cycle half clock transfer at different stages of IDDRX registers. The first
stage of the register captures data on the positive edge as shown by signal A and negative edge as shown by sig-
nal B. The data stream A goes through an additional half clock cycle transfers shown by signal C. Phase aligned
data streams B and C are presented to the next stage registers clocked by the FPGA CLK
10-10
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-12. READ Data Transfer When DDRCLKPOL=0
DQS at PIN
DQ at PIN
PRMBDET
P0
N0
P1
N1
DQS at IOL
DQ at IOL
P0
N0
P0
P1
N1
P1
A
N0
P0
N1
P1
B
C
FPGA CLK
DDRCLKPOL= 0
CLK TO SYNC
IO REGISTERS
DATAIN_P
DATAIN_N
P0
N0
Notes -
(1) DDR memory sends DQ aligned to DQS strobe.
(2) The DQS Strobe is delayed by 90 degree using the dedicated DQS logic.
(3) DQ is now center aligned to DQS Strobe.
(4) PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to
generate the DDRCLKPOL signal.
(5) The first set of IO registers A and B, capture data on the positive edge and negative edge of DQS.
(6) IO register C transfers data so that both data are now aligned to negative edge of DQS.
(7) DDCLKPOL signal generated will determine if the CLK going into the synchronization registers need to
be inverted. In this case, the DDRCLKPOL=0 as the CLK is LOW at the 1st rising edge of PRMBDET.
(8) The IO Synchronization registers capture data at on positive edge of the FPGA CLK.
10-11
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-13. Read Data Transfer When DDRCLKPOL=1
DQS at PIN
DQ at PIN
P0
N0
P1
N1
PRMBDET
DQS at IOL
DQ at IOL
N1
P0
N0
P0
P1
A
B
C
P1
N0
P0
N1
P1
FPGA CLK
DDRCLKPOL=1
CLK TO SYNC
IO REGISTERS
DATAIN_P
DATAIN_N
P0
N0
Notes -
(1) DDR memory sends DQ aligned to DQS strobe.
(2) The DQS Strobe is delayed by 90 degree using the dedicated DQS logic.
(3) DQ is now center aligned to DQS Strobe.
(4) PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to
generate the DDRCLKPOL signal.
(5) The first set of IO registers A and B, capture data on the positive edge and negative edge of DQS.
(6) IO register C transfers data so that both data are now aligned to negative edge of DQS.
(7) DDCLKPOL signal generated will determine if the CLK going into the synchronization registers need to
be inverted. In this case, the DDRCLKPOL=1 as the CLK is HIGH at the 1st rising edge of PRMBDET.
(8) The IO Synchronization registers capture data at on negative edge of the FPGA CLK.
Data Read Critical Path
Data in the second stage DDR registers can be registered either on the positive edge or on the falling edge of
FPGA clock depending on the DDRCLKPOL signal. In order to ensure that the data transferred to the FPGA core
registers is aligned to the rising edge of system CLK, this path should be constrained with a half clock transfer. This
half clock transfer can be forced in the software by assigning a multicycle constraint (multicycle of 0.5 X) on all the
data paths to the first PFU register.
10-12
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DQS Postamble
DDR Usage Guide
At the end of a READ cycle, the DDR SDRAM device executes the READ cycle postamble and then immediately
tristates both the DQ and DQS output drivers. Since neither the memory controller (FPGA) nor the DDR SDRAM
device are driving DQ or DQS at that time, these signals float to a level determined by the off-chip termination
resistors. While these signals are floating, noise on the DQS strobe may be interpreted as a valid strobe signal by
the FPGA input buffer. This can cause the last READ data captured in the IOL input DDR registers to be overwrit-
ten before the data has been transferred to the free running resynchronization registers inside the FPGA.
Figure 10-14. Postamble Effect on READ
DQS at PIN
P0
P0
N0
N0
P1
P1
N1
N1
DQ at PIN
DQS at IOL
DQ at IOL
P0
P1
A
B
N0
P0
N1
P1
C
CLK at
synce reg
P0
N0
DATAIN_P
DATAIN_N
LatticeECP/EC and LatticeXP devices have extra dedicated logic in the in the DQS Delay Block that will prevent
this postamble problem. The DQS postamble logic is automatically implemented when the user instantiates the
DQS Delay logic (DQSBUFB software primitive) in a design.
This postamble solution was implemented in all the devices of the LatticeECP/EC and LatticeXP families except
the LFEC20/LFECP20 device. For this device, it is recommended that the user issue an extra READ command to
assure correct data has been transferred to the synchronization registers.
The circumstances under which the extended READ cycle is issued are given in Table 10-8.
Table 10-8. DDR Read Postamble
Current Command
Next Command
Action
Lost Cycles
Read (Row x, Bank y) Read (Row x, Bank y) None.
None
3
Read (any address)
NOP
Extend the current read command.1
Extend the current read to (Row x, Bank y) consecutive to
current command
Read (Row x, Bank y) Read (Row n, Bank y)
Read (Row x, Bank y) Read (Row x, Bank n)
3
If the Row x, Bank n was open, do nothing. Else, extend
the current read to Row x, Bank y
3
3
Read (any address)
Write/LMR
Extend the current read command.
1. Current read is extended one or more additional clock cycles.
10-13
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-15. Postamble Solution with Extra READ Command
DQS at PIN
P0
P0
N0
N0
P1
P1
N1
N1
DQ at PIN
DQS at IOL
DQ at IOL
P0
P1
A
B
N0
P0
N1
P1
C
CLK at
synce reg
P0
N0
P1
N1
DATAIN_P
DATAIN_N
Memory Write Implementation
To implement the write portion of a DDR memory interface, two streams of single data rate data must be multi-
plexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive
at the memory pins center-aligned with data, DQ. Along with the strobe and data this portion of the interface pro-
vides the CLKP, CLKN Address/Command and Data Mask (DM) signals to the memory.
LatticeECP/EC and LatticeXP devices contain DDR output and tri-state registers along with PLLs that allow the
easy implementation of the write portion of the DDR memory interfaces. The DDR output registers can be
accessed in the design tools via the ODDRXB primitive.
All DDR output signals (“ADDR, CMD”, DQS, DQ, DM) are initially aligned to the rising edge of CLK inside the
FPGA core. These signals are used for the entire DDR write interface or the controls of DDR read interface. The
relative phase of the signals may be adjusted in the IOL logic before departing the FPGA. The adjustments are
shown in Figure 16
The adjustments are as follows:
The PLL is used to generate a 90 degree phase shifted clock. This 90 degree phase shifted clock will be used to
generate DQS and the differential clocks going to the memory.
The CLKP needs to be centered relative to the ADDR,CMD signal, which is an SDR signal. This is accomplished
by inverting the CLKP signal relative to the PLL’s 90 degree phase shifted CLK.
The DDR clock can be generated by assigning “0” to the DA input and “1” to the DB inputs of the ODDRXB primi-
tive as shown in Figure 10-16. This is then fed into a SSTL25 differential output buffer to generate CLKP and CLKN
differential clocks. Generating the CLKN in this manner would prevent any skew between the two signals.
The DDR interface specification for t
and t
parameters, defined as DQS falling to CLKP rising setup and
DSH
DSS
hold times must be met. This is met by making CLKP and DQS identical in phase. DQS is inverted to match CLKP
(= CLK + 270). This is accomplished by routing the positive DQS data in core logic to DB, and negative DQS data
in core logic to DA inputs of the ODDRXB primitive.
10-14
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Internally the DQS and ADDR/CMD signals are clocked using the primary FPGA clock. Therefore, the user will
need to do a 1/4 (one-quarter) clock transfer from the core logic to the DDR registers. Timing can be hard to meet,
so it is recommended that the user first register these signals with the inverted Clock, so that the transfer from the
core logic to I/O registers will only require a 1/2 (half) clock transfer.
The data DQ and DM needs to be delayed by 90° as it leaves the FPGA. This is to center the data and data mask
relative to the DQS when it reaches the DDR memory. This can be accomplished by inverting the CLK to the DQ
and DM data.
The DM signal is generated using the same clock as the DQ data pin. The memory masks the DQ signals if the DM
pins are driven high.
The tristate control for the data output can also be implemented using the ODDRXB primitive.
Figure 10-16 illustrates how to hook up the ODDRXB primitives and the PLL. The DDR Software Primitives section
describes each of the primitives and its instantiation in more detail. Appendix A and Appendix B provide example
code for implementing the complete I/O section of a memory interface for a LatticeECP/EC or LatticeXP device.
Figure 10-16. Software Primitive Implementation for Memory Write
Core Logic PIO Logic
ODDRXB
CLK + 90
CLK
CLKP
CLKN
CLK
DA
CLK
PLL
Q
“0”
“1”
DB
LSR
D
D
D
D
D
ADDR/
CMD
Q
Q
D
Q
Q
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
CLK
DA
DB
dqstri_p
(From
User logic)
dqstri_n
Q
Q
Q
LSR
DDR Memory
Device
CLK
DA
DB
DQS
“0”
“1”
Q
Q
Q
Q
LSR
CLK
DA
DB
datatri_p
datatri_n
LSR
CLK
DA
DB
DQ
DM
(From
User logic)
dataout_p
dataout_n
LSR
CLK
DA
DB
LSR
10-15
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Write Timing Waveforms
Figure 10-17 shows DDR write side data transfer timing for the DQ Data pad and the DQS Strobe Pad. When writ-
ing to the DDR memory device, the DM (Data Mask) and the ADDR/ CMD (Address and Command) signals are
also sent to the memory device along with the data and strobe signals.
Figure 10-17. DDR Write Data Transfer for DQ Data
CLK
DATAOUT_P
DATAOUT_N
P0
N0
P1
N1
P2
N2
CLK +270
DQS
CLKP
CLKN
CLK +180
DQ
P0
N0
P1
N1
P2
N2
Notes -
(1) DATAOUT_P and DATAOUT_N are inputs to the DDR output registers.
(2) DQS is generated at 270 degree phase of CLK.
(3) CLKP is generated simular to DQS and CLKN is the inverted CLKP.
(4) DQ is generated at 180 degree phase of CLK.
(5) DQ is center aligned with the DQS strobe signal when it reaches the memory.
Design Rules/Guidelines
Listed below are some rules and guidelines to keep in mind when implementing DDR memory interfaces in the Lat-
ticeECP/EC and LatticeXP devices.
• The LatticeECP/EC and LatticeXP devices have dedicated DQ-DQS banks. Please refer to the logical sig-
nal connections of the groups in the LatticeECP/EC and LatticeXP data sheets before locking these pins.
• There are two DQSDLLs on the device, one for the top half and one for the bottom half. Hence, only one
DQSDLL primitive should be instantiated for each half of the device. Since there is only one DQSDLL on
each half of the device, all the DDR memory interfaces on that half of the device should run at the same fre-
quency. Each DQSDLL will generate 90 degree digital delay bits for all the DQS delay blocks on that half of
the device based on the reference clock input to the DLL.
10-16
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
• The DDR SDRAM interface supports the SSTL25 I/O standard, therefore the interface pins should be
assigned as SSTL25 I/O type.
• When implementing a DDR interface, the VREF1 of the bank is used to provide the reference voltage for the
interface pins.
• Appendix F shows DDR400 implementation results of the LatticeEC Advanced Evaluation Board.
QDR II Interface
QDR II SRAM is a new memory technology defined by a number of leading memory vendors for high-performance
and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate
unidirectional data buses dedicated for read and write operations running at double data rate. Both the QDR II read
and write interfaces use HSTL 1.8V I/O standard.
A QDR II memory controller can be easily implemented using the LatticeECP/EC and LatticeXP devices by taking
advantage of the DDR I/O registers. For LatticeECP/EC and LatticeXP devices, ODDRXB primitives are used on
the QDR outputs and PFU registers are used on the QDR inputs to implement the DDR interface. To see the details
of this implementation refer to Lattice reference design RD1019, QDR Memory Controller on the Lattice web site at
www.latticesemi.com.
FCRAM (Fast Cycle Random Access Memory) Interface
FCRAM is a DDR-type DRAM, which performs data output at both the rising and the falling edges of the clock.
FCRAM devices operate at a core voltage of 2.5V with SSTL Class II I/O. It has enhanced both the core and
peripheral logic of the SDRAM. In FCRAM the address and command signals are synchronized with the clock
input, and the data pins are synchronized with the DQS signal. Data output takes place at both the rising and falling
edges of the DQS. DQS is in phase with the clock input of the device. The DDR SDRAM and DDR FCRAM control-
ler will have different pin outs.
LatticeECP/EC and LatticeXP devices can implement an FCRAM interface using the dedicated DQS logic, input
DDR registers and output DDR registers as described in the Implementing Memory Interfaces section of this docu-
ment. Generation of address and control signals for FCRAM are different compared to the DDR SDRAM devices.
Please refer to the FCRAM data sheets to see detailed specifications. Toshiba, Inc. and Fujitsu, Inc. offer FCRAM
devices in 256Mb densities. They are available in x8 or x16 configurations.
Generic High Speed DDR Implementation
In addition to the DDR memory interface, users can use the I/O logic registers to implement a high speed DDR
interface. DDR data write operations can be implemented using the DDR output registers similar to the memory
interface implementation using the ODDRXB primitives.
On the input side, the read interface can be implemented using the core logic PFU registers. The PFU register next
to the I/O cells can be used to de-mux the DDR data to single data rate data. This method of implementing DDR
can run at 300 MHz when accompanied by proper preferences in the software. The HDL and the preferences to
implement this DDR interface are listed in Appendix D of this document.
Board Design Guidelines
The most common challenge associated with implementing DDR memory interfaces is the board design and lay-
out. Users must strictly follow the guidelines recommended by memory device vendors.
Some common recommendations include matching trace lengths of interface signals to avoid skew, proper DQ-
DQS signal grouping, proper termination of the SSTL2 I/O standard, proper VREF and VTT generation decoupling
and proper PCB routing.
10-17
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Some reference documents that discuss board layout guidelines:
• www.idt.com, IDT, PCB Design for Double Data Rate Memory.
• www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces.
• www.micron.com, TN4607, DDR 333 Design Guide for Two DIMM Systems
References
• www.jedec.org – JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification
• www.micron.com – DDR SDRAM Data Sheets
• www.infinion.com – DDR SDRAM Data Sheets
• www.samsung.com – DDR SDRAM Data Sheets
• www.latticesemi.com – RD1019 QDR Memory Controller Reference Design for LatticeECP/EC devices
• www.toshiba.com – DDR FCRAM Data Sheet
• www.fujitsu.com – DDR FCRAM Data Sheet
• www.latticesemi.com – LatticeEC Advanced Evaluation Board User’s Guide
• www.latticesemi.com – DDR SDRAM Controller (Pipelined Version for LatticeECP/EC Devices) User's
Guide
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
—
Version
—
Change Summary
Previous Lattice releases.
February 2007
03.2
Updated Generic High Speed DDR Implementation section.
Updated Appendix D.
10-18
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix A. Using IPexpress™ to Generate DDR Modules
The input and output DDR module can be generated using IPexpress. The I/O section under the Architecture mod-
ules provides two options to the user:
1. DDR_GENERIC – The option allows generation of a Generic DDR interface, which in the case of Lat-
ticeECP/EC and LatticeXP devices, is only the output side DDR. The input side for a Generic DDR inter-
face must be implemented using PFU registers. Appendix D provides the example code for the input side
generic DDR.
2. DDR_MEM – This option allows the user to generate a complete DDR memory interface. It will generate
both the read and write side interface required to interface with the memory.
IPexpress generates only the modules that are implemented within the IOLOGIC. Any logic required in the FPGA
core to complete the memory interface must be implemented by the user.
Figure 10-18. IPexpress I/O Section
DDR Generic
DDR Generic will generate the output DDR (ODDRXB) primitives for a given bus width. The user has the option to
enable or disable tristate control to the output DDR registers. Figure 10-19 shows the DDR Generic views of IPex-
press.
10-19
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-19. DDR Generic Configuration Options
DDR Memory Interface
This IPexpress option generates both read and write interfaces using all DDR primitives for a given bus width.
Figure 10-20 shows the options under this section.
Figure 10-20. Configuration Options for DDR Memory Interface
10-20
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix B. Verilog Example for DDR Input and Output Modules
module ddr_mem (dq, dqs, clk, reset, uddcntl, read, datain_p, datain_n, dqsc, prmbdet, lock,
ddrclkpol, clk90, dqstri_p, dqstri_n, datatri_p, datatri_n, dataout_p, dataout_n, ddrclk);
inout [7:0] dq/* synthesis IO_TYPE="SSTL25_II"*/;
inout dqs/* synthesis IO_TYPE="SSTL25_II"*/;
--clk is the core clock and clk90 is the 90 degree phase shifted clock coming from the PLL
input clk, clk90;
input reset, uddcntl, read;
input [7:0] dataout_p, dataout_n;
input [7:0] datatri_p, datatri_n;
input dqstri_p, dqstri_n;
output [7:0] datain_p;
output[7:0] datain_n;
output dqsc, prmbdet, lock, ddrclkpol;
output ddrclk /* synthesis IO_TYPE="SSTL25D_II"*/ ;
wire vcc_net,gnd_net;
wire dqsbuf, dqsdel, clk, ddrclkpol_sig;
wire [7:0] ddrin, ddrout, tridata;
wire dqsout, tridqs, dqsin, ddrclk;
assign vcc_net = 1'b1;
assign gnd_net = 1'b0;
assign ddrclkpol = ddrclkpol_sig;
//-------Bidirectional Buffers ------------------------------------------------------
BB bidiInst0 (.I(ddrout[0]), .T(tridata[0]), .O(ddrin[0]), .B(dq[0]));
BB bidiInst1 (.I(ddrout[1]), .T(tridata[1]), .O(ddrin[1]), .B(dq[1]));
BB bidiInst2 (.I(ddrout[2]), .T(tridata[2]), .O(ddrin[2]), .B(dq[2]));
BB bidiInst3 (.I(ddrout[3]), .T(tridata[3]), .O(ddrin[3]), .B(dq[3]));
BB bidiInst4 (.I(ddrout[4]), .T(tridata[4]), .O(ddrin[4]), .B(dq[4]));
BB bidiInst5 (.I(ddrout[5]), .T(tridata[5]), .O(ddrin[5]), .B(dq[5]));
BB bidiInst6 (.I(ddrout[6]), .T(tridata[6]), .O(ddrin[6]), .B(dq[6]));
BB bidiInst7 (.I(ddrout[7]), .T(tridata[7]), .O(ddrin[7]), .B(dq[7]));
//Bidirectional Strobe, DQS
BB bidiInst8(.I(dqsout), .T(tridqs), .O(dqsin), .B(dqs));
//------------------------------------------------------------------------------------
//-----------DDR Input ---------------------------------------------------------------
DQSBUFB
POL(ddrclkpol_sig),
U8
(.DQSI(dqsin),
.DQSC(dqsc), .PRMBDET(prmbdet), .DQSO(dqsbuf));
DQSDLL U9 (.CLK(clk), .UDDCNTL(uddcntl), .RST(reset), .DQSDEL(dqsdel), .LOCK(lock));
.CLK(clk),
.READ(read),
.DQSDEL(dqsdel),
.DDRCLK-
IDDRXB
UL0
(.D(ddrin[0]),
.ECLK(dqsbuf),
.SCLK(clk),
.CE(vcc_net),
.DDRCLK-
POL(ddrclkpol_sig),
.LSR(reset), .QA(datain_p[0]), .QB(datain_n[0]));
10-21
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
IDDRXB
POL(ddrclkpol_sig),
UL1
(.D(ddrin[1]),
.LSR(reset), .QA(datain_p[1]), .QB(datain_n[1]));
(.D(ddrin[2]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[2]), .QB(datain_n[2]));
(.D(ddrin[3]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[3]), .QB(datain_n[3]));
(.D(ddrin[4]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[4]), .QB(datain_n[4]));
(.D(ddrin[5]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[5]), .QB(datain_n[5]));
(.D(ddrin[6]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[6]), .QB(datain_n[6]));
(.D(ddrin[7]), .ECLK(dqsbuf), .SCLK(clk),
.LSR(reset), .QA(datain_p[7]), .QB(datain_n[7]));
.ECLK(dqsbuf),
.SCLK(clk),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
IDDRXB
POL(ddrclkpol_sig),
UL2
IDDRXB
POL(ddrclkpol_sig),
UL3
IDDRXB
POL(ddrclkpol_sig),
UL4
IDDRXB
POL(ddrclkpol_sig),
UL5
IDDRXB
POL(ddrclkpol_sig),
UL6
IDDRXB
POL(ddrclkpol_sig),
UL7
//----------------------------------------------------------------------------------------
//----TRISTATE Instantiations-------------------------------------------------------------
// DDR Trisate for data, DQ
ODDRXB T0 (.DA(datatri_p[0]), .DB(datatri_n[0]), .LSR(reset), .CLK(~clk), .Q(tridata[0]));
ODDRXB T1 (.DA(datatri_p[1]), .DB(datatri_n[1]), .LSR(reset), .CLK(~clk), .Q(tridata[1]));
ODDRXB T2 (.DA(datatri_p[2]), .DB(datatri_n[2]), .LSR(reset), .CLK(~clk), .Q(tridata[2]));
ODDRXB T3 (.DA(datatri_p[3]), .DB(datatri_n[3]), .LSR(reset), .CLK(~clk), .Q(tridata[3]));
ODDRXB T4 (.DA(datatri_p[4]), .DB(datatri_n[4]), .LSR(reset), .CLK(~clk), .Q(tridata[4]));
ODDRXB T5 (.DA(datatri_p[5]), .DB(datatri_n[5]), .LSR(reset), .CLK(~clk), .Q(tridata[5]));
ODDRXB T6 (.DA(datatri_p[6]), .DB(datatri_n[6]), .LSR(reset), .CLK(~clk), .Q(tridata[6]));
ODDRXB T7 (.DA(datatri_p[7]), .DB(datatri_n[7]), .LSR(reset), .CLK(~clk), .Q(tridata[7]));
// DDR Trisate for strobe, DQS
ODDRXB T8 (.DA(dqstri_p), .DB(dqstri_n), .LSR(reset), .CLK(clk90), .Q(tridqs));
//-----------------------------------------------------------------------------------------
//-----------DQ output---------------------------------------------------------------------
-
-
ODDRXB O0 (.DA(dataout_p[0]), .DB(dataout_n[0]), .LSR(reset), .CLK(~clk), .Q(ddrout[0]));
ODDRXB O1 (.DA(dataout_p[1]), .DB(dataout_n[1]), .LSR(reset), .CLK(~clk), .Q(ddrout[1]));
ODDRXB O2 (.DA(dataout_p[2]), .DB(dataout_n[2]), .LSR(reset), .CLK(~clk), .Q(ddrout[2]));
ODDRXB O3 (.DA(dataout_p[3]), .DB(dataout_n[3]), .LSR(reset), .CLK(~clk), .Q(ddrout[3]));
ODDRXB O4 (.DA(dataout_p[4]), .DB(dataout_n[4]), .LSR(reset), .CLK(~clk), .Q(ddrout[4]));
ODDRXB O5 (.DA(dataout_p[5]), .DB(dataout_n[5]), .LSR(reset), .CLK(~clk), .Q(ddrout[5]));
ODDRXB O6 (.DA(dataout_p[6]), .DB(dataout_n[6]), .LSR(reset), .CLK(~clk), .Q(ddrout[6]));
ODDRXB O7 (.DA(dataout_p[7]), .DB(dataout_n[7]), .LSR(reset), .CLK(~clk), .Q(ddrout[7]));
10-22
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
//-----------------------------------------------------------------------------------------
//--------------- DQS output---------------------------------------------------------------
--
--
ODDRXB O8 (.DA(gnd_net), .DB(vcc_net), .LSR(reset), .CLK(clk90), .Q(dqsout));
//-----------------------------------------------------------------------------------------
--
--
--
//--------------- CLKOUTP and CLKOUTN Generation-------------------------------------------
ODDRXB O9 (.DA(gnd_net), .DB(vcc_net), .LSR(reset), .CLK(clk90), .Q(ddrclk));
//-----------------------------------------------------------------------------------------
endmodule
10-23
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix C. VHDL Example for DDR Input and Output Modules
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
entity ddr_mem is
port( dq
dqs
: inout std_logic_vector(7 downto 0 );
: inout std_logic;
clk
: in std_logic; -- core clock
: in std_logic; -- 90 degree phase shifted clock from the pll
: in std_logic;
clk90
reset
uddcntl
read
: in std_logic;
: in std_logic;
dataout_p : in std_logic_vector(7 downto 0);
dataout_n : in std_logic_vector(7 downto 0);
datatri_p : in std_logic_vector(7 downto 0);
datatri_n : in std_logic_vector(7 downto 0);
dqstri_p
dqstri_n
ddrclk
: in std_logic;
: in std_logic;
: out std_logic;
datain_p
datain_n
dqsc
: out std_logic_vector(7 downto 0);
: out std_logic_vector(7 downto 0);
: out std_logic;
prmbdet
lock
: out std_logic;
: out std_logic;
ddrclkpol : out std_logic);
--*****DDR interface signals assigned SSTL25 IO Standard *************
ATTRIBUTE IO_TYPE
:
:
:
:
string;
ATTRIBUTE IO_TYPE OF ddrclk
ATTRIBUTE IO_TYPE OF dq
ATTRIBUTE IO_TYPE OF dqs
SIGNAL IS "SSTL25D_II";
SIGNAL IS "SSTL25_II";
SIGNAL IS "SSTL25_II";
end ddr_mem;
architecture structure of ddr_mem is
--*****DDR Input register*********************************************
component IDDRXB
port(
D
: in STD_LOGIC;
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
CE
: in STD_LOGIC;
LSR : in STD_LOGIC;
DDRCLKPOL : in STD_LOGIC;
QA
QB
: out STD_LOGIC;
: out STD_LOGIC);
end component;
10-24
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
--*******DDR Output register *******************************************
component ODDRXB
port(
CLK : in STD_LOGIC;
DA
DB
: in STD_LOGIC;
: in STD_LOGIC;
LSR : in STD_LOGIC;
: out STD_LOGIC);
Q
end component;
--*******Bidirectional Buffer********************************************
component BB
port(
I
T
O
B
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: inout STD_LOGIC);
end component;
--******DQS DLL Component*************************************************
component DQSDLL
port(
CLK
RST
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC);
UDDCNTL
LOCK
DQSDEL
end component;
--****** DQS Delay block***************************************************
component DQSBUFB
port(
DQSI
CLK
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC);
READ
DQSDEL
DQSO
DDRCLKPOL
DQSC
PRMBDET
end component;
signal dqsbuf : std_logic;
signal dqsdel : std_logic;
signal ddrclkpol_sig : std_logic;
signal ddrin : std_logic_vector(7 downto 0 );
signal ddrout : std_logic_vector(7 downto 0 );
signal tridata : std_logic_vector(7 downto 0 );
signal dqsout : std_logic;
signal tridqs : std_logic;
signal dqsin : std_logic;
signal vcc_net : std_logic;
signal gnd_net : std_logic;
10-25
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
signal clkinv : std_logic;
signal ddrclk : std_logic;
begin
vcc_net <= '1';
gnd_net <= '0';
clkinv<= not clk;
ddrclkpol<=ddrclkpol_sig;
--*************BIDIRECTIONAL BUFFERS*****************************************************
bidiInst0 : BB PORT MAP( I => ddrout(0),T => tridata(0),O => ddrin(0),B => dq(0));
bidiInst1 : BB PORT MAP( I => ddrout(1),T => tridata(1),O => ddrin(1),B => dq(1));
bidiInst2 : BB PORT MAP( I => ddrout(2),T => tridata(2),O => ddrin(2),B => dq(2));
bidiInst3 : BB PORT MAP( I => ddrout(3),T => tridata(3),O => ddrin(3),B => dq(3));
bidiInst4 : BB PORT MAP( I => ddrout(4),T => tridata(4),O => ddrin(4),B => dq(4));
bidiInst5 : BB PORT MAP( I => ddrout(5),T => tridata(5),O => ddrin(5),B => dq(5));
bidiInst6 : BB PORT MAP( I => ddrout(6),T => tridata(6),O => ddrin(6),B => dq(6));
bidiInst7 : BB PORT MAP( I => ddrout(7),T => tridata(7),O => ddrin(7),B => dq(7));
bidiInst8 : BB PORT MAP( I=> dqsout, T=> tridqs, O=> dqsin, B=> dqs);
--***************************************************************************************
--*************DDRInput******************************************************************
--DQSDLL, generates the DQS delay
I0: DQSDLL PORT MAP(CLK=>clk, UDDCNTL=> uddcntl, RST=> reset, DQSDEL=> dqsdel,
LOCK => lock);
I1: DQSBUFB PORT MAP( DQSI=> dqsin, CLK=>clk, READ=> read, DQSDEL=> dqsdel,
DDRCLKPOL=> ddrclkpol_sig, DQSC=> dqsc, PRMBDET=> prmbdet,
DQSO=> dqsbuf);
--DDR INPUT primitives
I2 : IDDRXB PORT MAP(D=> ddrin(0), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(0),
QB => datain_n(0));
I3 : IDDRXB PORT MAP(D=> ddrin(1), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(1),
QB => datain_n(1));
I4 : IDDRXB PORT MAP(D=> ddrin(2), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(2),
QB => datain_n(2));
I5 : IDDRXB PORT MAP(D=> ddrin(3), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(3),
QB => datain_n(3));
I6 : IDDRXB PORT MAP(D=> ddrin(4), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(4),
QB => datain_n(4));
I7 : IDDRXB PORT MAP(D=> ddrin(5), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(5),
QB => datain_n(5));
10-26
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
I8 : IDDRXB PORT MAP(D=> ddrin(6), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(6),
QB => datain_n(6));
I9 : IDDRXB PORT MAP(D=> ddrin(7), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(7),
QB => datain_n(7));
--***************************************************************************************
--*****TRISTATE Instantiations***********************************************************
-- DDR Trisate for data, DQ
T0 : ODDRXB PORT MAP( DA => datatri_p(0), DB => datatri_n(0), LSR => reset,
CLK => clkinv, Q => tridata(0));
T1 : ODDRXB PORT MAP( DA => datatri_p(1), DB => datatri_n(1), LSR => reset,
CLK => clkinv, Q => tridata(1));
T2 : ODDRXB PORT MAP( DA=> datatri_p(2), DB => datatri_n(2), LSR => reset,
CLK => clkinv, Q => tridata(2));
T3 : ODDRXB PORT MAP( DA => datatri_p(3), DB => datatri_n(3), LSR => reset,
CLK => clkinv, Q => tridata(3));
T4 : ODDRXB PORT MAP( DA => datatri_p(4), DB => datatri_n(4), LSR => reset,
CLK => clkinv, Q => tridata(4));
T5 : ODDRXB PORT MAP( DA => datatri_p(5), DB => datatri_n(5), LSR => reset,
CLK => clkinv, Q => tridata(5));
T6 : ODDRXB PORT MAP( DA => datatri_p(6), DB => datatri_n(6), LSR => reset,
CLK => clkinv, Q => tridata(6));
T7 : ODDRXB PORT MAP( DA => datatri_p(7), DB => datatri_n(7), LSR => reset,
CLK => clkinv, Q => tridata(7));
--DDR Trisate for strobe, DQS
T8: ODDRXB PORT MAP( DA =>dqstri_p, DB=> dqstri_n, LSR=> reset, CLK=> clk90,
Q => tridqs);
--****************************************************************************************
--***************DDR Output***************************************************************
--DQ OUTPUT
O0 : ODDRXB PORT MAP( DA => dataout_p(0), DB => dataout_n(0), LSR => reset,
CLK => clkinv, Q => ddrout(0));
O1 : ODDRXB PORT MAP( DA => dataout_p(1), DB => dataout_n(1), LSR => reset,
CLK => clkinv, Q => ddrout(1));
O2 : ODDRXB PORT MAP( DA => dataout_p(2), DB => dataout_n(2), LSR => reset,
CLK => clkinv, Q => ddrout(2));
O3 : ODDRXB PORT MAP( DA => dataout_p(3), DB => dataout_n(3), LSR => reset,
CLK => clkinv, Q => ddrout(3));
O4 : ODDRXB PORT MAP( DA => dataout_p(4), DB => dataout_n(4), LSR => reset,
CLK => clkinv, Q => ddrout(4));
O5 : ODDRXB PORT MAP( DA => dataout_p(5), DB => dataout_n(5), LSR => reset,
CLK => clkinv, Q => ddrout(5));
O6 : ODDRXB PORT MAP( DA => dataout_p(6), DB => dataout_n(6), LSR => reset,
CLK => clkinv, Q => ddrout(6));
O7 : ODDRXB PORT MAP( DA => dataout_p(7), DB => dataout_n(7), LSR => reset,
CLK => clkinv, Q => ddrout(7));
10-27
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
--DQS output
O8: ODDRXB PORT MAP( DA => gnd_net, DB => vcc_net, LSR => reset, CLK => clk90,
Q => dqsout);
--clkp and clkn Generation
O9 : ODDRXB PORT MAP( DA => vcc_net, DB => gnd_net, LSR => reset, CLK => clk90,
Q => ddrclk);
--******************************************************************************************
end structure;
10-28
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix D. Generic (Non-Memory) High-Speed DDR Interface
The following HDL implements the DDR input interface using PFU registers for non-memory DDR applications.
VHDL Implementation
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
entity ddrin is
port (rst : in std_logic;
ddrclk: in std_logic;
ddrdata: in std_logic_vector(7 downto 0);
datap: out std_logic_vector(7 downto 0);
datan: out std_logic_vector(7 downto 0));
end ddrin;
architecture structure of ddrin is
-- parameterized module component declaration
component pll90
port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
CLKOS: out std_logic; LOCK: out std_logic);
end component;
signal pos0 : std_logic_vector( 7 downto 0 );
signal pos1 : std_logic_vector( 7 downto 0 );
signal neg0 : std_logic_vector( 7 downto 0 );
signal clklock : std_logic;
signal ddrclk0: std_logic;
signal ddrclk90: std_logic;
signal vcc_net : std_logic;
signal gnd_net: std_logic;
attribute syn_useioff : boolean;
attribute syn_useioff of structure : architecture is false;
begin
vcc_net <= '1';
gnd_net <= '0';
-- parameterized module component instance
I0 : pll90
port map (CLK=>ddrclk, RESET=>rst, CLKOP=>ddrclk0, CLKOS=>ddrclk90, LOCK=>clklock);
demux: process (rst, ddrclk90)
begin
if rst = '1' then
pos0
neg0
pos1
<= (others => '0');
<= (others => '0');
<= (others => '0');
elsif rising_edge(ddrclk90) then
pos0 <= ddrdata;
10-29
elsif falling_edge(ddrclk90) then
neg0 <=ddrdata;
pos1 <=pos0;
end if;
end process demux;
synch: process (rst, ddrclk90)
begin
if rst = '1' then
datap <= (others => '0');
datan <= (others => '0');
elsif rising_edge(ddrclk90) then
datap<= pos1;
elsif falling_edge(ddrclk90) then
datan<= neg0;
end if;
end process synch;
end structure;
LatticeECP/EC and LatticeXP
Lattice Semiconductor
Verilog Example
DDR Usage Guide
module ddrin (rst, ddrclk, ddrdata, datap, datan)/*synthesis syn_useioff = 0*/;
// Inputs
input
input
input
rst;
ddrclk;
[7:0] ddrdata;
// Outputs
output
[7:0] datap, datan;
reg [7:0] pos0/*synthesis syn_keep=1*/;
reg [7:0] pos1/*synthesis syn_keep=1*/;
reg [7:0] neg0/*synthesis syn_keep=1*/;
reg [7:0] datap, datan/*synthesis syn_keep=1*/;
//PLL signals
wire ddrclk0;
wire ddrclk90;
pll I0 (.CLK(ddrclk), .RESET(rst), .CLKOP(ddrclk0), .CLKOS(ddrclk90), .LOCK(clklock));
always @ ( posedge ddrclk90)
begin
if (rst)
begin
pos0 <= 0;
end
else
begin
pos0 <= ddrdata;
end
end
always@ (negedge ddrclk90)
begin
if (rst)
begin
neg0<=0;
pos1<=0;
end
else
begin
neg0<=ddrdata;
pos1<=pos0;
end
end
always @ (posedge ddrclk90)
begin
if (rst)
begin
datap<= 0;
datan<= 0;
end
else
begin
datap<= pos1;
datan<= neg0;
end
10-31
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
end
endmodule
Preference File
In order to run the above DDR PFU Implementation at 300MHZ, the following preferences were added to the soft-
ware preference file.
COMMERCIAL;
FREQUENCY NET "ddrclk90" 300.000000 MHz ;
INPUT_SETUP PORT "ddrdata_0" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_1" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_2" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_3" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_4" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_5" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_6" 0.800000 ns CLKNET "ddrclk90" ;
INPUT_SETUP PORT "ddrdata_7" 0.800000 ns CLKNET "ddrclk90" ;
BLOCK ASYNCPATHS ;
10-32
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix E. List of Compatible DDR SDRAM
Below are the criteria used to list the DDR SDRAM part numbers.
1. The memory device should support one DQS strobe for every eight DQ data bits.
2. 4-bit, 8-bit and 16-bit configurations. For 16-bit configurations, each data byte must have an independent
DQS strobe.
3. The memory device uses SSTL2 I/O interface standard.
4. Data transfer rate DDR400, DDR333 or DDR266 for LatticeECP/EC devices and DDR333 or DDR266 for
LatticeXP devices.
5. Clock transfer rate of 200MHz, 167MHz or 133MHz for LatticeECP/EC devices and 167MHz or 133MHz for
LatticeXP devices.
Table 10-9 lists the DDR SDRAM part numbers that can be used with the LatticeECP/EC and LatticeXP devices.
Please note these part numbers are chosen based on the criteria stated above and have not necessary been vali-
dated in hardware.
Table 10-9. List of Compatible DDR SDRAM
DDR SDRAM Vendor
Micron 128MB
Part Number
MT46V32M4TG
Configuration
Max Data Rate
DDR266
Clock Speed
133MHz
32Mx4
DDR333
DDR266
167MHz
133MHz
Micron 128MB
Micron 128MB
MT46V16M8TG
MT46V8M16TG
16Mx8
8Mx16
DDR266
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
Micron 256MB
Micron 256MB
Micron 256MB
MT46V64M4FG
MT46V64M4TG
MT46V32M8FG
64Mx4
64Mx4
32Mx8
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
Micron 256MB
Micron 256MB
Micron 256MB
MT46V32M8TG
MT46V16M16FG
MT46V16M16TG
32Mx8
16Mx16
16Mx16
DDR266
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
Micron 512MB
Micron 512MB
Micron 512MB
MT46V128M4FN
MT46V128M4TG
MT46V64M8FN
128Mx4
128Mx4
64Mx8
DDR266
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
Micron 512MB
Micron 512MB
MT46V64M8TG
MT46V32M16FN
64Mx8
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
32Mx16
10-33
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Table 10-9. List of Compatible DDR SDRAM (Continued)
DDR SDRAM Vendor
Part Number
Configuration
Max Data Rate
DDR400
Clock Speed
200MHz
Micron 512MB
MT46V32M16TG
32Mx16
DDR333
DDR266
167MHz
133MHz
Micron 1GB
Micron 1GB
MT46V256M4TG
MT46V128M8TG
256Mx4
128Mx8
DDR266
DDR266
133MHz
133MHz
DDR333
DDR266
167MHz
133MHz
Micron 1GB
MT46V64M16TG
64Mx16
K4H280438E-TC/LB3
K4H280838E-TC/LB3
K4H281638E-TC/LB3
K4H560438E-TC/LB3
K4H560438E-NC/LB3
32Mx4
16Mx8
8Mx16
64Mx4
64Mx4
DDR333
DDR333
DDR333
DDR333
DDR333
167MHz
167MHz
167MHz
167MHz
167MHz
Samsung 128MB E die
DDR333
DDR400
167MHz
200MHz
K4H560438E-GC/LB3, CC
K4H560838E-TC/LB3, CC
K4H560838E-NC/LB3, CC
K4H560838E-GC/LB3, CC
K4H510838B-TC/LB3, CC
K4H510838B-NC/LB3, CC
K4H511638B-TC/LB3, CC
64Mx4
32Mx8
32Mx8
32Mx8
64Mx8
64Mx8
32Mx16
DDR333
DDR400
167MHz
200MHz
Samsung 256 Mb E-die
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
Samsung 512Mb B die
DDR333
DDR400
167MHz
200MHz
K4H510438B-TC/LB3
K4H510438B-NC/LB3
HYB25D128400AT
HYB25D128400CT
HYB25D128400CE
HYB25D128800AT
HYB25D128800CT
HYB25D128800CE
128Mx4
128Mx4
32Mx4
32Mx4
32Mx4
16Mx8
16Mx8
16Mx8
DDR333
DDR333
DDR266
DDR266
DDR266
DDR266
DDR333
DDR333
167MHz
167MHz
133MHz
133MHz
133MHz
133MHz
167MHz
167MHz
Infineon 128Mb
DDR333
DDR266
167MHz
133MHz
HYB25D128160AT
HYB25D128160CT
8Mx16
8Mx16
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
HYB25D128160CE
HYB25D128160CC
8Mx16
8Mx16
DDR333
167MHz
10-34
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Table 10-9. List of Compatible DDR SDRAM (Continued)
DDR SDRAM Vendor
Part Number
HYB25D256400BT
HYB25D256400CT
HYB25D256400CE
HYB25D256800BT
HYB25D256800CT
Configuration
64Mx4
Max Data Rate
DDR266
Clock Speed
133MHz
64Mx4
DDR266
DDR266
DDR333
DDR333
133MHz
133MHz
167MHz
167MHz
64Mx4
32Mx8
32Mx8
DDR333
DDR400
167MHz
200MHz
HYB25D256800CE
32Mx8
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
HYB25D256160BT
16Mx16
DDR333
DDR400
167MHz
200MHz
HYB25D256160CT
HYB25D256160CE
16Mx16
16Mx16
Infineon 256Mb
DDR333
DDR400
167MHz
200MHz
DDR400
DDR333
DDR266
200MHz
167MHz
133MHz
HYB25D256400BC
64Mx16
HYB25D256400CF
HYB25D256400CC
64Mx16
64Mx16
DDR333
DDR333
167MHz
167MHz
DDR333
DDR266
167MHz
133MHz
HYB25D256160BC
HYB25D256160CC
16Mx16
16Mx16
DDR333
DDR400
167MHz
200MHz
HYB25D512400AT
HYB25D512400BT
HYB25D512400BE
HYB25D1G400BG
128Mx4
128Mx4
128Mx4
256Mx4
DDR266
DDR333
DDR333
DDR266
133MHz
167MHz
167MHz
133MHz
DDR333
DDR266
167MHz
133MHz
HYB25D512800AT
HYB25D512800BT
HYB25D512800BE
HYB25D512160AT
HYB25D512160BT
HYB25D512160BE
HYB25D512400BC
64Mx8
64Mx8
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
64Mx8
DDR333
DDR266
167MHz
133MHz
32Mx16
32Mx16
32Mx16
128Mx4
DDR333
DDR400
167MHz
200MHz
Infineon 512Mb
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
HYB25D512400BF
HYB25D512800BC
HYB25D512800BF
128Mx4
64Mx8
64Mx8
DDR333
167MHz
DDR333
DDR400
167MHz
200MHz
DDR333
DDR400
167MHz
200MHz
HYB25D512160BC
HYB25D512160BF
32Mx16
32Mx16
DDR333
DDR400
167MHz
200MHz
10-35
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board
The DDR400 interface was implemented using the LatticeEC20 device on the LatticeEC Advanced Evaluation
Board. Figures 10-21, 10-22 and 10-23 show the READ, WRITE and WRITE to READ transition operations running
at 200MHz. For more information on the evaluation board, refer to LatticeEC Advanced Evaluation Board User’s
Guide available on the Lattice web site at www.latticesemi.com.
Figure 10-21. READ Function Running at 200MHz
Note: An extra READ command is implemented in the LatticeEC20 device to protect the data during postamble.
This extra READ is not required for other LatticeEC devices. Refer to the DQS Postamble section of this document
for more information.
10-36
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Figure 10-22. WRITE Function Running at 200MHz
Figure 10-23. WRITE to READ Transition Running at 200MHz
Note: An extra READ command is implemented in the LatticeEC20 device to protect the data during postamble.
This extra READ is not required for other LatticeEC devices. Refer to the DQS Postamble section of this document
for more information.
10-37
LatticeECP/EC and LatticeXP sysCLOCK
PLL Design and Usage Guide
June 2007
Technical Note TN1049
Introduction
As clock distribution and clock skew management become critical factors in overall system performance, the Phase
Locked Loop (PLL) is increasing in importance for digital designers. Lattice incorporates its sysCLOCK™ PLL tech-
nology in the LatticeECP™, LatticeEC™ and LatticeXP™ device families to help designers manage clocks within
their designs. The PLL components in the LatticeECP/EC and LatticeXP device families share the same architec-
ture. This technical note describes the features and functionalities of the PLLs and their configuration in the isp-
LEVER® design tool. Figure 11-1 shows the block diagram of the PLL.
Figure 11-1. LatticeECP/EC and LatticeXP sysCLOCK PLL Block Diagram
DDAOZR
DDAOLAG
DDAODEL[2:0]
RST
CLKOK
CLKOK
Divider
CLKI
Divider
CLKI
CLKOP
CLKOS
Phase &
Frequency Filter
Detector
Loop
Voltage
Controlled
Oscillator
CLKOP
Divider
Delay
Adjust
CLKFB
CLKFB
Divider
Phase/Duty
Select
Internal feedback from CLKOP Divider output
DDAMODE
DDAIZR
DDAILAG
LOCK
Lock
Detect
DDAIDEL[2:0]
Features
• Clock synthesis
• Phase shift/duty cycle selection
• Internal and external feedback
• Dynamic delay adjustment
• No external components required
• Lock detect output
Functional Description
PLL Divider and Delay Blocks
Input Clock (CLKI) Divider
The CLKI divider is used to control the input clock frequency into the PLL block. It can be set to an integer value of
1 to 16. The divider setting directly corresponds to the divisor of the output clock. The input and output of the input
divider must be within the input and output frequency ranges specified in the device data sheet.
Feedback Loop (CLKFB) Divider
The CLKFB divider is used to divide the feedback signal. Effectively, this multiplies the output clock, because the
divided feedback must speed up to match the input frequency into the PLL block. The PLL block increases the out-
put frequency until the divided feedback frequency equals the input frequency. Like the input divider, the feedback
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
11-1
tn1049_04.3
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
loop divider can be set to an integer value of 1 to 16. The input and output of the feedback divider must be within
the input and output frequency ranges specified in the device data sheet.
Delay Adjustment
The delay adjust circuit provides programmable clock delay. The programmable clock delay allows for step delays
in increments of 250ps (nominal) for a total of 2.00ns lagging or leading. The time delay setting has a tolerance.
See device data sheet for details. Under this mode, CLKOP, CLKOS and CLKOK are identically affected. The delay
adjustment has two modes of operation:
• Static Delay Adjustment – In this mode, the user-selected delay is configured at power-up.
• Dynamic Delay Adjustment (DDA) – In this mode, a simple bus is used to configure the delay. The bus
signals are available to the general purpose FPGA.
Output Clock (CLKOP) Divider
The CLKOP divider serves the dual purposes of squaring the duty cycle of the VCO output and scaling up the VCO
frequency into the 420MHz to 840MHz range to minimize jitter. Refer to Table 11-3 for CLKOP Divider value.
CLKOK Divider
The CLKOK divider feeds the global clock net. It divides the CLKOP signal of the PLL by the value of the divider. It
can be set to values of 2, 4, 6,....126,128.
PLL Inputs and Outputs
CLKI Input
The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the data sheet in order
for the PLL to operate correctly. The CLKI can be derived from a dedicated dual-purpose pin or from routing.
RST Input
The PLL reset occurs under two conditions. At power-up an internal power-up reset signal from the configuration
block resets the PLL. The user controlled PLL reset signal RST is provided as part of the PLL module that can be
driven by an internally generated reset function or a pin. This RST signal resets all internal PLL counters. When
RST goes inactive, the PLL will start the lock-in process, and will take the t
time to complete the PLL lock.
LOCK
Note: For LatticeECP/EC, RST must be asserted to re-start the locking process after losing lock. Refer to the Lat-
ticeECP/EC Family Data Sheet for the RST pulse width requirement. For LatticeXP, RST may be tied to GND.
Figure 11-2 shows the timing diagram of the RST Input.
Figure 11-2. RST Input Timing Diagram
tRST
RST
tLOCK
LOCK
CLKFBK Input
The feedback signal to the PLL, which is fed through the feedback divider can be derived from the global clock net,
a dedicated dual-purpose pin, or directly from the CLKOP divider. Feedback must be supplied in order for the PLL
to synchronize the input and output clocks. External feedback allows the designer to compensate for board-level
clock alignment.
CLKOP Output
The sysCLOCK PLL main clock output, CLKOP, is a signal available for selection as a primary clock.
11-2
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
CLKOS Output with Phase and Duty Cycle Select
The sysCLOCK PLL auxiliary clock output, CLKOS, is a signal available for selection as a primary clock. The
CLKOS is used when phase shift and/or duty cycle adjustment is desired. The programmable phase shift allows for
different phase in increments of 45° to 315°. The duty select feature provides duty select in 1/8th of the clock
period.
CLKOK Output with Lower Frequency
The CLKOK is used when a lower frequency is desired. It is a signal available for selection as a primary clock.
Dynamic Delay Control I/O Ports
Refer to Table 11-1 and Table 11-3 for detailed information.
LOCK Output
The LOCK output provides information about the status of the PLL. After the device is powered up and the input
clock is valid, the PLL will achieve lock within the specified lock time. Once lock is achieved, the PLL lock signal will
be asserted. If, during operation, the input clock or feedback signals to the PLL become invalid, the PLL will lose
lock. The LOCK signal is available to the FPGA routing to implement generation of RST.
Note: For LatticeECP/EC, RST must be asserted to restart the locking process after losing lock. Refer to the
LatticeECP/EC Family Data Sheet for the RST pulse width requirement. For LatticeXP, RST may be tied to
GND.
PLL Attributes
The PLL utilizes several attributes that allow the configuration of the PLL through source constraints. The following
section details these attributes and their usage.
FIN
The input frequency can be any value within the specified frequency range based on the divider settings.
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV
These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid
combination; determined by the input frequency, the dividers, and the PLL specifications.
Frequency_Pin_CLKI, Frequency_Pin_CLKOP and Frequency_Pin_CLKOK
These output clock frequencies determine the divider values.
FDEL
The FDEL attribute is used to pass the Delay Adjustment step associated with the Output Clock of the PLL. This
allows the user to advance or retard the Output Clock by the step value passed multiplied by 250ps(nominal). The
step ranges from -8 to +8 resulting the total delay range to +/- 2ns.
PHASEADJ
The PHASEADJ attribute is used to select Coarse Phase Shift for CLKOS output. The phase adjustment is pro-
grammable in 45° increments.
DUTY
The DUTY attribute is used to select the Duty Cycle for CLKOS output. The Duty Cycle is programmable at 1/8 of
the period increment.
FB_MODE
There are three sources of feedback signals that can drive the CLKFB Divider: internal, clocktree and external
feedback. Clocktree feedback is used by default. Internal feedback takes the CLKOP output at CLKOP Divider out-
put before the Clocktree to minimize the feedback path delay. The external feedback is driven from the pin.
DELAY_CNTL
11-3
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
This attribute is designed to select the Delay Adjustment mode. If the attribute is set to “DYNAMIC” the delay con-
trol switches between Dynamic and Static depending upon the input logic of DDAMODE pin. If the attribute is set to
“STATIC”, Dynamic Delay inputs are ignored in this mode.
LatticeECP/EC and LatticeXP PLL Primitive Definitions
The PLL primitive name is EHXPLLB. Figure 11-3 shows the LatticeECP/EC and LatticeXP PLL primitive library
symbol. Some features and I/Os are optional as described in Table 11-1 and Table 11-2.
Figure 11-3. LatticeECP/EC and LatticeXP PLL Primitive Symbol
EHXPLLB
RST
CLKI
CLKFB
CLKOP
CLKOS
CLKOK
DDAMODE
DDAIZR
LOCK
DDAOZR
DDAILAG
DDAIDEL2
DDAIDEL1
DDAIDEL0
DDAOLAG
DDAODEL2
DDAODEL1
DDAODEL0
Table 11-1. LatticeECP/EC and LatticeXP PLL I/O Definitions
Signal
I/O
I
Description
PLL reference clock input. From internal logic or dedicated clock pin.
Feedback clock input. From internal node, CLKOP or dedicated pin.
“1” to reset PLL
Optional
No
CLKI
CLKFB1
I
No
RST
I
No
CLKOP
O
O
O
O
I
PLL output clock to clock tree
No
CLKOS
PLL output clock to clock tree with optional phase shift/duty cycle
PLL output clock to clock tree through K-divider for lower frequency
“1” indicates PLL locked to CLKI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CLKOK
LOCK2
DDAMODE
DDAIZR
DDA Mode. “1”: Pin Control (dynamic), “0”: fuse control (static)
DDA Delay Zero. “1” delay=0, “0”: delay=[DDILAG+DDAIDEL].
DDA Lag/Lead. “1”: Lead, “0”: Lag.
I
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
I
I
DDA Delay
O
O
O
DDA Delay Zero Output
DDA Lag/Lead Output
DDA Delay Output
1. When internal feedback or clocktree feedback is selected in the IPexpress™ GUI, software uses CLKOP as the source of CLKFB. CLKOS
is not recommended as the source of CLKFB even in external feedback mode.
2. ModelSim® simulation models take two to four clock cycles from RST release to LOCK high.
PLL Attributes Definitions
The EHXPLLB can be configured through attributes in the source code. The following section details these attri-
butes and their usage.
Table 11-2. LatticeECP/EC and LatticeXP PLL Attributes
Preference Preference
User
IPexpress
Attribute
Name
Language
Support
Editor
Default
Value
Accessible
GUI Access
Support
Value
Note 5
Note 5
Note 5
Units
MHz
MHz
MHz
CLKI Frequency
Y
Y
Y
FREQUENCY_PIN_CLKI
FREQUENCY_PIN_CLKOP
FREQUENCY_PIN_CLKOK
N
N
N
N
N
N
100
100
50
CLKOP Frequency
CLKOK Frequency
CLKOP Frequency
Tolerance
Y
N
N
0.0, 0.1, 0.2, 0.5, 1.0, 2.0, 5.0, 10.0
0.0
%
11-4
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Table 11-2. LatticeECP/EC and LatticeXP PLL Attributes (Continued)
Preference Preference
User
Accessible
IPexpress
GUI Access
Attribute
Name
Language
Support
Editor
Default
Value
Support
Value
Units
CLKOP Actual
Frequency
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
Y
N
N
N
N
N
N
MHz
CLKOK Frequency
Tolerance
0.0, 0.1, 0.2, 0.5,1.0, 2.0, 5.0, 10.0
0.0
%
CLKOK Actual
Frequency
MHz
CLKI Divider
Setting
CLKI_DIV4, 6
1 to 16 (1 to 15)
1 to 16 (1 to 15)
Note 3
1
1
CLKFB Divider
Setting
CLKFB_DIV6
CLKOP_DIV6
CLKOP Divider
Setting
82 (4 or 6)
CLKOK Divider
Setting
Y
N
Y
CLKOK_DIV
FDEL
Y
Y
Y
N
Y
N
2, 4, 6,..,126, 128
-8 to 8
2
0
0
Fine Delay Adjust
ps
Coarse Phase Shift
Selection (O)
PHASEADJ
0, 45, 90...315
Degrees
Duty Cycle Selection
(1/8 increment)
Y
DUTY
Y
N
1 to 7
4
Delay Control
Feedback Mode
CLKOS Select
CLKOK Select
Y
Y
Y
Y
DELAY_CNTL1
FB_MODE
Y
N
N
N
N
N
N
N
DYNAMIC/STATIC
STATIC
INTERNAL/CLOCKTREE/EXTERNAL CLOCKTREE
1. DYNAMIC: This mode switches delay control between Dynamic and Static depending upon the input logic of the DDAMODE pin.
STATIC: This is Static Control Only mode.
2. The CLKOP_DIV value is calculated to maximize the fVCO within the specified range. For LatticeXP devices, if CLKOS is not used, the
default value is 6. If CLKOS is used, the value is 4.
3. The CLKOP Divider values are 2, 4, 6, 8,..32 (2, 4, 6, 8..30 for LatticeXP devices) if CLKOS is not used. The CLKOP Divider values are 2,
4, 8, 16, 32 (2, 4, 8, 16 for LatticeXP devices) if CLKOS is used.
4. All divider settings are user transparent in Frequency Mode. These are user attributes in Divider Mode.
5. Refer to data sheet for frequency limits.
6. Values in parentheses are for LatticeXP devices.
7. This attribute is not available in the IPexpress GUI. After reviewing the trace report file, users can determine the amount of delay that will
best fit the clocking in their design. Further information on FDEL settings is described in the following section.
FDEL Settings
There are four ways the user can enter the desired FDEL value.
1. Although the FDEL entry is not available in the IPexpress GUI, the module generated by IPexpress
includes the attribute with default value, “0”. Users can replace it with a desired value.
Example of source code with default FDEL value:
attribute FDEL of ehxpll_mod_0_0 : label is "0";
generic map (…
FDEL=>"0",
…
")
2. Preference File: User may specify the preference in the Preference file.
Example:
ASIC "FDEL_CODE_0_0" TYPE "EHXPLLB" FDEL="-2"
;
3. Pre-Map Preference Editor: Users can enter the FDEL value in the Pre-Map Preference Editor as shown in
Figure 11-4.
11-5
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-4. Pre-Map Preference Editor
4. EPIC Device Editor: Users can edit their preferences in the EPIC Device Editor as shown in Figure 11-5.
Figure 11-5. EPIC Preferences Edit Window
Dynamic Delay Adjustment
The Dynamic Delay Adjustment is controlled by the DDAMODE input. When the DDAMODE input is set to “1”, the
delay control is handled through the inputs, DDAIZR, DDAILAG and DDAIDEL(2:0). For this mode, the attribute
“DELAY_CNTL” must be set to “DYNAMIC”. Table 11-3 shows the delay adjustment values based on the attri-
bute/input settings.
In this mode, the PLL may come out of lock due to the abrupt change of phase. RST must be asserted to re-lock
the PLL. Upon de-assertion of RST, the PLL will start the lock-in process and will take the t
the PLL lock.
time to complete
LOCK
11-6
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Table 11-3. Delay Adjustment
DDAMODE = 1: Dynamic Delay Adjustment
DDAMODE = 0
DELAY 1 tDLY
=
Equivalent FDEL
Value
DDAIZR
DDAILAG
DDAIDEL[2:0]
111
250ps (nominal)
Lead 8 tDLY
Lead 7 tDLY
Lead 6 tDLY
Lead 5 tDLY
Lead 4 tDLY
Lead 3 tDLY
Lead 2 tDLY
Lead 1 tDLY
No delay
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
-8
-7
-6
-5
-4
-3
-2
-1
0
1
110
1
101
1
100
1
011
1
010
1
001
1
000
Don’t Care
Don’t Care
000
0
0
0
0
0
0
0
0
Lag 1 tDLY
Lag 2 tDLY
Lag 3 tDLY
Lag 4 tDLY
Lag 5 tDLY
Lag 6 tDLY
Lag 7 tDLY
Lag 8 tDLY
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
Note: tDLY = Unit Delay Time = 250 ps (nominal). See the data sheet for the tolerance of this delay
PLL Usage in IPexpress
Including sysCLOCK PLLs in a Design
The sysCLOCK PLL capability can be accessed through the IPexpress GUI. The following section describes the
usage of IPexpress.
IPexpress Usage
The LatticeECP/EC and LatticeXP PLL is fully supported in IPexpress in the ispLEVER software. IPexpress allows
the user to define the desired PLL using a simple, easy-to-use GUI. Following definition, a VHDL or Verilog module
that instantiates the desired PLL is created. This module can be included directly in the user’s design.
Figure 11-6 shows the main window when PLL is selected. The only entry required in this window is the module
name. After entering the module name, clicking on “Customize” will open the “Configuration” window as shown in
Figure 11-7.
11-7
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-6. IPexpress Main Window
Configuration Tab
The Configuration Tab lists all user accessible attributes. Default values are set initially.
There are two modes in the Configuration Tab which can be used to configure the PLL, Frequency Mode and
Divider Mode.
Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the
divider settings for the user. If the output frequency the user entered is not achievable, the nearest frequency will be
displayed in the ‘Actual’ text box. After input and output frequencies are entered, clicking the ‘Calculate’ button will
display the divider values. If the desired output frequency is not achievable with the given frequency tolerance, the
software generates an error. Users may increase the frequency tolerance or change the output frequencies.
Figure 11-7 shows the Configuration Tab window.
11-8
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-7. Configuration Tab
Divider Mode: In this mode, the user sets the input frequency and divider settings. It is assumed the user is famil-
iar with the PLL operation. The user must choose the CLKOP Divider value to maximize the f to achieve opti-
VCO
mum PLL performance. After input frequency and divider settings are set, clicking the ‘Calculate’ button will display
the output frequencies. If the divider settings are out of the PLL specification, the software will generate an error.
EHXPLLB Example Projects
ispLEVER provides example PLL projects for first time PLL users.
In the ispLEVER Project Navigator, go to the File menu and select Open Examples....
Select the FPGA folder. The LatticeEC and LatticeXP folders include PLL example projects in both Verilog and
VHDL.
11-9
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Equations for Generating Input and Output Frequency Ranges
The values of f
f
and f
are the absolute frequency ranges for the PLL. The values of f f f
IN, OUT
VCO
INMIN, INMAX, OUT-
and f
are the calculated frequency ranges based on the divider settings. These calculated frequency
MIN
OUTMAX
ranges become the limits for the specific divider settings used in the design.
Table 11-4. Frequency Limits
Parameter
LatticeECP/EC
LatticeXP
fIN
Note 1
Note 1
Note 1
Note 1
fOUT
fOUTK
VCO (Hz)
f
CLKI Divider
1 to 16
1 to 16
1 to 15
1 to 15
CLKFB Divider
CLKOP Divider
CLKOK Divider
Maximum (N*V)
See Table 11-2
2, 4, 6, 8,.. ,126, 128
Note 1
32
30
fPFD (fIN/M) (Hz)
Note: Refer to data sheet for the latest data.
The divider names are abbreviated with legacy names as:
• CLKI DIVIDER:M
• CLKFB DIVIDER:N
• CLKOP DIVIDER:V
• CLKOK DIVIDER:K
for use in the equations below.
f
Constraint
VCO
From the loop:
= f * (N/M)
f
(1)
OUT
IN
From the loop:
= f
f
* V
OUT
(2)
(3)
(4)
VCO
Substitute (1) in (2) yields:
= f * (N/M) * V
f
VCO
IN
Arrange (3):
= (f
f
/ (V*N))*M
VCO
IN
From equation (4):
f
f
= ((f
= (f
/(V*N))*M
/(V*N))*M
(5)
(6)
INMIN
VCOMIN
VCOMAX
INMAX
f
Constraint
PFD
From the loop:
f
f
f
= f / M
(7)
(8)
PFD
IN
= f
* M
IN
PFD
= f
* M = 25 * M (assume f
= 25)
PFDMIN
INMIN
PFDMIN
Equation (5) becomes:
11-10
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
f
= ((f
/ (V*N))*M, if below 25 * M round up to 25 * M
(9)
INMIN
VCOMIN
From the loop:
f
= f
* M = 420 * M
(10)
INMAX
PFDMAX
Assume f
= 420
INMAX
Equation (6) becomes:
= (f
f
/ (V*N))*M, if above 420 round down to 420
VCOMAX
(11)
INMAX
From equation (1):
f
f
= f
= f
* (N/M), if below 25 * N round up to 25 * N
(12)
(13)
OUTMIN
OUTMAX
INMIN
* (N/M), if above 420 round down to 420
INMAX
f
f
= f
= f
/ K
OUTKMIN
OUTKMAX
OUTMIN
/ K
OUTMAX
Clock Distribution in LatticeECP/EC and LatticeXP
The clock inputs are selected from external I/Os, the sysCLOCK PLLs or general routing. These clock inputs are
fed through the chip via a clock distribution system.
LatticeECP/EC and LatticeXP devices provide a quadrant-based primary and secondary clock structure.
Primary Clock Sources and Distribution
Each quadrant has four primary clock nets: CLK0, CLK1, CLK2 and CLK3. CLK2 and CLK3 provide dynamic clock
selection (DCS) capability. Figure 11-8 illustrates the block diagram of the primary clock distribution.
Figure 11-8. Primary Clocks and Center Switch Boxes
QUADRANT TL
QUADRANT TR
CLK0 CLK1 CLK2 CLK3
CLK3 CLK2 CLK1 CLK0
General
Routing
General
Routing
DCS
DCS
DCS
DCS
16:1
16:1
16:1
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
16:1
PCLKT7
CLKOP
PCLKT2
CLKOP
CLKOS
CLKOK
CLKOS
CLKOK
PLL*
PLL*
PLL
Primary Clocks in Center Switch Box
PLL*: For LatticeECP/EC/XP-10 and larger devices
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
PLL
16:1
16:1
16:1
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
16:1
DCS
DCS
DCS
DCS
General
Routing
General
Routing
CLK0 CLK1 CLK2 CLK3
CLK3 CLK2 CLK1 CLK0
QUADRANT BL
QUADRANT BR
Note: Two PLLs are available in LatticeECP/EC/XP-6 or smaller devices.
11-11
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Note on the Primary Clock
The CLKOP must be used as the feedback source to optimize the PLL performance.
Most designers use the PLL for the clock tree injection removal mode and the CLKOP should be assigned as the
primary clock. This is done automatically by the software unless the user specifies otherwise.
CLKOP can route to CLK0 and CLK1 only. CLKOS/CLKOK can route to all primary clocks (CLK0 to CLK3).
When CLK2 or CLK3 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned
as a buffer mode by the software. Please see the DCS section of this document for further information.
Clock Net Preferences
There are two clock nets, primary clock and secondary clock.
As illustrated in Figure 11-9, users can set each clock to the desired clock net in the Pre-map Preference Editor or
write in the Preference File as shown in the examples below.
Primary-Pure and Primary-DCS
Primary Clock Net can be assigned to either Primary-Pure (CLK0 and CLK1) or Primary-DCS (CLK2 and CLK3).
Syntax Example
USE PRIMARY DCS NET "bf_clk";
Global Primary Clock and Quadrant Primary Clock
Global Primary Clock
If a primary clock is not assigned as a quadrant clock, the software assumes it is a Global Clock.
There are two Global Primary/Pure Clocks and two Global Primary/DCS Clocks available.
Quadrant Primary Clock
Any Primary Clock may be assigned to a Quadrant Clock. The Clock may be assigned to a single quadrant or to
two adjacent quadrants (not diagonally adjacent).
When the quadrant clock net is used, users must ensure that the registers each clock drives can be assigned in
that quadrant without any routing issues.
With the Quadrant Primary Clocking scheme, the maximum number of Primary Clocks is 16 as long as all the Pri-
mary Clock Sources are avaialble.
Syntax Example
USE PRIMARY PURE NET "bf_clk" QUADRANT_TL;
11-12
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-9. Clock Preferences in the Pre-map Preference Editor
Secondary Clock Sources and Distribution
LatticeECP/EC and LatticeXP devices support quadrant base Secondary Clocks. Figure 11-10 describes the Sec-
ondary Clock arrangement.
Figure 11-10. Secondary Clock Center Switch Box
QUADRANT TR
Scondary Clock Trunk
QUADRANT TR
Scondary Clock Trunk
General
Routing
SCLK0 SCLK1 SCLK2 SCLK3 SCLK3 SCLK2 SCLK1 SCLK0
4
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
PCLKT7
PCLKT2
General
Routing
General
Routing
Secondary Clocks in Center Switch Box
4
4
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
4
SCLK0 SCLK1 SCLK2 SCLK3
SCLK3 SCLK2 SCLK1 SCLK0
General
Routing
QUADRANT BL
Scondary Clock Trunk
QUADRANT BR
Scondary Clock Trunk
Limitations on Secondary Clock Availability
As illustrated in Figure 11-11, three secondary clocks are shared with CLK, CE and LSR.
This routing scheme limits the secondary clocks available per quadrant base to three, which results in a maximum
of 12 available secondary clocks per device. Figure 11-11 illustrates the primary and secondary clock distribution
structure of the PFUs.
11-13
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
LFEC6/LFXP6 and smaller devices have limited routing resources and can implement a maximum of nine second-
ary clocks per device.
Figure 11-11. Primary Clock and Secondary Clock/CE/LSR Distribution
Primary Clock Net
PCLK0
Primary Clock
Local
4
PFU
CLK(0:3%
PCLK1
PCLK2
PCLK3
3
Secondary Clock
/CE/LSR
Secondary Clock
/CE/LSR
PFU
CE(0:3%
3
Secondary Clock/CE/LSR Net
Local
SCLK0/CE/LSR
SCLK1/CE/LSR
SCLK2/CE/LSR
SCLK3/CE/LSR
Secondary Clock
/CE/LSR
PFU
LSR(0:3%
3
Local
Dynamic Clock Selection (DCS)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of when the enable signal is toggled. The
DCS blocks are located in pairs at the center of each side of the device. Thus, there are eight of them in every
device.
Table 11-5. DCS I/O
I/O
Name
Description
Input Clock Select
SEL
Input
CLK0
Primary Clock Input 0
Primary Clock Input 1
To Primary Clock
CLK1
Output
DCSOUT
11-14
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Table 11-6. DCS Attributes
Output
Attribute Name
Description
SEL=0
CLK0
CLK0
0
SEL=1
CLK1
CLK1
CLK1
CLK1
0
Value
POS (Default)
NEG
Rising edge triggered, latched state is high
Falling edge triggered, latched state is low
Sel is active high, Disabled output is low
Sel is active high, Disabled output is high
Sel is active low, Disabled output is low
Sel is active low, Disabled output is high
Buffer for CLK0
HIGH_LOW
HIGH_HIGH
LOW_LOW
LOW_HIGH
CLK0
1
DCS MODE
CLK0
CLK0
CLK0
CLK1
1
CLK0
CLK1
Buffer for CLK1
CLK1
Figure 11-12. DCS Primitive Symbol
DCS
CLK0
CLK1
SEL
DCSOUT
DCS Waveforms
The DCSOUT waveform timing is described in Figure 11-13 for each mode. The ‘POS’ and ‘NEG’ modes describe
DCSOUT timing at both the falling and rising edges of SEL.
Figure 11-13. DCS Waveforms
DCS MODE = POS
At the rising edge (POS) of SEL, the DCSOUT changes from CLK0 to CLK1. This mode is the default mode.
DCS MODE = POS
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
SEL Rising edge:
- Wait for CLK1 rising edge,
latch output & remain high
- Switch output at CLK0 rising edge
- Wait for CLK0 rising edge,
latch output & remain high
- Switch output at CLK1 rising edge
11-15
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
DCS MODE = NEG
At the falling edge (NEG) of SEL, the DCSOUT changes from CLK0 to CLK1.
DCS MODE = NEG
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
SEL Rising edge:
- Wait for CLK1 falling edge,
latch output & remain low
- Switch output at CLK0 falling edge
- Wait for CLK0 falling edge,
latch output & remain low
- Switch output at CLK1 falling edge
DCS MODE = HIGH_LOW
SEL is active high (HIGH) to select CLK1, and the disabled output is LOW.
DCS MODE = LOW_LOW
SEL is active low (LOW) to select CLK0, and the disabled output is LOW.
DCS MODE = HIGH_LOW
DCS MODE = LOW_LOW
CLK1
SEL
CLK0
SEL
DCSOUT
DCSOUT
- Switch low at CLK1 falling edge.
- Switch low at CLK0 falling edge.
- If SEL is low, output stays low at on
CLK1 rising edge. SEL must not
- If SEL is high, output stays low at
on CLK0 rising edge.
change during setup prior to rising clock.
DCS MODE = HIGH_HIGH
SEL is active high (HIGH) to select CLK1, and the disabled output is HIGH.
DCS MODE = LOW_HIGH
SEL is active low (LOW) to select CLK0, and the disabled output is HIGH.
11-16
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
DCS MODE = HIGH_HIGH
DCS MODE = LOW_HIGH
CLK1
SEL
CLK0
SEL
DCSOUT
DCSOUT
- Switch high at CLK1 rising edge.
- Switch high at CLK0 rising edge.
- If SEL is low, output stays low high
on CLK1 falling edge.
- If SEL is high, output stays high on
CLK0 falling edge.
Use of DCS with PLL
The four PLL CLKOP sources reach CLK0 and CLK1 of the quadrant clock. When using the DCS, the PLL needs a
free-running feedback path to keep the PLL in lock. The user should use CLKOP as this feedback path, and
CLKOS as the input into the DCS. CLKOP does not reach CLK2 or CLK3 to prevent the user from using the PLL
improperly with DCS. See Figure 11-14.
Figure 11-14. Implementation of Dynamic Clock Select for a PLL Clock (Must Use Both CLKOP and CLKOS)
CLK2 ISB
D
C
S
CLK2
CLK0
CLK2 ISB
CLKI
CLKOS
(set 0°)
PLL
CLKOP
CLKFB
CLK0 ISB
Other Design Considerations
Jitter Considerations
The Clock Output jitter specifications assume that the reference clock is free of jitter. Even if the clock source is
clean, there are a number of sources that place noise in the PLL clock input. While intrinsic jitter is not avoidable,
there are ways to minimize the input jitter and output jitter.
Signal inputs that share the same I/O bank with PLL clock inputs are preferably less noisy inputs and slower switch-
ing signals. Try to avoid placing any high speed and noisy signals in the same I/O bank with clock signals if possi-
ble. Use differential signaling if possible.
When external feedback is used, the PCB path must be well designed to avoid reflection as well as noise coupling
from adjacent signal sources. A shorter PCB feedback path length does not necessarily reduce feedback input jit-
ter.
Simulation Limitations
• Simulation does not compensate for external delays and dividers in the feedback loop.
• The LOCK signal is not simulated according to the t
specification. The LOCK signal will appear active
LOCK
shortly after the simulation begins, but will remain active throughout the simulation.
• The jitter specifications are not included.
11-17
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available
It is best to connect VCCPLL to VCC at a single point using a filter and to create a separate GNDPLL plane directly
under it (tied via a single point to GND).
Separate islands for both VCCPLL and GNDPLL are recommended if applicable.
DCS Usage with Verilog
module dcs(clk0,clk1,sel,dcsout);
input clk0, clk1, sel;
output dcsout;
DCS DCSInst0 (.SEL(sel),.CLK0(clk0),.CLK1(clk1),.DCSOUT(dcsout));
defparam DCSInst0.DCSMODE = "CLK0";
endmodule
DCS Usage with VHDL
COMPONENT DCS
-- synthesis translate_off
GENERIC
(
DCSMODE : string := "POS"
);
-- synthesis translate_on
PORT
(
CLK0
CLK1
SEL
DCSOUT
);
:IN
:IN
:IN
:OUT
std_logic;
std_logic;
std_logic;
std_logic
END COMPONENT;
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is "POS";
begin
DCSInst0: DCS
-- synthesis translate_off
GENERIC MAP(
DCSMODE => "POS"
)
-- synthesis translate_on
PORT MAP
(
SEL
=> clksel,
=> dcsclk0,
=> sysclk1,
=> dcsclk
CLK0
CLK1
DCSOUT
);
11-18
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
01.0
Change Summary
June 2004
October 2004
Initial release.
01.1
RST description with timing diagram added.
Primitive ‘Wake_On_Lock’ removed.
Added RST input in EPLLB.
Fin min 33 replaced with 25.
FB_MODE default = CLOCKTREE
CLKOP_DIV values for EHXPLLB 2, 4, 8,16, 32.
Appendices C and D integrated to body of the document.
DCS source code example moved to Appendix A.
LatticeXP information added.
December 2004
January 2005
02.0
03.0
Figures 6 and 7 updated.
CLKOP_FREQ, CLKOK_FREQ user attributes added.
FB_MODE added.
October 2005
04.0
Clock Distribution section added.
Example code section removed and referred to help file.
GUI screen shots updated.
MM/IP Manager renamed as IPexpress.
Epllb definition section removed.
Clkos/clkok select attributes added.
Detailed clock distribution information added.
September 2006
April 2007
04.1
04.2
Updated footnote 3 in the LatticeECP/EC and LatticeXP PLL Attributes
table.
June 2007
04.3
Updated Lock Output section of PLL Inputs and Outputs..
LatticeECP/EC and LatticeXP PLL I/O Definitions table - corrected sig-
nal name DDAIDEL to read DDAIDEL[2:0] in the Signals column.
11-19
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Appendix A. Clock Preferences
A few key clock preferences are introduced below. Refer to the ‘Help’ file for other preferences and detailed infor-
mation.
ASIC
The following preference command assigns a phase of 90° to the CIMDLLA CLKOP.
ASIC "my_pll" TYPE "EXHXPLLB" CLKOS_PHASE=90;
FREQUENCY
The following physical preference command assigns a frequency of 100 MHz to a net named clk1.
FREQUENCY NET "clk1" 100 MHz;
The following preference specifies a hold margin value for each clock domain.
FREQUENCY NET "RX_CLKA_CMOS_c" 100.000 MHz HOLD_MARGIN 1 ns;
MAXSKEW
The following command assigns a maximum skew of 5 ns to a net named NetB.
MAXSKEW NET "NetB" 5 NS;
MULTICYCLE
The following command will relax the period to 50 ns for the path starting at COMPA to COMPB (NET1).
MULTICYCLE "PATH1" START COMP "COMPA" END COMP "COMPB" NET "NET1" 50 NS ;
PERIOD
The following command assigns a clock period of 30 ns to the port named Clk1.
PERIOD PORT "Clk1" 30 NS;
PROHIBIT
This command prohibits the use of a primary clock to route a clock net named bf_clk.
PROHIBIT PRIMARY NET "bf_clk";
CLOCK_TO_OUT
Specifies a maximum allowable output delay relative to a clock.
Below are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of
TRACE reporting.
The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers.
CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKNET "pll_rxclk" ;
The above preference will yield the following clock path:
11-20
LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Physical Path Details:
Clock path pll_inst/pll_utp_0_0 to PFU_33:
Name Fanout Delay (ns)
ROUTE 49 2.892 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk
--------
2.892 (0.0% logic, 100.0% route), 0 logic levels.
Site
Resource
If CLKPORT is used, the trace is complete back to the clock port resource and provides PLL compensation timing
numbers.
CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKPORT "RxClk" ;
The above preference will yield the following clock path:
Clock path RxClk to PFU_33:
Name Fanout Delay (ns)
Site
Resource
IN_DEL
ROUTE
--- 1.431
0.843
D5.PAD to
D5.INCK RxClk
1
D5.INCK to ULPPLL.CLKIN RxClk_c
MCLK_DEL --- 3.605 ULPPLL.CLKIN to ULPPLL.MCLK pll_inst/pll_utp_0_0
ROUTE 49 2.892 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk
--------
8.771 (57.4% logic, 42.6% route), 2 logic levels.
INPUT_SETUP
Specifies an setup time requirement for input ports relative to a clock net.
INPUT_SETUP PORT "datain" 2.000000 ns HOLD 1.000000 ns CLKPORT "clk" PLL_PHASE_BACK ;
PLL_PHASE_BACK
This preference is used with INPUT_SETUP when the user wants a trace calculation based on the previous clock
edge.
This preference is useful when setting the PLL output phase adjustment. Since there is no negative phase adjust-
ment provided, the PLL_PHASE_BACK preference works as if negative phase adjustment is available.
For example:
If phase adjustment of -90° of CLKOS is desired, the user can set the phase to 270° and set the INPUT_SETUP
preference with PLL_PHASE_BACK.
11-21
Power Estimation and Management for
LatticeECP/EC and LatticeXP Devices
September 2007
Technical Note TN1052
Introduction
One of the requirements when using FPGA devices is the ability to calculate power dissipation for a particular
device used on a board. Lattice’s ispLEVER® design tools include a Power Calculator tool which allows designers
to calculate the power dissipation for a given device. This technical note explains how to use Power Calculator to
calculate the power consumption of Lattice devices. General guidelines to reduce power consumption are also
included.
Power Supply Sequencing and Hot Socketing
LatticeECP™, LatticeEC™ and LatticeXP devices have eight sysIO™ buffer banks in addition to the V
V
CC, CCAUX
and V
power supplies; each is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O
CCJ
supply voltage (V
), and two voltage references V
and V
resources allowing each bank to be com-
CCIO
REF1
REF2
pletely independent from each other.
The LatticeECP/EC and LatticeXP devices are designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. The I/Os remain in tristate until the power supply volt-
age is high enough to ensure reliable operation during power up and power-down sequences and the leakage into
I/O pins is controlled to within specified limits. Refer to the Typical I/O Behavior During Power-up and Hot Socketing
sections of the device data sheet for more details.
Power Calculator Hardware Assumptions
The power consumption for a device can be coarsely broken down into the DC portion and the AC portion.
The power calculator reports the power dissipation in terms of:
1. DC portion of the power consumption.
2. AC portion of the power consumption.
The DC power (or the static power consumption) is the total power consumption of the used and unused resources.
These components are fixed for each resource used and depend upon the number of resource units utilized. The
DC component also includes the static power dissipation for the unused resources of the device.
The AC portion of power consumption is associated with the used resources and it is the dynamic part of the power
consumption. Its power dissipation is directly proportional to the frequency at which the resource is running and the
number of resource units used.
Power Calculator
Power Calculator is a powerful tool which allows users to make an estimate of the power consumption at two differ-
ent levels:
1. Estimate of the utilized resources before completing place and route
2. Post place and route design
For first level estimation, the user provides estimates of device usage in the Power Calculator Wizard and the tool
provides a rough estimate of the power consumption.
The second level is a more accurate approach where the user imports the actual device utilization by importing the
post Place and Route netlist (NCD) file.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
12-1
tn1052_02.3
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator Equations
The power equations used in the Power Calculator have the following general form:
Total DC Power (Resource)
= Total DC Power of Used Portion + Total DC Power of Unused Portion
= [DC Leakage per resource when Used * N
]
RESOURCE
+ [DC Leakage per resource when Unused * (N
- N
)]
RESOURCE
TOTAL RESOURCE
Where:
N
N
is the total number of resources in a device.
is the number of resources used in the design.
TOTAL RESOURCE
RESOURCE
The total DC power consumption for all the resources as per the design data is the sum of Quiescent Power and
the individual DC power of the resources in the Power Calculator.
Total DC Power (I
)
CCAUX
= K
* 500 µA + Typical Standby I
RESOURCE
CCAUX
Where:
KRESOURCE
is the number of reference input I/O such as HSTL/SSTL. For LVDS KRE-
SOURCE is number of inputs divided by two.
I
is a DC current that does not change with I/O toggle rate or temperature.
CCAUX
Typical Standby I
is found in the data sheet.
CCAUX
The AC power, on the other hand, is governed by the equation:
Total AC Power (Resource)
= K
* f
* AF
* N
RESOURCE RESOURCE
RESOURCE
MAX
Where:
N
N
K
is the total number of resources in a device.
is the number of resources used in the design.
is the power constant for the resource, measured in mW/MHz.
is the maximum frequency at which the resource is running, measured in MHz.
TOTAL RESOURCE
RESOURCE
RESOURCE
MAX
f
AF
is the activity factor for the resource group, as a percentage (%) of switching
RESOURCE
frequency.
Based on the above equations, if we wish to calculate the power consumption of the Slice portion, it will be as fol-
lows:
Total DC Power (Slice)
= Total DC Power of Used Portion + Total DC Power of Unused Portion
= [DC Leakage per Slice when Used * N
]
SLICE
+ [DC Leakage per Slice when Unused * (N
- N
)]
SLICE
TOTAL SLICE
Total AC Power (Slice)
= K * f
* AF
* N
SLICE
SLICE
MAX
SLICE
The DC and AC power, for a dedicated block, like DSP in LatticeECP devices, is governed by the following equa-
tions.
Total DC Power (Resource)
= DC Leakage per Resource * N
RESOURCE
12-2
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Total AC Power (Resource)
= K
* f
* N
RESOURCE
MAX RESOURCE
Where:
N
K
f
is the total number of resources in a device.
is the power constant for the resource, measured in mW/MHz.
is the maximum frequency at which the resource is running, measured in MHz.
RESOURCE
RESOURCE
MAX
Starting the Power Calculator
The user can launch the Power Calculator by one of the two methods. The first method is by clicking the Power Cal-
culator button in the toolbar as shown in Figure 12-1.
Figure 12-1. Starting Power Calculator from Toolbar
Alternatively, users can launch the Power Calculator by going to the Tools menu and selecting the option Power
Calculator as shown in Figure 12-2.
12-3
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-2. Starting Power Calculator from Tools Menu
The Power Calculator does not support some of Lattice’s older devices. The toolbar button and menu item is only
present when supported devices are selected.
12-4
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Starting a Power Calculator Project
Once the Power Calculator has been started, the Power Calculator window appears. Click on File ->Menu, and
select New to get to the Start Project window, as shown in Figure 12-3.
Figure 12-3. Power Calculator Start Project Window (Create New Project)
The Start Project window is used to create a new Power Calculator Project (*.pep project). Three pieces of data are
input in the Start Project window.
1. The Power Calculator project name by default is same as the Project Navigator project name. The name
can be changed, if desired.
2. Project Directory is where the Power Calculator project (*.pep) file will be stored. By default, the file is
stored in the main project folder.
3. Input an NCD file (if available) or browse to the NCD file in a different location.
12-5
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator Main Window
The main power calculator window is shown in Figure 12-4.
Figure 12-4. Power Calculator Main Window (Type View)
The top pane of the window shows information about the device family, device and the part number as it appears in
the Project Navigator. The V used for the Power Calculation is also listed. Users have an option to provide the
CC
ambient temperature, and the junction temperature is calculated based on that.
Users can also enter values of airflow in Linear Feet per Minute (LFM) along with heat sink to get the junction tem-
perature. A table in the top part of the Power Calculator summarizes the currents and power consumption associ-
ated with each type of power supply for the device. This also takes into consideration the I/O power supplies.
In the middle pane of the window, there are two tabs:
1. Power View
2. Report
The first tab is the Power view. Under this tab, the Power Calculator tool has an interactive spreadsheet type inter-
face.
12-6
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
The second and third columns, which are shaded blue in the tool, provide the DC (or static) and AC (or dynamic)
power consumption, respectively.
In case of the I/O, there are four columns that are shaded blue. These provide the DC and AC power for I/Os for the
core voltage, V and the I/O voltage supply, V
CC
CCIO.
The first three rows show the Quiescent Power for V
device or device with no resource utilization.
V
and V
These are DC power numbers for a blank
CCJ.
CC, CCAUX
Some of the cells are shaded yellow in the tool. These cells are editable cells and users can type in values such as
frequency, activity factors and resource utilization.
The second tab or the Report tab is the summary of the Power View. This report is in text format that provides the
details of the power consumption.
The final pane or the lower pane of the window is the log pane where users can see the log of the various opera-
tions in the Power Calculator.
Figure 12-5. Power Calculator Main Window (Power Report View)
12-7
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator Wizard
The Power Calculator Wizard allows users to estimate the power consumption of a design. This estimation is done
before actually creating the design. The user must understand the logic requirements of the design. The wizard
asks the user to provide these parameters and then estimates the power consumption of the device.
To start the Power Calculator in the wizard mode, go to the File menu and select Wizard. Alternatively, click on the
Wizard button and get the Power Calculator - Wizard window, as shown in Figure 12-6. Select the option Create
a New Project and check the Wizard check box in the Power Calculator Start Project window. Users provide the
project name and the project folder and click Continue. Since power is being estimated before the actual design,
no NCD file is required.
Figure 12-6. Power Calculator Start Project Window (Using the New Project Window Wizard)
The next screen, as shown in Figure 12-7, allows users to select the device family, device and appropriate part
number. After making proper the selections, click Continue. This is shown in Figure 12-7.
12-8
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-7. Power Calculator Wizard Mode Window - Device Selection
In the following screens, as shown in Figures 12-8-12-12, users can select further resources such as I/O types and
provide a clock name, frequency at which the clock in running and other parameters, by selecting the appropriate
resource using the pull-down Type menu:
1. Routing Resources
2. Logic
3. EBR
4. I/O
5. PLL
6. Clock Tree
The numbers in these windows refers to the number of clocks and the index corresponds to each of the clocks. By
default, the clock names are clk_1, clk_2, and so on. The name of each clock can be changed by typing in the
Clock Name text box. For each clock domain and resource users can specify parameters such as frequency, activ-
ity factor, etc. Users can click the Create button for each clock-driven resource using the pull-down Type menu.
These parameters are then used in the Power Type View window (see Figure 12-13) which can be seen by clicking
Finish.
12-9
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-8. Power Calculator Wizard Mode Window - Resource Specification - Logic
Figure 12-9. Power Calculator Wizard Mode Window - Resource Specification - EBR
12-10
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-10. Power Calculator Wizard Mode Window - Resource Specification - PLL
Figure 12-11. Power Calculator Wizard Mode Window - Resource Specification - Routing Resources
12-11
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-12. Power Calculator Wizard Mode Window - Resource Specification - I/Os
Figure 12-13. Power Calculator Wizard Mode - Main Window
12-12
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator – Creating a New Project Without the NCD File
A new project can be started without the NCD file by either using the Wizard (as discussed above) or by selecting
the Create a New Project option in the Power Calculator – Start Project. A project name and project directory
must be provided. After clicking Continue, the Power Calculator main window will be displayed.
However, in this case there are no resources added. The power estimation row for the Routing resources is always
available in the Power Calculator. Users are then asked to add more information like the slice, EBR, I/O, PLL and
clock tree utilization to calculate the power consumption.
For example, to add logic resources (as shown in Figure 12-14), right-click on Logic >> and then select Add in the
menu that pops up.
Figure 12-14. Power Calculator Main Window – Adding Resources
This adds a new row for the logic resource utilization with clock domain as clk_1.
Similarly, other resources like EBR, I/Os, PLLs and routing can be added. Each of these resources is for AC power
estimation and categorized by clock domains.
12-13
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator – Creating a New Project With the NCD File
If the post place and routed NCD file is available, the Power Calculator can use it to import the accurate information
about the design data and resource utilization and calculate the power. When the Power Calculator is started, the
NCD file is automatically placed in the NCD File option, if available in the project directory. Otherwise, the user can
browse to the NCD file in the Power Calculator.
Figure 12-15. Power Calculator Start Project Window – With Post Place and Route NCD File
The information from the NCD file is automatically inserted into the correct rows and the Power Calculator uses the
Clock names from the design, as shown in Figure 12-16.
12-14
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Figure 12-16. Power Calculator Main Window – Resource Utilization Picked Up From the NCD File
12-15
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator – Open Existing Project
The Power Calculator – Start Project window also allows users to open an existing project. Select the option Open
Existing Project and browse to the *.pep project file and click Continue. This opens the existing project in similar
windows as discussed above. This is shown in Figure 12-17.
Figure 12-17. Opening Existing Project in Power Calculator
12-16
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Power Calculator – Total Power
The Power Calculator project created or opened using any of the methods discussed here would allow a user to
calculate the power consumption for the device running with their design.
The estimated power is indicated in the Total section at the bottom of the table as shown in Figure 12-18.
Figure 12-18. Calculated Power in the Power Calculator Main Window
The second and third columns from the left indicate the DC (or static) and AC (or dynamic) power consumption.
The total power consumption for the design can be seen in the same table. Scroll down to the row labeled Total.
Activity Factor
Activity Factor % (or AF%) is defined as the percentage of frequency (or time) that a signal is active or toggling of
the output.
Most of the resources associated with a clock domain are running or toggling at some percentage of the frequency
at which the clock is running. Users are required to provide this value as a percentage under the AF% column in
the Power Calculator tool.
12-17
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Another term used for I/Os is the I/O Toggle Rate or the I/O Toggle Frequency. The AF% is applicable to the PFU,
Routing and Memory Read Write Ports, etc. The activity of I/Os is determined by the signals provided by the user
(in the case of inputs) or as an output of the design (in the case of outputs). So, the rates at which I/Os toggle
define their activity. The Toggle Rate (or TR) in MHz of the output is defined as:
Toggle Rate (MHz) = 1/2 * f
* AF%
MAX
Users are required to provide the TR (MHz) value for the I/O instead of providing the Frequency and AF% in case
of other resources.
The AF can be calculated for each routing resource, output or PFU, however it involves long calculations. The gen-
eral recommendation of a design occupying roughly 30% to 70% of the device is that the AF% used can be
between 15% to 25%. This is an average value that can be seen most of the design. The accurate value of an AF
depends upon clock frequency, stimulus to the design and the final output.
Ambient and Junction Temperature and Airflow
A common method of characterizing a packaged device’s thermal performance is with thermal resistance, . For a
semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a
given reference for each watt of power (heat) dissipated at the die surface. Its units are °C/W.
The most common examples are , thermal resistance junction-to-ambient (in °C/W) and , thermal resis-
JA
JC
tance junction-to-case (also in °C/W). Another factor is , thermal resistance junction-to-board (in °C/W).
JB
Knowing the reference (i.e. ambient, case or board) temperature, the power, and the relevant value, the junction
temperature can be calculated as per following equations.
T = T + * P
(1)
(2)
(3)
J
A
JA
T = T + * P
J
C
JC
T = T + * P
J
B
JB
Where T , T T and T are the junction, ambient, case (or package) and board temperatures (in °C) respectively.
J
A,
C
B
P is the total power dissipation of the device.
is commonly used with natural and forced convection air-cooled systems. is useful when the package has
JA
JC
a high conductivity case mounted directly to a PCB or heatsink. And applies when the board temperature adja-
JB
cent to the package is known.
The Power Calculator utilizes the 25°C junction temperature as its basis to calculate power, per Equation 1 above.
Users can also provide the airflow values (in LFM) and ambient temperature to get a calculated value of the junc-
tion temperature based on the power estimate.
Managing Power Consumption
One of the most critical design factors today is reducing system power consumption, especially for modern hand-
held devices and electronics. There are several design techniques that designers can use to significantly reduce
overall system power consumption. Some of these include:
1. Reducing operating voltage.
2. Operating within the specified package temperature limitations.
3. Using optimum clock frequency reduces power consumption, as the dynamic power is directly proportional
to the frequency of operation. Designers must determine if a portion of their design can be clocked at a
lower rate that will reduce power.
4. Reducing the span of the design across the device. A more closely placed design utilizes fewer routing
resources for less power consumption.
12-18
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
5. Reducing the voltage swing of the I/Os where possible.
6. Using optimum encoding where possible. For example, a 16-bit binary counter has, on average, only 12%
Activity Factor and a 7-bit binary counter has an average of 28% Activity Factor. On the other hand, a 7-bit
Linear Feedback Shift Register could toggle as much as 50% Activity Factor, which causes higher power
consumption. A gray code counter, where only one bit changes at each clock edge, will use the least
amount of power, as the Activity Factor would be less than 10%.
7. Minimize the operating temperature, by the following methods:
a. Use packages that can better dissipate heat. For example, packages with lower thermal impedance.
b. Place heat sinks and thermal planes around the device on the PCB.
c. Better airflow techniques using mechanical airflow guides and fans (both system fans and device
mounted fans).
Power Calculator Assumptions
Following are the assumptions made in the Power Calculator:
1. The Power Calculator tool is based on equations with constants based on room temperature of 25°C.
2. The user can define the Ambient Temperature (Ta) for device Junction Temperature (Tj) calculation based
on the power estimation. Tj is calculated from user-entered Ta and power calculation of typical room tem-
perature.
3. The I/O power consumption is based on output loading of 5pF. Users have ability to change this capacitive
loading.
4. The current version of the Power Calculator allows users to get an estimate of the power dissipation and
the current for each type of power supplies, that are V
V
V
and V
For V
only static
CC, CCIO, CCJ
CCAUX.
CCAUX,
I
values are provided in the Calculator.
CCAUX
Additional V
contributions due to differential output buffers, differential input buffers and reference
CCAUX
input buffers must be added per pair for differential buffers or per pin for reference input buffers according
to the user's design. See the equation given in this technical note for Total DC Power (I ).
CCAUX
5. The nominal V is used by default to calculate the power consumption. Users can choose a lower or
CC
higher V from a list of available values. For example, the nominal V of 1.2V is used by default for the
CC
CC
LatticeECP/EC and LatticeXP families of devices.
6. The current versions also allows users to enter an airflow in Linear Feet per Minute (LFM) along with the
Heat Sink option to calculate the Junction Temperature.
7. The default value of the I/O types for the LatticeEC and LatticeXP devices is LVCMOS12, 6mA.
8. The Activity Factor (AF) is defined as the toggle rate of the registered output. For example, assuming that
the input of a flip-flop is changing at every clock cycle, 100% AF of a flip-flop running at 100MHz is 50MHz.
12-19
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Revision History
Date
Version
01.0
Change Summary
June 2004
Initial release.
01.1
Provided additional description of the assumptions used in the power
model.
July 2004
October 2004
February 2005
01.2
02.0
Updated screen shots for ispLEVER 4.1.
Added support for LatticeXP family throughout.
Added DC and AC power for a dedicated block like DSP for LatticeECP
devices.
May 2005
02.1
Updated the Power Supply Sequencing and Hot Socketing section.
Updated the total DC Power consumption to be sum of Quiescent and
the DC power of resources.
November 2006
September 2007
02.2
02.3
Added calculation of ICCAUX in Power Calculator Equations section.
Document title changed to “Power Estimation and Management for Lat-
ticeECP/EC and LatticeXP Devices”.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
12-20
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
Appendix A. Power Calculator Project Example
This example assumes that you have post Place and Route NCD netlist in the design folder. Click on File > New or
click on the New Project button. The New Project Window will open as shown below.
The various fields are filled in automatically with the project name the same as the ispLEVER project name and the
directory also the same as the design folder. If the Post Place and Route NCD file is available, the NCD File field is
also automatically filled. Users can also browse to the particular location to change the folder where they wish to
create the Power Calculator project. Users can also browse to the NCD file in case it is not available at the root
design folder.
Click Finish. This opens the Main Power Calculator project window, as shown below.
Note that the project window above imports all the resource utilization information from the NCD file. It does not,
however, include information such as the frequency at which the design is operating or the activity factors at which
the various components are toggling. This information is to be filled in by the user.
The top portion of the Power Calculator window shows information such as the device family and device being con-
sidered for power calculation, the V
which is by default the nominal V for the device, and operating conditions.
CC,
CC
Operating conditions users can enter include the ambient temperature, and heat sink available. Users can also
select the air flow values.
There is a grayed box for junction temperature that shows Tj based on the given conditions and the calculated
power.
If we assume the design is running at 100 MHz with a 10% Activity Factor, the final Power Calculator will be as
shown below.
12-21
Power Estimation and Management
for LatticeECP/EC and LatticeXP Devices
Lattice Semiconductor
12-22
LatticeXP sysCONFIG
Usage Guide
September 2008
Technical Note TN1082
Introduction
The memory in the LatticeXP™ FPGAs is built using Flash cells, along with SRAM cells, so that configuration
memory can be loaded automatically at power-up, or at any time the user wishes to update the device. In addition
to “instant-on” capability, on-chip Flash memory greatly increases design security by getting rid of the external con-
figuration bitstream; while maintaining the ease of use and reprogrammability of an SRAM-based FPGA.
While an external device is not required, the LatticeXP does support several external configuration modes. The
available external configuration modes are:
• Slave Serial
• Master Serial
• Slave Parallel
• ispJTAG™ (1149.1 interface)
This guide will cover all the configuration options available for the LatticeXP.
Programming Overview
The LatticeXP contains two types of memory, SRAM and Flash (refer to Figure 13-1). SRAM contains the FPGA
configuration, essentially the “fuses” that define the circuit connections; Flash provides an internal storage space
for the configuration data.
The SRAM can be configured using JTAG, one of the external configuration modes, or by using the data stored in
on-chip Flash. The configuration process consists of SRAM initialization (clear the RAM and the address pointers),
loading the SRAM with the configuration data, and setting the FPGA into user mode (waking up the FPGA).
On-chip Flash can be programmed by using JTAG or by using the external Slave Parallel port. JTAG Flash pro-
gramming can be performed any time the device is powered up. The Slave Parallel port uses the sysCONFIG™
pins and can program the Flash directly or in the background. Direct programming takes place during config mode,
background programming during user mode. The FPGA enters config mode at power up, when the PROGRAMN
pin is pulled low, or when a refresh command is issued via JTAG; it enters user mode when it wakes up, i.e. when
the device begins running user code. These two programming modes, direct and background, will be referred to in
this document as Flash Direct and Flash Background.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
13-1
tn1082_01.9
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Figure 13-1. Programming Block Diagram
ispJTAG 1149.1 TAP
sysCONFIG Port
Port
Master/Slave Serial
,
JTAG 1532
Slave Parallel
Program in seconds
(Slave Parallel Only%
Program in
milliseconds
Mode
SDM
Flash Memory
Space
Program in
microseconds
SRAM Memory
Space
Memory Space
Configuration Pins
The LatticeXP supports two types of sysCONFIG pins, dedicated and dual-purpose. The dual-purpose pins are
available as extra I/O pins if they are not used for configuration.
Two configuration mode pins, along with a programmable option, control the dual-purpose configuration pins. The
configuration mode pins (CFG) are generally hard wired on the PCB and determine which configuration mode will
be used; the programmable option is accessed via preferences in Lattice ispLEVER® design software, or as HDL
source file attributes, and allows the user to protect the configuration pins from accidental use by the user or the
place-and-route software. The LatticeXP devices also support ispJTAG for configuration, including transparent
readback, and for JTAG testing. The following sections describe the functionality of the sysCONFIG and JTAG pins.
Note that JTAG and ispJTAG will be used interchangeably in this document. Table 13-1 is provided for reference.
Table 13-1. Configuration Pins for the LatticeXP Device
Pin Name
CFG[1:0]
I/O Type
Pin Type
Dedicated
Mode Used
Input, weak pull-up
Input, weak pull-up
All
All
PROGRAMN
INITN
Dedicated
Bi-Directional Open Drain, weak pull-up
Bi-Directional Open Drain with weak pull-up or Active Drive
Input or Output
Dedicated
All
DONE
CCLK
Dedicated
All
Dedicated
All
DIN
Input, weak pull-up
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
JTAG
Serial
DOUT/CSON
CSN
Output
Serial or Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Input, weak pull-up
CS1N
Input, weak pull-up
WRITEN
BUSY
Input, weak pull-up
Output, tri-state, weak pull-up
Input or Output
D[0:7]
TDI
Input, weak pull-up
13-2
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-1. Configuration Pins for the LatticeXP Device (Continued)
Pin Name I/O Type
TDO
Pin Type
JTAG
Mode Used
Output
TCK
TMS
Input with Hysteresis
Input, weak pull-up
JTAG
JTAG
Note: Weak pull-ups consist of a current source of 30uA to 150uA. The pull-ups for CFG and PROGRAMN track VCC (core); the pull-ups for
TDI and TMS track VCCJ; all other pull-ups track the VCCIO for that pin.
Dedicated Pins
Following is a description of the dedicated sysCONFIG pins for the LatticeXP device. These pins are used to con-
trol or monitor the configuration process. These pins are used for non-JTAG programming sequences only. The
JTAG pins will be explained later in the ispJTAG Pins section of this document.
CFG[1:0]
The Configuration Mode pins, CFG[1:0], are dedicated inputs with weak pull-ups. The CFG pins are used to select
the configuration mode for the LatticeXP, i.e. what type of device the LatticeXP will configure from. At Power-On-
Reset (POR), or when the PROGRAMN pin is driven low, and depending on the configuration mode selected, dif-
ferent groups of dual-purpose pins will be used for device configuration.
Table 13-2. LatticeXP Configuration Modes
Configuration Mode
Slave Serial
CFG[1]
CFG[0]
0
0
1
1
0
1
0
1
Master Serial
Slave Parallel
Self Download Mode (SDM)
When both CFG pins are high the device will configure itself by reading the data stored in on-chip Flash; this is
referred to as SDM, or Self Download Mode. See the Self-Download section of this document for more information
regarding SDM.
PROGRAMN
The PROGRAMN pin is a dedicated input with a weak pull-up. This pin is used to initiate a non-JTAG SRAM config-
uration sequence. A high to low signal applied to PROGRAMN sets the device into configuration mode. The PRO-
GRAMN pin can be used to trigger configuration at any time. If the device is using JTAG then PROGRAMN will be
ignored until the device is released from JTAG mode.
PROGRAMN should not be low externally during power-up. It should be driven high or rising with the power supply
via an external pullup resistor. Once all power supplies have reached minimum levels, PROGRAMN may be used
to initiate the configuration process.
If the CFG pins are not both high (not in SDM) then the configuration sequence will proceed using the selected
configuration port. If both CFG pins are high (SDM), and the Flash has been programmed, then the configuration
sequence will proceed using the data in on-chip Flash.
If both CFG pins are high (SDM), and the Flash has not been programmed, the configuration sequence will pause
and wait for the Flash done bit to be programmed. Once the Flash has been programmed, and PROGRAMN is
brought high, the configuration sequence will continue.
INITN
The INITN pin is a dedicated bi-directional open drain pin with a weak pull-up. INITN is capable of driving a low
pulse out as well as detecting a low pulse driven in.
13-3
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
During SRAM configuration from an external device INITN going low indicates that the SRAM is being initialized;
INITN going high indicates that the FPGA is ready to accept configuration data. To delay configuration the INITN
pin can be held low externally. The device will not enter configuration mode as long as the INITN pin is held low.
After configuration has started INITN is used to indicate a bitstream error. The INITN pin will be driven low if the
calculated CRC and the configuration data CRC do not match; DONE will then remain low and the LatticeXP will
not wake up.
During SRAM configuration from on-chip Flash INITN is not used or monitored and is driven low.
When programming on-chip Flash the INITN pin is only used to indicate an error during erase or program. If an
error occurs INITN will be driven low. During Flash Direct programming an error will prevent the FPGA from config-
uring from the Flash, during Flash Background programming an error will not affect the configuration already run-
ning in SRAM.
DONE
The DONE pin is a dedicated bi-directional open drain with a weak pull-up (default), or an actively driven pin.
DONE will be driven low when the device is in configuration mode and the internal DONE bit is not programmed.
When the INITN and PROGRAMN pins go high (or in the case of SDM just PROGRAMN goes high), and the inter-
nal DONE bit is programmed, the DONE pin will be released (or driven high, if it is an actively driven pin). The
DONE pin can be held low externally and, depending on the wake-up sequence selected, the device will not
become functional until the DONE pin is externally brought high.
Reading the DONE bit is a good way for an external device to tell if the FPGA is configured.
When using JTAG to configure SRAM the DONE pin is driven by the boundary scan cell, so the state of the DONE
pin has no meaning during JTAG configuration.
CCLK
CCLK is a dedicated bi-directional pin; direction depends on whether a Master or Slave mode is selected. If a Mas-
ter mode is selected via the CFG pins, the CCLK pin will become an output pin; otherwise CCLK is an input pin.
If the CCLK pin becomes an output, the internal programmable oscillator is connected to the CCLK and is driven
out to slave devices. CCLK will stop 120 clock cycles after the DONE pin is brought high and the device wake-up
sequence completed. The extra clock cycles ensure that enough clocks are provided to wake-up other devices in
the chain. When stopped, CCLK becomes an input (tri-stated output). CCLK will restart (become an output) on the
next configuration initialization sequence.
The MCCLK_FREQ parameter (see ispLEVER software documentation) controls the CCLK master frequency (see
Table 13-3). Until changed during configuration CCLK will be 2.5 MHz. One of the first things loaded during config-
uration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the selected
value using a glitchless switch. Care should be exercised not to exceed the frequency specification of the slave
devices or the signal integrity capabilities of the PCB layout.
Table 13-3. Master Clock Frequency Selections
CCLK (MHz)
CCLK (MHz)
CCLK (MHz)
2.5
4.3
5.4
6.9
8.1
9.2
10.0
13
15
20
26
30
34
41
45
51
55
60
130
-
-
Note: Default is the lowest frequency, 2.5 MHz.
13-4
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-4. Maximum Configuration Bits
Density
Bitstream Size (Mb)
LFXP3
LFXP6
1
1.6
2.8
4
LFXP10
LFXP15
LFXP20
4.9
Table 13-5. SDM Pin Usage
Configuration Mode
CFG[1:0]
SDM (Self Download Mode)
[1, 1]
Flash Programming Mode
Port
Direct
Background
Direct
Background
User
sysCONFIG
ispJTAG1
TAP
Pins
CCLK, CSN, CS1N, WRITEN, D[0:7]
User I/O States
PROGRAMN
BUSY
Tristate
User
Keep at High
Status
BSCAN
Keep At High2
Status
Not Used
INITN
Pass/Fail
Done
Pass/Fail
Not Used
ON
Not Used3
Keep at High4
DONE
PERSISTENT Bit
Don’t Care
Don’t Care
1. ispJTAG can be used to program the Flash regardless of the state of the CFG pins, however only if the device is in SDM can Flash be used
to configure SRAM
2. The state of the PROGRAMN pin is ignored by the device during JTAG Flash programming but the pin should be held high as a low will
inhibit Flash to SRAM data transfer.
3. The state of the INITN pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the
internal pull-up.
4. The state of the DONE pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the
internal pull-up as a low can keep the device from waking up.
Table 13-6. Pins Used for Memory Access
CFG Pins
On-Chip Flash
Write or Read2
TAP
SRAM
Readback2, 3
1
X1
1
0
X1
1
CFG Mode
JTAG
Write From
TAP
TAP
sysCONFIG
sysCONFIG
N/A5
SDM
sysCONFIG
N/A4
On-Chip Flash
sysCONFIG
sysCONFIG
sysCONFIG
1
0
Slave Parallel
Master Serial
Slave Serial
0
1
N/A4
N/A4
0
0
N/A5
1. The ispJTAG port is always available independent of the CFG setting.
2. Readback can only be disabled by programming the security bit.
3. Set the PERSISTENT bit to ON to retain the sysCONFIG port for background readback.
4. Flash access is not allowed in this mode.
5. SRAM readback is not allowed in this mode.
Programming Sequence
There are three types of programming, SRAM, Flash Direct, and Flash Background. This section goes through the
process for each showing how the dedicated pins are used.
SRAM: When not using SDM (Self Download Mode, on-chip Flash) to program SRAM the sequence begins when
the internal power-on reset (POR) is released or the PROGRAMN pin is driven low (see Figure 13-2). The Lattic-
eXP then drives INITN low, tri-states the I/Os, and initializes the internal SRAM and control logic. When this is com-
13-5
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
plete, if PROGRAMN is high, INITN will be released. If INITN is held low externally the LatticeXP will wait until it
goes high. When INITN goes high the LatticeXP begins looking for the configuration data preamble on the selected
configuration port, as determined by the CFG pins.
Once configuration is complete the internal DONE bit is set, the DONE pin goes high, and the FPGA wakes up
(enters user mode). If a CRC error is detected when reading the bitstream INITN will go low, the internal DONE bit
will not be set, the DONE pin will stay low, and the LatticeXP will not wake up.
When using SDM to program SRAM the sequence is similar but INITN is not used or monitored (INITN is driven
low). The sequence begins when the internal power-on reset (POR) is released or the PROGRAMN pin is driven
low (see Figure 13-2). The LatticeXP then tri-states the I/Os and initializes the internal SRAM and control logic.
When initialization is complete the LatticeXP begins loading configuration data from on-chip Flash.
As with non-SDM, once configuration is complete the internal DONE bit is set, the DONE pin goes high, and the
FPGA wakes up (enters user mode).
Figure 13-2. SRAM Configuration Timing Diagram
CCLK
PROGRAMN
INITN
DONE
Initialize
Configure
Wake-Up
Flash Direct: Flash Direct programming is possible using the Slave Parallel port if both CFG pins are high (SDM).
Serial ports may not be used to program the Flash. Flash Direct is only valid if the DONE pin is low (the SRAM is
blank).
The sequence begins when the PROGRAMN pin is driven low. The LatticeXP tri-states the I/Os, and initializes the
internal SRAM and control logic. The LatticeXP waits for WRITEN and both CSN and CS1N pins to go low and
then looks for the programming preamble followed by the erase, program, and verify commands. Data is written
and read on the D[0:7] pins.
Once the Flash is programmed the PROGRAMN pin can be brought high to start the transfer from Flash to SRAM.
Flash Background: Flash Background programming is possible using the Slave Parallel port if both CFG pins are
high (SDM). Serial ports may not be used to program the Flash. Flash Background will not disturb the FPGA's
present configuration.
Flash Background programming may be used in both config mode and user mode (Done bit = 0 or 1). To support
Flash Background programming in user mode the PERSISTENT bit must be set to ON.
When WRITEN goes low, and CSN and CS1N are low, the FPGA will wait for the preamble and then look for the
proper commands. A low on INITN indicates an error during a Flash erase or program. Data is written and read on
the D[0:7] pins.
After programming the Flash the user may toggle the PROGRAMN pin to transfer the Flash data to SRAM.
13-6
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Figure 13-3. Flash Programming Timing Diagram
FLASH to SRAM upload happens if DONE
fuse is programmed and CFG[1:0] are high.
CCLK
PROGRAMN
INITN
LOW to select Direct Programming. High to select Background Programming.
Drive to LOW if error happens
CSN
WRITEN
D[0:7]
BUSY
CS1N
Dual-Purpose sysCONFIG Pins
The following is a list of the dual-purpose sysCONFIG pins. These pins are available as general purpose I/O
(GPIO) after configuration. If a dual-purpose pin is to be used both for configuration and as a GPIO, the user must
adhere to the following:
• The I/O type must remain the same. For example, if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
tion it must remain a 3.3V CMOS pin as GPIO.
• The user must select the correct CONFIG_MODE setting and set the PERSISTENT bit to OFF in order to use
the dual-purpose sysCONFIG pins as GPIO after configuration. These settings can be found in the ispLEVER
Design Planner (formerly called the Preference Editor).
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
Also, if slave parallel configuration mode is not being used then one or both of the parallel port chip selects (CSN,
CS1N) must be high or tri-stated during configuration.
After configuration, these pins, if not used as GPIO, are tri-stated and weakly pulled up.
DIN
DIN (data input) is a dual-purpose input with a weak pull-up. DIN is used for the serial bitstream configurations.
DOUT/CSON
The DOUT/CSON is a dual-purpose output that is used in Chain Mode (daisy chaining). This pin can be used in
serial or parallel modes and has two uses.
For serial and parallel configuration modes, when BYPASS Chain Mode is selected, this pin will become DOUT. In
a serial configuration mode, when the device becomes fully configured, a BYPASS instruction will be executed and
the data on DIN will be presented on the DOUT pin through a bypass register. In this way the serial data is passed
to the next device. In parallel configuration mode the data will be serialized and then presented on DOUT; D[0]
(MSb) will be shifted out first followed by D[1], D[2] and so on to D[7] (LSb).
For parallel configuration mode, when FLOW_THROUGH Chain Mode is selected, this pin will become Chip Select
Out (CSON). In FLOW_THROUGH Chain Mode, when the device is fully configured (the internal DONE bit goes
13-7
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
high), the Flow-Through instruction will be executed and the CSON pin will be driven low to enable the next
device’s chip select pin.
The DOUT/CSON bypass register will drive out a high upon power up and continue to do so until the execution of
the Bypass or Flow-Through instruction within the bitstream.
Chain Mode is not supported when configuring from internal Flash (SDM).
CSN and CS1N
Both CSN and CS1N are active low input pins with weak pull-ups and are used in parallel mode only. These inputs
are OR’ed and used to enable the D[0:7] data pins to receive or output a byte of data.
In non-SDM, when CSN or CS1N are high, the D[0:7], INITN, and BUSY pins are tri-stated. CSN and CS1N are
interchangeable when controlling the D[0:7], INITN, and BUSY pins.
When SDM is selected and CSN or CS1N are high, the D[0:7], INITN, and BUSY pins are tri-stated. If the Flash
has not been programmed a high on both CSN and CS1N will cause the LatticeXP to drive the INITN pin low to
reset the internal FPGA configuration circuitry. The LatticeXP will then monitor D[0:7] waiting for the configuration
preamble. CSN and CS1N are interchangeable when controlling the D[0:7], INITN, and BUSY pins.
During configuration or programming through the parallel sysCONFIG interface, CSN and SCIN should remain low
during the entire process. Deassertion of either of these signals will interrupt the process, requiring a new cycle to
properly transfer the data.
If SRAM or Flash will need to be accessed while the device is in user mode (the DONE pin is high) then the PER-
SISTENT preference must be set to ON in order to preserve these pins as CSN and CS1N.
WRITEN
The WRITEN pin is an active low input with a weak pull-up and used for parallel mode only. The WRITEN pin is
used to determine the direction of the data pins D[0:7]. The WRITEN pin must be driven low when a byte of data is
to be clocked into the device and driven high when data is to be read from the device.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve this pin as WRITEN.
BUSY
In parallel mode the BUSY pin is a tri-stated output with a weak pull-up. The BUSY pin will be driven low by the Lat-
ticeXP device only when it is ready to receive a byte of data from the D[0:7] pins or a byte of data is ready for read-
ing. The BUSY pin can be used to support asynchronous peripheral mode (handshaking). This pin is used to
indicate that the LatticeXP needs extra time to execute a command.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve this pin as BUSY.
D[0:7]
The D[0:7] pins support slave parallel mode only. The D[0:7] pins are tri-statable bi-directional I/O pins used for
data write and read. When the WRITEN signal is low, and the CSN and CS1N pins are low, the D[0:7] pins become
data inputs. When the WRITEN signal is driven high, and the CSN and CS1N pins are low, the D[0:7] pins become
data outputs. If either CSN or CS1N is high D[0:7] will be tri-state. D[0] is the most significant bit and D[7] is the
least significant bit.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve these pins as D[0:7].
Care must be exercised during read back of EBR or PFU memory. It is up to the user to ensure that reading these
RAMs will not cause data corruption, i.e. these RAMs may not be read while being accessed by user code.
13-8
Lattice Semiconductor
ispJTAG Pins
LatticeXP sysCONFIG Usage Guide
The ispJTAG pins are standard IEEE 1149.1 TAP (Test Access Port) pins. The ispJTAG pins are dedicated pins and
are always accessible when the LatticeXP device is powered up. When programming the SRAM via ispJTAG the
dedicated programming pins, such as DONE, cannot be used to determine programming progress. This is because
the state of the boundary scan cell will drive the pin, per JTAG 1149.1, rather than normal internal logic.
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state.
TDI
The Test Data Input pin is used to shift in serial test instructions and data. An internal pull-up resistor on the TDI pin
is provided. The internal resistor is pulled up to V
CCJ.
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
the state of TMS, a transition will be made in the TAP controller state machine. An internal pull-up resistor on the
TMS pin is provided. The internal resistor is pulled up to V
CCJ.
TCK
The test clock pin, TCK, provides the clock to run the TAP controller, which loads and unloads the data and instruc-
tion registers. TCK can be stopped in either the high or low state and can be clocked at frequencies up to the fre-
quency indicated in the device data sheet. The TCK pin supports the value is shown in the DC parameter table of
the data sheet. The TCK pin does not have a pull-up. A pull-down on the PCB of 4.7 K is recommended to avoid
inadvertent clocking of the TAP controller as V ramps up.
CC
Optional TRST
Test Reset, TRST, in not supported on the LatticeXP device.
VCCJ
JTAG V (V
) supplies independent power to the JTAG port to allow chaining with other JTAG devices at a com-
CCJ
CC
mon voltage. V
must be connected even if JTAG is not used. This voltage may also power the JTAG download
CCJ
cable. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V.
Please see In-System Programming Design Guidelines for ispJTAG Devices, available on the Lattice web site at
www.latticesemi.com, for further JTAG chain information.
Configuration and JTAG Voltage Levels
All of the control pins and programming pins default to LVCMOS. CFG and PROGRAMN are linked to V (core);
CC
TCK, TDI, TDO, and TMS track V
; all other pins track the V
for that pin.
CCJ
CCIO
Configuration Modes and Options
The LatticeXP device supports several configuration modes, utilizing serial or parallel data inputs, as well as self-
configuration. On power up, or upon driving the PROGRAMN pin low, the CFG[1:0] pins are sampled to determine
the mode that will be used to configure the LatticeXP device. The CFG pins are generally hard wired on the PCB
and determine which port the device will use to retrieve its configuration data. CONFIG_MODE is a programmable
option accessed via preferences in Lattice ispLEVER design software, or as HDL source file attributes, and allow
the user to protect the configuration pins from accidental use by the user or the place-and-route software.
Table 13-7 shows the mode, CFG[1:0], and the software CONFIG_MODE parameter. The following sections break-
down each configuration mode.
13-9
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-7. Configuration Modes for the LatticeXP
Configuration Mode
Slave Serial (no overload option)
Slave Serial (Bypass ON)
CFG[1] CFG[0]
CONFIG_MODE1
Chain Mode2
0
0
0
0
Slave_Serial
Slave_Serial
Master_Serial
Master_Serial
Slave_Parallel
Slave_Parallel
Slave_Parallel
None/Slave_Parallel4
None5
Disable
Bypass
Disable
Bypass
Disable
Bypass
Master Serial (no overload option)
Master Serial (Bypass ON)
0
1
0
1
Slave Parallel (no overload option)
Slave Parallel (Bypass ON)
1
0
1
0
Slave Parallel (Flow Through ON)
Self Download Mode (SDM)
ispJTAG (1149.1 interface)
1
0
Flowthrough
Disable
1
X3
1
X3
1. CONFIG_MODE can be found in the ispLEVER Preference Editor.
2. CHAIN_MODE can be found in the ispLEVER bitgen options (right-click on Generate Bitstream Data and click on Properties).
3. The ispJTAG interface is always on.
4. If ispJTAG is used exclusively to access the on-chip Flash and SRAM select None, if Slave Parallel is used to access the Flash and/or the
SRAM select Slave_Parallel.
5. The None selection indicates that no dual-purpose pins are reserved for configuration. This is the default.
Configuration Options
Several configuration options are available for each CONFIG_MODE.
• When daisy chaining multiple FPGA devices a configuration overflow option is provided. Configuration data over-
flow occurs once the first FPGA has completed its download, the remaining data in the configuration storage
device is then output through the first FPGA to subsequent FPGAs. Configuration data overflow is not supported
when using SDM.
• When using a master clock, the master clock frequency can be set.
• A security bit is provided to prevent SRAM or Flash readback.
By setting the proper parameters in the Lattice ispLEVER design software the selected configuration options are
set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take
effect. These options are described in the following sections.
Bypass Overflow Option
The Bypass overflow option can be used in serial and parallel device daisy chains. When the first device has com-
pleted configuration data download, and the Bypass option preference is selected, data coming into the device
configuration port on the sysCONFIG pins will overflow serially out of DOUT and into the DIN pin of the next slave
serial device. The Bypass option is selected in ispLEVER by right-clicking on Generate Bitstream Data and clicking
on Properties.
In serial configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option connects the DIN pin to DOUT pin via a bypass register. The bypass register is initialized with a ‘1’ at the
beginning of configuration.
In parallel configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option causes the data coming from D[0:7] to be serially shifted to DOUT. The serialized data is shifted to DOUT
through the bypass register. D[0] of the byte wide data will be shifted out first followed by D[1], D[2] and so on.
Once the Bypass option starts, the device will remain in Bypass until the wake up sequence completes.
Flow-Though Overflow Option
The Flow-Through overflow option is used in parallel mode only. The Flow-Through option causes the CSON pin to
go low when the FPGA has received all of its configuration data, driving the chip select on the next device in the
daisy chain so that it will start reading configuration data from D[0:7]. The Flow Through Option will also tri-state
13-10
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
the D[0:7], INITN, and BUSY pins, once all of the configuration data has been received, in order to prevent interfer-
ence with other devices in the daisy chain.
Once the Flow-Through option starts, the device will remain in Flow-Through until the wake up sequence com-
pletes.
Master Clock
If the CFG pins indicate that this is a Master device the CCLK pin will become an output with the frequency set by
the user. The default Master Clock Frequency is 2.5 MHz.
The user can determine the Master Clock frequency by setting the MCCLK_FREQ preference in the Lattice isp-
LEVER design software. One of the first things loaded during configuration is the MCCLK_FREQ parameter; once
this parameter is loaded the frequency changes to the selected value using a glitchless switch. Care should be
exercised not to exceed the frequency specification of the slave devices or the signal integrity capabilities of the
PCB layout. See Table 13-3 for available options.
Security Bit
Setting the security bit prevents readback of the SRAM and Flash from JTAG or the sysCONFIG pins. When the
security bit is set the only operations available are erase and write. The security bit is updated as the last operation
of SRAM configuration or Flash programming. By using on-chip Flash, and setting the security bit, the user can
create a very secure device.
The security bit is accessed via the Preference Editor in ispLEVER design software.
More information on device security can be found in the document FPGA Design Security Issues: Using the
ispXPGA Family of FPGAs to Achieve High Design Security, available on the Lattice Semiconductor web site at
www.latticesemi.com.
Slave Serial Mode
Configuration Mode
Slave Serial (no overload option)
Slave Serial (Bypass ON)
CFG[1]
CFG[0]
CONFIG_MODE
Slave_Serial
Chain Mode
Disable
0
0
0
0
Slave_Serial
Bypass
The CCLK pin becomes an input and data at DI is clocked on the rising edge of CCLK. After the device is fully con-
figured, if the Bypass option has been set, data sent to DI will be presented to the next device via the DOUT pin as
shown in Figure 13-4.
Master Serial Mode
Configuration Mode
Master Serial (no overload option)
Master Serial (Bypass ON)
CFG[1]
CFG[0]
CONFIG_MODE
Master_Serial
Master_Serial
Chain Mode
Disable
0
0
1
1
Bypass
In Master Serial mode the device will drive CCLK out to the Slave Serial devices in the chain and the serial PROM
that will provide the bitstream. The Master device accepts the data at DIN on the rising edge of CCLK. The Master
Serial device starts driving CCLK at the beginning of the configuration and continues to drive CCLK until the exter-
nal DONE pin is driven high and an additional 100 to 500 clock cycles have been generated. The CCLK frequency
on power up defaults to 2.5 MHz. The master clock frequency default remains unless a new clock frequency is
loaded from the bitstream.
If a Master Serial device is daisy chained with Slave Serial devices the Bypass option should be used so that over-
flow configuration data is directed to the DOUT pin.
Figure 13-4 shows a serial daisy chain. The daisy chain allows multiple Lattice FPGA devices to be configured
using one configuration storage device. The center device operates in Master Serial with the Bypass option set
13-11
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
while the other Lattice FPGA devices in the daisy chain operate in Slave Serial mode. The RESET/OE pin of the
PROM is driven by INITN while the Chip Select pin is driven by the DONE pin of the devices.
Figure 13-4. Master and Slave Serial Daisy Chain
LatticeXP
LatticeXP
Serial
Master Serial
Slave Serial
PROM
CLK
CCLK
DIN
CCLK
DIN
DOUT
DOUT
DATA
CS
DONE
INITN
DONE
INITN
RESET/OE
CFG0
CFG1
CFG1
CFG0
Master Program
PROGRAMN
PROGRAMN
Slave Parallel Mode
Configuration Mode
Slave Parallel (no overload option)
Slave Parallel (Bypass ON)
CFG[1]
CFG[0]
CONFIG_MODE
Chain Mode
Disable
1
1
1
0
0
0
Slave_Parallel
Slave_Parallel
Slave_Parallel
Bypass
Slave Parallel (Flow Through ON)
Flowthrough
In Slave Parallel mode a host system sends the configuration data in a byte-wide stream to the device. The CCLK,
CSN, CS1N, and WRITEN pins are driven by the host system. The Slave Parallel configuration mode allows multi-
ple devices to be chained in parallel, as shown in Figure 13-5.
WRITEN, CSN, and CS1N must be held low to write to the device; data is input from D[0:7]. Slave Parallel mode
can also be used for readback of the internal configuration. By driving the WRITEN pin low, and CSN and CS1N
low, the device will input the readback instructions on the D[0:7] pins; WRITEN is then driven high and data read on
D[0:7]. In order to support readback the PERSISTENT bit in ispLEVER’s Preference Editor must be set to ON.
The Slave Parallel mode can support two types of overflow, Bypass and Flow-Through. If the Bypass option is set,
after the first device has received all of its configuration data, the data presented to the D[0:7] pins will be serialized
and bypassed to the DOUT pin. If the Flow-Through option is set, after the first device has received all of its config-
uration data, the CSON signal will drive the following parallel mode device’s chip select low as shown in Figure 13-
5.
To support asynchronous configuration, where the host may provide data faster than the FPGA can accept it, Slave
Parallel mode can use the BUSY signal. By driving the BUSY signal high the Slave Parallel device tells the host to
pause sending data. See Figure 13-6.
13-12
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Figure 13-5. Master and Slave Parallel Daisy Chain
LatticeEC
Master Parallel
LatticeXP
Slave Parallel
Serial
PROM
CLK
CCLK
CCLK
D[0:7]
DONE
INITN
WRITEN
CSN
D[0:7]
DATA[0:7]
CS
DONE
INITN
RESET/OE
WRITEN CSOUTN
*2
*1
CSN
CS0N
CS1N
CFG2
CFG1
*1,2
Bypass
Reset
CS1N
CFG1
PROGRAMN CFG0
PROGRAMN CFG0
Master Program
*1 Both CS pins can be held or driven low
*2 An option that allows the Bypass and Flow-Through option to be reset
Figure 13-6. Asynchronous Usage of Slave Parallel Configuration Mode
Data[0:7]
INIT
DONE
CLOCK
LatticeXP
Slave Parallel
LatticeXP
Slave Serial
(Asynchronous%
CCLK
CCLK
D[0:7]
DOUT
DIN
DOUT
DONE
DONE
INITN
INITN
CFG1
CFG0
BUSY
WRITEN
CSN
PROGRAMN
*2
*1
CFG1
CFG0
CSN
*1,2
Bypass
Reset
CS1N
PROGRAMN
PROGRAM
WRITE
BUSY
*1 Both CS pins can be held or driven low
*2 An option that allows the Bypass and Flow-Through option to be reset
13-13
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Figure 13-6 shows an asynchronous peripheral write sequence using the Bypass option. To send configuration
data to a device, the WRITEN signal has to be asserted. During the write cycle, the BUSY signal provides hand-
shaking between the host system and the LatticeXP device. When BUSY is low the device is ready to read a byte
of data at the next rising edge of CCLK. The BUSY signal is set high when the device reads the data and the device
requires extra clock cycles to process the data.
Self Download Mode
Configuration Mode
CFG[1]
CFG[0]
CONFIG_MODE
Chain Mode
Self Download Mode (SDM)
1
1
None/Slave_Parallel
Disable
Self Download Mode (SDM) allows the FPGA to configure itself without using any external devices, and because
the bitstream is not exposed this is also a very secure configuration mode. The user may access on-chip Flash
using ispJTAG or the slave parallel port on the sysCONFIG pins.
JTAG may access the on-chip Flash any time the device is powered up, without disturbing device operation. JTAG
may also read and write the configuration SRAM. If access to the on-chip Flash and SRAM is limited to JTAG then
CONFIG_MODE should be set to None, freeing the dual-purpose pins for use as general purpose I/O.
The slave parallel port can also be used to access on-chip Flash. If the slave parallel port is used then
CONFIG_MODE should be set to Slave_Parallel. WRITEN, CSN, and CS1N must be held low to write to on-chip
Flash; data is input from D[0:7]. The slave parallel port can also be used for readback of both Flash and SRAM. By
driving the WRITEN pin low, and CSN and CS1N low, the device will input the readback instructions on the D[0:7]
pins; a bit in the read command will determine if the read is directed to Flash or SRAM. In order to support read-
back while the device is in user mode (the DONE pin is high) the PERSISTENT bit in ispLEVER’s Preference Editor
must be set to ON.
SDM does not support overflow.
ispJTAG Mode
Configuration Mode
CFG[1]
CFG[0]
CONFIG_MODE
Chain Mode
ispJTAG (1149.1 interface)
X
X
None
The LatticeXP device can be configured through the ispJTAG port. The ispJTAG port is always on and available,
regardless of the configuration mode selected. A CONFIG_MODE of None can be selected in the Lattice isp-
LEVER design software to tell the place and route tools that the JTAG port will be used exclusively, i.e. the serial
and parallel ports will not be used. Setting the CONFIG_MODE to None allows software to use all of the dual-pur-
pose pins as general purpose I/Os.
ISC 1532
Configuration through the ispJTAG port conforms to the IEEE 1532 Standard. The Boundary Scan cells take con-
trol of the I/Os during any 1532 mode instruction. The Boundary Scan cells can be set to a pre-determined value
whenever using the JTAG 1532 mode. Because of this the dedicated pins, such as DONE, cannot be relied upon
for valid configuration status.
13-14
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Transparent Readback
The ispJTAG Transparent Readback mode allows the user to read the content of the device SRAM or Flash while
the device remains in a functional state. Care must be exercised when reading EBR and distributed RAM, as it is
possible to cause conflicts with accesses from the user design (causing possible data corruption).
The I/O and non-JTAG configuration pins remain active during a Transparent Readback. The device enters the
Transparent Readback mode through a JTAG instruction.
Boundary Scan and BSDL Files
BSDL files for this device can be found on the Lattice web site at www.latticesemi.com. The boundary scan ring
covers all of the I/O pins, as well as the dedicated and dual-purpose sysCONFIG pins.
Power Save Mode
An I/O Power Save mode option is available for the LatticeXP device and will deactivate portions of the I/O cell driv-
ers. This is only valid when using comparator type inputs pins (pins that use VREF), like HSTL, SSTL, etc.
Power Save mode limits some of the functionality of Boundary Scan. For Boundary Scan testing it is recommended
that the I/O Power Save mode be set to OFF so that all of the I/Os will be fully functional.
Wake Up Options
When configuration is complete (the SRAM has been loaded), the device should wake up in a predictable fashion.
The following selections determine how the device will wake up. Two synchronous wake up processes are avail-
able. One automatically wakes the device up when the internal Done bit is set regardless of whether the DONE pin
is held low externally or not, the other waits for the DONE pin to be driven high before starting the wake up process.
The DONE_EX preference determines whether the external DONE pin will control the synchronous wake up.
Wake Up Sequence
Table 13-8 provides a list of the wake up sequences supported by the LatticeXP.
Table 13-8. Wake Up Sequences Supported by LatticeXP
Sequence
Phase T0
Phase T1
Phase T2
GOE, GWDIS, GSR
GWDIS, GSR
Phase T3
1
2
DONE
DONE
DONE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
3
GOE, GWDIS, GSR
4
GOE
5
GOE
GWDIS, GSR
GSR
6
GOE
GWDIS
7
GOE
GSR
GWDIS
8
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
9
GOE, GWDIS, GSR
GOE
10
11
12
13
14
15
16
17
18
19
20
GWDIS, GSR
GOE
GWDIS, GSR
GOE, GWDIS, GSR
DONE
GOE, GWDIS, GSR
GOE
DONE
DONE
GWDIS, GSR
GSR
GOE, GWDIS
GWDIS
DONE
DONE
GOE, GSR
GOE
GWDIS, GSR
GOE, GSR
DONE
DONE
GWDIS
DONE
GOE, GWDIS, GSR
GOE, GWDIS, GSR
13-15
DONE
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-8. Wake Up Sequences Supported by LatticeXP (Continued)
Sequence
Phase T0
Phase T1
Phase T2
GWDIS, GSR
Phase T3
21 (Default)
GOE
DONE
DONE
DONE
DONE
DONE
22
23
24
25
GOE, GWDIS
GWDIS
GSR
GOE, GSR
GOE
GWDIS, GSR
GOE, GSR
GWDIS
Figure 13-7. Wake Up Sequence to Internal Clock
CLK
DONE BIT
GLOBAL OUTPUT ENABLE
GLOBAL SET/RESET
GLOBAL WRITE DISABLE
DONE PIN
T0
T1
T2
T3
Synchronous to Internal Done Bit
If the LatticeXP device is the only device in the chain, or the last device in a chain, the wake up process should be
initiated by the completion of the configuration. Once the configuration is complete, the internal Done bit will be set
and then the wake up process will begin.
Synchronous to External DONE Signal
The DONE pin can be selected to delay wake up. If DONE_EX is true then the wake up sequence will be delayed
until the DONE pin is high. The device will then follow the WAKE_UP sequence selected.
Software Selectable Options
In order to control the configuration of the LatticeXP device beyond the default settings, software preferences are
used. Table 13-9 is a list of the preferences with their default settings.
13-16
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-9. Software Preference List for the LatticeXP
Preference Name
PERSISTENT
Default Setting [List of All Settings]
OFF [off, on]
NONE[SLAVE_PARALLEL, SLAVE_SERIAL, MASTER_SERIAL,
NONE]
CONFIG_MODE
DONE_OD
ON [off, on]
DONE_EX
OFF [off, on]
MCCLK_FREQ
CONFIG_SECURE
Lowest Frequency (see Table 13-3)
OFF [off, on]
21 (DONE_EX = off)
4 (DONE_EX = on)
WAKE_UP
PWRSAVE
OFF [off, on]
PERSISTENT Bit
In order to use the sysCONFIG port while in user mode to read SRAM or Flash memory, the PERSISTENT bit must
be set to ON. PERSISTENT = ON preserves all of the sysCONFIG pins so the FPGA can be accessed by an exter-
nal device at any time. PERSISTENT = ON lets the software know that all of the dual-purpose configuration pins
are reserved and NOT available for use by the fitter or the user. PERSISTENT = ON reserves all of the dual-pur-
pose sysCONFIG pins, without regard to CONFIG_MODE.
Configuration Mode
The device knows which physical sysCONFIG port will be used by reading the state of the CFG[1:0] pins, but the
fitter software also needs to know which port will be used. The fitter cannot sample the configuration pins so the
user must tell the fitter by selecting the proper CONFIG_MODE. CONFIG_MODE tells the fitter which sysCONFIG
pins are not available for use as user I/O.
There are several additional configuration options, such as overflow, that are set by software. These options are
selected by clicking Properties under Generate Bitstream Data in ispLEVER. If either overflow option is selected,
then the DONE_EX and WAKE_UP selections will be set to correspond (see Table 13-10). Refer to the Configura-
tion Modes and Options section of this document for more details.
Table 13-10. Overflow Option Defaults
Overflow Option
DONE_EX Preference
WAKE_UP Preference
Default 21 (user selectable 1 through 25)
Default 21 (user selectable 1 through 25)
Default 4 (User selectable 1 through 7)
Off
Off
Off (Default)
On
On (either)
On (automatically set by software)
DONE Open Drain
The “DONE_OD” preference allows the user to configure the DONE pin as an open drain pin. The “DONE_OD”
preference is only used for the DONE pin. When the DONE pin is driven low, internally or externally, this indicates
that configuration is not complete and the device is not ready for the wake up sequence. Once configuration is com-
plete, with no errors, and the device is ready for wake up, the DONE pin must be driven high. For other devices to
be able to control the wake up process an open drain configuration is needed to avoid contention on the DONE pin.
The “DONE_OD” preference for the DONE pin defaults to ON. The DONE_OD preference is automatically set to
ON if the DONE_EX preference is set to ON. See Table 13-11 for more information on the relationship between
DONE_OD and DONE_EX.
DONE External
The LatticeXP device can wake up on its own after the Done bit is set or wait for the DONE pin to be driven high
externally. Set DONE_EX = ON to delay wake up until the DONE pin is driven high by an external signal synchro-
13-17
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
nous to the clock; select OFF to synchronously wake up when the internal Done bit is set and ignore any external
driving of the DONE pin. The default is DONE_EX = OFF. If DONE_EX is set to ON, DONE_OD will be set to ON.
If an external signal is driving the DONE pin it should be open drain as well (an external pull-up resistor may need
to be added). See Table 13-11 for more information on the relationship between DONE_OD and DONE_EX.
Table 13-11. Summary of DONE pin Preferences (Preferences)
DONE_EX
OFF
Wake Up Process
External DONE ignored
External DONE low delays
DONE_OD
User selected
ON
Set to Default (ON)
Master Clock Selection
When the user has determined that the LatticeXP will be a master configuration device (by properly setting the
CFG[1:0] pins), and therefore provide the source clocking for configuration, the CCLK pin becomes an output with
the frequency set by the value in MCCLK_FREQ. At the start of configuration the device operates at the default
Master Clock Frequency of 2.5 MHz. Some of the first bits in the configuration bitstream are MCCLK_FREQ, once
these are read the clock immediately starts operating at the user-defined frequency. The clock frequency is
changed using a glitchless switch.
Security
When CONFIG_SECURE is set to ON, NO read back operation will be supported through the sysCONFIG or
ispJTAG port of the general contents. The ispJTAG DeviceID area is readable and not considered securable.
Default is OFF.
Wake Up Sequence
The WAKE_UP sequence controls three internal signals and the DONE pin. The DONE pin will be driven after con-
figuration and prior to user mode. See the Wake Up Sequence section of this document for an example of the
phase controls and information on the wake up selections. The default setting for the WAKE_UP preference is
determined by the DONE_EX setting.
Wake Up with DONE_EX = Off (Default Setting)
The WAKE_UP preference for DONE_EX = OFF (default) supports the user selectable options 1 through 25, as
shown in Table 13-8. If the user does not select a wake-up sequence, the default, for DONE_EX = OFF, will be
wake-up sequence 21.
Wake Up with DONE_EX = On
The WAKE_UP preference for DONE_EX = ON supports the user selectable options 1 through 7, as shown in
Table 13-8. If the user does not select a wake-up sequence, the default will be wake-up sequence 4.
Start_Up Clock Selection
Once the FPGA is configured, it enters the start-up state, which is the transition between the configuration and
operational states. This sequence is synchronized to a clock source, which defaults to CCLK when sysCONFIG is
used, or TCK when JTAG is used.
If desired, a user-defined clock source can be used instead of CCLK/TCK. You need to specify this clock signal,
and instantiate the STRTUP library element in your design. The example shown below shows the proper syntax of
instantiating the STRTUP library element.
Verilog:
STRTUP u1 (.UCLK(<clock_name>)) /* synthesis syn_noprune=1 */;
13-18
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
VHDL:
component STRTUP
port(STRTUP: in STD_ULOGIC );
end component;
attribute syn_noprune: boolean ;
attribute syn_noprune of STRTUP: component is true;
begin
u1: STRTUP port map (UCLK =><clock name>);
INBUF
The I/O INBUF option will disable all unused input buffers to save power. INBUF mode limits some of the function-
ality of Boundary Scan. For Boundary Scan testing it is recommended that the I/O Power Save mode be set to ON
so that all of the I/Os will be fully functional.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
01.0
Change Summary
February 2005
March 2005
Initial release.
01.1
Changed Figure 12-1 to make it more understandable
Changed Table 12-5 to make it more understandable
Changed CFG[0:1] to CFG[1:0]
Added msb, lsb references to D[0:7]
Added Max Config Bits Table
July 2005
01.2
01.3
Changed INITN description, INITN is low during SDM configuration
September 2005
Added information on how to use the sysCONFIG dual-purpose pins as
GPIO.
February 2006
August 2007
01.4
01.5
01.6
01.7
Removed "pull-up" from TDO signal.
Nomenclature for Power Save feature changed to INBUF.
Updated Dual-Purpose sysCONFIG Pins text section.
Updated PROGRAMN text section.
September 2007
March 2008
Updated CSN and SC1N text section.
Updated Bypass Overflow Option text section.
Updated Flow-Through Overflow Option text section.
Updated Slave Parallel Mode text section.
July 2008
01.8
01.9
Updated LatticeXP Device Preference List table.
Updated Wake-Up Sequence to Internal Clock waveform.
Replaced Wake-up Clock Selection text section with new Start_Up
Clock Selection text section.
September 2008
Updated CCLK text section.
13-19
Lattice ispTRACY
Usage Guide
February 2006
Technical Note TN1054
Introduction
This document describes the functionality and usage of ispTRACY™, Lattice’s integrated logic analyzer for the
ispXPGA®, LatticeSC™, LatticeECP2™, LatticeECP™, LatticeEC™ and LatticeXP™ FPGA families. The isp-
TRACY tool consists of an Intellectual Property (IP) hardware block and three software tools – Core Generator,
Core Linker and ispLA. ispTRACY allows for fast debugging and functional verification inside Lattice FPGA devices
without the need for expensive test and measurement equipment. Debugging is accomplished through the hard-
ware IP compiled in the design, on device block RAM and the device JTAG port.
ispTRACY IP Core Features
The ispTRACY IP core is highly configurable. These configurable features include width and depth of data capture
lines, multiple edge and level sensitive trigger signals, complex comparison for trigger events, delayed trigger
events and more. ispTRACY allows multiple ispTRACY IP cores to be included in a single design. The following
table summarizes the features of the ispTRACY IP core.
Table 14-1. ispTRACY IP Core Features
Feature
Depth of Memory Capture
Data Capture Width
Triggering Schemes
Number of Triggers
Number of Core
Description
256 to 4096 samples
8 to 256 bits
Rising/falling edges, level logic, comparison, trigger after combination of events
4 to 128 bits, can be a combination of edge and level sensitive signals
Up to 16 ispTRACY cores
ispTRACY IP Module Generator
To include ispTRACY cores in a design, the first step is to run IPexpress™ from the ispLEVER® Project Navigator.
Figure 14-1 shows the launch button for the IP Manager program.
Figure 14-1. IPexpress Launch Button in ispLEVER Project Navigator
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
14-1
tn1054_01.2
Lattice Semiconductor
Lattice ispTRACY Usage Guide
Once IPexpress is launched, you will be presented with the option of generating the ispTRACY IP module by
selecting the JTAG module uner Architecture and clicking the Customize button. Figure 14-2 shows the IPexpress
window. Selections for the project path and module name are made through this window
Figure 14-2. ispTRACY IP Manager Program Window
ispTRACY Core Generator
The ispTRACY Core Generator under JTAG Module provides all the controls for customizing the ispTRACY
core(s). Selections on this page influence the final size of the core(s) inside the FPGA and features available in
terms of triggers, size of data bus and depth of memory capture. Figure 14-3 shows the Core Generator window
and Table 14-3 contains descriptions of each of the figures available in the IP core. Once the core features are
selected, clicking on the Generate button will create the necessary files for the Core Linker Program.
Figure 14-3. ispTRACY Core Generator Window
14-2
Lattice Semiconductor
Lattice ispTRACY Usage Guide
Table 14-2. ispTRACY Core Generator Features and Descriptions
Feature
Description
The number of ispLA(s) in an XPGA can be either 1, 2, 3, ..., or 16. The ispLA needs to be
configured before use. After [Generate] button is clicked, the ispTRACY software will gen-
erate the required logic for each ispLA based on its own configuration.
Number of Core
ispTRACY Core
Lists the ispLA.
The comparison logic can compare the trigger bus with the patterns setting by the user.
This field needs to be ON for ">", ">=", "<", "<=" comparison. If it's OFF, only = (equal) and
<> (not equal) comparison can be preformed.
Size Comparison Logic
This field configures the size of the event counter. If this field is 8, the counter can be set to
the value from 1 to 255. If this field is 16, the counter can be set to the value from 1 to
65535. If this field is "None", the counter logic is removed (i.e. counter value N always
equal 1). If the counter value is set to N, then when the pattern occurs N times, the corre-
sponding event will be TRUE.
Event Counter Size
If this is ON, the trace bus and trigger bus are the same bus. If this is OFF, the trace bus
and trigger bus are different and they can have different bus sizes.
Trigger Same as Trace
Trigger Bus Size
Trace Bus Size
This specifies the trigger bus size. It can be 4, 5, 6, ..., up to 128.
This specifies the trace bus size. It can be a multiple of 8 up to 256 (i.e. 8, 16, 24, 32,
40,..., up to 256).
This is the depth of the trace memory. It defines the number of trace bus samples that
ispLA can capture. This field can be set be set to 512, 1024, 2048, or 4096. It can also be
set to 256 if the trace bus size is a multiple of 16 (i.e. 16, 32, 48, etc.).
Trace Memory Depth
The field causes the Sample_After_Trigger mode logic to be removed or not. If this is ON,
the trace mode can be set to "One Shot" mode or "Sample After Trigger" mode.
Sample_After_Trigger Mode Logic
If this is OFF, the trace can only be running at "One Shot" mode. When this logic is turned
off, the ispLA will use less logic.
The trigger bus signals can be either edge sensitive signals or level sensitive signals. The
level sensitive trigger signals can only be set to 0, 1 or X (don't care). The edge sensitive
trigger signals can be set to 0, 1, X, R (rising edge), F (falling edge) or B (both edges).
This field specifies the number of edge sensitive trigger signals.
Number of Edge Trigger Signals
Number of Level Trigger Signals
This field specifies the number of level sensitive trigger signals. Note that (Number of
Edge Trigger Signals) + (Number of Level Trigger Signals) = (Trigger Bus Size).
This specifies if the "Trigger Input" logic exists. If this field is "None", the logic will be
removed and the trigger condition can only be set using EV0 and EV1.
Trigger Input Logic
If this field is set to "Pin" the trigger input logic exists and the trigger input should come
from an ispXPGA device I/O pin. The trigger input can be set to either active low or active
high.
This specifies if the "Trigger Output" logic exists. If this field is "None", the logic will be
removed. If this field is set to "Pin" the trigger output logic exists and the trigger output
should go out through an XPGA device I/O pin. If this is set to "ispLA", the trigger output
will be connected to the trigger input of other ispLAs.
Trigger Output Logic
You must choose "Trigger Input Logic" of the other ispLAs to be this ispLA. Same as the
trigger input, the trigger output can be set to either active low or active high.
At least one ispLA should have this option set to "Pin."
Generates the core.
Generate
Cancel
Help
Cancels the action and closes the dialog box without saving any changes.
Displays online Help topics for this dialog box.
14-3
Lattice Semiconductor
Lattice ispTRACY Usage Guide
ispTRACY Core Linker
Once the ispTRACY core is created, it must be linked into the target design. This is accomplished through the Core
Linker program. The Core Linker program allows the user access to internal and external signals of the target
design. The internal signals can be named signals or component ports. This window also displays the available isp-
TRACY ports. To connect ispTRACY signals, the desired signal(s) are selected in the left-hand signal window. Sig-
nals chosen from this window are reflected in the Selected signals window. Signals must be highlighted in this
window, the ispTRACY port window and then click on the connect button to connect the signals in the RTL code.
Multiple instances (for example, a data bus) can be connected at once by highlighting the first signal, holding down
the SHIFT key and clicking on the last desired signal. Figure 14-4 shows the ispTRACY Core Linker window.
Figure 14-4. ispTRACY Core Linker Program Window
When you click the Save button (or File -> Save menu selection), the Core Linker will create modified versions of
your source file, with the ispTRACY core linked into these modified files. Only design files that are directly con-
nected to the core will be modified. A dialogue box will indicate which files have been changed and will need to be
replaced in the design project for ispTRACY to function. The design files names will be the original files names with
the module name for the ispTRACY core (from the IPexpress ispTRACY core generation) appended. Figure 14-5
shows the changed files dialogue box.
14-4
Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-5. ispTRACY Core Linker Output Window
After clicking OK, you will be back in the ispTRACY Core Linker. You may now close this and return to the isp-
LEVER Project Navigator. At this point, it is necessary to replace the original design files with the ispTRACY Core
Linker modified files. Figure 6 shows this file replacement process on a design.
Figure 14-6. Original Project Navigator (left) and ispTRACY Project Navigator (right)
14-5
Lattice Semiconductor
Lattice ispTRACY Usage Guide
ispTRACY ispLA Program
After replacing the original design files with the ispTRACY Core Linker modified files, it is necessary to re-compile
the design and then program the device using the ispVM® software (see online documentation for running the
ispVM program). Once the device is successfully programmed, the ispLA program needs to be started. Figure 14-7
shows the ispLA launch button from the Project Navigator.
Figure 14-7. ispLA Launch Button in ispLEVER Project Navigator
ispLA provides for capture and display of data from the ispTRACY core. The program is used to setup the trigger
events counters, trigger location in data buffer, event patterns, event comparisons and data display. Figure 14-8
shows the initial startup windows required to run ispLA.
Figure 14-8. ispLA Program Window – New Project Setup
Once the project is set up, you can open up a trigger setup and viewing window for the project by clicking on
Window -> Show ispLA Window -> Device 0 -> Device 0 LA0. Figure 9 shows the ispLA window. There are three
tabs available under this window, trigger setup, event pattern and signal analysis (data view).
14-6
Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-9. ispLA Project Setup Window - Trigger Setup options
The options available in the Trigger setup window are based on selected ispTRACY core options. In the Trace
Mode box, One Shot mode will always be available, but Sample After Trigger availability is dependent on selecting
Sample_After_Trigger Mode Logic => ON. The position slider can be used to select the trigger point anywhere
within the data memory depth. There are three preconfigured trigger positions in the drop-down menu box. They
are Pre-Trigger (5% before and 95% after trigger), Center (50% before and 50% after trigger) and Post Trigger
(95% before and 5% after trigger). In the Compare Mode box the options are also dependant on core configuration.
EV0 and EV1 are always available. The comparisons available and number of samples will be determined by the
Size Comparison Logic and Event Counter Size. The equal to comparison is always available. Additions compari-
sons include >, <. !=, <=, >=. The Trigger Condition box configures which event or combination of events will cause
the ispLA program to trigger and upload captured data from the device. In a simple case, this would be set to Wait
for EV0. More complex cases could possible be wait for EV0 and EV1, or after EV1 wait until EV0. The final two
boxed on this screen control the signal polarity of Trigger In (if available) and Trigger Out.
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Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-10. ispLA Project Setup Window - Event Pattern Setup
The Event Pattern window configures the patterns for EV0 and EV1. Pattern 0 corresponds to EV0 and Pattern 1
corresponds to EV1. The sample types for trigger signals depends on whether the signal is edge or level sensitive.
If the signal is level sensitive, in the middle pattern window, only logic 0 (0) ,logic (1) or don't care (X) are available.
For edge sensitive signals, the options are logic 0 (0), logic 1 (1), rising (R), falling (F), both/either edge (B) or don't
care (X). In this window, changes to the pattern are made in the center section (Pattern 1 or Pattern 0) and the
changes are reflected in the right section.
To begin sampling , click on the green run button. Sampling will complete when the trigger conditions are met. The
data will be uploaded through the JTAG cable and results displayed I the Signal Analysis window. Figure 14-11
shows the Signal Analysis window after a data capture cycle.
Figure 14-11. ispLA Signal Analysis Window
14-8
Lattice Semiconductor
Lattice ispTRACY Usage Guide
Conclusion
ispTRACY is a full-featured logic analysis tool for use in Lattice FPGA products including ispXPGA, LatticeECP/EC
and LatticeXP families. Using internal device resources, including PFF/PFU, Embedded Block Ram and the device
JTAG port, the user can quickly verify functionality and assist in device debugging. ispTRACY reduces the need for
external test and measurement equipment to debug FPGA projects, while providing full access to a wide range of
internal signals, components and design elements.
References
• ispTRACY Usage Guide, 2/07/04 Rev. 0.1, page 14 of 14.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
14-9
HDL Synthesis Coding Guidelines for
Lattice Semiconductor FPGAs
October 2005
Technical Note TN1008
Introduction
Coding style plays an important role in utilizing FPGA resources. Although many popular synthesis tools have sig-
nificantly improved optimization algorithms for FPGAs, it still is the responsibility of the user to generate meaningful
and efficient HDL code to guide their synthesis tools to achieve the best result for a specific architecture. This appli-
cation note is intended to help designers establish useful HDL coding styles for Lattice Semiconductor FPGA
devices. It includes VHDL and Verilog design guidelines for both novice and experienced users.
The application note is divided into two sections. The general coding styles for FPGAs section provides an over-
view for effective FPGA designs. The following topics are discussed in detail:
• Hierarchical Coding
• Design Partitioning
• Encoding Methodologies for State Machines
• Coding Styles for Finite State Machines (FSM)
• Using Pipelines
• Comparing IF Statements and CASE Statements
• Avoiding Non-intentional Latches
The HDL Design with Lattice Semiconductor FPGA Devices section covers specific coding techniques and exam-
ples:
• Using the Lattice Semiconductor FPGA Synthesis Library
• Implementation of Multiplexers
• Creating Clock Dividers
• Register Control Signals (CE, LSR, GSR)
• Using PIC Features
• Implementation of Memories
• Preventing Logic Replication and Fanout
• Comparing Synthesis Results and Place and Route Results
General Coding Styles for FPGA
The following recommendations for common HDL coding styles will help users generate robust and reliable FPGA
designs.
Hierarchical Coding
HDL designs can either be synthesized as a flat module or as many small hierarchical modules. Each methodology
has its advantages and disadvantages. Since designs in smaller blocks are easier to keep track of, it is preferred to
apply hierarchical structure to large and complex FPGA designs. Hierarchical coding methodology allows a group
of engineers to work on one design at the same time. It speeds up design compilation, makes changing the imple-
mentation of key blocks easier, and reduces the design period by allowing the re-use of design modules for current
and future designs. In addition, it produces designs that are easier to understand. However, if the design mapping
into the FPGA is not optimal across hierarchical boundaries, it will lead to lower device utilization and design perfor-
mance. This disadvantage can be overcome with careful design considerations when choosing the design hierar-
chy. Here are some tips for building hierarchical structures:
• The top level should only contain instantiation statements to call all major blocks
• Any I/O instantiations should be at the top level
• Any signals going into or out of the devices should be declared as input, output or bi-directional pins at the
top level
www.latticesemi.com
15-1
tn1008_02.1
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
• Memory blocks should be kept separate from other code
Design Partitioning
By effectively partitioning the design, a designer can reduce overall run time and improve synthesis results. Here
are some recommendations for design partitioning.
Maintain Synchronous Sub-blocks by Registering All Outputs
It is suggested to arrange the design boundary such that the outputs in each block are registered. Registering out-
puts helps the synthesis tool to consider the implementation of the combinatorial logic and registers into the same
logic block. Registering outputs also makes the application of timing constraints easier since it eliminates possible
problems with logic optimization across design boundaries. Single clock is recommended for each synchronous
block because it significantly reduces the timing consideration in the block. It leaves the adjustment of the clock
relationships of the whole design at the top level of the hierarchy. Figure 15-1 shows an example of synchronous
blocks with registered outputs.
Figure 15-1. Synchronous Blocks with Registered Outputs
A
B
C
A
B
Keep Related Logic Together in the Same Block
Keeping related logic and sharable resources in the same block allows the sharing of common combinatorial terms
and arithmetic functions within the block. It also allows the synthesis tools to optimize the entire critical path in a
single operation. Since synthesis tools can only effectively handle optimization of certain amounts of logic, optimi-
zation of critical paths pending across the boundaries may not be optimal. Figure 15-2 shows an example of merg-
ing sharable resource in the same block.
Figure 15-2. Merge Sharable Resource in the Same Block
A
B
C
+
+
A
B
MUX
+
MUX
Separate Logic with Different Optimization Goals
Separating critical paths from non-critical paths may achieve efficient synthesis results. At the beginning of the proj-
ect, one should consider the design in terms of performance requirements and resource requirements. If there are
15-2
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
two portions of a block, one that needs to be optimized for area and a second that needs to be optimized for speed,
they should be separated into two blocks. By doing this, different optimization strategies for each module can be
applied without being limited by one another.
Keep Logic with the Same Relaxation Constraints in the Same Block
When a portion of the design does not require high performance, this portion can be applied with relaxed timing
constraints such as “multicycle” to achieve high utilization of device area. Relaxation constraints help to reduce
overall run time. They can also help to efficiently save resources, which can be used on critical paths. Figure 15-3
shows an example of grouping logic with the same relaxation constraint in one block.
Figure 15-3. Logic with the Same Relaxation Constraint
A
B
A
FF1
FF2
FF1
FF2
Keep Instantiated Code in Separate Blocks
It is recommended that the RAM block in the hierarchy be left in a separate block (Figure 15-4). This allows for easy
swapping between the RAM behavioral code for simulation, and the code for technology instantiation. In addition,
this coding style facilitates the integration of the ispLEVER® IPexpress™ tool into the synthesis process.
Figure 15-4. Separate RAM Block
Top
RAM
Controller
Register File
State Machine
Keep the Number FPGA Gates at 30 to 80 PFUs Per Block
Counter
This range varies based on the computer configuration, time required to complete each optimization run, and the
targeted FPGA routing resources. Although a smaller block methodology allows more control, it may not produce
the most efficient design since it does not provide the synthesis tool enough logic to apply “Resource Sharing”
algorithms. On the other hand, having a large number of gates per block gives the synthesis tool too much to work
on and causes changes that affect more logic than necessary in an incremental or multi-block design flow.
State Encoding Methodologies for State Machines
There are several ways to encode a state machine, including binary encoding, gray-code encoding and one-hot
encoding. State machines with binary or gray-code encoded states have minimal numbers of flip-flops and wide
combinatorial functions, which are typically favored for CPLD architectures. However, most FPGAs have many flip-
flops and relatively narrow combinatorial function generators. Binary or gray-code encoding schemes can result in
inefficient implementation in terms of speed and density for FPGAs. On the other hand, one-hot encoded state
machine represents each state with one flip-flop. As a result, it decreases the width of combinatorial logic, which
matches well with FPGA architectures. For large and complex state machines, one-hot encoding usually is the
preferable method for FPGA architectures. For small state machines, binary encoding or gray-code encoding may
be more efficient.
There are many ways to ensure the state machine encoding scheme for a design. One can hard code the states in
the source code by specifying a numerical value for each state. This approach ensures the correct encoding of the
state machine but is more restrictive in the coding style. The enumerated coding style leaves the flexibility of state
machine encoding to the synthesis tools. Most synthesis tools allow users to define encoding styles either through
15-3
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
attributes in the source code or through the tool’s Graphical User Interface (GUI). Each synthesis tool has its own
synthesis attributes and syntax for choosing the encoding styles. Refer to the synthesis tools documentation for
details about attributes syntax and values.
The following syntax defines an enumeration type in VHDL:
type type_name is (state1_name,state2_name,......,stateN_name)
Here is a VHDL example of enumeration states:
type STATE_TYPE is (S0,S1,S2,S3,S4);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
The following are examples of Synplify® and LeonardoSpectrum® VHDL synthesis attributes.
Synplify:
attribute syn_encoding : string;
attribute syn_encoding of <signal_name> : type is "value ";
-- The syn_encoding attribute has 4 values : sequential, onehot, gray and safe.
LeonardoSpectrum:
-- Declare TYPE_ENCODING_STYLE attribute
-- Not needed if the exemplar_1164 package is used
type encoding_style is (BINARY, ONEHOT, GRAY, RANDOM, AUTO);
attribute TYPE_ENCODING_STYLE : encoding_style;
...
attribute TYPE_ENCODING_STYLE of <typename> : type is ONEHOT;
In Verilog, one must provide explicit state values for states. This can be done by using the bit pattern (e.g., 3'b001),
or by defining a parameter and using it as the case item. The latter method is preferable. The following is an exam-
ple using parameter for state values.
Parameter state1 = 2'h1, state2 = 2'h2;
...
current_state = state2; // setting current state to 2'h2
The attributes in the source code override the default encoding style assigned during synthesis. Since Verilog does
not have predefined attributes for synthesis, attributes are usually attached to the appropriate objects in the source
code as comments. The attributes and their values are case sensitive and usually appear in lower case. The follow-
ing examples use attributes in Verilog source code to specify state machine encoding style.
Synplify:
Reg[2:0] state; /* synthesis syn_encoding = "value" */;
// The syn_encoding attribute has 4 values : sequential, onehot, gray and safe.
In LeonardoSpectrum, it is recommended to set the state machine variable to an enumeration type with enum
pragma. Once this is set in the source code, encoding schemes can be selected in the LeonardoSpectrum GUI.
LeonardoSpectrum:
Parameter /* exemplar enum <type_name> */ s0 = 0, s1 = 1, s2 = 2, s3 = 3, S4 = 4;
Reg [2:0] /* exemplar enum <type_name> */ present_state, next_state ;
In general, synthesis tools will select the optimal encoding style that takes into account the target device architec-
ture and size of the decode logic. One can always apply synthesis attributes to override the default encoding style
if necessary.
15-4
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Coding Styles for FSM
A finite state machine (FSM) is a hardware component that advances from the current state to the next state at the
clock edge. As mentioned in the Encoding Methodologies for State Machines section, the preferable scheme for
FPGA architectures is one-hot encoding. This section discusses some common issues encountered when con-
structing state machines, such as initialization and state coverage, and special case statements in Verilog.
General State Machine Description
Generally, there are two approaches to describe a state machine. One is to use one process/block to handle both
state transitions and state outputs. The other is to separate the state transition and the state outputs into two differ-
ent process/blocks. The latter approach is more straightforward because it separates the synchronous state regis-
ters from the decoding logic used in the computation of the next state and the outputs. This will make the code
easier to read and modify, and makes the documentation more efficient. If the outputs of the state machine are
combinatorial signals, the second approach is almost always necessary because it will prevent the accidental reg-
istering of the state machine outputs.
The following examples describe a simple state machine in VHDL and Verilog. In the VHDL example, a sequential
process is separated from the combinatorial process. In Verilog code, two always blocks are used to describe the
state machine in a similar way.
VHDL Example for State Machine
Verilog Example for State Machine
.
.
.
. . .
architecture lattice_fpga of dram_refresh is
type state_typ is (s0, s1, s2, s3, s4);
parameter s0
=
0, s1
=
1, s2
=
2, s3
=
3, s4
=
4;
signal present_state, next_state
begin
: state_typ;
reg [2:0] present_state, next_state;
reg ras, cas, ready;
-- process to update the present state
registers: process (clk, reset)
begin
// always block to update the present state
always
@ (posedge clk or posedge reset)
if (reset='1') then
begin
present_state <= s0;
if (reset) present_state
= s0;
elsif clk'event and clk='1' then
present_state <= next_state;
end if;
else present_state next_state;
=
end
end process registers;
// always block to calculate the next state
&
=
outputs
always
begin
@ (present_state or refresh or cs)
-- process to calculate the next state
transitions: process (present_state, refresh, cs)
begin
& output
next_state
ras 1'bX; cas
case (present_state)
= s0;
=
= 1'bX; ready = 1'bX;
ras <= '0'; cas <= '0'; ready <= '0';
case present_state is
s0
:
if (refresh) begin
next_state s3;
ras 1'b1; cas
when s0 =>
=
ras <= '1'; cas <= '1'; ready <= '1';
=
=
1'b0; ready
1'b0;
if (refresh
elsif (cs
=
'1') then next_state <= s3;
end
=
'1') then next_state <= s1;
else if (cs) begin
else next_state <= s0;
end if;
when s1 =>
next_state
=
=
=
=
=
=
=
s1; ras
s0; ras
s2; ras
s0; ras
s2; ras
s4; ras
s0; ras
=
=
=
=
=
=
=
1'b0; cas
1'b1; cas
1'b0; cas
1'b1; cas
1'b0; cas
1'b1; cas
1'b0; cas
=
=
=
=
=
=
=
1'b1; ready
=
=
=
=
=
=
=
1'b0;
1'b1;
1'b0;
1'b1;
1'b0;
1'b0;
1'b0;
end
else begin
next_state
ras <= '0'; cas <= '1'; ready <= '0';
next_state <= s2;
1'b1; ready
1'b0; ready
1'b1; ready
1'b0; ready
1'b0; ready
1'b0; ready
end
when s2 =>
ras <= '0'; cas <= '0'; ready <= '0';
if (cs '0') then next_state <= s0;
s1
s2
:
:
begin
next_state
=
end
else next_state <= s2;
end if;
when s3 =>
ras <= '1'; cas <= '0'; ready <= '0';
next_state <= s4;
when s4 =>
ras <= '0'; cas <= '0'; ready <= '0';
next_state <= s0;
when others =>
if (~cs) begin
next_state
end
else begin
next_state
end
begin
next_state
end
s3
s4
:
:
ras <= '0'; cas <= '0'; ready <= '0';
next_state <= s0;
end case;
begin
next_state
end
end process transitions;
.
endcase
. .
end
.
.
.
15-5
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Initialization and Default State
A state machine must be initialized to a valid state after power-up. This can be done at the device level during
power up or by including a reset operation to bring it to a known state. For all Lattice Semiconductor FPGA devices,
the Global Set/Reset (GSR) is pulsed at power-up, regardless of the function defined in the design source code. In
the above example, an asynchronous reset can be used to bring the state machine to a valid initialization state. In
the same manner, a state machine should have a default state to ensure the state machine will not go into an
invalid state if not all the possible combinations are clearly defined in the design source code. VHDL and Verilog
have different syntax for default state declaration. In VHDL, if a CASE statement is used to construct a state
machine, “When Others” should be used as the last statement before the end of the statement, If an IF-THEN-
ELSE statement is used, “Else” should be the last assignment for the state machine. In Verilog, use “default” as the
last assignment for a CASE statement, and use “Else” for the IF-THEN-ELSE statement.
When Others in VHDL
Default Clause in Verilog
...
...
architecture lattice_fpga of FSM1 is
// Define state labels explicitly
type state_typ is (deflt, idle, read, write);
parameter deflt=2'bxx;
parameter idle =2'b00;
parameter read =2'b01;
signal next_state
begin
: state_typ;
process(clk, rst)
begin
parameter write=2'b10;
if (rst='1') then
reg [1:0] next_state;
reg dout;
next_state <= idle; dout <= '0';
elsif (clk'event and clk='1') then
case next_state is
always @(posedge clk or posedge rst)
if (rst) begin
next_state <= idle;
dout <= 1'b0;
when idle =>
next_state <= read; dout <= din(0);
when read =>
next_state <= write; dout <= din(1);
end
when write =>
else begin
next_state <= idle; dout <= din(2);
case(next_state)
when others =>
idle: begin
dout <= din[0]; next_state <= read;
next_state <= deflt; dout <= '0';
end case;
end
end if;
read: begin
end process;
...
dout <= din[1]; next_state <= write;
end
write: begin
dout <= din[2]; next_state <= idle;
end
default: begin
dout <= 1'b0; next_state <= deflt;
end
Full Case and Parallel Case Specification in Verilog
Verilog has additional attributes to define the default states without writing it specifically in the code. One can use
“full_case” to achieve the same performance as “default”. The following examples show the equivalent representa-
tions of the same code in Synplify. LeonardoSpectrum allows users to apply Verilog-specific options in the GUI set-
tings.
…
…
case (current_state) // synthesis full_case
2’b00 : next_state <= 2’b01;
2’b01 : next_state <= 2’b11;
2’b11 : next_state <= 2’b00;
…
case (current_state)
2’b00 : next_state <= 2’b01;
2’b01 : next_state <= 2’b11;
2’b11 : next_state <= 2’b00;
default : next_state <= 2bx;
“Parallel_case” makes sure that all the statements in a case statement are mutually exclusive. It is used to inform
the synthesis tools that only one case can be true at a time. The syntax for this attribute in Synplify is as follows:
// synthesis parallel_case
Using Pipelines in the Designs
Pipelining can improve design performance by restructuring a long data path with several levels of logic and break-
ing it up over multiple clock cycles. This method allows a faster clock cycle by relaxing the clock-to-output and
setup time requirements between the registers. It is usually an advantageous structure for creating faster data
paths in register-rich FPGA devices. Knowledge of each FPGA architecture helps in planning pipelines at the
15-6
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
beginning of the design cycle. When the pipelining technique is applied, special care must be taken for the rest of
the design to account for the additional data path latency. The following illustrates the same data path before
(Figure 15-5) and after pipelining (Figure 15-6).
Figure 15-5. Before Pipelining
FF1
Comb.
Comb.
Comb.
FF1
Function
Function
Function
Slow Clock
Figure 15-6. After Pipelining
FF1
Comb.
Function
FF2
Comb.
Function
FF3
Comb.
Function
FF4
Fast Clock
Before pipelining, the clock speed is determined by the clock-to-out time of the source register, the logic delay
through four levels of combinatorial logic, the associated routing delays, and the setup time of the destination regis-
ter. After pipelining is applied, the clock speed is significantly improved by reducing the delay of four logic levels to
one logic level and the associated routing delays, even though the rest of the timing requirements remain the same.
It is recommended to check the Place and Route timing report to ensure that the pipelined design gives the desired
performance.
Comparing IF statement and CASE statement
CASE and IF-THEN-ELSE statements are common for sequential logic in HDL designs. The IF-THEN-ELSE state-
ment generally generates priority-encoded logic, whereas the CASE statement implements balanced logic. An IF-
THEN-ELSE statement can contain a set of different expressions while a Case statement is evaluated against a
common controlling expression. Both statements will give the same functional implementation if the decode condi-
tions are mutually exclusive, as shown in the following VHDL codes.
-- Case Statement — mutually exclusive conditions
process (s, x, y, z)
begin
-- If-Then-Else — mutually exclusive conditions
process (s, x, y, z)
begin
O1 <= ‘0’;
O1 <= ‘0’;
O2 <= ‘0’;
O2 <= ‘0’;
O3 <= ‘0’;
O3 <= ‘0’;
case (s) is
if s = “00” then O1 <= x;
elsif s = “01” then O2 <= y;
elsif s = “10” then O3 <= z;
end if;
when “00” => O1 <= x;
when “01” => O2 <= y;
when “10” => O3 <= z;
end case;
end process;
end process;
15-7
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
However, the use of If-Then-Else construct could be a key pitfall to make the design more complex than necessary,
because extra logic are needed to build a priority tree. Consider the following examples:
--A: If-Then-Elese Statement: Complex O3 Equations
process(s1, s2, s3, x, y, z)
begin
--B: If-Then-Else Statement: Simplified O3 Equation
process (s1, s2, s3, x, y, z)
begin
O1 <= ‘0’;
O1 <= ‘0’;
O2 <= ‘0’;
O2 <= ‘0’;
O3 <= ‘0’;
O3 <= ‘0’;
if s1 = ‘1’ then
O1 <= x;
if s1 = ‘1’ then
O1 <= x;
elsif s2 = ‘1’ then
O2 <= y;
elsif s3 = ‘1’ then
O3 <= z;
end if;
if s2 = ‘1’ then
O2 <= y;
end if;
end if;
end process;
if s3 <= ‘1’ then
O3 <= z;
end if;
end process;
If the decode conditions are not mutually exclusive, IF-THEN-ELSE construct will cause the last output to be
dependent on all the control signals. The equation for O3 output in example A is:
O3 <= z and (s3) and (not (s1 and s2));
If the same code can be written as in example B, most of the synthesis tools will remove the priority tree and
decode the output as:
O3 <= z and s3;
This reduces the logic requirement for the state machine decoder. If each output is indeed dependent of all of the
inputs, it is better to use a CASE statement since CASE statements provide equal branches for each output.
Avoiding Non-intentional Latches
Synthesis tools infer latches from incomplete conditional expressions, such as an IF-THEN-ELSE statements with-
out an Else clause. To avoid non-intentional latches, one should specify all conditions explicitly or specify a default
assignment. Otherwise, latches will be inserted into the resulting RTL code, requiring additional resources in the
device or introducing combinatorial feedback loops that create asynchronous timing problems. Non-intentional
latches can be avoided by using clocked registers or by employing any of the following coding techniques:
• Assigning a default value at the beginning of a process
• Assigning outputs for all input conditions
• Using else, (when others) as the final clause
Another way to avoid non-intentional latches is to check the synthesis tool outputs. Most of the synthesis tools give
warnings whenever there are latches in the design. Checking the warning list after synthesis will save a tremen-
dous amount of effort in trying to determine why a design is so large later in the Place and Route stage.
HDL Design with Lattice Semiconductor FPGA Devices
The following section discusses the HDL coding techniques utilizing specific Lattice Semiconductor FPGA system
features. This kind of architecture-specific coding style will further improve resource utilization and enhance the
performance of designs.
Lattice Semiconductor FPGA Synthesis Library
The Lattice Semiconductor FPGA Synthesis Library includes a number of library elements to perform specific logic
functions. These library elements are optimized for Lattice Semiconductor FPGAs and have high performance and
utilization. The following are the classifications of the library elements in the Lattice Semiconductor FPGA Synthe-
15-8
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
sis Library. The definitions of these library elements can be found in the Reference Manuals section of the isp-
LEVER on-line help system.
• Logic gates and LUTs
• Comparators, adders, subtractors
• Counters
• Flip-flops and latches
• Memory, 4E-specific memory (block RAM function)
• Multiplexors
• Multipliers
• All I/O cells, including I/O flip-flops
• PIC cells
• Special cells, including PLL, GSR, boundary scan, etc.
• FPSC elements
IPepxress, a parameterized module complier optimized for Lattice FPGA devices, is available for more complex
logic functions. IPexpress supports generation of library elements with a number of different options such as PLLs
and creates parameterized logic functions such as PFU and EBR memory, multipliers, adders, subtractors, and
counters. IPexpress accepts options that specify parameters for parameterized modules such as data path mod-
ules and memory modules, and produces a circuit description with Lattice Semiconductor FPGA library elements.
Output from IPexpress can be written in EDIF, VHDL, or Verilog. In order to use synthesis tools to utilize the Lattice
FPGA architectural features, it is strongly recommended to use IPexpress to generate modules for source code
instantiation. The following are examples of Lattice Semiconductor FPGA modules supported by IPexpress:
• PLL
• Memory implemented in PFU:
– Synchronous single-port RAM, synchronous dual-port RAM, synchronous ROM, synchronous FIFO
• Memory implemented with EBR:
– Quad-port Block RAM, Dual-Port Block RAM, Single-Port Block RAM, ROM, FIFO
• Other EBR based Functions
– Multiplier, CAM
• PFU based functions
– Multiplier, adder, subtractor, adder/subtractor, linear feedback shifter, counter
• MPI/System Bus
IPexpress is especially efficient when generating high pin count modules as it saves time in manually cascading
small library elements from the synthesis library. Detailed information about IPexpress and its user guide can be
found in the ispLEVER help system.
15-9
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Implementing Multiplexers
The flexible configurations of LUTs can realize any 4-, 5-, or 6-input logic function like 2-to-1, 3-to-1 or 4-to-1 multi-
plexers. Larger multiplexers can be efficiently created by programming multiple 4-input LUTs. Synthesis tools camn
automatically infer Lattice FPGA optimized multiplexer library elements based on the behavioral description in the
HDL source code. This provides the flexibility to the Mapper and Place and Route tools to configure the LUT mode
and connections in the most optimum fashion.
16:1 MUX
…
process(sel, din)
begin
if
(sel="0000") then muxout <= din(0);
elsif (sel="0001") then muxout <= din(1);
elsif (sel="0010") then muxout <= din(2);
elsif (sel="0011") then muxout <= din(3);
elsif (sel="0100") then muxout <= din(4);
elsif (sel="0101") then muxout <= din(5);
elsif (sel="0110") then muxout <= din(6);
elsif (sel="0111") then muxout <= din(7);
elsif (sel="1000") then muxout <= din(8);
elsif (sel="1001") then muxout <= din(9);
elsif (sel="1010") then muxout <= din(10);
elsif (sel="1011") then muxout <= din(11);
elsif (sel="1100") then muxout <= din(12);
elsif (sel="1101") then muxout <= din(13);
elsif (sel="1110") then muxout <= din(14);
elsif (sel="1111") then muxout <= din(15);
else muxout <= '0';
end if;
end process;
…
Clock Dividers
There are two ways to implement clock dividers in Lattice Semiconductor FPGA devices. The first is to cascade the
registers with asynchronous clocks. The register output feeds the clock pin of the next register (Figure 15-7). Since
the clock number in each PFU is limited to two, any clock divider with more than two bits will require multiple PFU
implementations. As a result, the asynchronous daisy chaining implementation of clock divider will be slower due to
the inter-PFU routing delays. This kind of delays is usually ambiguous and inconsistent because of the nature of
FPGA routing structures.
Figure 15-7. Daisy Chaining of Flip-flops
PFU
PFU
LU
D
LU
D
15-10
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
The following are the HDL representations of the design in Figure 15-7.
//Verilog Example of Daisy Chaining FF
...
-- VHDL Example of Daisy Chaining FF
...
always @(posedge CLK or posedge RST)
begin
-- 1st FF to divide Clock in half
CLK_DIV1: process(CLK, RST)
begin
if (RST)
clk1
else
clk1
=
1'b0;
if (RST='1') then
clk1 <= '0';
=
!clk1;
elsif (CLK'event and CLK='1') then
clk1 <= not clk1;
end if;
end
always @(posedge clk1 or posedge RST)
end process CLK_DIV1;
begin
if (RST)
-- 2nd FF to divide clock in half
CLK_DIV2: process(clk1, RST)
begin
clk2
else
clk2
=
1'b0;
=
!clk2;
if (RST='1') then
end
...
clk2 <= '0';
elsif (clk1'event and clk1='1') then
clk2 <= not clk2;
end if;
end process CLK_DIV2;
The preferable way is to fully employ the PFU's natural “Ripple-mode”. A single PFU can support up to 8-bit ripple
functions with fast carry logic. Figure 15-8 is an example of 4-bit counter in PFU “Ripple Mode”. In Lattice Semicon-
ductor FPGA architectures, an internal generated clock can get on the clock spine for small skew clock distribution,
further enhancing the performance of the clock divider.
Figure 15-8. Use PFU “Ripple Mode”
DIVBY2
LUT in
Ripple Mode
4-Bit
DIVBY4
DIVBY8
DIVBY16
Counter
Here are the HDL representations of the design in Figure 15-8.
-- VHDL : “RippleMode” Clock Divider
...
//Verilog : “RippleMode” Clock Divider
...
always @(posedge CLK or posedge RST)
COUNT4: process(CLK, RST)
begin
begin
if (RST)
if (RST='1') then
cnt <= (others=>'0');
elsif (CLK'event and CLK='1') then
cnt
else
cnt
=
4'b0;
cnt
=
+
1'b1;
cnt <= cnt
end if;
+
1;
end
end process COUNT4;
assign DIVBY4
assign DIVBY16
=
=
cnt[1];
cnt[3];
DIVBY4 <= cnt(1);
DIVBY16 <= cnt(3);
...
15-11
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Register Control Signals
The general-purpose latches/FFs in the PFU are used in a variety of configurations depending on device family. For
example, the Lattice EC, ECP, SC and XP family of devices clock, clock enable and LSR control can be applied to
the registers on a slice basis. Each slice contains two LUT4 lookup tables feeding two registers (programmed asto
be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such
as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (prgorammable as synchro-
nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. The ORCA Series 4 family of
devices clock, clock enable and LSR control can be applied to the registers on a nibble-wide basis. When writing
design codes in HDL, keep the architecture in mind to avoid wasting resources in the device. Here are several
points for consideration:
• If the register number is not a multiple of 2 or 4 (dependent on device family), try to code the registers in a
way that all registers share the same clock, and in a way that all registers share the same control signals.
• Lattice Semiconductor FPGA devices have multiple dedicated Clock Enable signals per PFU. Try to code
the asynchronous clocks as clock enables, so that PFU clock signals can be released to use global low-
skew clocks.
• Try to code the registers with Local synchronous Set/Reset and Global asynchronous Set/Reset
For more detailed architecture information, refer to the Lattice Semiconductor FPGA data sheets.
Clock Enable
Figure 15-9 shows an example of gated clocking. Gating clock is not encouraged in digital designs because it may
cause timing issues such as unexpected clock skews. The structure of the PFU makes the gating clock even more
undesirable since it will use up all the clock resources in one PFU and sometimes waste the FF/ Latches resources
in the PFU. By using the clock enable in the PFU, the same functionality can be achieved without worrying about
timing issues as only one signal is controlling the clock. Since only one clock is used in the PFU, all related logic
can be implemented in one block to achieve better performance. Figure 15-10 shows the design with clock enable
signal being used.
Figure 15-9. Asynchronous: Gated Clocking
din
qout
D
Q
clk
gate
Figure 15-10. Synchronous: Clock Enabling
A
B
qout
D
Q
din
S
clken
clk
The VHDL and Verilog coding for Clock Enable are as shown in Figure 15-10.
-- VHDL example for Clock Enable
// Verilog example for Clock Enable
...
...
Clock_Enable: process(clk)
always @(posedge clk)
begin
qout <= clken
? din : qout;
if (clk'event or clk='1') then
if (clken='1') then
qout <= din;
...
end if;
end if;
end process Clock_Enable;
15-12
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
The following are guidelines for coding the Clock Enable in Lattice Semiconductor FPGAs:
• Clock Enable is only supported by FFs, not latches.
• Nibble wide FFs and slices inside a PFU share the same Clock Enable
• All flip-flops in the Lattice Semiconductor FPGA library have a positive clock enable signal
• In the ORCA Series 4 architecture, the Clock Enable signal has the higher priority over synchronous
set/reset by default. However, it can be programmed to have the priority of synchronous LSR over the prior-
ity of Clock Enable. This can be achieved by instantiating the library element in the source code. For exam-
ple, the library element FD1P3IX is a flip-flop that allows synchronous Clear to override Clock Enable.
Users can also specify the priority of generic coding by setting the priority of the control signals differently.
The following examples demonstrate coding methodologies to help the synthesis tools to set the higher pri-
ority of Clock Enable or synchronous LSR.
-- VHDL Example of CE over Sync. LSR
...
// Verilog Example of CE over Sync. LSR
...
COUNT8: process(CLK, GRST)
always @(posedge CLK or posedge GRST)
begin
begin
if (GRST
=
'1') then
if (GRST)
cnt <= (others => '0');
elsif (CLK'event and CLK='1') then
-- CE Over LSR: Clock Enable has higher priority
cnt
else
if (CKEN)
cnt
else if (LRST)
cnt 4'b0;
= 4'b0;
if (CKEN
cnt <= cnt
elsif (LRST '1') then
cnt <= (others =>'0');
end if;
end if;
=
'1') then
= cnt + 1'b1;
+
1;
=
=
end...
end process COUNT8;
-- VHDL Example of Sync. LSR Over CE
...
// Verilog Example of Sync. LSR Over CE
...
COUNT8: process(CLK, GRST)
begin
always @(posedge CLK or posedge GRST)
begin
if (GRST
=
'1') then
if (GRST)
cnt <= (others => '0');
elsif (CLK'event and CLK='1') then
-- LSR over CE: Sync. Set/Reset has higher priority
cnt
else if (LRST)
cnt 4'b0;
else if (CKEN)
cnt cnt + 1'b1;
= 4'b0;
=
if (LRST
cnt <= (others => '0');
elsif (CKEN '1') then
cnt <= cnt 1;
end if;
= '1') then
=
=
end
...
+
SET / Reset
There are two types of set/reset functions in Lattice Semiconductor FPGAs: Global (GSR) and Local (LSR). The
GSR signal is asynchronous and is used to initialize all registers during configuration. It can be activated either by
an external dedicated pin or from internal logic after configuration. The local SET/Reset signal may be synchro-
nous or asynchronous. GSR is pulsed at power up to either set or reset the registers depending on the configura-
tion of the device. Since the GSR signal has dedicated routing resources that connect to the set and reset pin of
the flip-flops, it saves general-purpose routing and buffering resources and improves overall performance. If asyn-
chronous reset is used in the design, it is recommended to use the GSR for this function, if possible. The reset sig-
nal can be forced to be GSR by the instantiation library element. Synthesis tools will automatically infer GSR if all
15-13
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
registers in the design are asynchronously set or reset by the same wire. The following examples show the correct
syntax for instantiating GSR in the VHDL and Verilog codes.
-- VHDL Example of GSR Instantiation
library ieee;
// Verilog Example of GSR Instantiation
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
module gsr_test(clk, rst, cntout);
input clk, rst;
output[1:0] cntout;
entity gsr_test is
port (rst, clk: in std_logic;
cntout
end gsr_test;
: out std_logic_vector(1 downto 0));
reg[1:0] cnt;
GSR u1 (.GSR(rst));
architecture behave of gsr_test is
signal cnt std_logic_vector(1 downto 0);
begin
:
always @(posedge clk or negedge rst)
begin
if (!rst)
u1: GSR port map (gsr=>rst);
cnt
cnt
=
=
2'b0;
cnt
else
process(clk, rst)
begin
+
1;
end
if rst
=
'1' then
cnt <= "00";
assign cntout
endmodule
= cnt;
elsif rising_edge (clk) then
cnt <= cnt 1;
+
end if;
end process;
cntout <= cnt;
end behave;
Use PIC Features
Using I/O Registers/Latches in PIC
Moving registers or latches into Input/Output cells (PIC) may reduce the number of PFUs used and decrease rout-
ing congestion. In addition, it reduces setup time requirements for incoming data and clock-to-output delay for out-
put data, as shown in Figure 15-11. Most synthesis tools will infer input registers or output registers in PIC if
possible. Users can set synthesis attributes in the specific tools to turn off the auto-infer capability. Users can also
instantiate library elements to control the implementation of PIC resource usage.
Figure 15-11. Moving FF into PIC Input Register
PIC
PFU
PIC
IN_SIG
IN_SIG
D
Q
D
Q
Before Using Input Register
After Using Input Register
Figure 15-12. Moving FF into PIC Output Register
PFU
PIC
PIC
OUT_SIG
OUT_SIG
D
Q
D
Q
Before Using Output Register
After Using Output Register
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HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Inferring Bi-directional I/O
Users can either structurally instantiate the bi-directional I/O library elements, or behaviorally describe the I/O
paths to infer bi-directional buffers. The following VHDL and Verilog examples show how to infer bi-directional I/O
buffers.
// Inferring Bi-directional I/O in Verilog
-- Inferring Bi-directional I/O in VHDL
module bidir_infer (A, B, DIR);
inout A, B;
input DIR;
library ieee;
use ieee.std_logic_1164.all;
entity bidir_infer is
assign
assign
B
A
=
=
(DIR)
(~DIR)
?
?
A
B
:
:
1'bz;
1'bz;
port(A,
dir
B
:
:
inout std_logic;
in std_logic);
end bidir_infer;
endmodule
architecture lattice_fpga of bidir_infer is
begin
B
A
<=
<=
A
B
when (dir='1') else 'Z';
when (dir='0') else 'Z';
end lattice_fpga
Specifying I/O Types and Locations
Users can either assign I/O types and unique I/O locations in the Preference Editor or specify them as attributes in
the VHDL or Verilog source code. The following examples show how to add attributes in the Synplify and Leonardo-
Spectrum synthesis tool sets. For a complete list of supported attributes, refer to the HDL Attributes section of the
ispLEVER on-line help system.
-- VHDL example of specifying I/O type and location attributes for Synplify & Leonardo
entity cnt is
port(clk: in std_logic;
res: out std_logic);
attribute LEVELMODE: string:
attribute LEVELMODE of clk : signal is “SSTL2”;
attribute LOC of clk : signal is “V2”;
attribute LEVELMODE of res : signal is “SSTL2”;
attribute LOC of res : signal is “V3”;
end entity cnt;
-- Verilog example of specifying I/O type and location attributes for Synplify & Leonardo
module cnt(clk,res);
input clk /* synthesis LEVELMODE=”SSTL2” LOC=”V2”*/;
output res /* synthesis LEVELMODE=”SSTL2” LOC=”V3” */;
...
// exemplar begin
// exemplar attribute clk LEVELMODE SSTL2
// exemplar attribute clk LOC V2
// exemplar attribute res LEVELMODE SSTL2
// exemplar attribute res LOC V3
// exemplar end
endmodule
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HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Lattice Semiconductor
Implementation of Memories
Although an RTL description of RAM is portable and the coding is straightforward, it is not recommended because
the structure of RAM blocks in every architecture is unique. Synthesis tools are not optimized to handle RAM imple-
mentation and thus generate inefficient netlists for device fitting. For Lattice Semiconductor FPGA devices, RAM
blocks should be generated through IPexpress as shown in the following screen shot.
When implementing large memories in the design, it is recommended to construct the memory from the Enhanced
Block RAM (EBR) components found in every Lattice Semiconductor FPGA device. When implementing small
memories in the design, it is recommended to construct the memory from the resources in the PFU. The memory
utilizing resources in the PFU can also be generated by IPexpress.
Lattice Semiconductor FPGAs support many different memory types including synchronous dual-port RAM, syn-
chronous single-port RAM, synchronous FIFO and synchronous ROM. For more information on supported mem-
ory types per FPGA architecture, please consult the Lattice Semiconductor FPGA data sheets.
Preventing Logic Replication and Limited Fanout
Lattice Semiconductor FPGA device architectures are designed to handle high signal fanouts. When users make
use of clock resources, there will be no hindrance on fanout problems. However, synthesis tools tend to replicate
logic to reduce fanout during logic synthesis. For example, if the code implies Clock Enable and is synthesized with
speed constraints, the synthesis tool may replicate the Clock Enable logic. This kind of logic replication occupies
more resources in the devices and makes performance checking more difficult. It is recommended to control the
logic replication in synthesis process by using attributes for high fanout limit.
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In the Synplicity® project GUI, under the Implementation Options => Devices tab, users can set the Fanout Guide
value to 1000 instead of using the default value of 100. This will guide the tool to allow high fanout signals without
replicating the logic. In the LeonardoSpectrum tool project GUI, under Technology => Advanced Settings, users
can set the Max Fanout to be any number instead of the default value “0”.
Use ispLEVER Project Navigator Results for Device Utilization and Performance
Many synthesis tools give usage reports at the end of a successful synthesis. These reports show the name and
the number of library elements used in the design. The data in these reports do not represent the actual implemen-
tation of the design in the final Place and Route tool because the EDIF netlist will be further optimized during Map-
ping and Place and Route to achieve the best results. It is strongly recommended to use the MAP report and the
PAR report in the ispLEVER Project Navigator tool to understand the actual resource utilization in the device.
Although the synthesis report also provides a performance summary, the timing information is based on estimated
logic delays only. The Place & Route TRACE Report in the ispLEVER Project Navigator gives accurate perfor-
mance analysis of the design by including actual logic and routing delays in the paths.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
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Lattice Semiconductor FPGA
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July 2004
Technical Note TN1018
Introduction
Lattice Semiconductor’s ispLEVER® software, together with Lattice Semiconductor’s catalog of programmable
devices, provides options to help meet design timing and logic utilization requirements. Additionally, for those
instances where objectives push the capabilities of the device architecture, ispLEVER provides the tools for meet-
ing the most challenging requirements.
For the most aggressive design requirements, the designer should become familiar with a variety of timing con-
straints (called preferences) and Place And Route (PAR) techniques for providing the optimal PAR results. This
document describes these tips and techniques. Advanced techniques in floorplanning will not be discussed in this
document. Instead they are covered in technical note number TN1010, Lattice Semiconductor Design Floorplan-
ning.
ispLEVER Place and Route Software (PAR)
In the ispLEVER design flow, after a design has undergone the necessary translation to bring it into the mapped
physical design (.ncd file) format, it is ready for placement and routing. This phase is handled by the timing-driven
PAR software program. Designers can invoke PAR from the ispLEVER Project Navigator or from the command line.
PAR performs the following:
• Takes a mapped physical design (.ncd file) and a preference file (.prf) as input files.
• Places and routes the design, attempting to meet the timing preferences in the input .prf file.
• Creates a file which can then be processed by the ispLEVER design implementation tools.
Placement
The PAR process places the mapped physical design (.ncd file) in two stages: a constructive placement and an
optimizing placement. PAR writes the physical design after each of these stages is complete.
During constructive placement, PAR places components into sites based on factors such as:
• Constraints specified in the input file (for example, certain components must be in certain locations).
• The length of connections.
• The available routing resources.
• Cost tables which assign random weighted values to each of the relevant factors. There are 100 possible
cost tables.
Constructive placement continues until all components are placed. Optimizing placement is a fine-tuning of the
results of the constructive placement.
Routing
Routing is also done in two stages: iterative routing and delay reduction routing (also called cleanup). PAR writes
the physical design (.ncd file) only after iterations where the routing score has improved.
During iterative routing, the router performs an iterative procedure to converge on a solution that routes the design
to completion or minimizes the number of unrouted nets.
During cleanup routing (also called delay reduction), the router takes the results of iterative routing and reroutes
some connections to minimize the signal delays within the device. There are two types of cleanup routing that can
be performed:
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• A faster cost-based cleanup routing, which makes routing decisions by assigning weighted values to the
factors (for example, the type of routing resources used) affecting delay times between sources and loads.
• A more CPU-intensive, delay-based cleanup routing, which makes routing decisions based on computed
delay times between sources and loads on the routed nets.
Note that if PAR finds timing preferences in the preference file, timing-driven placement and routing is automatically
invoked.
Timing Driven PAR Process
The ispLEVER software offers timing driven placement and routing through an integrated static timing analysis util-
ity (i.e., it does not depend on input stimulus to the circuit). This means that placement and routing is executed
according to timing constraints (preferences) that the designer specifies up front in the design process. PAR
attempts to meet timing constraints in the preference file without exceeding the specified timing constraints.
To use timing-driven PAR, the designer simply writes timing preferences into a preference (.prf) file, which serves
as input to the integrated static timing analysis utility. See the Process Flows section of the ispLEVER on-line help
system for more information about the PAR software and ispLEVER design flow.
General Strategy Guidelines
Preferences should be inserted at the front end of a design flow. This prevents designers from having to change
PAR physical preferences as net names may change with every synthesis run.
The tips below are general recommendations.
• Analyze Trace results in the integrated static timing analysis utility report (.twr) file carefully.
• Look at mapped frequency before you PAR a design to check for errors and warnings in the preference file
and to check for logic depth. Logic depth is reported in .twr files as logic levels (components).
• Determine if design changes are required. A typical example design change is pipelining, or registering, the
datapath. This technique may be the only way to achieve high internal frequencies if the designs logic levels
are too deep.
• It is recommended to perform place and route early in the design phase with a preliminary preference file to
gather information about the design.
• Tune up your preference file to include all I/O and internal timing paths as appropriate. The Translating
Board Requirements into FPGA Preferences section of this document goes over an appropriate preference
file example.
• Establish the pin-out in the preference file. Locating I/O can also be done in the HDL, as well as in synthesis
constraint files.
• Push PAR when necessary by running multiple routing iterations and multiple placement iterations.
• Revise the preference file as appropriate, especially utilizing multicycle opportunities when possible.
• Floorplan the design if necessary (see technical note number TN1010, Lattice Semiconductor Design
Floorplanning).
• For Lattice Semiconductor ORCA Series devices, use clock boosting as a last resort, remembering to run
trace hold timing checks on the clock boosted design. Refer to the Clock Boosting section of this document
for more information on clock boosting.
Typical Design Preferences
The full preference language includes many different design constraints from very global preferences to very spe-
cific preferences. To a new user this is a very large list to digest and utilize effectively. Listed here are the recom-
mended preferences that should be applied to all designs. Refer to the Constraints & Preferences section of the
ispLEVER on-line help system for more information on preferences.
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• Block Asynchronous Paths: Prevents the timing tools from analyzing any paths from input pads to regis-
ters or from input pads to output pads.
• Block RAM Reads during Write: If using PFU based RAM, this will prevent timing analysis on a RAM read
during a write on the same address in a single clock period.
• Frequency/Period <net>: Each clock net in the design should contain a frequency or period preference.
• Input Setup: Each synchronous input should have an input_setup preference.
• Clock-to-Out: Each synchronous output should have a clock_to_out preference.
• Block <net>: All asynchronous reset nets in the design should be blocked.
• Multicycle: The multicycle preference allows the designer to relax a frequency/period constraint on
selected paths.
Proper Preferences
Providing proper preferences is key to a successful design. If the constraints of a preference file are tighter than the
system requirements, the design will end up being over-constrained. As a consequence, PAR run times will be con-
siderably longer. In addition, over-constraining non-critical paths will force PAR to waste unnecessary processing
power trying to meet these constraints, hence creating possible conflicts with real critical paths that ought to be
optimized first.
On the other hand, if a preference file is under-constrained compared to real system requirements, real timing
issues not previously seen during dynamic timing simulations and static timing analysis could be observed on a
test board, or during production.
Common causes of over-constrained timing preferences include:
• Multicycle paths not specified.
• Multiple paths to/from I/Os with different specifications.
• Attempt to fool the PAR tool with tighter than necessary specifications.
Note that over-constrained designs will also need a significantly larger amount of processing power and computing
resources. As a result, it might be necessary to increase some of the allocated system resources (as in increasing
your PC virtual memory paging size).
Common causes of under-constrained timing preferences include:
• I/O specifications not defined.
• Asynchronous logic without MAXDELAY preferences.
• Internally generated or unintentional clocks not specified in preference file.
• Blocking critical paths.
In general, to make sure that no critical paths were left out due to under-constraining, it is recommended to check
for path coverage at the end of a Trace report file (.twr).
An example of such an output is shown in Figure 16-1.
Figure 16-1. Trace Report (.twr) Timing Summary Example
Timing summary:
---------------
Timing errors: 4096 Score: 25326584
Constraints cover 36575 paths, 6 nets, and 8635 connections (99.0% coverage)
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This particular example shows a 99.0% coverage. The way to find unconstrained paths is to run Trace with the
“Check Unconstrained Paths” checkbox selected. This will give a list of all of the signals that are not covered under
timing analysis. In some designs, many of these signals are a common ground net that indeed does not need to be
constrained. Designers should understand this point and use Trace (the ispLEVER static timing analysis tool) to
check unconstrained paths to make sure they are not missing any design paths that are timing critical.
Also, note the timing score shown in Figure 16-1. The timing score shows the total amount of error (in picoseconds)
for all timing preferences constraining the design. PAR attempts to minimize the timing score, PAR does not
attempt to maximize frequency.
The above discussion can be summarized by the following single equality:
Quality of Preference File = Quality of PAR Results
Translating Board Requirements into FPGA Preferences
Understanding the system board level timing and design constraints is the primary requirement for producing a
complete preference file. As a result, the major requirements such as clock frequency, I/O timing and loads can be
translated into the appropriate preference statements in a constraint file.
The following exercise will provide an example on how to extract preferences from system conditions.
Figure 16-2 shows an example system involving the interface between a port controller and a Lattice Semiconduc-
tor FPGA.
Figure 16-2. Interface Timing Example
PCB traces
Board propagation
delay of 1 ns to 2 ns
Port
Controller
Lattice
FPGA
9 pf input capacitance,
9 pf input capacitance
60 pf AC load
3 ns to 18 ns clk to out,
5 ns setup, 3 ns hold
clk
Chip to chip clock skew of 1 ns
5 pf parasitic board capacitance
In the system above, several parameters have already been provided:
• System clock frequency: period (P): 30 ns.
• Port controller maximum output propagation delay (PDMAXp): 18ns.
• Port controller minimum output propagation delay (PDMINp): 3 ns.
• Port controller input setup specification (TSp): 5 ns.
• Port controller input hold specification (THp): 3 ns.
• Max board propagation delay (PDMAXb): 6 ns.
• Min board propagation delay (PDMINb): 1 ns.
• Port controller to FPGA device clock skew and vice versa (Tskew): 1 ns.
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• Board trace AC loading (Cbac): 60 pf.
• Board trace parasitic capacitance (Cb): 5 pf.
• Port controller input capacitance (Cp) :9 pf.
• FPGA device input capacitance (Co): 9 pf.
The above information was specified under the following environmental conditions:
• Maximum ambient temperature (Ta): 70 (C.
• Estimated Power Consumption (Q): 2 W.
• 680 PBGAM Package Thermal resistance (j) at 0 feet per minute (fpm) airflow: 13.4 °C/W.
The goal of this exercise is to compute the following device I/O constraints:
1. Input setup specification.
2. Input hold specification.
3. Maximum output propagation delay.
4. Minimum output propagation delay.
5. Output loading.
6. Temperature.
The only parameter which can be obtained from the above is the device junction temperature:
Tj = j * Q - Ta
= 13.4 * 2 + 70
= 96.8 °C
The required constraints can be computed as follows:
1. Input setup specification
= P - PDMAXp - PDMAXb - Tskew
= 30 - 18 - 2 - 1
= 9 ns
2. Input hold specification
= PDMINp + PDMINb - Tskew
= 3 + 1 - 1
= 3 ns
3. Output maximum propagation delay requirement
= P - TSp - PDMAXb - Tskew
= 30 - 5 - 6 - 1
= 18 ns
4. Output minimum propagation delay requirement
= Thp - PDMINb + Tskew
= 3 - 1 + 1
= 3 ns
5. Output loading
= Cbac + Cb + Cp
= 60 + 5 + 9
= 74 pf
The preference file to use for this example is shown in Figure 16-3. For more preference language syntax and
examples, refer to the Constraints & Preferences section of the ispLEVER on-line help system.
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Figure 16-3. Interface Timing Preference File Example
PERIOD PORT "clk" 30 NS ;
INPUT_SETUP "port_controller*" 9 NS HOLD 3 NS CLKNET "clk";
CLOCK_TO_OUT "port_controller*" 18 NS MIN 3 NS CLKNET "clk";
OUTPUT PORT "port_controller*" LOAD 74 PF ;
TEMPERATURE 96.8 C ;
Analyzing Timing Reports
This section describes two examples of actual Trace reports (.twr report file from Trace). The purpose is to analyze
both examples and understand each section of the reports given the design paths constrained.
Example 1. Multicycle Between Two Different Clocks
In this first example, CLKA and CLKB were assigned 104 MHz and 66 MHz frequencies respectively.
In addition, a multicycle constraint was specified as per the preference file:
FREQUENCY NET "CLKA" 104 MHZ ;
FREQUENCY NET "CLKB" 66 MHZ ;
MULTICYCLE "M2" START CLKNET "CLKA" END CLKNET "CLKB" 2.000000 X ;
See Figure 16-4 for the block diagram and waveform for this example. The resulting Trace report is shown in
Figure 16-5.
Figure 16-4. Multicycle Clock Domains Block Diagram and Waveform
Combinational
Logic
CLKA
CLKB
7.7ns
7.70 ns
7.90 ns
9.60 ns
CLKA
CLKB
7.9 ns
15.15 ns
30.30 ns
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Figure 16-5. Trace Report for Multicycle Clock Domains Example
================================================================================
Preference: MULTICYCLE "M2" START CLKNET "CLKA" END CLKNET "CLKB" 2.000000 X ;
40 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'CLKA' and net 'CLKB' not
computed: nets may not be related
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 27.945ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
Source:
Destination:
FF
FF
Q
v_fifo_bank_1_stfifo0_wr_count_2 (from CLKA +)
v_fifo_bank_1_stfifo0_wr_count_r_2 (to CLKB +)
Data in
Delay:
2.456ns (37.3% logic, 62.7% route), 1 logic levels.
Constraint Details:
2.456ns physical path delay PFU_155 to PFU_156 meets
30.302ns delay constraint less
-0.099ns DIN_SET requirement (totaling 30.401ns) by 27.945ns
Physical Path Details:
Name
REG_DEL
ROUTE
Fanout
---
Delay (ns)
Site
Resource
R22C16.Q2 PFU_155 (from CLKA)
R23C17.DIN2 v_fifo_bank_1_stfifo0_wr_countZ0Z_2 (to CLKB)
0.917
1.539
R22C16.CLK0 to
R22C16.Q2 to
1
--------
2.456
(37.3% logic, 62.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.192
2.989
Site
AM17.PAD to
AM17.INDD to
Resource
AM17.INDD ip_CLKA
LLPPLL.CLKIN ip_CLKA_c
MCLK_DEL
ROUTE
---
177
0.424
3.094
LLPPLL.CLKIN to
LLPPLL.MCLK to
LLPPLL.MCLK v_io_ppl3_tx4_1_mtppll_rsp_rsppll_0_0
R22C16.CLK0 CLKA
--------
7.699
(21.0% logic, 79.0% route), 2 logic levels.
Destination Clock Path:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.192
3.091
Site
C17.PAD to
C17.INDD to
Resource
C17.INDD ip_CLKB
ULPPLL.CLKIN ip_CLKB_c
MCLK_DEL
ROUTE
---
263
0.424
3.182
ULPPLL.CLKIN to
ULPPLL.MCLK to
ULPPLL.MCLK v_io_ppl3_tx4_1_mtppll_mac_macpll_0_0
R23C17.CLK0 CLKB
--------
7.889
(20.5% logic, 79.5% route), 2 logic levels.
In Figure 16-5, notice how the path is described in terms of “Logical Details.”
This section shows both the source and destination registers using their unmapped names from the EDIF (Elec-
tronic Data Interchange Format) file. This is a feature that allows the user to recognize the type of logic being ana-
lyzed.
Based on the declared frequencies for both clocks, we already know the following:
• CLKA period = 9.6 ns.
• CLKB period = 15.15 ns.
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• No relative phase information exists between both clocks. As a result, Trace does not factor in the skews on
either clock.
As a consequence, we know that, ignoring everything else (clock skews, registers library setups, etc.), a single
cycle positive edge to positive edge setup available from CLKA to CLKB is: 15.15ns (refer to waveforms in
Figure 16-4). Hence, with 2X multicycle, the resulting setup would be twice that number, or:
Ts = 30.3 ns
(shows up as delay constraint under Constraint Details section of Trace report)
Having computed this, the available setup margin is known to be as follows:
M = (Ts - Td) - Ds
Where:
• Td = path delay from clock pin of source register to D pin of destination=2.456 ns. Shown in the Physical
Path Details section of Trace report.
• Ds = destination cell library setup requirement= -0.099 ns. This matches DIN_SET under Constraint Details
section of the .twr Trace report.
There is no phase relationship between CLKA and CLKB as indicated by the warnings in Figure 16-5. Hence, the
following skews were correctly ignored:
• TSB = delay or skew on destination clock CLKB = 7.889 ns. Shown in the Clock Skews detail section of
Trace report.
• TSA = delay or skew on source clock CLKA = 7.699 ns. Shown in the Clock Skews detail section of Trace
report.
Hence:
• M = (30.3 - 2.46) - (-0.099) = 27.9 ns. This matches the number in the “PASSED” section at the top of the
Trace report.
Example 2. CLOCK_TO_OUT with PLL Feedback
In this example, ip_macclk_c is assigned to 66 MHZ and the clock to out propagation delays are constrained in the
preference file:
FREQUENCY NET "ip_macclk_c" 66 MHZ;
CLOCK_TO_OUT ALLPORTS 7.000000 ns CLKPORT "ip_macclk" ;
See Figure 16-6 for the block diagram for this example. The resulting Trace report is shown in Figure 16-7.
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Figure 16-6. CLOCK_TO_OUT with PLL
CPDEL = 8.25
DPDEL = 3.17 ns
FBDEL1 = 3.38
Logic
rxseln
ULPPL
FB
PIO
MCLK
ip_macclk_c
CLKI
ip_macclk
FBDEL0 = 0.424 ns
Figure 16-7. Trace Report for CLOCK_TO_OUT with PLL
================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 7.000000 ns CLKPORT "ip_macclk" ;
2 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.681ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
ppl3_rx5_1_rxselnio (from macclk +)
rxseln
Source:
IO-FF Out
Port
Q
Pad
Destination:
Data Path Delay:
Clock Path Delay:
3.164ns (100.0% logic, 0.0% route), 1 logic levels.
8.249ns (19.6% logic, 80.4% route), 2 logic levels.
Constraint Details:
8.249ns delay ip_macclk to rxseln less
5.094ns feedback compensation
3.164ns delay rxseln to rxseln (totaling 6.319ns) meets
7.000ns offset ip_macclk to rxseln by 0.681ns
Physical Path Details:
Clock path ip_macclk to rxseln:
Name
IN_DEL
ROUTE
MCLK_DEL
ROUTE
Fanout
---
1
---
141
Delay (ns)
1.192
3.235
Site
C17.PAD to
C17.INDD to
Resource
C17.INDD ip_macclk
ULPPLL.CLKIN ip_macclk_c
ULPPLL.MCLK v_io_ppl3_tx4_1/mtppll_mac/macpll_0_0
F32.SC macclk
0.424
3.398
ULPPLL.CLKIN to
ULPPLL.MCLK to
--------
8.249
(19.6% logic, 80.4% route), 2 logic levels.
Data path rxseln to rxseln:
Name
OUTREGF_DE ---
Fanout
Delay (ns)
3.164
Site
F32.SC to
Resource
F32.PAD rxseln (from macclk)
--------
(100.0% logic, 0.0% route), 1 logic levels.
Feedback path:
Name
MCLK_DEL
ROUTE
Fanout
---
141
Delay (ns)
0.424
3.380
Site
ULPPLL.CLKIN to
ULPPLL.MCLK to
Resource
ULPPLL.MCLK v_io_ppl3_tx4_1/mtppll_mac/macpll_0_0
ULPPLL.FB macclk
--------
3.804
(11.1% logic, 88.9% route), 1 logic levels.
Report:
6.319ns is the minimum offset for this preference.
16-9
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
The different path measurements were obtained from the Trace report shown in Figure 16-7 as follows:
• DPDEL = Data Path Delay = 3.16 ns. Shown under Physical Path Details-> Data path in the timing report.
• FBDEL0 = Feedback cell delay across PLL = 0.42 ns, which is the first entry value under Feedback Path.
• FBDEL1 = Feedback routing delay from PLL output to PLL FB pin = 3.38 ns, which is the second entry
value under Feedback Path.
The full feedback delay includes both FBDEL0 and FBDEL1 (0.42 + 3.38 = 3.80) under Feedback Path, in addition
to any internal PLL delay added after the FB pin. Such a delay is a programmable attribute defined as FB_PDEL.
This programmable value can be set to any of one of 4 values (DEL0, DEL1, DEL2 or DEL3; DEL0 being 0 delay)
in either the HDL file input to synthesis, or in the graphical Editor for Programmable Integrated Circuits (EPIC) soft-
ware tool included with the ispLEVER software.
Therefore, the total feedback delay would be:
FBDEL = FBDEL0 + FBDEL1 + FB_PDEL = 3.80 + FB_PDEL
Under “Constraint Details” of the report file, the feedback compensation (FBDEL) is shown to be 5.09 ns. Since this
value is different from 3.804, we conclude that a non-zero value of FB_PDEL was applied (5.10 - 3.80 = 1.29 ns).
This value corresponds to FB_PDEL = DEL2 in an OR4E4-2 device.
Now, let's verify the available margin on this CLOCK_TO_OUT preference:
M = CKOUT - (CPDEL + DPDEL - FBDEL)
= 7.000 - (8.249 + 3.164 - 5.094) = 0.681 ns
This value matches the one at the top of the report file (“Passed” section). It also matches the final value under
“Constraints Details”.
ispLEVER Controlled Place and Route
Extensive benchmark experiments have been performed in order to determine the most optimum per device
default settings for all PAR options. At times, improved timing results can be obtained on a design by design basis
by trying different variations of the PAR options. This section describes the techniques that can be used within the
ispLEVER graphical user interface (GUI) to improve timing results from Trace on placed and routed designs.
Running Multiple Routing Passes
Improved timing results can be obtained by increasing the number of routing passes during the Routing phase of
PAR.
The PAR options window in Figure 16-8 can be launched by the following steps:
1. In the Project Navigator Source window, select the target FPGA device.
2. In the Processes window, right-click the Place & Route Design process and select Properties to open the
dialog box.
In the example screen shot shown in Figure 16-8, the router will route the design for five routing iterations, or until
all the timing preferences are met, whichever comes first. For example, PAR will stop after the second routing itera-
tion if it hits a timing score of zero on the second routing iteration.
The highest selection in Placement Effort level will result in longer PAR run times but may give better design timing
results. A lower Placement Effort will result in shorter PAR run times but will likely give less than optimal design tim-
ing results.
16-10
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
Figure 16-8. PAR Options Window
Figure 16-9. Example PAR report (.par) File, Routing Section
0 connections routed; 26590 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 11 mins 31 secs
Starting iterative routing.
End of iteration 1
26590 successful; 0 unrouted; (151840) real time: 14 mins 29 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 2
26590 successful; 0 unrouted; (577) real time: 16 mins 23 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 3
26590 successful; 0 unrouted; (0) real time: 17 mins 39 secs
Dumping design to file
The place and route (.par) report file contains execution information about the PAR command run. The report also
shows the steps taken as the program converges on a placement and routing solution. In the routing convergence
example text in Figure 16-9, the number in parenthesis is the timing score after each iteration. In this example, tim-
ing was met after three routing iterations, as can be seen from the (0) timing score.
Using Multiple Placement Iterations (Cost Tables)
Using multiple placement iterations can be achieved by selecting the Advanced Options in Figure 16-8.
As shown in the Advanced Options of Figure 16-8, the number of iterations is set to 10 and the placement start
point is set to iteration 1 (cost table 1). Only the best NCD file is to be saved as per the following line. Once PAR
runs, the tool will loop back through the place and route flow until the number of iterations has reached 10. In this
16-11
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
example, the NCD file with the best timing score would be saved. The tool keeps track of the timing and routing per-
formance for every iteration in a file called the multiple par report (.par). Such a file is shown in Figure 16-10.
Figure 16-10. Multiple PAR Report (.par)
Level/
Cost [ncd]
----------
Number
Unrouted
--------
Timing
Score
-------
0
25
102
158
186
318
470
Run
Time
NCD
Status
-----
01:58
02:01
01:45
02:15
01:54
02:39
01:51
02:25
02:00
02:27
--------
Complete
Complete
Complete
Complete
Complete
Complete
Complete
Complete
Complete
Complete
5_4
5_6
5_2
5_7
5_3
5_10
5_1
5_8
5_5
5_9
*
0
0
0
0
0
0
0
0
0
0
562
732
844
* : Design saved.
Figure 16-10 indicates that:
• The “5_” under the Level/Cost column means that the Placement Effort level was set to 5. The Placement
Effort level can range from 1 (lowest) to 5 (highest).
• 10 different iterations ran (10 cost tables).
• Timing scores are expressed in total picoseconds (ps) by which the design is missing constraints on all
preferences.
• Iteration number 4 (cost table 4) achieved a 0 timing score and hence was the design saved. More than one
.ncd file can be saved. This is user-controlled via the “Placement Save Best Runs” value box shown in
Figure 16-8.
• Each iteration routed completely.
Note that, in Figure 16-8, if “Placement Iterations (0=run until solved)” is set to 0, the tool will run indefinitely
through multiple iterations until a 0 timing score is reached. In a design that is known to have large timing violations,
a 0 timing score will never be reached. As a consequence, the user must intervene and stop the flow at a given
point in time.
In general, multiple placement iterations can help placement but can also use many CPU cycles. Multiple place-
ment iterations should be used carefully due to system limitations and the uncertainty of results. It is better to fix the
root cause of timing problems in the design stage.
Clock Boosting
Clock boosting, supported in Lattice Semiconductor’s ORCA Series device family, is the deliberate introduction of
clock skew on a target flop to increase the setup margin. Every programmable flip-flop in the device has program-
mable delay elements before clock inputs for this purpose. The automated clock boosting tool will attempt to meet
setup constraints by introducing delays to as many target registers as needed to meet timing, in effect, borrow reg-
ister hold margins to meet register set-up timing. The following bullets summarize how clock boosting is accom-
plished in Lattice Semiconductor ORCA Series device family.
• A 4-tap delay cell structure in front of the clock port of every flip-flop in the device (includes I/O flip-flops)
• Ability to borrow clock cycle time from one easily-met path and give this time to a difficult-to-meet path
16-12
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
Clock boosting is typically most useful in designs that are only missing timing on a few paths for one or two prefer-
ences. If the design is missing timing by over a few nanoseconds on any given path, clock boosting will not be able
to schedule skew in a way that will eliminate enough timing to make the critical preference. Clock boosting run
times can be shortened by using a preference file with only the failing preferences in it.
Figure 16-11. Clock Boosting Example
Combinational
Logic
FF_1
FF_2
FF_3
11 ns
7 ns
DEL1
DEL2
DEL3
DEL1 ~= 0.7 ns
DEL2 ~= 1.3 ns
DEL3 ~= 2.0 ns
Clock
Target Performance: 10 ns period (100 MHz)
The example illustrated in Figure 16-11 shows two register-to-register transfers that both need to meet the 10 ns
period constraint. By using delay cell DEL2 to delay the clock input on flip-flop FF_2, the first register transfer will
make its period constraint with a new minimum period of ~9.7 ns and the second register transfer will make its
period constraint by ~8.3 ns.
The D1, D2, and D3 delays shown in Figure 16-11 are variable depending on the speed grade and Lattice Semi-
conductor FPGA device family. For complete timing information, reference the software generated timing data
sheet, included with ispLEVER, for the desired Lattice Semiconductor FPGA device family.
To Perform Clock Boosting in the Project Navigator
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Clock Boosting under Place & Route Design process, and then
select Properties to open the Properties dialog box.
3. Select the Clock Boosting Output Filename property from the property list and type the name of the out-
put file name in the edit region (<file_name>.ncd).
4. Click Close to close the dialog box.
As shown in Figure 16-12, the original .ncd and .prf files as well as the output .ncd file are typed into the corre-
sponding entries. Checking “Maximize Frequency” will push the tool to improve the frequency beyond the input
preference requirement. This is generally only useful for bench marking.
16-13
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
Figure 16-12. Clock Boosting Window
Other important considerations on the practicality of using clock boosting:
• Some circuits show big improvement, others have no gain. Clock boosting results are very design-depen-
dent.
• Clock boosting uses minimum delay values which have not yet been validated at the system level.
• Automatic clock boosting identifies skew and hold time issues. However, after clock boosting is performed,
designers are strongly recommended to run Trace twice, once with regular, maximum delay analysis, and
again with minimum delays. The designer should then read over both resultant .twr timing reports to make
sure there are no timing errors. The minimum delay analysis is done by checking the “Check Hold Times”
checkbox in the Trace Options GUI window.
Guided Map and PAR
To decrease PAR runtimes after minor changes to a logical design, guided mapping uses a previously generated
.ncd file to “guide” the mapping of the new logical design. Guided mapping can be performed from the Guide File-
name property in the Project Navigator Map Design process, or specified using the command line -g option with
the file name of the guide file. In general, guided MAP should only be used in conjunction with guided PAR.
To Perform Guided Mapping in the Project Navigator
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Map Design process, and then select Properties to open the
Properties dialog box.
3. Select the Guide Filename property from the property list and type the name of the guide file name in the
edit region (<file_name>.ncd).
4. Click Close to close the dialog box.
The Map operation will use the guide file to generate the new design file.
To Perform Guided PAR in the Project Navigator
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Place & Route Design process and select Properties to open the
dialog box.
3. Under Advanced Options, select the Guide Filename property and type the name of the file in the text
field.
16-14
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
4. Click Close to close the dialog box.
5. Double-click the Place & Route Design process. The ispLEVER software runs the process using the
specified guide file.
Notes on Guided Mapping
All guidance criteria is based on signal name matching. Topology of combinatorial logic is considered when Soft-
wire LUTs (SWLs) exist in the guided file.
Register elements are mapped in two passes. In the first pass, register control signals are matched by name
exactly. In the second pass, the control signals names are not matched. This methodology provides a greater
chance of matching for registers since control signal names have a tendency to change from successive synthesis
runs. Other matching considerations are as follows:
• For combinatorial logic, new SWLs are matched from SWLs extracted from the guide design.
• All unmatched logic are mapped through the regular mapping process.
• The performance of the guided mapped design can be no better than the original.
• A guide report, <design_name>.gpr, gives details of the success guided map had in matching with the
guide file.
Notes on Guided PAR
To decrease PAR runtimes after minor changes to the physical design file (.ncd), guided PAR uses a previously
placed and/or routed .ncd file to “guide” the placement and routing of the new .ncd file. Guided PAR can be per-
formed from the Project Navigator or specified using the command line -g option with the file name of the guide file.
For PAR to use a guide file for design, PAR first tries to find a guiding object (i.e., nets, components, and/or macros)
in the guide file that corresponds to an object in the new .ncd file. A guiding object is an object in the guide file of
the same name, type, and connectivity as an object in the new .ncd file. A guided object is an object in the new .ncd
file that has a corresponding guiding object in the guide file.
After PAR compares the objects in each file, it places and routes each object of the new .ncd file based on the
placement/routing of its guiding object. If PAR fails to find a guiding object for a component, for example, PAR will
try to find one based on the connectivity. PAR appends the names of all objects which do not have a guiding object
in the guide file to .gpr (Guided PAR Report) file. The matching factor specifies the percentage of the same connec-
tivity that guiding and guided objects must have. It can only be specified using the -mf option in the command line.
The matching factor option applies to nets and components only. When matching factor is 100 (the default), a guid-
ing object must have exactly the same connectivity as the object it is guiding. When a matching factor is specified,
the value specified is taken as the minimum percentage of the same connectivity that a guided object and its guid-
ing object have. Note that the matching factor is always 100 when the guided PAR is performed from the Project
Navigator.
After all guided objects are placed and routed, PAR locks down the locations of all guided components and macros
and then proceeds with its normal operation. Guided PAR supports the following preferences: USE SPINE, USE
PRIMARY, USE SECONDARY, USE LONGLINE, USE HALFLINE, LOCATE COMP, LOCATE MACRO, and hard-
placed PGROUPs.
Conclusion
In general, different designs respond better to different strategies. The processes outlined in this application note
may not be optimal for all cases. For a design's first place and route, run PAR at the low placer effort level and with
a low number of routing iterations. There is no point in running 100 cost tables if the design's logic depth is too high.
The techniques discussed within this document, like interpreting static timing reports and using proper preferences,
will guide the user to better PAR results.
16-15
Lattice Semiconductor FPGA
Successful Place and Route
Lattice Semiconductor
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
16-16
Board Timing Guidelines for the
DDR SDRAM Controller IP Core
June 2004
Technical Note TN1071
Introduction
This document describes how to meet board timing requirements for DDR signals. The Lattice DDR SDRAM Con-
troller IP core, non-pipelined version (DDR-NP) is used as an example.
Figure 17-1 describes the timing diagram for the DDR signals. A total of five clocks are used in the DDR board
design using the Lattice DDR IP core. The following is the clock description:
clk:
ddr_clk:
ddr_clk_n:
pll_mclk (clkx):
Input clock for PLL (max. frequency of 133MHz for DDR NP)
Output clock going to DDR (max. frequency of 133MHz for DDR NP)
Negated version of ddr_clk
Same as ddr_clk, used inside the FPGA only.
pll_nclk (clk2x): A 266MHz clock for DDR NP, used inside the FPGA only.
Figure 17-1. DDR Signal Timing Diagram
tCDQS
tDDR_CLK
tCCTRL
tBDCTRL
ddr_ad &
command signals
D
Q
tBDC
CLK
ddr_clk
pll_mclk
pll_nclk
FPGA
clkx tree
CLKIN
CLKFB
CLKX
DDR
MEMORY
ddr_clk_n
dqs_out
PLL
FPGA
clk2x tree
CLK2X
D
Q
tBDDS
tBDD
ddr_dq_out
(write flops)
ddr_dq
ENB
Q
D
tPD
ddr_dq_in
(read flops)
Q
D
tFPGA_CLK
tCDQ
www.latticesemi.com
17-1
tn1071_01.0
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
As shown in Figure 17-1, input to PLL is CLK (133MHz for DDR NP). The PLL generates pll_mclk(133MHz) and
pll_nclk(266MHz). The clocks ddr_clkand ddr_clk_ngo to DDR memory and are delayed by I/O pad delay
with respect to pll_mclk. The clocks pll_mclk and pll_nclk are internal to the FPGA. Command and
address signals are clocked by a negative edge of pll_mclk. The signal dqs_outacts as a clock for DDR write
and is generated by negative edge of pll_nclk. The signal ddr_dq_outis the DDR write data bus and gener-
ated by positive edge of pll_nclk. The flops ddr_dq_*latch the read data and are clocked by positive edge of
pll_nclk.
Read Operation
Figure 17-2 shows the timing of the DDR read operation. Table 17-1 describes the timing arcs of the read opera-
tion.
Figure 17-2. Read Timing Diagram
At DDR Interface
tAC (min)
tAC (min)
ddr_clk
DQ at DDR
(min case)
tAC (max)
tAC (max)
DQ at DDR
(max case )
Inside FPGA
tSKEW
tSKEW
pll_mclk
(inside FPGA)
tBDD + tPD
tBDD + tPD
DQ at FPGA
flops (min case)
tBDD + tPD
tBDD + tPD
DQ at FPGA
flops (max case)
17-2
Board Timing Guidelines
Lattice Semiconductor
Table 17-1. Read Operation Timing Arcs
Symbol
for the DDR SDRAM Controller IP Core
Example:
DDR-NP on ORCA 4
Description
tCK
Clock period of ddr_clk
7.5ns
Delay from the CLK input of the FPGA to the ddr_clkpad including Feedback
compensation (Clock Path Delay - Feedback Path).
tDDR_CLK (max)
2.471
Delay from the CLK input of the FPGA to the ddr_clkpad including Feedback
compensation (Clock Path Delay - Feedback Path).
tDDR_CLK (min)
tBDC
1.1381
—
Board delay of ddr_clkfrom FPGA to DDR SDRAM.
Time from the rising edge of ddr_clkafter which the data is available at DDR
output pins (max.).
tAC(MAX)
0.75ns
Time from the rising edge of ddr_clkafter which the data is available at DDR
tAC(MIN)
tBDD
-0.75ns
—
output pins (min.).
Board delay from DDR SDRAM data pad to the FPGA ddr_dqpad.
Propagation delay from FPGA input pad to the ddr_dq_inflip-flop input pin (Data
Path Delay).
tPD
0.0ns1
tFDS
Set-up time required by the ddr_dq_inflip-flop (INREG_SET).
Hold time required by the ddr_dq_inflip-flop (INREG_HLD).
Skew of the PLL.
3.195ns1
-1.609ns1
0.3ns
tFDH
tSKEW
Delay from the CLK input of the FPGA to the ddr_dq_inflip-flop clock input includ-
ing feedback compensation (Clock Out Path Delay - Feedback Path).
t
FPGA_CLK (max)
2.935ns1
1.239ns1
Delay from the CLK input of the FPGA to the ddr_dq_inflip-flop clock input includ-
ing feedback compensation (Clock Out Path Delay - Feedback Path).
tFPGA_CLK (min)
1. tFPGA_CLK, tDDR_CLK, tPD and tFDS can be easily obtained from the PNR time reports.
Set-up Time Calculation for the Data Input (Max. Case)
The DDR Controller IP core uses the positive edge of pll_nclkto latch in the data.
Table 17-1 timing arcs are used to calculate the following:
Max. delay of clock to ddr_dq_inflops = tFPGA_CLK (max) + (tCK * 1/2) - tSKEW - tFDS
Max. delay of DDR read data to ddr_dq_inflops = tDDR_CLK (max) + tBDC + tAC (max) + tBDD + tPD
To meet set-up time at ddr_dq_inflops, Clock Delay - Data Delay > 0
Therefore:
FPGA_CLK (max) + (tCK * 1/2) - tSKEW - tFDS - tDDR_CLK (max) - tBDC - tAC (max) - tBDD - tPD > 0
t
Isolating the board delays, we get:
(tBDD + tBDC) < tFPGA_CLK (max) + (tCK * 1/2) - tSKEW - tFDS - tDDR_CLK (max) - tAC (max) - tPD
(tBDD + tBDC) < 3.75 - 0.3 - 3.195 - 2.47 + 2.935 - 0.75 - 0.0
(tBDD + tBDC) < -0.03 ns
Hold Time Calculation for the Data Input (Min. Case)
As shown in Figure 17-2, the min data is available at DDR output pins after tAC (min) time from the rising edge of
ddr_clk. Since tAC (min) is generally a negative number, data appears before the rising edge. This data will incur
board delay (tBDD) and propagation delay from FPGA input pad to the flip-flop input pin (tPD).
Min. Delay of DDR read Data = tDDR_CLK (min) + tBDC + tAC (min) + tBDD + tPD
17-3
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Min. Delay of Clock to ddr_dq_inflops = tFPGA_CLK (min) + tSKEW + tFDH
To meet hold time at ddr_dq_inflops, Data Delay - Clock Delay > 0
Therefore:
DDR_CLK (min) + tBDC + tAC (min) + tBDD + tPD - tFPGA_CLK (min) - tSKEW - tFDH > 0
t
Isolating the board delays, we get:
(tBDD + tBDC) > tFPGA_CLK (min) + tSKEW + tFDH - tDDR_CLK (min) - tAC (min) - tPD
(tBDD + tBDC) > (1.239) ns + 0.3 + (-1.609ns) - (1.138) - (-0.75) - 0
(tBDD + tBDC) > -0.458 ns
Conclusion: To meet read set-up and hold timing, board delay for ddr_dq, ddr_clkand ddr_clk_nshould be:
-0.458ns < (tBDD + tBDC) < -0.03ns
Write Operation
For a proper write operation, data (ddr_dq) should meet set-up (tDS) and hold (tDH) time requirements of DDR
SDRAM with respect to ddr_dqs signal. The ddr_dqs signal is generated with respect to negative edge of
pll_nclkand data ddr_dqout is generated with respect to positive edge of pll_nclkas shown in Figure 17-3.
As a result, 1/2 clk2x(3.75ns/2) is provided as set-up and hold for ddr_dq_outwith respect to dqs_out.
For maximum set-up and hold margin, the ddr_dqsand ddr_dqtraces on the board should be matched.
Table 17-2. Write Operation Timing Arcs
Symbol
Description
ORCA 4
0.75ns
0.75 ns
—
tDS
Set-up time required by the DQ with respect to DQS for DDR SDRAM.
Hold time required by the DQ with respect to DQS for DDR SDRAM.
Clock-to-out timing for ddr_dqwith respect to pll_nclk.
Clock-to-out timing for ddr_dqswith respect to pll_nclk.
Board delay of ddr_dqsfrom FPGA to DDR SDRAM pins.
tDH
tCDQ
tCDQS
tBDDS
—
—
Figure 17-3. Write Timing Diagram
tCDQ
tCDQS
pll_nclk (clk2x)
dqs_out
ddr_dq_out
Write Set-up
Clock Delay = tCDQS + 1/2 clk2x- tDS + tBDDS
Data Delay = tCDQ + tBDD
17-4
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Clock Delay - Data Delay > 0
Therefore:
tCDQS + 1/2 clk2x- tDS + tBDDS - tCDQ - tBDD > 0
Assumptions for write set-up and hold equations:
1. tBDDS and tBDD are equal (board delays are same both for dqs_outand ddr_dq_out).
2. tCDQ and tCDQS are equal (both are output delays from I/O flop).
Therefore:
1/2 clk2x- tDS > 0
3.75/2 - 0.75 > 0
1.125 > 0
Write Hold
Data Delay = tCDQ + tBDD
Clock Delay = tCDQS + 1/2 clk2x+ tDH + tBDDS
Data Delay - Clock Delay > 0
Therefore:
CDQS + 1/2 clk2x- tDH + tBDDS - tCDQ - tBDD > 0
t
Assumptions for write set-up and hold equations:
1. tBDDS and tBDD are equal (board delays are same both for dqs_outand ddr_dq_out).
2. tCDQ and tCDQS are equal (both are output delays from I/O flop).
Therefore:
1/2 clk2x- tDH > 0
3.75/2 - 0.75 > 0
1.125 > 0
Address and Command Signals
Address (ddr_ad) and command signals (ddr_cas, ddr_ras, ddr_we) should meet set-up (tDS) and hold (tDH
)
timings at DDR interface with respect to positive edge of ddr_clk. Address and command signals are clocked
using negative edge of pll_mclk inside the FPGA as shown below. The ddr_clk signal is a delayed by pad
delay and board delay at DDR interface compared to pll_mclkinside the FPGA. As a result, 1/2clkxof set-up
and hold is provided by design.
17-5
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Table 17-3. Timing Arcs for Address and Command Signals
Symbol
Description
ORCA4
Is the clock-to-out time for ddr_ad and command signals.
t
CCTRL (max)
4.834 ns
2.147 ns
—
(Clock Path Delay - Feedback Path) + Data Path Delay
Is the clock-to-out time for ddr_ad and command signals.
(Clock Path Delay - Feedback Path) + Data Path Delay
tCCTRL (min)
tBDCTRL
Is the board delay of ddr_adand command signals from
FPGA pins to DDR SDRAM pins.
Figure 17-4. Timing Diagram for Address and Command Signals
At FPGA
CLK
tCCTRL
pll_mclk (clkx)
ddr_ad,
command_signals
tDDR_CLK + tBDC
At DDR Interface
tSKEW
tSKEW
ddr_clk
tBDCTRL
tDS
ddr_ad,
command_signals
tDH
Set-up Calculation
Max Delay of Clock to DDR = tDDR_CLK (max) + tBDC + tCK * 1/2 - tSKEW - tDS
Max Delays of command signals Data to DDR = tCCTRL (max) + tBDCTRL
To meet set up time at DDR memory, Clock Delay - Data Delay > 0
Therefore:
DDR_CLK (max) + tBDC + tCK * 1/2 - tSKEW - tDS - tCCTRL (max) - tBDCTRL > 0
Isolating the board delays, we get:
t
t
t
t
BDCTRL - tBDC < tDDR_CLK (max) + tCK * 1/2 - tSKEW - tDS - tCCTRL (max)
BDCTRL - tBDC < 2.47 + 3.75 - 0.3 - 0.75 - 4.834
BDCTRL - tBDC < 0.336 ns
17-6
Board Timing Guidelines
Lattice Semiconductor
Hold Calculation
for the DDR SDRAM Controller IP Core
Min Delay of command signals Data to DDR = tCCTRL (min) + tBDCTRL + tCK * 1/2
Min Delay of Clock to DDR = tDDR_CLK (min) + tBDC + tSKEW + tDH
To meet hold time at DDR memory, Data Delay - Clock Delay > 0
Therefore:
CCTRL (min) + tBDCTRL + tCK * 1/2 - tDDR_CLK (min) - tBDC - tSKEW - tDH > 0
Isolating the board delays, we get:
t
tBDCTRL - tBDC > - tCCTRL (min) - tCK * 1/2 + tDDR_CLK (min) + tSKEW + tDH
tBDCTRL - tBDC > -2.147 - 3.75 + (1.138) + 0.3 + 0.75
tBDCTRL - tBDC > -3.709
tBDCTRL - tBDC > -3.709 ns
Conclusion: To meet set-up and hold timings of command signals, board delay of command signals ddr_clkand
ddr_clk_nshould be:
-3.709 ns < (tBDCTRL - tBDC) < 0.336 ns
Board Design Guidelines
• The ddr_clkand ddr_clk_npads should be placed adjacent to each other in the FPGA to get similar
internal FPGA delays.
• The ddr_clkand ddr_clk_ntrace delays on the board should be matched.
• The DQ trace delays can be calculated using the following formula, for memory reads:
tSKEW + tFDH - tAC (min) - tPD - tDDR_CLK + tFPGA_CLK < (tBDD + tBDC) < (tCK * 1/2) - tSKEW - tFDS - tAC (max) - tPD
-
tDDR_CLK + tFPGA_CLK
• The DQ and DQS trace lengths should be balanced and matching to get maximum set-up/hold time during
memory writes.
• The address and control signals for the DDR SDRAM are generated on the negative edge of the FPGA
clock. The trace lengths for address and control lines are calculated using following equation:
-tCCTRL - tCK * 1/2 + tDDR_CLK + tSKEW + tDH < (tBDCTRL - tBDC) < tDDR_CLK + tCK * 1/2 - tSKEW - tDS - tCCTRL + tBDC
• As shown in Figure 17-1, both FPGA internal clock and ddr_clkare generated by a single PLL. It may be
difficult to meet read data Set-up and hold timing with a single PLL. As shown in Figure 17-5, a two-PLL
clocking scheme is proposed to meet read data set-up and hold timing. Adjusting feedback delay of PLL2
can control delay of pll_mclk. Increasing delay on pll_mclkcan increase the read set-up margin but it
also decreases the hold margin. To get better timing, skew between ddr_clkand pll_mclkhas to be
minimized.
17-7
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Figure 17-5. Two PLL Clocking Scheme
PLL1
ddr_clk_n
(133MHz)
MCLK
DIV2
sysCLOCK
133MHz
CLKIN
DIV0
PIO
PPLL
NCLK
DIV3
FB
DIV1
ddr_clk
pll1_nclk (133MHz)
(133MHz)
PLL2
PIO
pll_nclk (266MHz)
pll_mclk (133MHz)
MCLK
DIV2
CLKIN
DIV0
HPPLL
DDR SDRAM
Memory
NCLK
DIV3
FB
DIV1
N-stage TBUFs
DDRCT_NP
User interface
IP Core
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
17-8
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Appendix A. Example Extractions of Delays from Timing Reports
From the Set-up Report below, which was run for MAX conditions:
• tPD = 0.0 ns
• tFDS = 3.195 ns
• tFPGA_CLK (max) = 6.206 - 3.271 = 2.935 ns
===============================================================
Preference: INPUT_SETUP PORT “ddr_dq_*” 2.000000 ns CLKNET “pll_nclk” ;
32 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------------------
------------------------------------
Passed: The following path meets requirements by 1.740ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
Source:
Destination: O-FF In
pll_nclk +)
Port
Pad
ddr_dq_23
Data in
U1_ddrct_np_o4_1_008/U3_databusif/ddr_dqoeZ0Z_23 (to
Data Path Delay:
Clock Path Delay:
Constraint Details:
0.000ns (0.0% logic, 0.0% route), 0 logic levels.
6.206ns (29.3% logic, 70.7% route), 2 logic levels.
0.000ns delay ddr_dq_23 to ddr_dq_23 less
2.000ns offset ddr_dq_23 to clk (totaling -2.000ns) meets
6.206ns delay clk to ddr_dq_23 less
3.271ns feedback compensation less
3.195ns INREG_SET requirement (totaling -0.260ns) by 1.740ns
Physical Path Details:
Data path ddr_dq_23 to ddr_dq_23:
Name
Fanout
Delay (ns)
--------
Site
Resource
0.000
Clock path clk to ddr_dq_23:
(0.0% logic, 0.0% route), 0 logic levels.
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.431
0.816
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
NCLK_DEL
ROUTE
---
136
0.385 LLHPPLL.CLKIN to
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
N24.SC pll_nclk
3.574
--------
6.206
LLHPPLL.NCLK to
(29.3% logic, 70.7% route), 2 logic levels.
17-9
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.385 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
2.886
--------
3.271
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
Report:
0.260ns is the minimum offset for this preference.
From the Hold Report below, which was run for MIN conditions:
• tPD = 0.0 ns
• tFDH = -1.609 ns
• tFPGA_CLK (min) = 3.144 - 1.905 = 1.239 ns
===============================================================
Preference: INPUT_SETUP PORT “ddr_dq_*” 2.000000 ns CLKNET “pll_nclk” ;
32 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------------------
---------------
Passed: The following path meets requirements by 0.370ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
Source:
Port
Pad
ddr_dq_31
Destination:
(to pll_nclk +)
IO-FF In
Data in
U1_ddrct_np_o4_1_008/U3_databusif/ddr_dqoeZ0Z_31
Data Path Delay:
Clock Path Delay:
Constraint Details:
0.000ns (0.0% logic, 0.0% route), 0 logic levels.
3.144ns (25.7% logic, 74.3% route), 2 logic levels.
0.000ns delay ddr_dq_31 to ddr_dq_31 plus
0.000ns hold offset ddr_dq_31 to clk (totaling 0.000ns) meets
3.144ns delay clk to ddr_dq_31 plus
1.905ns feedback compensation less
-1.609ns INREG_HLD requirement (totaling -0.370ns) by 0.370ns
Physical Path Details:
Data path ddr_dq_31 to ddr_dq_31:
Name
Fanout
Delay (ns)
--------
Site
Resource
0.000
(0.0% logic, 0.0% route), 0 logic levels.
17-10
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Clock path clk to ddr_dq_31:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
0.576
0.507
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
NCLK_DEL
ROUTE
---
136
0.231 LLHPPLL.CLKIN to
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
C25.SC pll_nclk
1.830
--------
3.144
LLHPPLL.NCLK to
(25.7% logic, 74.3% route), 2 logic levels.
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.231 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
1.674
--------
1.905
LLHPPLL.NCLK to
(12.1% logic, 87.9% route), 1 logic levels.
Report: There is no minimum offset greater than zero for this preference.
From the Set-up Report below, which was run for MAX conditions:
• tDDR_CLK (max) = 5.741 - 3.271 = 2.47 ns
===========================================================================
Preference: CLOCK_TO_OUT PORT “ddr_cas_n” MAX 5.500000 ns CLKPORT “clk” CLKOUT PORT “ddr_clk”
;
1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------------------
------------------------------------
Passed: The following path meets requirements by 3.182ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_cas_nZ0 (from
ddr_cas_n
Source:
Unknown
Port
Q
ddr_clk_c -)
Destination:
Pad
Data Path Delay:
Clock Path Delay:
Constraint Details:
1.713ns (100.0% logic, 0.0% route), 1 logic levels.
6.346ns (28.6% logic, 71.4% route), 2 logic levels.
6.346ns delay clk to ddr_cas_n less
3.271ns feedback compensation
1.713ns delay ddr_cas_n to ddr_cas_n less
2.470ns delay clk to ddr_clk (totaling 2.318ns) meets
5.500ns offset clk to ddr_cas_n by 3.182ns
Physical Path Details:
Clock path clk to ddr_cas_n:
17-11
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.431
0.816
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
---
449
0.385 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
AE15.SC ddr_clk_c
3.714
--------
6.346
LLHPPLL.MCLK to
(28.6% logic, 71.4% route), 2 logic levels.
Data path ddr_cas_n to ddr_cas_n:
Name
OUTREG_DEL ---
Fanout
Delay (ns)
1.713
Site
AE15.SC to
Resource
AE15.PAD ddr_cas_n (from ddr_clk_c)
--------
1.713
Clock out path:
(100.0% logic, 0.0% route), 1 logic levels.
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.431
0.816
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
OUTDD_DEL
---
449
---
0.385 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
AF3.OUTDD ddr_clk_c
1.191
1.918
LLHPPLL.MCLK to
AF3.OUTDD to
AF3.PAD ddr_clk
--------
5.741
(65.0% logic, 35.0% route), 3 logic levels.
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.385 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
2.886
--------
3.271
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
Report:
2.318ns is the minimum offset for this preference.
From the Hold Report below, which was run for MIN conditions:
• tDDR_CLK (min) = 3.043 - 1.905 = 1.138 ns
===========================================================================
Preference: CLOCK_TO_OUT PORT “ddr_cas_n” MAX 5.500000 ns CLKPORT “clk” CLKOUT PORT “ddr_clk”
;
1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------------------
------------------------------------
Passed: The following path meets requirements by 1.056ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_cas_nZ0 (from
ddr_cas_n
Source:
Unknown
Port
Q
ddr_clk_c -)
Destination:
Pad
17-12
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
Data Path Delay:
Clock Path Delay:
Constraint Details:
0.928ns (100.0% logic, 0.0% route), 1 logic levels.
3.171ns (25.4% logic, 74.6% route), 2 logic levels.
3.171ns delay clk to ddr_cas_n less
1.905ns feedback compensation
0.928ns delay ddr_cas_n to ddr_cas_n less
1.138ns delay clk to ddr_clk (totaling 1.056ns) meets
0.000ns hold offset clk to ddr_cas_n by 1.056ns
Physical Path Details:
Clock path clk to ddr_cas_n:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
0.576
0.507
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
---
449
0.231 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
AE15.SC ddr_clk_c
1.857
--------
3.171
LLHPPLL.MCLK to
(25.4% logic, 74.6% route), 2 logic levels.
Data path ddr_cas_n to ddr_cas_n:
Name
OUTREG_DEL ---
Fanout
Delay (ns)
0.928
Site
AE15.SC to
Resource
AE15.PAD ddr_cas_n (from ddr_clk_c)
--------
0.928
(100.0% logic, 0.0% route), 1 logic levels.
Clock out path:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
0.576
0.507
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
OUTDD_DEL
---
449
---
0.231 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
AF3.OUTDD ddr_clk_c
0.778
0.951
LLHPPLL.MCLK to
AF3.OUTDD to
AF3.PAD ddr_clk
--------
3.043
(57.8% logic, 42.2% route), 3 logic levels.
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.231 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
1.674
--------
1.905
LLHPPLL.NCLK to
(12.1% logic, 87.9% route), 1 logic levels.
Report:
1.056ns is the maximum offset for this preference.
===========================================================================
17-13
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
From the Set-up Report below, which was run for MAX conditions. The report shown here is for ddr_ad.
• tCCTRL (max) = (6.392-3.271) + 1.713 = 4.834 ns
Find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. Then take the
max of those delays as tCCTRL (max).
============================================================================================
Preference: CLOCK_TO_OUT PORT “ddr_ad_*” 5.500000 ns CLKNET “ddr_clk_c” ;
12 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 0.666ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_adZ0Z_6 (from
ddr_ad_6
Source:
Unknown
Port
Q
ddr_clk_c -)
Destination:
Pad
Data Path Delay:
Clock Path Delay:
Constraint Details:
1.713ns (100.0% logic, 0.0% route), 1 logic levels.
6.392ns (28.4% logic, 71.6% route), 2 logic levels.
6.392ns delay clk to ddr_ad_6 less
3.271ns feedback compensation
1.713ns delay ddr_ad_6 to ddr_ad_6 (totaling 4.834ns) meets
5.500ns offset clk to ddr_ad_6 by 0.666ns
Physical Path Details:
Clock path clk to ddr_ad_6:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
1.431
0.816
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
---
449
0.385 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
AE14.SC ddr_clk_c
3.760
--------
6.392
LLHPPLL.MCLK to
(28.4% logic, 71.6% route), 2 logic levels.
Data path ddr_ad_6 to ddr_ad_6:
Name
OUTREG_DEL ---
Fanout
Delay (ns)
1.713
Site
AE14.SC to
Resource
AE14.PAD ddr_ad_6 (from ddr_clk_c)
--------
1.713
(100.0% logic, 0.0% route), 1 logic levels.
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.385 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
2.886
--------
3.271
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
Report:
4.834ns is the minimum offset for this preference.
17-14
Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
From the Hold Report below, which was run for MIN conditions. The report shown here is for ddr_ad* only.
• tCCTRL (min) = (3.124-1.905) + 0.928 = 2.147 ns
Find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. Then take the
min of those delays as tCCTRL (min).
===========================================================================
Preference: CLOCK_TO_OUT PORT “ddr_ad_*” 5.500000 ns CLKNET “ddr_clk_c” ;
12 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 2.147ns
Logical Details: Cell type Pin type
Cell name (clock net +/-)
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_adZ0Z_4 (from
ddr_ad_4
Source:
Unknown
Port
Q
ddr_clk_c -)
Destination:
Pad
Data Path Delay:
Clock Path Delay:
Constraint Details:
0.928ns (100.0% logic, 0.0% route), 1 logic levels.
3.124ns (25.8% logic, 74.2% route), 2 logic levels.
3.124ns delay clk to ddr_ad_4 less
1.905ns feedback compensation
0.928ns delay ddr_ad_4 to ddr_ad_4 (totaling 2.147ns) meets
0.000ns hold offset clk to ddr_ad_4 by 2.147ns
Physical Path Details:
Clock path clk to ddr_ad_4:
Name
IN_DEL
ROUTE
Fanout
---
1
Delay (ns)
0.576
0.507
Site
AB4.PAD to
AB4.INCK to LLHPPLL.CLKIN clk_c
Resource
AB4.INCK clk
MCLK_DEL
ROUTE
---
449
0.231 LLHPPLL.CLKIN to
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
T26.SC ddr_clk_c
1.810
--------
3.124
LLHPPLL.MCLK to
(25.8% logic, 74.2% route), 2 logic levels.
Data path ddr_ad_4 to ddr_ad_4:
Name
OUTREG_DEL ---
Fanout
Delay (ns)
0.928
Site
T26.SC to
Resource
T26.PAD ddr_ad_4 (from ddr_clk_c)
--------
0.928
(100.0% logic, 0.0% route), 1 logic levels.
Feedback path:
Name
NCLK_DEL
ROUTE
Fanout
---
136
Delay (ns)
0.231 LLHPPLL.CLKIN to
Site
Resource
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
1.674
--------
1.905
LLHPPLL.NCLK to
(12.1% logic, 87.9% route), 1 logic levels.
Report:
2.220ns is the maximum offset for this preference.
17-15
PCB Layout Recommendations
for BGA Packages
October 2011
Technical Note TN1074
Introduction
As Ball Grid Array (BGA) packages become increasingly popular and become more populated across the array
with higher pin count and smaller pitch, it is important to understand how they are affected by various board layout
techniques. This document provides a brief overview of PCB layout considerations when working with BGA pack-
ages. It outlines some of the most common problems and provides tips for avoiding them at the design stage. A key
challenge of adopting fine-pitch (0.8 mm or less) BGA packages is the design of a route fanout pattern that maxi-
mizes I/O utilization while minimizing fabrication cost. This technical note provides an overview of PCB design
examples provided by Lattice Semiconductor.
For more information and design examples see the PCB Design Support page at the Lattice Semiconductor web
site (www.latticesemi.com/support/pcbdesignsupport.cfm).
BGA Board Layout Recommendations
In order to evenly balance the stress in the solder joints, Lattice recommends that PCB solder pads match the cor-
responding package solder pad type and dimensions. If a different PCB solder pad type is used, the recommended
pad dimension is based on an equivalent surface contact area.
Table 18-1. Lattice SMD/NSMD Pad Recommendations1
0.4 mm
Ball Pitch
0.5 mm
0.8 mm
1.0 mm
Ball Pitch
1.27 mm
Ball Pitch
Ball Pitch Ball Pitch
256 ftBGA
(Option 23),
324 ftBGA,
56, 64,
100
fpBGA,
144, 208, 256,
388, 484, 672,
272, 388
PBGA,
100, 132, 100, 256,
1020, 1152,
64, 132
ucBGA
25
WLCSP
144
csBGA
332
256 ftBGA 676, 900, 1152, 1704 Organic 256, 352
caBGA (Option 12) 1156 fpBGA
fcBGA
SBGA
Package Solder Pad Type
SMD
NSMD
0.25
SMD
0.35
SMD
0.50
SMD
0.50
SMD
0.55
SMD
SMD
Nominal BGA package solder pad
diameter (mm)
0.27
0.20
0.17
0.65
0.55
0.52
0.73
0.63
0.58
Optimum PCB (SMD) Solder
Mask Opening (mm)
0.28
0.25
0.25
0.23
0.40
0.35
0.40
0.35
0.45
0.40
Optimum PCB (NSMD) Solder
Land Diameter (mm)
1. These Lattice recommended PCB design values will result in optimum Board Level Reliability (BLR) performance for each corresponding
package. Designers who use PCB design values which deviate from these recommendations should understand that the BLR performance
may be reduced.
2. ispMACH 4000, MachXO and LatticeXP2.
3. LatticeECP3 and MachXO2.
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
18-1
tn1074_02.1
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Table 18-2. Lattice BGA Package Types
Package Type
Description
PBGA
fpBGA
ftBGA
Plastic BGA with 1.27 mm solder ball pitch. Die up configuration.
Fine Pitch BGA – Plastic BGA with 1.0 mm solder ball pitch. Die up configuration.
Fine Pitch Thin BGA – Thin plastic BGA with 1.0 mm solder ball pitch. Die up configuration.
Chip Array BGA – Plastic BGA with 0.8 mm solder ball pitch. Die up configuration.
Chip Scale BGA – Plastic BGA with 0.5 mm solder ball pitch. Die up configuration.
Flip-Chip BGA with 1.0 mm solder ball pitch. Die down configuration.
caBGA
csBGA
fcBGA
Super BGA – Similar to PBGA, but with an integrated heatsink plate. This package has 1.27 mm solder ball
pitch and die down configuration. SBGA packages offer enhanced thermal dissipation capability.
SBGA
ucBGA
WLCSP
Ultra Chip BGA – Saw-singulated plastic ball grid array package with 0.4 mm ball pitch.
Wafer-Level Chip Scale Package – Saw-singulated package with 0.4 mm ball pitch built onto a silicon
device. Die down configuration.
BGA Breakout and Routing Examples
Lattice provides several resources and different design implementations that show BGA breakout and routing of
various fine-pitch BGA packages. Different stack up and layer counts are also used to show a range of design rules
and fabrication costs. It is important to consult with your board fabrication and assembly houses as to the most
economical and reliable process for your application.
Currently there is a wide choice of BGAs from Lattice, with many devices offered in multiple packages and pitches
of BGA densities as well as non-BGA options such as TQFP, QFN and others. The BGA pitch or “center to center”
ball dimensions include, 1.00 mm BGAs, space-saving 0.5 mm pitch chip scale BGA and 0.4mm pitch ultra chip
scale BGA packages. Fine pitch packages offer advantages and disadvantages alike. Finer pitch means that the
trace and space limits will have to be adjusted down to match the BGA. Many times a design can get away with
small traces underneath the BGA then fan out with a slightly larger trace width. The PCB fabrication facility will
need to be aware of your design objectives and check for the smallest trace dimensions supported. Smaller traces
take more time to inspect, check and align etc. Etching needs to be closely monitored when trace and space rules
reach their lower limit.
The combination of fanout traces, escape vias, and escape traces that allow routing out from under the BGA pin
array to the perimeter of the device are collectively referred to as the “BGA breakout”. The fanout pattern will
arrange the breakout via, layer, and stack-up to maximize the number of I/Os that can be routed. Fanout patterns
are an important consideration for devices over 800 pins and can be follow polar (north/south/east/west) or layer-
biased directions. (Source: BGA Breakouts and Routing, Charles Pfeil, Mentor Graphics).
18-2
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-1. BGA Breakout Routing Terms
Lattice provides BGA breakout and routing examples for various fine pitch packages (www.latticesemi.com/sup-
port/pcbdesignsupport/bgabreakoutroutingexample/index.cfm). Each package example is built to comply with
IPC7351 (www.ipc.org) specifications and nomenclature conventions. Some examples include different layout
options depending on design and cost goals. For example, the 256-ball chip array BGA (BN256/BG256) examples
demonstrate a design with fully-utilized I/Os, fine trace width and pitch, on a 6-layer PCB stack-up and a less
expensive design with relaxed design rules, and fewer I/O pads routed, on a 4-layer PCB stack up.
Table 18-3. Package Layout Example Summary
Signal/
Power
Layers
Trace/
Width-
Space (mm)
Ball Pad Ball Mask
Via Pad
(mm)
Via Drill
(mm)
Package
MN64/MG64
Example # Pitch (mm)
(mm)
0.23
0.18
0.23
0.23
0.23
0.23
0.23
0.23
0.35
0.35
(mm)
0.33
0.28
0.38
0.38
0.38
0.38
0.33
0.38
0.50
0.50
1
1
1
2
1
2
1
2
1
2
0.5
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.8
0.8
6
6
4
4
4
4
6
4
6
4
.100/.100
.100/.100
.085/.085
.100/.100
.085/.085
.100/.100
.100/.100
.100/.100
.100/.100
.100/.100
0.30
0.25
0.45
0.45
0.40
0.40
0.30
0.30
0.40
0.40
0.125
0.10
UMN64/UMG64
0.20
MN100
0.20
0.15
MN132/MG132
MN144
0.15
0.125
0.125
0.125
0.15
BN256/BG256
For mechanical dimension details on packages, see the Lattice Package Diagrams document.
In order to show how some of the routing challenges are solved, examples are provided for fine-pitch BGA pack-
ages from the MachXO™ and the ispMACH® 4000ZE families. Principles for these apply to other Lattice BGA
packaged products.
18-3
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
64-ball csBGA BGA Breakout and Routing Example
This example places an ispMACH 4000ZE CPLD in a 5x5 mm, 0.5 mm pitch, 64-ball csBGA package (LC4064ZE-
MN64) in an 6-layer stack up with maximum I/O utilization.
Figure 18-2. CAM Artwork Screen Shots 64-Ball csBGA
Layer 1 Primary
Layer 2 Signal
Layer 3 GND
Layer 4 Power
Layer 5 Signal
Layer 6 Secondary
18-4
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
64-ball ucBGA BGA Breakout and Routing Example
This example places an ispMACH 4000ZE CPLD in a 4x4 mm, 0.4 mm pitch, 64-ball ucBGA package (LC4064ZE-
UMN64) in an 6-layer stack up with maximum I/O utilization. This example demonstrates a modified dogbone
fanout technique to get access to all pins yet limiting number of layers and via schedules, while setting up layers to
use reference planes for high-speed signal traces.
Figure 18-3. CAM Artwork Screen Shots, 64-Ball ucBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Signal
Layer 4 Signal
Layer 5 Power
Layer 6 Secondary
18-5
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
100-ball csBGA BGA Breakout and Routing Examples
These examples place a MachXO PLD in a 8x8 mm, 0.5 mm pitch, 100-ball csBGA package (LCMXO640-
M132/MN132) into two fabrication scenarios. Both examples utilize a 4-layer stack-up. The first example uses
0.085mm trace and 0.085 mm space design rules for maximum I/O accessibility; while the second example uses
0.100mm trace and 0.100mm space design rules and provides 15% less I/O.
Figure 18-4. CAM Artwork Screen Shots, Example #1, 100-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
18-6
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-5. CAM Artwork Screen Shots, Example #2, 100-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
18-7
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
132-ball csBGA BGA Breakout Examples
These examples place a MachXO PLD in a 8x8 mm, 0.5 mm pitch, 132-ball csBGA package (LCMXO640-
M132/MN132) into two fabrication scenarios. Both examples utilize a 4-layer stack-up. The first example uses
0.085mm trace and 0.085 mm space design rules for maximum I/O accessibility; while the second example uses
0.100mm trace and 0.100mm space design rules and provides 15% less I/O.
Figure 18-6. CAM Artwork Screen Shots, Example #1, 132-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
18-8
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-7. CAM Artwork Screen Shots, Example #2, 132-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
18-9
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
144-ball csBGA BGA Breakout Examples
These examples place an ispMACH 4000ZE in a 7x7 mm, 0.5 mm pitch, 144-ball csBGA package (LC4256ZE-
MN144) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O utilization and a 4-layer with
about 5% fewer I/Os. The 6-layer (Example #1) design avoids uses of micro vias and takes advantage of removed
pads on inner layers to route all pins out to 6 layers with good layer structure for high-speed signal integrity.
Figure 18-8. CAM Artwork Screen Shots, Example #1, 144-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Signal
Layer 4 Signal
Layer 5 Power
Layer 6 Secondary
18-10
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-9. CAM Artwork Screen Shots, Example #2, 144-ball csBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
18-11
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
256-ball caBGA BGA Breakout Examples
This BGA breakout and routing example places a MachXO PLD in a 14x14 mm, 0.8 mm pitch, 256-ball caBGA
package (LCMXO2280-B256/BN256) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O
utilization and a 4-layer with about 10% fewer I/Os. The 6-layer design (Example #1), demonstrates the best use of
mechanically drill blind vias to place caps near power pins to minimize layers.
Figure 18-10. CAM Artwork Screen Shots, Example #1, 256-Ball caBGA
Layer 1 Primary
Layer 2 Signal
Layer 3 GND
Layer 4 Power
Layer 5 Signal
Layer 6 Secondary
18-12
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-11. CAM Artwork Screen Shots, Example #2, 256-ball caBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
PCB Fabrication Cost and Design Rule Considerations
PCB fabrication cost is a key consideration for many electronics products. By reviewing the IC device package ball
density and pitch, I/O signal requirements of your application, and the manufacturing constraints of your PCB fabri-
cation facility you can better weigh the trade-offs between design decisions.
Choosing the best package for your application involves answering a few questions:
• What is the driving factor in the application? The smallest possible form factor or a low PCB cost?
• How many I/O signals does the application require?
• What PCB layer stack up will provide the best I/O density within budget?
• What layout design rules does the printed-circuit board (PCB) vendor support?
• How many PCB layers does the budget allow?
As the ball pitch becomes smaller with each new BGA generation, new PCB fabrication techniques and signal via
type have been developed to handle the complexities. Micro vias, laser vias, filled, buried and blind vias, even bur-
ied and plated over vias. Complex boards use a combination of most of these.
18-13
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Stack-up types, ordered by cost, high-to-low include:
• High-Density Interconnect (HDI) build up with micro vias
• Laminated with blind and buried vias
• Laminated with through vias
Figure 18-12. Stack-up Example
HDI is a “sandwich” with older-style larger geometry in the middle with fully drilled through holes and then a stack
of fine geometry of blind, buried or mixed via, laminated both on the top and bottom of the middle stack-up. The
laminated layers are thinner than traditional layers and allow finer drilling technology. Staggered micro vias allow
vias within close tolerance or connected to a BGA pad to go down to the next layer or more to route away for
escape routing or underneath the BGA device for further interconnect. HDI type interconnect is used on complex
boards and takes extra steps in the processing flow due to special drilling, plating an laminations. It is a mix of older
technology mixed with newer technology that results in a board that is highly routable.
Figure 18-13. HDI Stack-up with Staggered Micro Vias
Advantages and Disadvantages of BGA Packaging
As pin counts increase and board space becomes more valuable, it is important to place as many circuits per
square inch as possible. BGA offer the best I/O density for a given PCB area. Lattice offers a range of packages
from a 4x4 mm 64-ball csBGA to a 33x33 mm 1704-ball fcBGA.
One of the greatest advantages of BGA packaging is that it can be supported with existing placement and assem-
bly equipment. BGAs also offer significantly more misalignment tolerance and less susceptibility to co-planarity
issues. Even if the solder paste is misaligned or the device is slightly offset, the BGA will self-center during the
18-14
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
reflow process. This is due to the surface tension of the solder and flux in its molten state pulling each ball into the
center of the pad.
Figure 18-14. Misalignment of BGA Balls vs. QPF Leads
Controlling the oven re-flow profile is one of the most important assembly parameters for consistent and reliable
BGA placement. Profiles are typically tested on a pre-run. One or two panels are run to dial in the process, then
visual and X-ray inspection equipment are used for verification.
BGA packages present numerous benefits previously unobtainable in surface mount packaging technology. BGAs
provide higher pin counts in a much smaller area than was previous possible. No longer is the package design lim-
ited to connections along the periphery on the outside quadrants of the package edge like a PQFP or TQFP out-
line. Fully populated ball grid arrays with pitches as small as 0.4 mm are available.
Some BGA devices are arranged with de-populated interconnect near or around the center. These are dependent
on the die size and number of pins. The area void of interconnect in the middle of the array has some advantages,
it can be used for escape routing vias or tying directly to the ground or power planes.
Although the packages can be quite complex and densely populated, all of these packages receive strict quality
and reliability testing and are widely accepted today by designers and PCB fabrication/assembly houses. All of this
is due to advances in equipment and technology that have allowed a smooth transition into the assembly flow.
BGA Package Test and Assembly
How can a pad/ball/pin be tested that can’t be seen? All connections are hidden under the substrate at the ball
interconnect, making it impossible to directly probe or test. To address this limitation, Lattice programmable devices
provide JTAG, BSCAN, and boundary scan cells that allow electronic test and continuity of each pin with a bound-
ary scan tester. This can be embedded into the system itself or driven externally from a high-speed test head. The
boundary scan can test the pins or board for simple continuity tests or full functional test by shifting in test patterns
through the JTAG port.
For debug or prototype boards it may be necessary to place test points, open vias, or pads to have access to a
given set of pins in order to drive, over-drive or observe a given set of signals. These can be very small, as many
18-15
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
pogo pin type probes are extremely small and can handle GHz range DC frequency. Zero ohm resistors are also
commonly used in first-run boards as a way to gain access to a pad or pin.
After assembly, BGA solder point quality and integrity is visually inspected with X-ray technology as part of the fab-
rication process. A special X-ray machine can look through the plastic package, substrate and silicon to directly
view the BGA solder balls, vias, traces and pads.
Figure 18-15. Example of How Defects May Appear in an X-Ray Image
The X-ray image in Figure 18-16 shows proper alignment; no voids or defects are noted. Balls, vias and traces are
visible.
Figure 18-16. X-Ray Inspection Plot of ispMACH 4000ZE 144-ball csBGA
(Photo Courtesy of CEM, Ltd., www.cemltd.com)
18-16
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
PCB cross-sectioning is another method used to verify BGA and PCB quality and reliability. After a new process
has been developed or changed or when qualifying a new vendor, it is a good practice to get physical information
from the vendor on their BGA reflow. When trace/space and drill or laser tolerances are nearing their limits, board
yield can be as be as low as 50% for the bare board fab. Cross-sections give you a good idea if the process is cor-
rect but do not guarantee each batch or each board design will behave the same way due to layout dimensions,
thermal issues, flux/paste and alignment, etc.
Figure 18-17 shows a BGA cross-section that uses a non-soldermask over bare copper-defined pad. (NSMD) pad.
Figure 18-17. BGA Cross-Section
Figure 18-18 shows “offset” micro via stack routing between layers.
Figure 18-18. Cross-Section of Micro Vias
High-resolution video cameras are used for edge inspection to verify ball seating, distortion, solder wetting, flow,
contaminates, etc. Figure 18-19 is a video view of a side/edge shot looking at BGA balls soldered down to the isp-
MACH 4000ZE Pico Evaluation Board (www.latticesemi.com/4000ze-pico-kit), an FR4 4-layer PCB.
18-17
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Figure 18-19. Edge View Camera Inspection
In the photos samples above, trained technicians and computer camera recognition equipment are used for inspec-
tion of the X-ray results, looking for voids, shorts, missing connections, contaminants, alignment or other gross fail-
ure mechanisms. For example, in Figure 18-19, the BGA ball connections appear to be squashed downward, with
mild distortion, insuring that proper oven profile temperatures were achieved.
These technologies help in the successful placement and long term use of BGAs in the industry’s latest products.
Further advancements have been made in material content to conform to environmental issues, toxic materials and
recycling. Another issue that relates to board design is the physical silkscreen logos and information related to
recycling, lead content and other hazardous waste components, strict adherence must be paid to these require-
ments. Although a documentation and silkscreen issue, it can become a challenge to fit this information on the
board in some cases due to component population and must be accounted for in overall board real estate.
PCB Design Support
Lattice provides a collection of PCB design resources at www.latticesemi.com/support/pcbdesignsupport.cfm
including schematic libraries, PCB CAM viewers, technical notes, and BGA breakout and routing examples.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
18-18
PCB Layout Recommendations
for BGA Packages
Lattice Semiconductor
Revision History
Date
Version
01.0
Change Summary
January 2005
November 2005
June 2006
Initial release.
01.1
Figures updated.
01.2
Removed NSMD content.
September 2006
01.3
Added note to BGA Board Layout Recommendations table.
Reformatted BGA Package Types section in tabular format.
March 2008
May 2009
01.4
01.5
01.6
01.7
Revised recommended Solder Mask Defined and Non Solder Mask
Defined PCB solder pad dimensions to match industry standards.
Updated BGA Board Layout Recommendations table and BGA Pack-
age Types table for 0.4 mm pitch ucBGA package.
February 2010
March 2010
Edits to most sections and additional links and graphics added for each
example.
Replaced Lattice BGA Naming Conventions table with Lattice Semicon-
ductor BGA Package Types table and SMD/NSMD Pad Recommenda-
tions table.
August 2010
01.8
Lattice Semiconductor SMD/NSMD Pad Recommendations table:
Specified nominal Solder Mask Opening for each Lattice BGA package,
clarified recommended Solder Mask Opening and Solder Pad Diame-
ters and added cautionary note.
September 2010
February 2011
01.9
02.0
Lattice Semiconductor SMD/NSMD Pad Recommendations table -
Added 64 csBGA to 0.5mm pitch column.
Updated BGA Board Layout Recommendations text section.
Updated Lattice SMD/NSMD Pad Recommendations table.
Added WLCSP to Lattice SMD/NSMD Pad Recommendations table.
October 2011
02.1
Replaced reference to 6-layer example with description of two 4-layer
examples for 100-ball and 132-ball csBGA.
18-19
Section III. LatticeXP Family Handbook Revision History
LatticeXP Family Handbook
Revision History
Handbook HB1001
October 2011
Revision History
Handbook
Revison Number
Date
Change Summary
February 2005
April 2005
01.0
01.1
Initial release.
LatticeXP Family Data Sheet updated to version 01.1.
Technical note TN1051 updated to version 01.1.
LatticeXP Family Data Sheet updated to version 01.2.
LatticeXP Family Data Sheet updated to version 02.0.
Technical note TN1052 updated to version 02.1.
LatticeXP Family Data Sheet updated to version 02.1.
Technical note TN1056 updated to version 03.1.
LatticeXP Family Data Sheet updated to version 02.2.
LatticeXP Family Data Sheet updated to version 03.0.
May 2005
July 2005
01.2
01.3
July 2005
01.4
August 2005
September 2005
September 2005
October 2005
01.5
01.6
01.7
01.8
LatticeXP Family Data Sheet updated to version 03.1.
Technical note TN1056 updated to version 03.2.
Technical note TN1051 updated to version 01.5.
Technical note TN1050 updated to version 03.1.
Technical note TN1049 updated to version 04.0.
Technical note TN1082 updated to version 01.3.
Technical note TN1054 updated to version 01.1.
Technical note TN1008 updated to version 02.1.
Technical note TN1074 updated to version 01.1.
LatticeXP Family Data Sheet updated to version 04.0.
LatticeXP Family Data Sheet updated to version 04.1.
Technical note TN1051 updated to version 01.6.
Technical note TN1082 updated to version 01.4.
Technical note TN1054 updated to version 01.2.
LatticeXP Family Data Sheet updated to version 04.2.
LatticeXP Family Data Sheet updated to version 04.3.
Technical note TN1056 updated to version 03.3.
LatticeXP Family Data Sheet updated to version 04.4.
LatticeXP Family Data Sheet updated to version 04.5.
Technical note TN1051 updated to version 01.7.
LatticeXP Family Data Sheet updated to version 04.7.
Technical note TN1074 updated to version 01.3.
Technical note TN1051 updated to version 01.8.
Technical note TN1049 updated to version 04.1.
LatticeXP Family Data Sheet updated to version 04.8.
Technical note TN1052 updated to version 02.2.
LatticeXP Family Data Sheet updated to version 04.9.
December 2005
February 2006
02.0
02.1
March 2006
March 2006
02.2
02.3
April 2006
May 2006
02.4
02.5
October 2006
02.6
December 2006
February 2007
02.7
02.8
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
20-1
Revision History
Lattice Semiconductor
LatticeXP Family Handbook
Handbook
Revison Number
Date
Change Summary
April 2007
July 2007
02.9
03.0
Technical note TN1050 updated to version 03.2.
LatticeXP Family Data Sheet updated to version 05.0.
Technical note TN1049 updated to version 04.3.
LatticeXP Family Data Sheet updated to version 05.1.
Technical note TN1050 updated to version 03.2.
Technical note TN1082 updated to version 01.6.
Technical note TN1074 updated to version 01.6.
Technical note TN1082 updated to version 01.9.
Technical note TN1074 updated to version 01.7.
Technical note TN1074 updated to version 01.9.
Technical note TN1074 updated to version 02.0.
Technical note TN1074 updated to version 02.1.
November 2007
March 2010
03.1
03.2
March 2010
September 2010
September 2011
October 2011
03.3
03.4
03.5
03.6
Note: For detailed revision changes, please refer to the revision history for each document.
20-2
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