LX128BIFN10032_技术文档

™

ispGDX2 Family

High Performance Interfacing and Switching

September 2005

Data Sheet

■ Two Options Available

Features

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

■ High Performance Bus Switching

• High bandwidth

■ sysHSI Blocks Provide up to 16 High-speed

Channels

– Up to 12.8 Gbps (SERDES)

– Up to 38 Gbps (without SERDES)

• Up to 16 (15x10) FIFOs for data buffering

• High speed performance

• Serializer/de-serializer (SERDES) included

• Clock Data Recovery (CDR) built in

• 800 Mbps per channel

• LVDS differential support

• 10B/12B support

– f

= 360MHz

MAX

– t = 3.0ns

PD

– t = 2.9ns

CO

– Encoding / decoding

– Bit alignment

– Symbol alignment

– t = 2.0ns

S

• Built-in programmable control logic capability

• I/O intensive: 64 to 256 I/Os

• Expanded MUX capability up to 188:1 MUX

• 8B/10B support

– Bit alignment

– Symbol alignment

• Source Synchronous support

■ sysCLOCK™ PLL

• Frequency synthesis and skew management

• Clock multiply and divide capability

• Clock shifting up to +/-2.35ns in 335ps steps

• Up to four PLLs

■ Flexible Programming and Testing

• IEEE 1532 compliant In-System Programmabil-

ity (ISP™)

■ sysIO™ Interfacing

• Boundary scan test through IEEE 1149.1

interface

• 3.3V, 2.5V or 1.8V power supplies

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL

interfaces

• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for

standard board interfaces

• SSTL 2/3 Class I and II support

• HSTL Class I, III and IV support

• GTL+, PCI-X for bus interfaces

• LVPECL, LVDS and Bus LVDS differential support

• Hot socketing

• Programmable drive strength

Table 1. ispGDX2 Family Selection Guide

ispGDX2-64/E

ispGDX2-128/E

ispGDX2-256/E

I/Os

64

128

256

16

GDX Blocks

4

3.0ns

8

3.2ns

t

f

3.5ns

PD

S

2.0ns

2.9ns

3.1ns

3.2ns

CO

MAX

(Toggle)

360MHz

3.2Gbps

11Gbps

4

330MHz

6.4Gbps

21Gbps

8

300MHz

12.8Gbps

38Gbps

16

SERDES^{1, 2}

Without SERDES³

Max Bandwidth

sysHSI Channels²

LVDS/Bus LVDS (Pairs)

PLLs

32

64

128

2

4

Package

100-ball fpBGA

208-ball fpBGA

484-ball fpBGA

1. Max number of SERDES channels per device * 800Mbps

2. “E-Series” does not support sysHSI.

3. f

(Toggle) * maximum I/Os divided by 2.

MAX

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1

gdx2fam_13

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 1. ispGDX2 Block Diagram (256-I/O Device)

sysIO Bank

sysHSI

Block

sysHSI

Block

SERDES

FIFO

SERDES

FIFO

SERDES

FIFO

sysCLOCK

PLL

sysCLOCK

PLL

FIFO

GDX Block

Global Routing Pool

(GRP)

GDX Block

FIFO

GDX Block

FIFO

GDX Block

FIFO

sysCLOCK

PLL

sysCLOCK

PLL

sysHSI

Block

sysHSI

Block

SERDES

ISP & Boundary Scan

Test Port

sysIO Bank

Introduction

The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for

high speed bus switching and interface applications.

The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial

communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the

sysHSI Block.

This family of switches combines a ﬂexible switching architecture with advanced sysIO interfaces including high

performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through

a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.

The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,

the family supports bandwidth up to 38Gbps.

Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple

clocks and manage clock skews in their systems.

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Lattice Semiconductor

ispGDX2 Family Data Sheet

The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of

LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS

and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-

bility.

Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an

IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-

pendent of the core voltage supply. This further enhances the ﬂexibility of this family in system designs.

Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-

tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of

the ispGDX2 family and their key features.

Architecture

The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface

with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI

Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX

Block can be individually conﬁgured in one of four modes:

• Basic (No FIFO or SERDES)

• FIFO Only

• SERDES Only

• SERDES and FIFO

Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard

within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible

with the reference voltage. The banks are independent.

Global Routing Pool (GRP)

The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-

vative GRP is optimized for routability, ﬂexibility and speed. All the signals enter via the GDX Block. The block sup-

plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and

provides separate data and control routing.The data path is optimized to achieve faster speed and routing ﬂexibility

for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-

nals.

There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by

the software in the allocation of pins.

GDX Block

The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data ﬂow and control logic

for 16 I/O buffers. The data ﬂow is organized as four nibbles, each nibble containing four Multiplexer Register

Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals

going into and out of a GDX Block.

Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from

the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-

put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.

Besides the control signals from the Control Array, the following global signals are available to the MRBs in each

GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in

64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).

3

Lattice Semiconductor

ispGDX2 Family Data Sheet

MUX and Register Block (MRB)

Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,

FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3

shows the structure of the MRB.

Each of the three registers in the MRB can be conﬁgured as edge-triggered D-type ﬂip-ﬂop or as a level sensitive

latch. One register operates on the input data, the other output data and the last register synchronizes the output

enable function. The input and output data signals can bypass each of their registers. The polarity of the data out

and output enable signals can be selected.

The Output and OE register share the same clock and clock enable signals.The Input register has a separate clock

and clock enable.The initialization signals of each register can be independently conﬁgured as Set or Reset.These

registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register

input can be set either by one of the two output enables generated locally from the Control Array or from one of the

four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has

access to Global Clock, Clock Enable, Reset and TOE nets.

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Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 2. GDX Block

GRP

GDX Block

sysIO Bank

MUX

Select

32 bits

4 bits

Control Array

Control

8

Nibble 0

8

OE

IN

MUX and Register

Block (MRB)

0

8

2

OUT

8

OE

IN

MUX and Register

Block (MRB)

1

2

OUT

8

OE

IN

MUX and Register

Block (MRB)

2

4 bits

OUT

8

OE

IN

MUX and Register

Block (MRB)

3

2

4 bits

OUT

8

OE

IN

2

Nibble 1

MRBs 4-7

16 bits

OUT

4

8

OE

IN

2

Nibble 2

MRBs 8-11

16 bits

OUT

4

8

OE

IN

2

Nibble 3

MRBs 12-15

16 bits

OUT

4

The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-

ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-

ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input

register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.

The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be

combined as one shift register via the GRP.

5

Lattice Semiconductor

ispGDX2 Family Data Sheet

The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A

fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX

sizes and delay levels.

Table 2. MUX Size Versus Internal Delay

MUX Sizes

Levels of Internal GRP Delays

One Level

4:1

Up to 16:1

Up to 64:1

Two Levels

Three Levels

Up to 188:1 (with ispGDX2-256)

Four Levels

Figure 3. ispGDX2 Family MRB

Global

Signals

GDX

Control Array

MUX Select

Control Array Signals

2-4

4

2

4

D/L

ClK

Q

OE

MUX

Select

Global

Signals

OE

CK

Reg/Latch

TOE

CE

Set

Reset

Flags*

(FIFO, SERDES

or PLL)

V

CC

from

Out_Reg(n-1)

D/L

From GRP

Q

to Out_Reg(n-1)

to Out_Reg(n+1)

from

Out_Reg(n+1)

ClK

Out

Reg/Latch

CE

Set

Reset

V

CC

S/R

Global Resetb

To GRP

Delay

FIFO Out*

to IN_Reg(n-1)

to IN_Reg(n+1)

from IN_Reg(n-1)

from IN_Reg(n+1)

D/L

Q

CK

ClK

Input

Reg/Latch

CE

Set

Reset

S/R

Global Resetb

*Selected MRBs see Logic Signal Connection Table for details

Control Array

The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms

of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs

to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-

nals. Figure 4 illustrates the control array.

6

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 4. ispGDX2 Family Control Array

32 Inputs from Control GRP

Each connection

is programmable.

MUX Select

to Nibble 0

MUX Select

to Nibble 1

MUX Select

to Nibble 2

MUX Select

to Nibble 3

To MRB Clock/

Clock Enable

On selected blocks,

this signal can reset

the M Divider of the

PLL.

To MRB

Set/Reset

To MRB

Output Enable

sysIO Banks

The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of sup-

porting different I/O standards. The number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices

respectively. Each sysIO bank has its own I/O supply voltage (V

) and reference voltage (V

), allowing each

CCO

REF

bank complete independence from the other banks. Each I/O within a bank can be individually conﬁgured to any

standard consistent with the V and V settings. Figure 5 shows the I/O banks for the ispGDX2-256 device.

CCO

REF

The I/O of the ispGDX2 devices contain a programmable strength and slew rate tri-state output buffer, a program-

mable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-

keeper latch. These programmable capabilities allow the support of a wide range of I/O standards.

7

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 5. ispGDX2-256 sysIO Banks

sysIO Bank 4

sysIO Bank 5

sysIO Bank 3

sysIO Bank 2

V_CCO5

V_CCO2

V_REF2

GND

V_REF5

GND

V_CCO6

V_REF6

GND

V_CCO1

V_REF1

GND

sysIO Bank 6

sysIO Bank 7

sysIO Bank 1

sysIO Bank 0

There are three classes of I/O interface standards implemented in the ispGDX2 devices. The ﬁrst is the non-termi-

nated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS

interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally,

PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the

terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL

interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional V

signal. At the system

REF

level, a termination voltage, V , is also required. Typically, an output will be terminated to V at the receiving end

TT

of the transmission line it is driving. The ﬁnal types of interfaces implemented are the differential standards

LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with

nominal V

, V

and V .

CCO REF TT

The ispGDX2 family also features 5V tolerant I/O. I/O banks with V

= 3.3V may have inputs driven to a maxi-

CCO

mum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.

8

Lattice Semiconductor

ispGDX2 Family Data Sheet

Table 3. ispGDX2 Supported I/O Standards

sysIO Standard

LVCMOS 3.3

Nominal V

3.3V

2.5V

1.8V

3.3V

2.5V

3.3V

2.5V

1.5V

Nominal V

—

Nominal V

—

CCO

REF

TT

LVCMOS 2.5

LVCMOS 1.8

LVTTL

—

PCI 3.3

—

PCI -X

—

AGP-1X

—

SSTL3 class I & II

SSTL2 class I & II

CTT 3.3

1.5V

1.25V

1.5V

1.25V

0.75V

0.9V

1.0V

—

1.5V

1.25V

1.5V

1.25V

0.75V

1.5V

—

CTT 2.5

HSTL class I

HSTL class III

HSTL class IV

GTL+

1.8/2.5/3.3V

3.3V

LVPECL^{1, 2, 3}

LVDS

2.5/3.3V

—

Bus-LVDS

—

1. LVPECL drivers require three resistor pack (see Figure 17).

2. Depending on the driving LVPECL output speciﬁcation, GDX2 LVPECL input driver may require terminating resistors.

3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.

The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated

with a bank consistent with their location.

Table 4. I/O Standards Supported by Dedicated Inputs

LVCMOS

Yes

LVDS

No

All other ASIC I/Os

Global OE Pins

Global MUX Select Pins

Resetb

Yes²

No

Yes

No

Yes

No

Global Clock/Clock Enables

ispJTAG™ Port

TOE

Yes

Yes¹

Yes

No

Yes

No

1. LVCMOS as deﬁned by the V

2. No PCI clamp.

pin voltage.

CCJ

For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design

and Usage Guidelines.

sysCLOCK PLL

The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-

back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and

generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are

deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.

Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide

capabilities of the PLL, each PLL has associated dividers.The M divider is used to divide the clock signal, while the

9

Lattice Semiconductor

ispGDX2 Family Data Sheet

N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adja-

cent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output

clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay fea-

ture that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better per-

formance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL

Design and Usage Guidelines.

Figure 6. sysCLOCK PLL

PLL_LOCK

CLK_OUT

CLK_IN

Input Clock

Programmable

(M) Divider

+Delay

Post-scalar

(V) Divider

1 to 32

--------------------

PLL (n)

Clock Net

1, 2, 4, 8,

16, 32

Programmable

-Delay

PLL_RST

Clock (K)

Divider

2, 4, 8,

16, 32

To Adjacent_PLL

From

Adjacent_PLL

Feedback

Divider (N)

X 1 to 32

PLL_FBK

There are four global clock networks routed to each MRB block. These global clocks, CLK0-3, can either be gener-

ated by the PLL circuits or supplied externally. External clock pins can be conﬁgured as single-ended or differential

(LVDS) input. Figure 7 illustrates how the sysCLOCK PLL inputs and outputs can be routed to the I/O pins or gen-

eral routing. Figure 10 shows the clock network for the ispGDX2-256 and Figure 8 shows the clock networks for

ispGDX2-128 and ispGDX2-64. The Reset (0) pin from the Control Array of selected GDX Blocks can be pro-

grammed to reset the M Divider of the PLLs. This provides a means for generating the reset signal internally.

Table 5 details which GDX Block provides reset to the PLLs.

Table 5. Internal Reset Input of the PLL (M Divider)

PLL0

PLL1

PLL2

PLL3

ispGDX2-256

ispGDX2-128

ispGDX2-64

GDX Block 5A

GDX Block 2A

GDX Block 0A

GDX Block 7B

GDX Block 1A

GDX Block 0A

GDX Block 1B

GDX Block 3B

—

10

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 7. I/O Pin Connection to the sysCLOCK PLL¹

PLL_LOCK

CLK_OUT

Output

Reg/

Latch

Input Clock

(M) Divider

÷ 1 to 32

Programmable

+ Delay

GCLK_IN

Post-scalar

(V) Divider

÷

--------------------

PLL (n)

Clock Net

1, 2, 4, 8,

16, 32

Programmable

- Delay

Clock

(K) Divider

÷

2, 4, 8,

16, 32

To Adjacent_PLL

Delay

Input

Reg/

Latch

From Adjacent_PLL

Feedback

Divider (N)

x 1 to 32

GRP

GDX Block

PLL_FBK

PLL_RST

Resetb (0)

Control Array

(from selected blocks)

GCLK_IN

1. Some pins are shared. See Logic Signal Connections Table for details.

11

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 8. ispGDX2-64 CLOCK Network

Clock Net

MRB

sysIO Interface

sysCLOCK

CLK0

K(0)

PLL

(0)

Reg/

GCLK/CE0

+

Clock Net

Latch

VREF0

-

CLK_OUT0

Reg/

Clock Net

Latch

GCLK/CE1

+

-

VREF1

CLK_OUT2

CLK2

K(2)

PLL

(2)

Reg/

GCLK/CE2

+

Clock Net

Latch

VREF2

-

Reg/

Clock Net

Latch

GCLK/CE3

+

-

VREF3

Figure 9. ispGDX2-128 CLOCK Network

Clock Net

MRB

sysIO Interface

sysCLOCK

CLK0

K(0)

PLL

(0)

Reg/

GCLK/CE0

+

Clock Net

Latch

VREF0

-

CLK_OUT0

Reg/

Clock Net

Latch

GCLK/CE1

+

-

VREF1

CLK_OUT2

CLK2

K(2)

PLL

(2)

Reg/

GCLK/CE2

+

Clock Net

Latch

-

VREF2

Reg/

Clock Net

Latch

GCLK/CE3

+

-

VREF3

12

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 10. ispGDX2-256 CLOCK Network

MRB

sysIO Interface

sysCLOCK

Clock Net

CLK0

K(0)

PLL

(0)

Reg/

GCLK/CE0

+

Clock Net

Latch

VREF0

-

CLK_OUT0

CLK1

CLK2

CLK3

K(1)

PLL

(1)

Reg/

GCLK/CE1

+

Clock Net

Latch

-

VREF1

CLK_OUT1

K(2)

PLL

(2)

Reg/

Latch

GCLK/CE2

+

Clock Net

VREF2

-

CLK_OUT2

K(3)

PLL

(3)

Reg/

Latch

GCLK/CE3

+

Clock Net

-

VREF3

CLK_OUT3

13

Lattice Semiconductor

ispGDX2 Family Data Sheet

Operating Modes

All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and

FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB

connects to the output register. Inputs are connected to the GRP via the MRB.

Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERDES connections is pro-

vided in their respective sections.

Figure 11. Four Operating Modes of ispGDX2 Devices

Basic

Mode

FIFO

sysIO

Bank

GDX

Block

GRP

SERDES

FIFO

Mode

FIFO

sysIO

Bank

GDX

Block

SERDES

Mode

(FIFO in

Flow-through

Mode)

FIFO*

sysIO

Bank

GDX

Block

SERDES

and

FIFO Mode

FIFO

sysIO

Bank

GDX

Block

GRP

SERDES

*FIFO held in RESET for SERDES-only mode.

FIFO Operations

Each GDX Block is associated with a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two

address counters and two comparators, is used to implement a FIFO as a “circular queue”. The FIFO has separate

clocks, the Read Clock (RCLK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three addi-

tional control signals Write Enable, Read Enable and FIFO Reset. Three ﬂags show the status of the FIFO: Empty,

Full and Start Read. Each FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the con-

nections to the FIFO.

14

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 12. ispGDX2 FIFO Signals

10

Data Out (DOUT)

Data In (DIN)

Write Clock (WCLK)

Write Enable (WE)

Read Clock (RCLK)

Read Enable (RE)

FIFO

10x15

Full (FULL)

Empty (EMPTY)

Start Read (STRDb)

Global Reset (RESETb)

Power-on Reset (PORb)

FIFO Reset (FIFORSTb)

Read Clock and Read Enable are the same as the Clock and Clock Enable signals of the input registers of the

associated MRB.These registers are used to register the FIFO outputs, and in modes that utilize the FIFO are con-

ﬁgured to use the same clock and clock enable signals. The Write Clock is selected from one of the GCLK/CE sig-

nals or the RECCLK (Recovered Clock) signal from the associated SERDES. The Write Enable is selected from

one of the local MRB product term CLK/CE signals. All FIFO operations occur on the rising edge of the clock

although clock polarity of these signals can be programmed.

The ﬂags from the FIFO, FULL, EMPTY and STRDb (Start Read) are each fed via a MUX in the MRB to an I/O

buffer. The STRDb (half full) signal is used in conjunction with SERDES. STRDb is an active low signal, the signal

is inactive (high) on FIFO RESET. After the FIFO reset when the FIFO contains data in ﬁve memory locations, at

the following write clock transition the STRDb becomes active (low). Note, if the Read Clocks arrive before writing

the sixth location, it may take longer than ﬁve write clocks before the STRDb becomes active. When the FIFO has

data in the ﬁrst six locations, at the next write clock transition the STRDb becomes inactive (high). Again, if the

Read Clocks arrive before writing the seventh location, the STRDb may stay active for longer than one write clock

period, even if the FIFO contains data in less than ﬁve locations. After this event, the STRDb stays inactive until the

FIFO is RESET again. STRDb does not become active again even if less than six memory locations are occupied

in the FIFO. It is the user’s responsibility to monitor the FULL and EMPTY signals to avoid data underﬂow/overﬂow

and to take appropriate actions.

Figure 13 shows how the FIFO is connected between the I/O banks and the GDX Blocks in FIFO mode. For more

information on the FIFO, please refer to Lattice technical note number TN1020, sysHSI Usage Guidelines.

15

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 13. Operation in FIFO Mode²

GDX Block ¹

SERDES

Pre-Assigned Pins

GRP

FIFO

10

Delay

Input

Reg/

10

DIN

RXD

Parallel

Data

DOUT

Serial

Data In

(SIN)

Latch

RCLK

RE

TXD Serial

Parallel Data Out

Data (SOUT)

10

Output

Reg/

Latch

PT-CLK/CE(0:3)

WE

GCLK/CE(0:3)

RECCLK

Input

Reg/

Latch

CAL

WCLK

Input

Reg/

Latch

SYDT

Output

Reg/

Latch

FULL

EMPTY

Output

Reg/

Latch

CDRRSTb

FIFORSTb

Notes:

POR

RESETb

1. For clarity, only a portion of the GDX Block is shown.

2. Some signals share pins. See Logic Signal Connections tables for details.

16

Lattice Semiconductor

ispGDX2 Family Data Sheet

High Speed Serial Interface Block (sysHSI Block)¹

The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The

ispGDX2 devices have multiple sysHSI Blocks.

Each sysHSI Block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and

Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full

duplex channel. The two SERDES in a given sysHSI Block share a common clock and must operate at the same

nominal frequency. Figure 14 shows the sysHSI Block.

Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see

Lattice’s sysHSI application notes). The encoding and decoding of the 10B/12B standard are performed within the

device in dedicated logic. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding

and decoding are performed outside the device.

Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,

and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, the SER-

DES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for

output.

Additionally, multiple sysHSI Blocks can be grouped together to form a source synchronous interface of between 1-

8 channels.

Figure 15 shows the connections of the SERDES block with the FIFO, sysIO block and the MRB. Table 6 provides

the descriptions of the SERDES.

For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guide-

lines.

Table 6. SERDES Signal Descriptions

Signal

CDRRSTb

SYDT

I/O

Description

Resets the CDR circuit of sysHSI block

I

O

Symbol alignment detect for sysHSI block

Initiates source synchronous calibration sequence

Parallel data in for sysHSI block

CAL

I

RXD

Internal

I

TXD

Parallel data out for sysHSI block

REFCLK

SIN

Reference clock received from the clock tree

Serial data input for sysHSI block (LVDS input)

Serial data output for sysHSI block (LVDS output)

Clock input for source synchronous group

Clock output for source synchronous group

Recovered clock from encoded data by CDR of sysHSI block

Lock output of the PLL associated with sysHSI block

SOUT

O

SS_CLKIN

SS_CLKOUT

RECCLK

CSLOCK

I

O

Internal

1. “E-Series” does not support sysHSI.

17

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 14. sysHSI Block with SERDES and FIFO

sysHSI Block

Core Logic

SERDES

10

SOUT

TXD

Serializer

RXD

SIN

De-serializer

including CDR

FIFO

RECCLK

GDX

Block

CSLOCK

SS_CLKOUT

CSPLL

SS_CLKIN

CAL

GRP

Shared Source Synchronous

pins drive multiple sysHSI

blocks

SERDES

Serializer

10

SOUT

SIN

TXD

RXD

De-serializer

including CDR

FIFO

RECCLK

GDX

Block

REFCLK (0:3)

Reference clocks

from CLK (0:3)

Note: Some pins are shared. See Logic Signal Connections table for details

18

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 15. Operation in SERDES Only Mode^{1, 2}

GRP

GDX Block

SERDES

Pre-Assigned Pins

FIFO

10

Delay

Input

Reg/

DIN

RXD

Parallel

Data

DOUT

Serial

Data In

(SIN)

Latch

RCLK

RE

TXD Serial

Parallel Data Out

Data (SOUT)

10

Output

Reg/

Latch

PT-CLK/CE(0:3)

WE

GCLK/CE(0:3)

RECCLK

Input

Reg/

Latch

CAL

WCLK

Input

Reg/

Latch

SYDT

Output

Reg/

Latch

FULL

EMPTY

Output

Reg/

Latch

CDRRSTb

FIFORSTb

Notes:

POR

RESETb

1. Some pins shared. See Logic Signal

Connections table for details.

2. For SERDES only mode programmable bit

holds FIFO in reset. Input registers used for

DOUT, and RECCLK configured as

latches and held in pass through.

19

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 16. Operation in SERDES with FIFO Mode

GRP

GDX Block

SERDES

FIFO

Pre-Assigned Pins

10

Delay

Input

Reg/

DIN

RXD

Parallel

Data

DOUT

Serial

Data In

(SIN)

Latch

RCLK

RE

TXD Serial

Parallel Data Out

Data (SOUT)

10

Output

Reg/

Latch

PT-CLK/CE(0:3)

WE

GCLK/CE(0:3)

RECCLK

Input

Reg/

Latch

CAL

WCLK

Input

Reg/

Latch

SYDT

Output

Reg/

Latch

FULL

EMPTY

Output

Reg/

Latch

CDRRSTb

FIFORSTb

POR

RESETb

20

Lattice Semiconductor

ispGDX2 Family Data Sheet

IEEE 1149.1-Compliant Boundary Scan Testability

All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows func-

tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit-

ical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port has its own supply voltage that

can operate with LVCMOS3.3, 2.5 and 1.8 standards.

sysIO Quick Conﬁguration

To facilitate the most efﬁcient board test, the physical nature of the I/O cells must be set before running any continu-

ity tests. As these tests are fast, by nature, the overhead and time that is required for conﬁguration of the I/Os'

physical nature should be minimal so that board test time is minimized. The ispGDX2 family of devices allows this

by offering the user the ability to quickly conﬁgure the physical nature of the sysIO cells. This quick conﬁguration

takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's

ispVM™ System programming software can either perform the quick conﬁguration through the PC parallel port, or

can generate the ATE or test vectors necessary for a third-party test system.

IEEE 1532-Compliant In-System Programming

In-system programming of devices provides a number of signiﬁcant beneﬁts including rapid prototyping, lower

inventory levels, higher quality and the ability to make in-ﬁeld modiﬁcations. All ispGDX2 devices provide In-System

Programming (ISP) capability through their Boundary Scan Test Access Port. This capability has been imple-

mented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532

as the communication interface through which ISP is achieved, designers get the beneﬁt of a standard, well deﬁned

interface.

The ispGDX2 devices can be programmed across the commercial temperature and voltage range. The PC-based

Lattice software facilitates in-system programming of ispGDX2 devices. The software takes the JEDEC ﬁle output

produced by the design implementation software, along with information about the scan chain, and creates a set of

vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port

of a PC. Alternatively, the software can output ﬁles in formats understood by common automated test equipment.

This equipment can then be used to program ispGDX2 devices during the testing of a circuit board.

Security Scheme

A programmable security scheme is provided on the ispGDX2 devices as a deterrent to unauthorized copying of

the array conﬁguration patterns. Once programmed, this scheme prevents readback of the programmed pattern by

a device programmer, securing proprietary designs from competitors. The security scheme also prevents program-

ming and veriﬁcation. The entire device must be erased in order to reset the security scheme.

Hot Socketing

The ispGDX2 devices are well suited for those applications that require hot socketing capability. Hot socketing a

device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without

being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals.

21

Lattice Semiconductor

ispGDX2 Family Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

ispGDX2C (1.8V)

ispGDX2B/V (2.5/3.3V)

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V

CC

PLL Supply Voltage V

. . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V

CCP

Output Supply Voltage V

. . . . . . . . . . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . -0.5 to 4.5V

CCO

JTAG Supply Voltage (V

) . . . . . . . . . . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . -0.5 to 4.5V

CCJ

Input or I/O Tristate Voltage Applied ^{4, 5}. . . . . . . . . -0.5 to 5.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C

Junction Temp. (T ) with Power Applied . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C

J

1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied (while program-

ming, following the programming speciﬁcations).

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V (MAX)+2) volts is permitted for a duration of <20ns.

IH

5. A maximum of 64 I/Os per device with V > 3.6V is allowed.

IN

Recommended Operating Conditions

Symbol

Parameter

Supply Voltage for 1.8V Devices¹

Min.

1.65

2.3

3

Max.

1.95

2.7

Units

V

Supply Voltage for 2.5V Devices

V

CC

Supply Voltage for 3.3V Devices

3.6

V

Supply Voltage for PLL and sysHSI Blocks, 1.8V Devices¹

Supply Voltage for PLL and sysHSI Blocks, 2.5V Devices

Supply Voltage for PLL and sysHSI Blocks, 3.3V Devices

Power Supply Voltage for JTAG Programming 1.8V Operation

Power Supply Voltage for JTAG Programming 2.5V Operation

Power Supply Voltage for JTAG Programming 3.3V Operation

Junction Commercial Operation

1.65

2.3

3

1.95

2.7

V

CCP

CCJ

3.6

V

1.65

2.3

3

1.95

2.7

V

3.6

V

T (COM)

0

90

°C

J

T (IND)

Junction Industrial Operation

-40

105

J

1. sysHSI speciﬁcation is valid for V and V

= 1.7V to 1.9V.

CCP

CC

Erase Reprogram Speciﬁcations

Parameter

Min

Max

Units

Erase/Reprogram Cycle

1,000

—

Cycles

Note: Valid over commercial temperature range.

Hot Socketing Speciﬁcations^{1, 2, 3}

Symbol

Parameter

Condition

Min

Typ

Max

Units

4

I

Input or Tristated I/O Leakage Current 0 ≤ V ≤ 3.0V

—

+/-50

+/-800

μA

DK

IN

1. Insensitive to sequence of V and V

. However, assumes monotonic rise/fall rates for V and V

provided (V - V

) ≤ 3.6V.

CCO

CC

CCO

CC

CCO,

IN

2. LVTTL, LVCMOS only.

3. 0 < V ≤ V (MAX), 0 < V

≤ V

(MAX).

CCO

CC

CCO

4. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.

DK

PU PD

BH

22

Lattice Semiconductor

ispGDX2 Family Data Sheet

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

0 ≤ V ≤ (V - 0.2V)

Min.

—

Typ.

—

Max.

10

Units

μA

IN

CCO

1

I , I

Input or I/O Low Leakage

IL IH

(V

- 0.2V) < V ≤ 3.6V

—

30

μA

CCO

IN

3.6V < V ≤ 5.5V and

3

IN

I

Input High Leakage Current

—

3

mA

IH

3.0V ≤ V

≤ 3.6V

CCO

I

I/O Active Pull-up Current

0 ≤ V ≤ 0.7 V

CCO

-30

30

-30

—

-150

150

—

μA

V

PU

IN

I/O Active Pull-down Current

V (MAX) ≤ V ≤ V (MAX)

IL IN IH

PD

Bus Hold Low Sustaining Current V = V (MAX)

BHLS

BHHS

BHLO

BHLH

IN

IL

Bus Hold High Sustaining Current V = 0.7 V

—

IN

CCO

Bus Hold Low Overdrive Current 0 ≤ V ≤ V (MAX)

150

-150

IN

IH

Bus Hold High Overdrive Current 0 ≤ V ≤ V (MAX)

—

IN

IH

V

Bus Hold Trip Points

I/O Capacitance²

V

* 0.35

V

* 0.65

BHT

CCO

V

= 3.3V, 2.5V, 1.8V

—

CCO

C

8

6

pf

1

2

3

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

Clock Capacitance²

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

Global Input Capacitance²

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. T = 25°C, f = 1.0MHz.

A

3. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ V

≤ 3.6V. The JTAG ports are not included for the 5V tolerant inter-

CCO

face.

Supply Current

Over Recommended Operating Conditions (ispGDX2-256)⁴

Symbol

Description

Power Pins

Vcc (V)

3.3

2.5

1.8

3.3

2.5

1.8

3.3

2.5

1.8

3.3

2.5

1.8

3.3

2.5

1.8

Min.

—

Typ.

59.6

58.7

60.0

118.7

117.5

14.7

17.4

35

Max.

—

Units

mA

µA

Core Logic Power Supply Current

1,2

I

V

CC

GPLL/sysHSI Logic Power Supply

Current

GPLL/sysHSI CSPLL Power

Supply Current

2

I

V

CCP

3

Bank Power Supply Current

JTAG Programming Current

V

35

CCO

25

1.5

V

1.0

CCJ

800

1. 64-input switching frequency at 20 MHz, with one GRP fanout.

2. One GPLL with f = 400 MHz and one sysHSI Block (two receivers and two transmitters) at 622 MHz data rate.

VCO

3. All 8-bank reference circuit currents, all I/Os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled.

4. T = 25°C

A

23

Lattice Semiconductor

ispGDX2 Family Data Sheet

sysIO Recommended Operating Conditions

V

(V)¹

V

(V)

REF

CCO

Standard

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8²

LVTTL

Min.

3.0

2.3

1.65

3.0

3.15

2.3

3.0

2.3

1.4

3.0

2.3

Typ.

Max.

3.6

2.7

1.95

3.6

3.45

2.7

3.6

2.7

1.6

3.6

Min.

Typ.

Max.

3.3

2.5

-

1.8

-

3.3

-

PCI 3.3

3.3

-

PCI-X

3.3

-

AGP-1X

3.3

-

SSTL 2

2.5

1.15

1.25

1.5

0.75

0.9

1.0

-

1.35

SSTL 3

3.3

1.3

1.7

CTT 3.3

3.3

1.35

1.65

CTT 2.5

2.5

1.35

1.65

HSTL Class I

HSTL Class III

HSTL Class IV

GTL+

1.5

0.68

0.9

1.5

-

1.5

-

0.882

1.122

LVPECL

3.3

-

LVDS

2.5/3.3

-

BLVDS

-

1. Inputs are independent of V

2. Software default setting.

setting. However, V

must be set within the valid operating range for one of the supported standards.

CCO

24

Lattice Semiconductor

ispGDX2 Family Data Sheet

sysIO Single Ended DC Electrical Characteristics

Over Recommended Operating Conditions

V

IH

2

IL

Input/Output

Standard

V

I

OH

OL

OH

OL

Min (V)

Max (V)

Min (V)

Max (V)

Min (V)

(mA)

20, 16, 12, -20, -16, -12,

8, 5.33, 4 -8, -5.33, -4

0.4

2.4

LVCMOS 3.3

LVTTL

-0.3

0.8

2.0

5.5

0.2

0.4

0.2

V

- 0.2

0.1

4

-0.1

-4

CCO

2.4

-0.3

0.8

0.7

2.0

1.7

5.5

3.6

V

- 0.2

0.1

-0.1

CCO

16, 12, 8, -16, -12, -8,

0.4

- 0.4

CCO

5.33, 4

-5.33, -4

LVCMOS 2.5

0.2

0.4

0.2

V

- 0.2

- 0.4

0.1

-0.1

CCO

LVCMOS 1.8^{1, 3}

LVCMOS 1.8³

-0.3

0.68

1.07

3.6

8

-8

CCO

V

-0.4 12, 5.33, 4 -12, -5.33, -4

CCO

V

- 0.2

0.1

1.5

8

-0.1

-0.5

-8

PCI 3.3⁴

PCI -X⁵

AGP-1X⁴

-0.3

1.08

1.26

1.08

1.5

3.6

0.1 V

0.9 V

CCO

0.1 V

CCO

0.1 V

CCO

SSTL3 class I

SSTL3 class II

SSTL2 class I

SSTL2 class II

CTT 3.3

V

- 0.2

V

+ 0.2

0.7

0.5

V

- 1.1

REF

CCO

+ 0.2

V

- 0.9

- 0.62

- 0.43

+ 0.4

- 0.4

16

7.6

15.2

8

-16

-7.6

-15.2

-8

V

- 0.18 V

+ 0.18

+ 0.2

+ 0.1

+ 0.2

0.54

0.35

V

REF

CCO

V

- 0.2

- 0.3

- 0.1

- 0.2

- 0.3

- 0.2

V

- 0.4

V

REF

CTT 2.5

V

8

-8

REF

HSTL class I

HSTL class III

HSTL class IV

GTL+

V

0.4

V

8

-8

CCO

0.4

0.6

- 0.4

24

48

36

-8

- 0.4

-8

n/a

1. Software default setting.

2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of

the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND

connections or between the last GND in a bank and the end of a bank.

3. For 1.8V devices (ispGDX2C) these speciﬁcations are V = 0.35 V and V = 0.65V

IL

CC

IH

CC

4. For 1.8V power supply devices these speciﬁcations are V = 0.3 * V * 3.3/1.8, V = 0.5 * V * 3.3/1.8

IL

CC

IH

CC

5. For 1.8V power supply devices these speciﬁcations are V = 0.35 * V * 3.3/1.8 and V = 0.5 * V * 3.3/1.8

IL

CC

IH

CC

25

Lattice Semiconductor

ispGDX2 Family Data Sheet

sysIO Differential DC Electrical Characteristics

Over Recommended Operating Conditions

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Typ.

Max.

Units

LVDS

V

Input Voltage

—

0

+/-100

—

2.4

—

V

mV

µA

V

INP INM

Differential Input Threshold

Input Current

0.2V ≤ V

≤ 1.8V

THD

CM

I

Power On

R = 100Ω

—

+/-10

1.60

—

IN

V

Output High Voltage for V or V

—

1.38

1.03

350

—

OH

OL

OD

OP

OM

T

Output Low Voltage for V or V

R = 100Ω

0.9

V

OP

OM

T

Output Voltage Differential

(V - V ), R = 100Ω

250

—

450

50

mV

V

OP

OM

T

ΔV

Change in V Between High and Low —

OD

V

Output Voltage Offset

(V - V )/2, R = 100Ω

1.125

—

1.25

—

1.375

50

OS

OP

OM

T

ΔV

Change in VOS Between H and L

Output Short Circuit Current

—

mV

OS

I

V

= 0V. Driver Outputs

OSD

OD

—

24

mA

Shorted.

Bus LVDS¹

V

Output High Voltage for V or V

R = 27Ω

—

0.95

240

—

1.4

1.1

300

—

1.80

—

V

OH

OL

OD

OP

OM

T

Output Low Voltage for V or V

R = 27Ω

T

OP

OM

Output Voltage Differential

|V - V |, RT = 27Ω

460

27

mV

V

OP

OM

ΔV

Change in V Between H and L

OD

V

Output Voltage Offset

|V - VOM| /2, RT = 27Ω

1.1

—

1.3

—

1.5

27

OS

OP

ΔV

Change in V Between H and L

mV

OS

I

Output Short Circuit Current

V

= 0. Driver Outputs

OSD

OD

—

36

65

mA

Shorted.

1. V and V

are the two outputs of the LVDS output buffer.

OP

OM

1

LVPECL

DC Parameter

Parameter Description

Output Supply Voltage

Input Voltage High

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

3.0

3.3

3.6

V

CCO

IH

1.49

0.86

1.7

2.72

2.125

2.11

1.49

0.86

1.92

1.06

0.3

2.72

2.125

2.28

1.49

0.86

2.03

1.25

0.3

2.72

2.125

2.41

Input Voltage Low

IL

Output Voltage High

Output Voltage Low

Differential Input voltage

OH

OL

0.96

0.3

1.27

1.43

1.57

2

DIFF

1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 17).

The V levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.

OH

2. Valid for 0.2V ≤ V

≤ 1.8V.

CM

Figure 17. LVPECL Driver with Three Resistor Pack

1/4 of Bourns P/N

ispGDX2

CAT 16-PC4F12

LVPECL Buffer

A

Zo

Rs

to LVPECL

differential

receiver

Rs

26

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics

Over Recommended Operating Conditions

-3

-32

-35

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Output Paths

t

Data From Input Pin to Output Pin

Data From Global Select Pin to Output Pin

Global Clock to Output

—

3.0

2.8

2.9

—

3.2

3.0

3.1

—

3.5

3.3

3.2

—

5.0

4.7

5.4

—

ns

PD

PD_SEL

CO

—

Set-up Time Before Global Clock

Hold Time After Global Clock

2.0

0.0

2.0

0.0

2.0

0.0

3.0

0.0

OPS

OPH

—

PT Clock Enable Setup Time Before

Global Clock

t

3.0

—

3.0

—

4.1

—

6.9

—

ns

OPCES

PT Clock Enable Hold Time After

Global Clock

t

0.0

—

0.0

—

0.0

—

0.0

—

ns

OPCEH

External Reset Pin to Output Delay

5.3

6.0

10.0

OPRSTO

Input Paths

t

Set-up Time Before Global Clock

0.5

2.0

1.0

0.0

—

0.5

2.0

1.0

0.0

—

0.5

2.0

1.0

0.0

—

0.9

3.0

1.7

0.0

—

ns

IPS

Set-up Time Before Global Clock

(Zero Hold Time)

IPSZ

IPH

Hold Time After Global Clock

(Zero Hold Time)

IPHZ

PT Clock Enable Setup Time Before

Global Clock

t

3.1

—

3.1

—

3.1

—

5.1

—

ns

IPCES

PT Clock Enable Hold Time After Global

Clock

t

0.0

—

0.0

—

0.0

—

0.0

—

ns

IPCEH

External Reset Pin to Output Delay

5.6

6.5

7.5

12.5

IPRSTO

Output Enable Paths

t

Global Clock to Output Enabled Pin

—

4.2

—

4.5

—

5.5

—

9.1

—

ns

OECO

Output Enable Register Set-up Time

Before Global Clock

1.6

0.0

3.5

1.6

0.0

3.5

2.0

0.0

4.1

3.4

0.0

6.9

OES

Hold Time After Global Clock

OEH

PT Clock Enable Setup Time Before

Global Clock

OECES

PT Clock Enable Hold Time After Global

Clock

t

0.0

—

0.0

—

0.0

—

0.0

—

ns

OECEH

t

Global OE Input to Output Enable/Disable

Test OE Input to Output Enable/Disable

Input to Output Enable/Disable

—

3.5

5.2

—

3.8

5.5

—

4.5

6.2

—

7.5

ns

GOE/DIS

TOE/DIS

EN/DIS

10.3

Clock and Reset Paths

t

Width of Reset Pulse

Clock Width

2.5

1.3

1.5

—

2.5

1.5

1.6

—

2.5

1.6

—

4.1

2.7

—

ns

RW

CW

GW

Clock Width

Clock Frequency with External

f

(Ext)

—

204

360

—

196

330

—

192

300

—

119 MHz

180 MHz

MAX

Feedback 1/(t

+ t

)

OPS

CO

f

(Tog, Clock Frequency Maximum Toggle

(No PLL)

MAX

No PLL)

27

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics

Over Recommended Operating Conditions

-3

-32

-35

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

f

Clock Frequency Maximum Toggle

MAX

—

360

—

330

—

300

—

180 MHz

(Tog, PLL) (With PLL)

Timing v.2.2

28

Lattice Semiconductor

ispGDX2 Family Data Sheet

Timing Model

The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in

Figure 18 shows the speciﬁc delay paths. Once the implementation of a given function is determined either con-

ceptually or from the software report ﬁle, the delay path of the function can easily be determined from the timing

model. The Lattice design tools report the timing delays based on the same timing model for a particular design.

Note that the internal timing parameters are given for reference only, and are not tested.The external timing param-

eters are tested and guaranteed for every device.

Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)

TOE path

t_{TOE_IN}

TOE/

GOE

t_{GOE_IN}

t _IOI

GOE path

t_PTOE

from GRP

to FIFO

(WE)

to sysHSI

(REFCLK)

t_GCLK

t_PTCLKEN

t_{CLK_IN}

t_{CLKEN_IN}

t_IOI

t _OEBYPASS

GCLK/

GCLKEN

from GRP

t_{PLL_DELAY}

t_{PLL_SEC_DELAY}

t_PTCLK

OE Reg.

D

Q

to sysHSI/FIFO

(Global Reset)

to FIFO

(WCLK)

CE

t _{SR_IN}

GSR

from sysHSI

(SOUT)

t_IOI

t _HSISOUT

S/R

from GRP

t_PTSR

from sysHSI/FIFO

(Flags)

t _HSIFIFOFLAG

Output

Delays

t_{SEL_IN}

t_IOI

from sysHSI

(SSCLKOUT)

t_HSISSCLKOUT

GSEL

t_BUF

t_EN

t_DIS

t _IOO

from Adjacent

Cells (Output)

t_OPBYPASS

OUT

t_PTSEL

Output Reg.

Q

t _OPAC

D

t_MUXPD

t_MUXSEL

from GRP

CE

to sysHSI

(TXD)

S/R

from Adjacent Cells

(Input)

t _IPAC

from FIFO

(DOUT)

t _FIFODATAOUT

to Adjacent Cells

(Output)

from sysHSI

(RECCLK, SYDT)

Input Reg.

t _HSIOUT

S/R

CE

from PLL

(PLL Output)

t _PLLOUT

t _IN

t _IOI

D

Q

IN

t _ROUTEGRP

to GRP

t_INDIO

t_IPBYPASS

to sysHSI/FIFO

(SIN, Control, DIN, I/O Reset, SSCLKIN)

to Adjacent Cells

(Input)

to FIFO

(REN)

Italicized parameters are optional.

Model Version 1.6.7

to FIFO

(RCLK)

29

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)

to I/O Cell

(RECCLK)

sysHSI

(RXD)

FIFO

Serial Data

In

Data Out

(RXD)

from I/O Cell

(SIN)

t_FIFODATAIN

Data In

t_HSISIN

Recovered

Clock

Write CLK

t_FIFOWCLK

to I/O Cell

(DOUT)

HSI Controls

CAL

Data Out

HSI Flags

CSLOCK

to I/O Cell

(Output Path Flag)

from I/O Cell

(Control)

t_HSICTRLCAL

FIFO Flags

to I/O Cell

(SYDT and Output

Path Flags)

SYDT

to I/O Cell

(Output Path Flags)

FULL, EMPTY

Source

Synchronous Clock

from I/O Cell

(SSCLKIN)

t_HSISSCLKIN

Read

Clock

from I/O Cell

(RCLK)

t_FIFORCLK

from I/O Cell

(REFCLK)

Reference Clock

t_HSIREFCLK

Read

Enable

from I/O Cell

(RE)

t_FIFOREN

RESET

from I/O Cell

(Global RESET)

t_HSIFIFORST

from I/O Cell

(I/O RESET)

Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)

sysHSI

(TXD)

Serial

Data Out

to I/O Cell

(SOUT)

from I/O Cell

(TXD)

Data In

t_HSITXDATA

from I/O Cell

(REFCLK)

Reference Clock

t_HSIREFCLK

Source

to I/O Cell

Synchronous Clock

(SSCLKOUT)

30

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 21. ispGDX2 Timing Model Diagram (in FIFO Only Mode)

from I/O Cell

(DIN)

t_FIFODATAIN

t_FIFOWCLK

t_FIFOWEN

Data In

FIFO

to I/O Cell

(DOUT)

Data Out

from I/O Cell

(WCLK)

Write

Clock

from I/O Cell

(WE)

Write

Enable

FIFO Flags

to I/O Cell

(Output Path Flags)

FULL, EMPTY

Read

Clock

from I/O Cell

(RCLK)

t_FIFORCLK

Read

Enable

from I/O Cell

(RE)

t_FIFOREN

RESET

from I/O Cell

(Global RESET)

t_HSIFIFORST

from I/O Cell

(I/O RESET)

31

Lattice Semiconductor

ispGDX2 Family Data Sheet

Sample External Timing Calculations

The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a

sample of equations to calculate the timing through the ispGDX2.

Figure 18 shows the speciﬁc delay paths and the Internal Timing Parameters table provides the parameter values.

Note that the internal timing parameters are given for reference only and are not tested. The external timing param-

eters are tested and guaranteed for every device.

Data from global select pin to output pin:

t

= t

+ t

PD_SEL

SEL_IN

MUXSEL

OPBYPASS BUF

Global clock to output:

= t + t + t

t

+ t

BUF

CO

CLK_IN

GCLK

OPCOi

Input register or latch set-up time before global clock:

= t + t - (t + t

t

)

GCLK

IPS

IN

IPS

CLK

Input register or latch hold time after global clock:

= (t + t ) + t - t

t

IPH

CLK_IN

GCLK

IPHi IN

Data from product term select to output pin:

t

= t + t

+ t

PD_PTSEL

IN

IPBYPASS

ROUTEGRP

PTSEL

MUXSEL

OPBYPASS BUF

Product term clock to output:

= t + t + t

t

+ t

CO_PT

IN

IPBYPASS

ROUTEGRP

PTCLK

OPCOi BUF

Input register or latch set-up time before product term clock:

= t + t - (t + t + t + t )

PTCLK

t

IPS_PT

IN

IPSi_PT

IN

IPBYPASS

ROUTEGRP

Input register or latch hold time after product term clock:

t

= (t + t

+ t

) + t

- t

IPH_PT

IN

IPBYPASS

ROUTEGRP

PTCLK

IPHi IN

Global OE input to output enable/disable:

= t + t + t

t

GOE/DIS

GOE_IN

OEBYPASS

EN

External reset pin to output delay:

= t + t + t

BUF

t

OPRSTO

SR_IN

OPASROi

32

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters¹

Over Recommended Operating Conditions

-3

-32

-35

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Input/Output Delays

t

Output Buffer Delay

—

0.80

1.00

1.80

1.50

2.00

0.40

1.60

2.00

3.70

—

0.80

1.00

1.80

2.00

0.40

1.60

2.70

3.70

—

0.80

1.00

1.80

2.50

2.00

0.40

1.60

2.70

3.70

—

1.14

1.67

3.00

4.17

3.33

0.57

2.29

4.50

6.17

ns

BUF

Global Clock Input Delay

Global Clock Enable Input Delay

Output Disable Delay

CLK_IN

CLKEN_IN

DIS

Output Enable Delay

EN

Global Output Enable Path Delay

Input Pin Delay

GOE_IN

IN

Global MUX Select Input Delay

Global Set/Reset Path Delay

Test Output Enable Path Delay

SEL_IN

SR_IN

TOE_IN

Shift Register and MUX Delays

Input Path Adjacent I/O Cell Delay

(Shift Register)

t

—

0.80

1.30

—

0.80

1.30

—

0.80

1.30

—

1.33

2.17

ns

IPAC

Output Path Adjacent I/O Cell Delay

(Shift Register)

OPAC

t

MUX Data Path Delay

MUX Select Path Delay

—

0.90

0.40

—

0.90

0.40

—

0.90

0.40

—

1.29

0.57

ns

MUXPD

MUXSEL

AND Arrays and Routing Delays

t

FIFO Output to I/O Block Delay

Clock Tree Delay

—

0.00

0.40

0.00

—

0.00

0.40

0.00

—

0.00

0.40

0.00

—

0.00

0.67

0.00

ns

FIFODATAOUT

GCLK

HSI/FIFO Flag to I/O Block Delay

HSI Output to I/O Cell Block Delay

HSIFIFOFLAG

HSIOUT

HSI Source Synchronous Clock to I/O Cell

Block Delay

t

—

0.00

—

0.00

—

0.00

—

0.00

ns

HSISSCLKOUT

t

PLL Delay Increment

—

0.33

2.20

2.10

2.40

1.70

1.40

0.90

—

0.33

2.20

2.10

2.40

1.70

1.40

0.90

—

0.33

2.20

2.10

2.40

1.70

2.70

0.90

—

0.33

3.67

3.50

4.00

2.83

4.50

1.29

ns

PLL_DELAY

Clock AND Array Delay

Clock Enable AND Array Delay

OE AND Array Delay

PTCLK

PTCLKEN

PTOE

Select AND Array Delay

Set/Reset AND Array Delay

Global Routing Pool Delay

PTSEL

PTSR

ROUTEGRP

Register/Latch Delays, Output Paths

t

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Recovery

Register/Latch Bypass Delay

—

2.50

0.00

—

2.50

0.20

—

2.50

0.50

—

4.17

0.71

—

ns

OPASROi

OPASRRi

OPBYPASS

OPCEHi

—

Register Clock Enable Hold Time

1.30

2.17

Register Clock Enable Setup Time

(Global Clock Enable)

t

1.10

1.00

—

1.10

1.00

—

1.10

2.10

—

1.83

3.50

—

ns

OPCESi

Register Clock Enable Setup Time

(Product Term Clock Enable)

OPCESi_PT

t

Register Clock to Output Delay

Register Hold Time

—

0.70

—

0.90

—

1.00

—

1.67

—

ns

OPCOi

0.80

1.33

OPHi

33

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters¹(Continued)

Over Recommended Operating Conditions

-3

-32

-35

-5

Parameter

Description

Latch Gate to Output Delay

Latch Hold Time

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

—

1.00

—

1.00

—

1.00

—

1.67

—

ns

OPLGOi

0.80

1.33

OPLHi

Latch Propagation Delay (Transparent

Mode)

t

—

0.30

—

0.30

—

0.30

—

0.50

ns

OPLPDi

t

Latch Setup Time (Global Gate)

1.20

1.00

1.20

1.00

—

1.20

1.00

1.20

1.00

—

1.20

1.00

1.20

1.00

—

2.00

1.67

2.00

1.67

—

ns

OPLSi

Latch Setup Time (Product Term Gate)

Register Setup Time (Global Clock)

Register Setup Time (Product Term Clock)

Asynchronous Set/Reset Pulse Width

OPLSi_PT

OPSi

—

OPSi_PT

OPSRPWi

2.50

4.17

Register/Latch Delays, Input Paths

t

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Recovery

Register/Latch Bypass Delay

—

1.00

2.50

0.00

—

1.00

2.50

0.00

—

1.70

2.50

0.00

—

2.83

4.17

0.00

—

ns

IPASROi

IPASRRi

IPBYPASS

IPCEHi

—

Register Clock Enable Hold Time

1.30

2.17

Register Clock Enable Setup Time

(Global Clock Enable)

t

1.10

—

1.10

—

1.10

—

1.83

—

ns

IPCESi

Register Clock Enable Setup Time

(Product Term Clock Enable)

IPCESi_PT

t

Register Clock to Output Delay

Register Hold Time

—

0.00

—

0.80

—

0.00

—

1.00

—

0.00

—

1.00

—

0.00

—

1.67

—

ns

IPCOi

IPHi

Latch Gate to Output Delay

Latch Hold Time

1.00

—

1.00

—

1.00

—

1.67

—

IPLGOi

IPLHi

0.00

Latch Propagation Delay (Transparent

Mode)

t

—

0.30

—

0.30

—

0.30

—

0.50

ns

IPLPDi

t

Latch Setup Time (Global Term)

1.50

—

1.50

—

1.50

—

2.50

—

ns

IPLSi

Latch Setup Time (Product Term Gate)

Register Setup Time (Global Clock)

Register Setup Time (Product Term Clock)

Asynchronous Set/Reset Pulse Width

IPLSi_PT

IPSi

—

IPSi_PT

IPSRPWi

2.50

4.17

OE Paths

t

Asynchronous Set/Reset to Output

Asynchronous Set/Reset Recovery

Register/Latch Bypass Delay

—

2.50

0.00

—

2.50

0.00

—

2.50

0.00

—

4.17

0.00

—

ns

OEASROi

OEASRRi

OEBYPASS

OECEHi

—

Register Clock Enable Hold Time

1.30

0.80

1.33

Register Clock Enable Setup Time (Global

Clock Enable)

t

1.20

1.50

—

1.20

1.50

—

1.20

2.10

—

2.00

3.50

—

ns

OECESi

Register Clock Enable Setup Time

(Product Term Clock Enable)

OECESi_PT

t

Register Clock to Output Delay

Register Hold Time

—

0.40

—

1.30

—

0.40

—

1.30

—

0.40

—

1.60

—

0.67

—

2.67

—

ns

OECOi

OEHi

Latch Gate to Output Delay

Latch Hold Time

1.60

—

1.60

—

1.60

—

2.67

—

OELGOi

OELHi

0.40

0.67

Latch Propagation Delay (Transparent

Mode)

t

—

0.30

—

0.30

—

0.30

—

0.50

ns

OELPDi

34

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters¹(Continued)

Over Recommended Operating Conditions

-3

-32

-35

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Latch Setup Time (Global Gate)

1.40

1.00

—

1.40

1.00

—

1.40

1.00

1.40

1.00

—

2.33

1.67

2.33

1.67

—

ns

OELSi

Latch Setup Time (Product Term Gate)

Register Setup Time (Global Clock)

Register Setup Time (Product Term Clock)

Asynchronous Set/Reset Pulse Width

OELSi_PT

OESi

—

OESi_PT

OESRPWi

2.50

4.17

Timing v.2.2

1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.

2. t is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t

(as

RANGE

PLL_DELAY

given in the sysCLOCK PLL Timing section) in either direction in steps of size t

PLL_DELAY.

35

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters

-3

-32

-35

-5

Parameter

Optional Adders

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Delay

—

1.50

1.30

—

1.50

1.30

—

1.50

1.30

—

2.50

1.30

ns

INDIO

Secondary PLL Output

Delay

t

PLL_SEC_DELAY

t

Output Adjusters

IOO

Using Slow Slew (LVTTL and

LVCMOS Outputs Only)

Slow Slew

—

0.90

1.20

0.30

—

0.90

1.20

0.30

—

0.90

1.20

0.30

—

0.90

1.20

0.30

ns

LVTTL_out

Using 3.3V TTL Drive

Using 1.8V CMOS Standard,

4mA Drive

LVCMOS_18_4mA_out

Using 1.8V CMOS Standard,

5.33mA Drive

LVCMOS_18_5.33mA_out

LVCMOS_18_8mA_out

LVCMOS_18_12mA_out

LVCMOS_25_4mA_out

LVCMOS_25_5.33mA_out

LVCMOS_25_8mA_out

LVCMOS_25_12mA_out

LVCMOS_25_16mA_out

LVCMOS_33_4mA_out

LVCMOS_33_5.33mA_out

LVCMOS_33_8mA_out

LVCMOS_33_12mA_out

LVCMOS_33_16mA_out

—

0.30

0.00

1.20

1.00

0.40

1.20

0.80

0.60

—

0.30

0.00

1.20

1.00

0.40

1.20

0.80

0.60

—

0.30

0.00

1.20

1.00

0.40

1.20

0.80

0.60

—

0.30

0.00

1.20

1.00

0.40

1.20

0.80

0.60

ns

Using 1.8V CMOS Standard,

8mA Drive

Using 1.8V CMOS Standard,

12mA Drive

Using 2.5V CMOS Standard,

4mA Drive

Using 2.5V CMOS Standard,

5.33mA Drive

Using 2.5V CMOS Standard,

8mA Drive

Using 2.5V CMOS Standard,

12mA Drive

Using 2.5V CMOS Standard,

16mA Drive

Using 3.3V CMOS Standard,

4mA Drive

Using 3.3V CMOS Standard,

5.33mA Drive

Using 3.3V CMOS Standard,

8mA Drive

Using 3.3V CMOS Standard,

12mA Drive

Using 3.3V CMOS Standard,

16mA Drive

Using 3.3V CMOS Standard,

20mA Drive

LVCMOS_33_20mA_out

AGP_1X_out

—

0.30

0.60

1.00

—

0.30

0.60

1.00

—

0.30

0.60

1.00

—

0.30

0.60

1.00

ns

Using AGP 1x Standard

Using Bus Low Voltage Dif-

ferential Signaling (BLVDS)

BLVDS_out

CTT25_out

CTT33_out

GTL+_out

Using CTT 2.5v

—

0.30

0.20

0.50

0.60

—

0.30

0.20

0.50

0.60

—

0.30

0.20

0.50

0.60

—

0.30

0.20

0.50

0.60

ns

Using CTT 3.3v

Using GTL+

HSTL_I_out

HSTL_III_out

HSTL_IV_out

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

Using HSTL 2.5V, Class IV

36

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters (Continued)

-3

-32

-35

-5

Parameter

LVPECL_out

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Using LVPECL Differential

Signaling

—

0.30

0.80

—

0.30

0.80

—

0.30

0.80

—

0.30

0.80

ns

Using Low Voltage Differen-

tial Signaling (LVDS)

LVDS_out

PCI_out

Using PCI Standard

—

0.60

0.30

0.50

0.20

0.40

—

0.60

0.30

0.50

0.20

0.40

—

0.60

0.30

0.50

0.20

0.40

—

0.60

0.30

0.50

0.20

0.40

ns

PCI_X_out

Using PCI-X Standard

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

SSTL2_I_out

SSTL2_II_out

SSTL3_I_out

SSTL3_II_out

t

Input Adjusters

IOI

LVTTL_in

Using 3.3V TTL

Using 1.8V CMOS

Using 2.5V CMOS

Using 3.3V CMOS

Using AGP 1x

—

0.00

1.00

—

0.00

1.00

—

0.00

1.00

—

0.00

1.00

ns

LVCMOS_18_in

LVCMOS_25_in

LVCMOS_33_in

AGP_1X_in

Using Bus Low Voltage Differ-

ential Signaling (BLVDS)

BLVDS_in

—

0.50

—

0.50

—

0.50

—

0.50

ns

CTT25_in

CTT33_in

GTL+_in

Using CTT 2.5V

—

1.00

0.50

0.60

—

1.00

0.50

0.60

—

1.00

0.50

0.60

—

1.00

0.50

0.60

ns

Using CTT 3.3V

Using GTL+

HSTL_I_in

HSTL_III_in

HSTL_IV_in

Using HSTL 2.5V, Class I

Using HSTL 2.5V, Class III

Using HSTL 2.5V, Class IV

Using Differential Signaling

(LVPECL)

LVPECL_in

LVDS_in

—

0.00

0.50

—

0.00

0.50

—

0.00

0.50

—

0.00

0.50

ns

Using Low Voltage Differen-

tial Signaling (LVDS)

PCI_in

Using PCI

—

1.00

0.50

0.60

—

1.00

0.50

0.60

—

1.00

0.50

0.60

—

1.00

0.50

0.60

ns

PCI_X_in

Using PCI-X

SSTL2_I_in

SSTL2_II_in

SSTL3_I_in

SSTL3_II_in

Using SSTL 2.5V, Class I

Using SSTL 2.5V, Class II

Using SSTL 3.3V, Class I

Using SSTL 3.3V, Class II

ns

Timing v.2.2

37

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing

-3

-32

-35

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Routing Delays

t

FIFO Input Delay

—

0.00

—

0.00

—

0.00

—

0.00

ns

FIFODATAIN

FIFODATAOUT

FIFORCLK

FIFOREN

FIFO Output to I/O Core Delay

Read Clock Input Delay

Read Clock Enable Input Delay

Write Clock Input Delay

FIFOWCLK

FIFOWEN

Write Clock Enable Input Delay

Core Delays

t

Global Read Clock to Write Clock Skew

Read Clock to Empty Flag Delay

Write Clock to Full Flag Delay

—

2.00

1.30

—

2.00

1.80

—

2.00

1.80

—

3.33

3.00

ns

FIFOCLKSKEW

FIFOEMPTY

FIFOFULL

Read Clock Hold after Read Clock Enable

Time

FIFORCEH

—

0.00

1.50

—

0.00

1.50

—

0.00

1.50

—

0.00

2.50

ns

t

Read Clock Setup before Read Clock

Enable Time

FIFORCES

t

Read Clock to FIFO Out Delay

Reset to Output Delay

—

0.50

0.70

2.00

1.20

0.00

—

0.50

0.70

2.00

1.50

0.00

—

0.50

0.70

2.00

0.00

—

0.83

1.17

3.33

0.00

ns

FIFORCLKO

FIFORSTO

FIFORSTPW

FIFORSTR

FIFOSTRD

FIFOTHRU

FIFOWCEH

Reset Pulse Width

Reset Recovery Time

Write Clock to Start Read Flag Delay

Flow Through Delay

Write Clock hold after Write Clock Enable

Time

—

2.00

0.00

—

2.00

0.00

—

2.00

0.00

—

3.33

0.00

ns

t

Write Clock Setup before Write Clock Enable

Time

FIFOWCES

t

Write Data Hold after Write Clock Time

Write Data Setup before Write Clock Time

—

0.50

1.00

—

0.50

1.00

—

0.70

1.00

—

1.17

1.67

ns

FIFOWCLKH

FIFOWCLKS

Timing v.2.2

38

Lattice Semiconductor

ispGDX2 Family Data Sheet

sysHSI Block Timing

Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on

a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N

input skew tolerance.

Figure 22. Receive Data Eye Diagram Template (Differential)

Bit Time

V_THD

200 mV Differential

+/- 100 mV Single Ended

jt_TH

eo_SIN

jt_TH

jt_TH: Optimum Threshold Crossing Jitter

The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal

quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye

closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s

ability to transfer error-free data.

Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital

links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery

(CDR) portion of the ispGDX2 SERDES receiver is its ability to ﬁlter incoming signal jitter that is below the clock

recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data

error free, with eye openings signiﬁcantly less than that shown in Figure 22.

sysHSI Block AC Speciﬁcations

Operating Frequency Ranges

Symbol

Description

Mode

SS:CAL

10B12B

8B10B

Test Condition

Min.

50

Max.

200

67

Units

MHz

f

Reference Clock Frequency

33

MHz

CLK

40

80

MHz

SS:CAL

10B12B

8B10B

with eo

400

800¹

Mbps

SIN

2

f

Serial Input

Serial Out

with eo

SIN

with eo

SIN

C = 5 pF, R = 100 Ohms,

LVDS

400

800¹

Mbps

2

L

SOUT

f

with no jitter

CLK

1. f

2. f

(8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.

SIN

and f

speeds are supported at V and V at 1.7V to 1.9V for ispGDX2C devices.

SIN

SOUT

CC

CCP

39

Lattice Semiconductor

ispGDX2 Family Data Sheet

LOCKIN Time

Symbol

Description

Mode

All

Condition

Min.

Max.

25

Units

t

CSPLL Lock Time

After input is stabilized

With SS mode sync pattern

μS

SCLOCK

1

SS

1024

960

t

RCP

CDRPLL Lock-in Time

10B12B With 10B12B sync pattern

t

CDRLOCK

RCP

8B10B

SS

With 8B10B idle pattern

t

SyncPat Length

1200

1100

50

t

SYNC

CAL Duration

SS

CAL

SyncPat Set-up Time to CAL

SyncPat Hold Time from CAL

SS

SUSYNC

SS

50

HDSYNC

1. REFCLK clock period.

REFCLK and SS_CLKIN Timing

Symbol

Description

Mode

Condition

Min.

Max.

100

Units

ppm

UIPP

ns

Frequency Deviation Between TX REFCLK and

CDRX REFCLK on One Link

8B10B/

10B12B

t

-100

DREFCLK

REFCLK, SS_CLKIN Peak-to-Peak Period Jitter

All

Random Jitter

0.01

JPPREFCLK

PWREFCLK

REFCLK, SS_CLKIN Pulse Width, (80% to 80% or

20% to 20%).

All

1

REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or

80% to 20%)

t

All

2

ns

RFREFCLK

Serializer Timing²

Symbol

Description

Mode

Condition

with no jitter

CLK

Min.

Max.

Units

UIPP

ps

t

SOUT Peak-to-Peak Output Data Jitter

SOUT Peak-to-Peak Random Jitter

SOUT Peak-to-Peak Deterministic Jitter

All

f

0.25

130

JPPSOUT

8B10B 800 Mbps w/K28.7-

t

JPP8B10B

8B10B 800 Mbps w/K28.5+

160

ps

LVDS

BLVDS

700

ps

SOUT Output Data Rise/Fall Time (20%,

80%)

t

RFSOUT

900

ps

SS/8B10B

10B12B

2Bt¹+ 2

1Bt¹+ 2

2Bt¹+10

1Bt¹+10

ns

t

REFCLK to SOUT Delay

COSOUT

SKTX

ns

Skew of SOUT with Respect to

SS_CLKOUT

SS

250

ps

t

SS_CLKOUT to bit0 of SOUT

TXD Data Setup Time

TXD Data Hold Time

SS

2Bt¹- t

2Bt¹+ t

SKTX

ns

CKOSOUT

SKTX

All

Note 3

1.5

HSITXDDATAS

1.0

HSITXDDATAH

1. Bt: Bit Time Period. High Speed Serial Bit Time.

2. The SIN and SOUT jitter speciﬁcations listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in

sysCLOCK PLL BYPASS mode.

3. Internal timing for reference only.

40

Lattice Semiconductor

ispGDX2 Family Data Sheet

Deserializer Timing

Symbol

Description

Mode

Conditions

Min.

-100

0.45

Max.

Units

8B10B/

10B12B

f

SIN Frequency Deviation from REFCLK

100

ppm

DSIN

eo

SIN Eye Opening Tolerance

Bit Error Rate

All

Notes 1, 2

UIPP

Bits

SIN

ber

10^-12

RXD, SYDT Valid Time Before RECCLK Fall-

ing Edge

t

All

Note 3

t

/2 - 0.7

ns

HSIOUTVALIDPRE

HSIOUTVALIDPOST

DSIN

RCP

RXD, SYDT Valid Time

After RECCLK Falling Edge

Bit 0 of SIN Delay to RXD Valid at RECCLK

Falling edge

1.5 t

+

1.5 t

4.5Bt + 10

+

RCP

4.5Bt + 2

1. Eye opening based on jitter frequency of 100KHz.

2. Lower frequency operation assumes maximum eye closure of 800ps.

3. Internal timing for reference only.

Lock-in Timing

CDRX_SS LOCK-IN (DE-SKEW) TIMING

SIN

MIN. 1200 SYNCPAT

MIN. 1100 LS CYCLE

DATA (SERIAL)

CAL

t_HDSYNC

t_SUSYNC

SYDT

RXD(0:7)

SYNCPAT

TRAINING SEQUENCE

DATA (PARALLEL)

SS MODE DATA TRANSFER

CDR_10B12B LOCK-IN TIMING

SIN

1024 SYNCPAT

DATA (SERIAL)

SYDT

RXD(0:9)

SYNCPAT

DATA (PARALLEL)

41

Lattice Semiconductor

ispGDX2 Family Data Sheet

Lock-in Timing (Continued)

CDR_8B10B LOCK-IN TIMING

SIN

240 Idle Pattern(960 TRCP)

DATA (SERIAL)

SYDT

RXD(0:9)

Idle Pattern

DATA (PARALLEL)

SYDT Timing

SYDT TIMING FOR CDRX_10B12B

RECCLK

SYDT

RXD(0:9)

Data0 Data1 Data2 Data3 Data4

Parallel Data

SYNC PATTERN

SYDT TIMING FOR CDRX_8B10B

RECCLK

SYDT

RXD(0:9)

K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5

D0

D2

D1

IDLE PATTERN

Data

42

Lattice Semiconductor

Serializer Timing

ispGDX2 Family Data Sheet

8B/10B SERIALIZER DELAY TIMING

SYMBOL N

t_COSOUT

SYMBOL N+1

TXD

REFCLK

SOUT

b4

b4 b5 b6 b7 b8 b9 b0 b1 b2 b3

b5 b6 b7 b8 b9 b0 b1 b2

SYMBOL N

SYMBOL N-1

SYMBOL N+1

10B/12B SERIALIZER DELAY TIMING

SYMBOL N

t_COSOUT

SYMBOL N+1

TXD

REFCLK

SOUT

b4

b5 b6 b7 b8 b9

"0" "1"

b4 b5 b6 b7 b8 b9

SYMBOL N-1

b0 b1 b2 b3

"0"

"1"

SYMBOL N

SS Mode SERIALIZER DELAY TIMING

SYMBOL N

SYMBOL N+1

TXD

t_COSOUT

REFCLK

SS_CLKOUT

SOUT

t_CKOSOUT

t_SKTX

b4

b5

b6

b7

b0

b2

SYMBOL N

b5

b1

b3

b6

b7

b0

SYMBOL

N+1

SYMBOL N-1

INTERNAL TIMING FOR sysHSI BLOCK

t_PWREFCLK

REFCLK

t_HSITXDDATAS

t_HSITXDDATAH

TXD

43

Lattice Semiconductor

Deserializer Timing

ispGDX2 Family Data Sheet

8B/10B DESERIALIZER DELAY TIMING

SYMBOL N+1

SYMBOL N

SYMBOL N+2

b4

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3

T_DSIN

b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5

SIN

RECCLK

RXD

SYMBOL N

SYMBOL N-1

10B/12B DESERIALIZER DELAY TIMING

SYMBOL N+2

SYMBOL N

b0 b1 b2 b3 b4 b5

SYMBOL N+1

SIN

b8 b9

b6 b7

"0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9

b4

"1"

"0" "1" b0 b1 b2 b3

T_TDSIN

RECCLK

RXD

SYMBOL N-1

SYMBOL N-2

SYMBOL N

CDRX_SS DESERIALIZER DELAY TIMING

SYMBOL N

SYMBOL N+2

SYMBOL N+1

b7

b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6

T_DSIN

b0 b1 b2 b3 b4

SIN

RECCLK

RXD

SYMBOL N-2

SYMBOL N

SYMBOL N-1

INTERNAL TIMING FOR sysHSI BLOCK

RECCLK

t_{HSIOUTVALIDPRE}

t_{HSIOUTVALIDPOST}

SYDT, RXD

44

Lattice Semiconductor

ispGDX2 Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Symbol

Parameter

Conditions

80% to 80%

Min

0.5

—

Max

—

Units

ns

t

Input clock, high time

Input clock, low time

PWH

PWL

20% to 20%

—

ns

t , t

Input Clock, rise and fall time

20% to 80%

3.0

ns

R

F

t

f

t

Input clock stability, cycle to cycle (peak)

M Divider input, frequency range

M Divider output, frequency range

N Divider input, frequency range

N Divider output, frequency range

V Divider input, frequency range

V Divider output, frequency range

Output clock, duty cycle

—

+/- 300

320

400

320

60

ps

INSTB

10

MHz

%

MDIVIN

MDIVOUT

NDIVIN

10

NDIVOUT

VDIVIN

100

10

VDIVOUT

OUTDUTY

40

Clean reference¹:

10 MHz ≤ f

100 MHz ≤ f

Clean reference¹:

≤ 40 MHz or

≤ 160 MHz

—

+/- 600

+/- 150

+/- 600

+/- 150

ps

MDIVOUT

VDIVIN

t

Output clock, cycle to cycle jitter (peak)

Output clock, period jitter (peak)

JIT(CC)

40 MHz ≤ f

160 MHz ≤ f

≤ 320 MHz and

≤ 400 MHz

MDIVOUT

VDIVIN

Clean reference¹:

10 MHz ≤ f

100 MHz ≤ f

≤ 40 MHz or

≤ 160 MHz

MDIVOUT

VDIVIN

2

T

JIT(PERIOD)

Clean reference¹:

40 MHz ≤ f

160 MHz ≤ f

≤ 320 MHz and

≤ 400 MHz

MDIVOUT

VDIVIN

t

Input clock to CLK_OUT delay

Internal feedback

External feedback

—

3.4

500

25

ns

ps

us

ps

ns

CLK_OUT_DLY

Input clock to external feedback delta

Time to acquire phase lock after input stable

Delay increment (Lead/Lag)

PHASE

LOCK

Typical = +/- 250ps

+/- 120 +/- 550

+/- 0.84 +/- 3.85

PLL_DELAY

RANGE

Total output delay range (lead/lag)

Minimum reset pulse width

1.8

—

PLL_RSTW

1. This condition assures that the output phase jitter will remain within speciﬁcation. Jitter speciﬁcation is based on optimized M, N and V set-

tings determined by the ispLEVER software.

2. Accumulated jitter measured over 10,000 waveform samples

45

Lattice Semiconductor

ispGDX2 Family Data Sheet

Boundary Scan Timing Speciﬁcations

Over Recommended Operating Conditions

Parameter

Description

Min

40

20

8

Max

—

Units

ns

t

TCK [BSCAN] clock pulse width

BTCP

TCK [BSCAN] clock pulse width high

—

ns

BTCPH

BTCPL

BTS

TCK [BSCAN] clock pulse width low

—

ns

TCK [BSCAN] setup time

—

ns

TCK [BSCAN] hold time

10

50

—

8

—

ns

BTH

TCK [BSCAN] rise/fall time

—

mV/ns

ns

BTRF

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enable

BSCAN test capture register setup time

10

—

BTCO

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

BUTCO

BTUODIS

BTUPOEN

ns

BSCAN test capture register hold time

10

—

ns

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

25

ns

46

Lattice Semiconductor

ispGDX2 Family Data Sheet

Power Consumption

I_CORE

I_HSI

I_PLL

200

90

80

100

I_{HSI_D}

I_{PLL_D}

70

60

50

40

30

20

10

0

80

150

100

50

60

40

20

0

I_{HSI_A}

I_{PLL_A}

0

200

400

600

800 1000 1200

0

50 100 150 200 250 300 350

0

200

400

600

MHz

Mbps

MHz

Power Estimation Coefﬁcients – Core and PLL

Device

V

I

(mA)

K

PLLA

CC

DC

REF

IN

CORE

PLLD

3.3

2.5

1.8

10.0

3.25

3.13

3.00

0.0139

0.292

0.157

0.179

0.024

ispGDX2-256

10.0

4.0

0.0139

0.0213

0.292

0.239

0.024

I

:

Blank chip background current

DC

K

K :

:

Reference voltage circuit current per bank

I/O current per input per MHz

REF

IN

K

:

Core current per MHz with GRP fanout of 1

PLL logic current per MHz per PLL

PLL analog portion current per MHz per PLL

CORE

:

PLLD

:

PLLA

Power Estimation Coefﬁcients – sysHSI

Device

V

K

TXA

CC

RXD

RXSTBY

RXA

TXD

TXSTBY

3.3

2.5

1.8

0.027

0.019

1.3

0.0023

0.0040

0.011

2.4

0.0018

0.0023

ispGDX2-256

1.3

3.7

2.4

1.2

K

:

Receiver Logic current per Mbps

Receiver Logic standby current

Receiver Analog portion current per Mbps

Transmitter Logic current per Mbps

Transmitter Logic standby current

Transmitter Analog portion current per Mbps

RXD

:

RXSTBY

:

RXA

TXD

:

TXSTBY

:

TXA

47

Lattice Semiconductor

ispGDX2 Family Data Sheet

Power Consumption (Continued)

Power consumption in the ispGDX2 family is the sum of three components:

I

= I

+ I

(I

combines current supplied via V pins and V pins)

CCP

CC-TOTAL

CORE

PLL

HSI CC-TOTAL

CC

I

= I + I

+ I

CORE

DC

REF IN

= Blank chip background current

+ K * Number of Banks with V

active

REF

+ (K * Number of inputs + K

) * Average Input Switching Frequency (MHz)

IN

CORE

I

= I

+ I

PLL

PLL_D PLL_A

= [K

* F

* Number of PLLs used] + [K

* F

* Number of PLLs used]

PLLD

VCO

PLLA

VCO

= [(K

+ K

) * F

] * Number of PLLs used

PLLD

PLLA

VCO

= I + I

HSI

RX

TX

= [(K

+ K

) * F + I

] * Number of Receiver Channels

RXD

RXA

RX

RXSTBY

+ [(K

+ K

) * F + I

] * Number of Transmitter Channels

TXD

TXA

TX

TXSTBY

Where:

F

: sysClock PLL VCO Frequency in MHz

sysHSI Receiver Serial Data Rate

sysHSI Transmitter Serial Data Rate

VCO

:

RX

:

TX

I

can also be determined by calculating I

, the current supplied by the V pin, and I the current sup-

HSI_A,

HSI

HSI_D

CC

plied by the V

and V

.

CCP0

CCP1

I

= I

+ I

HSI

HSI_D HSI_A

= [(K

* F + I

)* Number of Receiver Channels

RXD

RX

RXSTBY

+ (K

* F + I

) * Number of Transmitter Channels]

TXD

RXA

TXA

TX

TXSTBY

+[(K

+ (K

* F ) * Number of Receiver Channels

RX

* F ) * Number of Transmitter Channels]

TX

The I

is supplied through V

and V

pins for PLL and sysHSI analog portion. The equation for I

can

CCP

CCP0

CCP1

CCP

be derived from the equations below.

I

= I

+ I

CCP

PLL_A HSI_A

= [(K

* F

) * Number of PLLs used]

PLLA

VCO

+ [(K

* F ) * Number of Receiver Channels

RXA

RX

+ (K

* F ) * Number of Transmitter Channels]

TXA

TX

Where:

I

: PLL Analog Portion Current

: HSI Analog Portion Current

PLL_A

HSI_A

Note: For further information about the use of these coefﬁcients, refer to Technical Note TN1034, Power Estimation

in the ispGDX2 Family.

I

estimates are based on typical conditions. These values are for estimates only. Since the value of I

CC-

CC-TOTAL

is sensitive to operating conditions and the program in the device, the actual current should be veriﬁed.

TOTAL

48

Lattice Semiconductor

ispGDX2 Family Data Sheet

Switching Test Conditions

Figure 23 shows the output test load used for AC testing. Speciﬁc values for resistance, capacitance, voltage and

other test conditions are shown in Table 7.

Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V)

V_CCO

R₁

Device

Output

Test

Point

R₂

C_L*

*C_Lincludes Test Fixture and Probe Capacitance.

Table 7. Test Fixture Required Components

Test Condition

R

C

Timing Ref.

/2

V

CCO

1

2

L

Default LVCMOS 1.8 I/O (L -> H, H -> L)

106

35pF

V

1.8V

LVCMOS3.3 = 3.0V

LVCMOS2.5 = 2.3V

LVCMOS1.8 = 1.65V

1.65V

CCO

LVCMOS3.3 = 1.5V

LVCMOS I/O (L -> H, H -> L)

—

35pF

LVCMOS2.5 = V

LVCMOS1.8 = V

/2

CCO

Default LVCMOS 1.8 I/O (Z -> H)

Default LVCMOS 1.8 I/O (Z -> L)

Default LVCMOS 1.8 I/O (H -> Z)

Default LVCMOS 1.8 I/O (L -> Z)

—

106

—

106

—

35pF

5pF

V

/2

CCO

1.65V

106

—

V

- 0.15

+ 0.15

1.65V

OH

106

5pF

V

1.65V

OL

Note: Output test conditions for all other interfaces are determined by the respective standards.

49

Lattice Semiconductor

ispGDX2 Family Data Sheet

Signal Descriptions¹

Signal Names

General Purpose

BKx_IOy

Description

Input/Output – General purpose I/O number y in I/O Bank X.

Input – Global clock/clock enable inputs.

GCLK/CE0, GCLK/CE1, GCLK/CE2,

GCLK/CE3

SEL0, SEL1, SEL2², SEL3²

GOE0, GOE1, GOE2², GOE3²

Input – Global MUX select inputs.

Input – Global output enable inputs.

Input – Global RESET signal (active low).

No connect.

RESETb

NC

GND

GND – Ground.

V

VCC – The power supply pins for core logic.

VCC – The power supply for the JTAG logic.

VCC – The power supply pins for I/O Bank X.

Input – Deﬁnes the reference voltage for I/O Bank X.

CC

CCJ

CCO

x

REF

x

Testing and Programming

TMS

Input – Test Mode Select input, used to control the 1149.1 state machine.

Input – Test Clock Input pin, used to clock the 1149.1 state machine.

Input – Test Data In pin, used to load data into device using 1149.1 state machine.

Output – Test Data Out pin used to shift data out of device using 1149.1.

Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.

TCK

TDI

TDO

TOE

PLL Functions

PLL_FBKz

PLL_RSTz

CLK_OUTz

Input – Optional feedback input allows external feedback for PLL z.

Input – Optional input resets the M divider in PLL z.

Output – Optional clock output from PLL z (clock signal occupies the input path of

this I/O pad).

PLL_LOCKz

Output – Optional lock output from PLL z (lock signal occupies the input path of this

I/O pad).

GND GND

GND – Ground for PLLs.

P0,

P1

V

VCC – The power supply pins for PLLs.

CCP0, CCP1

FIFO Functions

FIFOy_DINw

Input – DATA IN Bit w of FIFO y.

FIFOy_DOUTw

Internal Signal – DATA OUT Bit w of FIFO y

Input – Reset input for FIFO y (active low).

Output – FULL ﬂag for FIFO y.

FIFOy_FIFORSTb

FIFOy_FULL

FIFOy_EMPTY

Output – EMPTY ﬂag for FIFO y.

FIFOy_STRDb

Output – Start read (STRDb) ﬂag for FIFO y.

SERDES Functions

HSImA_SINP, HSImB_SINP

HSImA_SINN, HSImB_SINN

HSImA_SOUTP, HSImB_SOUTP

HSImA_SOUTN, HSImB_SOUTN

HSImA_SYDT, HSImB_ SYDT

HSImA_RECCLK, HSImB_RECCLK

Input – Positive sense serial input for sysHSI BLOCK m channel A, B.

Input – Negative (minus) sense serial input for sysHSI BLOCK m channel A, B.

Output – Positive sense serial output for sysHSI BLOCK m channel A, B.

Output – Negative (minus) sense serial output for sysHSI BLOCK m channel A, B.

Output – Symbol alignment detect for sysHSI BLOCK m channel A, B.

Internal Signal – Recovered clock for sysHSI BLOCK m channel A, B.

HSImA_CDRRSTb, HSImB_CDRRSTb Input – Resets the CDR circuit of sysHSI BLOCK m channel A, B.

HSIm_CSLOCK Output – LOCK output of the PLL associated with channel m.

50

Lattice Semiconductor

ispGDX2 Family Data Sheet

Signal Descriptions¹(Continued)

Signal Names

Description

HSImA_TXDw, HSImB_ TXDw

HSImA_RXDw, HSImB_ RXDw

Source Synchronous Functions

SS_SCLKIN0P, SS_SCLKIN1P

SS_SCLKIN0N, SS_SCLKIN1N

SS_CLKOUT0N, SS_CLKOUT1P

SS_CLKOUT0N, SS_CLKOUT1N

CAL

Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.

Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.

Input – Positive sense clock input for Source Synchronous group A, B.

Input – Negative (minus) sense clock input for Source Synchronous group A, B.

Output – Positive sense clock output for Source Synchronous group A, B.

Output – Negative (minus) sense clock output for Source Synchronous group A, B.

Input – Initiates source synchronous calibration sequence.

1. m, w, x, y and z are variables.

2. Not on ispGDX2-64

ispGDX2-64 Power Supply and NC Connections¹

Signal

ispGDX2-64 (100-Ball fpBGA)²

V

A1, K10

CC

J7

CCO0

CCO1

CCO2

CCO3

CCO4

CCO5

CCO6

CCO7

CCJ

F10

E10

B7

B4

E1

F1

K4

K1

G6

CCP0

GND

G5

P0

A10, B9, C8, E6, E5, F6, F5, H3, J2

1. All grounds must be electrically connected at the board level.

2. Pin orientation A1 starts from the upper left corner of the top

side view with alphabetical order ascending vertically and

numerical order ascending horizontally.

51

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2 Power Supply and NC Connections¹

Signal

ispGDX2-128 (208-Ball fpBGA)³

ispGDX2-256 (484-Ball fpBGA)³

V

B15, C14, R15, B2, C3, P3, R2,

AA3, AA20, B3, B20, C2, C11, C12, C21, H9, H10, H11,

H12, H13, H14, J8, J15, K8, K15, L8, L15, L20, M3, M8,

M15, M20, N8, N15, P8, P15, R9, R10, R11, R12, R13,

R14, Y2, Y11, Y12, Y21

CC

V

N11, T12

L13, M16

E16, F13

A12, D11

A5, D6

E1, F4

L4, M1

N6, T5

P14

AA14, AB20, Y17

P21, U20, Y22

C22, E20, J21

A20, B14, C17

A3, B9, C6

C1, F3, J2

P2, U3, Y1

AA9, AB3, Y6

L3

CCO0

CCO1

CCO2

CCO3

CCO4

CCO5

CCO6

CCO7

CCJ

J1

K1

CCP0

CCP1

J16

N22

GND

H1

J1

P0

P1

H16

K22

A16, D13, H15, J15, N13, T16, A1, B9, B8, D4, H2, J2, A2, A11, A12, A21, A1, A22, AA1, AA2, AA11, AA12,

N4, R8, R9, T1, G7, G8, G9, G10, H7, H8, H9, H10, J7, AA21, AA22, AB1, AB2, AB11, AB12, AB21, AB22, B1,

J8, J9, J10, K7, K8, K9, K10

B2, B11, B12, B21, B22, C3, C20, D4, D19, E5, E18, F6,

F17, G7, G16, H8, H15, J9, J10, J11, J12, J13, J14, K9,

K10, K11, K12, K13, K14, L1, L2, L7, L9, L10, L11, L12,

L13, L14,L16, L21, L22, M1, M2, M7, M9, M10, M11,

M12,M13, M14, M16, M21, M22, N9, N10, N11, N12,

N13, N14, P9, P10, P11, P12, P13, P14, R8, R15, T7,

T16, U6, U17, V5, V18, W4, W19,Y3, Y20

NC²

A11, B16

D8, D11, E6, E7, E8, E9, E12, E13, E14, E15, E16, F7,

F16, G5, G6, G18, G19, H19, K4, K19, L19, M4, M19,

N4, P4, P19, R4, R18, T4, T5, T17, T18, U5, U7, U16, V7,

V8, V9, V10, V11, V12, V15, V16, V17, W14, Y18

1. All grounds must be electrically connected at the board level.

2. NC pins should not be connected to any active signals, V or GND.

CC

3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

52

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-64 Logic Signal Connections

sysIO

LVDS

GDX

SERDES Mode

I/O Cell²

FIFO Mode I/O

Cell/Pin³

100

Signal Name

GOE0

Bank Pair/Polarity Block MRB

I/O Pin¹

fpBGA

-

0

1

-

H6

J6

BK0_IO0/PLL_LOCK0

BK0_IO1

GND

0

-

0N

0P

-

0A

-

FIFO0_FULL

HSI0A_CDRRSTb

-

FIFO0_FIFORSTb

K6

-

GND

G7

BK0_IO2

BK0_IO3

GND

1N

1P

-

0A

-

2

3

-

HSI0A_SINN

HSI0A_RECCLK

HSI0A_SINP

-

H7

-

GND

K7

BK0_IO4/PLL_RST0

BK0_IO5

BK0_IO6

BK0_IO7

GND

2N

2P

3N

3P

-

0A

-

4

5

6

7

-

HSI0A_RXD0/TXD0 FIFO0_DIN0/DOUT0

HSI0A_RXD1/TXD1 FIFO0_DIN1/DOUT1

HSI0A_RXD2/TXD2 FIFO0_DIN2/DOUT2

HSI0A_RXD3/TXD3 FIFO0_DIN3/DOUT3

-

K8

-

J8

Note 4

K9

-

GND

J10

J9

TCK

-

RESETb

-

BK1_IO0/PLL_FBK0

BK1_IO1

BK1_IO2

BK1_IO3/VREF(0,1)

GND

1

-

4P

4N

5P

5N

-

0A

-

8

9

10

11

-

HSI0A_SYDT⁵

HSI0A_RXD4/TXD4 FIFO0_DIN4/DOUT4

HSI0A_RXD5/TXD5 FIFO0_DIN5/DOUT5

HSI0A_RXD6/TXD6 FIFO0_DIN6/DOUT6

HSI0A_RXD7/TXD7 FIFO0_DIN7/DOUT7

H10

H9

-

H8

FIFO0_STRDb⁶

G10

GND

G9

-

BK1_IO4

BK1_IO5

GND

6P

6N

0A

12

13

HSI0A_SOUTP

HSI0A_RXD8/TXD8 FIFO0_DIN8/DOUT8

HSI0A_RXD9/TXD9 FIFO0_DIN9/DOUT9

HSI0A_SOUTN

G8

-

GND

F9

BK1_IO6

BK1_IO7

GCLK/CE2

GCLK/CE3

BK2_IO0

BK2_IO1

GND

7P

7N

0A

-

14

15

-

SS_CLKIN1P

HSI0A_SYDT⁵

-

SS_CLKIN1N

-

FIFO0_ EMPTY

F8

CLK2P

CLK2N

8N

-

F7

-

E7

2

3

0B

-

0

SS_CLKOUT0N

-

FIFO1_FULL

E8

8P

1

SS_CLKOUT0P

-

FIFO1_EMPTY

E9

-

GND

D8

BK2_IO2

BK2_IO3

GND

9N

0B

-

2

HSI0B_SOUTN

HSI0BA_SYDT⁵

HSI0B_RXD0/TXD0

-

9P

3

HSI0B_SOUTP

FIFO1_DIN0

-

D9

-

GND

D10

C9

BK2_IO4/V

BK2_IO5

BK2_IO6

BK2_IO7

BK3_IO0

BK3_IO1

BK3_IO2

BK3_IO3

GND

(2,3)

10N

10P

11N

11P

12P

12N

13P

13N

-

0B

-

4

-

HSI0B_RXD1/TXD1 FIFO1_DIN1/DOUT1

HSI0B_RXD2/TXD2 FIFO1_DIN2/DOUT2

HSI0B_RXD3/TXD3 FIFO1_DIN3/DOUT3

HSI0B_RXD4/TXD4 FIFO1_DIN4/DOUT4

HSI0B_RXD5/TXD5 FIFO1_DIN5/DOUT5

HSI0B_RXD6/TXD6 FIFO1_DIN6/DOUT6

HSI0B_RXD7/TXD7 FIFO1_DIN7/DOUT7

HSI0B_RXD8/TXD8 FIFO1_DIN8/DOUT8

REF

5

-

6

HSI0_CSLOCK

Note 4

C10

B10

A9

7

8

-

9

HSI0B_SYDT⁵

B8

10

11

-

A8

-

A7

-

GND

C7

BK3_IO4

BK3_IO5

GND

14P

14N

-

0B

-

12

13

-

HSI0B_SINP

HSI0B_SINN

-

HSI0B_RXD9/TXD9 FIFO1_DIN9/DOUT9

HSI0B_RECCLK

-

D7

-

GND

B6

BK3_IO6

15P

15N

0B

14

FIFO1_STRDb⁶

-

BK3_IO7/CLK_OUT0

15 HSI0B_CDRRSTb

FIFO1_FIFORSTb

C6

53

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-64 Logic Signal Connections (Continued)

sysIO

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

100

fpBGA

Signal Name

Bank Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

SEL0

SEL1

-

D6

D5

-

BK4_IO0/CLK_OUT2

BK4_IO1

GND

4

-

16N

16P

-

1A⁷

-

1A⁷

0

1

-

HSI1A_CDRRSTb

FIFO2_STRDb⁶

-

FIFO2_FIFORSTb

C5

-

B5

-

GND

D4

BK4_IO2

BK4_IO3

GND

17N

17P

2

3

HSI1A_SINN

HSI1A_RECCLK

HSI1A_SINP

HSI1A_RXD9/TXD9 FIFO2_DIN9/DOUT9

C4

-

GND

A6

BK4_IO4

BK4_IO5

BK4_IO6

BK4_IO7

TMS

18N

18P

19N

19P

1A⁷

-

4

5

-

HSI1A_RXD8/TXD8 FIFO2_DIN8/DOUT8

HSI1A_RXD7/TXD7 FIFO2_DIN7/DOUT7

HSI1A_RXD6/TXD6 FIFO2_DIN6/DOUT6

HSI1A_RXD5/TXD5 FIFO2_DIN5/DOUT5

CAL

HSI1A_SYDT⁵

A5

6

A4

7

-

A3

-

B3

TDI

-

A2

GND

-

GND

B1

TDO

-

TOE

-

B2

BK5_IO0

BK5_IO1

BK5_IO2

BK5_IO3/Vref(4,5)

GND

5

-

20P

20N

21P

21N

-

1A⁷

-

1A⁷

-

8

Note 4

HSI1A_RXD4/TXD4 FIFO2_DIN4/DOUT4

HSI1A_RXD3/TXD3 FIFO2_DIN3/DOUT3

HSI1A_RXD2/TXD2 FIFO2_DIN2/DOUT2

HSI1A_RXD1/TXD1 FIFO2_DIN1/DOUT1

C1

9

HSI1_CSLOCK

C2

10

11

-

C3

-

D1

-

GND

D3

BK5_IO4

BK5_IO5

GND

22P

22N

-

12

13

HSI1A_SOUTP

HSI1A_RXD0/TXD0 FIFO2_DIN0/DOUT0

HSI1A_SOUTN

HSI1A_SYDT⁵

-

D2

-

GND

E2

BK5_IO6

BK5_IO7

GCLK/CE0

GCLK/CE1

BK6_IO0

BK6_IO1

GND

23P

23N

CLK0P

CLK0N

24N

24P

-

1A⁷

-

14

15

-

SS_CLKIN1P

-

FIFO2_EMPTY

SS_CLKIN1N

-

FIFO2_FULL

E3

-

E4

-

F4

6

7

1B

-

0

SS_CLKOUT1N

-

FIFO3_EMPTY

F3

1

SS_CLKOUT1P

HSI1B_SYDT⁵

-

F2

-

GND

G3

G2

GND

G1

H1

BK6_IO2

BK6_IO3

GND

25N

25P

-

1B

-

2

HSI1B_SOUTN

HSI1B_RXD9/TXD9 FIFO3_DIN9/DOUT9

HSI1B_RXD8/TXD8 FIFO3_DIN8/DOUT8

3

HSI1B_SOUTP

-

BK6_IO4/Vref(Bank6,7)

BK6_IO5

BK6_IO6

BK6_IO7/PLL_FBK2

BK7_IO0

BK7_IO1

BK7_IO2

BK7_IO3/PLL_RST2

GND

26N

26P

27N

27P

28P

28N

29P

29N

-

1B

-

4

FIFO3_STRDb⁶

HSI1B_RXD7/TXD7 FIFO3_DIN7/DOUT7

HSI1B_RXD6/TXD6 FIFO3_DIN6/DOUT6

HSI1B_RXD5/TXD5 FIFO3_DIN5/DOUT5

HSI1B_RXD4/TXD4 FIFO3_DIN4/DOUT4

HSI1B_RXD3/TXD3 FIFO3_DIN3/DOUT3

HSI1B_RXD2/TXD2 FIFO3_DIN2/DOUT2

HSI1B_RXD1/TXD1 FIFO3_DIN1/DOUT1

HSI1B_RXD0/TXD0 FIFO3_DIN0/DOUT0

5

-

6

-

H2

7

HSI1B_SYDT⁵

J1

8

Note 4

J3

9

-

K2

10

11

-

J4

-

K3

-

GND

G4

H4

BK7_IO4

BK7_IO5

30P

30N

1B

12

13

HSI1B_SINP

HSI1B_SINN

-

HSI1B_RECCLK

54

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-64 Logic Signal Connections (Continued)

sysIO

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

100

fpBGA

Signal Name

Bank Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

GND

7

-

FIFO3_FIFORSTb

FIFO3_FULL

-

GND

K5

BK7_IO6

31P

31N

-

1B

-

14 HSI1B_CDRRSTb

BK7_IO7/PLL_LOCK2

GOE1

15

-

J5

H5

1. The signals in this column route to/from the assigned pins of the associated I/O cell.

2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When

transmit data (TXD) is present in the cell, the associated pin is available for input only.

3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in

FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and

the pins.

4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.

5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-

able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for

transmitter.

6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only.

7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.

55

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-128 Logic Signal Connections

sysIO

LVDS

GDX

SERDES Mode

I/O Cell²

FIFO Mode I/O

Cell/Pin³

208

fpBGA

Signal Name

Bank Pair/Polarity Block MRB

I/O Pin¹

TOE

-

P8

P9

BK0_IO0

BK0_IO1

0

0N

0P

0A

0

1

FIFO0A_FULL

-

T10

BK0_IO2 / PLL_LOCK2 /

PLL_RST2

0

1N

1P

0A

2

-

R10

BK0_IO3

GND

0

-

0A

-

3

-

HSI0A_SYDT⁵

-

FIFO0A_ EMPTY

-

T11

-

GND

BK0_IO4

BK0_IO5

BK0_IO6

BK0_IO7

BK0_IO8

BK0_IO9 / PLL_FB2

BK0_IO10

BK0_IO11

GND

2N

2P

3N

3P

4N

4P

5N

5P

0A

4

HSI0A_SINN

HSI0A_RXD0/TXD0 FIFO0A_DIN0/DOUT0 P10

HSI0A_RXD1/TXD1 FIFO0A_DIN1/DOUT1 N10

HSI0A_RXD2/TXD2 FIFO0A_DIN2/DOUT2 R11

HSI0A_RXD3/TXD3 FIFO0A_DIN3/DOUT3 T13

HSI0A_RXD4/TXD4 FIFO0A_DIN4/DOUT4 P11

HSI0A_RXD5/TXD5 FIFO0A_DIN5/DOUT5 R12

HSI0A_RXD6/TXD6 FIFO0A_DIN6/DOUT6 P12

HSI0A_RXD7/TXD7 FIFO0A_DIN7/DOUT7 N12

5

HSI0A_SINP

6

-

0A

-

7

-

8

Note 4

9

-

10

11

-

HSI0A_SOUTN

HSI0A_SOUTP

-

GND

BK0_IO12

BK0_IO13

BK0_IO14

BK0_IO15 / VREF0

GOE3

6N

6P

7N

7P

0A

-

12

13

-

HSI0A_RXD8/TXD8 FIFO0A_DIN8/DOUT8 T14

HSI0A_RXD9/TXD9 FIFO0A_DIN9/DOUT9 R13

HSI0A_SYDT⁵

14 HSI0A_CDRRSTb

HSI0A_RECCLK

FIFO0A_FIFORSTb

T15

P13

T9

15

-

FIFO0A_STRDb⁶

-

TDO

-

R16

GND

N14

GND

1

-

BK1_IO0 / VREF1

BK1_IO1

BK1_IO2

BK1_IO3

BK1_IO4

BK1_IO5

BK1_IO6

BK1_IO7

BK1_IO8

BK1_IO9

BK1_IO10

BK1_IO11

GND

8P

8N

0B

-

0

-

HSI0B_SYDT⁵

FIFO0B_FULL

1

-

HSI0B_RXD0/TXD0 FIFO0B_DIN0/DOUT0 P15

HSI0B_RXD1/TXD1 FIFO0B_DIN1/DOUT1 N15

HSI0B_RXD2/TXD2 FIFO0B_DIN2/DOUT2 L14

HSI0B_RXD3/TXD3 FIFO0B_DIN3/DOUT3 M14

HSI0B_RXD4/TXD4 FIFO0B_DIN4/DOUT4 M13

HSI0B_RXD5/TXD5 FIFO0B_DIN5/DOUT5 M15

HSI0B_RXD6/TXD6 FIFO0B_DIN6/DOUT6 L15

HSI0B_RXD7/TXD7 FIFO0B_DIN7/DOUT7 P16

HSI0B_RXD8/TXD8 FIFO0B_DIN8/DOUT8 N16

HSI0B_RXD9/TXD9 FIFO0B_DIN9/DOUT9 K14

9P

2

Note 4

9N

3

-

10P

10N

11P

11N

12P

12N

13P

13N

4

HSI0B_SOUTP

HSI0B_SOUTN

HSI0_CSLOCK

HSI0B_SYDT⁵

-

5

6

7

8

9

-

10

11

-

HSI0B_SINP

HSI0B_SINN

-

HSI0B_RECCLK

-

K13

GND

K15

L16

J14

J13

N8

-

BK1_IO12

BK1_IO13

BK1_IO14

BK1_IO15 / CLK_OUT2

GCLK/CE2

SEL2

14P

14N

15P

15N

0B

-

12

FIFO0B_STRDb⁶

-

13 HSI0B_CDRRSTb

-

FIFO0B_FIFORSTb

14

15

-

SS_CLKIN1P

-

SS_CLKIN1N

-

FIFO0B_ EMPTY

-

K16

G16

N9

SEL3

-

GCLK/CE3

BK2_IO0

BK2_IO1

BK2_IO2

-

2

16N

16P

17N

1A⁷

0

1

2

SS_CLKOUT1N

SS_CLKOUT1P

-

FIFO1A_FULL

H13

H14

G15

-

HSI1A_SYDT⁵

56

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-128 Logic Signal Connections (Continued)

sysIO

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

208

Signal Name

BK2_IO3

Bank Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

fpBGA

2

-

17P

1A⁷

-

3

-

HSI1A_RXD0/TXD0 FIFO1A_DIN0/DOUT0 F16

GND

-

BK2_IO4

BK2_IO5

BK2_IO6

BK2_IO7

BK2_IO8

BK2_IO9

BK2_IO10

BK2_IO11

GND

18N

18P

19N

19P

20N

20P

21N

21P

1A⁷

-

1A⁷

-

4

HSI1A_SINN

HSI1A_SINP

HSI1_CSLOCK

Note 4

HSI1A_RXD1/TXD1 FIFO1A_DIN1/DOUT1 G13

HSI1A_RXD2/TXD2 FIFO1A_DIN2/DOUT2 G14

HSI1A_RXD3/TXD3 FIFO1A_DIN3/DOUT3 F14

HSI1A_RXD4/TXD4 FIFO1A_DIN4/DOUT4 F15

HSI1A_RXD5/TXD5 FIFO1A_DIN5/DOUT5 D16

HSI1A_RXD6/TXD6 FIFO1A_DIN6/DOUT6 E15

HSI1A_RXD7/TXD7 FIFO1A_DIN7/DOUT7 E13

HSI1A_RXD8/TXD8 FIFO1A_DIN8/DOUT8 E14

5

6

7

8

CAL

9

-

10

11

-

HSI1A_SOUTN

HSI1A_SOUTP

-

GND

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15 / VREF2

TCK

22N

22P

23N

23P

12

HSI1A_SYDT⁵

HSI1A_RXD9/TXD9 FIFO1A_DIN9/DOUT9 C16

13 HSI1A_CDRRSTb

HSI1A_RECCLK

FIFO1A_FIFORSTb

D15

C15

D14

R14

A9

14

15

-

FIFO1A_STRDb⁶

-

FIFO1A_EMPTY

-

GOE2

-

BK3_IO0 / VREF3

BK3_IO1

BK3_IO2

BK3_IO3

GND

3

24P

24N

25P

25N

1B

0

1

2

3

-

HSI1B_RXD0/TXD0 FIFO1B_DIN0/DOUT0 C13

HSI1B_RXD1/TXD1 FIFO1B_DIN1/DOUT1 B14

HSI1B_RXD2/TXD2 FIFO1B_DIN2/DOUT2 A15

HSI1B_RXD3/TXD3 FIFO1B_DIN3/DOUT3 B13

Note 4

-

GND

BK3_IO4

BK3_IO5

BK3_IO6

BK3_IO7

26P

26N

27P

1B

4

5

6

HSI1B_SOUTP

HSI1B_SOUTN

-

HSI1B_RXD4/TXD4 FIFO1B_DIN4/DOUT4 D12

HSI1B_RXD5/TXD5 FIFO1B_DIN5/DOUT5 C12

HSI1B_RXD6/TXD6 FIFO1B_DIN6/DOUT6 A14

FIFO1B_DIN7/DOUT7

3

27N

1B

7

-

HSI1B_RXD7/TXD7

A13

/ FIFO1B_STRDb

BK3_IO8

BK3_IO9

BK3_IO10

BK3_IO11

GND

3

-

28P

28N

29P

29N

1B

-

8

9

-

HSI1B_RXD8/TXD8 FIFO1B_DIN8/DOUT8 B12

HSI1B_RXD9/TXD9 FIFO1B_DIN9/DOUT9 C11

HSI1B_SYDT⁵

10

11

-

HSI1B_SINP

HSI1B_RECCLK

-

D10

C10

GND

B11

B10

A10

C9

HSI1B_SINN

-

BK3_IO12

BK3_IO13

BK3_IO14

BK3_IO15

RESET

30P

30N

31P

31N

1B

-

12

HSI1B_SYDT⁵

FIFO1B_FULL

FIFO1B_FIFORSTb

-

13 HSI1B_CDRRSTb

-

14

15

-

FIFO1B_ EMPTY

-

A7

BK4_IO0

4

32N

32P

2A

0

FIFO2A_EMPTY

C8

BK4_IO1 / PLL_LOCK0 /

PLL_RST0

4

2A

1

-

B7

BK4_IO2

BK4_IO3

GND

4

33N

33P

2A

2

3

HSI2A_CDRRSTb

-

FIFO2A_FIFORSTb

A6

B6

-

HSI2A_SYDT⁵

FIFO2A_FULL

-

GND

C7

BK4_IO4

BK4_IO5

BK4_IO6

BK4_IO7

34N

34P

35N

35P

2A

4

5

6

7

HSI2A_SINN

HSI2A_SINP

HSI2A_SYDT⁵

-

HSI2A_RECCLK

D7

HSI2A_RXD9/TXD9 FIFO2A_DIN9/DOUT9 C6

HSI2A_RXD8/TXD8 FIFO2A_DIN8/DOUT8 B5

57

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-128 Logic Signal Connections (Continued)

sysIO

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

208

Signal Name

BK4_IO8

Bank Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

fpBGA

4

-

36N

36P

37N

37P

2A

8

9

FIFO2A_STRDb⁶

HSI2A_RXD7/TXD7 FIFO2A_DIN7/DOUT7 A4

HSI2A_RXD6/TXD6 FIFO2A_DIN6/DOUT6 A3

HSI2A_RXD5/TXD5 FIFO2A_DIN5/DOUT5 C5

HSI2A_RXD4/TXD4 FIFO2A_DIN4/DOUT4 D5

BK4_IO9 / PLL_FB0

BK4_IO10

BK4_IO11

GND

-

10

11

-

HSI2A_SOUTN

HSI2A_SOUTP

-

GND

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15 / VREF4

GOE1

38N

38P

39N

39P

2A

12

13

14

15

-

HSI2A_RXD3/TXD3 FIFO2A_DIN3/DOUT3 B4

HSI2A_RXD2/TXD2 FIFO2A_DIN2/DOUT2 A2

HSI2A_RXD1/TXD1 FIFO2A_DIN1/DOUT1 B3

HSI2A_RXD0/TXD0 FIFO2A_DIN0/DOUT0 C4

-

Note 4

-

A8

R1

TMS

-

GND

5

-

GND

D3

BK5_IO0 / VREF5

BK5_IO1

BK5_IO2

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

BK5_IO7

BK5_IO8

BK5_IO9

BK5_IO10

BK5_IO11

GND

40P

40N

41P

41N

42P

42N

43P

43N

44P

44N

45P

45N

2B

-

0

-

FIFO2B_EMPTY

-

1

FIFO2B_STRDb⁶

-

C2

2

HSI2B_CDRRSTb

HSI2B_SYDT⁵

HSI2B_RECCLK

FIFO2B_FIFORSTb

D2

3

HSI2B_RXD9/TXD9 FIFO2B_DIN9/DOUT9 B1

HSI2B_RXD8/TXD8 FIFO2B_DIN8/DOUT8 E3

HSI2B_RXD7/TXD7 FIFO2B_DIN7/DOUT7 E4

HSI2B_RXD6/TXD6 FIFO2B_DIN6/DOUT6 F3

HSI2B_RXD5/TXD5 FIFO2B_DIN5/DOUT5 E2

HSI2B_RXD4/TXD4 FIFO2B_DIN4/DOUT4 F2

HSI2B_RXD3/TXD3 FIFO2B_DIN3/DOUT3 C1

HSI2B_RXD2/TXD2 FIFO2B_DIN2/DOUT2 G3

HSI2B_RXD1/TXD1 FIFO2B_DIN1/DOUT1 G4

4

HSI2B_SOUTP

5

HSI2B_SOUTN

6

-

7

-

8

Note 4

9

HSI2_CSLOCK

10

11

-

HSI2B_SINP

HSI2B_SINN

-

GND

BK5_IO12

BK5_IO13

BK5_IO14

BK5_IO15 / CLK_OUT0

GCLK/CE0

SEL0

46P

46N

2B

-

12

13

14

15

-

HSI2B_RXD0/TXD0 FIFO2B_DIN0/DOUT0 D1

-

HSI2B_SYDT⁵

-

G2

H4

H3

D9

F1

47P

SS_CLKIN0P

-

47N

SS_CLKIN0N

-

FIFO2B_FULL

CLK0P

-

SEL1

-

G1

D8

J4

GCLK/CE1

BK6_IO0

BK6_IO1

BK6_IO2

BK6_IO3

GND

-

CLK0N

48N

-

6

3A

-

0

SS_CLKOUT0N

SS_CLKOUT0P

HSI3A_CDRRSTb

FIFO3A_STRDb⁶

-

FIFO3A_EMPTY

48P

1

-

J3

49N

2

-

FIFO3A_FIFORSTb

K1

K2

GND

K4

49P

3

-

BK6_IO4

BK6_IO5

BK6_IO6

BK6_IO7

BK6_IO8

BK6_IO9

BK6_IO10

BK6_IO11

50N

50P

51N

51P

52N

52P

53N

53P

3A

4

HSI3A_SINN

HSI3A_SINP

-

HSI3A_RECCLK

5

HSI3A_RXD9/TXD9 FIFO3A_DIN9/DOUT9 K3

HSI3A_RXD8/TXD8 FIFO3A_DIN8/DOUT8 L1

HSI3A_RXD7/TXD7 FIFO3A_DIN7/DOUT7 L2

HSI3A_RXD6/TXD6 FIFO3A_DIN6/DOUT6 N1

HSI3A_RXD5/TXD5 FIFO3A_DIN5/DOUT5 M2

HSI3A_RXD4/TXD4 FIFO3A_DIN4/DOUT4 M4

HSI3A_RXD3/TXD3 FIFO3A_DIN3/DOUT3 M3

6

7

-

8

HSI3A_SYDT⁵

HSI3_CSLOCK

HSI3A_SOUTN

HSI3A_SOUTP

9

10

11

58

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-128 Logic Signal Connections (Continued)

sysIO

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

208

fpBGA

Signal Name

Bank Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

GND

6

-

12

13

14

15

-

GND

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15 / VREF6

TDI

54N

54P

55N

55P

3A

-

HSI3A_RXD2/TXD2 FIFO3A_DIN2/DOUT2 L3

HSI3A_RXD1/TXD1 FIFO3A_DIN1/DOUT1 N2

HSI3A_RXD0/TXD0 FIFO3A_DIN0/DOUT0 P1

Note 4

-

HSI3A_SYDT⁵

FIFO3A_ FULL

P2

N3

-

GOE0

-

T8

GND

7

-

GND

T2

BK7_IO0 / VREF7

BK7_IO1

BK7_IO2

BK7_IO3

BK7_IO4

BK7_IO5

BK7_IO6

BK7_IO7

BK7_IO8

BK7_IO9

BK7_IO10

BK7_IO11

GND

56P

56N

57P

57N

58P

58N

59P

59N

60P

60N

61P

61N

3B

-

0

FIFO3B_STRDb⁶

-

1

HSI3B_CDRRSTb

HSI3B_SYDT⁵

HSI3B_RECCLK

FIFO3B_FIFORSTb

R3

2

HSI3B_RXD9/TXD9 FIFO3B_DIN9/DOUT9 P4

HSI3B_RXD8/TXD8 FIFO3B_DIN8/DOUT8 T3

HSI3B_RXD7/TXD7 FIFO3B_DIN7/DOUT7 N5

HSI3B_RXD6/TXD6 FIFO3B_DIN6/DOUT6 P5

HSI3B_RXD5/TXD5 FIFO3B_DIN5/DOUT5 R4

HSI3B_RXD4/TXD4 FIFO3B_DIN4/DOUT4 T4

HSI3B_RXD3/TXD3 FIFO3B_DIN3/DOUT3 R5

HSI3B_RXD2/TXD2 FIFO3B_DIN2/DOUT2 P6

HSI3B_RXD1/TXD1 FIFO3B_DIN1/DOUT1 N7

HSI3B_RXD0/TXD0 FIFO3B_DIN0/DOUT0 P7

3

-

4

HSI3B_SOUTP

5

HSI3B_SOUTN

6

-

7

Note 4

8

-

9

-

10

11

-

HSI3B_SINP

HSI3B_SINN

-

GND

R6

BK7_IO12

BK7_IO13

BK7_IO14

BK7_IO15

62P

62N

63P

63N

3B

12

13

14

15

HSI3B_SYDT⁵

FIFO3B_ EMPTY

-

T6

-

R7

FIFO3B_FULL

T7

1. The signals in this column route to/from the assigned pins of the associated I/O cell.

2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When

transmit data (TXD) is present in the cell, the associated pin is available for input only.

3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in

FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and

the pins.

4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.

5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-

able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for

transmitter.

6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only.

7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.

59

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

I/O Cell²

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

BK0_IO0

BK0_IO1

0

0N

0P

0A

0

1

-

FIFO0A_FULL

-

AB13

AA13

BK0_IO2/

PLL_LOCK2

0

1N

0A

2

-

V13

BK0_IO3

GND

0

1P

-

0A

-

3

-

FIFO0A_ EMPTY

-

V14

GND

U12

U13

W12

Y13

-

SYDT_HSI0A⁵

BK0_IO4

BK0_IO5

BK0_IO6

BK0_IO7

BK0_IO8

2N

2P

3N

3P

4N

0A

4

5

6

7

8

HSI0A_SINN

HSI0A_RXD0/TXD0

HSI0A_RXD1/TXD1

HSI0A_RXD2/TXD2

HSI0A_RXD3/TXD3

HSI0A_RXD4/TXD4

FIFO0A_DIN0/DOUT0

FIFO0A_DIN1/DOUT1

FIFO0A_DIN2/DOUT2

FIFO0A_DIN3/DOUT3

FIFO0A_DIN4/DOUT4

HSI0A_SINP

-

0A

-

Note 4

W13

BK0_IO9/

PLL_FB2

0

4P

0A

9

-

HSI0A_RXD5/TXD5

FIFO0A_DIN5/DOUT5

Y14

BK0_IO10

BK0_IO11

GND

0

5N

5P

-

0A

-

10

11

-

HSI0A_SOUTN

HSI0A_RXD6/TXD6

FIFO0A_DIN6/DOUT6

FIFO0A_DIN7/DOUT7

-

T12

T13

HSI0A_SOUTP

HSI0A_RXD7/TXD7

-

GND

AB14

AB15

Y15

BK0_IO12

BK0_IO13

BK0_IO14

BK0_IO15

BK0_IO16

6N

6P

7N

7P

8N

0A

1A

12

13

14

15

0

-

HSI0A_RXD8/TXD8

FIFO0A_DIN8/DOUT8

FIFO0A_DIN9/DOUT9

FIFO0A_FIFORSTb

-

HSI0A_SYDT⁵

HSI0A_CDRRSTb

FIFO0A_STRDb⁶

-

HSI0A_RXD9/TXD9

HSI0A_RECCLK

-

W15

AA15

FIFO1A_FULL

BK0_IO17/

PLL_RST2

0

8P

1A

1

-

AA16

BK0_IO18

BK0_IO19

GND

0

9N

9P

-

1A

-

2

3

-

HSI1A_SYDT⁵

HSI1A_RXD0/TXD0

-

Y16

W16

GND

U14

-

FIFO1A_DIN0/DOUT0

-

BK0_IO20

10N

1A

4

HSI1A_SOUTN

HSI1A_RXD1/TXD1

FIFO1A_DIN1/DOUT1

BK0_IO21/

VREF0

0

10P

1A

5

HSI1A_SOUTP

HSI1A_RXD2/TXD2

FIFO1A_DIN2/DOUT2

U15

BK0_IO22

BK0_IO23

BK0_IO24

BK0_IO25

BK0_IO26

BK0_IO27

BK0_IO28

BK0_IO29

BK0_IO30

BK0_IO31

GND

0

-

11N

11P

12N

12P

13N

13P

14N

14P

15N

15P

-

1A

-

6

7

-

HSI1A_RXD3/TXD3

FIFO1A_DIN3/DOUT3

AB16

AB17

AA17

W17

T14

Note 4

HSI1A_RXD4/TXD4

FIFO1A_DIN4/DOUT4

8

-

HSI1A_RXD5/TXD5

FIFO1A_DIN5/DOUT5

9

-

HSI1A_RXD6/TXD6

FIFO1A_DIN6/DOUT6

10

11

12

13

14

15

-

HSI1A_SINN

HSI1A_RXD7/TXD7

FIFO1A_DIN7/DOUT7

HSI1A_SINP

HSI1A_SYDT⁵

HSI1A_CDRRSTb⁵

FIFO1A_STRDb⁶

HSI1A_RXD8/TXD8

FIFO1A_DIN8/DOUT8

T15

HSI1A_RXD9/TXD9

FIFO1A_DIN9/DOUT9

AA18

AB18

W18

Y19

HSI1A_RECCLK

FIFO1A_FIFORSTb

-

FIFO1A_EMPTY

-

GND

AA19

AB19

GND

W21

W20

V22

GOE3

-

TDO

-

GND

1

-

BK1_IO0

BK1_IO1

BK1_IO2

BK1_IO3

BK1_IO4

16P

16N

17P

17N

18P

0B

0

-

FIFO0B_ FULL

-

1

-

HSI0B_SYDT⁵

HSI0B_RXD0/TXD0

HSI0B_RXD1/TXD1

HSI0B_RXD2/TXD2

2

FIFO0B_DIN0/DOUT0

FIFO0B_DIN1/DOUT1

FIFO0B_DIN2/DOUT2

3

Note 4

HSI0B_SINP

W22

P16

4

60

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

BK1_IO5

BK1_IO6

BK1_IO7

BK1_IO8

BK1_IO9

1

18N

19P

19N

20P

20N

0B

5

6

7

8

9

HSI0B_SINN

HSI0B_RXD3/TXD3

HSI0B_RXD4/TXD4

HSI0B_RXD5/TXD5

HSI0B_RXD6/TXD6

HSI0B_RXD7/TXD7

FIFO0B_DIN3/DOUT3

FIFO0B_DIN4/DOUT4

FIFO0B_DIN5/DOUT5

FIFO0B_DIN6/DOUT6

FIFO0B_DIN7/DOUT7

P17

U18

V19

V20

V21

HSI0_CSLOCK

-

HSI0B_SYDT⁵

BK1_IO10/

VREF1

1

21P

0B

10

HSI0B_SOUTP

HSI0B_RXD8/TXD8

FIFO0B_DIN8/DOUT8

R16

BK1_IO11

GND

1

21N

-

0B

-

11

-

HSI0B_SOUTN

HSI0B_RXD9/TXD9

FIFO0B_DIN9/DOUT9

R17

GND

U19

T19

U21

U22

R19

T20

T21

T22

GND

N16

N17

R20

R21

N19

P20

P18

N18

GND

R22

P22

M18

-

BK1_IO12

BK1_IO13

BK1_IO14

BK1_IO15

BK1_IO16

BK1_IO17

BK1_IO18

BK1_IO19

GND

22P

22N

23P

23N

24P

24N

25P

25N

-

0B

1B

-

12

13

14

15

0

HSI0B_CDRRSTb

FIFO0B_STRDb⁶

HSI0B_RECCLK

FIFO0B_FIFORSTb

-

FIFO0B_EMPTY

FIFO1B_FULL

FIFO1B_DIN0/DOUT0

FIFO1B_DIN1/DOUT1

FIFO1B_DIN2/DOUT2

-

HSI1B_SYDT⁵

HSI1B_RXD0/TXD0

HSI1B_RXD1/TXD1

HSI1B_RXD2/TXD2

-

1

-

2

Note 4

3

-

BK1_IO20

BK1_IO21

BK1_IO22

BK1_IO23

BK1_IO24

BK1_IO25

BK1_IO26

BK1_IO27

GND

26P

26N

27P

27N

28P

28N

29P

29N

1B

-

4

HSI1B_SOUTP

HSI1B_SOUTN

HSI1_CSLOCK

HSI1B_SYDT⁵

-

HSI1B_RXD3/TXD3

HSI1B_RXD4/TXD4

HSI1B_RXD5/TXD5

HSI1B_RXD6/TXD6

HSI1B_RXD7/TXD7

HSI1B_RXD8/TXD8

HSI1B_RXD9/TXD9

HSI1B_RECCLK

-

FIFO1B_DIN3/DOUT3

FIFO1B_DIN4/DOUT4

FIFO1B_DIN5/DOUT5

FIFO1B_DIN6/DOUT6

FIFO1B_DIN7/DOUT7

FIFO1B_DIN8/DOUT8

FIFO1B_DIN9/DOUT9

-

5

6

7

8

9

-

10

11

-

HSI1B_SINP

HSI1B_SINN

-

FIFO1B_STRDb⁶

HSI1B_CDRRSTb

SS_CLKIN1P

-

BK1_IO28

BK1_IO29

BK1_IO30

30P

30N

31P

1B

12

13

14

-

FIFO1B_FIFORSTb

-

BK1_IO31/

CLK_OUT2

1

31N

1B

15

SS_CLKIN1N

-

FIFO1B_EMPTY

M17

GCLK/CE2

SEL2

-

CLK2P

-

N20

N21

K21

K20

-

SEL3

-

GCLK/CE3

CLK2N

BK2_IO0/

CLK_OUT3

2

32N

3A⁷

0

SS_CLKOUT1N

-

FIFO3A_FULL

K17

BK2_IO1

BK2_IO2

BK2_IO3

GND

2

32P

33N

33P

3A⁷

-

3A⁷

1

2

3

-

SS_CLKOUT1P

-

K18

L17

L18

GND

J17

J18

J22

J20

H22

H21

-

HSI3A_SYDT⁵

-

HSI3A_RXD0/TXD0

-

FIFO3A_DIN0/DOUT0

-

HSI3A_SINN

HSI3A_SINP

HSI3_CSLOCK

Note 4

BK2_IO4

BK2_IO5

BK2_IO6

BK2_IO7

BK2_IO8

BK2_IO9

34N

34P

35N

35P

36N

36P

4

5

6

7

8

9

HSI3A_RXD1/TXD1

HSI3A_RXD2/TXD2

HSI3A_RXD3/TXD3

HSI3A_RXD4/TXD4

HSI3A_RXD5/TXD5

HSI3A_RXD6/TXD6

FIFO3A_DIN1/DOUT1

FIFO3A_DIN2/DOUT2

FIFO3A_DIN3/DOUT3

FIFO3A_DIN4/DOUT4

FIFO3A_DIN5/DOUT5

FIFO3A_DIN6/DOUT6

CAL

-

61

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

BK2_IO10

BK2_IO11

GND

2

37N

37P

-

3A⁷

-

10

11

-

HSI3A_SOUTN

HSI3A_RXD7/TXD7

FIFO3A_DIN7/DOUT7

K16

J16

HSI3A_SOUTP

HSI3A_RXD8/TXD8

FIFO3A_DIN8/DOUT8

-

GND

J19

BK2_IO12

BK2_IO13

BK2_IO14

BK2_IO15

BK2_IO16

BK2_IO17

BK2_IO18

BK2_IO19

GND

38N

38P

39N

39P

40N

40P

41N

41P

-

3A⁷

2A

-

12

13

14

15

0

HSI3A_SYDT⁵

HSI3A_RXD9/TXD9

FIFO3A_DIN9/DOUT9

HSI3A_CDRRSTb

FIFO3A_STRDb⁶

HSI3A_RECCLK

FIFO3A_FIFORSTb

H20

G21

G20

G22

F22

F20

F21

GND

-

FIFO3A_EMPTY

-

FIFO2A_FULL

1

-

HSI2A_SYDT⁵

HSI2A_RXD0/TXD0

HSI2A_RXD1/TXD1

-

2

-

FIFO2A_DIN0/DOUT0

FIFO2A_DIN1/DOUT1

-

3

Note 4

-

BK2_IO20/

PLL_FB3

2

42N

42P

2A

4

5

HSI2A_SOUTN

HSI2A_SOUTP

HSI2A_RXD2/TXD2

HSI2A_RXD3/TXD3

FIFO2A_DIN2/DOUT2

FIFO2A_DIN3/DOUT3

H18

G17

BK2_IO21/

VREF2

BK2_IO22

BK2_IO23

BK2_IO24

BK2_IO25

BK2_IO26

BK2_IO27

BK2_IO28

BK2_IO29

BK2_IO30

BK2_IO31

GND

2

-

43N

43P

44N

44P

45N

45P

46N

46P

47N

47P

-

2A

-

6

7

HSI2_CSLOCK

HSI2A_RXD4/TXD4

HSI2A_RXD5/TXD5

HSI2A_RXD6/TXD6

HSI2A_RXD7/TXD7

HSI2A_RXD8/TXD8

HSI2A_RXD9/TXD9

HSI2A_RECCLK

-

FIFO2A_DIN4/DOUT4

FIFO2A_DIN5/DOUT5

FIFO2A_DIN6/DOUT6

FIFO2A_DIN7/DOUT7

FIFO2A_DIN8/DOUT8

FIFO2A_DIN9/DOUT9

FIFO2A_FIFORSTb

-

E21

F19

E22

D22

H17

H16

E19

F18

D20

D21

GND

B19

C19

E17

D18

A19

A18

GND

G15

G14

D17

D16

C18

B18

-

8

-

9

HSI2A_SYDT⁵

10

11

12

13

14

15

-

HSI2A_SINN

HSI2A_SINP

HSI2A_CDRRSTb

FIFO2A_STRDb⁶

-

FIFO2A_EMPTY

-

TCK

-

GOE2

-

BK3_IO0

BK3_IO1

BK3_IO2

BK3_IO3

GND

3

48P

48N

49P

49N

-

3B

-

0

-

HSI3B_SYDT⁵

HSI3B_RXD0/TXD0

HSI3B_RXD1/TXD1

HSI3B_RXD2/TXD2

-

FIFO3B_FULL

1

-

FIFO3B_DIN0/DOUT0

FIFO3B_DIN1/DOUT1

FIFO3B_DIN2/DOUT2

-

2

Note 4

3

-

BK3_IO4

BK3_IO5

BK3_IO6

BK3_IO7

BK3_IO8

BK3_IO9

50P

50N

51P

51N

52P

52N

3B

4

HSI3B_SINP

HSI3B_RXD3/TXD3

HSI3B_RXD4/TXD4

HSI3B_RXD5/TXD5

HSI3B_RXD6/TXD6

HSI3B_RXD7/TXD7

HSI3B_RXD8/TXD8

FIFO3B_DIN3/DOUT3

FIFO3B_DIN4/DOUT4

FIFO3B_DIN5/DOUT5

FIFO3B_DIN6/DOUT6

FIFO3B_DIN7/DOUT7

FIFO3B_DIN8/DOUT8

5

HSI3B_SINN

6

-

7

HSI3B_SYDT⁵

8

-

9

BK3_IO10/

VREF3

3

53P

3B

10

HSI3B_SOUTP

HSI3B_RXD9/TXD9

FIFO3B_DIN9/DOUT9

F15

BK3_IO11

GND

3

53N

-

3B

-

11

-

HSI3B_SOUTN

-

FIFO3B_STRDb⁶

HSI3B_RECCLK

-

F14

GND

B17

A17

-

BK3_IO12

BK3_IO13

54P

54N

3B

12

13

-

HSI3B_CDRRSTb

HSI3B_RECCLK

FIFO3B_FIFORSTb

BK3_IO14/

PLL_RST3

3

55P

3B

14

-

A16

62

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

BK3_IO15

BK3_IO16

BK3_IO17

BK3_IO18

BK3_IO19

GND

3

55N

56P

56N

57P

57N

-

3B

2B

-

15

0

-

FIFO3B_EMPTY

FIFO2B_DIN0/DOUT0

FIFO2B_DIN1/DOUT1

FIFO2B_DIN2/DOUT2

FIFO2B_DIN3/DOUT3

-

C16

D15

D14

B16

C15

GND

G13

G12

B15

A15

C14

A14

F13

F12

GND

D13

C13

-

HSI2B_RXD0/TXD0

HSI2B_RXD1/TXD1

HSI2B_RXD2/TXD2

HSI2B_RXD3/TXD3

-

1

Note 4

2

-

3

-

BK3_IO20

BK3_IO21

BK3_IO22

BK3_IO23

BK3_IO24

BK3_IO25

BK3_IO26

BK3_IO27

GND

58P

58N

59P

59N

60P

60N

61P

61N

-

2B

-

4

HSI2B_SOUTP

HSI2B_RXD4/TXD4

HSI2B_RXD5/TXD5

HSI2B_RXD6/TXD6

HSI2B_RXD7/TXD7

HSI2B_RXD8/TXD8

HSI2B_RXD9/TXD9

HSI2B_RECCLK

-

FIFO2B_DIN4/DOUT4

FIFO2B_DIN5/DOUT5

FIFO2B_DIN6/DOUT6

FIFO2B_DIN7 /DOUT7

FIFO2B_DIN8/DOUT8

FIFO2B_DIN9/DOUT9

-

5

HSI2B_SOUTN

6

-

7

FIFO2B_STRDb⁶

8

-

HSI2B_SYDT⁵

HSI2B_SINP

HSI2B_SINN

-

9

10

11

-

BK3_IO28

BK3_IO29

62P

62N

2B

12

13

-

HSI2B_SYDT⁵

FIFO2B_FULL

HSI2B_CDRRSTb

-

FIFO2B_FIFORSTb

BK3_IO30/

3

63P

63N

2B

14

-

B13

PLL_LOCK3

BK3_IO31

RESETb

BK4_IO0

3

-

2B

-

15

-

FIFO2B_ EMPTY

A13

D12

A10

-

4

64N

64P

4A

0

FIFO4A_EMPTY

BK4_IO1/

PLL_LOCK0

4

4A

1

-

B10

BK4_IO2

BK4_IO3

GND

4

65N

65P

4A

2

3

HSI4A_CDRRSTb

-

FIFO4A_FIFORSTb

E11

E10

GND

F11

F10

C10

C9

-

HSI4A_SYDT⁵

FIFO4A_FULL

-

BK4_IO4

BK4_IO5

BK4_IO6

BK4_IO7

BK4_IO8

66N

66P

67N

67P

68N

4A

4

5

6

7

8

HSI4A_SINN

HSI4A_SINP

HSI4A_SYDT⁵

-

HSI4A_RECCLK

HSI4A_RXD9/TXD9

HSI4A_RXD8/TXD8

HSI4A_RXD7/TXD7

-

FIFO4A_DIN9/DOUT9

FIFO4A_DIN8/DOUT8

FIFO4A_DIN7 /DOUT7

FIFO4A_STRDb⁶

D10

BK4_IO9/

PLL_FB0

4

68P

4A

9

-

HSI4A_RXD6/TXD6

FIFO4A_DIN6/DOUT6

D9

BK4_IO10

BK4_IO11

GND

4

69N

69P

4A

10

11

-

HSI4A_SOUTN

HSI4A_RXD5/TXD5

HSI4A_RXD4/TXD4

-

FIFO4A_DIN5/DOUT5

FIFO4A_DIN4/DOUT4

-

G11

G10

GND

A9

HSI4A_SOUTP

-

BK4_IO12

BK4_IO13

BK4_IO14

BK4_IO15

BK4_IO16

70N

70P

71N

71P

72N

4A

5A

12

13

14

15

0

-

HSI4A_RXD3/TXD3

HSI4A_RXD2/TXD2

HSI4A_RXD1/TXD1

HSI4A_RXD0/TXD0

-

FIFO4A_DIN3/DOUT3

FIFO4A_DIN2/DOUT2

FIFO4A_DIN1/DOUT1

FIFO4A_DIN0/DOUT0

FIFO5A_EMPTY

-

C8

Note 4

B8

-

A8

B7

BK4_IO17/

PLL_RST0

4

72P

5A

1

-

C7

BK4_IO18

BK4_IO19

GND

4

73N

73P

-

5A

-

2

3

-

HSI5A_CDRRSTb

FIFO5A_STRDb⁶

-

FIFO5A_FIFORSTb

A7

B6

-

GND

F9

BK4_IO20

74N

5A

4

HSI5A_SOUTN

HSI5A_RECCLK

63

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

BK4_IO21/

VREF4

4

74P

5A

5

HSI5A_SOUTP

HSI5A_RXD9/TXD9

FIFO5A_DIN9/DOUT9

F8

BK4_IO22

BK4_IO23

BK4_IO24

BK4_IO25

BK4_IO26

BK4_IO27

BK4_IO28

BK4_IO29

BK4_IO30

BK4_IO31

GND

4

-

75N

75P

76N

76P

77N

77P

78N

78P

79N

79P

5A

-

6

7

-

HSI5A_RXD8/TXD8

HSI5A_RXD7/TXD7

HSI5A_RXD6/TXD6

HSI5A_RXD5/TXD5

HSI5A_RXD4/TXD4

HSI5A_RXD3/TXD3

HSI5A_RXD2/TXD2

HSI5A_RXD1/TXD1

HSI5A_RXD0/TXD0

HSI5A_SYDT⁵

-

FIFO5A_DIN8/DOUT8

FIFO5A_DIN7/DOUT7

FIFO5A_DIN6/DOUT6

FIFO5A_DIN5/DOUT5

FIFO5A_DIN4/DOUT4

FIFO5A_DIN3/DOUT3

FIFO5A_DIN2/DOUT2

FIFO5A_DIN1/DOUT1

FIFO5A_DIN0/DOUT0

FIFO5A_FULL

D7

D6

A6

A5

G9

G8

C5

B5

D5

C4

GND

B4

A4

GND

D2

D3

F5

-

8

HSI5A_SYDT⁵

9

-

10

11

12

13

14

15

-

HSI5A_SINN

HSI5A_SINP

-

Note 4

-

GOE1

-

TMS

-

GND

5

-

BK5_IO0

BK5_IO1

BK5_IO2

BK5_IO3

BK5_IO4

BK5_IO5

BK5_IO6

BK5_IO7

BK5_IO8

BK5_IO9

80P

80N

81P

81N

82P

82N

83P

83N

84P

84N

4B

0

-

FIFO4B_EMPTY

-

1

-

2

FIFO4B_STRDb⁶

HSI4B_CDRRSTb

HSI4B_SINP

HSI4B_SINN

HSI4B_SYDT⁵

-

3

HSI4B_RECCLK

HSI4B_RXD9/TXD9

HSI4B_RXD8/TXD8

HSI4B_RXD7/TXD7

HSI4B_RXD6/TXD6

HSI4B_RXD5/TXD5

HSI4_RXD4/TXD4

FIFO4B_FIFORSTb

FIFO4B_DIN9/DOUT9

FIFO4B_DIN8/DOUT8

FIFO4B_DIN7/DOUT7

FIFO4B_DIN6/DOUT6

FIFO4B_DIN5/DOUT5

FIFO4B_DIN4/DOUT4

E4

J7

4

5

J6

6

D1

E1

F4

7

8

-

9

HSI4_CSLOCK

E3

BK5_IO10/

VREF5

5

85P

4B

10

HSI4B_SOUTP

HSI4B_RXD3/TXD3

FIFO4B_DIN3/DOUT3

H7

BK5_IO11

GND

5

85N

-

4B

-

11

-

HSI4B_SOUTN

HSI4B_RXD2/TXD2

-

FIFO4B_DIN2/DOUT2

-

H6

GND

E2

-

BK5_IO12

BK5_IO13

BK5_IO14

BK5_IO15

BK5_IO16

BK5_IO17

BK5_IO18

BK5_IO19

GND

86P

86N

87P

87N

88P

88N

89P

89N

-

4B

5B

-

12

13

14

15

0

Note 4

HSI4B_RXD1/TXD1

HSI4B_RXD0/TXD0

HSI4B_SYDT⁵

-

FIFO4B_DIN1/DOUT1

FIFO4B_DIN0/DOUT0

-

F2

-

G4

H5

F1

-

FIFO4B_FULL

-

FIFO5B_EMPTY

-

1

FIFO5B_STRDb⁶

HSI5B_CDRRSTb

HSI5B_SYDT⁵

-

G1

G3

G2

GND

K7

2

HSI5B_RECCLK

HSI5B_RXD9/TXD9

-

FIFO5B_FIFORSTb

FIFO5B_DIN9/DOUT9

-

3

-

BK5_IO20

BK5_IO21

BK5_IO22

BK5_IO23

BK5_IO24

BK5_IO25

BK5_IO26

BK5_IO27

90P

90N

91P

91N

92P

92N

93P

93N

5B

4

HSI5B_SOUTP

HSI5B_SOUTN

-

HSI5B_RXD8/TXD8

HSI5B_RXD7/TXD7

HSI5B_RXD6/TXD6

HSI5B_RXD5/TXD5

HSI5B_RXD4/TXD4

HSI5B_RXD3/TXD3

HSI5B_RXD2/TXD2

HSI5B_RXD1/TXD1

FIFO5B_DIN8/DOUT8

FIFO5B_DIN7/DOUT7

FIFO5B_DIN6/DOUT6

FIFO5B_DIN5/DOUT5

FIFO5B_DIN4/DOUT4

FIFO5B_DIN3/DOUT3

FIFO5B_DIN2/DOUT2

FIFO5B_DIN1/DOUT1

5

K6

6

H4

H3

H1

H2

J5

7

-

8

Note 4

9

HSI5_CSLOCK

HSI5B_SINP

HSI5B_SINN

10

11

K5

64

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

GND

5

-

HSI5B_RXD0/TXD0

HSI5B_SYDT⁵

-

GND

J4

BK5_IO28

BK5_IO29

BK5_IO30

94P

94N

95P

5B

12

13

14

-

FIFO5B_DIN0/DOUT0

-

J3

SS_CLKIN0P

L6

BK5_IO31/

CLK_OUT0

5

95N

5B

15

SS_CLKIN0N

-

FIFO5B_FULL

L5

GCLK/CE0

SEL0

-

CLK0P

-

L4

K3

K2

N1

-

SEL1

-

GCLK/CE1

CLK0N

BK6_IO0/

CLK_OUT1

6

96N

7A

0

SS_CLKOUT0N

-

FIFO7A_EMPTY

N6

BK6_IO1

BK6_IO2

BK6_IO3

GND

6

96P

97N

97P

-

7A

-

1

2

SS_CLKOUT0P

-

N5

M5

M6

GND

P6

HSI7A_CDRRST

FIFO7A_STRDb⁶

-

FIFO7A_FIFORSTb

3

-

BK6_IO4

BK6_IO5

BK6_IO6

BK6_IO7

BK6_IO8

BK6_IO9

BK6_IO10

BK6_IO11

GND

98N

98P

99N

99P

100N

100P

101N

101P

-

7A

-

4

HSI7A_SINN

HSI7A_RECCLK

HSI7A_RXD9/TXD9

HSI7A_RXD8/TXD8

HSI7A_RXD7/TXD7

HSI7A_RXD6/TXD6

HSI7A_RXD5/TXD5

HSI7A_RXD4/TXD4

HSI7A_RXD3/TXD3

-

5

HSI7A_SINP

FIFO7A_DIN9/DOUT9

FIFO7A_DIN8/DOUT8

FIFO7A_DIN7/DOUT7

FIFO7A_DIN6/DOUT6

FIFO7A_DIN5/DOUT5

FIFO7A_DIN4/DOUT4

FIFO7A_DIN3/DOUT3

-

P5

6

-

N3

7

-

N2

8

HSI7A_SYDT⁵

P3

9

HSI7_CSLOCK

P1

10

11

-

HSI7A_SOUTN

N7

HSI7A_SOUTP

P7

-

GND

R3

BK6_IO12

BK6_IO13

BK6_IO14

BK6_IO15

BK6_IO16

BK6_IO17

BK6_IO18

BK6_IO19

GND

102N

102P

103N

103P

104N

104P

105N

105P

-

7A

6A

-

12

13

14

15

0

-

HSI7A_RXD2/TXD2

HSI7A_RXD1/TXD1

HSI7A_RXD0/TXD0

HSI7A_SYDT⁵

-

FIFO7A_DIN2/DOUT2

FIFO7A_DIN1/DOUT1

FIFO7A_DIN0/DOUT0

FIFO7A_ FULL

FIFO6A_EMPTY

-

Note 4

R2

-

R1

-

T1

-

T2

1

-

T3

2

FIFO6A_STRDb⁶

HSI6A_CDRRSTb

-

U1

3

HSI6_RECCLK

-

FIFO6A_FIFORSTb

-

U2

-

GND

BK6_IO20/

PLL_FB1

6

106N

106P

6A

4

5

HSI6A_SOUTN

HSI6A_RXD9/TXD9

HSI6A_RXD8/TXD8

FIFO6A_DIN9/DOUT9

FIFO6A_DIN8/DOUT8

R5

T6

BK6_IO21/

VREF6

HSI6A_SOUTP

BK6_IO22

BK6_IO23

BK6_IO24

BK6_IO25

BK6_IO26

BK6_IO27

BK6_IO28

BK6_IO29

BK6_IO30

BK6_IO31

6

107N

107P

108N

108P

109N

109P

110N

110P

111N

111P

6A

6

HSI6A_SYDT⁵

HSI6A_RXD7/TXD7

HSI6A_RXD6/TXD6

HSI6A_RXD5/TXD5

HSI6A_RXD4/TXD4

HSI6A_RXD3/TXD3

HSI6A_RXD2/TXD2

HSI6A_RXD1/TXD1

HSI6A_RXD0/TXD0

HSI6A_SYDT⁵

FIFO6A_DIN7/DOUT7

FIFO6A_DIN6/DOUT6

FIFO6A_DIN5/DOUT5

FIFO6A_DIN4/DOUT4

FIFO6A_DIN3/DOUT3

FIFO6A_DIN2/DOUT2

FIFO6A_DIN1/DOUT1

FIFO6A_DIN0/DOUT0

-

U4

V4

V3

V2

R6

R7

W1

V1

W2

W3

7

-

8

-

9

HSI6_CSLOCK

10

11

12

13

14

15

HSI6A_SINN

HSI6A_SINP

Note 4

-

FIFO6A_ FULL

65

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

GND

6

-

GND

AA4

Y4

TDI

-

GOE0

-

GND

7

-

GND

AB4

AB5

V6

BK7_IO0

BK7_IO1

BK7_IO2

BK7_IO3

BK7_IO4

BK7_IO5

BK7_IO6

BK7_IO7

BK7_IO8

BK7_IO9

112P

112N

113P

113N

114P

114N

115P

115N

116P

116N

7B

0

1

2

3

4

5

6

7

8

9

-

FIFO7B_ EMPTY

-

FIFO7B_STRDb⁶

-

HSI7B_CDRRSTb

HSI7B_SYDT⁵

HSI7B_RECCLK

HSI7B_RXD9/TXD9

HSI7B_RXD8/TXD8

HSI7B_RXD7/TXD7

HSI7B_RXD6/TXD6

HSI7B_RXD5/TXD5

HSI7B_RXD4/TXD4

HSI7B_RXD3/TXD3

FIFO7B_FIFORSTb

FIFO7B_DIN9/DOUT9

FIFO7B_DIN8/DOUT8

FIFO7B_DIN7/DOUT7

FIFO7B_DIN6/DOUT6

FIFO7B_DIN5/DOUT5

FIFO7B_DIN4/DOUT4

FIFO7B_DIN3/DOUT3

W5

T8

HSI7B_SINP

HSI7B_SINN

T9

-

W6

Y5

-

Note 4

-

AA5

AA6

BK7_IO10/

VREF7

7

117P

7B

10

HSI7B_SOUTP

HSI7B_RXD2/TXD2

FIFO7B_DIN2/DOUT2

U8

BK7_IO11

GND

7

117N

-

7B

-

11

-

HSI7B_SOUTN

HSI7B_RXD1/TXD1

-

FIFO7B_DIN1/DOUT1

U9

GND

W7

-

BK7_IO12

BK7_IO13

118P

118N

7B

12

13

HSI7B_RXD0/TXD0

HSI7B_SYDT⁵

FIFO7B_DIN0/DOUT0

-

W8

BK7_IO14/

PLL_RST1

7

119P

7B

14

-

AB6

BK7_IO15

BK7_IO16

BK7_IO17

BK7_IO18

BK7_IO19

GND

7

119N

120P

120N

121P

121N

-

7B

6B

-

15

0

-

FIFO7B_FULL

-

AB7

Y7

FIFO6B_STRDb⁶

-

1

HSI6B_CDRRSTb

HSI6B_SYDT⁵

HSI6B_RECCLK

HSI6B_RXD9/TXD9

HSI6B_RXD8/TXD8

-

FIFO6B_FIFORSTb

FIFO6B_DIN9/DOUT9

FIFO6B_DIN8/DOUT8

-

AA7

W9

2

3

-

Y8

-

GND

T10

T11

AA8

AB8

W10

Y9

BK7_IO20

BK7_IO21

BK7_IO22

BK7_IO23

BK7_IO24

BK7_IO25

BK7_IO26

BK7_IO27

GND

122P

122N

123P

123N

124P

124N

125P

125N

-

6B

-

4

HSI6B_SOUTP

HSI6B_RXD7/TXD7

HSI6B_RXD6/TXD6

HSI6B_RXD5/TXD5

HSI6B_RXD4/TXD4

HSI6B_RXD3/TXD3

HSI6B_RXD2/TXD2

HSI6B_RXD1/TXD1

HSI6B_RXD0/TXD0

-

FIFO6B_DIN7/DOUT7

FIFO6B_DIN6/DOUT6

FIFO6B_DIN5/DOUT5

FIFO6B_DIN4/DOUT4

FIFO6B_DIN3/DOUT3

FIFO6B_DIN2/DOUT2

FIFO6B_DIN1/DOUT1

FIFO6B_DIN0/DOUT0

-

5

HSI6B_SOUTN

6

-

7

-

8

Note 4

9

-

10

11

-

HSI6B_SINP

U10

U11

GND

W11

HSI6B_SINN

-

BK7_IO28

126P

6B

12

HSI6B_SYDT⁵

FIFO6B_ EMPTY

BK7_IO29/

PLL_LOCK1

7

126N

6B

13

-

Y10

BK7_IO30

BK7_IO31

7

127P

127N

6B

14

15

-

AA10

AB9

FIFO6B_FULL

66

Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2-256 Logic Signal Connections (Continued)

Signal

Name

sysIO

Bank

LVDS

GDX

SERDES Mode

FIFO Mode I/O

Cell/Pin³

484

fpBGA

Pair/Polarity Block MRB

I/O Pin¹

I/O Cell²

TOE

-

AB10

1. The signals in this column route to/from the assigned pins of the associated I/O cell.

2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When

transmit data (TXD) is present in the cell, the associated pin is available for input only.

3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in

FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY ﬂags are routed to the associated pins through the output MUX and

the pins.

4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.

5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-

able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for

transmitter.

6. FIFO_STRDb ﬂag output is used in SERDES with FIFO Mode only.

7. sysHSI Source Synchronous Receive Mode is not available for channel 3A.

67

Lattice Semiconductor

ispGDX2 Family Data Sheet

Part Number Description

LX XXX X X – XX FXXX X

Device Family

Grade

C = Commercial

I = Industrial

LX

Device Number

64 = 64 I/Os

Package

F100 = 100-Ball fpBGA

FN100 = Lead-Free 100-Ball fpBGA

F208 = 208-Ball fpBGA

FN208 = Lead-Free 208-Ball fpBGA

F484 = 484-Ball fpBGA

FN484 = Lead-Free 484-Ball fpBGA

128 = 128 I/Os

256 = 256 I/Os

sysHSI Support

Blank = Supports sysHSI

E = No sysHSI support

Power Supply Voltage

V = 3.3V

B = 2.5V

Speed

3 = 3.0ns

32 = 3.2ns

35 = 3.5ns

5 = 5.0ns

C = 1.8V

Ordering Information

Conventional Packaging

Commercial

Family

LX64V

Part Number

LX64V-3F100C

LX64V-5F100C

LX128V-32F208C

LX128V-5F208C

LX256V-35F484C

LX256V-5F484C

LX64B-3F100C

LX64B-5F100C

LX128B-32F208C

LX128B-5F208C

LX256B-35F484C

LX256B-5F484C

LX64C-3F100C

LX64C-5F100C

LX128C-32F208C

LX128C-5F208C

LX256C-35F484C

LX256C-5F484C

I/Os

64

Voltage

t

Package

fpBGA

Pins

100

208

484

100

208

484

100

208

484

Grade

C

PD

3.3

2.5

1.8

3

64

5

C

128

256

64

3.2

5

C

LX128V

LX256V

LX64B

C

3.5

5

C

3

C

64

5

C

128

256

64

3.2

5

C

LX128B

LX256B

LX64C

C

3.5

5

C

3

C

64

5

C

128

256

3.2

5

C

LX128C

LX256C

C

3.5

5

C

68

Lattice Semiconductor

ispGDX2 Family Data Sheet

“E-Series” Commercial

Family

Part Number

LX64EV-3F100C

LX64EV-5F100C

LX128EV-32F208C

LX128EV-5F208C

LX256EV-35F484C

LX256EV-5F484C

LX64EB-3F100C

LX64EB-5F100C

LX128EB-32F208C

LX128EB-5F208C

LX256EB-35F484C

LX256EB-5F484C

LX64EC-3F100C

LX64EC-5F100C

LX128EC-32F208C

LX128EC-5F208C

I/Os

64

Voltage

3.3

2.5

1.8

t

Package

fpBGA

Pins

100

208

484

100

208

484

100

208

Grade

C

PD

3

LX64EV

64

5

C

128

256

64

3.2

5

C

LX128EV

LX256EV

LX64EB

C

3.5

5

C

3

C

64

5

C

128

256

64

3.2

5

C

LX128EB

LX256EB

LX64EC

LX128EC

C

3.5

5

C

3

C

64

5

C

128

3.2

5

C

“E-Series” Industrial

Family

Part Number

I/Os

64

Voltage

3.3

t

Package

fpBGA

Pins

100

208

484

Grade

PD

LX64EV LX64EV-5F100I

LX64EB LX64EB-5F100I

LX64EC LX64EC-5F100I

LX128EV LX128EV-5F208I

LX128EB LX128EB-5F208I

LX128EC LX128EC-5F208I

LX256EV LX256EV-5F484I

LX256EB LX256EB-5F484I

LX256EC LX256EC-5F484I

5

I

64

2.5

5

64

1.8

128

256

3.3

2.5

1.8

3.3

2.5

1.8

69

Lattice Semiconductor

ispGDX2 Family Data Sheet

Lead-Free Packaging

Commercial

Family

LX64V

Part Number

LX64V-3FN100C

LX64V-5FN100C

LX64B-3FN100C

LX64B-5FN100C

LX64C-3FN100C

LX64C-5FN100C

LX128V-32FN208C

LX128V-5FN208C

LX128B-32FN208C

LX128B-5FN208C

LX128C-32FN208C

LX128C-5FN208C

LX256V-35FN484C

LX256V-5FN484C

LX256B-35FN484C

LX256B-5FN484C

LX256C-35FN484C

LX256C-5FN484C

I/Os

64

Voltage

3.3

2.5

1.8

3.3

2.5

1.8

3.3

2.5

1.8

t

Package

Pins

100

208

484

Grade

C

PD

3.0

5.0

3.0

5.0

3.0

5.0

3.2

5.0

3.2

5.0

3.2

5.0

3.5

5.0

3.5

5.0

3.5

5.0

Lead-free fpBGA

64

C

64

C

LX64B

64

C

64

C

LX64C

64

C

128

256

C

LX128V

LX128B

LX128C

LX256V

LX256B

LX256C

C

“E-Series” Commercial

Family

Part Number

LX64EV-3FN100C

LX64EV-5FN100C

LX64EB-3FN100C

LX64EB-5FN100C

LX64EC-3FN100C

LX64EC-5FN100C

LX128EV-32FN208C

LX128EV-5FN208C

LX128EB-32FN208C

LX128EB-5FN208C

LX128EC-32FN208C

LX128EC-5FN208C

LX256EV-35FN484C

LX256EV-5FN484C

LX256EB-35FN484C

LX256EB-5FN484C

LX256EC-35FN484C

LX256EC-5FN484C

I/Os

64

Voltage

3.3

2.5

1.8

3.3

2.5

1.8

3.3

2.5

1.8

t

Package

Pins

100

208

484

Grade

C

PD

3.0

5.0

3.0

5.0

3.0

5.0

3.2

5.0

3.2

5.0

3.2

5.0

3.5

5.0

3.5

5.0

3.5

5.0

Lead-free fpBGA

LX64EV

64

C

64

C

LX64EB

64

C

64

C

LX64EC

LX128EV

LX128EB

LX128EC

LX256EV

LX256EB

LX256EC

64

C

128

256

C

70

Lattice Semiconductor

ispGDX2 Family Data Sheet

“E-Series” Industrial

Family

LX64EV

Part Number

LX64EV-5FN100I

LX64EB-5FN100I

LX64EC-5FN100I

LX128EV-5FN208I

LX128EB-5FN208I

LX128EC-5FN208I

LX256EV-5FN484I

LX256EB-5FN484I

LX256EC-5FN484I

I/Os

64

Voltage

3.3

t

Package

Pins

100

208

484

Grade

PD

5.0

Lead-free fpBGA

I

LX64EB

64

2.5

LX64EC

LX128EV

LX128EB

LX128EC

LX256EV

LX256EB

LX256EC

64

1.8

128

256

3.3

2.5

1.8

3.3

2.5

1.8

71

Lattice Semiconductor

ispGDX2 Family Data Sheet

For Further Information

In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispGDX2

Family:

• sysIO Design and Usage Guidelines (TN1000)

• sysCLOCK PLL Design and Usage Guidelines (TN1003)

• sysHSI Usage Guide (TN1020)

• Power Estimation in ispGDX2 Devices (TN1021)

72


型号：	LX128BIFN10032
厂家：	LATTICE SEMICONDUCTOR
描述：	High Performance Interfacing and Switching 高性能接口和开关开关
文件：	总72页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LX128BIFN10032 [LATTICE]

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