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M4A5-128/64-7VC [LATTICE]

High Performance E 2 CMOS In-System Programmable Logic; 高性能e 2的CMOS在系统可编程逻辑
M4A5-128/64-7VC
型号： M4A5-128/64-7VC
厂家： LATTICE SEMICONDUCTOR    LATTICE SEMICONDUCTOR
描述：

High Performance E 2 CMOS In-System Programmable Logic
高性能e 2的CMOS在系统可编程逻辑

可编程逻辑器件 输入元件 时钟
文件： 总62页 (文件大小：1140K)
中文：  中文翻译
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ispMACH™ 4A CPLD Family  
High Performance E2CMOS®  
In-System Programmable Logic  
FEATURES  
2
  High-performance, E CMOS 3.3-V & 5-V CPLD families  
  Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit  
— SpeedLocking  
and refit feature  
TM  
performance for guaranteed fixed timing  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
  High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
  32 to 512 macrocells; 32 to 768 registers  
  44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages  
  Flexible architecture for a w ide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
2
  Advanced E CMOS process provides high-performance, cost-effective solutions  
TM  
  Supported by ispDesignEXPERT softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for ispMACH 4A  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and third-party hardw are programming support  
TM  
— LatticePRO  
equipment  
software for in-system programmability support on PCs and automated test  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# ISPM4A Rev: D  
Amendment/0  
Issue Date: August 2000  
Table 1. ispMACH 4A Device Features  
3.3 V Devices  
Feature  
2
2
2
2
2
2
1
M4A3-32  
32  
M4A3-64  
M4A3-96  
96  
M4A3-128  
128  
64  
M4A3-192  
192  
96  
M4A3-256  
M4A3-384  
384  
M4A3-512  
Macrocells  
64  
256  
512  
1
2
1
1
User I/O options  
32  
32/64  
48  
128 /160 /192  
160/192  
6.5  
160/192/256  
3
t
(ns)  
5.0  
5.5  
167  
4.0  
3.5  
5.5  
5.5  
6.0  
5.5  
7.5  
125  
5.5  
5.0  
179  
Yes  
Yes  
PD  
f
(MHz)  
(ns)  
182  
4.0  
167  
4.0  
167  
4.0  
160  
4.5  
167  
4.0  
3.5  
154  
CNT  
t
4.5  
COS  
t
(ns)  
3.0  
3.5  
3.5  
3.5  
3.5  
SS  
1
2
1
Static Power (mA)  
JTAG Compliant  
PCI Compliant  
20  
25/52  
40  
55  
85  
110 /150  
Yes  
149/155  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
5 V Devices  
Feature  
2
2
2
2
1
2
M4A5-32  
32  
M4A5-64  
64  
M4A5-96  
96  
M4A5-128  
128  
64  
M4A5-192  
192  
96  
M4A5-256  
256  
Macrocells  
User I/O options  
32  
32  
48  
128  
t
(ns)  
5.0  
5.5  
5.5  
5.5  
6.0  
6.5  
PD  
f
(MHz)  
(ns)  
182  
4.0  
167  
4.0  
167  
4.0  
167  
4.0  
160  
4.5  
154  
CNT  
t
5.0  
COS  
t
(ns)  
3.0  
3.5  
3.5  
3.5  
3.5  
3.5  
SS  
Static Power (mA)  
JTAG Compliant  
PCI Compliant  
20  
25  
40  
55  
74  
110  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Notes:  
1. Advance information. Please contact a Lattice sales representative for details on availability.  
2. Preliminary information.  
3. M4A3-256/ 128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/ 160 and M4A3-256/ 192  
2
ispMACH 4A Family  
GENERAL DESCRIPTION  
™
The ispMACH 4A family from Lattice offers an exceptionally flexible architecture and delivers  
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products  
and software tools. The overall benefits for users are a guaranteed and predictable CPLD  
solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer  
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.  
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.  
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std.  
1149.1) interface. JTAG boundary scan testing also allows product testability on automated test  
equipment for device connectivity.  
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out  
retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A  
products can deliver guaranteed fixed timing as fast as 5.0 ns t and 182 MHz f  
through the  
PD  
CNT  
SpeedLocking feature when using up to 20 product terms per output (Table 2).  
Table 2. ispMACH 4A Speed Grades  
Speed Grade  
Device  
-5  
-55  
-6  
-65  
-7  
-10  
-12  
-14  
3
M4A3-32  
C
C, I  
C, I  
I
3
M4A5-32  
3
M4A3-64/32  
C
C
C
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
I
I
I
3
M4A5-64/32  
2
M4A3-64/64  
3
M4A3-96  
3
M4A5-96  
3
M4A3-128  
C
C, I  
C, I  
C, I  
C, I  
I
I
3
M4A5-128  
3
M4A3-192  
C
2
M4A5-192  
3
M4A3-256/128  
C
C
C
C, I  
C
C, I  
C, I  
I
I
3
M4A5-256/128  
2
M4A3-256/192  
C
C, I  
I
2
M4A3-256/160  
2
M4A3-384  
C
C, I  
C, I  
C, I  
C, I  
I
I
2
M4A3-512  
C
Notes:  
1. C = Commercial, I = Industrial  
2. Advance information. Please contact a Lattice sales representative for details on availability.  
3. Preliminary information.  
ispMACH 4A Family  
3
The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP),  
Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-  
pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table  
3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept  
5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-  
Friendly inputs and I/Os, a programmable power-down mode for extra power savings and  
individual output slew rate control for the highest speed transition or for the lowest noise  
transition.  
Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)  
3.3 V Devices  
2
2
1
1
Package  
44-pin PLCC  
M4A3-32  
32+2  
M4A3-64  
M4A3-96  
M4A3-128  
M4A3-192  
M4A3-256  
M4A3-384  
M4A3-512  
2
32+2  
2
44-pin TQFP  
32+2  
32+2  
2
48-pin TQFP  
32+2  
32+2  
1
2
100-pin TQFP  
100-pin PQFP  
100-ball caBGA  
144-pin TQFP  
144-ball fpBGA  
208-pin PQFP  
256-ball fpBGA  
256-ball BGA  
388-ball fpBGA  
64+6  
48+8  
64+6  
2
64+6  
1
64+6  
2
96+16  
1
96+16  
2
1
128+14 , 160  
160  
192  
192  
160  
192  
2
1
128+14 , 192  
2
128+14  
256  
5 V Devices  
2
2
2
2
1
2
Package  
44-pin PLCC  
44-pin TQFP  
48-pin TQFP  
100-pin TQFP  
100-pin PQFP  
144-pin TQFP  
208-pin PQFP  
256-ball BGA  
M4A5-32  
32+2  
M4A5-64  
32+2  
M4A5-96  
M4A5-128  
M4A5-192  
M4A5-256  
32+2  
32+2  
32+2  
32+2  
48+8  
64+6  
64+6  
96+16  
128+14  
128+14  
Note:  
1. Advance information. Please contact a Lattice sales representative for details on availability.  
2. Preliminary information.  
4
ispMACH 4A Family  
FUNCTIONAL DESCRIPTION  
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized  
®
PAL blocks interconnected by a central switch matrix. The central switch matrix allows  
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL  
blocks and central switch matrix allow the logic designer to create large designs in a single  
device instead of having to use multiple devices.  
The key to being able to make effective use of these devices lies in the interconnect schemes.  
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms  
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the  
output switch matrix. In addition, more input routing options are provided by the input switch  
matrix. These resources provide the flexibility needed to fit designs efficiently.  
PAL Block  
4
Note 2  
Clock  
Generator  
Clock/Input  
Pins  
33/  
34/  
36  
Note 3  
I/O  
Pins  
16  
16  
8
Logic  
Allocator  
with XOR  
Output/  
Buried  
Macrocells  
Logic  
Array  
Note 1  
Dedicated  
Input Pins  
16  
Input  
Switch  
Matrix  
16  
I/O  
Pins  
PAL Block  
PAL Block  
I/O  
Pins  
17466G-001  
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure  
Notes:  
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/ O cell ratio (see next page).  
2. Block clocks do not go to I/ O cells in M4A(3,5)-32/ 32.  
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do  
not connect to the central switch matrix.  
ispMACH 4A Family  
5
Table 4. Architectural Summary of ispMACH 4A devices  
ispMACH 4A Devices  
M4A3-64/32, M4A5-64/32  
M4A3-96/48, M4A5-96/48  
M4A3-128/64, M4A5-128/64  
M4A3-192/96, M4A5-192/96  
M4A3-256/128, M4A5-256/128  
M4A3-384  
M4A3-32/32  
M4A5-32/32  
M4A3-64/64  
M4A3-256/160  
M4A3-256/192  
M4A3-512  
Macrocell-I/O Cell  
Ratio  
2:1  
1:1  
1
Input Switch Matrix  
Input Registers  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
Yes  
Yes  
Central Switch Matrix  
Output Switch Matrix  
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O  
cells internally in a PAL block (Table 4).  
The central switch matrix takes all dedicated inputs and signals from the input switch matrices  
and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block  
still must go through the central switch matrix. This mechanism ensures that PAL blocks in  
ispMACH 4A devices communicate with each other with consistent, predictable delays.  
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL  
devices on a single chip. It allows the designer to think of the device not as a collection of  
blocks, but as a single programmable device; the software partitions the design into PAL blocks  
through the central switch matrix so that the designer does not have to be concerned with the  
internal architecture of the device.  
Each PAL block consists of:  
  Product-term array  
  Logic allocator  
  Macrocells  
  Output switch matrix  
  I/O cells  
  Input switch matrix  
  Clock generator  
Notes:  
1. M4A3-64/ 64 internal switch matrix functionality embedded in central switch matrix.  
6
ispMACH 4A Family  
Product-Term Array  
The product-term array consists of a number of product terms that form the basis of the logic  
being implemented. The inputs to the AND gates come from the central switch matrix (Table 5),  
and are provided in both true and complement forms for efficient logic implementation.  
Table 5. PAL Block Inputs  
Device  
Number of Inputs to PAL Block  
M4A3-32/32 and M4A5-32/32  
M4A3-64/32 and M4A5-64/32  
M4A3-64/64  
33  
33  
33  
33  
33  
M4A3-96/48 and M4A5-96/48  
M4A3-128/64 and M4A5-128/64  
M4A3-192/96 and M4A5-192/96  
M4A3-256/128 and M4A5-256/128  
34  
34  
M4A3-256/160 and M4A3-256/192  
M4A3-384  
36  
36  
36  
M4A3-512  
Logic Allocator  
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”  
The availability and distribution of product term clusters are automatically considered by the  
software as it fits functions within a PAL block. The size of a product term cluster has been  
optimized to provide high utilization of product terms, making complex functions using many  
product terms possible. Yet when few product terms are used, there will be a minimal number  
of unused—or wasted—product terms left over. The product term clusters available to each  
macrocell within a PAL block are shown in Tables 6 and 7.  
Each product term cluster is associated with a macrocell. The size of a cluster depends on the  
configuration of the associated macrocell. When the macrocell is used in synchronous mode  
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in  
asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term  
cluster is routed to a different macrocell, the allocator configuration is not determined by the  
mode of the macrocell actually being driven. The configuration is always set by the mode of the  
macrocell that the cluster will drive if not routed away, regardless of the actual routing.  
In addition, there is an extra product term that can either join the basic cluster to give an  
extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included  
with the basic cluster, this provides for up to 20 product terms on a synchronous function that  
uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18  
product terms.  
When the extra product term is used to extend the cluster, the value of the second XOR input  
can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic  
allocator are shown in Figures 3 and 4.  
ispMACH 4A Family  
7
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)  
Output Macrocell  
Available Clusters  
C , C , C  
Output Macrocell  
Available Clusters  
C , C , C , C  
M
M
8
0
0
1
2
7
8
9
10  
M
C , C , C , C  
M
C , C , C , C  
8 9 10 11  
1
0
1
2
3
9
M
C , C , C , C  
M
C , C , C , C  
9 10 11 12  
2
1
2
3
4
10  
M
C , C , C , C  
M
C , C , C , C  
10 11 12 13  
3
2
3
4
5
11  
M
C , C , C , C  
M
C , C , C , C  
11 12 13 14  
4
3
4
5
6
12  
M
C , C , C , C  
M
C , C , C , C  
12 13 14 15  
5
4
5
6
7
13  
M
C , C , C , C  
M
C , C , C  
13 14 15  
6
5
6
7
8
14  
M
C , C , C , C  
M
C , C  
7
6
7
8
9
15  
14 15  
Table 7. Logic Allocator for M4A(3,5)-32/32  
Output Macrocell  
Available Clusters  
C , C , C  
Output Macrocell  
Available Clusters  
M
M
C , C , C  
8 9 10  
0
0
1
2
8
M
C , C , C , C  
M
C , C , C , C  
8 9 10 11  
1
0
1
2
3
9
M
C , C , C , C  
M
C , C , C , C  
9 10 11 12  
2
1
2
3
4
10  
M
C , C , C , C  
M
C , C , C , C  
10 11 12 13  
3
2
3
4
5
11  
M
C , C , C , C  
M
C , C , C , C  
11 12 13 14  
4
3
4
5
6
12  
M
C , C , C , C  
M
C , C , C , C  
12 13 14 15  
5
4
5
6
7
13  
M
C , C , C  
M
C , C , C  
13 14 15  
6
5
6
7
14  
M
C , C  
M
C , C  
14 15  
7
6
7
15  
Logic Allocator  
Basic Product  
Term Cluster  
n
n
0 Default  
0 Default  
Extra  
Product  
Term  
Prog. Polarity  
17466G-005  
a. Synchronous Mode  
Logic Allocator  
Basic Product  
Term Cluster  
n
n
0 Default  
0 Default  
Extra  
Product  
Term  
Prog. Polarity  
b. Asynchronous Mode  
17466G-006  
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”  
8
ispMACH 4A Family  
a. Basic cluster w ith XOR  
b. Extended cluster, active high  
c. Extended cluster, active low  
0
d. Basic cluster routed aw ay;  
single-product-term, active high  
e. Extended cluster routed aw ay  
17466G-007  
Figure 3. Logic Allocator Configurations: Synchronous Mode  
a. Basic cluster w ith XOR  
b. Extended cluster, active high  
c. Extended cluster, active low  
0
d. Basic cluster routed aw ay;  
single-product-term, active high  
e. Extended cluster routed aw ay  
17466G-008  
Figure 4. Logic Allocator Configurations: Asynchronous Mode  
Note that the configuration of the logic allocator has absolutely no impact on the speed of the  
signal. All configurations have the same delay. This means that designers do not have to decide  
between optimizing resources or speed; both can be optimized.  
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to  
provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-  
flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to  
another macrocell, the extra product term is still available for logic. In this case, the first XOR  
input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without  
giving up the use of the macrocell.  
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the  
ends of the block have fewer product terms available.  
ispMACH 4A Family  
9
Macrocell  
The macrocell consists of a storage element, routing resources, a clock multiplexer, and  
initialization control. The macrocell has two fundamental modes: synchronous and  
asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the  
macrocell.  
Power-Up  
Reset  
PAL-Block  
Initialization  
Product Terms  
SWAP  
Common PAL-block resource  
Individual macrocell resources  
To Output and Input  
Switch Matrices  
AP  
AR  
From Logic Allocator  
Q
D/T/L  
Block CLK0  
Block CLK1  
Block CLK2  
Block CLK3  
From  
PAL-Clock  
Generator  
17466G-009  
a. Synchronous mode  
Power-Up  
Reset  
Individual  
Initialization  
Product Term  
To Output and Input  
Switch Matrices  
AP  
AR  
From Logic  
Allocator  
Q
D/T/L  
Block CLK0  
Block CLK1  
From PAL-Block  
Clock Generator  
Individual Clock  
Product Term  
b. Asynchronous mode  
Figure 5. Macrocell  
17466G-010  
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous  
mode will generally be used, since it provides more product terms in the allocator.  
10  
ispMACH 4A Family  
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be  
synthesized. The primary flip-flop configurations are shown in Figure 6, although others are  
possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will  
cause oscillation if both J and K inputs are HIGH.  
AP AR  
AP AR  
D
Q
D
Q
b. D-type w ith programmable D polarity  
a. D-type w ith XOR  
AP AR  
AP AR  
L
Q
L
Q
G
G
c. Latch w ith XOR  
d. Latch w ith programmable D polarity  
AP AR  
T
Q
f. Combinatorial w ith XOR  
e. T-type w ith programmable T polarity  
g. Combinatorial w ith programmable polarity  
17466G-011  
Figure 6. Primary Macrocell Configurations  
ispMACH 4A Family  
11  
Table 8. Register/Latch Operation  
1
Configuration  
Input(s)  
CLK/LE  
Q+  
D=X  
D=0  
D=1  
0,1, ↓ (↑)  
↑ (↓)  
Q
0
D-type Register  
T-type Register  
↑ (↓)  
1
T=X  
T=0  
T=1  
0, 1, ↓ (↑)  
↑ (↓)  
Q
Q
Q
↑ (↓)  
D=X  
D=0  
D=1  
1(0)  
0(1)  
0(1)  
Q
0
D-type Latch  
1
Note:  
1. Polarity of CLK/ LE can be programmed  
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator  
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product  
terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the  
extra product term must be used on the XOR gate input for flip-flop emulation. In any register  
type, the polarity of the inputs can be programmed.  
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode,  
with the additional choice of either polarity of an individual product term clock in the  
asynchronous mode.  
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous  
reset and preset are provided, each driven by a product term common to the entire PAL block.  
Power-Up  
Reset  
Power-Up  
Preset  
PAL-Block  
PAL-Block  
Initialization  
Initialization  
Product Terms  
Product Terms  
AR  
Q
AP  
D/T/L  
AR  
Q
AP  
D/L  
a. Pow er-up reset  
b. Pow er-up preset  
17466G-012  
17466G-013  
Figure 7. Synchronous Mode Initialization Configurations  
12  
ispMACH 4A Family  
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,  
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is  
provided for initialization. It can be selected to control reset or preset.  
Power-Up  
Preset  
Power-Up  
Reset  
Individual  
Preset  
Product Term  
Individual  
Reset  
Product Term  
AR  
Q
AP  
D/L/T  
AR  
Q
AP  
D/L/T  
a. Reset  
b. Preset  
17466G-014  
17466G-015  
Figure 8. Asynchronous Mode Initialization Configurations  
Note that the reset/preset swapping selection feature effects power-up reset as well. The  
initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data  
to the output switch matrix and the input switch matrix. The output switch matrix can route this  
data to an output if so desired. The input switch matrix can send the signal back to the central  
switch matrix as feedback.  
Table 9. Asynchronous Reset/Preset Operation  
1
AR  
0
AP  
0
CLK/LE  
Q+  
X
X
X
X
See Table 8  
0
1
1
0
0
1
0
1
1
Note:  
1. Transparent latch is unaffected by AR, AP  
ispMACH 4A Family  
13  
Output Sw itch Matrix  
The output switch matrix allows macrocells to be connected to any of several I/O cells within a  
PAL block. This provides high flexibility in determining pinout and allows design changes to  
occur without effecting pinout.  
In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many  
macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells  
to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can  
choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A  
devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells  
(Figure 9).  
M0  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M0  
M1  
M0  
M1  
I/O0  
I/O1  
M2  
M2  
I/O2  
M3  
M3  
I/O3  
M4  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M4  
I/O4  
M5  
M5  
I/O5  
M6  
M6  
I/O6  
M7  
M7  
I/O7  
M8  
M8  
I/O8  
M8  
M9  
I/O8  
M9  
M9  
I/O9  
I/O9  
M10  
M11  
M12  
M13  
M14  
M15  
M10  
M11  
M12  
M13  
M14  
M15  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
M10  
M11  
M12  
M13  
M14  
M15  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
Each I/O cell can  
choose one of 8  
macrocells in  
all ispMACH 4A  
devices.  
Each macrocell can drive  
one of 4 I/O cells in  
ispMACH 4A devices with  
2:1 macrocell-I/O cell ratio. macrocell-I/O cell ratio except  
M4A(3, 5)-32/32 devices.  
Each macrocell can drive  
one of 8 I/O cells in  
ispMACH 4A devices with 1:1  
Each macrocell can drive  
one of 8 I/O cells in  
M4A(3, 5)-32/32 devices.  
Figure 9. ispMACH 4A Output Sw itch Matrix  
Table 10. Output Sw itch Matrix Combinations for ispMACH 4A Devices w ith 2:1 Macrocell-I/O Cell Ratio  
Macrocell  
M0, M1  
M2, M3  
M4, M5  
M6, M7  
M8, M9  
Routable to I/O Cells  
I/O0, I/O5, I/O6, I/O7  
I/O0, I/O1, I/O6, I/O7  
I/O0, I/O1, I/O2, I/O7  
I/O0, I/O1, I/O2, I/O3  
I/O1, I/O2, I/O3, I/O4  
14  
ispMACH 4A Family  
Table 10. Output Sw itch Matrix Combinations for ispMACH 4A Devices w ith 2:1 Macrocell-I/O Cell Ratio  
Macrocell  
M10, M11  
M12, M13  
M14, M15  
Routable to I/O Cells  
I/O2, I/O3, I/O4, I/O5  
I/O3, I/O4, I/O5, I/O6  
I/O4, I/O5, I/O6, I/O7  
I/O Cell  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
Available Macrocells  
M0, M1, M2, M3, M4, M5, M6, M7  
M2, M3, M4, M5, M6, M7, M8, M9  
M4, M5, M6, M7, M8, M9, M10, M11  
M6, M7, M8, M9, M10, M11, M12, M13  
M8, M9, M10, M11, M12, M13, M14, M15  
M0, M1, M10, M11, M12, M13, M14, M15  
M0, M1, M2, M3, M12, M13, M14, M15  
M0, M1, M2, M3, M4, M5, M14, M15  
Table 11. Output Sw itch Matrix Combinations for M4A3-256/160 and M4A3-256/192  
Macrocell  
M0  
Routable to I/O Cells  
I/O0  
I/O0  
I/O0  
I/O0  
I/O0  
I/O0  
I/O0  
I/O0  
I/O8  
I/O8  
I/O8  
I/O8  
I/O8  
I/O8  
I/O8  
I/O8  
I/O1  
I/O1  
I/O1  
I/O1  
I/O1  
I/O1  
I/O1  
I/O1  
I/O9  
I/O9  
I/O9  
I/O9  
I/O9  
I/O9  
I/O9  
I/O9  
I/O2  
I/O3  
I/O4  
I/O4  
I/O5  
I/O5  
I/O6  
I/O6  
I/O7  
M1  
I/O2  
I/O3  
I/O7  
M2  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M3  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M4  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M5  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M6  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M7  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
M8  
I/O10  
I/O10  
I/O10  
I/O10  
I/O10  
I/O10  
I/O10  
I/O10  
I/O11  
I/O11  
I/O11  
I/O11  
I/O11  
I/O11  
I/O11  
I/O11  
I/O12  
I/O12  
I/O12  
I/O12  
I/O12  
I/O12  
I/O12  
I/O12  
I/O13  
I/O13  
I/O13  
I/O13  
I/O13  
I/O13  
I/O13  
I/O13  
I/O14  
I/O14  
I/O14  
I/O14  
I/O14  
I/O14  
I/O14  
I/O14  
I/O15  
I/O15  
I/O15  
I/O15  
I/O15  
I/O15  
I/O15  
I/O15  
M9  
M10  
M11  
M12  
M13  
M14  
M15  
I/O Cell  
I/O0  
Available Macrocells  
M0  
M0  
M0  
M0  
M0  
M0  
M0  
M1  
M1  
M1  
M1  
M1  
M1  
M1  
M2  
M2  
M2  
M2  
M2  
M2  
M2  
M3  
M3  
M3  
M3  
M3  
M3  
M3  
M4  
M4  
M4  
M4  
M4  
M4  
M4  
M5  
M5  
M5  
M5  
M5  
M5  
M5  
M6  
M6  
M6  
M6  
M6  
M6  
M6  
M7  
M7  
M7  
M7  
M7  
M7  
M7  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
ispMACH 4A Family  
15  
Table 11. Output Sw itch Matrix Combinations for M4A3-256/160 and M4A3-256/192  
Macrocell  
I/O7  
Routable to I/O Cells  
M0  
M8  
M8  
M8  
M8  
M8  
M8  
M8  
M8  
M1  
M9  
M9  
M9  
M9  
M9  
M9  
M9  
M9  
M2  
M3  
M4  
M5  
M6  
M7  
I/O8  
M10  
M10  
M10  
M10  
M10  
M10  
M10  
M10  
M11  
M11  
M11  
M11  
M11  
M11  
M11  
M11  
M12  
M12  
M12  
M12  
M12  
M12  
M12  
M12  
M13  
M13  
M13  
M13  
M13  
M13  
M13  
M13  
M14  
M14  
M14  
M14  
M14  
M14  
M14  
M14  
M15  
M15  
M15  
M15  
M15  
M15  
M15  
M15  
I/O9  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
Table 12. Output Sw itch Matrix Combinations for M4A(3,5)-32/32  
Macrocell  
Routable to I/O Cells  
M0, M1, M2, M3, M4, M5, M6, M7  
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7  
M8, M9, M10, M11, M12, M13, M14, M15  
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15  
I/O Cell  
Available Macrocells  
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7  
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15  
M0, M1, M2, M3, M4, M5, M6, M7  
M8, M9, M10, M11, M12, M13, M14, M15  
Table 13. Output Sw itch Matrix Combinations for M4A3-64/64  
Macrocell  
Routable to I/O Cells  
MO, M1  
M2, M3  
I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15  
I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15  
I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15  
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7  
I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9  
I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11  
I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13  
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15  
M4, M5  
M6, M7  
M8, M9  
M10, M11  
M12, M13  
M14, M15  
I/O Cell  
I/O0, I/O1  
I/O2, I/O3  
I/O4, I/O5  
I/O6, I/O7  
I/O8, I/O9  
I/O10, I/O11  
I/O12, I/O13  
I/O14, I/O15  
Available Macrocells  
M0, M1, M2, M3, M4, M5, M6, M7  
M2, M3, M4, M5, M6, M7, M8, M9  
M4, M5, M6, M7, M8, M9, M10, M11  
M6, M7, M8, M9, M10, M11, M12, M13  
M8, M9, M10, M11, M12, M13, M14, M15  
M0, M1, M10, M11, M12, M13, M14, M15  
M0, M1, M2, M3, M12, M13, M14, M15  
M0, M1, M2, M3, M4, M5, M14, M15  
16  
ispMACH 4A Family  
I/O Cell  
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback  
path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual  
output enable product term is provided for each I/O cell. The feedback signal drives the input  
switch matrix.  
Individual  
Output Enable  
Product Term  
From Output  
Switch Matrix  
Individual  
Output Enable  
Product Term  
To  
Input  
Switch  
Matrix  
From Output  
Switch Matrix  
D/L  
Q
To  
Input  
Switch  
Matrix  
Block CLK0  
Block CLK1  
Block CLK2  
Block CLK3  
Power-up reset  
17466G-017  
17466G-018  
Figure 10. I/O Cell for ispMACH 4A Devices w ith 2:1 Figure 11. I/O Cell for ispMACH 4A Devices w ith 1:1  
Macrocell-I/O Cell Ratio Macrocell-I/O Cell Ratio  
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input  
in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and  
registered versions of the input are sent to the input switch matrix. This allows for such functions  
as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the  
second data value is put on the I/O pin and compared with the previous stored value.  
Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the  
macrocells. It powers up to a logic low.  
Zero-Hold-Time Input Register  
The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay  
associated with loading data into all I/O cell registers and latches. When programmed, the ZHT  
fuse increases the data path setup delays to input storage elements, matching equivalent delays  
in the clock path. When the fuse is erased, the setup time to the input storage element is  
minimized. This feature facilitates doing worst-case designs for which data is loaded from  
sources which have low (or zero) minimum output propagation delays from clock edges.  
ispMACH 4A Family  
17  
Input Sw itch Matrix  
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch  
matrix. Without the input switch matrix, each input and feedback signal has only one way to  
enter the central switch matrix. The input switch matrix provides additional ways for these  
signals to enter the central switch matrix.  
From Input Cell  
17466G-002  
17466G-003  
Figure 12. ispMACH 4A w ith 2:1 Macrocell-I/O Cell Figure 13. ispMACH 4A w ith 1:1 Macrocell-I/O Cell  
Ratio - Input Sw itch Matrix Ratio - Input Sw itch Matrix  
18  
ispMACH 4A Family  
PAL Block Clock Generation  
Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive  
a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals  
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of  
a large number of combinations of the true and complement edges of the global clock signals.  
Table 14 lists the possible combinations.  
GCLK0  
Block CLK0  
(GCLK0 or GCLK1)  
GCLK1  
Block CLK1  
(GCLK1 or GCLK0)  
GCLK2  
Block CLK2  
(GCLK2 or GCLK3)  
GCLK3  
Block CLK3  
(GCLK3 or GCLK2)  
17466G-004  
1
Figure 14. PAL Block Clock Generator  
1. M4A(3,5)-32/ 32 and M4A(3,5)-64/ 32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is  
tied to GCLK1.  
1
Table 14. PAL Block Clock Combinations  
Block CLK0  
Block CLK1  
Block CLK2  
Block CLK3  
GCLK0  
GCLK1  
GCLK0  
GCLK1  
X
GCLK1  
GCLK1  
GCLK0  
GCLK0  
X
X
X
X
X
X
X
X
X
GCLK2 (GCLK0)  
GCLK3 (GCLK1)  
GCLK2 (GCLK0)  
GCLK3 (GCLK1)  
GCLK3 (GCLK1)  
GCLK3 (GCLK1)  
GCLK2 (GCLK0)  
GCLK2 (GCLK0)  
X
X
X
X
X
X
Note:  
1. Values in parentheses are for the M4A(3,5)-32/ 32 and M4A(3,5)-64/ 32.  
This feature provides high flexibility for partitioning state machines and dual-phase clocks. It  
also allows latches to be driven with either polarity of latch enable, and in a master-slave  
configuration.  
ispMACH 4A Family  
19  
ispMACH 4A TIMING MODEL  
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a  
ispMACH 4A device, and at the same time, be easy to understand. This model accurately  
describes all combinatorial and registered paths through the device, making a distinction  
between internal feedback and external feedback. A signal uses internal feedback when it is fed  
back into the switch matrix or block without having to go through the output buffer. The input  
register specifications are also reported as internal feedback. When a signal is fed back into the  
switch matrix after having gone through the output buffer, it is using external feedback.  
The parameter, t , is defined as the time it takes to go from feedback through the output buffer  
BUF  
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter  
designator is followed by an “i”. By adding t  
to this internal parameter, the external parameter  
BUF  
is derived. For example, t = t  
+ t . A diagram representing the modularized ispMACH 4A  
PD  
PDi  
BUF  
timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and  
High Speed Design for a more detailed discussion about the timing parameters.  
(External Feedback)  
(Internal Feedback)  
COMB/DFF/TFF/  
LATCH/SR*/JK*  
tSLW  
*emulated  
Central  
Switch  
Matrix  
IN  
OUT  
tSS(T)  
tPDi  
tBUF  
Q
tSA(T)  
tPDLi  
tH(S/A)  
tS(S/A)L  
tH(S/A)L  
tSRR  
tCO(S/A)i  
tGO(S/A)i  
tSRi  
tPL  
INPUT REG/  
INPUT LATCH  
tEA  
tER  
S/R  
tSIRS  
tHIRS  
tSIL  
tPDILi  
tICOSi  
tIGOSi  
tPDILZi  
Q
tHIL  
tSIRZ  
tHIRZ  
tSILZ  
tHILZ  
BLK CLK  
17466G-025  
Figure 15. ispMACH 4A Timing Model  
SPEEDLOCKING FOR GUARANTEED FIXED TIMING  
The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual  
macrocell with the assistance of an XOR gate without incurring additional timing delays.  
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is  
independent of the logic required by the design. Other competitive CPLDs incur serious timing  
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and  
SpeedLocking combine to give designs easy access to the performance required in today’s  
designs.  
20  
ispMACH 4A Family  
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY  
All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard.  
This allows functional testing of the circuit board on which the device is mounted through a  
serial scan path that can access all critical logic nodes. Internal registers are linked internally,  
allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be  
captured and shifted out for verification. In addition, these devices can be linked into a board-  
level serial scan path for more complete board-level testing.  
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING  
Programming devices in-system provides a number of significant benefits including: rapid  
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.  
All ispMACH 4A devices provide In-System Programming (ISP) capability through their  
Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures  
that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the  
communication interface through which ISP is achieved, customers get the benefit of a standard,  
well-defined interface.  
ispMACH 4A devices can be programmed across the commercial temperature and voltage range.  
The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices.  
LatticePRO takes the JEDEC file output produced by the design implementation software, along  
with information about the JTAG chain, and creates a set of vectors that are used to drive the  
JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port  
of a PC. Alternatively, LatticePRO software can output files in formats understood by common  
automated test equipment. This equpment can then be used to program ispMACH 4A devices  
during the testing of a circuit board.  
PCI COMPLIANT  
ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI  
Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V  
devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI  
condition to clamp the inputs as they rise above V because of their 5-V input tolerant feature.  
CC  
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS  
Both the 3.3-V and 5-V V ispMACH 4A devices are safe for mixed supply voltage system  
CC  
designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,  
while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5  
V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-  
use mixed-voltage design capability.  
PULL UP OR BUS-FRIENDLY INPUTS AND I/Os  
All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry  
incorporating two inverters in series which loop back to the input. This double inversion weakly  
holds the input at its last driven logic state. While it is good design practice to tie unused pins  
to a known state, the Bus-Friendly input structure pulls pins away from the input threshold  
voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches  
are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH  
Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.  
ispMACH 4A Family  
21  
All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either  
pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs  
and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled  
MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.  
POWER MANAGEMENT  
Each individual PAL block in ispMACH 4A devices features a programmable low-power mode,  
which results in power savings of up to 50%. The signal speed paths in the low-power PAL block  
will be slower than those in the non-low-power PAL block. This feature allows speed critical  
paths to run at maximum frequency while the rest of the signal paths operate in the low-power  
mode.  
PROGRAMMABLE SLEW RATE  
Each ispMACH 4A device I/O has an individually programmable output slew rate control bit.  
Each output can be individually configured for the higher speed transition (3 V/ns) or for the  
lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-  
slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum.  
For designs with short traces or well terminated lines, the fast slew rate can be used to achieve  
the highest speed. The slew rate is adjusted independent of power.  
POWER-UP RESET/SET  
All flip-flops power up to a known state for predictable system initialization. If a macrocell is  
configured to SET on a signal from the control generator, then that macrocell will be SET during  
device power-up. If a macrocell is configured to RESET on a signal from the control generator  
or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee  
initialization values, the V rise must be monotonic, and the clock must be inactive until the  
CC  
reset delay time has elapsed.  
SECURITY BIT  
A programmable security bit is provided on the ispMACH 4A devices as a deterrent to  
unauthorized copying of the array configuration patterns. Once programmed, this bit defeats  
readback of the programmed pattern by a device programmer, securing proprietary designs from  
competitors. Programming and verification are also defeated by the security bit. The bit can only  
be reset by erasing the entire device.  
HOT SOCKETING  
ispMACH 4A devices are well-suited for those applications that require hot socketing capability.  
Hot socketing a device requires that the device, when powered down, can tolerate active signals  
on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the  
powered-down MACH devices be minimal on active signals.  
22  
ispMACH 4A Family  
M4A(3, 5)-64/32  
M4A3-64/64  
M4A(3, 5)-96/48  
M4A(3, 5)-128/64  
M4A3-384  
M4A3-512  
M4(3, 5)-192/96  
M4(3, 5)-256/128  
CLOCK  
GENERATOR  
A
A
B
16  
17  
17  
17  
18  
18  
4
0
M0  
C0  
C1  
MACROCELL  
MACROCELL  
I/O0  
M0  
I/O  
O0  
O1  
M1  
CELL  
M1  
M2  
M3  
C2  
C3  
MACROCELL  
MACROCELL  
M2  
M3  
I/O1  
I/O2  
I/O3  
I/O  
CELL  
M4  
M5  
C4  
C5  
MACROCELL  
MACROCELL  
M4  
M5  
I/O  
CELL  
O2  
O3  
M6  
M7  
C6  
C7  
MACROCELL  
MACROCELL  
M6  
M7  
I/O  
CELL  
M8  
M9  
C8  
C9  
MACROCELL  
MACROCELL  
M8  
M9  
I/O4  
I/O5  
I/O6  
I/O  
CELL  
O4  
O5  
O6  
M10  
M11  
C10  
C11  
MACROCELL  
MACROCELL  
M10  
M11  
I/O  
CELL  
M12  
M13  
C12  
C13  
MACROCELL  
MACROCELL  
M12  
M13  
I/O  
CELL  
M14  
M15  
C14  
C15  
MACROCELL  
MACROCELL  
I/O7  
M14  
M15  
I/O  
CELL  
O7  
89  
B
16  
24  
INPUT SWITCH  
MATRIX  
16  
Figure 16. PAL Block for ispMACH 4A w ith 2:1 Macrocell - I/O Cell Ratio  
ispMACH 4A Family  
23  
M4A3-256/160  
M4A3-256/192  
M4A3-64/64  
A
B
16  
17  
18  
18  
CLOCK  
A
GENERATOR  
4
0
I/O0  
I/O1  
M0  
M1  
I/O  
CELL  
O0  
O1  
MACROCELL  
MACROCELL  
M0  
C0  
C1  
I/O  
CELL  
M1  
I/O2  
I/O3  
M2  
M3  
I/O  
CELL  
C2  
C3  
O2  
O3  
MACROCELL  
MACROCELL  
M2  
M3  
I/O  
CELL  
I/O4  
I/O5  
M4  
M5  
I/O  
CELL  
C4  
C5  
O4  
O5  
MACROCELL  
MACROCELL  
M4  
M5  
I/O  
CELL  
I/O6  
I/O7  
M6  
M7  
I/O  
CELL  
C6  
C7  
MACROCELL  
MACROCELL  
O6  
O7  
M6  
M7  
I/O  
CELL  
I/O8  
I/O9  
M8  
M9  
I/O  
CELL  
C8  
C9  
O8  
O9  
MACROCELL  
MACROCELL  
M8  
M9  
I/O  
CELL  
I/O10  
I/O11  
M10  
M11  
I/O  
CELL  
C10  
C11  
O10  
O11  
MACROCELL  
MACROCELL  
M10  
M11  
I/O  
CELL  
I/O12  
I/O13  
M12  
M13  
I/O  
CELL  
C12  
C13  
O12  
O13  
MACROCELL  
MACROCELL  
M12  
M13  
I/O  
CELL  
I/O14  
I/O15  
M14  
M15  
I/O  
CELL  
C14  
C15  
MACROCELL  
MACROCELL  
O14  
O15  
M14  
M15  
I/O  
CELL  
97  
B
16  
INPUT  
SWITCH  
MATRIX  
32  
16  
17466H-41  
Figure 17. PAL Block for ispMACH 4A Devices w ith 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)  
24  
ispMACH 4A Family  
CLK0/I0 CLK0/I1  
CLOCK  
16  
GENERATOR  
2
0
I/O0  
I/O1  
M0  
M1  
I/O  
CELL  
O0  
O1  
MACROCELL  
MACROCELL  
M0  
M1  
C0  
C1  
I/O  
CELL  
I/O2  
I/O3  
M2  
M3  
I/O  
CELL  
C2  
C3  
O2  
O3  
MACROCELL  
MACROCELL  
M2  
M3  
I/O  
CELL  
I/O4  
I/O5  
M4  
M5  
I/O  
CELL  
C4  
C5  
O4  
O5  
MACROCELL  
MACROCELL  
M4  
M5  
I/O  
CELL  
I/O6  
I/O7  
M6  
M7  
I/O  
CELL  
C6  
C7  
MACROCELL  
MACROCELL  
O6  
O7  
M6  
M7  
I/O  
CELL  
I/O8  
I/O9  
M8  
M9  
I/O  
CELL  
C8  
C9  
O8  
O9  
MACROCELL  
MACROCELL  
M8  
M9  
I/O  
CELL  
I/O10  
I/O11  
M10  
M11  
I/O  
CELL  
C10  
C11  
O10  
O11  
MACROCELL  
MACROCELL  
M10  
M11  
I/O  
CELL  
I/O12  
I/O13  
M12  
M13  
I/O  
CELL  
C12  
C13  
O12  
O13  
MACROCELL  
MACROCELL  
M12  
M13  
I/O  
CELL  
I/O14  
I/O15  
M14  
M15  
I/O  
CELL  
C14  
C15  
MACROCELL  
MACROCELL  
O14  
O15  
M14  
M15  
I/O  
CELL  
97  
17  
16  
INPUT  
SWITCH  
MATRIX  
32  
16  
Figure 18. PAL Block for M4A (3,5)-32/32  
17466H-042  
ispMACH 4A Family  
25  
BLOCK DIAGRAM – M4A(3,5)-32/32  
Block A  
I/O8–I/O15  
I/O0–I/O7  
8
8
I/O Cells  
I/O Cells  
8
8
Output Switch  
Output Switch  
Matrix  
8
Matrix  
8
8
8
4
4
8
8
8
8
Macrocells  
8
Macrocells  
2
8
66 X 98  
AND Logic Array  
and Logic Allocator  
16  
16  
16  
33  
Central Switch Matrix  
2
2
33  
16  
66 X 98  
AND Logic Array  
and Logic Allocator  
8
2
8
Macrocells  
8
Macrocells  
8
8
4
4
8
8
8
8
8
Output Switch  
Output Switch  
Matrix  
Matrix  
8
8
I/O Cells  
8
I/O Cells  
8
I/O16–I/O23  
I/O24–I/O31  
Block B  
17466H-019  
26  
ispMACH 4A Family  
BLOCK DIAGRAM – M4A(3,5)-64/32  
Block A  
Block D  
I/O0–I/O7  
I/O24–I/O31  
8
8
I/O Cells  
I/O Cells  
8
8
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
16  
16  
66 X 90  
AND Logic Array  
and Logic Allocator  
66 X 90  
AND Logic Array  
and Logic Allocator  
2
2
24  
24  
24  
33  
33  
33  
Central Switch Matrix  
2
2
33  
24  
66 X 90  
66 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
2
2
16  
16  
Macrocells  
Macrocells  
16  
16  
16  
4
4
4
4
16  
16  
16  
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
I/O Cells  
8
I/O Cells  
8
I/O8–I/O15  
I/O16–I/O23  
Block C  
Block B  
17466H-020  
ispMACH 4A Family  
27  
BLOCK DIAGRAM – M4A3-64/64  
Block A  
Block D  
16  
16  
I/O Cells  
I/O Cells  
16  
16  
Output Switch  
Output Switch  
Matrix  
Matrix  
16  
16  
16  
16  
16  
16  
16  
16  
4
4
Macrocells  
16  
Macrocells  
16  
66 X 90  
AND Logic Array  
and Logic Allocator  
66 X 90  
AND Logic Array  
and Logic Allocator  
4
4
33  
33  
33  
Central Switch Matrix  
4
2
4
33  
66 X 90  
66 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
16  
16  
Macrocells  
Macrocells  
16  
16  
16  
16  
4
4
16  
16  
16  
16  
Output Switch  
Matrix  
Output Switch  
Matrix  
16  
16  
I/O Cells  
16  
I/O Cells  
16  
Block C  
Block B  
17466H-020A  
28  
ispMACH 4A Family  
BLOCK DIAGRAM – M4A(3,5)-96/48  
I2, I3, I6, I7  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
OE  
OE  
OE  
Clock Generator  
Clock Generator  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
Clock Generator  
Clock Generator  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
Clock Generator  
Clock Generator  
CLK0/I0, CLK1/I1,  
CLK2/I4, CLK3/I5  
17466G-021  
ispMACH 4A Family  
29  
BLOCK DIAGRAM – M4A(3,5)-128/64  
I2, I5  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
OE  
OE  
OE  
OE  
Clock Generator  
Clock Generator  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
Clock Generator  
Clock Generator  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
Clock Generator  
Clock Generator  
Input Switch  
Matrix  
Input Switch  
Matrix  
OE  
Clock Generator  
Clock Generator  
CLK0/I0, CLK1/I1,  
CLK2/I3, CLK3/I4  
17466H-022  
ispMACH 4A Family  
30  
BLOCK DIAGRAM – M4A(3,5)-192/96  
Block B  
I/O8–I/O15  
Block A  
I/O0–I/O7  
Block L  
I/O88–I/O95  
Block K  
I/O80–I/O87  
CLK0–CLK3  
4
4
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
34  
34  
34  
34  
I/O72–I/O79 Block J  
I/O64–I/O71 Block I  
Block C I/O16–I/O23  
Block D I/O24–I/O31  
8
8
8
8
I/O Cells  
8
I/O Cells  
I/O Cells  
I/O Cells  
8
8
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
34  
34  
34  
34  
34  
34  
34  
34  
24  
24  
24  
24  
68 X 90  
68 X 90  
68 X 90  
68 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
I/O Cells  
8
8
I/O Cells  
8
8
8
I/O Cells  
I/O Cells  
8
8
16  
I0–I15  
I/O32–I/O39  
I/O40–I/O47  
I/O48–I/O55  
I/O56–I/O63  
Block E  
Block F  
Block G  
Block H  
17466G-067  
ispMACH 4A Family  
31  
BLOCK DIAGRAM – M4A(3,5)-256/128  
Block B  
I/O8–I/O15  
Block A  
I/O0–I/O7  
Block P  
I/O120–I/O127  
Block O  
I/O112–I/O119  
CLK0–CLK3  
4
4
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
34  
34  
34  
34  
34  
34  
34  
34  
24  
24  
24  
24  
68 X 90  
68 X 90  
68 X 90  
68 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
I/O Cells  
8
8
8
8
I/O Cells  
8
I/O Cells  
I/O Cells  
8
8
8
Block C I/O16–I/O23  
Block D I/O24–I/O31  
Block E I/O32–I/O39  
Block F I/O40–I/O47  
I/O104–I/O111 Block N  
I/O96–I/O103 Block M  
I/O88–I/O95 Block L  
I/O80–I/O87 Block K  
8
8
8
I/O Cells  
8
I/O Cells  
I/O Cells  
I/O Cells  
8
8
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
68 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
34  
34  
34  
34  
34  
34  
34  
34  
24  
24  
24  
24  
68 X 90  
68 X 90  
68 X 90  
68 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
I/O Cells  
8
8
I/O Cells  
8
8
8
I/O Cells  
I/O Cells  
8
8
14  
I0–I13  
I/O56–I/O63  
Block H  
I/O64–I/O71  
Block I  
I/O72–I/O79  
Block J  
I/O48–I/O55  
Block G  
17466G-024  
32  
ispMACH 4A Family  
BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192  
CLK0–CLK3  
Block P  
Block O  
Block B  
Block A  
4
4
16  
I/O Cells  
16  
16  
I/O Cells  
16  
16  
I/O Cells  
16  
16  
I/O Cells  
16  
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
16  
4
16  
4
16  
4
16  
4
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
4
4
4
4
32  
32  
32  
32  
36  
36  
36  
36  
36  
36  
36  
36  
32  
32  
32  
32  
72 X 98  
72 X 98  
72 X 98  
72 X 98  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
16  
4
4
16  
4
4
16  
4
4
16  
4
16  
16  
16  
16  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
16  
I/O Cells  
16  
16  
16  
16  
I/O Cells  
16  
I/O Cells  
I/O Cells  
16  
16  
16  
Block C  
Block D  
Block E  
Block F  
Block N  
Block M  
Block L  
Block K  
16  
16  
16  
I/O Cells  
16  
I/O Cells  
I/O Cells  
I/O Cells  
16  
16  
16  
4
16  
4
4
16  
4
4
16  
4
4
16  
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
72 X 98  
AND Logic Array  
and Logic Allocator  
4
4
4
4
32  
32  
32  
32  
36  
36  
36  
36  
36  
36  
36  
36  
32  
32  
32  
32  
72 X 98  
72 X 98  
72 X 98  
72 X 98  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
16  
4
16  
4
16  
4
16  
16  
16  
16  
16  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
4
4
4
4
16  
I/O Cells  
16  
16  
I/O Cells  
16  
16  
16  
I/O Cells  
I/O Cells  
16  
16  
Block G  
Block H  
Block I  
Block J  
17466G-050  
ispMACH 4A Family  
33  
BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192  
CLK0–CLK3  
Block B  
Block A  
Block HX  
Block GX  
4
4
4
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
Detail A  
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
36  
36  
36  
36  
36  
36  
36  
36  
24  
24  
24  
24  
72 X 90  
72 X 90  
72 X 90  
72 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
Block D  
Block C  
Block FX  
Block CX  
Block EX  
Block DX  
Block E  
Block F  
Repeat Detail A  
Block G  
Block J  
Block H  
Block I  
Block AX  
Block P  
Block BX  
Block O  
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
36  
36  
36  
36  
36  
36  
36  
36  
24  
24  
24  
24  
72 X 90  
72 X 90  
72 X 90  
72 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
I/O Cells  
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
8
Block K  
Block L  
Block M  
Block N  
17466G-067  
34  
ispMACH 4A Family  
BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256  
CLK0–CLK3  
Block B  
Block A  
Block PX  
Block OX  
4
4
4
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
Detail A  
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
36  
36  
36  
36  
36  
36  
36  
36  
24  
24  
24  
24  
72 X 90  
72 X 90  
72 X 90  
72 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
Block D  
Block MX  
Block LX  
Block C  
Block NX  
Block KX  
Block E  
Block F  
Repeat Detail A  
Repeat Detail A  
Block G  
Block J  
Block H  
Block I  
Block IX  
Block JX  
Block GX  
Block HX  
Block K  
Block N  
Block L  
Block M  
Block EX  
Block DX  
Block FX  
Block CX  
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
8
I/O Cells  
8
4
4
4
4
4
4
4
4
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Macrocells  
Macrocells  
Macrocells  
Macrocells  
16  
16  
16  
16  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
72 X 90  
AND Logic Array  
and Logic Allocator  
4
4
4
4
24  
24  
24  
24  
36  
36  
36  
36  
36  
36  
36  
36  
24  
24  
24  
24  
72 X 90  
72 X 90  
72 X 90  
72 X 90  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
AND Logic Array  
and Logic Allocator  
4
4
4
4
16  
16  
16  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
Macrocells  
16  
16  
16  
16  
16  
4
4
4
4
4
4
4
4
16  
16  
16  
16  
8
8
8
8
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
Output Switch  
Matrix  
8
8
8
8
I/O Cells  
I/O Cells  
8
I/O Cells  
8
I/O Cells  
8
8
Block O  
Block P  
Block AX  
Block BX  
17466G-068  
ispMACH 4A Family  
35  
ABSOLUTE MAXIMUM RATINGS  
OPERATING RANGES  
M4A5  
Commercial (C) Devices  
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C  
Ambient Temperature (T )  
A
Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C  
Ambient Temperature  
with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C  
Supply Voltage (V )  
CC  
with Respect to Ground . . . . . . . . . . +4.75 V to +5.25 V  
Device Junction Temperature . . . . . . . . . . . . . . . +130°C  
Supply Voltage  
with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V  
Industrial (I) Devices  
Ambient Temperature (T )  
A
DC Input Voltage. . . . . . . . . . . . . . . -0.5 V to V + 0.5 V  
Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C  
CC  
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 V  
Supply Voltage (V  
)
CC  
with Respect to Ground . . . . . . . . . . . +4.50 V to +5.5 V  
Latchup Current (T = -40°C to +85°C) . . . . . . . 200 mA  
A
Operating ranges define those limits between which the func-  
tionality of the device is guaranteed.  
Stresses a bove those listed u n der Absolu te Ma xim u m  
Ratings may cause permanent device failure. Functionality  
at or above these limits is not implied. Exposure to Absolute  
Maximum Ratings for extended periods may affect device  
reliability.  
5-V DC CHARACTERISTICS OVER OPERATING RANGES  
Parameter  
Symbol  
Parameter Description  
Output HIGH Voltage  
Test Conditions  
= –3.2 mA, V = Min, V = V or V  
IL  
Min  
Typ  
Max  
Unit  
V
I
2.4  
OH  
CC  
IN  
IH  
V
OH  
I
= –2.5 mA, V = Max, V = V or V  
IL  
3.6  
0.5  
V
OH  
CC  
IN  
IH  
V
Output LOW Voltage  
Input HIGH Voltage  
I
= 24 mA, V = Min, V = V or V (Note 1)  
V
OL  
OL  
CC  
IN  
IH  
IL  
Guaranteed Input Logical HIGH Voltage for all Inputs  
(Note 2)  
V
2.0  
V
V
IH  
Guaranteed Input Logical LOW Voltage for all Inputs  
(Note 2)  
V
Input LOW Voltage  
0.8  
IL  
I
Input HIGH Leakage Current  
V = 5.25 V, V = Max (Note 3)  
10  
–10  
10  
µA  
µA  
µA  
µA  
mA  
IH  
IN  
CC  
I
Input LOW Leakage Current  
V = 0 V, V = Max (Note 3)  
IN CC  
IL  
I
Off-State Output Leakage Current HIGH  
Off-State Output Leakage Current LOW  
Output Short-Circuit Current  
V
= 5.25 V, V = Max, V = V or V (Note 3)  
OZH  
OUT CC IN IH IL  
I
V
= 0 V, V = Max , V = V or V (Note 3)  
–10  
–160  
OZL  
OUT  
CC  
IN  
IH  
IL  
I
V
= 0.5 V, V = Max (Note 4)  
–30  
SC  
OUT  
CC  
Notes:  
1. Total I  
for one PAL block should not exceed 64 mA.  
OL  
2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.  
3. I/ O pin leakage is the worst case of I and I (or I and I ).  
IL  
OZL  
IH  
OZH  
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.  
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.  
OUT  
36  
ispMACH 4A Family  
ABSOLUTE MAXIMUM RATINGS  
OPERATING RANGES  
M4A3  
Commercial (C) Devices  
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C  
Ambient Temperature (T )  
A
Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C  
Ambient Temperature  
with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C  
Supply Voltage (V )  
CC  
with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V  
Device Junction Temperature . . . . . . . . . . . . . . . +130°C  
Supply Voltage  
with Respect to Ground . . . . . . . . . . . . . -0.5 V to +4.5 V  
Industrial (I) Devices  
Ambient Temperature (T )  
A
DC Input Voltage. . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V  
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 V  
Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C  
Supply Voltage (V  
)
CC  
with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V  
Latchup Current (T = -40°C to +85°C) . . . . . . . 200 mA  
A
Operating ranges define those limits between which the func-  
tionality of the device is guaranteed.  
Stresses a bove those listed u n der Absolu te Ma xim u m  
Ratings may cause permanent device failure. Functionality  
at or above these limits is not implied. Exposure to Absolute  
Maximum Ratings for extended periods may affect device  
reliability.  
3.3-V DC CHARACTERISTICS OVER OPERATING RANGES  
Parameter  
Symbol  
Parameter Description  
Output HIGH Voltage  
Test Conditions  
= –100 µA  
Min  
Typ  
Max  
Unit  
V
I
V – 0.2  
V = Min  
OH  
CC  
CC  
V
OH  
V = V or V  
I
= –3.2 mA  
= 100 µA  
= 24 mA  
2.4  
V
IN  
IH  
IL  
OH  
V = Min  
CC  
I
0.2  
0.5  
V
V
OL  
V
Output LOW Voltage  
V = V or V  
OL  
IN IH IL  
I
(Note 1)  
OL  
Guaranteed Input Logical HIGH Voltage for all  
Inputs  
V
Input HIGH Voltage  
Input LOW Voltage  
2.0  
5.5  
0.8  
V
V
IH  
Guaranteed Input Logical LOW Voltage for all  
Inputs  
V
–0.3  
IL  
I
Input HIGH Leakage Current  
Input LOW Leakage Current  
V = 3.6 V, V = Max (Note 2)  
5
µA  
µA  
IH  
IN  
CC  
I
V = 0 V, V = Max (Note 2)  
–5  
IL  
IN  
CC  
V
= 3.6 V, V = Max  
CC  
OUT  
I
Off-State Output Leakage Current HIGH  
5
µA  
OZH  
V = V or V (Note 2)  
IN  
IH  
IL  
V
= 0 V, V = Max  
CC  
OUT  
I
Off-State Output Leakage Current LOW  
Output Short-Circuit Current  
–5  
µA  
OZL  
V = V or V (Note 2)  
IN  
IH  
IL  
I
V
= 0.5 V, V = Max (Note 3)  
–15  
–160  
mA  
SC  
OUT  
CC  
Notes:  
1. Total I for one PAL block should not exceed 64 mA.  
OL  
2. I/ O pin leakage is the worst case of I and I  
(or I and I  
).  
OZH  
IL  
OZL  
IH  
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.  
Notes:  
1. See “MACH Switching Test Circuit”document on the Literature Download page of the Lattice web site.  
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.  
ispMACH 4A Family  
37  
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1  
-5  
-55  
-6  
-65  
-7  
-10  
-12  
-14  
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit  
Combinatorial Delay:  
Internal combinatorial propagation  
t
3.5  
5.0  
4.0  
5.5  
4.3  
6.0  
4.5  
6.5  
5.0  
7.5  
7.0  
9.0  
11.0 ns  
14.0 ns  
PDi  
delay  
t
Combinatorial propagation delay  
10.0  
12.0  
PD  
Registered Delays:  
Synchronous clock setup time, D-type  
t
3.0  
4.0  
2.5  
3.0  
3.5  
4.0  
2.5  
3.0  
3.5  
4.0  
2.5  
3.0  
3.5  
4.0  
3.0  
3.5  
5.0  
6.0  
3.5  
4.5  
5.5  
6.5  
4.0  
5.0  
7.0  
8.0  
5.0  
6.0  
10.0  
11.0  
8.0  
ns  
ns  
ns  
ns  
SS  
register  
Synchronous clock setup time, T-type  
register  
t
SST  
Asynchronous clock setup time, D-type  
register  
t
SA  
Asynchronous clock setup time, T-type  
register  
t
9.0  
SAT  
t
Synchronous clock hold time  
0.0  
2.5  
0.0  
2.5  
0.0  
2.5  
0.0  
3.0  
0.0  
3.5  
0.0  
4.0  
0.0  
5.0  
0.0  
8.0  
ns  
ns  
HS  
t
Asynchronous clock hold time  
Synchronous clock to internal output  
Synchronous clock to output  
HA  
t
2.5  
4.0  
5.0  
6.5  
2.5  
4.0  
5.0  
6.5  
2.8  
4.5  
5.0  
6.8  
3.0  
5.0  
5.0  
7.0  
3.0  
5.5  
6.0  
8.5  
3.0  
6.0  
3.5  
6.5  
3.5 ns  
6.5 ns  
12.0 ns  
15.0 ns  
COSi  
t
COS  
t
Asynchronous clock to internal output  
Asynchronous clock to output  
8.0  
10.0  
13.0  
COAi  
t
11.0  
COA  
Latched Delays:  
t
Synchronous latch setup time  
Asynchronous latch setup time  
Synchronous latch hold time  
Asynchronous latch hold time  
Transparent latch to internal output  
4.0  
3.0  
0.0  
3.0  
4.0  
3.0  
0.0  
3.0  
4.0  
3.5  
0.0  
3.5  
4.5  
3.5  
0.0  
3.5  
6.0  
4.0  
0.0  
4.0  
7.0  
4.0  
0.0  
4.0  
8.0  
5.0  
0.0  
5.0  
10.0  
8.0  
0.0  
8.0  
ns  
SSL  
t
ns  
ns  
SAL  
t
HSL  
t
ns  
HAL  
t
5.5  
7.0  
5.5  
7.0  
5.8  
7.5  
6.0  
8.0  
7.5  
9.0  
11.0  
14.0  
12.0 ns  
PDLi  
Propagation delay through transparent  
latch to output  
t
10.0  
12.0  
15.0 ns  
PDL  
t
Synchronous gate to internal output  
Synchronous gate to output  
3.0  
4.5  
6.0  
7.5  
3.0  
4.5  
6.0  
7.5  
3.0  
4.8  
6.0  
7.8  
3.0  
5.0  
6.0  
8.0  
3.5  
6.0  
4.5  
7.5  
7.0  
8.0 ns  
11.0 ns  
15.0 ns  
18.0 ns  
GOSi  
t
10.0  
13.0  
16.0  
GOS  
t
Asynchronous gate to internal output  
Asynchronous gate to output  
8.5  
10.0  
13.0  
GOAi  
t
11.0  
GOA  
Input Register Delays:  
t
Input register setup time  
1.5  
2.5  
1.5  
2.5  
2.0  
3.0  
2.0  
3.0  
2.0  
3.0  
2.0  
3.0  
2.0  
3.0  
2.0  
4.0  
ns  
ns  
SIRS  
t
Input register hold time  
HIRS  
t
Input register clock to internal feedback  
3.0  
3.0  
3.0  
3.0  
3.5  
4.5  
6.0  
6.0 ns  
ICOSi  
Input Latch Delays:  
t
Input latch setup time  
1.5  
2.5  
1.5  
2.5  
1.5  
2.5  
2.0  
3.0  
2.0  
3.0  
2.0  
3.0  
2.0  
3.0  
2.0  
4.0  
ns  
ns  
SIL  
t
Input latch hold time  
HIL  
t
Input latch gate to internal feedback  
3.5  
1.5  
3.5  
1.5  
3.8  
1.5  
4.0  
1.5  
4.0  
2.0  
4.0  
2.0  
4.0  
2.0  
5.0 ns  
IGOSi  
Transparent input latch to internal  
feedback  
t
2.0 ns  
PDILi  
38  
ispMACH 4A Family  
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)  
-5  
-55  
-6  
-65  
-7  
-10  
-12  
-14  
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit  
Input Register Delays with ZHT Option:  
t
Input register setup time - ZHT  
Input register hold time - ZHT  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
ns  
ns  
SIRZ  
t
HIRZ  
Input Latch Delays with ZHT Option:  
t
Input latch setup time - ZHT  
Input latch hold time - ZHT  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
6.0  
0.0  
ns  
ns  
SILZ  
t
HILZ  
t
Transparent input latch to internal  
feedback - ZHT  
PDIL  
Zi  
6.0  
6.0  
6.0  
6.0  
6.0  
6.0  
6.0  
6.0 ns  
Output Delays:  
t
Output buffer delay  
Slow slew rate delay adder  
Output enable time  
1.5  
2.5  
7.5  
7.5  
1.5  
2.5  
7.5  
7.5  
1.8  
2.5  
8.5  
8.5  
2.0  
2.5  
8.5  
8.5  
2.5  
2.5  
9.5  
9.5  
3.0  
2.5  
3.0  
2.5  
3.0 ns  
2.5 ns  
15.0 ns  
15.0 ns  
BUF  
t
SLW  
t
10.0  
10.0  
12.0  
12.0  
EA  
t
Output disable time  
ER  
Power Delay:  
Power-down mode delay adder  
Reset and Preset Delays:  
Asynchronous reset or preset to internal  
t
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5 ns  
PL  
t
7.5  
9.0  
7.7  
9.2  
8.0  
8.0  
9.5  
11.0  
14.0  
13.0  
16.0  
16.0 ns  
19.0 ns  
SRi  
register output  
Asynchronous reset or preset to register  
output  
t
10.0  
10.0  
12.0  
SR  
Asynchronous reset and preset register  
recovery time  
t
7.0  
7.0  
7.0  
7.0  
7.5  
8.0  
7.5  
8.0  
8.0  
8.0  
10.0  
12.0  
15.0  
15.0  
ns  
ns  
SRR  
t
Asynchronous reset or preset width  
10.0  
10.0  
SRW  
Clock/LE Width:  
t
Global clock width low  
2.0  
2.0  
3.0  
3.0  
2.0  
2.0  
3.0  
3.0  
2.5  
2.5  
3.5  
3.5  
2.5  
2.5  
3.5  
3.5  
3.0  
3.0  
4.0  
4.0  
4.0  
4.0  
5.0  
5.0  
5.0  
5.0  
8.0  
8.0  
6.0  
6.0  
9.0  
9.0  
ns  
ns  
ns  
ns  
WLS  
t
Global clock width high  
WHS  
t
Product term clock width low  
Product term clock width high  
WLA  
t
WHA  
Global gate width low (for low  
transparent) or high (for high  
transparent)  
t
4.0  
4.0  
4.0  
4.0  
4.5  
4.5  
4.5  
4.5  
5.0  
5.0  
5.0  
5.0  
6.0  
6.0  
6.0  
9.0  
ns  
ns  
GWS  
Product term gate width low (for low  
transparent) or high (for high  
transparent)  
t
GWA  
t
Input register clock width low  
Input register clock width high  
Input latch gate width  
3.0  
3.0  
4.0  
3.0  
3.0  
4.0  
3.5  
3.5  
4.5  
3.5  
3.5  
4.5  
4.0  
4.0  
5.0  
5.0  
5.0  
5.0  
6.0  
6.0  
6.0  
6.0  
6.0  
6.0  
ns  
ns  
ns  
WIRL  
t
WIRH  
t
WIL  
ispMACH 4A Family  
39  
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)  
-5  
-55  
-6  
-65  
-7  
-10  
-12  
-14  
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit  
Frequency:  
External feedback, D-type, Min of  
1/(t + t ) or 1/(t + t  
143  
125  
182  
154  
250  
111  
105  
133  
125  
167  
167  
133  
125  
167  
154  
250  
111  
105  
133  
125  
167  
167  
125  
118  
160  
148  
200  
108  
102  
125  
125  
143  
143  
118  
111  
154  
143  
200  
100  
95.2  
125  
118  
143  
143  
95.2  
87.0  
125  
111  
154  
83.3  
76.9  
105  
95.2  
125  
125  
87.0  
80.0  
118  
105  
125  
66.7  
62.5  
83.3  
76.9  
100  
100  
74.1  
69.0  
95.0  
87.0  
100  
60.6  
57.1  
74.1  
69.0  
83.3  
43.5  
41.7  
50.0  
47.6  
55.6  
83.3  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
)
SS COS  
WLS WHS  
Externalfeedback, T-type, Minof 1/(t  
WLS  
+ t ) or 1/(t + t  
)
WHS  
SST COS  
Internal feedback (f ), D-type, Min of  
CNT  
f
MAXS  
1/(t + t ) or 1/(t + t  
)
WLS WHS  
SS COSi  
Internal feedback (f ), T-type, Min of  
CNT  
1/(t + t ) or 1/(t + t  
)
WLS WHS  
2
SST COSi  
No feedback , Min of 1/(t + t ),  
WLS WHS  
1/(t + t ) or 1/(t + t )  
SS HS  
SST HS  
External feedback, D-type, Min of 1/  
(t + t ) or 1/(t + t  
55.6  
52.6  
66.7  
62.5  
62.5  
83.3  
)
SA COA  
WLA WHA  
External feedback, T-type, Min of 1/(t  
WLA  
+ t ) or 1/(t + t  
)
WHA  
SAT COA  
Internal feedback (f ), D-type, Min of  
CNTA  
f
MAXA  
1/(t + t ) or 1/(t + t  
)
WLA WHA  
SA COAi  
Internal feedback (f ), T-type, Min of  
CNTA  
1/(t + t ) or 1/(t + t  
)
WLA WHA  
2
SAT COAi  
No feedback , Min of 1/(t + t ),  
WLA WHA  
1/(t + t ) or 1/(t + t )  
SA HA  
SAT HA  
Maximum input register frequency, Min  
f
MAXI  
of 1/(t  
+ t ) or 1/(t + t  
)
WIRH WIRL  
SIRS HIRS  
Notes:  
1. See “Switching Test Circuit”document on the Literature Download page of the Lattice web site.  
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.  
CAPACITANCE 1  
Parameter Symbol  
Parameter Description  
Input capacitance  
Test Conditions  
3.3 V or 5 V, 25°C, 1 MHz  
3.3 V or 5 V, 25°C, 1 MHz  
Typ  
6
Unit  
pF  
C
V =2.0 V  
IN  
IN  
C
Output capacitance  
V
=2.0V  
8
pF  
I/O  
OUT  
Note:  
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified  
where this parameter may be affected.  
40  
ispMACH 4A Family  
ICC vs. FREQUENCY  
These curves represent the typical power consumption for a particular device at system frequen-  
cy.The selected “typical”pattern is a 16-bit up-down counter.This pattern fills the device and ex-  
ercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register.  
Power/Speed are optimized to obtain the highest counter frequency and the lowest power.The  
highest frequency (LSBs) is placed in common PAL blocks, which are set to high power.The low-  
est frequency signals (MSBs) are placed in a common PAL block and set to lowest power.  
V
= 5 V or 3.3 V, T = 25º C  
M4A-512/160  
CC  
A
400  
350  
300  
250  
200  
150  
100  
M4A-384/160  
M4A-256/160  
M4A-256/128  
M4A-192/96  
M4A-96/48  
M4A-128/64  
M4A-64/64  
M4A-64/32  
50  
0
M4A-32/32  
Frequency (MHz)  
Figure 19. ispMACH 4A I Curves at High Speed Mode  
CC  
M4A-512/160  
V
= 5 V or 3.3 V, T = 25º C  
250  
200  
150  
100  
50  
CC  
A
M4A-384/160  
M4A-256/160  
M4A-256/128  
M4A-192/96  
M4A-96/48  
M4A-128/64  
M4A-64/64  
M4A-64/32  
M4A-32/32  
0
Frequency (MHz)  
Figure 20. ispMACH 4A I Curves at Low Pow er Mode  
CC  
ispMACH 4A Family  
41  
44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)  
Top View  
44-Pin PLCC  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
40  
1 44 43 42 41  
6
5
4
3
2
39  
I/O27 D3  
I/O26 D2  
I/O25 D1  
I/O24 D0  
TDO  
B3  
B2  
B1  
B0  
7
A2  
A1  
A0  
A2 I/O5  
A1 I/O6  
A0 I/O7  
TDI  
38  
8
37  
36  
35  
34  
9
C
7
10  
11  
12  
CLK0/I0  
GND  
M4A(3,5)-32/32  
M4A(3,5)-32/32  
GND  
I/O Cell  
PAL Block  
CLK1/I1  
TMS  
33  
32  
31  
30  
29  
TCK  
13  
14  
15  
16  
17  
A8  
A9  
B0 I/O8  
B1 I/O9  
B2 I/O10  
B3 I/O11  
C0  
C1  
C2  
B8  
I/O23  
I/O22  
I/O21  
B9  
A10  
A11  
B10  
28  
18 19 20 21 22 23 24 25 26 27  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
17466G-026  
PIN DESIGNATIONS  
CLK/I = Clock or Input  
GND = Ground  
I/O  
= Input/Output  
= Supply Voltage  
V
CC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
42  
ispMACH 4A Family  
44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)  
Top View  
44-Pin TQFP  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
1
2
3
4
5
6
7
8
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A2  
A1  
A0  
A2  
A1  
A0  
I/O5  
I/O6  
I/O7  
TDI  
I/O27 D3  
I/O26 D2  
I/O25 D1  
I/O24 D0  
TDO  
GND  
CLK1/I1  
TMS  
B3  
B2  
B1  
B0  
C
7
M4A(3,5)-32/32  
CLK0/I0  
GND  
I/O Cell  
PAL Block  
M4A(3,5)-32/32  
TCK  
I/O8  
I/O9  
A8  
A9  
A10  
A11  
B0  
B1  
B2 I/O10  
B3 I/O11  
9
10  
11  
I/O23  
I/O22  
I/O21  
C0  
C1  
C2  
B8  
B9  
B10  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
PIN DESIGNATIONS  
CLK/I = Clock or Input  
GND = Ground  
I/O  
= Input/Output  
= Supply Voltage  
V
CC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
ispMACH 4A Family  
43  
48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)  
Top View  
48-Pin TQFP  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
A2  
A1  
A0  
A2 I/O5  
A1 I/O6  
A0 I/O7  
TDI  
CLK0/I0  
NC  
1
2
3
4
5
6
7
8
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
I/O27 D3  
I/O26 D2  
I/O25 D1  
I/O24 D0  
TDO  
B3  
B2  
B1  
B0  
C
7
M4A(3,5)-32/32  
GND  
NC  
M4A(3,5)-32/32  
I/O Cell  
PAL Block  
GND  
TCK  
CLK1/I1  
TMS  
I/O23 C0  
I/O22 C1  
I/O21 C2  
A8  
A9  
A10  
A11  
B0  
B1  
B2  
B3  
9
I/O8  
I/O9  
I/O10  
I/O11  
10  
11  
12  
B8  
B9  
B10  
M4A(3,5)-64/32  
M4A(3,5)-64/32  
17466G-028  
PIN DESIGNATIONS  
CLK/I = Clock or Input  
GND = Ground  
I/O  
= Input/Output  
= Supply Voltage  
= No Connect  
V
CC  
NC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
44  
ispMACH 4A Family  
100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48)  
Top View  
100-Pin TQFP  
NC  
TDI  
NC  
NC  
TDO  
NC  
NC  
NC  
1
2
3
4
5
6
7
8
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
A1  
A0  
B0  
B1  
I/O6  
I/O7  
I/O8  
I/O9  
I/O41  
I/O40  
I/O39  
I/O38  
I/O37  
I/O36  
I5/CLK3  
GND  
VCC  
I4/CLK2  
I/O35  
I/O34  
I/O33  
I/O32  
I/O31  
I/O30  
NC  
F1  
F0  
E0  
E1  
E2  
E3  
B2 I/O10  
B3 I/O11  
I0/CLK0  
VCC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
C
7
GND  
I1/CLK1  
B4 I/O12  
B5 I/O13  
B6 I/O14  
B7 I/O15  
C0 I/O16  
C1 I/O17  
NC  
I/O Cell  
E4  
E5  
E6  
E7  
D0  
D1  
PAL Block  
NC  
TMS  
TCK  
NC  
NC  
NC  
NC  
17466G-029  
PIN DESIGNATIONS  
CLK/I = Clock or Input  
GND = Ground  
I
= Input  
I/O  
= Input/Output  
= Supply Voltage  
= No Connect  
V
CC  
NC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
ispMACH 4A Family  
45  
100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64)  
Top View  
100-Pin PQFP  
1
2
80  
79  
78  
77  
GND  
GND  
TD0  
TRST  
I/O55  
I/O54  
I/O53  
I/O52  
I/O51  
GND  
GND  
TDI  
I5  
I/O8  
I/O9  
I/O10  
I/O11  
3
4
5
6
7
8
9
(83)  
(12)  
(13)  
(14)  
(15)  
(16)  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
G7  
G6  
G5  
G4  
G3  
G2  
G1  
G0  
(73) 76  
(72) 75  
(71) 74  
(70) 73  
(69) 72  
I/O12  
10(17)  
11 (18)  
12(19)  
13(20)  
14  
I/O13  
I/O14  
I/O15  
IO/CLK0  
I/O50  
I/O49  
I/O48  
I4/CLK3  
GND  
(68) 71  
(67) 70  
(66) 69  
(65) 68  
67  
C
7
V
CC  
V
CC  
GND  
15  
16  
66  
65  
64  
I/O Cell  
PAL Block  
V
GND  
CC  
V
CC  
17  
GND  
I1/CLK1  
I/O16  
(23)  
(24)  
(25)  
18  
19  
20  
I3/CLK2  
I/O47  
I/O46  
63  
62  
61  
(62)  
(61)  
(60)  
C0  
C1  
F0  
F1  
I/O17  
(26)  
(27)  
(28)  
(29)  
(30)  
(31)  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
C2  
C3  
C4  
C5  
C6  
C7  
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
TMS  
TCK  
GND  
GND  
I/O45  
I/O44  
I/O43  
I/O42  
I/O41  
I/O40  
I2  
ENABLE  
GND  
GND  
F2  
F3  
F4  
F5  
F6  
F7  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
(59)  
(58)  
(57)  
(56)  
(55)  
(54)  
(41)  
17466G-031  
PIN DESIGNATIONS  
I/CLK = Input or Clock  
GND = Ground  
I
= Input  
I/O  
= Input/Output  
= Supply Voltage  
V
CC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
TRST = Test Reset  
ENABLE = Program  
46  
ispMACH 4A Family  
100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64)  
Top View  
100-Pin TQFP  
M4A3-128/64  
M4A5-128/64  
M4A3-64/64  
GND  
TDI  
I/O8  
GND  
TDO  
1
2
3
4
5
6
7
8
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
TRST  
I/O55  
I/O54  
I/O53  
I/O52  
I/O51  
I/O50  
I/O49  
I/O48  
I4/CLK3  
GND  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
A1  
A3  
A5  
A7  
A9  
A11  
A13  
A15  
I/O9  
D1  
D3  
D5  
D7  
G7  
G6  
G5  
G4  
G3  
G2  
G1  
G0  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
I0/CLK0  
D9  
C
7
D11  
D13  
D15  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
V
CC  
GND  
I1/CLK1  
I/O16  
I/O17  
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
TMS  
I/O Cell  
V
CC  
I3/CLK2  
I/O47  
I/O46  
I/O45  
I/O44  
I/O43  
I/O42  
I/O41  
I/O40  
ENABLE  
GND  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
B15  
B13  
B11  
B9  
B7  
B5  
C15  
C13  
C11  
C9  
C7  
C5  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
PAL Block  
B3  
B1  
C3  
C1  
TCK  
GND  
17466G-032a  
PIN DESIGNATIONS  
CLK/I = Clock or Input  
GND = Ground  
I
= Input  
I/O  
= Input/Output  
= Supply Voltage  
V
CC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
TRST = Test Reset  
ENABLE = Program  
ispMACH 4A Family  
47  
100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64)  
Bottom View  
100-Ball caBGA  
10  
9
8
7
6
5
4
3
2
1
I/O63  
H7  
I/O60  
H4  
I/O57  
H1  
I/O1  
A1  
I/O4  
A4  
I/O7  
A7  
GND  
GND  
GND  
GND  
A
B
C
D
E
F
A
B
C
D
E
F
I/O61  
H5  
I/O0  
A0  
I/O6  
A6  
I/O15  
B7  
TRST  
GND  
TDO  
I5  
VCC  
GND  
TDI  
I/O53  
G5  
I/O62  
H6  
I/O58  
H2  
I/O56  
H0  
I/O2  
A2  
I/O14  
B6  
I/O13  
B5  
I/O12  
B4  
GND  
I/O50  
G2  
I/O55  
G7  
I/O59  
H3  
I/O3  
A3  
I/O5  
A5  
I/O11  
B3  
I/O10  
B2  
I/O9  
B1  
GND  
CLK0/I0  
VCC  
I/O49  
G1  
I/O51  
G3  
I/O54  
G6  
I/O16  
C0  
I/O20  
C4  
I/O8  
B0  
VCC  
GND  
CLK3/I3  
GND  
I/O40  
F0  
I/O52  
G4  
I/O48  
G0  
I/O22  
C6  
I/O19  
C3  
I/O17  
C1  
VCC  
VCC  
CLK1/I1  
I/O41  
F1  
I/O42  
F2  
I/O43  
F3  
I/O37  
E5  
I/O35  
E3  
I/O27  
D3  
I/O23  
C7  
I/O18  
C2  
CLK2/I2  
GND  
G
H
J
G
H
J
I/O44  
F4  
I/O45  
F5  
I/O46  
F6  
I/O34  
E2  
I/O24  
D0  
I/O26  
D2  
I/O30  
D6  
I/O21  
C5  
GND  
TCK  
I/O47  
F7  
I/O38  
E6  
I/O32  
E0  
I/O29  
D5  
ENABLE  
GND  
VCC  
I2  
GND  
TMS  
I/O39  
E7  
I/O36  
E4  
I/O33  
E1  
I/O25  
D1  
I/O28  
D4  
I/O31  
D7  
GND  
GND  
GND  
GND  
K
K
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
I/O Cell  
PAL Block  
Program  
17466G-100cabga  
48  
ispMACH 4A Family  
144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96)  
Top View  
144-Pin TQFP  
GND  
TDI  
1
2
3
4
5
6
7
8
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
GND  
TDO  
NC  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
I2  
I3  
VCC  
GND  
I4  
I/O8  
I/O9  
I/O10  
I/O11  
I/O12  
I/O13  
I/O14  
I/O15  
GND  
VCC  
I/O16  
I/O17  
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
TMS  
TCK  
GND  
I/O71 K0  
I/O70 K1  
I/O69 K2  
I/O68 K3  
I/O67 K4  
I/O66 K5  
I/O65 K6  
I/O64 K7  
I12  
VCC  
GND  
I11  
I10  
I/O63 J0  
I/O62 J1  
I/O61 J2  
I/O60 J3  
I/O59 J4  
I/O58 J5  
I/O57 J6  
I/O56 J7  
GND  
VCC  
I/O55  
I/O54  
I/O53  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
C
7
C7  
C6  
C5  
C4  
C3  
C2  
C1  
C0  
I/O Cell  
PAL Block  
E7  
E6  
E5  
E4  
E3  
E2  
E1  
E0  
I0  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
I/O52  
I/O51  
I/O50  
I/O49  
I/O48  
NC  
GND  
74  
73  
17466G-033  
PIN DESIGNATIONS  
CLK = Clock  
GND = Ground  
I
= Input  
I/O  
= Input/Output  
= Supply Voltage  
V
CC  
TDI = Test Data In  
TCK = Test Clock  
TMS = Test Mode Select  
TDO = Test Data Out  
ispMACH 4A Family  
49  
144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96)  
Bottom View  
144-Ball fpBGA  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O95  
L7  
I/O91  
L3  
I/O2  
A2  
I/O6  
A6  
I/O8  
B0  
I/O13  
B5  
I/O15  
B7  
GND  
GBCLK3  
I0  
GND  
I13  
A
B
C
D
E
F
A
B
C
D
E
F
I/O94  
L6  
I/O90  
L2  
I/O88  
L0  
I/O3  
A3  
I/O7  
A7  
I/O10  
B2  
I/O14  
B6  
I/O31  
D7  
GND  
GND  
VCC  
GND  
I1  
TDI  
I/O93  
L5  
I/O0  
A0  
I/O4  
A4  
I/O12  
B4  
I/O30  
D6  
I/O27  
D3  
I/O28  
D4  
TDO  
I14  
GND  
I/O84  
K4  
I/O82  
K2  
I/O80  
K0  
I/O92  
L4  
I/O1  
A1  
I/O11  
B3  
I/O29  
D5  
I/O25  
D1  
I/O24  
D0  
GBCLK0  
VCC  
I2  
I4  
I/O87  
K7  
I/O85  
K5  
I/O81  
K1  
I/O89  
L1  
I/O5  
A5  
I/O9  
B1  
I/O26  
D2  
I/O23  
C7  
I12  
I10  
GND  
VCC  
I/086  
K6  
I/O83  
K3  
I/O19  
C3  
I/O20  
C4  
I/O21  
C5  
I/O22  
C6  
I11  
GND  
I15  
I3  
I7  
GND  
I/O75  
J3  
I/O74  
J2  
I/O73  
J1  
I/O72  
J0  
I/O35  
E3  
I/O38  
E6  
I/O16  
C0  
I/O17  
C1  
I/O18  
C2  
VCC  
GND  
G
H
J
G
H
J
I/O79  
J7  
I/O78  
J6  
I/O77  
J5  
I/O76  
J4  
I/O66  
I2  
I/O57  
H1  
I/O53  
G5  
I/O41  
F1  
I/O33  
E1  
I/O37  
E5  
I/O39  
E7  
VCC  
I/O64  
I0  
I/O65  
I1  
I/O69  
I5  
I/O59  
H3  
I/O49  
G1  
I/O44  
F4  
I/O32  
E0  
I/O34  
E2  
I/O36  
E4  
VCC  
VCC  
GBCLK2  
VCC  
I/O68  
I4  
I/O67  
I3  
I/O70  
I6  
I/O60  
H4  
I/O52  
G4  
I/O48  
G0  
I/O45  
F5  
GND  
I6  
TCK  
TMS  
GND  
K
L
K
L
I/O71  
I7  
I/O62  
H6  
I/O58  
H2  
I/O55  
G7  
I/O51  
G3  
I/O40  
F0  
I/O42  
F2  
I/O46  
F6  
GND  
I9  
GND  
I/O63  
H7  
I/O61  
H5  
I/O56  
H0  
I/O54  
G6  
I/O50  
G2  
I/O43  
F3  
I/O47  
F7  
GND  
I8  
GBCLK1  
I5  
GND  
M
M
12  
11  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
I/O Cell  
PAL Block  
Program  
m4a3.192.96_144bga  
50  
ispMACH 4A Family  
208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND  
M4A3-256/160)  
Top View  
208-Pin PQFP  
M4A3-256/160  
M4A(3, 5)-  
256/128  
GND  
TDI  
1
2
3
4
5
6
7
8
9
156 GND  
155 TDO  
GND  
TDO  
NC  
GND  
TDI  
RECOMMEND TO TIE TO VCC  
C7 I/O16  
C6 I/O17  
C5 I/O18  
C4 I/O19  
C3 I/O20  
C2 I/O21  
C1 I/O22  
154 TRST  
153 I/O111  
152 I/O110  
151 I/O109  
150 I/O108  
149 I/O107  
148 I/O106  
147 I/O105  
146 I/O104  
145 VCC  
C15 I/O20  
C14 I/O21  
C13 I/O22  
C12 I/O23  
C11 I/O24  
C10 I/O25  
C9 I/O26  
C8 I/O27  
VCC  
N7 I/O139 N15  
N6 I/O138 N14  
N5 I/O137 N13  
N4 I/O136 N12  
N3 I/O135 N11  
N2 I/O134 N10  
N1 I/O133 N9  
N0 I/O132 N8  
VCC  
C0 I/O23 10  
VCC 11  
GND 12  
GND  
D7 I/O24 13  
D6 I/O25 14  
D5 I/O26 15  
D4 I/O27 16  
D3 I/O28 17  
D2 I/O29 18  
D1 I/O30 19  
D0 I/O31 20  
I2 21  
144 GND  
GND  
C7 I/O28  
C6 I/O29  
C5 I/O30  
C4 I/O31  
C3 I/O32  
C2 I/O33  
C1 I/O34  
C0 I/O35  
D14 I/O36  
D12 I/O37  
GND  
143 I/O103 M7 I/O131 N7  
142 I/O102 M6 I/O130 N6  
141 I/O101 M5 I/O129 N5  
140 I/O100 M4 I/O128 N4  
PIN DESIGNATIONS  
139 I/O99  
138 I/O98  
137 I/O97  
136 I/O96  
135 I11  
134 GND  
133 VCC  
132 VCC  
131 GND  
130 GND  
129 VCC  
128 VCC  
127 GND  
126 I10  
M3 I/O127 N3  
M2 I/O126 N2  
M1 I/O125 N1  
M0 I/O124 N0  
I/O123 M10  
GND  
CLK  
GND  
I
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
I3 22  
GND 23  
VCC 24  
VCC 25  
GND 26  
GND 27  
VCC 28  
VCC 29  
I/O  
N/C  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
Test Mode Select  
Test Data Out  
Test Reset  
Program  
I/O122 M6  
I/O121 M2  
I/O120 M0  
I/O119 L4  
I/O118 L6  
VCC  
GND  
VCC  
D6 I/O38  
D4 I/O39  
E0 I/O40  
E2 I/O41  
E6 I/O42  
GND  
E10 I/O43  
F0 I/O44  
F1 I/O45  
F2 I/O46  
F3 I/O47  
F4 I/O48  
F5 I/O49  
F6 I/O50  
F7 I/O51  
GND  
GND 30  
I4 31  
I/O117 L12  
I/O116 L14  
L0 I/O115 K0  
L1 I/O114 K1  
L2 I/O113 K2  
L3 I/O112 K3  
L4 I/O111 K4  
L5 I/O110 K5  
L6 I/O109 K6  
L7 I/O108 K7  
GND  
C
7
E0 I/O32 32  
E1 I/O33 33  
E2 I/O34 34  
E3 I/O35 35  
E4 I/O36 36  
E5 I/O37 37  
E6 I/O38 38  
E7 I/O39 39  
GND 40  
125 I9  
I/O Cell  
PAL Block  
124 I/O95  
123 I/O94  
122 I/O93  
121 I/O92  
120 I/O91  
119 I/O90  
118 I/O89  
117 I/O88  
116 GND  
115 VCC  
114 I/O87  
113 I/O86  
112 I/O85  
111 I/O84  
110 I/O83  
109 I/O82  
108 I/O81  
107 I/O80  
VCC 41  
VCC  
F0 I/O40 42  
F1 I/O41 43  
F2 I/O42 44  
F3 I/O43 45  
F4 I/O44 46  
F5 I/O45 47  
F6 I/O46 48  
F7 I/O47 49  
TMS 50  
VCC  
F8 I/O52  
F9 I/O53  
F10 I/O54  
F11 I/O55  
F12 I/O56  
F13 I/O57  
F14 I/O58  
F15 I/O59  
TMS  
K0 I/O107 K8  
K1 I/O106 K9  
K2 I/O105 K10  
K3 I/O104 K11  
K4 I/O103 K12  
K5 I/O102 K13  
K6 I/O101 K14  
K7 I/O100 K15  
NC  
TCK 51  
GND 52  
RECOMMEND TO TIE TO GND 106 ENABLE  
TCK  
GND  
105 GND  
GND  
17466G-044  
ispMACH 4A Family  
51  
208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160)  
Top View  
208-Pin PQFP  
M4A3-512/160  
M4A3-384/160  
GND  
TDI  
GND  
TDI  
1
2
3
4
5
6
7
8
9
156 GND  
155 TDO  
154 NC  
GND  
TDO  
NC  
F7  
F6  
F5  
F4  
F3  
F2  
F1  
F0  
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
I/O24  
I/O25  
VCC  
GND  
I/O26  
I/O27  
I/O28  
I/O29  
I/O30  
I/O31  
I/O32  
I/O33  
I/O34  
I/O35  
GND  
VCC  
I/O36  
I/O37  
I/O38  
I/O39  
I/O40  
GND  
I/O41  
I/O42  
I/O43  
I/O44  
I/O45  
I/O46  
I/O47  
I/O48  
I/O49  
GND  
VCC  
RECOMMEND TO TIE TO VCC  
C7 I/O18  
C6 I/O19  
C5 I/O20  
C4 I/O21  
C3 I/O22  
C2 I/O23  
C1 I/O24  
153 I/O137 XF7  
152 I/O136 XF6  
151 I/O135 XF5  
150 I/O134 XF4  
149 I/O133 XF3  
148 I/O132 XF2  
147 I/O131 XF1  
146 I/O130 XF0  
145 VCC  
I/O137 XK7  
I/O136 XK6  
I/O135 XK5  
I/O134 XK4  
I/O133 XK3  
I/O132 XK2  
I/O131 XK1  
I/O130 XK0  
VCC  
C0 I/O25 10  
VCC 11  
GND 12  
G7  
G6  
G5  
G4  
G3  
G2  
G1  
G0  
E7  
E5  
F7 I/O26 13  
F6 I/O27 14  
F5 I/O28 15  
F4 I/O29 16  
F3 I/O30 17  
F2 I/O31 18  
F1 I/O32 19  
F0 I/O33 20  
E7 I/O34 21  
E5 I/O35 22  
GND 23  
144 GND  
GND  
143 I/O129 XC7  
142 I/O128 XC6  
141 I/O127 XC5  
140 I/O126 XC4  
139 I/O125 XC3  
138 I/O124 XC2  
137 I/O123 XC1  
136 I/O122 XC0  
135 I/O121 XD5  
134 GND  
133 I/O120 XD3  
132 I/O119 XD2  
131 I/O118 XD0  
130 I/O117 XA0  
129 I/O116 XA2  
128 VCC  
I/O129 XJ7  
I/O128 XJ6  
I/O127 XJ5  
I/O126 XJ4  
I/O125 XJ3  
I/O124 XJ2  
I/O123 XJ1  
I/O122 XJ0  
I/O121 XL5  
GND  
I/O120 XL3  
I/O119 XL2  
I/O118 XL0  
I/O117 XE0  
I/O116 XE2  
VCC  
PIN DESIGNATIONS  
CLK  
GND  
I
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
I/O  
N/C  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
Test Mode Select  
Test Data Out  
Test Reset  
Program  
VCC 24  
E2  
E0  
L0  
L2  
L3  
E2 I/O36 25  
E0 I/O37 26  
H0 I/O38 27  
H2 I/O39 28  
H3 I/O40 29  
GND 30  
H5 I/O41 31  
G0 I/O42 32  
G1 I/O43 33  
G2 I/O44 34  
G3 I/O45 35  
G4 I/O46 36  
G5 I/O47 37  
G6 I/O48 38  
G7 I/O49 39  
GND 40  
127 GND  
GND  
L5  
J0  
J1  
J2  
J3  
J4  
J5  
J6  
J7  
126 I/O115 XA5  
125 I/O114 XA7  
124 I/O113 XB0  
123 I/O112 XB1  
122 I/O111 XB2  
121 I/O110 XB3  
120 I/O109 XB4  
119 I/O108 XB5  
118 I/O107 XB6  
117 I/O106 XB7  
116 GND  
I/O115 XE5  
I/O114 XE7  
I/O113 XG0  
I/O112 XG1  
I/O111 XG2  
I/O110 XG3  
I/O109 XG4  
I/O108 XG5  
I/O107 XG6  
I/O106 XG7  
GND  
C
7
I/O Cell  
PAL Block  
VCC 41  
K0  
K1  
K2  
K3  
K4  
K5  
K6  
K7  
I/O50  
I/O51  
I/O52  
I/O53  
I/O54  
I/O55  
I/O56  
I/O57  
TMS  
J0 I/O50 42  
J1 I/O51 43  
J2 I/O52 44  
J3 I/O53 45  
J4 I/O54 46  
J5 I/O55 47  
J6 I/O56 48  
J7 I/O57 49  
TMS 50  
115 VCC  
VCC  
114 I/O105  
113 I/O104  
112 I/O103  
111 I/O102  
110 I/O101  
109 I/O100  
108 I/O99  
107 I/O98  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
I/O105 XF0  
I/O104 XF1  
I/O103 XF2  
I/O102 XF3  
I/O101 XF4  
I/O100 XF5  
I/O99 XF6  
I/O98 XF7  
NC  
TCK  
GND  
TCK 51  
GND 52  
RECOMMEND TO TIE TO GND 106 NC  
105 GND  
GND  
17466Ga-044  
52  
ispMACH 4A Family  
256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128)  
Bottom View  
256-Ball BGA  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O108  
N4  
I/O105  
N1  
I/O100  
M4  
I/O96  
M0  
I/O95  
L0  
I/O91  
L4  
I/O87  
K0  
A
GND  
N/C  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
N/C  
GND  
GND  
GND  
A
I/O113  
O6  
I/O109  
N5  
I/O106 I/O103  
N2 M7  
I/O102  
M6  
I/O98  
M2  
I/O93  
L2  
I/O89  
L6  
I/O88  
L7  
I/O85  
K2  
I/O83  
K4  
I/O82  
K5  
B
C
D
E
F
GND  
N/C  
N/C  
I11  
N/C  
I10  
I9  
N/C  
N/C  
GND  
B
C
D
E
F
I/O116  
O3  
I/O111 I/O107  
I/O104 I/O101  
N0  
I/O97  
M1  
I/O94  
L1  
I/O90  
L5  
I/O86  
K1  
I/O84  
K3  
I/O80  
K7  
I/O78  
J6  
I/O74  
J2  
N/C  
VCC  
TRST  
VCC  
TDI  
N/C  
N/C  
ENABLE VCC  
N7  
N3  
M5  
I/O120  
P7  
I/O117  
O2  
I/O112  
O7  
I/O110  
N6  
I/O99  
M3  
I/O92  
L3  
I/O81  
K6  
I/O79  
I/O75  
J3  
I/O71  
I7  
VCC  
VCC  
N/C  
N/C  
VCC  
VCC  
VCC  
J7  
I/O123  
P4  
I/O119  
O0  
I/O114  
O5  
I/O77  
I/O72  
J0  
I/O68  
I4  
TDO  
J5  
I/O122  
P5  
I/O118 I/O115  
I/O76  
J4  
I/O73  
J1  
I/O69  
I5  
GND  
GND  
O1  
O4  
I/O125 I/O121  
P2 P6  
I/O70  
I6  
I/O65  
I1  
G
H
I12  
VCC  
VCC  
I8  
G
H
PIN DESIGNATIONS  
I/O127 I/O126 I/O124  
I/O67  
I3  
I/O66  
I2  
I/O64  
I0  
GND  
GND  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
Test Mode Select  
Test Data Out  
Test Reset  
P0  
P1  
P3  
J
N/C  
N/C  
N/C  
I13  
I7  
N/C  
N/C  
N/C  
N/C  
N/C  
J
K
GND  
CLK3  
CLK0  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
I0  
N/C  
CLK2  
K
VCC  
TDI  
L
N/C  
N/C  
N/C  
I6  
N/C  
N/C  
CLK1  
GND  
L
TCK  
TMS  
TDO  
TRST  
ENABLE  
I/O63  
H0  
I/O62  
H1  
M
C
7
M
I/O Cell  
I/O0  
A0  
I/O2  
A2  
I/O3  
A3  
I/O60  
H3  
I/O61  
H2  
I/O59  
H4  
Program  
N
P
R
T
GND  
I1  
GND  
I5  
N
P
R
T
PAL Block  
I/O1  
A1  
I/O6  
A6  
I/O57  
H6  
I/O58  
H5  
VCC  
N/C  
VCC  
I/O5  
A5  
I/O9  
B1  
I/O51  
G4  
I/O54  
G1  
I/O56  
H7  
GND  
GND  
N/C  
I/O4  
A4  
I/O8  
B0  
I/O12  
B4  
I/O50  
G5  
I/O55  
G0  
TCK  
TMS  
VCC  
I/O7  
A7  
I/O11  
B3  
I/O15  
B7  
I/O48  
G7  
I/O53  
G2  
I/O18  
C5  
I/O24  
D7  
I/O29  
D2  
I/O35  
E3  
U
V
VCC  
VCC  
VCC  
I2  
I3  
N/C  
N/C  
N/C  
VCC  
N/C  
VCC  
N/C  
N/C  
U
V
I/O10  
B2  
I/O13  
B5  
I/O16  
C7  
I/O17  
C6  
I/O21  
C2  
I/O23  
C0  
I/O27  
D4  
I/O31  
D0  
I/O33  
E1  
I/O37  
E5  
I/O41  
F1  
I/O43  
F3  
I/O46  
F6  
I/O47  
F7  
I/O52  
G3  
VCC  
N/C  
VCC  
N/C  
I/O14  
B6  
I/O19  
C4  
I/O22  
C1  
I/O25  
D6  
I/O28  
D3  
I/O34  
E2  
I/O38  
E6  
I/O39  
E7  
I/O42  
F2  
I/O45  
F5  
I/O49  
G6  
W
Y
W
Y
GND  
N/C  
N/C  
N/C  
I4  
N/C  
GND  
I/O20  
C3  
I/O26  
D5  
I/O30  
D1  
I/O32  
E0  
I/O36  
E4  
I/O40  
F0  
I/O44  
F4  
GND  
GND  
GND  
N/C  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
N/C  
GND  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
17466G-045  
ispMACH 4A Family  
53  
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192)  
Bottom View  
256-Ball fpBGA  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O167 I/O181 I/O180 I/O177 I/O174 I/O172 I/O191 I/O186 I/O1  
N15 O13 O12 O9 O6 O4 P14 P4 A2  
I/O3  
A6  
I/O9  
B1  
I/O13 I/O15 I/O18 I/O20  
GCLK0  
A
B
C
D
E
F
A
B
C
D
E
F
B5  
B7  
B10  
B12  
I/O165 I/O166 I/O182 I/O179 I/O175 I/O173 I/O168 I/O187 I/O0  
I/O5  
A10  
I/O7  
A14  
I/O10 I/O16 I/O19 I/O21  
B2  
NC  
N13  
N14  
O14  
O11  
O7  
O5  
O0  
P6  
A0  
B8  
B11  
B13  
I/O163 I/O164  
N11 N12  
I/O183 I/O178 I/O170 I/O171 I/O189 I/O184 I/O6  
I/O12 I/O14 I/O23 I/O22  
I/O39  
C15  
NC  
TDI  
O15  
O10  
O2  
O3  
P10  
P0  
A12  
B4  
B6  
B15  
B14  
I/O158 I/O159  
I/O17 I/O38 I/O37  
B9 C14 C13  
TDO  
GND  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
VCC  
N6  
N7  
I/O156  
N4  
I/O162  
N10  
I/O160 I/O161 I/O190  
I/O188 I/O2  
P8  
I/O8  
B0  
I/O36 I/O35 I/O31  
C12 C11 C7  
NC  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
GCLK3  
NC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
N8  
N9  
P12  
A4  
I/O152 I/O157 I/O155  
N0 N5 N3  
I/O154 I/O153 I/O176 I/O169 I/O185 I/O4  
I/O11 I/O34  
B3 C10  
I/O32 I/O30 I/O29  
C8 C6 C5  
N2  
N1  
O8  
O1  
P2  
A8  
I/O147 I/O150 I/O149  
M6 M12 M10  
I/O148 I/O151  
M8 M14  
I/O33 I/O28  
C9 C4  
I/O26 I/O25 I/O47  
C2 C1 D14  
VCC  
GND  
GND  
VCC  
G
H
J
G
H
J
I/O144 I/O146 I/145  
M0 M4 OM2  
I/O136 I/O137  
L0 L2  
I/O27 I/O24  
C3 C0  
I/O44 I/O43 I/O42  
D8 D6 D4  
GND  
GND  
VCC  
VCC  
VCC  
GND  
VCC  
VCC  
GND  
GND  
GND  
VCC  
I/O138 I/O139 I/O140  
L4 L6 L8  
I/O142 I/O141  
L12 L10  
I/O46 I/O45  
D12 D10  
I/O49 I/O48 I/O50  
E2 E0 E4  
I/O143 I/O120 I/O121  
L14 K0 K1  
I/O123 I/O122  
K3 K2  
I/O41 I/O40  
D2 D0  
I/O55 I/O54 I/O56  
E14 E12 F0  
K
L
K
L
I/O124 I/O125 I/O127  
K4 K5 K7  
I/O130 I/O126 I/O98 I/O91 I/O75 I/O77 I/O52 I/O51  
K10 K6 I4 H6 G3 G5 E8 E6  
I/O59 I/O60 I/O57  
F3 F4 F1  
I/O128 I/O129 I/O131  
K8 K9 K11  
I/O107 I/O105 I/O100 I/O90 I/O74 I/O80 I/O83 I/O53  
I/O68 I/O63 I/O58  
M
N
P
R
T
M
N
P
R
T
J3  
J1  
I8  
H4  
G2  
G8  
G11  
E10  
F12  
F7  
F2  
I/O132 I/O133 I/O135  
K12 K13 K15  
I/O64 I/O61  
F8 F5  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
TCK  
I/O134 I/O117 I/O118 I/O119 I/O108 I/O106 I/O101 I/O89 I/O93 I/O94 I/O79 I/O84 I/O87  
K14 J13 J14 J15 J4 J2 I10 H2 H10 H12 G7 G12 G15  
I/O65 I/O62  
F9 F6  
TMS  
I/O116 I/O115 I/O112 I/O111 I/O104 I/O102 I/O99 I/O96 I/O92 I/O72 I/O76 I/O81 I/O85 I/O71 I/O67 I/O66  
J12  
J11  
J8  
J7  
J0  
I12  
I6  
I0  
H8  
G0  
G4  
G9  
G13  
F15  
F11  
F10  
I/O114 I/O113 I/O110 I/O109 I/O103  
I/O97 I/O88  
I/O95 I/O73 I/O78 I/O82 I/O86 I/O70 I/O69  
H14  
GCLK2  
GCLK1  
J10  
J9  
J6  
J5  
I14  
I2  
H0  
G1  
G6  
G10  
G14  
F14  
F13  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
I/O Cell  
17466G-047  
Program  
PAL Block  
54  
ispMACH 4A Family  
256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192)  
Bottom View  
256-Ball BGA  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O11  
XF7  
I/O44  
XF6  
I/O58  
XC6  
I/O70  
XC2  
I/O76  
XD6  
I/O108  
XA5  
I/O116  
XB0  
I/O128 I/O134  
XB7 O3  
A
B
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
A
B
I/O12  
XG7  
I/O28  
XF5  
I/O45  
XF3  
I/O59  
XC7  
I/O64  
XC5  
I/O71  
XC3  
I/O77  
XD7  
I/O84  
XD5  
I/O90  
XD2  
I/O96  
XA0  
I/O102 I/O109  
I/O117  
XB1  
I/O122 I/O129 I/O135 I/O148 I/O164  
GND  
GND  
XA3  
XA6  
XB4  
XB6  
O4  
O6  
O7  
I/O13  
XG5  
I/O46  
XF4  
I/O91  
XD1  
I/O97  
XA1  
I/O136  
O5  
I/O0  
XG6  
I/O60  
XF2  
I/O65  
XF1  
I/O72  
XC4  
I/O78  
XC0  
I/O85  
XD4  
I/O103  
XA4  
I/O110  
XB2  
I/O118  
XB5  
I/O123 I/O130  
I/O165 I/O181  
N7 N6  
C
D
E
VCC  
VCC  
C
D
E
O0  
O1  
I/O1  
XE7  
I/O14  
XG3  
I/O29  
XG4  
I/O66  
XF0  
I/O79  
XC1  
I/O86  
XD3  
I/O92  
XD0  
I/O98  
XA2  
I/O104  
XA7  
I/O111  
XB3  
I/O124  
O2  
I/O149 I/O166 I/O182  
N4 N5 P7  
VCC  
TDI  
VCC  
VCC  
VCC  
VCC  
VCC  
TDO  
I/O2  
XE0  
I/O15  
XG0  
I/O30  
XG1  
I/O150 I/O167 I/O183  
N2  
N3  
P6  
I/O16  
XE1  
I/O31  
XE6  
I/O47  
XG2  
I/O137 I/O151 I/O168  
F
G
H
J
GND  
GND  
F
G
H
J
N1  
N0  
P5  
I/O3  
XH6  
I/O17  
XE4  
I/O32  
XE5  
I/O152 I/O169 I/O184  
VCC  
VCC  
P4  
P3  
M7  
PIN DESIGNATIONS  
I/O18  
XH5  
I/O33  
XE2  
I/O48  
XE3  
I/O138 I/O153 I/O170  
P2 P1 P0  
GND  
GND  
CLK  
GND  
I
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
I/O4  
XH0  
I/O19  
XH1  
I/O34  
XH4  
I/O49  
XH7  
I/O139 I/O154 I/O171 I/O185  
M6  
M5  
M4  
M3  
I/O35  
XH2  
I/O50  
XH3  
I/O140 I/O155  
M0 M1  
I/O186  
M2  
I/O  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
K
GND  
CLK3  
CLK0  
CLK2  
K
N/C  
VCC  
TDI  
TCK  
TMS  
TDO  
I/O5  
A2  
I/O36  
A0  
I/O51  
A1  
I/O141 I/O156  
L3 L4  
L
M
N
P
R
CLK1  
GND  
L
M
N
P
R
C
7
I/O6  
A4  
I/O20  
A3  
I/O37  
A5  
I/O52  
A6  
I/O142 I/O157 I/O172 I/O187  
Test Mode Select  
Test Data Out  
I/O Cell  
L6  
L5  
L0  
L1  
PAL Block  
I/O21  
A7  
I/O38  
D0  
I/O53  
D1  
I/O143 I/O158 I/O173  
GND  
GND  
I5  
I0  
L7  
I/O7  
D2  
I/O22  
D3  
I/O39  
D4  
I/O159 I/O174 I/O188  
VCC  
VCC  
I4  
I1  
L2  
I/O23  
D5  
I/O40  
D6  
I/O54  
D7  
I/O144 I/O160 I/O175  
GND  
GND  
K5  
K0  
I3  
I/O8  
B3  
I/O24  
B0  
I/O41  
B7  
I/O161 I/O176 I/O189  
K4 K1 I2  
T
TCK  
VCC  
TMS  
T
I/O9  
B4  
I/O25  
B1  
I/O42  
B6  
I/O162 I/O177 I/O190  
I/O67  
I/O80  
F0  
I/O87  
E5  
I/O93  
E2  
I/O99  
H2  
I/O112  
I/O125  
J1  
I/O105  
H5  
U
V
VCC  
VCC  
VCC  
VCC  
VCC  
U
V
K7  
K2  
I6  
C0  
G0  
I/O10  
B5  
I/O26  
B2  
I/O55  
C5  
I/O61  
C2  
I/O68  
C1  
I/O73  
F4  
I/O81  
F1  
I/O88  
E4  
I/O94  
E1  
I/O100 I/O106  
H1 H4  
I/O113  
G1  
I/O119  
G4  
I/O126 I/O131 I/O145  
J0 J2 J5  
I/O178 I/O191  
VCC  
VCC  
K3  
I7  
I/O27  
C7  
I/O43  
C6  
I/O56  
C3  
I/O62  
F7  
I/O69  
F5  
I/O74  
F3  
I/O82  
E7  
I/O89  
E3  
I/O95  
E0  
I/O101 I/O107  
I/O114  
H7  
I/O120 I/O127 I/O132 I/O146 I/O163 I/O179  
W
Y
W
Y
GND  
GND  
20  
GND  
H0  
H3  
G3  
G5  
G7  
J4  
J6  
J7  
I/O57  
C4  
I/O63  
F6  
I/O75  
F2  
I/O83  
E6  
I/O115  
H6  
I/O121  
G2  
I/O133 I/O147  
I/O180  
K6  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
G6  
J3  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
17466G-046  
ispMACH 4A Family  
55  
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128)  
Bottom View  
256-Ball fpBGA  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O117 I/O116 I/O113 I/O126 I/O124  
O5 O4 O1 P6 P4  
I/O1  
A1  
I/O5  
A5  
I/O7  
A7  
I/O10  
B2  
I/O12  
B4  
TRST  
I12  
NC  
NC  
NC  
CLK0  
A
B
C
D
E
F
A
B
C
D
E
F
I/O110 I/O111 I/O118 I/O115 I/O127 I/O125 I/O120  
I/O2  
A2  
I/O8  
B0  
I/O11  
B3  
I/O13  
B5  
NC  
NC  
NC  
NC  
NC  
I0  
I1  
NC  
N6  
N7  
O6  
O3  
P7  
P5  
P0  
I/O108 I/O109  
I/O119 I/O114 I/O122 I/O123  
I/O4  
A4  
I/O6  
A6  
I/O5  
B7  
I/O14  
B6  
I/O23  
C7  
NC  
TDI  
N4  
N5  
O7  
O2  
P2  
P3  
I/O104  
N0  
I/O9  
B1  
I/O22  
C6  
I/O21  
C5  
NC  
TDO  
GND  
GND  
VCC  
GND  
VCC  
CLK3  
GND  
NC  
GND  
NC  
VCC  
GND  
NC  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
I/O102  
M6  
I/O107  
N3  
I/O105 I/O106  
I/O0  
A0  
I/O20  
C4  
I/O19  
C3  
I/O31  
D7  
NC  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
I13  
N1  
N2  
I/O98  
M2  
I/O103 I/O101  
I/O100  
M4  
I/O99  
M3  
I/O112 I/O121  
O0  
I/O3  
A3  
I/O18  
C2  
I/O16  
C0  
I/O30  
D6  
I/O29  
D5  
NC  
NC  
M7  
M5  
P1  
I/O96  
M0  
I/O97  
M1  
I/O17  
C1  
I/O28  
D4  
I/O26  
D2  
I/O25  
D1  
NC  
I11  
NC  
VCC  
GND  
GND  
VCC  
VCC  
GND  
VCC  
GND  
GND  
VCC  
I2  
G
H
J
G
H
J
I/O88  
L0  
I/O89  
L1  
I/O90  
L2  
I/O27  
D3  
I/O24  
D0  
I10  
I9  
GND  
GND  
VCC  
NC  
VCC  
VCC  
GND  
NC  
NC  
NC  
I4  
NC  
NC  
NC  
NC  
NC  
I/O91  
L3  
I/O92  
L4  
I/O93  
L5  
I/O95  
L7  
I/O94  
L6  
I3  
NC  
NC  
I/O32  
E0  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
K
L
K
L
I/O80  
K0  
I/O83  
K3  
I/O59  
H3  
I/O61  
H5  
I/O35  
E3  
I/O36  
E4  
I/O33  
E1  
NC  
I/O81  
K1  
I/O82  
K2  
I/O84  
K4  
I/O67  
I3  
I/O65  
I1  
I/O58  
H2  
I/O48  
G0  
I/O51  
G3  
I/O44  
F4  
I/O39  
E7  
I/O34  
E2  
NC  
NC  
NC  
M
N
P
R
T
M
N
P
R
T
I/O85  
K5  
I/O86  
K6  
I/O40  
F0  
I/O37  
E5  
TENB  
GND  
VCC  
GND  
NC  
VCC  
NC  
GND  
NC  
GND  
I6  
VCC  
GND  
TCK  
TMS  
I/O87  
K7  
I/O77  
J5  
I/O78  
J6  
I/O79  
J7  
I/O68  
I4  
I/O66  
I2  
I/O63  
H7  
I/O52  
G4  
I/O55  
G7  
I/O41  
F1  
I/O38  
E6  
I/O76  
J4  
I/O75  
J3  
I/O72  
J0  
I/O71  
I7  
I/O64  
I0  
I/O56  
H0  
I/O60  
H4  
I/O49  
G1  
I/O53  
G5  
I/O47  
F7  
I/O43  
F3  
I/O42  
F2  
I7  
NC  
NC  
NC  
I/O74  
J2  
I/O73  
J1  
I/O70  
I6  
I/O69  
I5  
I/O57  
H1  
I/O62  
H6  
I/O50  
G2  
I/O54  
G6  
I/O46  
F6  
I/O45  
F5  
I8  
CLK2  
NC  
NC  
CLK1  
I5  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
I/O Cell  
PAL Block  
Program  
m4a3.256.128_256bga  
56  
ispMACH 4A Family  
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192)  
Bottom View  
256-Ball fpBGA  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O175 I/O181 I/O180 I/O177 I/O166 I/O164 I/O191 I/O186  
I/O1  
A1  
I/O3  
A3  
I/O25  
D1  
I/O29  
D5  
I/O31  
D7  
I/O10  
B2  
I/O12  
B4  
CLK0  
A
B
C
D
E
F
A
B
C
D
E
F
FX7 GX5 GX4 GX1 EX6 EX4 HX7 HX2  
I/O173 I/O174 I/O182 I/O179 I/O167 I/O165 I/O160 I/O187  
I/O0  
A0  
I/O5  
A5  
I/O7  
A7  
I/O26  
D2  
I/O8  
B0  
I/O11  
B3  
I/O13  
B5  
N/C  
FX5  
FX6  
GX6  
GX3  
EX7  
EX5  
EX0  
HX3  
I/O171 I/O172  
FX3 FX4  
I/O183 I/O178 I/O162 I/O163 I/O189 I/O184  
I/O6  
A6  
I/O28  
D4  
I/O30  
D6  
I/O15  
B7  
I/O14  
B6  
I/O23  
C7  
N/C  
TDI  
GX7  
GX2  
EX2  
EX3  
HX5  
HX0  
I/O150 I/O151  
I/O9  
B1  
I/O22  
C6  
I/O21  
C5  
TDO  
GND  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
N/C  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
CX6  
CX7  
I/O148  
CX4  
I/O170  
FX2  
I/O168  
FX0  
169  
FX1  
I/O190  
HX6  
I/O188  
HX4  
I/O2  
A2  
I/O24  
D0  
I/O20  
C4  
I/O19  
C3  
I/O47  
F7  
N/C  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
CLK3  
I/O144 I/O149 I/O147  
CX0 CX5 CX3  
I/O146 I/O145 I/O176 I/O161 I/O185  
CX2  
I/O4  
A4  
I/O27  
D3  
I/O18  
C2  
I/O16  
C0  
I/O46  
F6  
I/O45  
F5  
CX1  
GX0  
EX1  
HX1  
I/O155 I/O158 I/O157  
DX3 DX6 DX5  
I/O156 I/O159  
DX4 DX7  
I/O17  
C1  
I/O44  
F4  
I/O42  
F2  
I/O41  
F1  
I/O39  
E7  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
G
H
J
G
H
J
I/O152 I/O154 I/O153  
DX0 DX2 DX1  
I/O128 I/O129  
AX0 AX1  
I/O43  
F3  
I/O40  
F0  
I/O36  
E4  
I/O35  
E3  
I/O34  
E2  
GND  
GND  
VCC  
VCC  
VCC  
GND  
VCC  
VCC  
GND  
I/O130 I/O131 I/O132  
AX2 AX3 AX4  
I/O134 I/O133  
AX6 AX5  
I/O38  
E6  
I/O37  
E5  
I/O57  
H1  
I/O56  
H0  
I/O58  
H2  
I/O135 I/O136 I/O137  
AX7 BX0 BX1  
I/O139 I/O138  
BX3 BX2  
I/O33  
E1  
I/O32  
E0  
I/O63  
H7  
I/O62  
H6  
I/O48  
G0  
K
L
K
L
I/O140 I/O141 I/O143  
BX4 BX5 BX7  
I/O114 I/O142 I/O98  
O2 BX6 M2  
I/O91  
L3  
I/O67  
I3  
I/O69  
I5  
I/O60  
H4  
I/O59  
H3  
I/O51  
G3  
I/O52  
G4  
I/O49  
G1  
I/O112 I/O113 I/O115  
O0 O1 O3  
I/O123 I/O121 I/O100 I/O90  
P3  
I/O66  
I2  
I/O80  
K0  
I/O83  
K3  
I/O61  
H5  
I/O76  
J4  
I/O55  
G7  
I/O50  
G2  
M
N
P
R
T
M
N
P
R
T
P1  
M4  
L2  
I/O116 I/O117 I/O119  
O4 O5 O7  
I/O72  
J0  
I/O53  
G5  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
TCK  
TMS  
I/O118 I/O109 I/O110 I/O111 I/O124 I/O122 I/O101 I/O89  
I/O93  
L5  
I/O94  
L6  
I/O71  
I7  
I/O84  
K4  
I/O87  
K7  
I/O73  
J1  
I/O54  
G6  
O6  
N5  
N6  
N7  
P4  
P2  
M5  
L1  
I/O108 I/O107 I/O104 I/O127 I/O120 I/O102 I/O99  
I/O96  
M0  
I/O92  
L4  
I/O64  
I0  
I/O68  
I4  
I/O81  
K1  
I/O85  
K5  
I/O79  
J7  
I/O75  
J3  
I/O74  
J2  
N4  
N3  
N0  
P7  
P0  
M6  
CLK2  
11  
M3  
I/O106 I/O105 I/O126 I/O125 I/O103  
I/O97  
M1  
I/O88  
L0  
I/O95  
L7  
I/O65  
I1  
I/O70  
I6  
I/O82  
K2  
I/O86  
K6  
I/O78  
J6  
I/O77  
J5  
CLK1  
N2  
N1  
P6  
P5  
M7  
16  
15  
14  
13  
12  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
Test Mode Select  
Test Data Out  
Test Reset  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
C
7
I/O Cell  
Program  
PAL Block  
m4a3.384.192_256bga  
ispMACH 4A Family  
57  
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192)  
Bottom View  
256-Ball fpBGA  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O159 I/O181 I/O180 I/O177 I/O174 I/O172 I/O191 I/O186 I/O1  
KX7 OX5 OX4 OX1 NX6 NX4 PX7 PX2 A1  
I/O3  
A3  
I/O17 I/O21 I/O21 I/O10 I/O12  
A
B
C
D
E
F
CLK0  
A
B
C
D
E
F
C1  
C5  
C7  
B2  
B4  
I/O157 I/O158 I/O182 I/O179 I/O175 I/O173 I/O168 I/O187 I/O0  
I/O5  
A5  
I/O7  
A7  
I/O18  
C2  
I/O8  
B0  
I/O11 I/O13  
N/C  
KX5  
KX6  
OX6  
OX3  
NX7  
NX5  
NX0  
PX3  
A0  
B3  
B5  
I/O155 I/O156  
KX3 KX4  
I/O183 I/O178 I/O170 I/O171 I/O189 I/O184 I/O6  
I/O20 I/O22 I/O15 I/O14  
I/O39  
F7  
N/C  
TDI  
OX7  
OX2  
NX2  
NX3  
PX5  
PX0  
A6  
C4  
C6  
B7  
B6  
I/O150 I/O151  
I/O9  
B1  
I/O38 I/O37  
F6 F5  
TDO  
GND  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
VCC  
JX6  
JX7  
I/O148  
JX4  
I/O154  
KX2  
I/O152 I/O153 I/O190  
KX0 KX1 PX6  
I/O188 I/O2  
I/O16  
C0  
I/O36 I/O35 I/O47  
F4 F3 G7  
N/C  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
CLK3  
N/C  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
VCC  
GND  
PX4  
A2  
I/O144 I/O149 I/O147  
JX0 JX5 JX3  
I/O146 I/O145 I/O176 I/O169 I/O185 I/O4  
I/O19 I/O34  
C3 F2  
I/O32 I/O46 I/O45  
F0 G6 G5  
JX2  
JX1  
OX0  
NX1  
PX1  
A4  
I/O163 I/O166 I/O165  
LX3 LX6 LX5  
I/O164 I/O167  
LX4 LX7  
I/O33 I/O44  
F1 G4  
I/O42 I/O41 I/O31  
G2 G1 E7  
G
H
J
VCC  
GND  
GND  
VCC  
G
H
J
I/O160 I/O162 I/O161  
LX0 LX2 LX1  
I/O120 I/O121  
EX0 EX1  
I/O43 I/O40  
G3 G0  
I/O28 I/O27 I/O26  
E4 E3 E2  
GND  
GND  
VCC  
VCC  
VCC  
GND  
VCC  
VCC  
GND  
GND  
GND  
VCC  
I/O122 I/O123 I/O124  
EX2 EX3 EX4  
I/O126 I/O125  
EX6 EX5  
I/O30 I/O29  
E6 E5  
I/O65 I/O64 I/O66  
L1 L0 L2  
I/O127 I/O136 I/O137  
EX7 GX0 GX1  
I/O139 I/O138  
GX3 GX2  
I/O25 I/O24  
E1 E0  
I/O71 I/O70 I/O48  
L7 L6 J0  
K
L
K
L
I/O140 I/O141 I/O143  
GX4 GX5 GX7  
I/O130 I/O142 I/O98 I/O91 I/O75 I/O77 I/O68 I/O67  
FX2 GX6 AX2 P3 N3 N5 L4 L3  
I/O51 I/O52 I/O49  
J3 J4 J1  
I/O128 I/O129 I/O131  
FX0  
I/O115 I/O113 I/O100 I/O90 I/O74 I/O80 I/O83 I/O69  
I/O60 I/O55 I/O50  
M
N
P
R
T
M
N
P
R
T
FX1  
FX3  
CX3  
CX1  
AX4  
P2  
N2  
O0  
O3  
L5  
K4  
J7  
J2  
I/O132 I/O133 I/O135  
FX4 FX5 FX7  
I/O56 I/O53  
K0 J5  
GND  
VCC  
GND  
VCC  
GND  
GND  
VCC  
GND  
TCK  
I/O134 I/O109 I/O110 I/O111 I/O116 I/O114 I/O101 I/O89 I/O93 I/O94 I/O79 I/O84 I/O87  
FX6 BX5 BX6 BX7 CX4 CX2 AX5 P1 P5 P6 N7 O4 O7  
I/O57 I/O54  
K1 J6  
TMS  
I/O108 I/O107 I/O104 I/O119 I/O112 I/O102 I/O99 I/O96 I/O92 I/O72 I/O76 I/O81 I/O85 I/O63 I/O59 I/O58  
BX4  
BX3  
BX0  
CX7  
CX0  
AX6  
AX3  
AX0  
P4  
N0  
N4  
O1  
O5  
K7  
K3  
K2  
I/O106 I/O105 I/O118 I/O117 I/O103  
I/O97 I/O88  
I/O95 I/O73 I/O78 I/O82 I/O86 I/O62 I/O61  
P7  
CLK2  
CLK1  
BX2  
BX1  
CX6  
CX5  
AX7  
AX1  
P0  
N1  
N6  
O2  
O6  
K6  
K5  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
I/O Cell  
Program  
PAL Block  
m4a3.512.192_256bga  
58  
ispMACH 4A Family  
388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256)  
Bottom View  
388-Ball fpBGA  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I/O243 I/O240 I/O241 I/O236 I/O231 I/O228 I/O226 I/O255 I/O251 I/O248 I/O0  
I/O5  
A5  
I/O6 I/O27 I/O30 I/O17 I/O22 I/O8 I/O10  
A6 D3 D6 C1 C6 B0 B2  
GND  
N/C  
GND  
A
B
C
D
E
A
B
C
D
E
OX3  
OX0  
OX1  
NX4 MX7 MX4 MX2  
PX7  
PX3  
PX0  
A0  
I/O245 I/O242 I/O238 I/O234 I/O232 I/O229 I/O224 I/O253 I/O249 I/O2  
I/O26 I/O29 I/O31 I/O20 I/O9 I/O12 I/O13  
N/C  
GND  
CLK0  
GND  
TDI  
OX5  
OX2  
NX6  
NX2  
NX0 MX5 MX0  
PX5  
PX1  
A2  
D2  
D5  
D7  
C4  
B1  
B4  
B5  
I/O213  
KX5  
I/O247 I/O244 I/O239 I/O235 I/O230 I/O227  
I/O250 I/O11 I/O7 I/O25 I/O16 I/O18 I/O23 I/O11 I/O15  
I/O47 I/O44  
F7 F4  
TDO GND  
CLK3  
GND  
OX7  
OX4  
NX7  
NX3 MX6 MX3  
PX2  
A1  
A7  
D1  
C0  
C2  
C7  
B3  
B7  
I/O210 I/O212 I/O215  
I/O246  
OX6  
I/O237 I/O233  
VCC  
I/O254  
PX6  
I/O3 I/O24  
A3 D0  
I/O19 I/O21  
C3 C5  
I/O14  
B6  
I/O46 I/O43 I/O41  
F6 F3 F1  
GND  
VCC  
VCC  
VCC  
VCC  
GND  
KX2  
KX4  
KX7  
NX5  
NX1  
I/O207 I/O209 I/O211 I/O214  
I/O45 I/O42 I/O40 I/O54  
JX7  
KX1  
KX3  
KX6  
F5  
F2  
F0  
G6  
I/O203 I/O205 I/O208  
I/O55 I/O52 I/O50  
G7 G4 G2  
VCC  
VCC  
F
F
JX3  
JX5  
KX0  
I/O200 I/O202 I/O204 I/O206  
JX0 JX2 JX4 JX6  
I/O225 I/O252 I/O4 I/O28  
MX1 PX4 A4 D4  
I/O53 I/O51 I/O49 I/O39  
G5 G3 G1 E7  
VCC VCC  
N/C  
N/C  
VCC VCC  
G
H
J
G
H
J
I/O221 I/O222 I/O223 I/O201  
I/O48 I/O38 I/O37 I/O36  
VCC  
N/C  
N/C  
GND GND GND GND GND GND  
N/C  
VCC  
N/C  
LX5  
LX6  
LX7  
JX1  
G0  
E6  
E5  
E4  
I/O218 I/O219 I/O220  
I/O35 I/O34 I/O32  
E3 E2 E0  
VCC  
GND GND GND GND GND GND GND GND  
GND GND GND GND GND GND GND GND  
GND GND GND GND GND GND GND GND  
GND GND GND GND GND GND GND GND  
GND GND GND GND GND GND GND GND  
GND GND GND GND GND GND GND GND  
VCC  
LX2  
LX3  
LX4  
I/O197 I/O198 I/O199 I/O216  
IX5 IX6 IX7 LX0  
I/O217  
LX1  
I/O33  
E1  
I/O63 I/O62 I/O61 I/O60  
K
L
K
L
H7  
H6  
H5  
H4  
I/O192 I/O194 I/O195 I/O196  
I/O193  
IX1  
I/O58  
H2  
I/O59 I/O57 I/O56  
H3 H1 H0  
VCC  
IX0  
IX2  
IX3  
IX4  
I/O184 I/O185 I/O187  
I/O186  
HX2  
I/O69  
I5  
I/O67 I/O65 I/O66 I/O64  
I3 I1 I2 I0  
VCC  
M
N
P
M
N
P
HX0  
HX1  
HX3  
I/O188 I/O189 I/O191 I/O190  
I/O162  
EX2  
I/O89  
L1  
I/O88 I/O71 I/O70 I/O68  
HX4  
HX5  
HX7  
HX6  
L0  
I7  
I6  
I4  
I/O160 I/O161 I/O163  
EX0 EX1 EX3  
I/O92 I/O91 I/O90  
L4 L3 L2  
VCC  
N/C  
N/C  
VCC  
I/O164 I/O165 I/O166 I/O177  
EX4 EX5 EX6 GX1  
I/O74 I/O95 I/O94 I/O93  
J2 L7 L6 L5  
VCC  
N/C  
GND GND GND GND GND GND  
I/O152 I/O131 I/O122 I/O98  
N/C  
VCC  
R
T
R
T
I/O167 I/O176 I/O179 I/O181  
I/O78 I/O76 I/O73 I/O72  
VCC VCC  
N/C  
N/C  
VCC VCC  
EX7  
GX0  
GX3  
GX5  
DX0  
AX3  
P2  
M2  
J6  
J4  
J1  
J0  
I/O178 I/O180 I/O183  
I/O80 I/O77 I/O75  
K0 J5 J3  
VCC  
VCC  
U
V
U
V
GX2  
GX4  
GX7  
I/O182  
GX6  
I/O169 I/O172  
FX1  
I/O86 I/O83 I/O81 I/O79  
N/C  
FX4  
K6  
K3  
K1  
J7  
I/O168 I/O170 I/O173  
I/O143  
BX7  
I/O150 I/O145  
I/O153 I/O123  
I/O96  
M0  
I/O104 I/O111  
I/O119  
O7  
I/O87 I/O84 I/O82  
GND  
VCC  
VCC  
VCC  
VCC  
VCC  
GND  
W
Y
W
Y
FX0  
FX2  
FX5  
CX6  
CX1  
DX1  
P3  
N0  
N7  
K7  
K4  
K2  
I/O171 I/O174  
I/O141 I/O138 I/O136 I/O147 I/O158 I/O156  
I/O132 I/O121 I/O125 I/O99 I/O101 I/O106 I/O110 I/O115 I/O118  
I/O85  
K5  
GND  
CLK2  
GND TMS  
FX3  
FX6  
BX5  
BX2  
BX0  
CX3  
DX6  
DX4  
AX4  
P1  
P5  
M3  
M5  
N2  
N6  
O3  
O6  
I/O175  
FX7  
I/O142 I/O140 I/O151 I/O149 I/O144 I/O157 I/O154 I/O134 I/O130 I/O128  
CLK1  
I/O127 I/O100 I/O103 I/O108 I/O109 I/O113 I/O116  
GND  
GND TCK  
AA  
AB  
AA  
AB  
BX6  
BX4  
CX7  
CX5  
CX0  
DX5  
DX2  
AX6  
AX2  
AX0  
P7  
M4  
M7  
N4  
N5  
O1  
O4  
I/O139 I/O137 I/O148 I/O146 I/O159 I/O155 I/O135 I/O133 I/O129 I/O120 I/O124 I/O126 I/O97 I/O102 I/O105 I/O107 I/O112 I/O114 I/O117  
GND  
N/C  
GND  
BX3  
BX1  
CX4  
CX2  
DX7  
DX3  
AX7  
AX5  
AX1  
P0  
P4  
P6  
M1  
M6  
N1  
N3  
O0  
O2  
O5  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
PIN DESIGNATIONS  
CLK  
GND  
I
I/O  
N/C  
=
=
=
=
=
=
=
=
=
=
=
=
Clock  
Ground  
Input  
Input/Output  
No Connect  
Supply Voltage  
Test Data In  
Test Clock  
VCC  
TDI  
TCK  
TMS  
TDO  
TRST  
ENABLE  
Test Mode Select  
Test Data Out  
Test Reset  
C
7
m4a3.512.256_388bga  
I/O Cell  
Program  
PAL Block  
ispMACH 4A Family  
59  
ispMACH 4A PRODUCT ORDERING INFORMATION  
ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V  
Lattice programmable logic products are available with several ordering options.The order number (Valid Combination)  
is formed by a combination of:  
/
M4A3- 256 128 -7  
Y
C
FAMILY TYPE  
M4A3- = ispMACH 4A Family Low Voltage Advanced  
Feature (3.3-V V  
48  
= 48-pin TQFP for  
M4A3-32/32 or M4A3-64/32  
M4A5-32/32 or M4A5-64/32  
)
CC  
M4A5- = ispMACH 4A Family Advanced Feature (5-V V  
)
CC  
OPERATING CONDITIONS  
C
I
= Commercial (0°C to +70°C)  
= Industrial (-40°C to +85°C)  
MACROCELL DENSITY  
32=32 Macrocells192  
64=64 Macrocells256  
96=96 Macrocells384  
128=128 Macrocells512  
=
=
=
=
192 Macrocells  
256 Macrocells  
384 Macrocells  
512 Macrocells  
PACKAGE TYPE  
A
J
= Ball Grid Array (BGA)  
= Plastic Leaded Chip Carrier  
(PLCC)  
V
Y
FA  
= Thin Quad Flat Pack (TQFP)  
= Plastic Quad Flat Pack (PQFP)  
= Fine-pitch Ball Grid Array  
(fpBGA)  
I/Os  
/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP  
/48 = 48 I/Os in 100-pin TQFP  
/64 = 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA  
/96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA  
/128 = 128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA  
/160 = 160 I/Os in 208-pin PQFP  
/192 = 192 I/Os in 256-ball BGA or 256-ball fpBGA  
/256 = 256 I/Os in 388-ball fpBGA  
CA  
= Chip-array Ball Grid Array  
(caBGA)  
SPEED  
-5  
-55  
-6  
-65  
-7  
=5.0 ns t  
=5.5 ns t  
=6.0 ns t  
=6.5 ns t  
=7.5 ns t  
PD  
PD  
PD  
PD  
PD  
-10  
-12  
-14  
=10 ns t  
=12 ns t  
=14 ns t  
PD  
PD  
PD  
3.3V Commercial Combinations  
3.3V Industrial Combinations  
JI, VI, VI48  
M4A3-32/32  
M4A3-64/32  
M4A3-64/64  
M4A3-96/48  
M4A3-128/64  
M4A3-192/96  
M4A3-256/128  
-5, -7, -10  
JC, VC, VC48  
JC, VC, VC48  
VC  
M4A3-32/32  
M4A3-64/32  
M4A3-64/64  
M4A3-96/48  
JI, VI, VI48  
-7, -10, -12  
VI  
-55, -7, -10  
VC  
VI  
YC, VC, CAC  
VC, FAC  
YC, AC, FAC  
YC  
FAC  
YC  
AC, FAC  
YC  
FAC  
M4A3-128/64  
M4A3-192/96  
M4A3-256/128  
M4A3-256/160  
M4A3-256/192  
M4A3-384/160  
M4A3-384/192  
M4A3-512/160  
M4A3-512/192  
M4A3-512/256  
YI, VI, CAI  
VI, FAI  
YI, AI, FAI  
YI  
FAI  
YI  
AI, FAI  
YI  
FAI  
-6, -7, -10  
-55, -65, -7, -10  
-7, -10, -12  
-10, -12  
1
M4A3-256/160  
-7, -10  
1
M4A3-256/192  
M4A3-384/160  
M4A3-384/192  
M4A3-512/160  
M4A3-512/192  
M4A3-512/256  
-65, -10, -12  
-10, -12, -14  
-7, -10, -12  
FAC  
FAI  
1. Contact Factory for 6.5ns availability  
60  
ispMACH 4A Family  
5V Commercial Combinations  
5V Industrial Combinations  
M4A5-32/32  
M4A5-64/32  
M4A5-96/48  
M4A5-128/64  
M4A5-192/96  
M4A5-256/128  
-5, -7, -10,  
JC, VC, VC48  
JC, VC, VC48  
VC  
YC, VC  
VC  
YC, AC  
M4A5-32/32  
M4A5-64/32  
M4A5-96/48  
M4A5-128/64  
M4A5-192/96  
M4A5-256/128  
-7, -10, -12  
JI, VI, VI48  
JI, VI, VI48  
VI  
YI, VI  
VI  
YI, AI  
-55, -7, -10  
-7, -10, -12  
-6, -7, -10  
-65, -7, -10  
-7, -10, -12  
-10, -12  
Most ispMACH devices are dual-marked with both Commercial and Industrial grades.The Industrial speed grade is slower, i.e., M4A3-  
256/128-7YC-10YI  
Valid Combinations  
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to  
confirm availability of specific valid combinations and to check on newly released combinations.  
Copyright © 2000 Lattice Semiconductor.All rights reserved.  
ispMACH 4A Family  
61  
62  
ispMACH 4A Family  

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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