MACH230-15JC [LATTICE]
High-Density EE CMOS Programmable Logic; 高密度EE CMOS可编程逻辑
| 型号： | MACH230-15JC |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | High-Density EE CMOS Programmable Logic |
| 文件： | 总29页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: -10/15/20
IND: -18/24
Lattice Semiconductor
MACH230-10/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
84 Pins
64 Outputs
128 Flip-flops; 4 clock choices
128 Macrocells
8 “PAL26V16” blocks with buried macrocells
10 ns tPD Commercial
18 ns tPD Industrial
Pin-compatible with MACH130, MACH131,
MACH231, and MACH435
100 MHz fCNT
70 Inputs
GENERAL DESCRIPTION
TheMACH230isamemberofthehigh-performance
EE CMOS MACH 2 device family. This device has ap-
proximately twelve times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the reg-
ister can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the soft-
ware. All output macrocells can be connected to an I/O
cell. If a buried macrocell is desired, the internal feed-
back path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH230 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity be-
tween the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
Publication# 14132 Rev. I
Issue Date: May 1995
Amendment/0
I/O – I/O (Block A)
I/O – I/O (Block B)
I/O – I/O (Block C)
I/O – I/O (Block D)
24 31
0
7
8
15
16
23
I
I
2, 5
8
8
8
8
8
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
8
8
8
8
8
8
Macrocells
Macrocells
Macrocells
Macrocells
Macrocells
Macrocells
Macrocells
Macrocells
4
2
OE
OE
52 x 68
AND Logic Array
OE
OE
52 x 68
AND Logic Array
52 x 68
AND Logic Array
52 x 68
AND Logic Array
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
26
26
26
26
Switch Matrix
26
26
26
26
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
52 x 68
AND Logic Array
and Logic Allocator
4
OE
OE
OE
OE
Macrocells
Macrocells
8
Macrocells
Macrocells
8
Macrocells
Macrocells
8
Macrocells
Macrocells
8
4
8
8
8
8
8
8
8
8
8
8
8
8
I/O Cells
I/O Cells
I/O Cells
I/O Cells
I/O – I/O (Block H)
56 63
I/O – I/O (Block G)
48 55
I/O – I/O (Block F)
40 47
I/O – I/O (Block E)
31 39
CLK /I CLK /I
0 0, 1 1
CLK /I CLK /I
2 3,
3 4
14132I-1
CONNECTION DIAGRAM
Top View
84 PLCC
11 10
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75
74
12
13
14
15
I/O
I/O
GND
8
9
I/O
55
I/O
54
I/O
53
I/O
52
I/O
51
I/O
50
I/O
49
I/O
48
73
72
71
70
69
68
67
66
I/O
10
I/O
11
16
17
I/O
12
13
14
I/O
I/O
18
19
20
I/O
15
CLK /I
0 0
21
22
65
64
63
62
61
V
CLK /I
3 4
CC
GND
GND
23
24
25
26
27
28
29
30
V
CLK /I
1 1
I/O
I/O
CC
CLK /I
2 3
16
I/O
I/O
I/O
I/O
I/O
I/O
17
47
46
45
44
43
42
I/O
18
60
59
58
57
56
I/O
I/O
I/O
19
20
21
22
I/O
31
32
55
54
I/O
GND
I/O
I/O
23
41
40
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
14132I-2
Note:
Pin-compatible with MACH130, MACH131, MACH231, and MACH435.
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O = Input/Output
VCC = Supply Voltage
MACH230-10/15/20
3
ORDERING INFORMATION
Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH
230 -10
J
C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
DEVICE NUMBER
230 = 128 Macrocells, 84 Pins
SPEED
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
Valid Combinations
Valid Combinations
The Valid Combinations table lists configurations
plannedtobesupportedinvolumeforthisdevice. Con-
sult your local sales office to confirm availability of
specific valid combinations and to check on newly re-
leased combinations.
MACH230-10
JC
MACH230-15
MACH230-20
4
MACH230-10/15/20 (Com’l)
ORDERING INFORMATION
Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH
230 -18
J
I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
DEVICE NUMBER
230 = 128 Macrocells, 84 Pins
I
= Industrial (–40°C to +85°C)
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availabil-
ity of specific valid combinations and to check on newly
released combinations.
MACH230-18
JI
MACH230-24
MACH230-18/24 (Ind)
5
configures the logic allocator when fitting the design into
the device.
FUNCTIONAL DESCRIPTION
The MACH230 consists of eight PAL blocks connected
by a switch matrix. There are 64 I/O pins and 2
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are 4 clock pins that can
also be used as dedicated inputs.
Table 2 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
Table 2. Logic Allocation
Macrocell
Output
Available
Clusters
The PAL Blocks
Buried
M1
Each PAL block in the MACH230 (Figure 1) contains a
64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 26 inputs. This
makes the PAL block look effectively like an independ-
ent “PAL26V16” with 8 buried macrocells.
M0
C0, C1, C2
C0, C1, C2, C3
M2
C1, C2, C3, C4
C2, C3, C4, C5
M3
M4
C3, C4, C5, C6
C4, C5, C6, C7
M5
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
M6
C5, C6, C7, C8
C6, C7, C8, C9
M7
M8
C7, C8, C9, C10
C8, C9, C10, C11
M9
M10
M12
M14
C9, C10, C11, C12
C10, C11, C12, C13
M11
M13
M15
The Switch Matrix
The MACH230 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
C11, C12, C13, C14
C12, C13, C14, C15
C13, C14, C15
C14, C15
The Macrocell
The MACH230 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip-
flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The MACH230 places a restriction on buried macrocell
feedback only. Buried macrocell feedback from one
block can be used as an input only to that block or its
“sibling” block. Sibling blocks are illustrated in the block
diagram and in Table 1. Output macrocell feedback is
not restricted.
The flip-flops can individually select one of four clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initial-
ized with the common asynchronous reset and preset
product terms.
Table 1. Sibling Blocks
PAL Block
Sibling Block
A
B
C
D
E
F
H
G
F
E
D
C
B
A
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
G
H
The Product-Term Array
The MACH230 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides asyn-
chronous preset.
The I/O Cell
The I/O cell in the MACH230 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
The Logic Allocator
The logic allocator in the MACH230 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
6
MACH230-10/15/20
0
4
8
12
16
20
24
28
32
36
40
47
43
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Output
Macro
Cell
M0
Buried
Macro
Cell
M1
M2
I/O
Cell
I/O
Output
Macro
Cell
Buried
Macro
Cell
M3
M4
0
I/O
Cell
I/O
Output
Macro
Cell
C0
C1
Buried
Macro
Cell
C2
M5
M6
M7
M8
M9
C3
I/O
Cell
I/O
C4
Output
Macro
Cell
C5
C6
Buried
Macro
Cell
Switch
Matrix
C7
I/O
Cell
C8
I/O
Output
Macro
Cell
C9
C10
C11
C12
C13
C14
C15
Buried
Macro
Cell
I/O
I/O
I/O
I/O
Cell
Output
Macro
Cell
M10
Buried
Macro
Cell
M11
M12
M13
63
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
Cell
Output
Macro
Cell
M14
M15
Buried
Macro
Cell
4
0
4
8
16
12
8
16
20
24
28
32
36
40
43
47
51
14132I-3
Figure 1. MACH230 PAL Block
MACH230-10/15/20
7
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Ambient Temperature (TA)
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stressesabove those listed under Absolute MaximumRatings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min Typ Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
2.4
V
V
IN = VIH or VIL
IOL = 16 mA, VCC = Min
IN = VIH or VIL
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.5
V
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Current
Input LOW Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
VOUT = 5.25 V, VCC = Max
10
–10
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
ICC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
mA
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA)
235
VCC = 5.0 V, f = 25 MHz, TA = 25°C
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and
capable of being loaded, enabled, and reset.
8
MACH230-10 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
6
Unit
pF
CIN
Input Capacitance
Output Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
COUT
VOUT = 2.0 V f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
-10
Parameter
Symbol
Parameter Description
Min
Max
Unit
ns
tPD
Input, I/O, or Feedback to Combinatorial Output
10
D-type
T-type
6.5
7.5
0
ns
tS
Setup Time from Input, I/O, or Feedback to Clock
ns
tH
Register Data Hold Time
Clock to Output
ns
ns
tCO
6.5
tWL
tWH
Clock
Width
LOW
HIGH
4
4
ns
ns
D-type
T-type
D-type
T-type
77
72
100
91
125
8
MHz
MHz
MHz
MHz
MHz
ns
External Feedback
Maximum
fMAX
Frequency
Internal Feedback (fCNT
)
No Feedback
tSL
tHL
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
0
ns
tGO
Gate to Output
7.5
14
ns
tGWL
tPDL
Gate Width LOW
4
ns
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
ns
tSIR
tHIR
tICO
tICS
Input Register Setup Time
2
ns
ns
ns
ns
ns
Input Register Hold Time
2.5
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
15.5
D-type
T-type
11
12
tWICL
tWICH
Input Register
Clock Width
LOW
HIGH
4
4
ns
ns
fMAXIR
tSIL
Maximum Input Register Frequency
Input Latch Setup Time
125
2
MHz
ns
tHIL
Input Latch Hold Time
2.5
ns
tIGO
Input Latch Gate to Combinatorial Output
17
18
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
10
ns
9
MACH230-10 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)
-10
Parameter
Symbol
Parameter Description
Min
11
4
Max
Unit
ns
tIGS
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
tWIGL
tPDLL
ns
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
16
18
ns
tAR
tARW
tARR
tAP
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width
ns
ns
ns
ns
ns
ns
ns
ns
10
10
Asynchronous Reset Recovery Time
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width
18
tAPW
tAPR
tEA
10
10
Asynchronous Preset Recovery Time
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
15
15
tER
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the designis modified where
capacitance may be affected.
10
MACH230-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Ambient Temperature (TA)
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stressesabove those listed under Absolute MaximumRatings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
2.4
V
VIN = VIH or VIL
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
0.5
V
V
V
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Current
Input LOW Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
VOUT = 5.25 V, VCC = Max
10
–10
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
V
IN = VIH or VIL (Note 2)
VOUT = 0 V, VCC = Max
IN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
–10
µA
V
ISC
ICC
Output Short-Circuit Current
Supply Current (Typical)
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130
mA
mA
VCC = 5 V, TA = 25°C, f = 25 MHz
235
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
11
MACH230-15/20 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
6
Unit
pF
CIN
Input Capacitance
Output Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
COUT
VOUT = 2.0 V f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-15
Min
-20
Min
Parameter
Symbol
Parameter Description
Max
Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
15
20
ns
ns
ns
D-type
T-type
10
11
0
13
14
0
tS
Setup Time from Input, I/O, or Feedback to Clock
tH
Register Data Hold Time
Clock to Output (Note 3)
ns
ns
tCO
10
12
tWL
tWH
Clock
Width
LOW
HIGH
6
6
8
8
ns
ns
D-type
T-type
D-type
T-type
50
40
MHz
MHz
MHz
MHz
MHz
ns
External Feedback
1/(tS + tCO)
47.6
66.6
62.5
83.3
10
38.5
50
Maximum
Frequency
(Note 1)
fMAX
Internal Feedback (fCNT
)
47.6
62.5
13
No Feedback
1/(tWL + tWH
)
tSL
tHL
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
0
0
ns
tGO
Gate to Output (Note 3)
11
17
12
22
ns
tGWL
tPDL
Gate Width LOW
6
8
ns
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
ns
ns
ns
ns
ns
ns
tSIR
tHIR
tICO
tICS
Input Register Setup Time
2
2
3
Input Register Hold Time
2.5
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
18
23
D-type
T-type
15
16
20
21
tWICL
tWICH
Input Register
Clock Width
LOW
HIGH
6
6
8
8
ns
ns
fMAXIR
tSIL
Maximum Input Register Frequency 1/(tWICL + tWICH
Input Latch Setup Time
)
83.3
2
62.5
2
MHz
ns
tHIL
Input Latch Hold Time
2.5
3
ns
tIGO
Input Latch Gate to Combinatorial Output
20
22
25
27
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
ns
tSLL
tIGS
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
12
16
15
21
ns
ns
Input Latch Gate to Output Latch Setup
12
MACH230-15/20 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
-15
-20
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
ns
tWIGL
tPDLL
Input Latch Gate Width LOW
6
8
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
19
20
24
25
ns
tAR
tARW
tARR
tAP
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
ns
ns
ns
ns
ns
ns
ns
ns
15
10
20
15
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
20
25
tAPW
tAPR
tEA
15
10
20
15
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 3)
Input, I/O, or Feedback to Output Disable (Note 3)
15
15
20
20
tER
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. Parameters measured with 32 outputs switching.
13
MACH230-15/20 (Com’l)
ABSOLUTE MAXIMUM RATINGS
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA)
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC+ 0.5 V
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC+ 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA =–40°C to +85°C) . . . . . . . . . . . . . . . . . . 200 mA
Stressesabove those listed under Absolute MaximumRatings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min Typ Max Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIHor VIL
2.4
V
V
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
0.5
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–10
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT= 5.25 V, VCC = Max
VIN = VIHor VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT= 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
ICC
Output Short-Circuit Current
Supply Current (Typical)
VOUT= 0.5 V, VCC = Max (Note 3)
–30
–130 mA
mA
VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4)
235
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL(or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
14
MACH230-18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
6
Unit
pF
CIN
Input Capacitance
Output Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
COUT
VOUT= 2.0 V f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-18
Min
-24
Min
Parameter
Symbol
Parameter Description
Max
Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
18
24
ns
ns
ns
ns
ns
D-type
T-type
12
16
17
0
tS
Setup Time from Input, I/O, or Feedback to Clock
13.5
0
tH
Register Data Hold Time
Clock to Output (Note 3)
tCO
12
14.5
tWL
tWH
Clock
Width
LOW
HIGH
7.5
7.5
10
10
ns
ns
D-type
T-type
D-type
T-type
40
38
53
44
66.5
12
0
32
MHz
MHz
MHz
MHz
MHz
ns
External Feedback
1/(tS + tCO)
30.5
38
Maximum
Frequency
(Note 1)
fMAX
Internal Feedback (fCNT
)
34.5
50
No Feedback
1/(tWL + tWH
)
tSL
tHL
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
16
0
ns
tGO
tGWL
tPDL
Gate to Output (Note 3)
13.5
20.5
14.5
26.5
ns
Gate Width LOW
7.5
10
ns
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
ns
tSIR
tHIR
tICO
tICS
Input Register Setup Time
2.5
3.5
2.5
4
ns
ns
ns
ns
ns
Input Register Hold Time
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
22
28
D-type
T-type
18
24
19.5
25.5
tWICL
tWICH
Input Register
Clock Width
LOW
HIGH
7.5
7.5
10
10
ns
ns
fMAXIR
tSIL
Maximum Input Register Frequency 1/(tWICL+ tWICH)
Input Latch Setup Time
66.5
2.5
50
2.5
4
MHz
ns
tHIL
Input Latch Hold Time
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
24
30
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
26.5
32.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
14.5
18
ns
tIGS
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
19.5
7.5
25.5
10
ns
ns
ns
tWIGL
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
23
29
MACH230-18/24 (Ind)
15
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
(continued)
-18
-24
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tAR
tARW
tARR
tAP
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
24
30
18
12
24
18
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
24
30
tAPW
tAPR
tEA
18
12
24
18
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 3)
Input, I/O, or Feedback to Output Disable (Note 3)
18
18
24
24
tER
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. Parameters measured with 32 outputs switching.
16
MACH230-18/24 (Ind)
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
IOL (mA)
80
60
40
20
VOL (V)
–1.0 –0.8 –0.6 –0.4 –0.2
–20
.2
.4
.6
.8 1.0
–40
–60
–80
14132I-4
Output, LOW
IOH (mA)
25
1
2
3
4
5
VOH (V)
–3 –2 –1
–25
–50
–75
–100
–125
–150
14132I-5
Output, HIGH
II (mA)
20
VI (V)
–2 –1
1
2
3
4
5
–20
–40
–60
–80
–100
14132I-6
Input
MACH230-10/15/20
17
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
300
275
250
225
200
175
MACH230
150
ICC(mA)
125
100
75
50
25
0
0
10
20
30
40
50
60
70
Frequency (MHz)
14132I-7
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
18
MACH230-10/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
PLCC
Units
θjc
Thermal impedance, junction to case
5
°C/W
θja
Thermal impedance, junction to ambient
20
17
14
12
10
°C/W
°C/W
°C/W
°C/W
°C/W
θjma
Thermal impedance, junction to
ambient with air flow
200 lfpm air
400 lfpm air
600 lfpm air
800 lfpm air
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
packagesurface. Testsindicatethismeasurementreferencepointisdirectlybelowthedie-attachareaonthebottomcenterofthe
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
MACH230-10/15/20
19
SWITCHING WAVEFORMS
Input, I/O, or
VT
Feedback
tPD
Combinatorial
Output
VT
14132I-8
Combinatorial Output
Input, I/O, or
Feedback
Input, I/O,
or Feed-
back
VT
VT
tH
tS
tSL
tHL
Gate
VT
VT
Clock
tCO
tPDL
tGO
VT
Latched
Out
Registered
Output
VT
14132I-9
14132I-10
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH
Clock
Gate
VT
tGWS
tWL
14132I-12
14132I-11
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered
Input
VT
Registered
Input
VT
tSIR
tHIR
Input
Register
Clock
Input
Register
Clock
VT
tICO
VT
tICS
Combinatorial
Output
VT
Output
Register
Clock
VT
14132I-13
14132I-14
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup
(MACH 2 and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
20
MACH230-10/15/20
SWITCHING WAVEFORMS
Latched
In
VT
tSIL
tHIL
Gate
VT
tIGO
VT
Combinatorial
Output
14132I-15
Latched Input (MACH 2 and 4)
tPDLL
Latched
In
VT
Latched
Out
VT
tIGOL
Input
Latch Gate
tSLL
tIGS
VT
Output
Latch Gate
14132I-16
Latched Input and Output
(MACH 2, 3, and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH230-10/15/20
21
SWITCHING WAVEFORMS
tWICH
Input
Latch
Gate
Clock
VT
VT
tWICL
tWIGL
14132I-18
14132I-17
Input Register Clock Width
(MACH 2 and 4)
Input Latch Gate Width
(MACH 2 and 4)
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAR
tAP
Registered
Output
Registered
Output
VT
VT
tARR
VT
tAPR
Clock
Clock
VT
14132I-19
14132I-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
tEA
VOH - 0.5V
VOL + 0.5V
Outputs
VT
14132I-21
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
22
MACH230-10/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S1
R1
Output
Test Point
R2
CL
14132I-22
Commercial
Measured
Specification
tPD, tCO
S1
CL
R1
R2
Output Value
Closed
1.5 V
tEA
Z → H: Open
Z → L: Closed
35 pF
5 pF
1.5 V
300 Ω
390 Ω
tER
H → Z: Open
L → Z: Closed
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
MACH230-10/15/20
23
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
datasetuptimeandthedataholdtime(tS +tH). However,
a lower limit for the period of each fMAX type is the mini-
mum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, des-
ignated “fMAX no feedback.”
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (tS + tCO). The re-
ciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This fMAX is designated “fMAX external.”
For devices with input registers, one additional fMAX pa-
rameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no feed-
back. The minimum period will be limited either by the
sum of the setup and hold times (tSIR + tHIR) or the sum of
the clock widths (tWICL + tWICH). The clock widths are nor-
mally the limiting parameters, so that fMAXIR is specified
as 1/(tWICL + tWICH). Note that if both input and output reg-
istersareuseinthesamepath, theoverallfrequencywill
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this pa-
be limited by tICS
.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is meas-
ured directly.
rameter is sometimes called “fCNT.
”
CLK
CLK
(SECOND
CHIP)
LOGIC
REGISTER
LOGIC
REGISTER
tS
tS
tCO
fMAX External; 1/(tS + tCO
)
f
MAX Internal (fCNT
)
CLK
CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS
tSIR
tHIR
fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL
)
14132I-23
24
MACH230-10/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our
advanced Electrically Erasable process. This technol-
ogy uses an EE cell to replace the fuse link used in
bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.
Endurance Characteristics
Parameter
Symbol
Parameter Description
Min
Units
Test Conditions
10
Years
Max Storage
Temperature
Min Pattern Data Retention Time
Max Reprogramming Cycles
tDR
N
20
Years
Max Operating
Temperature
100
Cycles
Normal Programming
Conditions
MACH230-10/15/20
25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 kΩ
VCC
1 kΩ
ESD
Protection
Input
VCC
VCC
100 kΩ
1 kΩ
Preload Feedback
Circuitry
Input
14132I-24
I/O
26
MACH230-10/15/20
POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Max
Unit
tPR
tS
10
µs
See
Switching
Characteristics
tWL
VCC
4 V
Power
tPR
Registered
Output
tS
Clock
tWL
14132I-25
Power-Up Reset Waveform
MACH230-10/15/20
27
USING PRELOAD AND OBSERVABILITY
Inordertobetestable, acircuitmustbebothcontrollable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.
Preloaded
HIGH
D
Q1
In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.
Q
AR
Preloaded
HIGH
The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.
D
Q2
Q
AR
While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.
Onecaseinvolvesasynchronousresetandpreset. Ifthe
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.
On
Off
Preload
Mode
Q1
Another case to be aware of arises in testing combinato-
rial logic. When an output is configured as combinato-
rial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in
Fugure 3. As this value may change during the preload
or observe operation, you cannot count on the data
being correct after the operation. To insure valid testing
in these cases, outputs that are combinatorial latches
should not be tested immediately following a preload or
observe sequence, but should first be restored to a
known state.
AR
Q2
Figure 2. Preload/Reset Conflict
14132I-26
Set
All MACH 2 devices support both preload and
observability.
Reset
Contact individual programming vendors in order to
verify programmer support.
Figure 3. Combinatorial Latch
14132I-27
28
MACH230-10/15/20
PHYSICAL DIMENSIONS*
PL 084
84-Pin Plastic Leaded Chip Carrier (measured in inches)
.062
.083
1.185
1.195
.042
.056
1.150
1.156
1.090
1.130
1.000
REF
Pin 1 I.D.
1.185
1.195
1.150
1.156
.013
.021
.007
.013
.026
.032
.090
.130
.165
.180
.050 REF
SEATING PLANE
16-038-SQ
PL 084
DF79
8-1-95 ae
TOP VIEW
SIDE VIEW
*For reference only. BSC is an ANSI standard for Basic Space Centering.
MACH230-10/15/20
33
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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