LD8108A [LEADTREND]
AC/DC Speedy Charge⢠Controller for Charge 2.0 USB Interface;型号: | LD8108A |
厂家: | Leadtrend Technology |
描述: | AC/DC Speedy Charge⢠Controller for Charge 2.0 USB Interface |
文件: | 总13页 (文件大小:971K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LD8108A
08/02/2016
AC/DC Speedy Charge™ Controller for
Qualcomm® Quick Charge 2.0 USB Interface
REV. 00
General Description
Features
Speedy ChargeTM technology
The LD8108A is an AC/DC Speedy Charge™
controller for Qualcomm® Quick Charge™ 2.0 (QC2.0)
USB interface receiver for High Voltage Dedicated
Charging Port (HVDCP) charger solution.
Compatible with Qualcomm® Quick Charge™ 2.0
class-A portable devices charger solution
Fast discharging from HVDCP voltage to 5V
Active dummy load for PSR controller
Secondary side over temperature detection
Low operating current
The device can receive QC2.0 signal from D+ and D-
of USB interface for HVDCP control. Paired with LD5718A
series primary-side regulation (PSR) controllers, LD8108A
will send the digital data by a single photocouplier to PSR
controller and change output regulation.
VCC max. rating up to 30V
Applications
LD8108A provides typical 300mA discharging current
for output from HVDCP voltage to 5V in order to meet a
short discharge time. Active dummy load function is built
in LD8108A to keep output regulation while in no load
condition. LD8108A implements temperature detection
function which will send digital data to shutdown PSR
controller during over temperature condition.
Quick Charge™ 2.0 based HVDCP charger
AC/DC Speedy Charger for Smart phone and Tablet
The LD8108A is available in both SOP-8 package.
Typical Application
AC
Input
EMI
Filter
AC
Input
DIS
VCC
VCC
ST
OUT
LD8108A
DET
OPTOD
OTD
D+
D-
GND
FB
LD5718A
NTC
COMP
OPTO/
OTP
CS
GND
NTC
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LD8108A-DS-00 August 2016
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Pin Configuration
S O P-8 ( T O P V I E W )
8
6
5
7
Y Y :
W W :
P P :
Y e a r c o d e
W e e k c o d e
P r o d u c t i o n
T O P M A R
Y Y W W P P
1
2
3
4
Ordering Information
Part number TTimeout
VDET_T
Package
Top Mark
Shipping
2500 /tape & reel
LD8108A GS
900µs
4.0V
SOP-8
LD8108AGS
The LD8108A is ROHS compliant/ Green Packaged.
Pin Descriptions
Pin
NAME
FUNCTION
Typical 100uA sourcing current to a thermistor for over temperature detection
1
OTD
function
A typical 5mA driving current for a photocoupler to transmit the voltage
2
OPTOD
regulation setting and fault signal
3
4
D+
D-
USB D+ signal.
USB D- signal.
Primary side switching frequency detection for Vo discharge detection and
5
DET
active dummy load control.
6
7
8
GND
DIS
Ground.
Discharging for fast change output regulation or active dummy load.
Supply voltage pin.
VCC
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Block Diagram
External Over
Temperature
Detection
Primary Side
Fault Behaveior
TJ Detection
IDIS_ON
Int. OTP
OTD
DET
GND
DIS
Loading
Det.
Dummy Load &
Discharge
Discharge
Control
VCC
Detection
IDIS_DMY IVCC_DMY
Active
Dummy Load
Control
Internal Supply
UVLO
QC Disable or
Regulation Down
Primary Side
Fault Behavior
VCC
Regulation
Command
Output Voltage
Detection
Regulation
Check
QC2.0
Interface
Digital Signal
Ttransmitter
D+
D-
OTPOD
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Absolute Maximum Ratings
Supply Voltage VCC, DIS
-0.3V ~ 30V
-0.8V ~ 6V
-0.3V ~ 6V
-3mA ~ 3mA
150C
DET (IDET = -1mA ~ +1mA)
D+, D-, OPTO, OTD
IDET
Maximum Junction Temperature
Storage Temperature Range
Package Thermal Resistance, SOP-8, JA
Power Dissipation (SOP-8, at Ambient Temperature = 85C)
Lead Temperature (Soldering, 10sec)
ESD Level (Human Body Model)
ESD Level (Machine Model)
-65C ~ 125C
160 C/W
250mW
260C
2.5KV
250V
Recommended Operating Conditions
RDET
75kΩ ~ 120kΩ
-40C ~ 125C
Junction Temperature Range
Caution:
Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stress above Recommended Operating Conditions may affect
device reliability.
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Electrical Characteristics
(TA = +25C unless otherwise stated, VCC=5.0V)
PARAMETER
UVLO & Operating Current (VCC Pin)
UVLO(ON)
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
VUVLO_ON
VUVLO_OFF
VUVLO_HYS
VVCC_FAST
IOP
3.9
3.7
0.1
4.1
3.9
0.2
4.4
0.5
5
4.3
4.1
0.3
V
V
UVLO(OFF)
UVLO(ON) - UVLO(OFF)
V
Fast Response Threshold Level
*
V
Operating Current
1st Active Dummy Load of VCC
0.35
4
0.6
6.3
mA
mA
IVCC_DMY
Switching Pulse Detetion (DET Pin)
Upper Clamp Voltage
IDET = +1mA
VDET_UP2
ZDET
5
6
V
MΩ
V
Input Impendence
2.4
-0.8
3.7
3
3.6
0.5
4.1
Low Clamp Voltage
IDET = -1mA
*
VDET_L2
VDET_TH
TDET_T
Switching Pulse Trip Level
Switching Pulse Trip Debounce
Switching Puse Timeout for
Active Dummy Load Turn-on
1st Active Dummy Load Turn-on
Debounce
4.0
V
100
ns
TTIMEOUTA
TDMY_ONA
TDIS_ON
700
7
900
8
1000
9
µs
ms
ms
2nd Active Dummy Load Turn-on
70
75
92
Debounce
Output Discharge (DIS Pin)
Turn-off state leakage current
Maximum Turn-on Current (2nd
Active Dummy Load)
VCC = 4V, VDIS = 12V
VDIS > 5V
IDIS_OFF
IDIS_ON
IDISDMY
3
20
300
5.5
µA
mA
mA
150
3.5
1st Active Dummy Load of DIS
VDIS > 5V
5
Output Regulation Check (VCC Pin)
D+ = 3.3V, D- = 0.6V
VCCD9
VCCD5
8.1
9.00
5.00
9.9
VCC Trip Level for Stop
Discharge
VCC Trip Level for Enable 2nd
V
V
D+ =0.6V, D- = 0V
4.75
5.25
D+ = 0V, D- = 0V
VCCDISEN
5.3
5.6
6.4
Active Load
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PARAMETER
CONDITIONS
SYMBOL
MIN
90
TYP
MAX
UNITS
Over Temperature Detection (OTD Pin)
OTD Pin Source Current
IOTD
VOTD_OL
VOTP
100
110
5.5
1.1
µA
V
OTD Pin Open Loop Voltage
Over Temperature Threshold
Over Temperature Release
Threshold
*
0.9
1.00
1.10
V
*
VOTP_R
V
Over Temperature Threshold
Debounce
TOTD
150
4
250
5
350
5.5
µs
Photocoupler Driver (OPTOD Pin)
Photocoupler Driving Current
QC 2.0 Interface (D+ & D- Pin)
D+ & D- Data detect voltage
IOPTOD
mA
VDAT_REF
VSEL_REF
0.25
1.8
0.325
2.0
0.40
2.2
V
V
Output
Voltage
Selection
Reference
D+ high glitch filter time
TBC_DONE
RDAT_LKG
RDM_DWM
1000
400
1250
500
19
1500
600
ms
kΩ
kΩ
D+ Pull Down Resistance
D- Pull Down Resistance
*: Guaranteed by design.
14.25
24.5
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Typical Performance Characteristics
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Application Information
class-A, the output voltage could be regulated from 5V,
9V to 12V. LD8108A had passed UL verification to ensure
whole system working well.
Operation Overview
The LD8108A is Qualcomm® Quick Charge™ 2.0
(QC2.0) USB interface receiver for AC/DC Speedy
Charge™ High Voltage Dedicated Charging Port (HVDCP)
charger solution. Paired with AC/DC primary-side
regulation (PSR) controllers like LD5718A series IC, the
output voltage can be programmed from 5V, 9V to 12V in
order to boost more output power.
D+
D-
Output
12V
Class-A
Class-B
0.6V
3.3V
3.3V
0.6V
0.6V
3.3V
V
V
V
V
V
9V
20V
5V
0.6V
GND
V
V
(default)
LD8108A supports fast discharge function with
maximum 300mA discharging current while in a higher
voltage level to a default 5V within 0.5 second. So that it is
easily suitable and safe for general USB devices.
LD8108A is built-in active dummy load which improves
system efficiency and keeps quite low power consumption
in no load condition. LD8108A implements temperature
detection over OTD pin and will issue over temperature
protection(OTP) signal to primary-side controller only by a
single photocoupler.
Table 1
D+
+
-
2V
500k
Ω
+
-
Int. Bias
0.325V
On/Off
Control
Logic
Circuit
+
-
2V
OPTOD
D-
+
-
0.325V
19kΩ
On/Off
Control
Under Voltage Lockout (UVLO)
LD8108A
An UVLO comparator is implemented in the chip that
can detect the voltage across VCC pin and shutdown
the IC while in low VCC condition. It can be assure the
supply voltage is enough for controller operating. The
maxium rating of VCC would be 30V which is easily and
suitable for speedy charger design.
LD PSR Solution
(ex: LD5718A)
Int. Bias of PSR
Digital signal
Command
OPTO
Verf for
+
Error Amp.
Regulatio
n
-
0.3V
Photocoupler
Fig. 10
QC2.0 Interface
Speedy Charge™
LD8108A is compatible with Qualcomm® Quick
Charge™ 2.0 (QC2.0) protocol for High Voltage
Dedicated Charging Port (HVDCP) class-A system design.
As to the demand of larger battery usage in many
protable devides (PDs) now, Leadttrend Tech. develops a
total solution for fast charging technology and interface
that can provide safer and more flexiable topology for
speedy charger power design.
Please refer to Table
1 for the voltage setting
configulation. When LD8108A receives the command
from D+ and D- signal from USB port, LD8108A will
decode the command and transmit it to primary side
controller via a photocoupler to set the output voltage, the
function block diagram is shown as Fig 10. For QC2.0
LD8108A is built-in such a technology that secondary
side transmits signals to primary side via a single
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photocoupler. By such technology, the system can easily
be designed with more cost effective and better
performance.
+
VO
-
RDIS
DIS
VCC
LD8108A
Photocoupler driver (OPTOD)
Vo < Vset
Regulation Check
RDET
LD8108A integrates Speedy Charge™ technology
that secondary-side IC transmits commands to
primary-side controller, like LD5718A series. For example,
the commands include the output voltage setting and also
the over temperature protection (OVP).
tPLUSE
< timeout
Loading Det.
DET
Time’s up
Min. Discharge
Time
D+
D-
Int. OTP
Int. Bias
R
S
Q
Fast Discharging
QC 2.0
Interface
USB
LD8108A supports fast discharging function, the
block diagram shown as Fig. 11 which regulates the
output voltage to 5V within a short time when the output
voltage is set low or the output cable is unplugged.
Especially for speedy charge device unpluging condition
from USB cable, it’s necessary for a standard 5V USB
device within 0.5 sec discharging.
Regulation
Down
Regulation Command
OPTOD
Fig. 11
Active Dummy Load
As well known, Primary-Side Regulation (PSR)
controller must keep power MOSFET switching to sense
the output voltage which will generate extra engery to the
output at light load. However, in order to consume these
unnecessary energy to ouput, designers have to add a
dymmy load at output to keep the regulation. But the
dummy load will cause additional efficiency loss,
especially in higher output voltage levels like 9V, 12V.
The command of discharging function is applied from
D+/D- signal. The output will be discharged from DIS pin
while the discharge current can be fine-tuned by external
resistor RDIS and to avoid lots of power dissipation and
heat through IC package. The maximum discharging
current of LD8108A is around 300mA.
LD8108A is built-in active dummy load function, it will
turn-off dummy load during free running condition for
efficiency improvement. Please refer to the block diagram
shown as Fig. 12. The function which is according to DET
pulse frequency is determined in no load condition. The
dummy load will be turned-on if PSR controller switching
cycle time is more than 900µs for LD8108A and lasts for
more than debounce time. Once the dummy load causes
PSR switching cycle time less than 900µs for LD8108A,
the dummy load will be turned-off, please refer to the
waveforms as Fig 13.
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LD8108A will also provide 2nd active dummy load for
fast dischange function which is suitable for another
HVDCP solution, MediaTek Pump Express Plus™. The
2nd dummy load will be turned-on if the 1st dummy load
keeps turn on and last for 75ms during a higher level
output regulation condition without QC 2.0 mode, please
refer to the waveforms as shown in Fig. 14.
Regulation
= high level
Regulation = 5V
Vo
7V or 9V or 12V
5V
t
IDIS
2nd Dummy Load
75ms
1st Dummy Load
+
VO
-
t
t
RDIS
Io
DIS
VCC
Active Mode
No Load
Fig. 14
RDET
Switching
Pulse Det.
DET
Low Freq.
Det.
1st Dummy
Load
tPULSE> 900µs
1st Debounce
(8ms)
2nd Dummy
Load
2nd Debounce
(75ms)
Regulation
Check
> 5.6V
EN
QC 2.0
Interface
D+
D-
QC Mode
Fig. 12
Vo
※△VO < Ripple Spec
tPULSE > timeout
tPULSE < timeout
t
VDET
IDIS + IVCC
t
t
timeout
1st Debounce
Fig. 13
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Package Information
SOP-8
Dimensions in Millimeters
Dimensions in Inch
Symbols
MIN
MAX
MIN
MAX
A
B
C
D
4.801
3.810
1.346
0.330
5.004
3.988
1.753
0.508
0.189
0.150
0.053
0.013
0.197
0.157
0.069
0.020
F
H
I
1.194
0.178
0.102
5.791
0.406
0°
1.346
0.254
0.254
6.198
1.270
8°
0.047
0.007
0.004
0.228
0.016
0°
0.053
0.010
0.010
0.244
0.050
8°
J
M
θ
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.
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Revision History
REV.
00
Date
Change Notice
08/02/2016
Original Specification
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