LT1469-2 [Linear]
Dual 200MHz, 30V/μs 16-Bit Accurate AV ≥ 2 Op Amp; 200MHz的双通道， 30V /μs的16位精度的AV ≥ 2运算放大器
| 型号： | LT1469-2 |
| 厂家： | 
Linear |
| 描述： | Dual 200MHz, 30V/μs 16-Bit Accurate AV ≥ 2 Op Amp |
| 文件： | 总12页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1469-2
Dual 200MHz, 30V/µs
16-Bit Accurate A ≥ 2 Op Amp
V
FEATURES
DESCRIPTION
The LT®1469-2 is a dual, precision high speed opera-
tional amplifier with 16-bit accuracy, decompensated to
be stable in a gain of 2 or greater. The combination of
precision and AC performance makes the LT1469-2 the
optimum choice for high accuracy applications such as
DAC current-to-voltage conversion and ADC buffers. The
initial accuracy and drift characteristics of the input offset
voltage and inverting input bias current are tailored for
inverting applications.
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Stable in Gain A ≥ 2 (A = –1)
V
V
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n
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n
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200MHz Gain Bandwidth Product
30V/μs Slew Rate
Settling Time: 800ns (150ꢀV, 10V Step)
Specified at 5V and 15V Supplies
Maximum Input Offset Voltage: 125μV
Low Distortion: ꢀ96.±dB for 100kHz, 105
P-P
Maximum Input Offset 5oltage Drift: 3μ5/ꢁC
Maximum Inverting Input Bias Current: 10nA
Minimum DC Gain: 3005/m5
Minimum Output Swing into 2k: ±12.ꢂ5
Input Noise 5oltage: ±n5/√Hz
Input Noise Current: 0.6pA/√Hz
The 200MHz gain bandwidth ensures high open-loop gain
at frequency for reducing distortion. In noninverting ap-
plications such as an ADC buffer, the low distortion and
DC accuracy allow full 16-bit AC and DC performance.
The high slew rate of the LT1469-2 improves large-signal
performance in applications such as active filters and
instrumentation amplifiers compared to other precision
op amps.
Total Input Noise Optimized for 1kΩ < R < 20kΩ
Available in ꢂ-Lead Plastic SO and
S
12-Lead (4mm × 4mm) DFN Packages
APPLICATIONS
The LT1469-2 is specified on power supply voltages of
±±5 and ±1±5 and from ꢀ40ꢁC to ꢂ±ꢁC. It is available in
an ꢂ-lead SOIC package and a space saving 4mm × 4mm
leadlesspackage.Foraunity-gainstableopampwithsame
DC performance, see the LT1469 datasheet.
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Precision Instrumentation
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High Accuracy Data Acquisition Systems
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16-Bit DAC Current-to-5oltage Converter
ADC Buffer
Low Distortion Active Filters
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L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
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Photodiode Amplifiers
TYPICAL APPLICATION
16-Bit DAC I-to-V Converter
Large-Signal Transient, AV = –1
5
A
R
C
= ±1±5
= ꢀ1
S
5
F
105
20pF
= R = 2k
G
16
= 22pF
6k
F
DAC
ꢀ
INPUTS
2k
1/2
5
25/DI5
05
OUT
LT1469-2
LTC®1±97
+
±0pF
OPTIONAL NOISE FILTER
OFFSET: 5 + I (6kꢃ) < 1LSB
OS
B
SETTLING TIME TO 1±0μ5 = 1.6μs
SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE
14692 TA01a
200ns/DI5
14692 TA02
14692f
1
LT1469-2
(Note 1)
ABSOLUTE MAXIMUM RATINGS
+
ꢀ
Total Supply 5oltage (5 to 5 ).................................365
Input Current (Note 2)..........................................±10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4).... ꢀ40ꢁC to ꢂ±ꢁC
Specified Temperature Range (Note ±) .... ꢀ40ꢁC to ꢂ±ꢁC
Maximum Junction Temperature........................... 1±0ꢁC
Storage Temperature Range................... ꢀ6±ꢁC to 1±0ꢁC
PIN CONFIGURATION
TOP 5IEW
+
TOP 5IEW
1
2
3
4
±
6
5
12
OUT A
ꢀIN A
+IN A
+
5
OUT A
ꢀIN A
+IN A
1
2
3
4
ꢂ
7
6
±
11 OUT B
A
ꢀIN B
+IN B
N/C
10
9
OUT B
ꢀIN B
+IN B
13
B
ꢀ
A
5
ꢂ
N/C
N/C
B
ꢀ
5
7
N/C
Sꢂ PACKAGE
ꢂ-LEAD PLASTIC SO
= 1±0ꢁC, θ = 190ꢁC/W
DF PACKAGE
12-LEAD (4mm × 4mm) PLASTIC DFN
= 1±0ꢁC, θ = 37ꢁC/W
T
T
JMAX
JA
JMAX
JA
ꢀ
EXPOSED PAD (PIN 13) IS GND, MUST BE CONNECTED TO 5
ORDER INFORMATION
LEAD FREE FINISH
LT1469CSꢂ-2#PBF
LT1469ISꢂ-2#PBF
LT1469ACDF-2#PBF
LT1469AIDF-2#PBF
LT1469CDF-2#PBF
LT1469IDF-2#PBF
TAPE AND REEL
PART MARKING*
14692
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0ꢁC to 70ꢁC
LT1469CSꢂ-2#TRPBF
LT1469ISꢂ-2#TRPBF
LT1469ACDF-2#TRPBF
LT1469AIDF-2#TRPBF
LT1469CDF-2#TRPBF
LT1469IDF-2#TRPBF
ꢂ-Lead Plastic Small Outline
14692
ꢂ-Lead Plastic Small Outline
ꢀ40ꢁC to ꢂ±ꢁC
0ꢁC to 70ꢁC
14692
12-Lead (4mm × 4mm) Plastic DFN
12-Lead (4mm × 4mm) Plastic DFN
12-Lead (4mm × 4mm) Plastic DFN
12-Lead (4mm × 4mm) Plastic DFN
14692
ꢀ40ꢁC to ꢂ±ꢁC
0ꢁC to 70ꢁC
14692
14692
ꢀ40ꢁC to ꢂ±ꢁC
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
Input Offset 5oltage
Sꢂ Package
±1±5
±±5
±0
±0
12±
200
μ5
μ5
OS
LT1469A, DF Package
LT1469, DF Package
±1±5
±±5
±0
±0
12±
200
μ5
μ5
±1±5
±±5
100
1±0
22±
300
μ5
μ5
I
Input Offset Current
±±5 to ±1±5
13
±±0
nA
OS
14692f
2
LT1469-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
3
MAX
±10
±40
UNITS
nA
SUPPLY
I ꢀ
Inverting Input Bias Current
Noninverting Input Bias Current
Input Noise 5oltage
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
B
I +
B
ꢀ10
0.3
±
nA
0.1Hz to 10Hz
f = 10kHz
μ5
P-P
e
Input Noise 5oltage Density
Input Noise Current Density
Input Resistance
n5/√Hz
pA/√Hz
n
i
n
f = 10kHz
0.6
R
Common Mode, 5 = ±12.±5
Differential
±1±5
±1±5
100
±0
240
1±0
MΩ
kΩ
IN
CM
C
5
Input Capacitance
±1±5
4
pF
IN
Input 5oltage Range (Positive)
Guaranteed by CMRR
Guaranteed by CMRR
±1±5
±±5
12.±
2.±
13.±
3.6
5
5
CM
Input 5oltage Range (Negative)
Common Mode Rejection Ratio
±1±5
±±5
ꢀ14.3
ꢀ4.4
ꢀ12.±
ꢀ2.±
5
5
CMRR
PSRR
5
CM
5
CM
= ±12.±5
= ±2.±5
±1±5
±±5
96
96
110
112
dB
dB
Minimum Supply 5oltage
Power Supply Rejection Ratio
Large-Signal 5oltage Gain
Guaranteed by PSRR
5 = ±4.±5 to ±1±5
±2.±
112
±4.±
5
100
dB
S
A
5OL
5
OUT
5
OUT
5
OUT
5
OUT
= ±12.±5, R = 10k
±1±5
±1±5
±±5
300
300
200
200
2000
2000
ꢂ000
ꢂ000
5/m5
5/m5
5/m5
5/m5
L
= ±12.±5, R = 2k
L
= ±2.±5, R = 10k
L
= ±2.±5, R = 2k
±±5
L
5
Maximum Output Swing
Maximum Output Current
R = 10k, 1m5 Overdrive
±1±5
±1±5
±±5
±13.0 ±13.6
±12.ꢂ ±13.±
5
5
5
5
OUT
L
R = 2k, 1m5 Overdrive
L
R = 10k, 1m5 Overdrive
±3.0
±2.ꢂ
±3.7
±3.6
L
R = 2k, 1m5 Overdrive
±±5
L
I
I
5
OUT
5
OUT
= ±12.±5, 1m5 Overdrive
= ±2.±5, 1m5 Overdrive
±1±5
±±5
±1±
±1±
±22
±22
mA
mA
OUT
Output Short-Circuit Current
Slew Rate
5
OUT
= 05, 0.25 Overdrive (Note 3)
±1±5
±2±
±40
mA
SC
SR
R = 2k (Note 6)
L
±1±5
±±5
20
1±
30
22
5/μs
5/μs
FPBW
GBW
Full-Power Bandwidth
Gain Bandwidth Product
Settling Time
105 Peak, (Note 7)
35 Peak, (Note 7)
±1±5
±±5
47±
kHz
kHz
1160
f = 100kHz, R = 2k
±1±5
±±5
140
130
200
190
MHz
MHz
L
t
S
105 Step, 0.01%, A = ꢀ1
105 Step, 1±0μ5, A = ꢀ1
±1±5
±1±5
6±0
ꢂ00
ns
ns
5
5
R
Output Resistance
Channel Separation
A = ꢀ1, f = 100kHz
±1±5
0.02
Ω
OUT
5
5
OUT
5
OUT
= ±12.±5, R = 2k
±1±5
±±5
100
100
130
130
dB
dB
L
= ±2.±5, R = 2k
L
I
S
Supply Current
Per Amplifier
±1±5
±±5
4.1
3.ꢂ
±.2
±
mA
mA
Δ5
OS
Input Offset 5oltage Match
±1±5
±±5
30
±0
22±
3±0
μ5
μ5
ΔI ꢀ
Inverting Input Bias Current Match
Noninverting Input Bias Current Match
Common Mode Rejection Match
±±5 to ±1±5
±±5 to ±1±5
2
±
1ꢂ
7ꢂ
nA
nA
B
ΔI +
B
ΔCMRR
5
CM
5
CM
= ±12.±5 (Note 9)
= ±2.±5 (Note 9)
±1±5
±±5
93
93
113
11±
dB
dB
ΔPSRR
Power Supply Rejection Match
5 = ±4.±5 to ±1±5 (Note 9)
S
97
11±
dB
14692f
3
LT1469-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, 0°C ≤ TA ≤ 70°C. VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
Input Offset 5oltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
Sꢂ Package
±1±5
±±5
●
●
3±0
3±0
μ5
μ5
OS
LT1469A, DF Package
LT1469, DF Package
(Note ꢂ)
±1±5
±±5
●
●
22±
27±
μ5
μ5
±1±5
±±5
●
●
4±0
4±0
μ5
μ5
Δ5 /ΔT Input Offset 5oltage Drift
OS
±1±5
±±5
●
●
1
1
±
3
μ5/ꢁC
μ5/ꢁC
I
Input Offset Current
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
●
●
●
●
●
±ꢂ0
±20
±60
nA
pA/ꢁC
nA
OS
ΔI /ΔT
Input Offset Current Drift
(Note ꢂ)
(Note ꢂ)
60
40
OS
I ꢀ
Inverting Input Bias Current
Inverting Input Bias Current Drift
Noninverting Input Bias Current
Input 5oltage Range (Positive)
B
ΔI ꢀ/ΔT
pA/ꢁC
nA
B
I +
B
5
Guaranteed by CMRR
Guaranteed by CMRR
±1±5
±±5
●
●
12.±
2.±
5
5
CM
Input 5oltage Range (Negative)
Common Mode Rejection Ratio
±1±5
±±5
●
●
ꢀ12.±
ꢀ2.±
5
5
CMRR
PSRR
5
5
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
●
●
94
94
dB
dB
5
CM
CM
Minimum Supply 5oltage
Power Supply Rejection Ratio
Large-Signal 5oltage Gain
Guaranteed by PSRR
5 = ±4.±5 to ±1±5
±4.±
9±
dB
S
A
5
OUT
5
OUT
5
OUT
5
OUT
= ±12.±5, R = 10k
±1±5
±1±5
±±5
●
●
●
●
100
100
100
100
5/m5
5/m5
5/m5
5/m5
5OL
L
L
= ±12.±5, R = 2k
= ±2.±5, R = 10k
= ±2.±5, R = 2k
L
L
±±5
5
Maximum Output Swing
Maximum Output Current
R = 10k, 1m5 Overdrive
±1±5
±1±5
±±5
●
●
●
●
±12.9
±12.7
±2.9
5
5
5
5
OUT
L
R = 2k, 1m5 Overdrive
L
R = 10k, 1m5 Overdrive
L
R = 2k, 1m5 Overdrive
±±5
±2.7
L
I
I
5
OUT
5
OUT
= ±12.±5, 1m5 Overdrive
= ±2.±5, 1m5 Overdrive
±1±5
±±5
●
●
±12.±
±12.±
mA
mA
OUT
Output Short-Circuit Current
Slew Rate
5
OUT
= 05, 0.25 Overdrive (Note 3)
±1±5
●
±17
mA
SC
SR
R = 2k (Note 6)
L
±1±5
±±5
●
●
1ꢂ
13
5/μs
5/μs
GBW
Gain Bandwidth Product
Channel Separation
Supply Current
f = 100kHz, R = 2k
±1±5
±±5
●
●
130
120
200
190
MHz
MHz
L
5
OUT
5
OUT
= ±12.±5, R = 2k
±1±5
±±5
●
●
9ꢂ
9ꢂ
dB
dB
L
= ±2.±5, R = 2k
L
I
S
Per Amplifier
±1±5
±±5
●
●
6.±
6.3
mA
mA
Δ5
Input Offset 5oltage Match
±1±5
±±5
●
●
600
600
μ5
μ5
OS
ΔI ꢀ
Inverting Input Bias Current Match
Noninverting Input Bias Current Match
Common Mode Rejection Match
±±5 to ±1±5
±±5 to ±1±5
●
●
3ꢂ
nA
nA
B
ΔI +
B
11ꢂ
ΔCMRR
5
CM
5
CM
= ±12.±5 (Note 9)
= ±2.±5 (Note 9)
±1±5
±±5
●
●
91
91
dB
dB
ΔPSRR
Power Supply Rejection Match
5 = ±4.±5 to ±1±5 (Note 9)
S
●
92
dB
14692f
4
LT1469-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted. (Note 5)
SYMBOL PARAMETER
Input Offset 5oltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
Sꢂ Package
±1±5
±±5
●
●
±00
±00
μ5
μ5
OS
LT1469A, DF Package
LT1469, DF Package
(Note ꢂ)
±1±5
±±5
●
●
300
3±0
μ5
μ5
±1±5
±±5
●
●
600
600
μ5
μ5
Δ5 /ΔT Input Offset 5oltage Drift
OS
±1±5
±±5
●
●
1
1
6
±
μ5/ꢁC
μ5/ꢁC
I
Input Offset Current
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
●
●
●
●
●
±120
nA
pA/ꢁC
nA
OS
ΔI /ΔT
Input Offset Current Drift
(Note ꢂ)
(Note ꢂ)
120
ꢂ0
OS
I ꢀ
Inverting Input Bias Current
Inverting Input Bias Current Drift
Noninverting Input Bias Current
Input 5oltage Range (Positive)
±40
B
ΔI ꢀ/ΔT
pA/ꢁC
nA
B
I +
±ꢂ0
B
5
Guaranteed by CMRR
Guaranteed by CMRR
±1±5
±±5
●
●
12.±
2.±
5
5
CM
Input 5oltage Range (Negative)
Common Mode Rejection Ratio
±1±5
±±5
●
●
ꢀ12.±
ꢀ2.±
5
5
CMRR
PSRR
5
CM
5
CM
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
92
92
dB
dB
±4.±
Minimum Supply 5oltage
Power Supply Rejection Ratio
Large-Signal 5oltage Gain
Guaranteed by PSRR
5 = ±4.±5 to ±1±5
●
●
5
93
dB
S
A
5
OUT
5
OUT
5
OUT
5
OUT
= ±12,±5, R = 10k
±1±5
±1±5
±±5
●
●
●
●
7±
7±
7±
7±
5/m5
5/m5
5/m5
5/m5
5OL
L
L
= ±12.±5, R = 2k
= ±2.±5, R = 10k
= ±2.±5, R = 2k
L
L
±±5
5
Maximum Output Swing
Maximum Output Current
R = 10k, 1m5 Overdrive
±1±5
±1±5
±±5
●
●
●
●
±12.ꢂ
±12.6
±2.ꢂ
5
5
5
5
OUT
L
R = 2k, 1m5 Overdrive
L
R = 10k, 1m5 Overdrive
L
R = 2k, 1m5 Overdrive
±±5
±2.6
L
I
I
5
OUT
5
OUT
= ±12.±5, 1m5 Overdrive
= ±2.±5, 1m5 Overdrive
±1±5
±±5
●
●
±7
±7
mA
mA
OUT
Output Short-Circuit Current
Slew Rate
5
OUT
= 05, 0.25 Overdrive (Note 3)
±1±5
●
±12
mA
SC
SR
R = 2k (Note 6)
L
±1±5
±±5
●
●
1±
11
5/μs
5/μs
GBW
Gain Bandwidth Product
Channel Separation
f = 100kHz, R = 2k
±1±5
±±5
●
●
110
100
200
190
MHz
MHz
L
5
OUT
5
OUT
= ±12.±5, R = 2k
±1±5
±±5
●
●
96
96
dB
dB
L
= ±2.±5, R = 2k
L
I
Supply Current
Per Amplifier
±1±5
±±5
●
●
7
6.ꢂ
mA
mA
S
Δ5
OS
Input Offset 5oltage Match
±1±5
±±5
●
●
ꢂ00
ꢂ00
μ5
μ5
ΔI ꢀ
Inverting Input Bias Current Match
±±5 to ±1±5
±±5 to ±1±5
●
●
7ꢂ
nA
nA
B
ΔI +
B
Noninverting Input Bias Current
Match
1±ꢂ
ΔCMRR
ΔPSRR
Common Mode Rejection Match
5
5
= ±12.±5 (Note 9)
= ±2.±5 (Note 9)
±1±5
±±5
●
●
ꢂ9
ꢂ9
dB
dB
CM
CM
Power Supply Rejection Match
5 = ±4.±5 to ±1±5 (Note 9)
S
●
90
dB
14692f
5
LT1469-2
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The LT1469C-2 is guaranteed to meet specified performance from
0ꢁC to 70ꢁC and is designed, characterized and expected to meet specified
performance from ꢀ40ꢁC to ꢂ±ꢁC but is not tested or QA sampled at these
temperatures. The LT1469I-2 is guaranteed to meet specified performance
from ꢀ40ꢁC to ꢂ±ꢁC.
Note 6: Slew rate is measured between ±ꢂ5 on the output with ±125
swing for ±1±5 supplies and ±25 on the output with ±35 swing for ±±5
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.75, the input
current should be limited to less than 10mA. Input voltages outside the
supplies will be clamped by ESD protection devices and input currents
should also be limited to less than 10mA.
supplies. Tested in A = ꢀ10
5
Note 7: Full-power bandwidth is calculated from the slew rate.
Note 3: A heat sink may be required to keep the junction temperature
FPBW = SR/2π5 .
P
below absolute maximum when the output is shorted indefinitely.
Note 8: This parameter is not 100% tested.
Note 4: The LT1469C-2 and LT1469I-2 are guaranteed functional over the
operating temperature range of ꢀ40ꢁC to ꢂ±ꢁC.
Note 9: ΔCMRR and ΔPSRR are defined as follows: 1) CMRR and PSRR
are measured in μ5/5 on each amplifier; 2) the difference between the two
sides is calculated in μ5/5; 3) the result is converted to dB.
TYPICAL PERFORMANCE CHARACTERISTICS
Distribution of Input Offset
Voltage
Distribution of Inverting Input
Bias Current
Supply Current vs Supply Voltage
and Temperature
±0
40
30
20
10
0
40
30
20
10
0
6
±
4
3
2
1
5
= ±1±5
= 2±ꢁC
5
= ±1±5
= 2±ꢁC
S
A
S
A
ꢂ±ꢁC
2±ꢁC
T
T
ꢀ40ꢁC
ꢀ17± ꢀ12± ꢀ7± ꢀ2± 2±
7± 12± 17±
ꢀ10 ꢀ7.± ꢀ± ꢀ2.±
0
2.±
±
7.± 10
0
±
10
1±
20
SUPPLY 5OLTAGE (±5)
INPUT OFFSET 5OLTAGE (μ5)
IN5ERTING INPUT BIAS CURRENT (nA)
14692 G01
14692 G02
14692 G03
Total Noise vs Unmatched
Source Resistance
Input Noise Spectral Density
0.1Hz to 10Hz Voltage Noise
100
1000
100
10
1
5
= ±1±5
= 2±ꢁC
S
A
5
= ±1±5
= 2±ꢁC
S
A
5
= ±1±5
= 2±ꢁC
= 101
S
A
5
T
T
T
f = 10kHz
A
R
= 100k FOR i
S
n
TOTAL
NOISE
i
n
10
1
RESISTOR
NOISE ONLY
e
n
R
10
1
0.1
S
+
ꢀ
0.1
0.01
TIME (1s/DI5)
10
100
1k
10k
100k
1
10
100
1k
10k
100k
14692 G0±
SOURCE RESISTANCE, R (ꢃ)
FREQUENCY (Hz)
S
14692 G06
14692 G04
14692f
6
LT1469-2
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current
vs Temperature
Input Bias Current
Input Common Mode Range
vs Supply Voltage
vs Input Common Mode Voltage
+
30
20
ꢂ0
60
5
T
= 2±ꢁC
OS
5
= ±1±5
A
5
T
= ±1±5
= 2±ꢁC
S
S
A
ꢀ0.±
ꢀ1.0
ꢀ1.±
ꢀ2.0
Δ5 < 100μ5
40
10
ꢀ
+
I
I
20
B
ꢀ
0
I
B
0
+
I
B
ꢀ10
ꢀ20
ꢀ30
ꢀ40
2.0
1.±
1.0
0.±
ꢀ20
ꢀ40
ꢀ60
ꢀꢂ0
B
ꢀ
5
±0
TEMPERATURE (ꢁC)
100 12±
ꢀ10
ꢀ±
±
0
3
6
9
12
1±
1ꢂ
ꢀ±0 ꢀ2±
0
2±
7±
ꢀ1±
10
1±
0
SUPPLY 5OLTAGE (±5)
INPUT COMMON MODE 5OLTAGE (5)
14692 G09
14692 G07
14692 G0ꢂ
Output Voltage Swing
vs Supply Voltage
Output Voltage Swing
vs Load Current
Output Short-Circuit Current
vs Temperature
+
+
60
±±
±0
4±
40
3±
30
2±
20
1±
10
5
5
ꢀ0.±
ꢀ1.0
ꢀ1.±
ꢀ2.0
ꢀ2.±
R
= 10k
L
5
= ±1±5
S
5
5
= ±1±5
= ±0.25
ꢂ±ꢁC
S
IN
2±ꢁC
ꢀ1
ꢀ2
ꢀ3
ꢀ4
4
R
L
= 2k
ꢀ40ꢁC
SOURCE
SINK
2.±
2.0
1.±
1.0
3
ꢀ40ꢁC
ꢂ±ꢁC
2
R
= 2k
L
2±ꢁC
1
R
= 10k
L
T
A
= 2±ꢁC
ꢀ
ꢀ
5
5
0.±
ꢀ±0
0
2±
±0
7± 100 12±
ꢀ2±
0
±
10
1±
20
ꢀ20
0
10 1±
ꢀ1± ꢀ10 ꢀ±
±
20
SUPPLY 5OLTAGE (±5)
TEMPERATURE (ꢁC)
OUTPUT CURRENT (mA)
14692 G12
14692 G10
14692 G11
Open-Loop Gain
vs Resistive Load
Open-Loop Gain
vs Temperature
Warm-Up Drift vs Time
160
1±0
140
13±
130
12±
120
11±
110
10
0
R
= 2k
T
= 2±ꢁC
L
A
5
S
= ±±5
S
S0-ꢂ ±±5
ꢀ10
ꢀ20
ꢀ30
ꢀ40
ꢀ±0
ꢀ60
ꢀ70
ꢀꢂ0
5
5
= ±±5
S
S
140
130
120
110
100
5
= ±1±5
= ±1±5
S0-ꢂ ±1±5
90
±0
TEMPERATURE (ꢁC)
100 12±
ꢀ±0 ꢀ2±
0
2±
7±
10
100
1k
10k
0
20
40
60
ꢂ0 100 120 140
LOAD RESISTANCE (ꢃ)
TIME AFTER POWER UP (s)
14692 G14
14692 G13
14692 G1±
14692f
7
LT1469-2
TYPICAL PERFORMANCE CHARACTERISTICS
Open-Loop Gain and Phase
Gain vs Frequency, AV = –1
Output Impedance vs Frequency
vs Frequency
70
60
±0
40
30
20
10
0
100
ꢂ0
100
10
6
±
T
= 2±ꢁC
= ꢀ1
G
= 6.ꢂpF
= ±00ꢃ
5
T
= ±1±5
= 2±ꢁC
A
5
F
F
L
S
A
C
= 100pF
= 47pF
A
L
R
= R = 2k
4
PHASE
C
C
C
60
L
3
R
A
= 100
5
2
40
= 22pF
L
1
GAIN
A
= 10
1
5
20
0
0.1
0
NO C
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ±
L
A
= ꢀ1
1M
T
= 2±ꢁC
= ꢀ1
5
A
5
F
F
L
ꢀ20
ꢀ40
ꢀ60
A
0.01
R
= R = ±.1k
G
C
= ±pF
= 2k
R
ꢀ10
0.001
100k
1M
10M
100M
10k
100k
1M
FREQUENCY (Hz)
10M
100M
10k
100k
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
14692 G17
14692 G16
14692 G1ꢂ
Undistorted Output Swing
vs Frequency, VS = 15V
Undistorted Output Swing
vs Frequency, VS = 5V
Settling Time vs Output Step,
AV = –1
30
2±
20
1±
10
±
10
ꢂ
10
9
ꢂ
7
6
±
4
3
2
1
0
5
= ±1±5
= 2±ꢁC
S
A
F
1±0μ5
T
R
R
= R = 2.±k
G
6
A
5
= ꢀ1
= 2.±k
L
0.01%
INTO DIODES
C
4
0.1%
= ꢂpF
F
2
A
= ꢀ1
5
0
ꢀ2
ꢀ4
ꢀ6
ꢀꢂ
ꢀ10
0.1%
5
T
= ±1±5
= 2±ꢁC
= 2k
5
T
= ±±5
= 2±ꢁC
= 2k
S
S
A
A
1±0μ5
R
R
L
L
0.01%
THD<1%
THD<1%
0
1
10
100
1000
0
100 200 300 400 ±00 600 700 ꢂ00 9001000
1
10
100
1000 2000
FREQUENCY (kHz)
SETTLING TIME (ns)
FREQUENCY (kHz)
14692 G19
14692 G21
14692 G20
Settling Time vs Output Step,
AV = 2
Small-Signal Transient, AV = –1
Large-Signal Transient, AV = –1
10
ꢂ
5
= ±1±5
5
A
= ±1±5
= ꢀ1
S
S
5
F
105
R
= R = 2k
G
0.01%
6
C
= 22pF
L
4
2
20m5/DI5
25/DI5
05
0
ꢀ2
ꢀ4
ꢀ6
ꢀꢂ
ꢀ10
5
= ±1±5
= 2±ꢁC
S
A
T
0.01%
R
= R = 1k
G
F
R
L
= 2.±k INTO DIODES
200ns/DI5
±0ns/DI5
C
= 22pF
F
14692 G24
14692 G23
R
= ±11Ω//30pF
S
0
100 200 300 400 ±00 600 700 ꢂ00 9001000
SETTLING TIME (ns)
14692 G22
14692f
8
LT1469-2
APPLICATIONS INFORMATION
Gain of 2 Stable
input and a 1±5 supply will generate 10nA—equal to the
maximum I ꢀ specification).
B
The LT1469-2 is a decompensated version of the LT1469.
The DC precision performance is identical, but the internal
compensation capacitors have been reduced to a point
where the op amp needs a gain of 2 or greater in order
to be stable.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs: for inverting configurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below).
In general, for applications where the gain around the op
amp is ≥ 2, the decompensated version should be used,
because it will give the best AC performance. In applica-
tions where the gain is <2, the unity-gain stable version
should be used.
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
the amplifier. Air currents over device leads should be
minimized, package leads should be short and the two
input leads should be as close together as possible and
maintained at the same temperature.
The appropriate way to define the ‘gain’ is as the inverse
of the feedback ratio from output to differential input,
including all relevant parasitics. Moreover, as with all
feedback loops, the stability of the loop depends on the
value of that feedback ratio at frequencies where the total
loop-gain would cross unity. Therefore, it is possible to
have circuits in which the gain at DC is lower than the gain
at high frequency, and these circuits can be stable even
with a non unity-gain stable op amp. An example is many
current-output DAC buffer applications.
The parallel combination of the feedback resistor and gain
settingresistorontheinvertinginputcancombinewiththe
input capacitance to form a pole which can cause peak-
ing or even oscillations. A feedback capacitor of value C
F
= R • C /R may be used to cancel the input pole and
G
IN
F
Layout and Passive Components
optimize dynamic performance. For applications where
the DC noise gain is one, and a large feedback resistor is
The LT1469 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01μF to 0.1μF) in parallel with low ESR bypass capaci-
tors(1μFto10μFtantalum). ForbestDCperformance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (e.g., 1.±GΩ of leakage between an
used, C should be less than or equal to one half of C .
F
IN
An example would be a DAC I-to-5 converter as shown on
the front page of the data sheet where the DAC can have
many tens of picofarads of output capacitance.
+
5
C
F
R1
100ꢃ
R1
100ꢃ
Q1
Q2
+IN
ꢀIN
R
F
R
G
ꢀ
C
IN
1/2 LT1469-2
5
OUT
5
IN
+
14692 F02
ꢀ
5
14692 F01
Figure 1. Nulling Input Capacitance
Figure 2. Input Stage Protection
14692f
9
LT1469-2
APPLICATIONS INFORMATION
Input Considerations
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of
the input devices. If large differential input voltages are
anticipated, limit the input current to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external resis-
tor to less than 10mA.
The LT1469 inputs can be driven to the negative supply
and to within 0.±5 of the positive supply without phase
reversal. As the input moves closer than 0.±5 to the posi-
tive supply, the output reverses phase.
Total Input Noise
TheLT1469employsbiascurrentcancellationattheinputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-5 converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greaterthaneitherinputcurrent,theuseofbalancedsource
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
ThetotalinputnoiseoftheLT1469isoptimizedforasource
resistance between 1k and 20k. Within this range, the
total input noise is dominated by the noise of the source
resistance itself. When the source resistance is below
1k, voltage noise of the amplifier dominates. When the
source resistance is above 20k, the input noise current is
the dominant contributor.
SIMPLIFIED SCHEMATIC
+
5
I1
I2
I±
Q10
Qꢂ
Q9
OUT
+IN
Q1
Q2
ꢀIN Q±
Q3
Q6
Q7
Q11
Q4
C
BIAS
I3
I4
I6
ꢀ
5
14692 SS
14692f
10
LT1469-2
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(Reference LTC DWG # 0±-0ꢂ-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
2
3
4
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
DF Package
12-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 0±-0ꢂ-1773 Rev Ø)
4.00 ± 0.10
(4 SIDES)
2.50 REF
2.50 REF
7
12
0.70 ±0.05
0.40 ± 0.10
3.38 ±0.10
3.38 ±0.05
2.65 ± 0.05
4.50 ± 0.05
3.10 ± 0.05
2.65 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45°
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
CHAMFER
(DF12) DFN 0806 REV
Ø
6
1
0.25 ± 0.05
0.50 BSC
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.75 ± 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
14692f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1469-2
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1167
Precision Instrumentation Amplifier
Single 90MHz, 225/μs, 16-Bit Accurate Op Amp
Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity
LT146ꢂ
7±μ5 Max 5 , Single 5ersion of LT1469
OS
LTC1±9±/LTC1±96 16-Bit Serial Multiplying I
DAC
±1LSB Max INL/DNL, Low Glitch, DACꢂ043 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
±2.±5 Input, SINAD = 90dB, THD = ꢀ100dB
OUT
LTC1±97
LTC1604
LTC160±
16-Bit Parallel Multiplying I
DAC
OUT
16-Bit, 333ksps Sampling ADC
Single ±5, 16-Bit, 100ksps Sampling ADC
Low Power, ±105 Inputs, Parallel/Byte Interface
14692f
LT 0808 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 9±03±-7417
12
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(40ꢂ) 432-1900 FAX: (40ꢂ) 434-0±07 www.linear.com
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