LT1712 [Linear]
Single/Dual 4.5ns, 3V/5V, Rail-to-Rail Comparators; 单/双4.5ns ， 3V / 5V ，轨到轨比较器
| 型号： | LT1712 |
| 厂家： | 
Linear |
| 描述： | Single/Dual 4.5ns, 3V/5V, Rail-to-Rail Comparators |
| 文件： | 总12页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1711/LT1712
Single/Dual 4.5ns, 3V/5V/±5V,
Rail-to-Rail Comparators
U
FEATURES
DESCRIPTIO
■
Ultrafast: 4.5ns at 20mV Overdrive
The LT®1711/LT1712 are UltraFastTM 4.5ns comparators
featuringrail-to-railinputs,rail-to-railcomplementaryout-
puts and an output latch. Optimized for 3V and 5V power
supplies, they operate over a single supply voltage range
from 2.4V to 12V or from ±2.4V to ±6V dual supplies.
5.5ns at 5mV Overdrive
■
Rail-to-Rail Inputs
■
Rail-to-Rail Complementary Outputs (TTL/CMOS
Compatible)
■
Specified at 2.7V, 5V and ±5V Supplies
The LT1711/LT1712 are designed for ease of use in a
variety of systems. In addition to wide supply voltage
flexibility, rail-to-rail input common mode range extends
100mV beyond both supply rails, and the outputs are
protected against phase reversal for inputs extending
furtherbeyondtherails. Also, therail-to-railinputsmaybe
taken to opposite rails with no significant increase in input
current. The rail-to-rail matched complementary outputs
interface directly to TTL or CMOS logic and can sink 10mA
towithin0.5VofGNDorsource10mAtowithin0.7VofV+.
■
Output Latch
■
Inputs Can Exceed Supplies Without Phase Reversal
■
LT1711: 8-Lead MSOP Package
LT1712: 16-Lead Narrow SSOP Package
■
U
APPLICATIO S
■
High Speed Automatic Test Equipment
■
Current Sense for Switching Regulators
■
Crystal Oscillator Circuits
■
High Speed Sampling Circuits
The LT1711/LT1712 have internal TTL/CMOS compatible
latches for retaining data at the outputs. Each latch holds
data as long as the latch pin is held high. Latch pin
hysteresis provides protection against slow moving or
noisy latch signals. The LT1711 is available in the 8-pin
MSOP package. The LT1712 is available in the 16-pin
narrow SSOP package.
■
High Speed A/D Converters
■
Pulse Width Modulators
Window Comparators
■
■
Extended Range V/F Converters
Fast Pulse Height/Width Discriminators
Line Receivers
High Speed Triggers
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator
5V
LT1711/LT1712 Propagation Delay
vs Input Overdrive
47k* LT1004-2.5
1N4148
3.9k*
V
IN
0V TO 5V
6.0
T
= 25°C
= 5V
1M
A
1M*
1k*
+
V
V
V
–
5.5
= 0V
MV-209
VARACTOR
DIODE
5V
= 100mV
STEP
1M
0.047µF
C SELECT
5.0
4.5
4.0
3.5
3.0
1M
2k
+
(CHOOSE FOR CORRECT
PLL LOOP RESPONSE)
t
PD
100pF
–
390Ω
Y1** 15pF 100pF
t
PD
+
LT1711
FREQUENCY
OUTPUT
–
171112 TA01
2k
0
10
20
40
50
60
30
INPUT OVERDRIVE (mV)
200pF
* 1% FILM RESISTOR
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
171112 TA02
1
LT1711/LT1712
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Supply Voltage
Output Current (Continuous) .............................. ±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 2)... –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
V+ to V–............................................................ 12.6V
V+ to GND ........................................................ 12.6V
V– to GND .............................................–10V to 0.3V
Differential Input Voltage ................................... ±12.6V
Latch Pin Voltage...................................................... 7V
Input and Latch Current..................................... ±10mA
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
LATCH
ENABLE A
GND
NUMBER
–IN A
+IN A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
LT1711CMS8
LT1711IMS8
LT1712CGN
LT1712IGN
–
V
Q A
Q A
Q B
Q B
+
V
1
2
3
4
8 Q
7 Q
6 GND
5 LATCH
ENABLE
+
V
+IN
–IN
+
V
–
V
–
V
MS8 PACKAGE
MS8 PART MARKING
GN PART MARKING
+IN B
–IN B
GND
LATCH
ENABLE B
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 250°C/ W (NOTE 12)
LTTC
LTTD
1712
1712I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 120°C/ W (NOTE 12)
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
V
V
Positive Supply Voltage Range
Input Offset Voltage (Note 4)
●
●
2.4
7
V
+
+
R = 50Ω, V = V /2
0.5
5.0
6.0
mV
mV
mV
mV
OS
S
CM
R = 50Ω, V = V /2
S
CM
R = 50Ω, V = 0V
0.7
1
S
CM
+
R = 50Ω, V = V
S
CM
∆V /∆T Input Offset Voltage Drift
●
●
10
µV/°C
OS
I
Input Offset Current
0.2
3
6
µA
µA
OS
I
Input Bias Current (Note 5)
–18
–35
–5
5
µA
µA
B
●
●
10
+
V
Input Voltage Range (Note 9)
Common Mode Rejection Ratio
–0.1
V + 0.1
V
CM
+
+
+
+
CMRR
V = 5V, 0V ≤ V ≤ 5V
56
53
54
50
65
65
dB
dB
dB
dB
CM
V = 5V, 0V ≤ V ≤ 5V
●
●
CM
CM
V = 2.7V, 0V ≤ V ≤ 2.7V
V = 2.7V, 0V ≤ V ≤ 2.7V
CM
+
+
PSRR
Positive Power Supply Rejection Ratio
2.4V ≤ V ≤ 7V, V = 0V
58
56
75
dB
dB
CM
●
2
LT1711/LT1712
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
–
+
PSRR
Negative Power Supply Rejection Ratio
–7V ≤ V ≤ 0V, V = 5V, V = 5V
60
58
80
dB
dB
CM
●
A
V
Small-Signal Voltage Gain (Note 10)
Output Voltage Swing HIGH
1
15
V/mV
V
+
+
+
+
I
I
= 1mA, V = 50mV
OVERDRIVE
●
●
V – 0.5 V – 0.2
V – 0.7 V – 0.4
V
V
OH
OUT
OUT
= 10mA, V
= 50mV
OVERDRIVE
V
Output Voltage Swing LOW
I
I
= –1mA, V
= 50mV
●
●
0.20
0.35
0.4
0.5
V
V
OL
OUT
OUT
+
OVERDRIVE
= –10mA, V
= 50mV
OVERDRIVE
+
I
I
Positive Supply Current (Per Comparator)
Negative Supply Current (Per Comparator)
V = 5V, V
= 1V
15
19
26
mA
mA
OVERDRIVE
●
–
+
V = 5V, V
= 1V
8
10
13
mA
mA
OVERDRIVE
●
●
●
●
V
V
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Pin Current
2.4
V
V
IH
IL
0.8
15
+
I
t
V
= V
µA
IL
PD
LATCH
Propagation Delay (Note 6)
∆V = 100mV, V
= 20mV
= 20mV
= 5mV
4.5
6.0
8.5
ns
ns
ns
IN
IN
IN
OVERDRIVE
OVERDRIVE
OVERDRIVE
∆V = 100mV, V
●
∆V = 100mV, V
5.5
0.5
2
∆t
Differential Propagation Delay (Note 6)
Output Rise Time
∆V = 100mV, V
= 20mV
1.5
ns
ns
PD
IN
OVERDRIVE
t
t
t
t
t
t
f
t
10% to 90%
90% to 10%
r
f
Output Fall Time
2
ns
Latch Propagation Delay (Note 7)
Latch Setup Time (Note 7)
Latch Hold Time (Note 7)
5
ns
LPD
SU
1
ns
0
ns
H
Minimum Latch Disable Pulse Width (Note 7)
Maximum Toggle Frequency
Output Timing Jitter
5
ns
DPW
MAX
JITTER
V
V
= 100mV Sine Wave
100
11
MHz
IN
P-P
= 630mV (0dBm) Sine Wave, f = 30MHz
ps
RMS
IN
P-P
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
2.4
–7
TYP
MAX
UNITS
+
V
V
V
Positive Supply Voltage Range
●
●
7
0
V
V
–
Negative Supply Voltage Range (Note 3)
Input Offset Voltage (Note 4)
R = 50Ω, V = 0V
0.5
5.0
6.0
mV
mV
mV
mV
OS
S
CM
R = 50Ω, V = 0V
●
S
CM
R = 50Ω, V = 5V
0.7
1
S
CM
R = 50Ω, V = –5V
S
CM
∆V /∆T Input Offset Voltage Drift
OS
10
µV/°C
I
Input Offset Current
0.2
3
6
µA
µA
OS
●
I
Input Bias Current (Note 5)
–18
–35
–5
5
µA
µA
B
●
●
10
V
Input Voltage Range
–5.1
5.1
V
CM
CMRR
Common Mode Rejection Ratio
–5V ≤ V ≤ 5V
61
58
75
85
80
dB
dB
CM
●
●
●
+
+
PSRR
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
2.4V ≤ V ≤ 7V, V = –5V
58
56
dB
dB
CM
–
–
PSRR
–7V ≤ V ≤ 0V, V = 5V
60
58
dB
dB
CM
3
LT1711/LT1712
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
V
Small-Signal Voltage Gain
1
15
V/mV
V
Output Voltage Swing HIGH (Note 8)
I
I
= 1mA, V = 50mV
OVERDRIVE
●
●
4.5
4.3
4.8
4.6
V
V
OH
OUT
OUT
= 10mA, V
= 50mV
OVERDRIVE
V
Output Voltage Swing LOW (Note 8)
I
I
= –1mA, V
= 50mV
OVERDRIVE
●
●
0.20
0.30
0.4
0.5
V
V
OL
OUT
OUT
OVERDRIVE
= –10mA, V
= 50mV
+
I
I
Positive Supply Current (Per Comparator)
Negative Supply Current (Per Comparator)
V
= 1V
17
22
30
mA
mA
OVERDRIVE
●
–
V
= 1V
9
12
15
mA
mA
OVERDRIVE
●
●
●
●
V
V
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Pin Current
2.4
V
V
IH
IL
0.8
15
+
I
t
V
= V
µA
IL
PD
LATCH
Propagation Delay (Notes 6, 11)
∆V = 100mV, V
= 20mV
= 20mV
= 5mV
4.5
6.0
8.5
ns
ns
ns
IN
IN
IN
OVERDRIVE
OVERDRIVE
OVERDRIVE
∆V = 100mV, V
●
∆V = 100mV, V
5.5
0.5
2
∆t
Differential Propagation Delay (Notes 6, 11)
Output Rise Time
∆V = 100mV, V
= 20mV
1.5
ns
ns
PD
IN
OVERDRIVE
t
t
t
t
t
t
f
t
10% to 90%
90% to 10%
r
f
Output Fall Time
2
ns
Latch Propagation Delay (Note 7)
Latch Setup Time (Note 7)
Latch Hold Time (Note 7)
5
ns
LPD
SU
1
ns
0
ns
H
Minimum Latch Disable Pulse Width (Note 7)
Maximum Toggle Frequency
Output Timing Jitter
5
ns
DPW
MAX
JITTER
V
V
= 100mV Sine Wave
100
11
MHz
IN
P-P
= 630mV (0dBm) Sine Wave, f = 30MHz
ps
RMS
IN
P-P
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t ) is the interval after the latch is asserted in
H
which the input signal must remain stable. Latch disable pulse width
Note 2: The LT1711C/LT1712C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1711I/LT1712I are
guaranteed to meet specified performance from –40°C to 85°C.
Note 3: The negative supply should not be greater than the ground pin
voltage and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
(t
) is the width of the negative pulse on the latch enable pin that
DPW
latches in new data on the data inputs.
Note 8: Output voltage swings are characterized and tested at V = 5V and
V = 0V. They are guaranteed by design and correlation to meet these
specifications at V = –5V.
+
–
–
Note 9: The input voltage range is tested under the more demanding
+
–
conditions of V = 5V and V = –5V. The LT1711/LT1712 are guaranteed
–
by design and correlation to meet these specifications at V = 0V.
Note 10: The LT1711/LT1712 voltage gain is tested at V = 5V and
V = –5V only. Voltage gain at single supply V = 5V and V = 2.7V is
Note 4: Input offset voltage (V ) is measured with the LT1711/LT1712 in
OS
+
a configuration that adds external hysteresis. It is defined as the average of
the two hysteresis trip points.
–
+
+
guaranteed by design and correlation.
Note 5: Input bias current (I ) is defined as the average of the two input
currents.
B
+
Note 11: The LT1711/LT1712 t is tested at V = 5V and 2.7V with
PD
–
+
–
V = 0V. Propagation delay at V = 5V, V = –5V is guaranteed by design
Note 6: Propagation delay (t ) is measured with the overdrive added to
PD
and correlation.
the actual V . Differential propagation delay is defined as:
OS
+
–
∆t = t
– t . Load capacitance is 10pF. Due to test system
Note 12: Care must be taken to make sure that the LT1711/LT1712 do not
PD
PD
PD
requirements, the LT1711/LT1712 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
exceed T
temperature range. T
current increases with switching frequency (see Typical Performance
Characteristics).
when operating with ±5V supplies over the industrial
JMAX
is not exceeded for DC inputs, but supply
JMAX
Note 7: Latch propagation delay (t ) is the delay time for the output to
LPD
respond when the latch pin is deasserted. Latch setup time (t ) is the
SU
4
LT1711/LT1712
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage vs
Temperature
Propagation Delay
Propagation Delay vs
Temperature
vs Load Capacitance
2.5
2.0
10
9
8
7
6
5
4
3
2
1
0
+
–
V
V
= 5V
= 0V
T
= 25°C
= 5V
A
+
V
V
V
V
V
–
–
t
PD
= 0V
+
1.5
t
PD
= 2.5V
= 20mV
= 100mV
CM
OD
8
1.0
V
= 5V
CM
+
STEP
t
PD
0.5
7
–
t
PD
0
V
= 2.5V
CM
6
V
CM
= 0V
–0.5
–1.0
–1.5
–2.0
–2.5
+
–
V
V
V
V
V
C
= 5V
= 0V
5
= 2.5V
CM
OD
STEP
LOAD
= 20mV
= 100mV
= 10pF
4
3
–50
0
25
50
75 100 125
80
LOAD CAPACITANCE (pF)
120
–25
0
20
40
60
100
–25
0
25
50
75
125
–50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
171112 G01
171112 G02
171112 G03
Propagation Delay
vs Input Common Mode Voltage
Propagation Delay
Positive Supply Current
vs Positive Supply Voltage
vs Positive Supply Voltage
6.0
5.5
5.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
25
20
15
10
5
–
T
= 25°C
= 5V
T
= 25°C
A
A
V = 0V
–
+
–
V
= –5V
V
V
V
V
C
V
V
V
V
C
= 0V
–
= 0V
= 2.5V
= 20mV
CM
OD
= 20mV
OD
+
t
PD
= 100mV
= 10pF
= 100mV
= 10pF
STEP
LOAD
STEP
LOAD
+
t
PD
4.5
4.0
3.5
3.0
–
t
PD
–
t
PD
+
+
+
I
I
I
AT –55°C
AT 25°C
AT 85°C
∆V = 100mV
IN
OUT
I
= 0mA
0
2
6
8
10
0
1
3
4
5
6
0
4
–1
2
0
4
6
8
10
12
2
POSITIVE SUPPLY VOLTAGE (V)
INPUT COMMON MODE (V)
POSITIVE SUPPLY VOLTAGE (V)
171112 G04
171112 G05
171112 G06
Positive Supply Current
vs Switching Frequency
Negative Supply Current
vs Negative Supply Voltage
Input Bias Current
vs Input Common Mode Voltage
40
30
20
10
0
14
12
10
8
10
4
+
+
–
T
= 25°C
= 5V
V = 5V
V
V
= 5V
= 0V
IN
A
+
V
V
C
∆V = 100mV
OUT
IN
–
= 0V
I
= 0mA
∆V = 0mV
= 10pF
LOAD
–2
6
–8
–14
–20
4
–
–
–
I
I
I
AT –55°C
AT 25°C
AT 85°C
I
I
I
AT –55°C
B
B
B
2
AT 25°C
AT 125°C
0
0
10
20
30
40
50
60
–4
–6
–7
0
–1
–2
–3
–5
3
–1
0
1
2
4
5
6
SWITCHING FREQUENCY (MHz)
NEGATIVE SUPPLY VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
171112 G07
171112 G08
171112 G09
5
LT1711/LT1712
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Input Bias Current vs
Temperature
Output High Voltage
vs Source Current
Output Low Voltage
vs Sink Current
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
+
–
+
–
+
–
V
V
= 5V
= 0V
IN
V
V
= 5V
= 0V
V
V
V
= 5V
= 0V
∆V = 100mV
∆V = 100mV
IN
= 2.5V
CM
V
V
V
AT –55°C
AT 25°C
AT 125°C
V
OL
V
OL
V
OL
AT –55°C
AT 25°C
AT 125°C
OH
OH
OH
0.1
1.0
10
100
0.1
1.0
10
100
–25
0
25
50
75
125
–50
100
SOURCE CURRENT (mA)
SINK CURRENT (mA)
TEMPERATURE (°C)
171112 G11
171112 G12
171112 G10
Output Timing Jitter
vs Switching Frequency
Output Rising Edge, 5V Supply
Output Falling Edge, 5V Supply
100
90
80
70
60
50
40
30
30
10
0
T
= 25°C
= 5V
A
+
V
V
V
V
VIN
VIN
–
= 0V
= 2.5V
CM
= 630mV
IN
P-P
(0dBm) SINE WAVE
Q
Q
171112 G14
171112 G15
0
20
40
60
80
100
FREQUENCY (MHz)
171112 G13
U
U
U
PI FU CTIO S
LT1711
V+ (Pins 1): Positive Supply Voltage, Usually 5V.
+IN (Pin 2): Noninverting Input.
GND (Pin 6): Ground Supply Voltage, Usually 0V.
Q (Pin 7): Noninverting Output.
Q (Pin 8): Inverting Output.
–IN (Pin 3): Inverting Input.
V– (Pins 4): Negative Supply Voltage, Usually 0V or –5V.
LATCH ENABLE (Pin 5): Latch Enable Input. With a logic
high, the output is latched.
6
LT1711/LT1712
U
U
U
PI FU CTIO S
LT1712
–IN A (Pin 1): Inverting Input of A Channel Comparator.
Q B (Pin 11): Noninverting Output of B Channel
Comparator.
+IN A (Pin 2): Noninverting Input of A Channel
Comparator.
Q B (Pin 12): Inverting Output of B Channel
Comparator.
Q A (Pin 13): Inverting Output of A Channel
Comparator.
Q A (Pin 14): Noninverting Output of A Channel
Comparator.
GND (Pin 15): Ground Supply Voltage of A Channel
Comparator, Usually 0V
V– (Pins3,6):NegativeSupplyVoltage,Usually–5V.Pins
3 and 6 should be connected together externally.
V+ (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins
4 and 5 should be connected together externally.
+IN B (Pin 7): Noninverting Input of B Channel
Comparator.
–IN B (Pin 8): Inverting Input of B Channel Comparator.
LATCH ENABLE A (Pin 16): Latch Enable Input of A
Channel Comparator. With a logic high, the A output is
latched.
LATCHENABLEB(Pin9):LatchEnableInputofBChannel
Comparator. With a logic high, the B output is latched.
GND (Pin 10): Ground Supply Voltage of B Channel
Comparator, Usually 0V.
W U U
U
APPLICATIO S I FOR ATIO
Common Mode Considerations
differential input stage, the LT1711/LT1712 bias current
flows into or out of the device depending upon the com-
mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive,andthesecurrentsflowintothedevice.Forinputs
far enough away from the supply rails, the input bias
currentwillbesomecombinationoftheNPNandPNPbias
currents. As the differential input voltage increases, the
inputcurrentofeachpairwillincreaseforoneoftheinputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.
The LT1711/LT1712 are specified for a common mode
range of –5.1V to 5.1V on a ±5V supply, or a common
moderangeof–0.1Vto5.1Vonasingle5Vsupply.Amore
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply
voltage. The criteria for common mode limit is that the
output still responds correctly to a small differential input
signal.
When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.
Latch Pin Dynamics
The internal latches of the LT1711/LT1712 comparators
retain the input data (output latched) when their respec-
tive latch pin goes high. The latch pin will float to a low
state when disconnected, but it is better to ground the
Input Bias Current
Input bias current is measured with the outputs held at
2.5V with a 5V supply voltage. As with any rail-to-rail
7
LT1711/LT1712
W U U
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APPLICATIO S I FOR ATIO
latch when a flow-through condition is desired. The latch
pin is designed to be driven with either a TTL or CMOS
output.Ithasbuilt-inhysteresisofapproximately100mV,
so that slow moving or noisy input signals do not impact
latch performance.
termination impedances (typically 100Ω to 400Ω) to
eliminate any reflections that may occur. Also keep source
impedances as low as possible, preferably much less than
1kΩ.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
this isolation as shown in Figure 1, a typical topside layout
of the LT1712 on a multilayer PC board. Shown is the
topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1712 and its adjacent X7R
0805 bypass capacitors. The V+, V– and GND traces all
shield the inputs from the outputs. Although the two V–
pins are connected internally, they should be shorted
together externally as well in order for both to function as
shields. The same is true for the twoV+ pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
For the LT1712, if only one of the comparators is being
usedatagiventime,itisbesttolatchthesecondcompara-
tor to avoid any possibility of interactions between the two
comparators in the same package.
High Speed Design Techniques
The extremely fast speed of the LT1711/LT1712 necessi-
tates careful attention to proper PC board layout and
circuit design in order to prevent oscillations, as with
most high speed comparators. The most common prob-
lem involves power supply bypassing which is necessary
tomaintainlowsupplyimpedance. Resistanceandinduc-
tance in supply wires and PC traces can quickly build up
to unacceptable levels, thereby allowing the supply volt-
ages to move as the supply current changes. This move-
ment of the supply voltages will often result in improper
operation.Inaddition,adjacentdevicesconnectedthrough
anunbypassedsupplycaninteractwitheachotherthrough
the finite supply impedances.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1711/LT1712
supply pins. A good high frequency capacitor, such as a
1000pF ceramic, is recommended in parallel with larger
capacitors, such as a 0.1µF ceramic and a 4.7µF tantalum
in parallel. These bypass capacitors should be soldered to
the output ground plane such that the return currents do
not pass through the ground plane under the input cir-
cuitry. The common tie point for these two ground planes
should be at the board ground connection. Such star-
grounding and ground plane separation is extremely im-
portantfortheproperoperationofultrahighspeedcircuits.
171112 F01
Figure 1. Typical LT1712 Topside Metal
for Multilayer PCB Layout
Hysteresis
Another important technique to avoid oscillations is to
provide positive feedback, also known as hysteresis,
from the output to the input. Increased levels of hyster-
esis,however,reducethesensitivityofthedevicetoinput
voltagelevels, sotheamountofpositivefeedbackshould
be tailored to particular system requirements. The
LT1711/LT1712 are completely flexible regarding the
applicationofhysteresis, duetorail-to-railinputsandthe
complementary outputs. Specifically, feedback resistors
can be connected from one of the outputs to its corre-
spondinginput withoutregardtocommonmodeconsid-
erations. Figure 2 shows several configurations.
Poor trace routes and high source impedances are also
commonsourcesofproblems.Keeptracelengthsasshort
as possible and avoid running any output trace adjacent
to an input trace to prevent unnecessary coupling. If
output traces are longer than a few inches, provide proper
8
LT1711/LT1712
W U U
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APPLICATIO S I FOR ATIO
100k
50k
Q
V
+
IN
Q
Q
Q
50Ω
50Ω
50Ω
+
–
LT1711
V
V
+
–
V
+
IN
IN
IN
LT1711
LT1711
–
V
REF
–
Q
50k
+
–
V
V
V
= 5V
= –5V
= 5mV
(ALL 3 CASES)
Q
50Ω
HYST
100k
171112 F02
Figure 2. Various Configurations for Introducing Hysteresis
U
TYPICAL APPLICATIO S
Simultaneous Full Duplex 75Mbaud Interface
with Only Two Wires
with a full ±3V (one whole VS up or down) of ground
potential difference.
The circuit of Figure 3 shows a simple, fully bidirectional,
differential 2-wire interface that gives good results to
75Mbaud, using the LT1712. Eye diagrams under condi-
tions of unidirectional and bidirectional communication
are shown in Figures 4 and 5. Although not as pristine as
the unidirectional performance of Figure 4, the perfor-
mance under simultaneous bidirectional operation is still
excellent. Because the LT1712 input voltage range ex-
tends 100mV beyond both supply rails, the circuit works
The circuit works well with the resistor values shown, but
other sets of values can be used. The starting point is the
characteristic impedance, ZO, of the twisted-pair cable.
The input impedance of the resistive network should
match the characteristic impedance and is given by:
R1||(R2 +R3)
RIN = 2 •RO •
R + 2 • R1||(R2 +R3)
[
]
O
750k
14
750k
3V
3V
4
4
2
1
2
+
–
14
+
1/2
1/2
LT1712
RxD
RxD
LT1712
LE
16
LE
1
13
13
–
16
3
15
3
15
750k
750k
3V
3V
100k
11
100k
11
R1C
3V
R1A
R2A
R2C
3V
499Ω
499Ω
2.55k
2.55k
49.9Ω
49.9Ω
49.9Ω
49.9Ω
5
5
7
8
7
8
+
+
1/2
LT1712
LE
10
R
R
1/2
R3A
124Ω
R3C
124Ω
OA
OB
TxD
TxD
140Ω
140Ω
LT1712
LE
12
12
–
–
10
6
6-FEET
6
R1D
499Ω
TWISTED PAIR
R3B
124Ω
R1B
499Ω
R3D
124Ω
9
9
Z
≈ 120Ω
O
R2D
2.55k
DIODES: BAV99
R2B
2.55k
100k
×4
100k
171112 F03
Figure 3. 75Mbaud Full Duplex Interface on Two Wires
9
LT1711/LT1712
TYPICAL APPLICATIO S
U
171112 F05
171112 F04
Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent
Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open
This comes out to 120Ω for the values shown. The
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.
Thevenin equivalent source voltage is given by:
(R2 +R3 –R1)
VTH = VS •
(R2 +R3 +R1)
The LT1711 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuningbandwidth. Itshouldbepickedtocomplementloop
response in phase locking applications. Figure 6 is a plot
oftuninginputvoltageversusfrequencydeviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre-
quency exceeds ±240ppm for a 0V to 5V input.
RO
•
R + 2 • R1||(R2 +R3)
[
]
O
This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω ZO.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:
1 Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +
124Ω = 2.674k.
9
14.3217MHz
8
7
6
5
4
3
2
1
0
14.31818MHz
R3/R2 = 1/2 • 0.09761.
Having already designed R2 + R3 to be 2.653k (by allocat-
ing input impedance across RO, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and
123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.
14.3140MHz
1
0
4
5
2
3
INPUT VOLTAGE (V)
171112 F06
Voltage-Tunable Crystal Oscillator
Figure 6. Control Voltage vs Output Frequency for the
Front Page Application Circuit. Tuning Deviation from
Center Frequency Exceeds ±240ppm
The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre-
quency.Suchvoltage-controlledcrystaloscillators(VCXO)
10
LT1711/LT1712
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
2
3
4
0.043
(1.10)
MAX
0.034
(0.86)
REF
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.009 – 0.015
(0.22 – 0.38)
0.021 ± 0.006
(0.53 ± 0.015)
0.005 ± 0.002
(0.13 ± 0.05)
0.0256
(0.65)
BSC
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
11
LT1711/LT1712
U
TYPICAL APPLICATIO
1MHz Series Resonant Crystal Oscillator
with Square and Sinusoid Outputs
frequency glitch (middle trace of Figure 8). This glitch is
caused by the fast edge of the comparator output feeding
back through crystal capacitance. Amplitude stability of
the sine wave is maintained by the fact that the sine wave
is basically a filtered version of the square wave. Hence,
theusualamplitudecontrolloopsassociatedwithsinusoi-
daloscillatorsarenotnecessary.2 Thesinewaveisfiltered
and buffered by the fast, low noise LT1806 op amp. To
removetheglitch, theLT1806isconfiguredasabandpass
filter with a Q of 5 and unity-gain center frequency of
1MHz, with its output shown as the bottom trace of
Figure 8.Distortionwasmeasuredat–70dBcand–60dBc
on the second and third harmonics, respectively.
Figure 7 shows a classic 1MHz series resonant crystal
oscillator. At series resonance, the crystal is a low imped-
ance and the positive feedback connection is what brings
about oscillation at the series resonant frequency. The RC
feedback around the other path ensures that the circuit
does not find a stable DC operating point and refuse to
oscillate. The comparator output is a 1MHz square wave
(top trace of Figure 8) with jitter measured at better than
28psRMS on a 5V supply and 40psRMS on a 3V supply. At
Pin 2 of the comparator, on the other side of the crystal, is
a clean sine wave except for the presence of the small high
2 Amplitude will be a linear function of comparator output swing, which is supply dependent
and therefore adjustable. The important difference here is that any added amplitude
stabilization or control loop will not be faced with the classical task of avoiding regions of
nonoscillation versus clipping.
C4
100pF
R10
1k
R5
6.49k
C5
100pF
R6
162Ω
1MHz
AT-CUT
C3
100pF
R4
210Ω
R7
15.8k
V
S
3V/DIV
V
R1
1k
S
V
S
1
2
3
+
–
7
7
2
3
SQUARE
–
1V/DIV
1V/DIV
R2
1k
LT1711
LE
6
R9
2k
SINE
LT1806S8
8
1
4
V
S
+
5
6
4
C2
0.1µF
R8
2k
R3
1k
171112 F07
C1
0.1µF
171112 F08
200ns/DIV
Figure 8. Oscillator Waveforms with VS = 3V. Top is
Comparator Output. Middle is Xtal Feedback to Pin 2 at
LT1711 (Note the Glitches). Bottom is Buffered, Inverted
and Bandpass Filtered with a Q = 5 by LT1806
Figure 7. LT1711 Comparator is Configured as a Series
Resonant Xtal Oscillator. LT1806 Op Amp is Configured
in a Q = 5 Bandpass with fC = 1MHz
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1016
UltraFast Precision Comparator
Industry Standard 10ns Comparator
Single Supply Version of the LT1016
6mA Single Supply Comparator
LT1116
12ns Single Supply Ground Sensing Comparator
7ns, UltraFast Single Supply Comparator
60ns, Low Power, Single Supply Comparator
LT1394
LT1671
450µA Single Supply Comparator
7ns/5mA versions of the LT1711/LT1712
4mA Comparator with Rail-to-Rail Outputs and Level Shifting
Dual/Quad Version of the LT1719
LT1713/LT1714
LT1719
Single/Dual 7ns, Low Power, 3V/5V/±5V, R-R Comparator
4.5ns, Single Supply 3V/5V/±5V Comparator
LT1720/LT1721
Dual/Quad, 4.5ns, Single Supply Comparator
171112f LT/TP 0401 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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