LT1737CS#TRPBF [Linear]
LT1737 - High Power Isolated Flyback Controller; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LT1737CS#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT1737 - High Power Isolated Flyback Controller; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C 开关 光电二极管 |
| 文件： | 总28页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1737
High Power
Isolated Flyback Controller
U
FEATURES
DESCRIPTIO
■
Drives External Power MOSFET
The LT®1737 is a monolithic switching regulator control-
ler specifically designed for the isolated flyback topology.
It drives the gate of an external MOSFET and is generally
powered from a DC supply voltage. Output voltage feed-
back information may be supplied by a variety of methods
including a third transformer winding, the primary wind-
ing or even direct DC feedback (see Applications Informa-
tion). Its gate drive capability, coupled with a suitable
external MOSFET and other power path components, can
deliver load power up to tens of Watts.
■
Supply Voltage Range: 4.5V to 20V
■
Flyback Voltage Limited Only by
External Components
■
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
■
Switching Frequency from 50kHz to 250kHz
with External Capacitor
■
Moderate Accuracy Regulation Without User Trims
■
Regulation Maintained Well into Discontinuous Mode
■
External ISENSE Resistor
The LT1737 has a number of features not found on other
isolated flyback controller ICs. By utilizing current mode
switchingtechniques, itprovidesexcellentACandDCline
regulation. Its unique control circuitry can maintain regu-
lation well into discontinuous mode in most applications.
Optionalloadcompensationcircuitryallowsforimproved
load regulation. An optional undervoltage lockout pin
halts operation when the application input voltage is too
low. An optional external capacitor implements a soft-
start function.
■
Optional Load Compensation
■
Optional Undervoltage Lockout
■
Shutdown Feature Reduces IQ to 50µA Typ
■
Available in 16-Pin GN and SO Packages
U
APPLICATIO S
■
Isolated Flyback Switching Regulators
Medical Instruments
Instrumentation Power Supplies
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
12V-18V to Isolated 15V Converter
R2
35.7k
1%
V
IN
+
C1
22µF
T1
D1
COILTRONICS
CTX150-4
D2
MBRS1100
BAS16
Q1
2N3906
V
= 15V
= 300mA
OUT
OUT
I
•
+
240k
33k
R4
7.5k
C2
33µF
150µH
150µH
•
C3
0.1µF
UVLO
V
CC
M1
FB
GATE
IRFL014
LT1737
ENDLY MINENAB R
V
I
C
SENSE
R3
3.01k
1%
OSCAP
t
R
SGND
PGND
R1
0.27Ω
ON
OCMP
4.7k
CMPC
NOTE: SEE APPLICATIONS
75k
150k 100k
0.1µF
1nF
47pF
INFORMATION FOR ADDITIONAL
COMPONENT SPECIFICATIONS
1737 TA01
1737fa
1
LT1737
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC Supply Voltage................................................. 22V
UVLO Pin Voltage .................................................... VCC
ISENSE Pin Voltage .................................................... 2V
FB Pin Current ..................................................... ±2mA
Operating Junction
TOP VIEW
ORDER PART
NUMBER
PGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GATE
I
V
SENSE
CC
LT1737CGN
LT1737CS
LT1737IGN
LT1737IS
SFST
t
ON
R
ENDLY
MINENAB
SGND
OCMP
R
Temperature Range
CMPC
OSCAP
LT1737C............................................... 0°C to 100°C
LT1737I ............................................ –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
V
C
UVLO
GN PART MARKING
FB
3V
OUT
1737
1737I
GN PACKAGE
S PACKAGE
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 110°C/W (GN)
TJMAX = 125°C, θJA = 110°C/W (SO)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V
Minimum Input Voltage
●
4.1
4.5
V
CC(MIN)
I
Supply Current
Shutdown Current
V = Open
●
●
10
50
15
150
mA
µA
CC
C
V
= 0V, V = Open
UVLO
C
Feedback Amplifier
V
FB
Feedback Voltage
1.230
1.220
1.245
1.260
1.270
V
V
●
I
Feedback Pin Input Current
500
1000
50
nA
µmho
µA
FB
g
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
Reference Voltage/Current Line Regulation
Voltage Gain
∆l = ±10µA
●
●
400
30
1800
80
m
C
I
, I
SRC SNK
V
2.5
V
CL
4.75V ≤ V ≤ 18V
●
0.01
2000
40
0.05
50
%/V
V/V
µA
IN
V = 1V to 2V
C
Soft-Start Charging Current
V
V
= 0V
25
SFST
SFST
Soft-Start Discharge Current
= 1.5V, V
= 0V
0.8
1.5
mA
UVLO
Gate Output
V
GATE
Output High Level
Output Low Level
I
I
= 100mA
= 500mA
●
●
11.5
11.0
12.1
11.8
V
V
GATE
GATE
I
I
= 100mA
= 500mA
●
●
0.3
0.6
0.45
1.0
V
V
GATE
GATE
I
t
t
Output Sink Current in Shutdown, V
= 0V
V = 2V
GATE
●
1.2
2.5
30
30
mA
ns
GATE
UVLO
Rise Time
Fall Time
C = 1000pF
L
r
f
C = 1000pF
L
ns
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2
LT1737
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Amplifier
V
V
Control Pin Threshold
Switch Current Limit
Duty Cycle = Min
0.90
0.80
1.12
250
1.25
1.35
V
V
C
●
●
Duty Cycle ≤ 30%
Duty Cycle ≤ 30%
Duty Cycle = 80%
220
200
270
280
mV
mV
mV
ISENSE
220
∆V
ISENSE
/∆V
0.30
mV
C
Timing
f
Switching Frequency
C
= 100pF
90
80
100
115
125
kHz
kHz
OSCAP
●
C
Oscillator Capacitor Value
Minimum Switch On Time
Flyback Enable Delay Time
Minimum Flyback Enable Time
Timing Resistor Value
(Note 2)
33
200
pF
ns
ns
ns
kΩ
%
OSCAP
t
t
t
R
R
R
= 50k
tON
200
200
200
ON
= 50k
= 50k
ED
EN
ENDLY
MENAB
R
(Note 2)
24
85
240
t
Maximum Switch Duty Cycle
●
90
Load Compensation
Sense Offset Voltage
Current Gain Factor
UVLO Function
2
5
mV
mV
0.80
0.95
1.05
V
UVLO
UVLO Pin Lockout Threshold
UVLO Pin Shutdown Threshold
●
●
1.21
0.4
1.25
0.75
1.29
0.95
V
V
V
I
UVLO Pin Bias Current
V
V
= 1.2V
= 1.3V
–0.25
–4.50
+0.1
–3.5
+0.25
–2.50
µA
µA
UVLO
UVLO
UVLO
3V Output Function
V
REF
Reference Output Voltage
Output Impedance
Current Limit
I
= 1mA
●
●
2.8
8
3.0
10
15
3.2
V
Ω
LOAD
mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: Component value range guaranteed by design.
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LT1737
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage vs
Temperature
Shutdown Voltage (VUVLO) vs
Temperature
Shutdown ICC vs Temperature
125
100
75
50
25
0
4.3
4.2
4.1
4.0
3.9
3.8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50
0
25
50
75 100 125
–50 –25
0
25
75
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
1737 G02
1737 G01
1737 G03
UVLO Pin Input Current vs
Temperature
Oscillator Frequency vs
Temperature
Supply Current vs Temperature
1
13
12
11
10
9
115
110
105
100
95
V
= 1.2V
UVLO
0
–1
–2
–3
–4
–5
–6
V
= 1.3V
UVLO
90
8
85
50
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
1737 G05
1737 G06
1737 G04
VC Clamp Voltage, Switching
Threshold vs Temperature
VGATE vs ISINK
VCC-VGATE vs ISOURCE
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
CLAMP VOLTAGE
T
= 125°C
A
T
= 125°C
A
T
= 25°C
A
T
= 25°C
A
SWITCHING THRESHOLD
T
= –55°C
A
T
= –55°C
A
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1
10
100
1000
1
10
I
100
(mA)
1000
I
(mA)
SINK
SOURCE
1737 G07
1737 G09
1737 G08
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LT1737
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Enable Time vs
Temperature
Minimum Switch On Time vs
Temperature
Enable Delay Time vs
Temperature
275
250
225
200
175
150
125
275
250
225
200
175
150
125
275
250
225
200
175
150
125
R
= 50k
R
= 50k
TON
MINENAB
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
0
TEMPERATURE (°C)
100 125
–50 –25
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1737 G10
1737 G11
1737 G12
Feedback Amplifier Output Current
vs FB Pin Voltage
Feedback Amplifier
Transconductance vs Temperature
1600
1400
1200
1000
800
80
60
40
T
= –55°C
A
T
= 25°C
A
20
0
–20
–40
–60
–80
T
= 125°C
A
600
400
200
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1.10 1.15 1.20 1.25 1.30
FB PIN VOLTAGE (V)
1.40
1.05
1.35
1737 G14
1737 G13
Soft-Start Charging Current vs
Temperature
Soft-Start Sink Current vs
Temperature
2.5
2.0
1.5
1.0
0.5
0
60
50
40
30
20
10
0
V(SFST) = 0V
V(SFST) = 1.5V
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
1737 G16
1737 G15
1737fa
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LT1737
U
U
U
PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanosec-
onds. It should be connected directly to a good quality
ground plane.
3VOUT (Pin 9): Output pin for nominal 3V reference. This
facilitatesvarioususerapplications.Thisnodeisinternally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.
ISENSE (Pin2):Pintomeasureswitchcurrentwithexternal
sense resistor. The sense resistor should be of a nonin-
ductive construction as high speed performance is essen-
tial. Proper grounding technique is also required to avoid
distortion of the high speed current waveform. A preset
internal limit of nominally 250mV at this pin effects a
switch current limit.
UVLO (Pin 10): This is a dual function pin that implements
both undervoltage lockout and shutdown functions. Pull-
ing this pin to near ground effects shutdown and reduces
quiescent current to tens of microamperes.
Additionally, an external resistor divider between VIN and
ground may be connected to this pin to implement an
undervoltagelockoutfunction.Thebiascurrentonthispin
is a function of the state of the UVLO comparator; as the
threshold is exceeded, the bias current increases. This
creates a hysteresis band equal to the change in bias
current times the Thevenin impedance of the user’s resis-
tive divider. The user may thereby adjust the impedance of
theUVLOdividertoachieveadesireddegreeofhysteresis.
A 100pF capacitor to ground is recommended on this pin.
See Application Information for details.
SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function. See Applications Information for
details.
ROCMP (Pin 4): Input pin for optional external load com-
pensation resistor. Use of this pin allows nominal com-
pensation for nonzero output impedance in the power
transformer secondary circuit, including secondary wind-
ing impedance, output Schottky diode impedance and
outputcapacitorESR.Inlessdemandingapplications,this
resistor is not needed. See Applications Information for
more details.
SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FBpin, OSCAPcapacitorandtheVC compensationcapaci-
tor free of large ground currents.
RCMPC (Pin 5): Pin for external filter capacitor for optional
load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applica-
tions Information for further details.
MINENAB (Pin 12): Pin for external programming resistor
tosetminimumenabletime. SeeApplicationsInformation
for details.
OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Informa-
tion for details.
ENDLY (Pin 13): Pin for external programming resistor to
set enable delay time. See Applications Information for
details.
VC (pin 7): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a
capacitor between this node and ground.
tON (Pin 14): Pin for external programming resistor to set
switch minimum on time. See Applications Information
for details.
FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal band-
gap (VBG) reference, times the effective transformer turns
ratio is the primary determinant of the output voltage. The
Thevenin equivalent resistance of the feedback divider
should be roughly 3k. See Applications Information for
more details.
VCC (Pin 15): Supply voltage for the LT1737. Bypass this
pin to ground with 1µF or more.
GATE (Pin 16): This is the gate drive to the external power
MOSFET switch and has large dynamic currents flowing
through it. Keep the trace to the MOSFET as short as
possible to minimize electromagnetic radiation and volt-
age spikes. A series resistance of 5Ω or more may help to
dampen ringing in less than ideal layouts.
1737fa
6
LT1737
W
BLOCK DIAGRA
V
CC
3V
OUT
UVLO
BIAS
3V REG
(INTERNAL)
t
MINENAB ENDLY
ON
OSCAP
GATE
MOSFET
DRIVER
OSC
LOGIC
PGND
I
SENSE
COMP
I
AMP
SGND
FB
LOAD
COMPENSATION
FDBK
SOFT-START
SFST
1737 BD
V
R
R
CMPC
C
OCMP
1737fa
7
LT1737
W U
W
TI I G DIAGRA
V
SW
VOLTAGE
COLLAPSE
DETECT
V
FLBK
0.80×
FLBK
V
V
IN
GND
SWITCH
STATE
OFF
ON
OFF
ON
MINIMUM t
ON
ENABLE DELAY
DISABLED
MINIMUM ENABLE TIME
FLYBACK AMP
STATE
ENABLED
DISABLED
1737 TD
W
FLYBACK ERROR A PLIFIER
T1
•
D1
+
•
+
ISOLATED
C1
V
OUT
–
V
IN
•
M1
I
M
I
FXD
V
C
R1
R2
ENAB
FB
V
BG
C2
Q1 Q2
I
1737 EA
I
M
1737fa
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LT1737
U
OPERATIO
The LT1737 is a current mode switcher controller IC
designedspecificallyfortheisolatedflybacktopology. The
Block Diagram shows an overall view of the system. Many
of the blocks are similar to those found in traditional
designs, including: Internal Bias Regulator, Oscillator,
Logic, Current Amplifier and Comparator, Driver and Out-
put Switch. The novel sections include a special Flyback
Error Amplifier and a Load Compensation mechanism.
Also, due to the special dynamic requirements of flyback
control, the Logic system contains additional functionality
not found in conventional designs.
The relatively high gain in the overall loop will then cause
the voltage at the FB pin to be nearly equal to the bandgap
reference VBG. The relationship between VFLBK and VBG
may then be expressed as:
R1+ R2
(
)
VFLBK
=
VBG
R2
Combination with the previous VFLBK expression yields an
expression for VOUT in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
TheLT1737operatesmuchthesameastraditionalcurrent
mode switchers, the major difference being a different
type of error amplifier that derives its feedback informa-
tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is Application
Note AN19.
R1+ R2
⎛
⎞
(
)
1
N
ST
VOUT = VBG
– V –ISEC •ESR
F
⎜
⎟
R2
⎝
⎠
Additionally, it includes the effect of nonzero secondary
outputimpedance,whichisdiscussedinfurtherdetail,see
Load Compensation Theory. The practical aspects of
applying this equation for VOUT are found in the Applica-
tions Information section.
ERROR AMPLIFIER—PSEUDO DC THEORY
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dotted line connections to the
block labeled “ENAB”. Timing signals are then required to
enable and disable the flyback amplifier.
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when MOSFET output
switch M1 turns off, its drain voltage rises above the VIN
rail.Theamplitudeofthisflybackpulseasseenonthethird
winding is given as:
V
OUT
+ VF + ISEC •ESR
(
)
VFLBK
=
NST
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals that are required for
proper LT1737 operation. Please refer to the Timing
Diagram.
VF = D1 forward voltage
ISEC = transformer secondary current
ESR = total impedance of secondary circuit
Minimum Output Switch On Time
NST = transformer effective secondary-to-third
winding turns ratio
The LT1737 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse and output voltage informa-
tion is no longer available. This would cause irregular loop
responseandstart-up/latchupproblems.Thesolutioncho-
sen is to require the output switch to be on for an absolute
minimumtimepereachoscillatorcycle.Thisinturnestab-
lishes a minimum load requirement to maintain regula-
The flyback voltage is then scaled by external resistor
divider R1/R2 and presented at the FB pin. This is then
compared to the internal bandgap reference by the differ-
ential transistor pair Q1/Q2. The collector current from Q1
is mirrored around and subtracted from fixed current
source IFXD at the VC pin. An external capacitor integrates
this net current to provide the control voltage to set the
current mode trip point.
tion. See Applications Information for further details.
1737fa
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LT1737
U
OPERATIO
Enable Delay
Minimum Enable Time
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
formerprimarysidevoltagewaveformapproximatelyrep-
resents the output voltage. This is partly due to finite rise
time on the MOSFET drain node, but more importantly,
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side not directly related to
output voltage. (Some time is also required for internal
settling of the feedback amplifier circuitry.)
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
thelowloadlevelatwhichoutputvoltageregulationislost.
See Applications Information for details.
Inordertomaintainimmunitytothesephenomena, afixed
delay is introduced between the switch turnoff command
and the enabling of the feedback amplifier. This is termed
enable delay. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Application Infor-
mation for further details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
thefixed“minimumenabletime”describedtoamaximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and VC node slew rate.
Collapse Detect
Oncethefeedbackamplifierisenabled, somemechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodatesbothcontinuousanddiscontinuousmode
operation.
LOAD COMPENSATION THEORY
The LT1737 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
T1
V
IN
I
M
M1
R1
R2
+
–
FB
R3
50k
Q1 Q2
V
BG
Q3
A1
I
SENSE
LOAD
COMP I
R
SENSE
I
M
R
OCMP
R
CMPC
1737 F01
Figure 1. Load Compensation Diagram
1737fa
10
LT1737
U
OPERATIO
transformer secondary and output capacitor. This has
been represented previously by the expression “ISEC
⎛
⎞
VOUT
IIN =
•IOUT
⎜
⎟
•
V •Eff
⎝
⎠
IN
ESR.” However, it is generally more useful to convert this
expression to an effective output impedance. Because the
secondary current only flows during the off portion of the
duty cycle, the effective output impedance equals the
lumpedsecondaryimpedancetimestheinverseoftheOFF
duty cycle. That is:
combining the efficiency and voltage terms in a single
variable:
IIN = K1 • IOUT, where
⎛
⎞
VOUT
V •Eff
IN
K1=
⎜
⎟
⎝
⎠
⎛
⎞
1
ROUT = ESR
where
⎜
⎟
Switch current is converted to voltage by the external
sense resistor and averaged/lowpass filtered by R3 and
the external capacitor on RCMPC. This voltage is then
impressed across the external ROCMP resistor by op amp
A1 and transistor Q3. This produces a current at the
collector of Q3 which is then mirrored around and then
subtracted from the FB node. This action effectively in-
creases the voltage required at the top of the R1/R2
feedback divider to achieve equilibrium. So the effective
change in VOUT target is:
DC
⎝
⎠
OFF
ROUT = effective supply output impedance
ESR = lumped secondary impedance
DCOFF = OFF duty cycle
Expressing this in terms of the ON duty cycle, remember-
ing DCOFF = 1 – DC,
⎛
⎞
1
ROUT = ESR
⎜
⎟
1–DC
⎝
⎠
DC = ON duty cycle
⎛
⎞
RSENSE
∆VOUT = K1• ∆I
•(R1||R2)or
(
)
OUT
⎜
⎟
R
⎝
⎠
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external FB resistor
divider adjusted to compensate for nominal expected
error. Inmoredemandingapplications, outputimpedance
error may be minimized by the use of the load compensa-
tion function.
OCMP
⎛
⎞
∆VOUT
∆IOUT
RSENSE
= K1
•(R1||R2)
⎜
⎟
R
⎝
⎠
OCMP
Nominal output impedance cancellation is obtained by
equating this expression with ROUT
:
⎛
⎞
RSENSE
Toimplementtheloadcompensationfunction,avoltageis
developed that is proportional to average output switch
current.Thisvoltageisthenimpressedacrosstheexternal
ROCMP resistor, and the resulting current acts to decrease
the voltage at the FB pin. As output loading increases,
averageswitchcurrentincreasestomaintainroughoutput
voltage regulation. This causes an increase in ROCMP
resistor current which effects a corresponding increase in
flyback voltage amplitude.
ROUT = K1
•(R1||R2) and
⎜
⎟
R
⎝
⎠
OCMP
⎛
⎞
RSENSE
ROUT
ROCMP = K1
•(R1||R2)where
⎜
⎟
⎝
⎠
K1 = dimensionless variable related to VIN, VOUT and
efficiency as above
RSENSE = external sense resistor
ROUT = uncompensated output impedance
Assuming a relatively fixed power supply efficiency, Eff,
(R1||R2) = impedance of R1 and R2 in parallel
Power Out = Eff • Power In
VOUT • IOUT = Eff • VIN • IIN
The practical aspects of applying this equation to deter-
mineanappropriatevaluefortheROCMP resistorarefound
in the Applications Information section.
Average primary side current may be expressed in terms
of output current as follows:
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TRANSFORMER DESIGN CONSIDERATIONS
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Transformer specification and design is perhaps the most
critical part of applying the LT1737 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
Turns Ratios
Note that due to the use of the external feedback resistor
divider ratio to set output voltage, the user has relative
freedominselectingtransformerturnsratiotosuitagiven
application. In other words, “screwball” turns ratios like
“1.736:1.0” can scrupulously be avoided! In contrast,
simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can
be employed which yield more freedom in setting total
turns and mutual inductance. Turns ratio can then be
chosen on the basis of desired duty cycle. However,
remember that the input supply voltage plus the second-
ary-to-primary referred version of the flyback pulse (in-
cludingleakagespike)mustnotexceedtheallowedexternal
MOSFET breakdown rating.
Leakage Inductance
1. Operate the prototype supply at maximum expected
load current.
Transformer leakage inductance (on either the primary or
secondary)causesaspikeafteroutputswitchturnoff.This
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In many cases a
“snubber” circuit will be required to avoid overvoltage
breakdown at the output switch node. Application Note
AN19 is a good reference on snubber design.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the VSW waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note—the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V2/R behavior are less susceptible.
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node, and this works to
the user’s advantage in rejecting large, i.e., higher voltage,
leakage spikes. In other words, once a leakage spike is
several volts in amplitude, a further increase in amplitude
has little effect on the feedback system. So the user is
generally advised to arrange the snubber circuit to clamp
at as high a voltage as comfortably possible, observing
MOSFET breakdown, such that leakage spike duration is
as short as possible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
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which reduces the size of the primary-referred flyback
pulse used for feedback. This will increase the output
voltage target by a similar percentage. Note that unlike
leakage spike behavior, this phenomena is load indepen-
dent. To the extent that the secondary leakage inductance
is a constant percentage of mutual inductance (over
manufacturing variations), this can be accommodated by
adjusting the feedback resistor divider ratio.
two unknowns” is obtained from noting that the Thevenin
impedance of the resistor divider should be roughly 3k for
bias current cancellation and other reasons.
SELECTING ROCMP RESISTOR VALUE
The Operation section previously derived the following
expressions for ROUT, i.e., effective output impedance and
R
OCMP, the external resistor value required for its nominal
compensation:
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (POUT/PIN). Resistance in the
secondary increases effective output impedance which
degrades load regulation, (at least before load compensa-
tion is employed).
⎛
⎞
1
ROUT = ESR
⎜
⎟
1–DC
⎝
⎠
⎛
⎞
RSENSE
ROUT
ROCMP = K1
R1||R2
(
)
⎜
⎟
⎝
⎠
While the value for ROCMP may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of VIN to
VOUT times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However, re-
member that this will increase primary-to-secondary ca-
pacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
Build a prototype of the desired supply using the eventual
secondary components. Temporarily ground the RCMPC
pintodisabletheloadcompensationfunction. Operatethe
supply over the expected range of output current loading
while measuring the output voltage deviation. Approxi-
mate this variation as a single value of ROUT (straight line
approximation). Calculate a value for the K1 constant
based on VIN, VOUT and the measured (differential) effi-
ciency. These are then combined with RSENSE as indicated
SELECTING FEEDBACK RESISTOR DIVIDER VALUES
The expression for VOUT developed in the Operation sec-
tioncanberearrangedtoyieldthefollowingexpressionfor
the R1/R2 ratio:
R1+ R2
V
OUT
+ VF + ISEC •ESR
(
)
(
)
=
NST
where:
R2
VBG
VOUT = desired output voltage
to yield a value for ROCMP
.
VF = switching diode forward voltage
Verify this result by connecting a resistor of roughly this
value from the ROCMP pin to ground. (Disconnect the
ground short to RCMPC and connect the requisite 0.1µF
filter capacitor to ground.) Measure the output impedance
with the new compensation in place. Modify the original
ROCMP value if necessary to increase or decrease the
effective compensation.
ISEC • ESR = secondary resistive losses
VBG = data sheet reference voltage value
NST = effective secondary-to-third winding turns ratio
The above equation defines only the ratio of R1 to R2, not
their individual values. However, a “second equation for
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SELECTING OSCILLATOR CAPACITOR VALUE
1000
The switching frequency of the LT1737 is set by an
external capacitor connected between the OSCAP pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 2 shows the nominal relationship between
external capacitance and switching frequency. To mini-
mize stray capacitance and potential noise pickup, this
capacitor should be placed as close as possible to the IC
and the OSCAP node length/area minimized.
500
100
20
100
250
R
(kΩ)
T
300
1737 F03
Figure 3. “One Shot” Times vs Programming Resistor
indicative of actual current level in the transformer pri-
mary, and may cause irregular current mode switching
action, especially at light load.
100
50
However, the user must remember that the LT1737 does
not “skip cycles” at light loads. Therefore, minimum on
time will set a limit on minimum delivered power and con-
sequently a minimum load requirement to maintain regu-
lation (see Minimum Load Considerations). Similarly,
minimum on time has a direct effect on short-circuit be-
havior(seeMaximumLoad/Short-CircuitConsiderations).
30
100
(pF)
200
C
OSCAP
1737 F02
Figure 2. fOSC vs OSCAP Value
The user is normally tempted to set the minimum on time
to be short to minimize these load related consequences.
(Afterall, asmallerminimumontimeapproachestheideal
caseofzero, ornominimum.)However, alongertimemay
be required in certain applications based on MOSFET
switching current spike considerations.
SELECTING TIMING RESISTOR VALUES
There are three internal “one-shot” times that are pro-
grammed by external application resistors: minimum on
time, enable delay time and minimum enable time. These
are all part of the isolated flyback control technique, and
theirfunctionshavebeenpreviouslyoutlinedintheOpera-
tion section. Figure 3 shows nominal observed time ver-
sus external resistor value for these functions.
Enable Delay Time
This function provides a programmed delay between
turnoffofthegatedrivenodeandthesubsequentenabling
of the feedback amplifier. At high loads, a primary side
voltage spike after MOSFET turnoff may be observed due
to transformer leakage inductance. This spike is not in-
dicative of actual output voltage (see Figure 4B). Delaying
the enabling of the feedback amplifier allows this system
to effectively ignore most or all of the voltage spike and
maintain proper output voltage regulation. The enable
delay time should therefore be set to the maximum ex-
pected duration of the leakage spike. This may have
The following information should help in selecting and/or
optimizing these timing values.
Minimum On Time
This time defines a period whereby the normal switch
current limit is ignored. This feature provides immunity to
the leading edge current spike often seen at the source
nodeoftheexternalpowerMOSFET, duetorapidcharging
of its gate/source capacitance. This current spike is not
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implications regarding output voltage regulation at mini-
Average “start-up” VC current =
mum load (see Minimum Load Considerations).
MinimumEnable Time
•ISRC
A second benefit of the enable delay time function occurs
at light load. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage (see Figure 4C). So
the enable delay time should also be set long enough to
ignore the “irrelevant” portion of the flyback waveform at
light load.
SwitchingFrequency
Minimum enable time can also have implications at light
load (see Minimum Load Considerations). The temptation
is to set the minimum enable time to be fairly short, as this
is the least restrictive in terms of minimum load behavior.
However,toprovidea“reliable”minimumstart-upcurrent
of say, nominally 1µA, the user should set the minimum
enable time at no less that 2% of the switching period
(= 1/switching frequency).
Additionally, there are cases wherein the gate output is
called upon to drive a large geometry MOSFET such that
the turnoff transition is slowed significantly. Under such
circumstances, the enable delay time may be increased to
accommodate for the lengthy transition.
CURRENT SENSE RESISTOR CONSIDERATIONS
The external current sense resistor allows the user to
optimize the current limit behavior for the particular appli-
cation under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak switch current goes from a fraction of an ampere to
tens of amperes. Care must be taken to ensure proper
circuit operation, especially with small current sense
resistor values.
MOSFET GATE DRIVE
A
B
IDEALIZED FLYBACK
WAVEFORM
For example, a peak switch current of 10A requires a
sense resistor of 0.025Ω. Note that the instantaneous
peak power in the sense resistor is 2.5W, and it must be
ratedaccordingly.TheLT1737hasonlyasinglesenseline
to this resistor. Therefore, any parasitic resistance in the
ground side connection of the sense resistor will increase
its apparent value. In the case of a 0.025Ω sense resistor,
one milliohm of parasitic resistance will cause a 4%
reduction in peak switch current. So resistance of printed
circuit copper traces and vias cannot necessarily be
ignored.
FLYBACK WAVEFORM
WITH LARGE LEAKAGE
SPIKE AT HEAVY LOAD
ENABLE
DELAY
TIME
DISCONTINUOUS
MODE
NEEDED
RINGING
“SLOW” FLYBACK
WAVEFORM AT
LIGHT LOAD
C
ENABLE DELAY
TIME NEEDED
1737 F04
An additional consideration is parasitic inductance. In-
ductance in series with the current sense resistor will
accentuatethehighfrequencycomponentsofthecurrent
waveform. In particular, the gate switching spike and
multimegahertz ringing at the MOSFET can be
considerably amplified. If severe enough, this can cause
Figure 4
Minimum Enable Time
This function sets a minimum duration for the expected erratic operation. For example, assume 3nH of parasitic
flyback pulse. Its primary purpose is to provide a mini- inductance (equivalent to about 0.1 inch of wire in free
mum source current at the VC node to avoid start-up space) is in series with an ideal 0.025Ω sense resistor.
problems.
A “zero” will be formed at f = R/(2πL), or 1.3MHz. Above
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thresholdisdeliberatelysetataVBE plusseveralhundred
millivolts.) When this condition is removed, a nominal
40µA current acts to charge up the SFST node towards
roughly 3V. So, for example, a 0.1µF soft-start capacitor
will place a 0.4V/ms limit on the ramp rate at the VC node.
this frequency the sense resistor will behave like an
inductor.
Several techniques can be used to tame this potential
parasitic inductance problem. First, any resistor used for
current sensing purposes must be of an inherently non-
inductive construction. Mounting this resistor directly
above an unbroken ground plane and minimizing its
ground side connection will serve to absolutely minimize
parasitic inductance. In the case of low valued sense
resistors, these may be implemented as a parallel combi-
nation of several resistors for the thermal considerations
citedabove. Theparallelcombinationwillhelptolowerthe
parasitic inductance. Finally, it may be necessary to place
a “pole” between the current sense resistor and the
LT1737 ISENSE pin to undo the action of the inductive zero
(seeFigure5).Avalueof51Ωissuggestedfortheresistor,
whilethecapacitorisselectedempiricallyfortheparticular
application and layout. Using good high frequency mea-
surement techniques, the ISENSE pin waveform may be
observed directly with an oscilloscope while the capacitor
value is varied.
UVLO PIN FUNCTION
The UVLO pin effects both undervoltage lockout and
shutdownfunctions. Thisisaccomplishedbyusingdiffer-
ent voltage thresholds for the two functions—the shut-
down function is at roughly a VBE above ground (0.75V at
25°C, large temperature variation), while the UVLO func-
tionisatnearlyabandgapvoltage(1.25V,fairlystablewith
temperature). An external resistor divider between the
input supply and ground can then be used to achieve a
user-programmableundervoltagelockout(seeFigure6a).
An additional feature of this pin is that there is a change in
the input bias current at this pin as a function of the state
of the internal UVLO comparator. As the pin is brought
abovetheUVLOthreshold, thebiascurrentsourcedbythe
part increases. This positive feedback effects a hysteresis
band for reliable switching action. Note that the size of the
hysteresis is proportional to the Thevenin impedance of
the external UVLO resistor divider network, which makes
it user programmable. As a rough rule of thumb, each 4k
or so of impedance generates about 1% of hysteresis.
(This is based on roughly 1.25V for the threshold and 3µA
for the bias current shift.)
SENSE RESISTOR ZERO AT:
R
2πL
SENSE
GATE
SENSE
f =
P
51Ω
I
COMPENSATING POLE AT:
C
COMP
R
SENSE
SGND PGND
1
f =
2π(51Ω)C
COMP
L
P
FOR CANCELLATION:
PARASITIC
INDUCTANCE
L
P
C
COMP
=
R
(51Ω)
SENSE
1737 F05
Even in good quality ground plane layouts, it is common
for the switching node (MOSFET drain) to couple to the
UVLO pin with a stray capacitance of several thousandths
of a pF. To ensure proper UVLO action, a 100pF capacitor
is recommended from this pin to ground as shown in
Figure 6b. This will typically reduce the coupled noise to
a few millivolts. The UVLO filter capacitor should not be
mademuchlargerthanafewhundredpF, however, asthe
hysteresis action will become too slow. In cases where
further filtering is required, e.g., to attenuate high speed
supply ripple, the topology in Figure 6c is recommended.
Resistor R1 has been split into two equal parts. This
provides a node for effecting capacitor filtering of high
speed supply ripple, while leaving the UVLO pin node
impedance relatively unchanged at high frequency.
1737fa
Figure 5
SOFT-START FUNCTION
The LT1737 contains an optional soft-start function that is
enabled by connecting an explicit external capacitor be-
tweentheSFSTpinandground. Internalcircuitryprevents
thecontrolvoltageattheVC pinfromexceedingthatonthe
SFST pin.
The soft-start function is enagaged whenever VCC power
is removed, or as a result of either undervoltage lockout
or thermal (overtemperature) shutdown. The SFST node
isthendischargedrapidlytoroughlyaVBE aboveground.
(Remember that the VC pin control node switching
16
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U
V
IN
R1/2
R1/2
R2
V
V
IN
IN
C2
R1
R2
R1
R2
UVLO
UVLO
UVLO
C1
100pF
C1
100pF
1737 F06
(6a) “Standard” UVLO
Divider Topology
(6b) Filter Capacitor
Directly on UVLO Note
(6c) Recommended Topology to
Filter High Frequency Ripple
Figure 6
FREQUENCY COMPENSATION
Internal Voltage Reference
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (VC
pin) to ground. An additional series resistor, often re-
quired in traditional current mode switcher controllers, is
usually not required and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzerosecondarycircuitimpedance,whichaddsa“zero”
to the loop response.
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications.
User Programming Resistors
Outputvoltageiscontrolledbytheuser-suppliedfeedback
resistor divider ratio. To the extent that the resistor ratio
differs from the ideal value, the output voltage will be
proportionally affected. Highest accuracy systems will
demand 1% components.
In further contrast to traditional current mode switchers,
VC pinrippleisgenerallynotanissuewiththeLT1737. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the VC
voltagechangesduringtheflybackpulse,butisthen“held”
during the subsequent “switch on” portion of the next
cycle. This action naturally holds the VC voltage stable
duringthecurrentcomparatorsenseaction(currentmode
switching).
Schottky Diode Drop
The LT1737 senses the output voltage from the trans-
former primary side during the flyback portion of the
cycle. This sensed voltage therefore includes the forward
drop, VF, of the rectifier (usually a Schottky diode). The
nominal VF of this diode should therefore be included in
feedback resistor divider calculations. Lot to lot and
ambient temperature variations will show up as output
voltage shift/drift.
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error: the internal or external resistor divider
network that connects to VOUT and the internal IC refer-
ence.TheLT1737,whichsensestheoutputvoltageinboth
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary re-
duces the effective secondary-to-third winding turns ratio
(NS/NT) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part to
part, this can be accommodated by adjusting the feedback
resistor ratio.
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Output Impedance Error
f = switching frequency
LPRI = transformer primary side inductance
VIN = input voltage
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi-
nal expected error. In more demanding applications, out-
put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).
VOUT = output voltage
tON = output switch minimum on time
An additional constraint has to do with the minimum
enable time. The LT1737 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, tED, plus the
minimum enable time, tEN. Minimum power delivered to
the load is then:
MINIMUM LOAD CONSIDERATIONS
2
⎛
⎜
⎞
1
2 L
f
Minimum Power =
VOUT • t + t
(
)
EN
ED
[
]
⎟
The LT1737 generally provides better low load perfor-
mance than previous generation switcher/controllers uti-
lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon-
tinuousmode. Nevertheless, therestillremainconstraints
to ultimate low load operation. These relate to the mini-
mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
following theoretical derivations.
⎝
⎠
SEC
= VOUT •IOUT
Which yields a minimum output constraint:
⎛
⎞
2
1 f • VOUT
IOUT(MIN)
=
t
+ tEN
(
)
ED
where
⎜
⎟
2
LSEC
⎝
⎠
f = switching frequency
LSEC = transformer secondary side inductance
VOUT = output voltage
As outlined in the Operation section, the LT1737 utilizes a
minimum output switch on time, tON. This value can be
combined with expected VIN and switching frequency to
yield an expression for minimum delivered power.
tED = enable delay time
tEN = minimum enable time
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum on time”
constrained,or“minimumflybackpulsetime”constrained.
(A final note—LPRI and LSEC refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
⎛
⎜
⎞
2
1
2 L
f
Minimum Power =
V • t
IN ON
(
)
⎟
⎝
⎠
PRI
= VOUT •IOUT
This expression then yields a minimum output current
constraint:
⎛
⎜
⎞
2
1
f
IOUT(MIN)
=
V • t
IN ON
(
)
where
⎟
2 LPRI • VOUT
⎝
⎠
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MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
Trouble is typically only encountered in applications with
a relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switchontime.(Additionally,severalrealworldeffectssuch
astransformerleakageinductance,ACwindinglosses,and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate.)
The LT1737 is a current mode controller. It uses the VC
nodevoltageasaninputtoacurrentcomparatorthatturns
offtheoutputswitchonacycle-by-cyclebasisasthispeak
current is reached. The internal clamp on the VC node,
nominally2.5V, thenactsasanoutputswitchpeakcurrent
limit.
This 2.5V at the VC pin corresponds to a value of 250mV
at the ISENSE pin, when the (ON) switch duty cycle is less
than 40%. For a duty cycle above 40%, the internal slope
compensation mechanism lowers the effective ISENSE
voltage limit. For example, at a duty cycle of 80%, the
nominal ISENSE voltage limit is 220mV. This action be-
comes the switch current limit specification. Maximum
available output power is then determined by the switch
current limit, which is somewhat duty cycle dependent
due to internal slope compensation action.
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage condition does not cause excessive die tempera-
tures. The 16-lead SO package is rated at 100°C/W, and
the 16-lead GN at 110°C/W.
Average supply current is simply the sum of quiescent
current given in the specifications section plus gate drive
current. Gate drive current can be computed as:
IG = f • QG where
Overcurrent conditions are handled by the same mecha-
nism. The output switch turns on, the peak current is
quickly reached and the switch is turned off. Because the
outputswitchisonlyonforasmallfractionoftheavailable
period, power dissipation is controlled.
QG = total gate charge
f = switching frequency
(Note:TotalgatechargeismorecomplicatedthanCGS •VG
as it is frequently dominated by Miller effect of the CGD.
Furthermore, both capacitances are nonlinear in practice.
Fortunately, most MOSFET data sheets provide figures
and graphs which yield the total gate charge directly per
operating conditions.) Nearly all gate drive power is dissi-
pated in the IC, except for a small amount in the external
gate series resistor, so total IC dissipation may be com-
puted as:
Loss of current limit is possible under certain conditions.
Remember that the LT1737 normally exhibits a minimum
switchontime,irrespectiveofcurrenttrippoint.Iftheduty
cycleexhibitedbythisminimumontimeisgreaterthanthe
ratio of secondary winding voltage (referred-to-primary)
divided by input voltage, then peak current will not be
controlled at the nominal value, and will cycle-by-cycle
ratchet up to some higher level. Expressed mathemati-
cally, the requirement to maintain short-circuit control is:
PD(TOTAL) = VCC (IQ + • f • QG ), where
IQ = quiescent current (from specifications)
QG = total gate charge
V + I •R
SEC
(
)
F
SC
tON • f <
where
V •NSP
IN
f = switching frequency
tON = output switch minimum on time
f = switching frequency
VCC = LT1737 supply voltage
ISC = short-circuit output current
VF = output diode forward voltage at ISC
RSEC = resistance of transformer secondary
VIN = input voltage
SWITCH NODE CONSIDERATIONS
For maximum efficiency, gate drive rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the
components connected to the IC is essential, especially
NSP = secondary-to-primary turns ratio (NSEC/NPRI
)
1737fa
19
LT1737
W U U
U
APPLICATIO S I FOR ATIO
the power paths (primary and secondary). B field (mag-
netic) radiation is minimized by keeping MOSFET leads,
output diode and output bypass capacitor leads as short
as possible. E field radiation is kept low by minimizing the
length and area of all similar traces. A ground plane
should always be used under the switcher circuitry to
prevent interplane coupling.
GATE DRIVE RESISTOR CONSIDERATIONS
The gate drive circuitry internal to the LT1737 has been
designed to have as low an output impedance as practi-
cally possible—only a few ohms. A strong L/C resonance
is potentially presented by the inductance of the path
leading to the gate of the power MOSFET and its overall
gate capacitance. For this reason the path from the GATE
package pin to the physical MOSFET gate should be kept
as short as possible, and good layout/ground plane prac-
tice used to minimize the parasitic inductance.
The high speed switching current paths are shown sche-
matically in Figure 7. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary and MOSFET, and the path containing the trans-
former secondary, output diode and output capacitor
contain “nanosecond” rise and fall times. Keep these
paths as short as possible.
Anexplicitseriesgatedriveresistormaybeusefulinsome
applications to damp out this potential L/C resonance
(typically tens of MHz). A minimum value of perhaps
several ohms is suggested, and higher values (typically a
few tens of ohms) will offer increased damping. However,
as this resistor value becomes too large, gate voltage rise
time will increase to unacceptable levels, and efficiency
will suffer due to the sluggish switching action.
V
CC
V
IN
+
GATE
CHARGE
PATH
+
+
V
CC
SECONDARY
POWER
PATH
GATE
PRIMARY
POWER
PATH
PGND
GATE
1737 F07
DISCHARGE
PATH
Figure 7. High Speed Current Switching Paths
1737fa
20
LT1737
U
TYPICAL APPLICATIO S
BASIC APPLICATION WITH
3-WINDING TRANSFORMER
the LT1737 and the gate of MOSFET M1, an LT1121 low
dropout linear regulator is employed (U2). Resistor di-
viderR11/R12setstheoutputofU2atnominally8.25V. (A
few hundred millivolts of dropout will therefore be seen at
the very bottom of the input supply range.) The positive
goingdrivepotentialattheLT1737GATEpinistypically2V
orsobelowitsVCC supplypin, soalogiclevelMOSFEThas
been specified for M1.
Figure 8 shows a compact, low power application of the
LT1737.TransformerT1isanoff-the-shelfVERSA-PACTM,
#VP1-0190, produced by Coiltronics. As manufactured, it
consists of six ideally identical independent windings. In
this application, two windings are stacked in series on the
primary side and three are placed in parallel on the
secondary side. This arrangement provides a 2:1 primary-
to-secondary turns ratio while maximizing overall effi-
ciency. The remaining primary side winding provides a
ground-referred version of the flyback voltage waveform
for the purpose of feedback.
Capacitor C6 sets the switching frequency at approxi-
mately 200kHz. Optimal load compensation for the
transformer and secondary circuit components is set by
resistor R8. Resistor R10 provides a guaranteed mini-
mumloadofabout20mAtomaintainroughoutputvoltage
regulation. The soft-start and UVLO features are unused
as shown.
The design accepts an input voltage in the range of 8V to
25Vandoutputsanisolated5V. Topreventovervoltageon
VERSA-PAC is a trademark of Coiltronics, Inc.
6
T1
COILTRONICS
VP1-0190
•
3
1
V
IN
D1
MBRD330
V
OUT
5V
+
C1
10 11 12
500mA
330µF
R9
68Ω
5%
•
•
R10
240Ω
5%
+
8
3
1
2
C2
68µF
10V
D2
INP
OUT
35V
R11
24k
5%
R12
20k
5%
1N5250
U2
•
•
•
8 9
7
LT1121
GND ADJ
4
2
C4
470pF
50V
X7R
C3
D3
1µF
MBR0540
25V
Z5U
L1
1µH
R3
5
V
OUT
12.7k
1%
9
10
15
CC
R2
5.1Ω
5%
5V
500mA
3V
UVLO
V
+
C8
OUT
8
7
16
M1
33µF
FB
GATE
SENSE
IRLL014
10V
LT1737
2
V
I
C
R1
0.2Ω
0.5W
R4
3.92k
1%
C9
1nF
OPTIONAL OUTPUT FILTER
R13
51Ω
5%
OSCAP SFST
t
ENDLY MINENAB R
R
SGND PGND
11
ON
OCMP
CMPC
C5
1nF
25V
X7R
25V
X7R
6
3
14
13
12
4
5
1
IRC TYPE LR 2010
C7
C6
R5
51k
5%
R6
51k
5%
R7
51k
5%
R8
4.3k
5%
0.1µF
25V
Z5U
47pF
50V
NPO
1737 F08
C1: SANYO ALUMINUM ELECTROLYTIC (35CV331GX)
C2: SANYO POSCAP (10TPC68M)
C8: SANYO POSCAP (10TPA33M)
L1: COILCRAFT DO1608C-102 1µH, 0.05Ω INDUCTOR
M1: INT’L RECTIFIER IRLL014 60V, 0.2Ω LOGIC LEVEL N-CH MOSFET
U2: LINEAR TECHNOLOGY MICROPOWER LDO REGULATOR
D1: MOTOROLA 30V, 3A SCHOTTKY RECTIFIER
D2: 20V, 500mW ZENER DIODE
D3: MOTOROLA 40V, 0.5A SCHOTTKY RECTIFIER
Figure 8. 8V-25V to Isolated 5V Converter
1737fa
21
LT1737
U
TYPICAL APPLICATIO S
Overall power supply efficiency and output regulation
versus input voltage and load current may be seen in
Figures 9 and 10. Available output current is a function of
input voltage, varying from 650mA with 8V input to
1100mA with 25V input.
supply current required by the LT1737 generates more
and more wasted heat in linear regulator U2 as input
voltage is increased. The LT1725, a close “cousin” of the
LT1737 is recommended in such instances.
The LT1725 is very similar to the LT1737, but it contains
an integral wide hysteresis undervoltage lockout (UVLO)
circuit that monitors the VCC voltage. When used in
conjunction with a 3-winding transformer to provide both
device power and output voltage feedback information,
this allows for a “trickle charge” start-up from an input
voltage of up to hundreds of volts. The LT1725 is thus well
suited to operate from “telecom” input voltages of 48V to
72V,orevenofflineinputsuptoseveralhundredvolts!See
the LT1725 data sheet for further information.
Incaseswhentheoutputswitchingnoiseisobjectionable,
the optional output L/C filter shown may be added. The
oscilloscopephotosinFigure11showthedramaticreduc-
tion in output voltage ripple with the optional filter.
Note:Itistheoreticallypossibletoextendtheinputvoltage
range of this topology higher by raising the breakdown
voltage ratings on Q1, U2 and M1, while adjusting the
transformer windings as necessary. However this ap-
proach is generally undesirable as the relatively fixed
90
80
70
Without L/C Filter
V
= 8V
IN
60
50
40
30
20
V
= 15V
IN
50mV/DIV
AC COUPLED
V
= 25V
IN
0.01
1
0.1
(A)
I
VIN = 15V
1µs/DIV
1737 F11a
LOAD
ILOAD = 900mA
1737 F09
20MHz BANDWIDTH LIMITED
Figure 9. Efficiency vs ILOAD
With L/C Filter
5.25
5.00
V
IN
= 8V
V
= 15V
IN
V
= 25V
IN
50mV/DIV
AC COUPLED
4.75
0
250
500
750
(mA)
1000
1250
VIN = 15V
1µs/DIV
1737 F11b
ILOAD = 900mA
I
LOAD
20MHz BANDWIDTH LIMITED
1737 F10
Figure 10. Output Regulation
Figure 11
1737fa
22
LT1737
U
TYPICAL APPLICATIO S
APPLICATION WITH 2-WINDING TRANSFORMER
make this a preferable alternative. Furthermore, a variety
of manufacturers offer off-the-shelf dual wound magnet-
ics which often can be applied as 1:1 transformers.)
The previous application example utilized a 3-winding
transformer, the third winding providing only feedback
information. Additional circuitry may be employed to
provide feedback information, thus allowing the trans-
former to be reduced to a 2-winding topology. (The cost
and size savings associated with the transformer often
Figure 12 shows an LT1737 configured for operation with
a dual wound toroid, the Coiltronics #CTX150-4
OCTA-PACTM. A ground referred version of the flyback
voltagewaveformisnowprovidedbycomponentsQ1,R2,
OCTA-PAC is a trademark of Coiltronics, Inc.
R2
35.7k
1%
V
IN
+
C1
22µF
35V
T1
D1
COILTRONICS
CTX150-4
D2
BAS16
MBRS1100
V
OUT
Q1
2N3906
15V
1
3
R8
240k
5%
250mA
R11
100Ω
5%
•
R12
R13
7.5k
5%
+
C2
33µF
25V
D4
100Ω
1N5252
5%
C7
470pF
50V
X7R
•
C8
2
4
R9
33k
5%
0.1µF
25V
Z5U
C6
470pF
50V
X7R
D3
MBRS1100
9
10
UVLO
15
CC
R10
5.1Ω
3V
V
OUT
5%
8
16
M1
FB
GATE
SENSE
IRFL014
LT1737
ENDLY MINENAB R
7
2
V
C
I
R1
0.27Ω
0.5W
R3
3.01k
1%
OSCAP SFST
t
R
SGND PGND
11
ON
OCMP
4
CMPC
C3
1nF
25V
X7R
6
3
14
13
12
5
1
IRC TYPE LR 2010
C4
C5
R4
75k
5%
R5
150k
5%
R6
100k
5%
R7
4.7k
5%
0.1µF
25V
47pF
50V
NPO
1737 F12
Z5U
C1: AVX TPS TANTALUM (TPSE226M035R0300)
C2: AVX TPS TANTALUM (TPSE336M025R0200)
D1, D3: MOTOROLA 100V, 1A SCHOTTKY DIODE
D2: SIGNAL DIODE
M1: INT’L RECTIFIER 60V, 0.2Ω N-CH MOSFET
D4: 24V, 500mW ZENER DIODE
Figure 12. 12V-18V to Isolated 15V Converter
15.5
90
80
70
V
= 12V
IN
V
= 15V
IN
IN
V
= 18V
V
= 12V
IN
60
50
40
30
20
15.0
14.5
V
= 15V
V
= 18V
IN
IN
0
100
200
300
1
10
100
1000
I (mA)
LOAD
I
(mA)
LOAD
1737 F13
1737 F14
Figure 14. Load Regulation
Figure 13. Efficiency vs ILOAD
1737fa
23
LT1737
U
TYPICAL APPLICATIO S
R3 and D2. (Diode D2 prevents reverse emitter/base 5VIN APPLICATION
breakdown in Q1 when MOSFET M1 is in the “ON” state.)
The LT1737 is a bipolar technology IC specified to operate
The raw flyback voltage at the drain of MOSFET M1 minus
theVBE ofQ1isconvertedtoacurrentbyR2andthenback
to a voltage at R3. Or, stated mathematically:
downtoaminimuminputsupplyvoltageof4.5V.Although
its GATE pin drives “low” nearly to ground, its “high”
capability is limited by a headroom requirement of roughly
2VBEs. Thus when operating at a worst case 4.5V supply,
the GATE output will only drive up to a nominal 3V or so.
Fortunately, MOSFETs are now available with specified
performance at this level of gate voltage.
⎛
⎞
R3
R2
V = VFLBK – VBE
(
)
FB
⎜
⎟
⎝
⎠
Resistor R13 provides an initial pre-load to the supply
output to improve light load regulation. Resistor divider
R8/R9 sets the undervoltage lockout threshold at nomi-
nally 10.4V for turn-on, with turn-off about 600mV lower.
Overall power supply efficiency and output regulation
versus input voltage and load current may be seen in
Figures 13 and 14.
The circuit shown in Figure 15 provides an isolated 5V
output from an input between 4.5V and 5.5V. Two Si9804
low gate voltage MOSFETs are paralleled to handle the
primary-side current—up to 12A peak. This circuit pro-
vides more output power than the previous examples. It
V
IN
R2
11.0k
1%
+
+
C1A
C1B
220µF
10V
T1
D1
220µF
COILTRONICS
VP5-0083
D2
BAS16
MBRD835L
10V
V
5V
3A
OUT
Q1
2N3906
R8
R9
R10
270Ω
5%
+
C2A
220µF
10V
D4
12 11 10
4
9
5
8
6
7
10Ω
15Ω
•
•
•
1N5240
5%
5%
C7
2.2nF
50V
X7R
C8
1µF
25V
Z5U
•
•
•
3
C6
4.7nF
50V
X7R
1
2
+
C2B
220µF
10V
D3
MBR0520
9
10
UVLO
15
CC
3V
V
OUT
8
16
2
M1
SI9804
M2
SI9804
FB
GATE
SENSE
LT1737
7
V
C
I
R3
3.01k
1%
OSCAP SFST
t
ENDLY MINENAB R
R
SGND PGND
11
ON
14
OCMP
CMPC
C3
R11
51Ω
5%
1nF
25V
X7R
6
3
13
12
4
5
1
R1
C9
C4
C5
R4
75k
5%
R5
51k
5%
R6
51k
5%
R7
2.2k
5%
0.02Ω
1nF
25V
X7R
0.1µF
25V
Z5U
47pF
50V
NPO
1737 F15
C1A-B, C2A-B: SANYO POSCAP (10TPB220M)
D1: MOTOROLA 35V, 8A SCHOTTKY DIODE
D2: SIGNAL DIODE
D3: MOTOROLA 20V, 0.5A SCHOTTKY DIODE
D4: 10V, 500mW ZENER DIODE
M1, M2: SILICONIX/VISHAY 25V, 0.023Ω N-CH MOSFET
R1: 5 × 0.10Ω, 1W (IRC LR2512)
T1: COILTRONICS TRANSFORMER
Figure 15. 4.5V-5.5V to Isolated 5V Converter
1737fa
24
LT1737
U
TYPICAL APPLICATIO S
thereforerequiresaphysicallylargertransformer.Thelarg-
est size VERSA-PAC is used, a VP5-0083. Three windings
are paralleled for both the primary and secondary.
NONISOLATED APPLICATION
While the LT1737 was designed to serve isolated flyback
applications, it is useful to note that it is also capable of
supportingnonisolatedapplications.Theseareperformed
by providing a continuous pseudo-DC feedback signal to
the FB pin. (The part behaves as if the flyback waveform
is infinitely long.) Figure 18 demonstrates just such a
system.
Overall power supply efficiency and output regulation ver-
sus load current at the nominal VIN = 5V may be seen in
Figures 16 and 17.
90
80
70
60
50
40
30
20
A SEPIC topology is shown whereby a 8V to 16V input is
converted to a nonisolated 12V output. A conventional
resistive feedback divider, R3/R4 drives the FB pin. (Ca-
pacitor C7 serves to filter out high frequency ripple in the
output voltage.) A combination of an R/C network (R11/
C5) in parallel with a single capacitor (C9) on the VC node
provides the required loop compensation. The load com-
pensation function is unwanted, so the ROCMP pin is left
open and the RCMPC pin is grounded. An LT1121 low
dropout regulator is programmed to a nominal 8.25V
output by the R12/R13 resistor divider, and this allows the
LT1737 to drive M1, a logic level MOSFET. Minimum on
timeprogrammingresistorR5issetto33ktominimizethe
required output preload. Minimum enable time has no
direct effect on steady state operation, but programming
resistor R7 has been set to 100k for rapid start-up. Enable
delay resistor is similarly set to 24k.
0.01
0.1
1
10
I
(A)
LOAD
1737 F16
Figure 16. Efficiency vs ILOAD
5.25
Overall power supply efficiency versus input voltage and
load current may be seen in Figure 19. Because this
application example utilizes a nonisolated topology, load
regulation is not an issue. It is typically 0.2% (25mV) from
no load to full load.
5.00
4.75
Other nonisolated switching topologies may be similarly
implemented. For example, Boost and NonIsolated Fly-
back readily suggest themselves. (A Nonisolated Flyback
topology also can be used to generate a negative output
voltage. In this case, the feedback is a dynamic waveform
derived from the primary side of the transformer, similar
to an isolated LT1737 application.)
0
1
2
3
4
I
(A)
LOAD
1737 F17
Figure 17. Load Regulation
1737fa
25
LT1737
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
1737fa
26
LT1737
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
0.228 – 0.244
(3.810 – 3.988)
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1737fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LT1737
U
TYPICAL APPLICATIO S
V
IN
R3
C8
+
C1
150µF
20V
26.1k
0.1µF
1%
8
3
1
2
INP
OUT
L1
15µH
25V
Z5U
R8
160k
5%
R12
24k
5%
R13
20k
5%
U2
LT1121
GND ADJ
C7
R4
3.01k
1%
C2A
22µF
25V
47pF
50V
NPO
C4
R9
33k
5%
1µF
25V
Z5U
D1
MBRD640CT
9
10
15
R2
2.7Ω
5%
V
= 12V
OUT
3V
UVLO
V
CC
OUT
8
7
16
2
M1
C3
R14
+
FB
GATE
L2
15µH
IRLZ34S
33µF
16V
×4
C2B
22µF
25V
750Ω
LT1737
I
SENSE
5%
R11
22k
5%
C9
C10
R10
51Ω
5%
OSCAP SFST
t
ENDLY MINENAB R
R
SGND PGND
11
R1
0.025Ω
ON
OCMP
CMPC
5
47pF
50V
NPO
470pF
50V
1737 F18
6
3
14
13
12
4
1
C5
X7R
C6
R5
33k
5%
R6
24k
5%
R7
100k
5%
4.7nF
50V
47pF
50V
NPO
X7R
C1: SANYO OS-CON (20SV150M)
L1, L2: COILTRONICS UP4B-150 INDUCTOR
M1: INT’L RECTIFIER IRLZ34S 60V, 0.05Ω LOGIC LEVEL N-CH MOSFET
R1: IRC 4 × 0.1Ω, 1W (LR2512)
C2A-B: TOKIN Y5V (IE226ZY5U-C505)
C3: SANYO POSCAP (16TPC33M)
D1: MOTOROLA 40V, 6A SCHOTTKY DIODE
Figure 18. 8V-16V to 12V Nonisolated Converter
90
80
V
= 8V
IN
70
60
50
40
30
20
V
= 12V
IN
V
= 16V
IN
0.01
0.1
1
10
I
(A)
LOAD
1737 F19
Figure 19. Efficiency vs ILOAD
RELATED PARTS
PART NUMBER
LT1424-5
LT1424-9
LT1425
DESCRIPTION
COMMENTS
Isolated Flyback Switching Regulator
Isolated Flyback Switching Regulator
Isolated Flyback Switching Regulator
Ultralow Noise 1A Switching Regulator
General Purpose Isolated Flyback Controller
Ultra Low Noise DC/DC Controller
V
V
= 3V to 20V, I = 7mA
Q
IN
IN
= 3V to 20V, I = 7mA
Q
General Purpose with External Application Resistor
V = 2.7V to 23V, Reduced EMI and Switching Harmonics
IN
LT1533
LT1725
Suitable for Telecom or Offline Input Voltage
Reduced EMI and Switching Harmonics
LT1738
1737fa
LT/LT 0605 REV A • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2000
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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