LT1738EG [Linear]
Slew Rate Controlled Ultralow Noise DC/DC Controller; 压摆率控制的超低噪声DC / DC控制器
| 型号： | LT1738EG |
| 厂家： | 
Linear |
| 描述： | Slew Rate Controlled Ultralow Noise DC/DC Controller |
| 文件： | 总20页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1738
Slew Rate Controlled
Ultralow Noise DC/DC Controller
U
DESCRIPTIO
FEATURES
The LT®1738 is a switching regulator controller designed
to lower conducted and radiated electromagnetic interfer-
ence (EMI). Ultralow noise and EMI are achieved by
controlling the voltage and current slew rates of an exter-
nal N-channel MOSFET switch. Current and voltage slew
rates can be independently set to optimize harmonic
content of the switching waveforms vs efficiency. The
LT1738 can reduce high frequency harmonic power by as
much as 40dB with only minor losses in efficiency.
■
Greatly Reduced Conducted and Radiated EMI
■
■
Low Switching Harmonic Content
Independent Control of Output Switch Voltage and
Current Slew Rates
■
■
■
■
■
■
Greatly Reduced Need for External Filters
Single N-Channel MOSFET Driver
20kHz to 250kHz Oscillator Frequency
Easily Synchronized to External Clock
Regulates Positive and Negative Voltages
Easier Layout Than with Conventional Switchers
The LT1738 utilizes a current mode architecture opti-
mized for single switch topologies such as boost, flyback
and Cuk. The IC includes gate drive and all necessary
oscillator, control and protection circuitry. Unique error
amp circuitry can regulate both positive and negative
voltages. The internal oscillator may be synchronized to
an external clock for more accurate placement of switch-
ing harmonics.
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APPLICATIO S
■
Power Supplies for Noise Sensitive Communication
Equipment
■
EMI Compliant Offline Power Supplies
■
Precision Instrumentation Systems
■
Isolated Supplies for Industrial Automation
Protection features include gate drive lockout for low VIN,
soft-start, output current limit, short-circuit current limit-
ing, gate drive overvoltage clamp and input supply
undervoltage lockout.
■
Medical Instruments
Data Acquisition Systems
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Ultralow Noise 5V to 12V Converter
12V Output Noise
(Bandwidth = 100MHz)
MBRD620
22µH
10µH
B
A
5V
12V
1A
V
IN
+
+
150µF
OSCON
4 × 150µF
OSCON
P3
+
OPTIONAL
100µF
17
3
V
IN
GCL
5pF
POINT
A
14
2
1
4
400µV
P-P
SHDN
V5
CAP
ON SCHEMATIC
5
6
500µV/DIV
SYNC
1.3nF
7
8
Si9426
C
T
GATE
CS
POINT
B
LT1738
16.9k
ON SCHEMATIC
50mV/DIV
R
R
R
V
T
25k 3.3k
16
15
12
VSL
CSL
25mΩ
25k 3.3k
22nF
20
9
PGND
FB
21.5k
2.5k
C
1738 TA01a
5µs/DIV
0.22µF
SS GND NFB
1.5k
13 11 10
1738 TA01
10nF
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LT1738
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ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
Supply Voltage (VIN) ................................................ 20V
Gate Drive Current .....................................Internal Limit
V5 Current .................................................Internal Limit
SHDN Pin Voltage.................................................... 20V
Feedback Pin Voltage (Trans. 10ms) ...................... ±10V
Feedback Pin Current............................................ 10mA
Negative Feedback Pin Voltage (Trans. 10ms)........ ±10V
CS Pin.......................................................................... 5V
GCL Pin ..................................................................... 16V
SS Pin.......................................................................... 3V
Operating Junction Temperature Range
1
2
PGND
NC
20
19
18
17
16
15
14
13
12
11
GATE
CAP
GCL
CS
3
NC
LT1738EG
LT1738IG
4
V
IN
5
R
V5
VSL
6
R
SYNC
CSL
7
SHDN
SS
C
T
R
T
8
9
V
C
FB
10
GND
NFB
G PACKAGE
20-LEAD PLASTIC SSOP
(Note 3) ............................................ –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TJMAX = 150°C, θJA = 110°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL PARAMETER
Error Amplifiers
CONDITIONS
MIN
TYP
MAX
UNITS
V
Reference Voltage
Measured at Feedback Pin
●
●
●
●
1.235
1.250
250
1.265
1000
0.03
V
nA
REF
I
Feedback Input Current
V
= V
FB REF
FB
FB
Reference Voltage Line Regulation
Negative Feedback Reference Voltage
2.7V ≤ V ≤ 20V
0.012
–2.50
%/V
V
REG
IN
V
Measured at Negative Feedback Pin
with Feedback Pin Open
–2.56
–37
–2.45
NFR
I
Negative Feedback Input Current
V
= V
NFR
–25
0.009
1500
µA
NFR
NFB
NFB
Negative Feedback Reference Voltage Line Regulation 2.7V ≤ V ≤ 20V
●
0.03
%/V
REG
IN
g
Error Amplifier Transconductance
∆I = ±50µA
C
1100
700
2200
2500
µmho
µmho
m
●
●
●
I
I
Error Amp Sink Current
Error Amp Source Current
Error Amp Clamp Voltage
Error Amp Clamp Voltage
Error Amplifier Voltage Gain
FB Overvoltage Shutdown
Soft-Start Charge Current
V
V
= V + 150mV, V = 0.9V
120
120
200
200
1.27
0.12
250
1.47
9.0
350
350
µA
µA
V
ESK
FB
FB
REF
C
= V – 150mV, V = 0.9V
ESRC
REF
C
V
V
A
High Clamp, V = 1V
FB
CLH
CLL
V
Low Clamp, V = 1.5V
V
FB
180
V/V
V
FB
Outputs Drivers Disabled
OV
I
V
= 1V
SS
12
µA
SS
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LT1738
ELECTRICAL CHARACTERISTICS
other pins open unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and
SYMBOL PARAMETER
Oscillator and Sync
CONDITIONS
MIN
TYP
MAX
UNITS
f
f
Max Switch Frequency
250
kHz
kHz
MAX
Synchronization Frequency Range
SYNC Pin Input Threshold
SYNC Pin Input Resistance
Oscillator Frequency = 250kHz
290
0.7
SYNC
V
●
●
1.4
40
2
SYNC
R
kΩ
SYNC
Gate Drive
DC
VG
VG
Maximum Switch Duty Cycle
Gate On Voltage
R
VSL
= R = 3.9k,
CSL
90
93.5
%
MAX
Osc Frequency = 25kHz
V
V
= 12, GCL = 12
= 12, GCL = 8
10
7.6
10.4
7.9
10.7
8.1
V
V
ON
IN
IN
Gate Off Voltage
V
V
V
V
= 12V
= 12V
= 12V
0.2
0.35
V
A
A
V
OFF
IN
IG
IG
Max Gate Source Current
Max Gate Sink Current
0.3
0.3
SO
IN
SK
IN
V
Gate Drive Undervoltage Lockout (Note 5)
= 6.5V
GCL
7.3
7.5
INUVLO
Current Sense
t
Switch Current Limit Blanking Time
Sense Voltage Shutdown Voltage
Sense Voltage Fault Threshold
100
103
220
ns
mV
mV
IBL
V
V
V Pulled Low
C
●
86
120
300
SENSE
SENSEF
Slew Control for the Following Slew Tests See Test Circuit in Figure 1b
V
V
Output Voltage Slew Rising Edge
R
VSL
R
VSL
R
VSL
R
VSL
= R
= R
= R
= R
= 17k
= 17k
= 17k
= 17k
26
19
V/µs
V/µs
V/µs
V/µs
SLEWR
SLEWF
CSL
CSL
CSL
CSL
Output Voltage Slew Falling Edge
VI
VI
Output Current Slew Rising Edge (CS pin V)
Output Current Slew Falling Edge (CS pin V)
2.1
2.1
SLEWR
SLEWF
Supply and Protection
V
Minimum Input Voltage (Note 4)
Supply Current (Note 3)
V
= V
●
●
2.55
3.6
V
INMIN
VIN
GCL
IN
I
R
R
= R
= R
= 17k
= 17k
V
V
= 12
= 20
12
35
40
55
mA
mA
VSL
VSL
CSL
CSL
IN
IN
V
Shutdown Turn-On Threshold
Shutdown Turn-On Voltage Hysteresis
Shutdown Input Current Hysteresis
5V Reference Voltage
●
●
●
1.31
50
1.39
110
24
1.48
180
35
V
mV
µA
SHDN
∆V
SHDN
I
10
SHDN
V5
6.5V ≤ V ≤ 20V, IV5 = 5mA
4.85
4.80
5
5
5.20
5.15
V
V
IN
6.5V ≤ V ≤ 20V, IV5 = –5mA
IN
IV5
5V Reference Short-Circuit Current
V
V
= 6.5V Source
= 6.5V Sink
10
–10
mA
mA
SC
IN
IN
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: Supply current specification includes loads on each gate as in
Figure 1a. Actual supply currents vary with operating frequency, operating
voltages, V5 load, slew rates and type of external FET.
design, characterization and correlation with statistical process
controls.The LT1738I is guaranteed and tested to meet performance
specifications from – 40°C to 125°C.
Note 4: Output gate drive is enabled at this voltage. The GCL voltage will
also determine driver activity.
Note 3: The LT1738E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications from –40°C to 125°C are assured by
Note 5: Gate drive is ensured to be on when V is greater than max value.
IN
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LT1738
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TYPICAL PERFOR A CE CHARACTERISTICS
Feedback Voltage and Input
Current vs Temperature
Negative Feedback Voltage and
Input Current vs Temperature
1.260
1.258
1.256
1.254
1.252
1.250
1.248
1.246
1.244
1.242
1.240
750
700
650
600
550
500
450
400
350
300
250
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G01
1738 G02
Feedback Overvoltage Shutdown
vs Temperature
Error Amp Transconductance vs
Temperature
Error Amp Output Current vs
Feedback Pin Voltage from Nominal
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
500
400
–40°C
300
25°C
200
100
125°C
0
–100
–200
–300
–400
–500
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
–400 –300 –200 –100
0
100 200 300 400
TEMPERATURE (°C)
TEMPERATURE (°C)
FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)
1738 G03
1738 G04
1738 G05
VC Pin Threshold and Clamp
Voltage vs Temperature
CS Pin Trip Voltage and CS Fault
Voltage vs Temperature
SHDN Pin On and Off Thresholds
vs Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.50
1.45
1.40
1.35
1.30
1.25
240
220
200
180
160
140
120
100
80
CLAMP
FAULT
ON
THRESHOLD
TRIP
OFF
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1738 G06
1738 G07
1738 G08
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LT1738
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TYPICAL PERFOR A CE CHARACTERISTICS
SHDN Pin Hysteresis Current vs
Temperature
CS Pin to VC Pin Transfer
Function
VIN Current vs Temperature
27
25
23
21
19
17
15
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
18
17
16
15
14
13
12
T
= 25°C
A
V
= 12 R , R
= 4.85k
IN
VSL CSL
V
= 20 R , R
= 17k
IN
VSL CSL
V
= 12 R , R
VSL CSL
= 17k
IN
11 USING LOAD OF FIGURE 1A
= 120kHz
10
–50 –25
f
OSC
–50 –25
0
25 50 75 100 125 150
25 50 75
0
20
40
60
80
100
120
0
100
125 150
TEMPERATURE (°C)
CS PIN VOLTAGE (mV)
TEMPERATURE (°C)
1738 G09
1738 G10
1738 G11
Gate Drive High Voltage vs
Temperature
Gate Drive Low Voltage vs
Temperature
Slope Compensation
110
100
90
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
9.90
9.80
9.70
6.5
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
T
PIN = 0.9V
V
= 12V
C
A
IN
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
= 25°C
NO LOAD
GCL = 12V
V
= 12V
IN
NO LOAD
80
70
GCL = 6V
60
50
0
20
40
60
80
100
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
DUTY CYCLE (%)
TEMPERATURE (°C)
TEMPERATURE (°C)
1738 G12
1738 G13
1738 G14
Gate Drive Undervoltage Lockout
Voltage vs Temperature
Soft-Start Current vs Temperature
V5 Voltage vs Load Current
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
9.5
5.08
5.06
5.04
5.02
5.00
4.98
4.96
GCL = 6V
SS VOLTAGE = 0.9V
9.3
9.1
8.9
8.7
8.5
8.3
8.1
7.9
7.7
7.5
T = 125°C
T = 25°C
T = –40°C
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD CURRENT (mA)
1738 G15
1738 G16
1738 G17
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LT1738
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PI FU CTIO S
Part Supply
PGND(Pin20):PowerDriverGround. Thisgroundcomes
from the MOSFET gate driver. This pin can have several
hundred milliamperes of current on it when the external
MOSFET is being turned off.
V5 (Pin 5): This pin provides a 5V output that can sink or
source 10mA for use by external components. V5 source
current comes from VIN . Sink current goes to GND. VIN
must be greater than 6.5V in order for this voltage to be in
regulation. Ifthispinisused, asmallcapacitor(<1µF)may
be placed on this pin to reduce noise. This pin can be left
open if not used.
Oscillator
SYNC (Pin 6): The SYNC pin can be used to synchronize
the part to an external clock. The oscillator frequency
should be set close to the external clock frequency.
Synchronizing the clock to an external reference is useful
for creating more stable positioning of the switcher volt-
age and current harmonics. This pin can be left open or
tied to ground if not used.
GND (Pin 11): Signal Ground. The internal error amplifier,
negative feedback amplifier, oscillator, slew control cir-
cuitry, V5 regulator, current sense and the bandgap refer-
ence are referred to this ground. Keep the connection to
this pin, the feedback divider and VC compensation net-
work free of large ground currents.
CT (Pin 7): The oscillator capacitor pin is used in conjunc-
tionwithRT tosettheoscillatorfrequency. ForRT =16.9k:
SHDN(Pin14):Theshutdownpincandisabletheswitcher.
Grounding this pin will disable all internal circuitry.
COSC(nf) = 129/fOSC(kHz)
RT (Pin 8): A resistor to ground sets the charge and
discharge currents of the oscillator capacitor. The nomi-
nal value is 16.9k. It is possible to adjust this resistance
±25% to set oscillator frequency more accurately.
Increasing SHDN voltage will initially turn on the internal
bandgapregulator. Thisprovidesaprecisionthresholdfor
the turn on of the rest of the IC. As SHDN increases past
1.39V the internal LDO regulator turns on, enabling the
control and logic circuitry.
Gate Drive
24µA of current is sourced out of the pin above the turn on
threshold. This can be used to provide hysteresis for the
shutdown function. The hysteresis voltage will be set by
the Thevenin resistance of the resistor divider driving this
pin times the current sourced out. Above approximately
2.1V the hysteresis current is removed. There is approxi-
mately 0.1V of voltage hysteresis on this pin as well.
GATE (Pin 1): This pin connects to the gate of an external
N-channel MOSFET. This driver is capable of sinking and
sourcing at least 300mA.
The GCL pin sets the upper voltage of the gate drive. The
GATEpinwillnotbeactivateduntilVIN reachesaminimum
voltage as defined by the GCL pin (gate undervoltage
lockout).
The pin can be tied high (to VIN for instance).
The gate drive output has current limit protection to safe
guard against accidental shorts.
VIN (Pin 17): Input Supply. All supply current for the part
comes from this pin including gate drive and V5 regulator.
Charge current for gate drive can produce current pulses
of hundreds of milliamperes. Bypass this pin with a low
ESR capacitor.
GCL(Pin3):Thispinsetsthemaximumgatevoltagetothe
GATE pin to the MOSFET gate drive. This pin should be
either tied to a zener, a voltage source, or VIN.
When VIN is below 2.55V the part will go into supply
undervoltage lockout where the gate driver is driven low.
This, along with gate drive undervoltage lockout, prevents
unpredictable behavior during power up.
If the pin is tied to a zener or a voltage source, the
maximum gate drive voltage will be approximately VGCL
– 0.2V. If it is tied to VIN, the maximum gate voltage is
approximately VIN – 1.6.
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LT1738
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PI FU CTIO S
Approximately 50µA of current can be sourced from this
exceed the voltage on SS. Thus peak current will ramp up
as the SS pin ramps up. During a short circuit fault the SS
pin will be discharged to ground thus reinitializing soft-
start.
pin if VGCL < VIN – 0.8V.
This pin also controls undervoltage lockout of the gate
drive. If the pin is tied to a zener or voltage source, the gate
drive will not be enabled until VIN > VGCL + 0.8V. If this pin
is tied to VIN, then undervoltage lockout is disabled.
When SS is below the VC clamp voltage the VC pin will
closely track the SS pin.
There is an internal 19V zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.
This pin can be left open if not used.
CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current
slewing of the external MOSFET. Current sense is accom-
plished via a sense resistor (RS) connected from the
sourceoftheexternalMOSFETtoground. CSisconnected
to the top of RS. Current sense is referenced to the GND
pin.
Slew Control
CAP (Pin 2): This pin is the feedback node for the external
voltage slewing capacitor. Normally a small 1pf to 5pf
capacitor is connected from this pin to the drain of the
MOSFET.
The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
The switch maximum operating current will be equal to
0.1V/RS. At CS = 0.1V, the gate driver will be immediately
turned off (no slew control).
proportional to RVSL
.
If CS = 0.22V in addition to the drivers being turned off, VC
and SS will be discharged to ground (short-circuit protec-
tion). This will hasten turn off on subsequent cycles.
RCSL (Pin 15): A resistor to ground sets the current slew
rate for the external drive MOSFET during switching. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states of the
MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to RCSL
andRS (thecurrentsenseresistor)andmaximumcurrent.
Longer times produce a greater reduction of higher fre-
quency harmonics.
FB (Pin 9): The feedback pin is used for positive voltage
sensing. It is the inverting input to the error amplifier. The
noninverting input of this amplifier connects internally to
a 1.25V reference.
If the voltage on this pin exceeds the reference by 220mV,
thentheoutputdriverwillimmediatelyturnofftheexternal
MOSFET (no slew control). This provides for output over-
voltage protection
RVSL (Pin 16): A resistor to ground sets the voltage slew
rate for the drain of the external drive MOSFET. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how dv/dt related
When this input is below 0.9V then the current sense
blanking will be disabled. This will assist start up.
NFB (Pin 10): The negative feedback pin is used for
sensing a negative output voltage. The pin is connected to
the inverting input of the negative feedback amplifier
through a 100k source resistor. The negative feedback
amplifierprovidesagainof–0.5totheFBpin. Thenominal
regulation point would be –2.5V on NFB. This pin should
be left open if not used.
harmonics are reduced. This time is proportional to RVSL
,
CV and the input voltage. Longer times produce more
rolloff of harmonics. CV is the equivalent capacitance from
CAP to the drain of the MOSFET.
Switch Mode Control
SS (Pin 3): The SS pin allows for ramping of the switch
currentthresholdatstartup.Normallyacapacitorisplaced
on this pin to ground. An internal 9µA current source will
charge this capacitor up. The voltage on the VC pin cannot
If NFB is being used then overvoltage protection will occur
at 0.44V below the NFB regulation point.
At NFB < –1.8 current sense blanking will be disabled.
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LT1738
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PI FU CTIO S
TEST CIRCUITS
VC (Pin 12): The compensation pin is used for frequency
compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground. The
voltage on VC is proportional to the switch peak current.
The normal range of voltage on this pin is 0.25V to 1.27V.
However, during slope compensation the upper clamp
voltage is allowed to increase with the compensation.
0.9A
IN5819
20mA
5pF
5pF
IN5819
CAP
CAP
GATE
CS
Si4450DY
10
GATE
ZVN3306A
+
+
10
2
0.1
–
–
1738 F01b
1738 F01a
During a short-circuit fault the VC pin will be discharged to
ground.
Figure 1a. Typical Test Circuitry
Figure 1b. Test Circuit for Slew
W
BLOCK DIAGRA
SHDN
14
V
V5
5
R
R
VSL
IN
CSL
17
15
16
TO
DRIVERS
+
REGULATOR
NEGATIVE
FEEDBACK
AMP
–
GCL
3
2
1
V
REG
100k
50k
NFB 10
CAP
GATE
–
+
FB
9
ERROR
AMP
SLEW
CONTROL
+
1.25V
V
C
12
13
20 PGND
–
+
4
CS
COMP
+
–
SS
SENSE
AMP
S
R
Q
FF
R
T
8
7
OSCILLATOR
SUB
C
T
6
11
1738 BD
SYNC
GND
1738fa
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OPERATIO
In noise sensitive applications switching regulators tend
to be ruled out as a power supply option due to their
propensity for generating unwanted noise. When switch-
ing supplies are required due to efficiency or input/output
constraints, great pains must be taken to work around the
noise generated by a typical supply. These steps may
include pre and post regulator filtering, precise synchro-
nizationofthepowersupplyoscillatortoanexternalclock,
synchronizing the rest of the circuit to the power supply
oscillator or halting power supply switching during noise
sensitive operations. The LT1738 greatly simplifies the
task of eliminating supply noise by enabling the design of
an inherently low noise switching regulator power supply.
transconductanceamplifierthatintegratesthedifference
between the feedback output voltage and an internal
1.25V reference. The output of the error amp adjusts the
switch current trip point to provide the required load
current at the desired regulated output voltage. This
method of controlling current rather than voltage pro-
vides faster input transient response, cycle-by-cycle
current limiting for better output switch protection and
greater ease in compensating the feedback loop. The VC
pin is used for loop compensation and current limit
adjustment. During normal operation the VC voltage will
be between 0.25V and 1.27V. An external clamp on VC or
SS may be used for lowering the current limit.
The LT1738 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switch. Current mode
control provides excellent AC and DC line regulation and
simplifies loop compensation.
The negative voltage feedback amplifier allows for direct
regulation of negative output voltages. The voltage on the
NFB pin gets amplified by a gain of – 0.5 and driven on to
the FB input, i.e., the NFB pin regulates to –2.5V while the
amplifier output internally drives the FB pin to 1.25V as in
normal operation. The negative feedback amplifier input
impedance is 100k (typ) referred to ground.
Slew control capability provides much greater control
over the power supply components that can create con-
ducted and radiated electromagnetic interference. Com-
pliance with EMI standards will be an easier task and will
require fewer external filtering components.
Soft-Start
Control of the switch current during start up can be
obtained by using the SS pin. An external capacitor from
SStogroundischargedbyaninternal9µAcurrentsource.
The voltage on VC cannot exceed the voltage on SS. Thus
as the SS pin ramps up the VC voltage will be allowed to
ramp up. This will then provide for a smooth increase in
switchmaximumcurrent. SSwillbedischargedasaresult
of the CS voltage exceeding the short circuit threshold of
approximately 0.22V.
The LT1738 uses an external N-channel MOSFET as the
power switch. This allows the user to tailor the drive
conditions to a wide range of voltages and currents.
CURRENT MODE CONTROL
Referring to the block diagram. A switching cycle begins
with an oscillator discharge pulse, which resets the RS
flip-flop, turning on the GATE driver and the external
MOSFET. The switch current is sensed across the external
sense resistor and the resulting voltage is amplified and
compared to the output of the error amplifier (VC pin). The
driver is turned off once the output of the current sense
amplifier exceeds the voltage on the VC pin. In this way
pulse by pulse current limit is achieved.
Slew Control
Controlofoutputvoltageandcurrentslewratesisachieved
via two feedback loops. One loop controls the MOSFET
drain dV/dt and the other loop controls the MOSFET dI/dt.
The voltage slew rate uses an external capacitor between
CAPandtheMOSFETdrain.Thisintegratingcapclosesthe
voltage feedback loop. The external resistor RVSL sets the
current for the integrator. The voltage slew rate is thus
inversely proportional to both the value of capacitor and
Internal slope compensation is provided to ensure stabil-
ity under high duty cycle conditions.
Output regulation is obtained using the error amp to set
the switch current trip point. The error amp is a
RVSL
.
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OPERATIO
The current slew feedback loop consists of the voltage
across the external sense resistor, which is internally
amplified and differentiated. The derivative is limited to a
value set by RCSL. The current slew rate is thus inversely
proportional to both the value of sense resistor and RCSL.
The voltage on GCL determines two features. The first is
the maximum gate drive voltage. This will protect the
MOSFET gate from overvoltage.
With GCL tied to a zener or an external voltage source then
the maximum gate driver voltage is approximately
VGCL – 0.2V. If GCL is tied to VIN, then the maximum gate
voltage is determined by VIN and is approximately
VIN – 1.6V. There is an internal 19V zener on the GCL pin
that prevents the gate driver pin from exceeding approxi-
mately 19V.
The two control loops are combined internally so that a
smooth transition from current slew control to voltage
slew control is obtained. When turning on, the driver
current will slew before voltage. When turning off, voltage
will slew before current. In general it is desirable to have
RVSL and RCSL of similar value.
In addition, the GCL voltage determines undervoltage
lockout of the gate drive. This feature disables the gate
driver if VIN is too low to provide adequate voltage to turn
ontheMOSFET.Thisishelpfulduringstartuptoinsurethe
MOSFET has sufficient gate drive to saturate.
Internal Regulator
Mostofthecontrolcircuitryoperatesfromaninternal2.4V
low dropout regulator that is powered from VIN. The
internal low dropout design allows VIN to vary from 2.7V
to 20V with stable operation of the controller. When SHDN
< 1.3V the internal regulator is completely disabled.
If GCL is tied to a voltage source or zener less than 6.8V,
the gate driver will not turn on until VIN exceeds GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drive is
insured to be off for VIN < 7.3V and it will be turned on by
VGCL + 0.8V.
5V Regulator
A 5V regulator is provided for powering external circuitry.
This regulator draws current from VIN and requires VIN to
be greater than 6.5V to be in regulation. It can sink or
source 10mA. The output is current limited to prevent
against destruction from accidental short circuits.
If GCL is tied to VIN, the gate driver is always on
(undervoltage lockout is disabled).
The gate drive has current limits for the drive currents. If
the sink or source current is greater than 300mA then the
current will be limited.
Safety and Protection Features
The V5 regulator also has internal current limiting that will
only guarantee ±10mA output current.
There are several safety and protection features on the
chip. Thefirstisovercurrentlimit. Normallythegatedriver
will go low when the output of the internal sense amplifier
exceeds the voltage on the VC pin. The VC pin is clamped
suchthatmaximumoutputcurrentisattainedwhentheCS
pin voltage is 0.1V. At that level the outputs will be
immediately turned off (no slew). The effect of this control
is that the output voltage will foldback with overcurrent.
There is also an on chip thermal shutdown circuit that will
turn off the output in the event the chip temperature rises
to dangerous levels. Thermal shutdown has hysteresis
thatwillcausealowfrequency(<1kHz)oscillationtooccur
as the chip heats up and cools down.
The chip has an undervoltage lockout feature that will
force the gate driver low in the event that VIN drops below
2.5V.Thisinsurespredictablebehaviorduringstartupand
shut down. SHDN can be used in conjuction with an
external resistor divider to completely disable the part if
the input voltage is too low. This can be used to insure
adequate voltage to reliably run the converter. See the
section in Applications Information.
In addition, if the CS voltage exceeds 0.22V, the VC and SS
pins will be discharged to ground, resetting the soft-start
function. Thus if a short is present this will allow for faster
MOSFET turnoff and less MOSFET stress.
If the voltage on the FB pin exceeds regulation by approxi-
mately 0.22V, the outputs will immediately go low. The
implication is that there is an overvoltage fault.
Table 1 summarizes these features.
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Table 1. Safety and Protection Features
FEATURE
FUNCTION
EFFECT on GATE DRIVER SLEW CONTROL EFFECT on V , SS
C
Maximum Current Fault
Turn Off FET at Maximum
Immediately Goes Low
Overridden
Overridden
Overridden
None
None
Switch Current (V
= 0.1)
SENSE
Short-Circuit Fault
Overvoltage Fault
GCL Clamp
Turn Off FET and Reset V
Immediately Goes Low
Discharge V , SS
to GND
C
C
for Short-Circuit (V
= 0.22)
SENSE
Turn Off Driver If FB > V
(Output Overvoltage)
+ 0.22V Immediately Goes Low
None
REG
Set Max Gate Voltage to Prevent
FET Gate Breakdown
Limits Max Voltage
None
None
None
Gate Drive
Undervoltage Lockout
Disable Gate Drive When V
Is Too Low. Set Via GCL Pin
Immediately Goes Low
Immediately Goes Low
Overridden
Overridden
IN
Thermal Shutdown
Turn Off Driver If Chip
Temperature Is Too Hot
V
Undervoltage Lockout
Disable Part When V
2.55V
Immediately Goes Low
Limit Drive Current
None
Overridden
None
None
None
None
IN
IN
Gate Drive Source and Sink Current Limit
V5 Source/Sink Current Limit
Shutdown
Limit Gate Drive Current
Limit Current from V5
None
Disable Part When SHDN <1.3V
U
W
U U
APPLICATIO S I FOR ATIO
Reducing EMI from switching power supplies has tradi-
tionally invoked fear in designers. Many switchers are
designed solely on efficiency and as such produce wave-
forms filled with high frequency harmonics that then
propagate through the rest of the system.
to ensure oscillator frequency stability. The oscillator is of
a sawtooth design. A current defined by external resistor
RT is used to charge and discharge the capacitor CT . The
discharge rate is approximately ten times the charge rate.
By allowing the user to have control over both compo-
nents, trimming of oscillator frequency can be more easily
achieved.
The LT1738 provides control over two of the more impor-
tant variables for controlling EMI with switching inductive
loads: switch voltage slew rate and switch current slew
rate. The use of this part will reduce noise and EMI over
conventional switch mode controllers. Because these
variablesareundercontrol,asupplybuiltwiththispartwill
exhibit far less tendency to create EMI and less chance of
encountering problems during production.
The external capacitance CT is chosen by:
2180
CT (nF) =
f(kHz)•RT (kΩ)
where f is the desired oscillator frequency in kHz. For RT
equal to 16.9k, this simplifies to:
It is beyond the scope of this data sheet to get into EMI
fundamentals. Application Note 70 contains much infor-
mation concerning noise in switching regulators and
should be consulted.
129
CT (nF) =
f(kHz)
e.g., CT = 1.29nF for f = 100kHz
Oscillator Frequency
Nominally RT should be 16.9k. Since it sets up current, its
temperature coefficient should be selected to compliment
the capacitor. Ideally, both should have low temperature
The oscillator determines the switching frequency and
therefore the fundamental positioning of all harmonics.
The use of good quality external components is important
coefficients.
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Oscillator frequency is important for noise reduction in
twoways.Firstthelowertheoscillatorfrequencythelower
the waveform’s harmonics, making it easier to filter them.
Second the oscillator will control the placement of the
output voltage harmonics which can aid in specific prob-
lems where you might be trying to avoid a certain fre-
quency bandwidth.
rates (longer slew times, lower rolloff frequency for har-
monics ) are created with higher values of RVSL, RCSL, CV
and the current sense resistor.
Setting the voltage and current slew rates should be done
empirically. The most practical way of determining these
components is to set CV and the sense resistor value.
Then, start by making RVSL, RCSL each a 50k resistor pot
in series with 3.3k. Starting from the lowest resistor
setting (fast slew) adjust the pots until the noise level
meets your guidelines. Note that slower slewing wave-
forms will dissipate more power so that efficiency will
drop. You can monitor this as you make your slew adjust-
ment by measuring input and output voltage and their
respective currents. Monitor the MOSFET temperature as
slew rates are slowed. The MOSFET will heat up as
efficiency decreases.
Oscillator Sync
If a more precise frequency is desired (e.g., to accurately
place harmonics) the oscillator can be synchronized to an
external clock. Set the RC timing components for an
oscillator frequency 10% lower than the desired sync
frequency.
Drive the SYNC pin with a square wave (with greater than
2V amplitude). The rising edge of the sync square wave
will initiate clock discharge. The sync pulse should have a
minimum pulse width of 0.5µs.
Measuring noise should be done carefully. It is easy to
introduce noise by poor measurement techniques. Con-
sult AN70 for recommended measurement techniques.
Keeping probe ground leads very short is essential.
Be careful in sync’ing to frequencies much different from
the part since the internal oscillator charge slope deter-
minesslopecompensation.Itwouldbepossibletogetinto
subharmonic oscillation if the sync doesn’t allow for the
charge cycle of the capacitor to initiate slope compensa-
tion. In general, this will not be a problem until the sync
frequency is greater than 1.5 times the oscillator free-run
frequency.
Usually it will be desirable to keep the voltage and current
slew resistors approximately the same. There are circum-
stances where a better optimization can be found by
adjusting each separately, but as these values are sepa-
ratedfurther,alossofindependenceofcontrolmayoccur.
It is possible to use a single slew setting resistor. In this
case the RVSL and RCSL pins are tied together. A resistor
with a value of 1.8k to 34k (one half the individual resis-
tors) can then be tied from these pins to ground.
Slew Rate Setting
The primary reason to use this part is to gain advantage of
lower EMI and noise due to the slew control. The rolloff in
higher frequency harmonics has its theoretical basis with
two primary components. First, the clock frequency sets
thefundamentalpositioningofharmonicsandsecond,the
associated normal frequency rolloff of harmonics.
In general only the RCSL value will be available for adjust-
ment of current slew. The current slew time also depends
on the current sense resistor but this resistor is normally
set with consideration of the maximum current in the
MOSFET.
This part creates a second higher frequency rolloff of
harmonics that inversely depends on the slew time, the
time that voltage or current spends between the off state
and on state. This time is adjustable through the choice of
the slew resistors, the external resistors to ground on the
Setting the voltage slew also involves selection of the
capacitor CV. The voltage slew time is proportional to the
outputvoltageswing(basicallyinputvoltage),theexternal
voltage feedback capacitor and the RVSL value. Thus at
higher input voltages smaller capacitors will be used with
lower RVSL values. For a starting point use Table 2.
RVSL and RCSL pins and the external components used for
the external voltage feedback capacitor CV (from CAP to
the MOSFET drain) and the sense resistor. Lower slew
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R1
Table 2
V
OUT
FB PIN
INPUT VOLTAGE
< 25V
CAPACITOR VALUE
R2
5pF
2.5pF
1pF
1738 F03
50V
100V
Figure 3
Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 • C2)/(C1 + C2).
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V.ThenominalinputbiascurrentfortheNFBis–25µA
(INFB), which needs to be accounted for in setting up the
divider.
The second method makes use of a capacitor divider. Care
should be taken that the voltage rating of the capacitor
satisfies the full voltage swing thus essentially the same
rating as the MOSFET.
Referring to Figure 4, R1 is chosen such that:
The equivalent slew capacitance for Figure 2 is
(C1 • C2)/(C1 + C2 + C3).
VOUT − 2.5
R1= R2
MOSFET DRAIN
2.5 +R2•25µA
C2
C1
CAP
A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.
C3
1738 F02
R1
–V
Figure 2
NFB PIN
OUT
I
NFB
R2
Positive Output Voltage Setting
1738 F04
Sensing of a positive output voltage is usually done using
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a
1.25V bandgap reference. The FB pin will regulate to this
voltage.
Figure 4
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both posi-
tive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previ-
ously described. When both FB and NFB pins are used, the
LT1738 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load)willdominatecontroloftheregulator.Thistechnique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Referring to Figure 3, R1 is determined by:
VOUT
1.25
R1= R2
−1
The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.
One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If the
feedback capacitively pulls the FB pin above the internal
regulator voltage (2.4V), output regulation may be dis-
rupted. A series resistance with the feedback pin can
eliminatethispotentialproblem.Thereisaninternalclamp
onFBthatclampsat0.7Vabovetheregulationvoltagethat
should also help prevent this problem.
Shutdown
If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgapregulatorwillbepoweredon.Thiswillseta1.39V
threshold for turn on of the internal regulator that runs
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mostofthecontrolcircuitryoftheregulator. Noteafterthe
controlcircuitrypowerson,gatedriveractivitywilldepend
on the voltage of VIN with respect to the voltage on GCL.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(VC pin).
As the SHDN pin enables the internal regulator a 24µA
current will be sourced from the pin that can provide
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage sag
from an initial high current draw.
V
PIN
C
R
VC
2k
C
VC2
4.7nF
C
VC
0.01µF
1738 F05
In addition to the current hysteresis, there is also approxi-
mately 100mV of voltage hysteresis on the SHDN pin.
Figure 5
When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.
Referring to Figure 5, the main pole is formed by capacitor
CVC and the output impedance of the error amplifier
(approximately 400kΩ). The series resistor RVC creates a
“zero” which improves loop stability and transient re-
sponse. A second capacitor CVC2, typically one-tenth the
size of the main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the VC
pin. VC pin ripple is caused by output voltage ripple
attenuatedbytheoutputdividerandmultipliedbytheerror
amplifier. Without the second capacitor, VC pin ripple is:
Ifaresistordividerisusedtosettheturnonthresholdthen
the resistors are determined by the following equations:
RA + RB
V
IN
VON
=
•VSHDN
RB
RA
RB
SHDN
∆VSHDN
RA RB
VHYST = RA •
+ ISHDN
Reworking these equations yields:
1.25•VRIPPLE •gm•RVC
V
HYST •VSHDN − VON • ∆VSHDN
VCPINRIPPLE
=
(
(
)
)
RA =
RB =
VOUT
where VRIPPLE = Output ripple (VP-P
I
SHDN •VSHDN
(
)
)
VHYST •VSHDN − VON • ∆VSHDN
gm = Error amplifier transconductance
RVC = Series resistor on VC pin
VOUT = DC output voltage
I
• VON − VSHDN
(
)
]
[
SHDN
So if we wanted to turn on at 20V with 2V of hysteresis:
To prevent irregular switching, VC pin ripple should be
kept below 50mVP-P . Worst-case VC pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor for CVC2 pin reduces
switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
2V •1.39V − 20V •0.1V
RA =
RB =
= 23.4k
= 1.75k
24µA •1.39V
2V •1.39V − 20V •0.1V
24µA • 20V −1.39V
(
)
Resistor values could be altered further by adding zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
voltage.
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Setting Current Limit
The soft-start current will be initiated as soon as the part
turns on. Soft-start will be reinititated after a short-circuit
fault.
The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate driver
will immediately go low (no slew control). Therefore the
Thermal Considerations
sense resistor value should be set to RS = 0.1V/ISW(PEAK)
,
Most of the IC power dissipation is derived from the VIN
pin. The VIN current depends on a number of factors
including:oscillatorfrequency;loadsonV5;slewsettings;
gate charge current. Additional power is dissipated if V5
sinks current and during the MOSFET gate discharge.
where ISW(PEAK) is the peak current in the MOSFET.
ISW(PEAK) will depend on the topology and component
values and tolerances. Certainly it should be set below the
saturation current value for the inductor.
If the CS pin voltage is 0.22V in addition to the driver going
low, VC and SS will be discharged to ground. This is to
provideadditionalprotectionintheeventofashortcircuit.
BydischargingVC andSStheMOSFETwillnotbestressed
as hard on subsequent cycles since the current trip will be
set lower.
The power dissipation in the IC will be the sum of:
1) The RMS VIN current times VIN
2) V5 RMS sink current times 5V
3) The gate drive’s RMS discharge current times voltage.
TurnoffoftheMOSFETwillnormallybeinhibitedforabout
100ns at the start of every turn on cycle. This is to prevent
noisefrominterferingwithnormaloperationofthecontrol-
ler. This current sense blanking does not prevent the out-
puts from being turned off in the event of a fault. Slewing
ofthegatevoltageeffectivelyprovidesadditionalblanking.
Because of the strong VIN component it is advantageous
to operate the LT1738 at as low a VIN as possible.
It is always recommended that package temperature be
measured in each application. The part has an internal
thermal shutdown to minimize the chance of IC destruc-
tion but this should not replace careful thermal design.
TracestotheSENSEresistorshouldbekeptshortandwide
tominimizeresistanceandinductance.Largeinterwinding
capacitance in the transformer or high capacitance on the
drain of the MOSFET will produce a current pulse through
the sense resistor during drain voltage slewing. The mag-
nitude of the pulse is C • dV/dt where C is the capacitance
anddV/dtisthevoltageslewratewhichiscontrolledbythe
part. This pulse will increase the sensed current on switch
turn on and if large enough can cause premature MOSFET
turn off. If this occurs, the inductor transformer may need
a different winding technique (see AN39) or alternatively,
a blanking circuit can be used. Please contact the LTC ap-
plications group for support if required.
The thermal shutdown feature does not protect the exter-
nal MOSFET. A separate analysis must be done for this
device to insure that it is operating within safe limits.
Once IC power dissipation, PDIS, is determined die junc-
tion temperature is then computed as:
TJ = TAMB + PDIS • θJA
whereTAMB isambienttemperatureandθJAisthepackage
thermal resistance. For the 20-pin SSOP, θJA is 100°C/W.
Choosing The Inductor
For a boost converter, inductor selection involves trade-
offs of size, maximum output power, transient response
and filtering characteristics. Higher inductor values pro-
vide more output power and lower input ripple. However,
they are physically larger and can impede transient re-
sponse. Low inductor values have high magnetizing cur-
rent, which can reduce maximum power and increase
input current ripple.
Soft-Start
The soft-start pin is used to provide control of switching
current during startup. The maximum voltage on the VC
pin is approximately the voltage on the SS pin. A current
source will linearly charge a capacitor on the SS pin. The
VC pin voltage will thus ramp up also. The approximate
time for the voltage on these pins to ramp up is
(1.31V/9µA) • CSS or approximately 146ms per µF.
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The following procedure can be used to handle these
trade-offs:
Capacitors
Correct choice of input and output capacitors can be very
important to low noise switcher performance. Noise de-
pendsmoreontheESRofthecapacitors.Inadditionlower
ESR can also improve efficiency.
1. Assume that the average inductor current for a boost
converter is equal to load current times VOUT/VIN and
decide whether the inductor must withstand continu-
ous overload conditions. If average inductor current at
maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 1.5A overload
condition. Also be aware that boost converters are not
short-circuit protected, and under output short condi-
tions, only the available current of the input supply
limits inductor current.
Input capacitors must also withstand surges that occur
during the switching of some types of loads. Some solid
tantalum capacitors can fail under these surge conditions.
Design Note 95 offers more information but the following
is a brief summary of capacitor types and attributes.
Aluminum Electrolytic: Low cost and higher voltage. They
will typically only be used for higher voltage applications.
Large values will be needed for low ESR.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, espe-
cially with smaller inductors and lighter loads, so don’t
omit this step. Powdered iron cores are forgiving
becausetheysaturatesoftly,whereasferritecoressatu-
rate abruptly. Other core materials fall in between. The
following formula assumes continuous mode opera-
tion but it errs only slightly on the high side for discon-
tinuous mode, so it can be used for all conditions.
Specialty Polymer Aluminum: Panasonic has come out
with their series CD capacitors. While they are only avail-
able for voltages below 16V, they have very low ESR and
good surge capability.
Solid Tantalum: Small size and low impedance. Typically
the maximum voltage rating is 50V. With large surge
currents the capacitor may need to be derated or you need
a special type such as the AVX TPS line.
V V
2•L• f •VOUT
– V
IN
VOUT
V
IN
(
)
IN OUT
OS-CON: Lower impedance than aluminum but only avail-
able for 35V or less. Form factor may be a problem.
IPEAK = IOUT
+
Ceramic: Generally used for high frequency and high
voltage bypass. They may resonate with their ESL before
ESRbecomesdominant.Recentmultilayerceramic(MLC)
capacitors provide larger capacitance with low ESR.
L = inductance value
VIN = supply voltage
VOUT = output voltage
I = output current
There are continuous improvements being made in ca-
pacitors so consult with manufacturers as to your specific
needs.
f = oscillator frequency
3. Choose a core geometry. For low EMI problems a
closed structure should be used such as a pot core, ER
core or toroid (see AN70 appendix I).
Input Capacitors
4. Select an inductor that can handle peak current,
average current (heating effects) and fault current.
The input capacitor should have low ESR at high frequen-
cies since this will be an important factor concerning how
much conducted noise is generated.
5. Finally, double check output voltage ripple.
There are two separate requirements for input capacitors.
The first is for the supply to the part’s VIN pin. The VIN pin
will provide current for the part itself and the gate charge
current.
The experts in the Linear Technology Applications depart-
ment have experience with a wide range of inductor types
and can assist you in making a good choice.
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16
LT1738
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APPLICATIO S I FOR ATIO
The worst component from an AC point is the gate charge
current. The actual peak current depends on gate capaci-
tance and slew rate, being higher for larger values of each.
The total current can be estimated by gate charge and
frequency of operation. Because of the slewing with this
part gate charge is spread out over a longer time period
than with a normal FET driver. This reduces capacitance
requirements.
low to reduce capacitor dissipation. Typically ESR should
be below 0.05Ω.
The capacitance value can be computed by consideration
of desired load ripple, duty cycle and ESR.
1
DCMIN
f
COUT
=
•
∆VOUT
∆IL(MAX)
− ESR
Typically the current will have spikes of under 100mA
located at the gate voltage transitions. This is charge/
dischargetoandfromthethresholdvoltage. Mostslewing
occurs with the gate voltage near threshold.
MOSFET Selection
There is a wide variety of MOSFETs to choose from for this
part. Thepartwillworkwitheithernormalthreshold(3Vto
4V) or logic level threshold devices (1V to 2V).
Since the part’s VIN will typically be under 15V many
options are available for choice of capacitor. Values of
inputcapacitorforjusttheVIN requirementwilltypicallybe
in the 50µF range with an ESR of under 0.1Ω.
Select a voltage rating to insure under worst-case condi-
tionsthattheMOSFETwillnotbreakdown.Nextchoosean
RON sufficiently low to meet both the power dissipation
capabilities of the MOSFET package as well as overall
efficiency needs of the converter.
In addition to the part’s supply, decoupling of the supply
to the inductor needs to be considered. If this is the same
supply as the VIN pin then that capacitor will need to be
increased. However, often with this part the inductor
supply will be a higher voltage and as such will use a
separate capacitor.
The LT1738 can handle a large range of gate charges.
However at very large charge stability may be affected.
The power dissipation in the MOSFET depends on several
factors. The primary element is I2R heating when the
device is on. In addition, power is dissipated when the
device is slewing. An estimate for power dissipation is:
The inductor’s decoupling capacitor will see the switch
current as ripple.
The above switch current computation can be used to
estimate the capacity for these capacitors.
3 • ∆I2
2
V
IN
2 −RON • I2 +
∆I2
I2 +
4
1
DCMIN
f
4
CIN =
•
P = V •
+
•I
IN
∆VCAP
∆ISW(MAX)
ISR
VSR
− ESR
• f +I2 •RON •DC
where ∆VCAP is the allowed sag on the input capacitor.
ESR is the equivalent series resistance for the cap. In
general allowed sag will be a few tenths of a volt.
whereIistheaveragecurrent,∆Iistheripplecurrentinthe
switch, ISR is the current slew rate, VSR is the voltage slew
rate, f is the oscillator frequency, DC is the duty cycle and
Output Filter Capacitor
R
ON is the MOSFET on-resistance.
The output capacitor is chosen both for capacity and ESR.
The capacity must supply the load current in the switch on
state. While slew control reduces higher frequency com-
ponentsoftheripplecurrentinthecapacitor, thecapacitor
ESR and the magnitude of the output ripple current
controls the fundamental component. ESR should also be
Setting GCL Voltage
Setting the voltage on the GCL pin depends on what type
of MOSFET is used and the desired gate drive undervolt-
age lockout voltage.
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17
LT1738
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APPLICATIO S I FOR ATIO
First determine the maximum gate drive that you require.
Typically you will want it to be at least 2V greater than the
rated threshold. Higher voltages will lower the on resis-
tance and increase efficiency. Be certain to check the
maximum allowed gate voltage. Often this is 20V but for
some logic threshold MOSFETs it is only 8V to 10V.
The gate drive source current comes from VIN. The sink
currentexitsthroughPGND.Ingeneralthedecouplingcap
should be placed close to these two pins.
Switching Diodes
In general, switching diodes should be Schottky diodes.
Size and breakdown voltage depend on the specific con-
verter. A lower forward drop will improve converter effi-
ciency. No other special requirements are needed.
V
GCL needstobesetapproximately0.2Vabovethedesired
max gate threshold. In addition VIN needs to be at least
1.6V above the gate voltage.
The GCL pin can be tied to VIN which will result in a
maximum gate voltage of VIN – 1.6V.
PCB LAYOUT CONSIDERATIONS
Aswithanyswitcher,carefulconsiderationshouldbegiven
to PC board layout. Because this part reduces high fre-
quencyEMI,theboardlayoutislesscritical.However,high
currents and voltages still produce the need for careful
board layout to eliminate poor and erratic performance.
This pin also controls undervoltage lockout of the gate
drive. The undervoltage lockout will prevent the MOSFET
from switching until there is sufficient drive present.
If GCL is tied to a voltage source or zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds the GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drive is
insured to be off for VIN < 7.3V and they will be turned on
by VGCL + 0.8V.
Basic Considerations
Keep the high current loops physically small in area. The
main loops are shown in Figure 6: the power switch loops
(A)andtherectifierloop(B).Theseloopscanbekeptsmall
by physically keeping the components close to one an-
other. In addition, connection traces should be kept wide
to lower resistance and inductances. Components should
be placed to minimize connecting paths. Careful attention
to ground connections must also be maintained. Be care-
ful that currents from different high current loops do not
get coupled into the ground paths of other loops. Using
singular points of connection for the grounds is the best
way to do this. The two major points of connection are the
bottom of the input decoupling capacitor and the bottom
of the output decoupling capacitor. Typically, the sense
resistordevicePGNDanddeviceGNDwilltietothebottom
of the input capacitor.
If GCL is tied to VIN, the gate driver is always on
(undervoltage lockout is disabled).
Approximately 50µA of current can be sourced from this
pin if VIN > VGCL + 0.8V. This could be used to bias a zener.
The GCL pin has an internal 19V zener to ground that will
provide a failsafe for maximum gate voltage.
As an example say we are using a Siliconix Si4480DY
which has RDS(ON) rated at 6V. To get 6V, VGCL needs to
be set to 6.2V and VIN needs to be at least 7.6V.
Gate Driver Considerations
In general, the MOSFET should be positioned as close to
the part as possible to minimize inductance.
V
IN
•
When the part is active the gate drive will be pulled low to
lessthan0.2V. Whenthepartisoff, thegatedrivecontains
a40kresistorinserieswithadiodetogroundthatwilloffer
passive holdoff protection. If you are using some logic
level MOSFETs this might not be sufficient. A resistor may
be placed from gate to ground, however the value should
bereasonablyhightominimizeDClossesandpossibleAC
issues.
C
C
V
OUT OUT
IN
A
B
•
GATE
CS
1738 F06
Figure 6
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18
LT1738
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APPLICATIO S I FOR ATIO
There are two other loops to pay attention to. The current
slew involves a high bandwidth control that goes through
the MOSFET switch, the sense resistor and into the CS pin
of the part and out the GATE pin to the MOSFET. Trace
inductanceandresistanceshouldbekeptlowontheGATE
drive trace. The CS trace should have low inductance.
MORE HELP
AN70 contains information about low noise switchers and
measurementofnoiseandshouldbeconsulted.AN19and
AN29 also have general knowledge concerning switching
regulators. Also, our Application Department is always
ready to lend a helping hand.
Finally, careshouldbetakenwiththeCAPpin. Thepartwill
tolerate stray capacitance to ground on this pin (<5pFs).
However, stray capacitance to the MOSFET drain should
be minimized. This path would provide an alternate ca-
pacitive path for the voltage slew.
U
PACKAGE DESCRIPTIO
G Package
20-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
6.90 – 7.50*
(.272 – .295 )
1.25 ±0.12
20 19 18 17 16 15 14 13 12 11
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
8
1
2
3
4
6
9 10
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
(.002)
NOTE:
G20 SSOP 0802
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1738fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1738
U
TYPICAL APPLICATIO
Ultralow Noise 30W Offline Power Supply
DANGER: HIGH VOLTAGE
L1
X1
+
100µF
P6KE200A
1M
D1
+V
T1
400V
OUT
11
A1
0.1µF
1
90VAC
250VAC
TO 264VAC
“X2”
BR1
12V
2.5A
A2
MUR160
1M
+
C3
330µF
25V
K
A
7
12
3
6
X3
C4
+
+
C2
100k
V
BIAS
330µF
330µF
2W
10Ω
D4
BA521
25V
25V
5
8
–V
OUT
+
12V
IN755 A
17
V
IN
19
NC
10
NFB
56µF
35V
5pF
600V
510k
470pF
5pF
14
5
SHDN
V5
510k
6
2
SYNC
CAP
1.8nF
7
1
C
T
GATE
CS
MTP2N60E
U3
LT1738
0.1µF
1k
165k
165k
V
8
4
OUT
R
R
R
F
T
19.6k
3.9k
3.9k
1k
2
0.068Ω
16
15
9
18
20
12
ISO1
CNY17-3
3
2N2222
NC
0.22µF
1/2W
VSL
CSL
38.3k
1%
1
2
3
PGND
6
5
+
COMP
REF
V
1k
8
4
7
U2
V
C
LT1431
COLL
B
R
TOP
GCL
GND
11
10nF
SS
13
10k
1%
2N2222
RMIO
G-S
5
3
4
G-F
6
51k
V
BIAS
1738 TA02
UNLESS OTHERWISE NOTED: ALL RESISTORS 1206, 5%
BR1: GENERAL INSTRUMENTS W06G
C2, C3, C4: SANYO MV-GX
NOTE: PIN 2 OF LT1738 MUST BE LAID OUT
AWAY FROM FAST SLEWING NODES
D1: MBR20200CT
L1: HM18-10001
T1: PREMIER MAGNETICS POL-15033
INPUT FILTER IS REQUIRED TO ATTENUATE SWITCHING FREQUENCY HARMONICS AND PASS FCC CLASS B (LT1738 DOES NOT ATTENUATE THESE LOW FREQUENCY HARMONICS)
MAIN ADVANTAGE WITH LT1738 IS IT MAKES SUPPRESSING THE HIGH FREQUENCY NOISE AND EMI EASY. THIS IS PARTICULARLY USEFUL FOR MEDICAL DEVICES BECAUSE
THE AC LINE TO EARTH GND CAPS ON THE INPUT FILTER CAN BE ELIMINATED; ALLOWING THE DEVICE TO PASS THE EARTH GND LEAKAGE CURRENT MEDICAL SPECIFICATIONS.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1683
Ultralow Noise Push-Pull DC/DC Controller
Isolated Flyback Switching Regulator
Ultralow Noise 1A Switching Regulator
Ultralow Noise 2A Switching Regulator
1.5A, 200kHz Step-Down Switching Regulator
Low Dropout, Low Noise Linear Regulator
Low Noise Step-Down Switching Regulator
Synchronous Phase Modulated Full-Bridge Controller
Dual Output (Push-Pull) Current Mode Architecture.
LT1425
Excellent Regulation without Transformer “Third Winding”
Push-Pull Design for Low Noise Isolated Supplies
Ultralow Noise Regulator for Boost Topologies
Constant Frequency, 1.21V Reference Voltage
150mA to 3A, SOT-23 to TO-220
LT1533
LT1534
LT1576
LT176X Family
LT1777
Programmable dI/dt; Internally Limited dV/dt
Adaptive DirectSenseTM Zero Voltage Switching, 50W to
Kilowatts, Synchronous Rectification
LTC1922-1
LT3439
Ultralow Noise Transformer Driver
1A Push-Pull DC/DC Transformer Driver
DirectSense is a trademark of Linear Technology Corporation.
1738fa
LT/TP 1202 1K REV A • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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