LT3582-12
更新时间:2024-09-18 07:32:38
品牌:Linear
描述:I2C Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP
LT3582-12 概述
I2C Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP I2C可编程升压和单电感输出DC / DC与OTP转换器
LT3582-12 数据手册
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PDF下载LT3582/LT3582-5/LT3582-12
2
I C Programmable Boost
and Single Inductor Inverting
DC/DC Converters with OTP
DESCRIPTION
FEATURES
TheLT®3582/LT3582-5/LT3582-12aredualDC/DCconvert-
ers featuring positive and negative outputs and integrated
feedback resistors. The LT3582, with its built in One Time
Programming (OTP), has configurable output settings via
n
Output Voltages:
3.2V to 12.775V and –1.2V to –13.95V (LT3582)
5V and –5V (LT3582-5)
12V and –12V (LT3582-12)
2
2
n
Digitally Re-Programmable (LT3582) Via I C for:
Output Voltages
the I C interface, including output voltage settings, power
upsequencing,powerdowndischarge,andoutputvoltage
ramp rates. LT3582 settings can be changed adaptively in
the final product, or set during manufacturing and made
permanent using the built in non-volatile OTP memory.
The positive output voltage can be set between 3.2V and
12.775V in 25mV steps. The negative output voltage can
be set between –1.2V and –13.95V in –50mV steps. The
LT3582-5andLT3582-12arepre-configuredatthefactory
for 5V and 12V outputs respectively.
Power Sequencing
Output Voltage Ramp Rates
Power-up Defaults Settable with Non-volatile OTP
(LT3582)
n
2
n
n
I C Compatible Interface (Standard Mode*)
All Power Switches Integrated
350mA Current Limit (Boost)
600mA Current Limit (Inverting)
All Feedback Resistors Integrated
Input Voltage Range: 2.55V to 5.5V
Low Quiescent Current
n
n
n
The LT3582 series includes two monolithic converters,
one Boost and one Inverting. The Boost converter has an
integrated power switch and output disconnect switch.
The Inverting converter uses a single inductor topology
and includes an integrated power switch. Both Boost and
Inverting converters use a novel** control scheme result-
ing in low output voltage ripple while allowing for high
conversion efficiency over a wide load current range. The
LT3582 series is available in a 16-pin 3mm x 3mm QFN.
325μA in Active Mode
0.01μA in Shutdown Mode
Integrated Output Disconnect
Tiny 16-pin 3mm × 3mm QFN Package
n
n
APPLICATIONS
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
* Input thresholds are reduced to allow communication with low voltage digital ICs.
(See Electrical Characteristics).
AMOLED Power
n
CCD Power
n
General Purpose DC/DC Conversion
**Patent Pending
TYPICAL APPLICATION
12V Supplies from a Single 5V Input
Efficiency and Power Loss
350
300
250
200
150
100
95
85
75
65
55
45
35
SWN
SWN
SHDN
V
V
OUTP
OUTN
INPUT
V
IN
4.5V TO 5.5V
6.8ꢀH
SWP
6.8ꢀH
1ꢀF
GND
4.7ꢀF
LT3582
10ꢀF
V
CAPP
CAPP
NEG
–12V
V
OUTN
85mA
V
POS
SDA
SCL
CA
12V
V
OUTP
2
I C
80mA
50
0
V
PP
INTERFACE
4.7ꢀF
RAMPP RAMPN
OPTIONAL ON
LT3582-5/LT3582-12
0.1
1
10
100
(
)
10nF
10nF
LOAD CURRENT (mA)
3582512 TA01b
3582512 TA01a
3582512f
1
LT3582/LT3582-5/LT3582-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V Voltage..................................................................6V
IN
SWP Voltage.............................................................15V
SWN Voltage........................................................–16.5V
CAPP Voltage............................................................15V
16 15 14 13
CA
1
2
3
4
12 SWP
11 CAPP
V
OUTN
17
GND
CAPP-V
Voltage.................................... –0.8V to 8V
OUTP
SWN
CAPP
10
9
I
V
V
........................................................ 300mA
SWN
V
OUTP
CAPP-VOUTP
Voltage ...........................................................15V
5
6
7
8
OUTP
Voltage ......................................................–16.5V
OUTN
RAMPP Voltage...........................................................3V
RAMPN Voltage ..........................................................3V
SHDN Voltage .................................................–0.5 to 6V
UD PACKAGE
16-PIN (3mm × 3mm) PLASTIC QFN
T
= 125°C, θ = 68°C/W
JA
JMAX
EXPOSED PAD (PIN #17) IS GND, MUST BE SOLDERED TO PCB
V
Voltage...................................................–0.2 to 16V
PP
SDA, CA, SCL Voltage.....................................–0.5 to 6V
Operating Junction Temperature Range (Notes 3, 5)
LT3582E............................................. –40°C to 125°C
Storage Temperature Range .............. –65°C to 150°C
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
LDDB
PACKAGE DESCRIPTION
16-Pin (3mm × 3mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
LT3582EUD#PBF
LT3582EUD#TRPBF
LT3582EUD-5#TRPBF
LT3582EUD-12#TRPBF
LT3582EUD-5#PBF
LT3582EUD-12#PBF
LDVG
16-Pin (3mm × 3mm) Plastic QFN
16-Pin (3mm × 3mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
LDVH
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
2.4
TYP
MAX
UNITS
l
l
V
V
Minimum Operating Voltage
Maximum Operating Voltage
2.475
2.55
V
V
IN_MIN
IN_MAX
VIN
5.5
I
V
Quiescent Current
Ramp Current Configured to 1μA,
SWOFF Bit Active
325
450
ꢀA
IN
I
I
V
Quiescent Current in Shutdown
V
V
= 0
0.01
0
0.5
0.5
ꢀA
ꢀA
VIN_SHDN
IN
SHDN
SHDN
CAPP Quiescent Current in Shutdown
Minimum Switch Off Time
Minimum Switch Off Time
Maximum Switch On Time
Boost Switch Current Limit
= 0, V
= 5.0V, V
= 0V
OUTP
CAPP_SHDN
CAPP
T
T
T
Boost Switch
100
125
10
ns
OFF_MINP
OFF_MINN
ON_MAX
LIMIT_P
Inverting Switch
ns
Inverting and Boost Switches
ꢀs
l
I
285
350
430
mA
3582512f
2
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
600
500
560
0.01
MAX
UNITS
mA
l
I
Inverting Switch Current Limit
Boost Switch On Resistance
Inverting Switch On Resistance
490
720
LIMIT_N
R
R
I
I
= 200mA
= –400mA
= 5V
mΩ
mΩ
ꢀA
ON_P
ON_N
OFF_P
SWP
SWN
I
Boost Switch Leakage Current into
SWP pin
V
V
V
0.5
1
SWP
I
Inverting Switch Leakage Current out
of SWN pin
= 5.0, V = 0.0
SWN
0.01
1.4
ꢀA
Ω
OFF_N
IN
R
Output Disconnect Switch On
Resistance
= 10V, RAMPP > 1.4V
ON_DIS
CAPP
l
I
I
Output Disconnect Current Limit
124
2.4
155
4.8
186
8.8
mA
mA
LIMIT_DIS
V
Power-Down Discharge
V
= 8V
VOUTP_PDS
OUTP
OUTP
Current
I
I
CAPP Power-Down Discharge
Current
CAPP = 8V
1.2
2.4
–2.8
64
4.4
–4.2
128
mA
mA
μs
CAPP_PDS
V
Power-Down Discharge
V
= –8V
OUTN
–1.4
VOUTN_PDS
OUTN
Current
2
l
T
Configuration Startup Delay
V
> V
& SHDN > V
to I C
SHDN_VIH
STARTUP
IN
IN_MIN
Enabled and Power-up Sequencing Start
Programmable Output Characteristics6
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Positive Output Voltage
LT3582-5
LT3582-12
4.95
11.88
5
12
5.05
12.1
V
V
VOUTP
2
N_V
Positive V
Resolution
9
Bits
mV
V
OUTP
OUTP
2
V
V
V
V
V
V
V
V
V
LSB
25
VOUTP_LSB
VOUTP_FS
VOUTP_MIN
VOUTP_LR
VOUTN
OUTP
OUTP
OUTP
OUTP
2
l
l
Full Scale Voltage
Minimum Voltage
Line Regulation
Code = BFh, V
Code = 00h, V
= 1
= 0
12.56
3.152
12.775
3.20
12.94
3.248
PLUS
PLUS
2
V
Code = BFh, 2.575 < V < 5.5
–0.02
%/V
IN
l
l
Negative Output Voltage
LT3582-5
LT3582-12
–5.075
–12.1
–5
–12
–4.925
–11.868
V
V
2
N_V
Negative V
Resolution
8
Bits
mV
V
OUTN
OUTN
2
V
V
V
V
V
V
V
V
V
V
V
V
LSB
–50
VOUTN_LSB
VOUTN_FS
VOUTN_MIN
VOUTN_LR
OUTN
OUTN
OUTN
OUTN
OUTP
OUTP
OUTN
OUTN
2
l
l
Full Scale Voltage
Minimum Voltage
Line Regulation
Code = FFh
Code = 00h
–14.2
–1.23
–13.95
–1.205
–0.01
–13.7
–1.18
2
V
Code = FFh, 2.575 < V < 5.5
%/V
LSB
LSB
LSB
LSB
ꢀA
IN
2, 4
l
l
l
l
l
INL_V
Integral Nonlinearity
0.6
0.6
OUTP
2, 4
2
DNL_V
Differential Nonlinearity
OUTP
OUTN
2
INL_V
Integral Nonlinearity
0.85
0.85
1.3
DNL_V
Differential Nonlinearity
OUTN
RAMP00
I
I
RAMPP/RAMPN Pull Up Current
IRMP Code = 00
V
V
= 0.0V
= 0.0V
0.7
1.4
1.0
2.0
RAMPP
RAMPN
2
l
RAMPP/RAMPN Pull Up Current
IRMP Code = 01
V
V
= 0.0V
= 0.0V
2.6
ꢀA
RAMP01
RAMPP
RAMPN
3582512f
3
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Programmable Output Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
2
l
l
I
RAMPP/RAMPN Pull Up Current
IRMP Code = 10
V
V
= 0.0V
= 0.0V
2.8
4.0
5.2
ꢀA
RAMP10
RAMPP
RAMPN
I
RAMPP/RAMPN Pull Up Current
IRMP Code = 11
V
V
= 0.0V
= 0.0V
5.6
8.0
25
10.4
ꢀA
RAMP11
RAMPP
RAMPN
V
V
Voltage Increase When V
mV
VPLUS
OUTP
PLUS
2
Bit is Set from 0 to 1
Input/Output Pin Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.3
UNITS
V
l
l
V
V
V
SHDN Input Voltage High
SHDN Input Voltage Low
SHDN Input Hysteresis
SHDN Pin Bias Current
CA Input Voltage High
CA Input Voltage Low
SDA Input Voltage High
SDA Input Voltage Low
SCL Input Voltage High
SCL Input Voltage Low
Input Hysteresis
1.1
SHDN_VIH
SHDN_VIL
V
50
mV
ꢀA
V
HYST_SHDN
SHDN_BIAS
I
V
= 1V
2.5
4.5
6.5
SHDN
l
l
l
l
l
l
V
V
V
V
V
V
V
0.7 × V
CA_VIH
CA_VIL
IN
0.3 × V
0.85
0.85
V
IN
1.25
1.25
V
SDA_VIH
SDA_VIL
SCL_VIH
SCL_VIL
HYST
V
V
V
SDA, SCL Pins
CA = 0V & 5.5V
SCL = 0V & 5.5V
SDA = 0V & 5.5V
SDA, SCL Pins
3mA into SDA Pin
80
3
mV
ꢀA
ꢀA
ꢀA
pF
V
l
l
l
I
I
I
CA Input Leakage Current
SCL Input Leakage Current
SDA Input Leakage Current
Input Capacitance
1
1
1
LEAK_CA
LEAK_SCL
LEAK_SDA
C
V
V
V
IN
l
l
SDA Output Low Voltage
0.4
15
SDA_OL
PP_RANGE
PPUVLO
2
V
Voltage Range for OTP Write
13
V
PP
2
Under-voltage Lockout for V Pin
12.05
12.45
12.85
V
PP
I2C Timing Characteristics
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
ꢀs
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
Serial Clock Frequency
Serial Clock Low Period
Serial Clock High Period
100
SCL
4.7
4.0
4.7
4.0
4.7
4.0
300
LOW
ꢀs
HIGH
Bus Free Time Between Stop and Start
Start Condition Hold Time
ꢀs
BUF
ꢀs
HD,STA
SU,STA
SU,STO
HD,DATXMIT
Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time Transmitting
ꢀs
ꢀs
LT3582 Sending Data to Host
ns
3582512f
4
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
I2C Timing Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
l
l
l
t
t
t
Data Hold Time Receiving
Data Setup Time
SDA Fall Time
LT3582 Receiving Data from Host
HD,DATRCV
250
ns
SU,DAT
F
400pF load, V ≥ 2.5V
250
ns
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: This IC includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when over-temperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair
device reliability.
Note 2: LT3582 only.
Note 3: The LT3582E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlations with statistical process controls.
Note 6: Output voltage is measured under non-switching test conditions
approximating a moderate load current from the output.
Note 4: These specifications apply to the V trim bits in REG0 using
P
a 50mV LSB and do not include the additional V
trim bit. See
PLUS
Registers and OTP in the Applications Information section.
3582512f
5
LT3582/LT3582-5/LT3582-12
TA = 25°C unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequencies (Figure 13)
Load Regulation (Figure 13)
Output Voltage (Figure 13)
10000
1000
100
1.00
0.75
0.50
0.25
0
0.45
0.30
0.15
V
OUTP
V
OUTN
V
V
OUTP
0
–0.15
–0.30
–0.45
V
OUTN
OUTP
–0.25
–0.50
–0.75
–1.00
V
OUTN
10
0
20
40
60
80
100
0
20
40
60
80
100
–50 –25
0
25
50
75
100 125
LOAD CURRENT (mA)
LOAD CURRENT (mA)
TEMPERATURE (°C)
3582512 G01
3582512 G02
3582512 G03
Quiescent Current – Not Switching
Switch Resistance
Switch Current Limit
700
600
500
400
300
200
390
370
350
330
310
290
270
250
O.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SWN
V
OUTN
OUTP
V
SWP
–50 –25
0
25
50
75 100 125
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
V
(V)
INPUT VOLTAGE (V)
IN
3582512 G06
3582512 G04
3582512 G05
V
OUTP and VOUTN Pin Current
Output Disconnect PMOS Current
Limit During Normal Operation
Output Disconnect PMOS
On-Resistance
During Normal Operation
200
180
160
140
120
100
80
60
2.5
2
CURRENT INTO
OUTP
V
PIN
V
CODE
P
40
SET TO 12V
20
V
CODE
P
SET TO 5V
1.5
1
0
V
N
CODE
–20
–40
–60
–80
–100
SET TO –5V
V
N
CODE
SET TO –12V
0.5
0
CURRENT OUT
OF V
PIN
OUTN
–50 –25
0
25
50
75 100 125
0
2.5
5
7.5
10
12.5
15
2
4
6
8
10
12
TEMPERATURE (°C)
|V | (V)
OUT
V
(V)
CAPP
3582512 G08
3582512 G07
3582512 G09
3582512f
6
LT3582/LT3582-5/LT3582-12
TYPICAL PERFORMANCE CHARACTERISTICS Note: All waveforms on this page apply
to Figure 13.
Switching Waveform at 1mA
Load (Boost)
Switching Waveform at 10mA
Load (Boost)
Switching Waveform at 100mA
Load (Boost)
V
V
V
SWP
SWP
SWP
5V/DIV
5V/DIV
5V/DIV
V
V
V
VOUTP
VOUTP
VOUTP
10mV/DIV
10mV/DIV
10mV/DIV
AC COUPLED
AC COUPLED
AC COUPLED
I
I
I
L2
L2
L2
0.2A/DIV
0.2A/DIV
0.2A/DIV
3582512 G12
3582512 G10
3582512 G11
200ns/DIV
2μs/DIV
5μs/DIV
Switching Waveform at 1mA
Load (Inverting)
Switching Waveform at 10mA
Load (Inverting)
Load Transient, VOUTN, 30mA to
60mA to 30mA Steps
V
SWN
V
SWN
10V/DIV
10V/DIV
V
VOUTN
0.1V/DIV
AC COUPLED
V
VOUTN
V
VOUTN
20mV/DIV
50mV/DIV
AC COUPLED
AC COUPLED
LOAD
CURRENT
–20mA/DIV
I
L1
I
L1
I
L1
0.2A/DIV
0.2A/DIV
0.2A/DIV
3582512 G14
3582512 G13
3582512 G15
5μs/DIV
5μs/DIV
50μs/DIV
Power-Down Discharge
Waveforms
(PUSEQ = 11, PDDIS = 1)
Load Transient, VOUTP, 30mA to
60mA to 30mA Steps
Power-Up Sequencing Waveforms
(PUSEQ = 11)
V
RAMPN
1V/DIV
V
OUTP
V
0.2V/DIV
RAMPP
1V/DIV
AC COUPLED
V
RAMPN
1V/DIV
LOAD
CURRENT
20mA/DIV
V
RAMPP
1V/DIV
V
VOUTP
V
VOUTP
5V/DIV
5V/DIV
I
L2
V
V
VOUTN
VOUTN
0.2A/DIV
5V/DIV
5V/DIV
3582512 G18
3582512 G16
3582512 G17
5ms/DIV
50μs/DIV
5ms/DIV
3582512f
7
LT3582/LT3582-5/LT3582-12
PIN FUNCTIONS
CA (Pin 1): I C Address Select Pin. Tie this pin to V to set
the 7-bit address to 0110 001. Tie to GND for 1000 101.
2
disconnected from the Boost network which allows this
pin to discharge to GND, assuming a load is present to
discharge the capacitance.
IN
V
OUTN
(Pin2):Negative Output Voltage Pin. When the con-
verterisoperating,thispinisregulatedtotheprogrammed
negative output voltage. Place a ceramic capacitor from
this pin to GND.
CAPP (Pins 10 & 11): Connect the Boost output capacitor
from these pins to GND. During shutdown, the voltage on
these pins will remain close to the input voltage due to
the path through the Boost inductor and Schottky. During
normal operation, CAPP will be boosted slightly higher
than the programmed output voltage.
SWN (Pins 3 & 4): Negative switching node for the In-
verting converter. This is the drain of the internal PMOS
power switch. Connect one end of the Inverting inductor
to these pins. Keep the trace area on these pins as small
as possible.
SWP (Pin 12): Positive switching node for the Boost
converter. This is the drain of the internal NMOS power
switch. Connect one end of the Boost inductor to this pin.
Keep the trace area on this pin as small as possible.
V
(Pin 5): Input supply pin and source of the PMOS
IN
power switch. This pin must be bypassed locally with a
ceramic capacitor. The operating voltage range of this pin
is 2.55V to 5.5V.
GND (Pin 13): Ground Pin. Tie to a local ground plane.
Proper PCB layout is required to achieve advertised
performance; see Applications Information section for
more information.
RAMPN (Pin 6): Soft start ramp pin for the Inverting
converter. Place a capacitor from this pin to GND. A
programmable current of 1μA - 8μA (LT3582) or 1ꢀA
(LT3582-5/LT3582-12) charges this pin during startup,
V
(Pin 14): Programming Voltage Pin. Drive this pin
PP
to 13-15V when programming the OTP memory. Float
limiting the ramp rate of V
GND during shutdown.
. This pin is discharged to
otherwise. A bypass capacitor should be placed from
OUTN
this node to GND if V is used for programming. If V
PP
PP
falls below 13V during OTP programming, an internal
RAMPP(Pin7):SoftstartramppinfortheBoostconverter.
Place a capacitor from this pin to GND. A programmable
currentof1μA-8μA(LT3582)or1ꢀA(LT3582-5/LT3582-12)
charges this pin during startup, limiting the ramp rate of
2
FAULT bit, which can be read through the I C interface,
can be set high.
2
SDA (Pin 15): I C Bidirectional Data Pin. Tie to GND or
V
OUTP
. This pin is discharged to GND in shutdown.
V if unused.
IN
2
SHDN (Pin 8): Shutdown Pin. Drive this pin to 1.1V or
higher to enable the part. Drive to 0.3V or lower to shut
down. Includes an integrated 222k pulldown resistor.
SCL (Pin 16): I C Clock Pin. Tie to GND or V if
IN
unused.
Exposed Pad (Pin 17): Ground Pin. Tie to a local ground
plane. Proper PCB layout is required to achieve advertised
performance; see Applications Information section for
more information.
V
(Pin 9): Output of the Boost converter output
OUTP
disconnect circuit. A ceramic capacitor should be placed
from this node to GND. During shutdown, this pin is
3582512f
8
LT3582/LT3582-5/LT3582-12
BLOCK DIAGRAM
V
SWP
CAPP CAPP
V
OUTP
IN
Q
S
R
S
R
Q
VARIABLE DELAY
VARIABLE DELAY
Q
Q
DISCONNECT
CONTROL
SWN
SWN
OTP
+
–
GND
+
–
I
T
I
T
PEAK OFF
PEAK OFF
CONTROL
CONTROL
FBP
+
–
+
+
V
OUTN
VCN
VCP
0.80V
CHIP ENABLE
SHDN
FBN
–
222k
OTP
V
V
IN
PP
–
+
0.80V
SCL
SDA
CA
+
2V
SERIAL INTERFACE,
LOGIC AND OTP
OTP ADJUST
V
CAPP
V
OUTP
IN
RAMPN
0.75V
+
FBP
–
OUTPUT SEQUENCING
BY OTP
3582512 BD
V
OUTN
+
–
FBN
2V
50mV
OUTPUT SEQUENCING
OTP ADJUST
RAMPP
3582512f
9
LT3582/LT3582-5/LT3582-12
OPERATION
The LT3582 series are dual DC/DC converters, each con-
taining both a Boost and an Inverting converter. Operation
can be best understood by referring to the Block Diagram.
TheBoostandInvertingconverterseachuseanovelcontrol
technique,whichsimultaneouslyvariesbothpeakinductor
current and switch off time. This results in high efficiency
over a large load range and low output voltage ripple. In
addition, this technique further minimizes output ripple
when the switching frequency is in the audio band.
can be configured such that (1) they both rise simultane-
ously, (2) V rises to regulation before V rises, (3)
OUTP
OUTN
rises, or(4)neither
V
risestoregulationbeforeV
OUTN
OUTP
output rises. The outputs of the LT3582-5 and LT3582-12
are pre-configured to rise simultaneously.
Therampratesoftheoutputsareproportionaltotheramp
rates of their respective RAMP pins. A capacitor is placed
between each RAMP pin and ground. The RAMP pins are
discharged during shutdown. Once enabled, configurable
(LT3582) or pre-configured (LT3582-5/LT3582-12) cur-
rents charge each RAMP pin in the desired sequence
causing the outputs to rise.
Boost Converter: The Boost converter uses a grounded
source NMOS power transistor as the main switching ele-
ment.ThecurrentintheNMOSisconstantlymonitoredand
controlled, along with the off time of the switch to achieve
Output Power-Down Discharge: The power-down dis-
charge feature is permanently enabled on the LT3582-5
and LT3582-12 and can be enabled or disabled through
regulation of V
. The V
voltage is divided by the
OUTP
OUTP
internal programmable (LT3582 only) resistor divider to
create FBP. The voltage on FBP is compared to an internal
reference and amplified, creating an error signal on the
VCPnodewhichcommandstheappropriatepeakinductor
current and off time for the subsequent switching cycle.
2
I C on the LT3582. Upon SHDN falling, and when power-
down discharge is enabled, internal transistors will acti-
vate to assist in discharging the outputs toward ground.
When power-down discharge is disabled, the chip powers
down immediately after SHDN falls and the outputs will
discharge on their own depending on their external load
capacitances and currents.
InvertingConverter:TheInvertingconverterusesapower
PMOS transistor with the source connected to V . This
topology requires only one external inductor, instead of
the normally required two inductors plus flying capacitor.
Regulation is achieved in a similar manner as the Boost.
IN
OTPMemory(LT3582Only):TheLT3582includes22bits
ofuserprogrammableoutputsettingsand1programming
lockoutbit.Parameterssuchaspositive&negativeoutput
voltages and power sequencing settings can be changed
OutputPower-upSequencing:Afteraninitialstartupdelay
(T
= 64μS typical), the outputs V
and V
OUTP OUTN
STARTUP
2
rise (in magnitude) simultaneously with the LT3582-5/
in real time with the integrated I C interface. Settings can
LT3582-12 or in one of four selectable sequences with
then be made permanent by programming to the on-chip
non-volatile OTP (One Time Programmable) memory.
2
the LT3582. Using the I C interface, the LT3582 outputs
3582512f
10
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
I C Interface
2
recent byte of data was received. The transmitter always
releases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it pulls down the SDA line
so that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge by
leavingSDAhigh,thenthemastermayabortthetransmis-
sion by generating a STOP condition. When the master
is receiving data from the slave, the master pulls down
the SDA line during the clock pulse to indicate receipt of
the data. After the last byte has been received the master
leaves the SDA line HIGH (not acknowledge) and issues a
stop condition to terminate the transmission.
2
The LT3582 series contains an I C compatible interface
with reduced input threshold voltages to allow for direct
communication with low voltage digital ICs (see Electri-
2
cal Characteristics). I C communication is disabled when
2
SHDN is low. After SHDN rises, I C communication is
re-enabled after a delay of 64μs (typical). The chip is a
read-write slave device which allows the user to read the
currentsettingsand,fortheLT3582,writenewones.Most
settings can be made permanent via the One-Time-Pro-
grammablememory. Thechipwillalwaysenableusingthe
data stored in OTP and the LT3582 can be reconfigured
after power-up.
Device Addressing
START and STOP Conditions
The LT3582 series supports two 7-bit chip addresses
depending on the logic state of the CA pin. The addresses
are 0110 001 (CA=1) and 1000 101 (CA=0). Also, there
are seven internal data byte locations as shown in Table
1. OTP0-OTP2 are the OTP memory bytes. REG0-REG2
are the corresponding volatile registers used for storing
alternatesettings. Finally, theCommandRegister(CMDR)
is used for additional control of the chip.
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high, as shown in Figure 1. When the master
hasfinishedcommunicatingwiththeslave,itissuesaSTOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
All data bytes can be read from their assigned register
addresses. Since they share the same register addresses,
reads of the OTP and REG data bytes are differentiated
by their corresponding RSEL (Register Select) bits in the
ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between transmitter and receiver to indicate that the most
SDA
SCL
A6 - A0
1-7
B7 - B0
B7 - B0
8
9
1-7
8
9
1-7
8
9
S
P
START
CONDITION
CHIP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
3582512 F01
Figure 1. Data Transfer over I2C Bus
3582512f
11
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
LT3582 Chip Configuration
CMDR register. All data written to register addresses 0-2
isstoredinREGO-REG2.RegardlessoftheRSELbits,OTP
bytes cannot be written directly. See the OTP Program-
ming section for more information.
Settings such as output voltages and sequencing are
digitallyprogrammable.Thechipusessettingsfromeither
the REG or OTP bytes, depending on the states of the cor-
responding RSEL bits (0 for OTP and 1 for REG).
Data Transfer Protocol
During shutdown the RSEL bits are reset low. As a result,
the initial configuration comes from the OTP data bytes.
After power-up, the configuration can be changed by writ-
ing new settings to the appropriate REG data byte(s) then
setting the corresponding RSEL bit(s).
The LT3582 series supports 8-bit data transfers in the
transaction formats shown in Figures 2 and 3 below.
Multiple data bytes can only be transferred by issuing
multiple transactions.
Figure 2 shows the required format for writing a byte of
datatotheLT3582series.Again,thechipaddressdepends
on the CA pin logic state.
Finally, data in the REG bytes can be permanently pro-
grammed to OTP by applying voltage to the V pin and
PP
setting the WOTP bit in the Command Register. See the
OTP Programming section for more information.
S
CHIP ADDR
W
A
REG ADDR
A
DATA
A
P
LT3582-5/LT3582-12 Chip Configuration
0110 001 OR
1000 101
0
0
00000b2:b0
0
b7:b0
0
The LT3582-5/LT3582-12 are shipped from the factory
withtheOTPmemorypre-programmedandLOCKedwhich
prohibits subsequent changes to the configuration. The
FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW)
FROM SLAVE TO MASTER A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
2
W WRITE BIT (LOW)
configuration can still be read through the I C bus and
S: START CONDITION
the RST & SWOFF bits of the CMDR register (described
later) are functional. The following sections describe the
various configurable features of the LT3582. The LT3582-5
P: STOP CONDITION
Figure 2: I2C Byte Write Transaction
and LT3582-12 are pre-configured as follows: V and V
P
N
A byte of data is read from the LT3582 series using the
format shown in Figure 3. This transaction requires four
I C bytes to read one byte of chip data and must be
repeated for each subsequent byte of data that is read.
are programmed for 5V or 12V respectively, LOCK = 1,
2
IRMP = 00, PDDIS = 1, PUSEQ = 11 and V may be 1
PLUS
or 0. Since LOCK = 1, subsequent configuration changes
are prohibited. See Configuration Lockout (LOCK Bit) for
more information.
S
CHIP ADDR
W
A
REG ADDR
A
0110 001 OR
1000 101
0
0
00000b2:b0
0
Registers and OTP
The registers and OTP bytes for the LT3582 series are
organized as shown in Table 1. The CMDR is reset to 00h
upon power up, during shutdown and during under-volt-
age and thermal lockouts. REG0-REG2 are never reset
and must always be loaded with valid data before use.
The LT3582’s OTP memory is shipped with all 0’s, and
as a result, the PUSEQ bits are configured to disable the
outputs. The PUSEQ bits must be reconfigured to enable
the outputs.
S
CHIP ADDR
R
A
DATA
A
P
0110 001 OR
1000 101
1
0
b7:b0
1
Figure 3: I2C Byte Read Transaction
3582512f
12
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CMDR: The Command Register is used to control various
functions of the chip. During shutdown and power-up the
CMDR is initialized to 00h.
Table 1: LT3582 Series Register Map
REGIS-
TER
REGIS- BIT
TER
BIT
NAME
DESCRIPTION
ADDRESS NAME
The RSEL (Register Select) bits are functional only for
the LT3582. The LT3582-5 and LT3582-12 function as if
the RSEL bits are always “0”. These bits perform three
functions:
00h
REG0/
OTP0
7:0
7:0
V
V
V
OutputVoltage(00h=3.2V,
P
N
OUTP
BFh = 12.75V)
01h
REG1/
OTP1
V
OUTN
OutputVoltage(00h=1.2V,
FFh = 13.95V)
7
6
-
Reserved, Write to 0
• Each RSEL bit instructs the chip whether to use the
configuration data from the corresponding OTP byte
(RSELx=0) or the REG byte (RSELx=1). Changing an
RSELx bit immediately updates the chip configuration.
LOCK Lockout Bit: See “OTP Program-
ming Lockout” Section.
REG2/
OTP2
5
V
V
Output Voltage Bit: In-
OUTP
PLUS
02h
crease V
by ~25mV
OUTP
4:3 IRMP RAMPP & RAMPN Pullup Cur-
2
IRMP
• Each RSEL bit determines if I C reads return data from
rent: I
= (2)
ꢀA
RAMP
thecorrespondingOTPbyte(RSELx=0)ortheREGbyte
(RSELx=1).
2
PDDIS Power-Down Discharge Enable.
PUSEQ Must be 11 if Set.
1:0 PUSEQ Power-Up Sequencing: 00 =
Outputs Disabled, 01 = V
• OTPprogrammingonlyprogramsdatatothebyteswith
corresponding RSEL bits set high.
OUTN
Ramp 1st, 10 = V
Ramp 1st,
OUTP
11 = Both Ramp Together
SettingtheSWOFFbitimmediatelydisablestheBoostand
Invertingpowerswitchesandopenstheoutputdisconnect
PMOS switch. It is recommended to set this bit before
writing new configuration data. This can prevent unex-
pected chip behavior while modifying the configuration
and also forces a soft-start after SWOFF is cleared (see
Soft-Start and Power-up Sequencing). Writing “1” to the
7
6
WOTP Write OTP Memory
CF/
Clear Fault/OTP Programming
FAULT Fault
5
4
3
2
RST Reset
SWOFF Switches-Off
04h
CMDR
-
Reserved, Write to 0
RSEL2 Register Select 2 (0=OTP2,
1=REG2)
2
RSTbitresetstheinternalI ClogicandtheCMDRregister.
Readingbit6oftheCMDRreturnstheFAULTbitindicating
if an OTP programming attempt may have failed. FAULT
is cleared during reset, power-up, or by writing a “1” to
the CF (Clear Fault) bit. Conditions that set the FAULT bit
1
0
RSEL1 Register Select 1 (0=OTP1,
1=REG1)
RSEL0 Register Select 0 (0=OTP0,
1=REG0)
OTP0/REG0 & OTP1/REG1: Data in addresses 00h &
01h is used to set the output voltages of the Boost and
Inverting converters respectively. See Setting the Output
Voltages for more information.
are (1) OTP programming in which the V voltage is too
PP
low or (2) attempted OTP programming when the LOCK
bit is set. OTP write attempts that set the FAULT bit due
to low V voltage should be considered failures and the
PP
device should be discarded. Attempts to re-program the
OTP memory after the FAULT bit has been set are not
recommended. Finally, setting the WOTP bit starts the
OTP programming.
3582512f
13
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
OTP2/REG2: Data in address 02h configures the output
voltage sequencing, sets a fine voltage adjust for V
anddeterminesiffurtherOTPprogrammingispermittedor
not. Proper uses of the bits in address 02h are discussed
in the following sections.
Soft-Start/Output Voltage Ramping (IRMP bits)
,
OUTP
The LT3582 series contains soft-start circuitry to control
the output voltage ramp rates, therefore limiting peak
switch currents during start-up. High switch currents are
inherent in switching regulators during startup since the
feedback loop is saturated due to V
being far from its
OUT
Setting the Output Voltages (V , V
and V bits)
N
P
PLUS
finalvalue.Theregulatortriestochargetheoutputcapacitor
The LT3582 series contains two resistor dividers
which are programmable in the LT3582, to set the
as quickly as possible which results in large currents.
Capacitors must be connected from RAMPP & RAMPN
to ground for soft-start. During shutdown or when the
SWOFF bit is set, the RAMP capacitors are discharged
to ground. After SHDN rises or SWOFF is cleared, the
capacitors are charged by programmable (LT3582 only)
output voltages. The positive output voltage V
OUTP
is adjustable in 25mV steps by setting the V bits in
P
REG0/OTP0 in addition to the V
bit in REG2/OTP2.
PLUS
VOUTP = 3.2V + (VP • 50mV)+ (VPLUS • 25mV)
where:
V = an integer value from 0 to 191
currents, thus creating linear voltage ramps. The V
OUT
voltages ramp in proportion to their respective RAMP
voltages according to:
P
ꢀ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
ꢀ
ꢃ
VOUT
0.8V
IRAMP
V
= 0 or 1
PLUS
VOUT _RAMP _RATE =
•
Volts / Sec
ꢂ
ꢅ
C
ꢁ
ꢄ
RAMP
TheV
voltageisadjustablein–50mVstepsbysetting
OUTN
the V bits in REG1/OTP1.
N
Proportionality Constant
RAMP pin ramp rate (V/Sec)
VOUTN = –1.2V – (VN • 50mV)
where:
where:
V = an integer value from 0 to 255
N
I
= RAMP pin charging current set by IRMP
bits (1μA, 2μA, 4μA or 8μA for LT3582,
1ꢀA for LT3582-5/LT3582-12)
= External RAMP pin capacitor (Farads)
= Output voltage during regulation
RAMP
DynamicallyChangingtheOutputVoltage(LT3582Only):
After output regulation has been reached, it’s possible to
change the output voltages by writing new values to the
C
RAMP
V
OUT
V or V bits. When reducing the magnitude of an out-
N
P
put voltage, it will decay at a rate dependent on the load
current and capacitance. Configuring a large increase in
magnitude of an output voltage can cause a large increase
in switch current to charge the output capacitor. Before
reconfiguring the outputs, consider forcing a soft-start
For example, selecting I
= 1μA, C
= 10nF and
RAMP
RAMP
V
= 12V results in a power-up ramp rate of 1.5Volt/ms
OUTP
(see Figure 6).
Ramp rates less than 1-10V/ms generally result in good
startupcharacteristics. Theoutputsshouldlinearlyfollow
the RAMPx voltages with no distortions. Figure 7 shows
an excessive startup ramp rate of ~120V/ms in which sev-
by asserting the SWOFF bit before writing the new V or
P
V codes. Subsequently clearing SWOFF initiates the new
N
soft-start sequence.
eral startup issues have occurred: A) the expected V
OUTP
ramp up path is not followed B) inductor current ringing
occurs C) the V
ramp rate is limited due to the output
OUTP
3582512f
14
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Once enabled, the Disconnect Control circuit actively
disconnect current limit being reached D) additional ring-
ing occurs when the CAPP pin starts charging E) output
voltage overshoot occurs because the inductor currents
are maximized during the output ramp up.
drives the PMOS gate allowing V
as shown in Figure 6. Once V
to ramp up linearly
OUTP
reaches regulation,
OUTP
the PMOS is fully turned “on” to reduce resistance and
improve efficiency.
In some cases it may be desirable to use only one RAMP
pin capacitor. In cases where PUSEQ = 11 (see Power-Up
Sequencing section) the RAMPP & RAMPN pins can be
connected together and to a single capacitor. In this case
thecapacitorwillchargewithtwicethecurrentconfigured
by the IRMP bits.
Power-Up Sequencing (PUSEQ bits)
Once enabled, the part requires a delay of T
(64μs
STARTUP
t yp) to properly configureitself.Onceconfigured,theorder
inwhichV andV ramptoregulationis controlled
OUTP
OUTN
by the PUSEQ bits. The combinations available for the
LT3582 are shown in Table 2. The LT3582-5/LT3582-12
are pre-configured with the 11 combination.
Ramping V
from Ground: The LT3582 series has
OUTP
the unique ability to generate a smooth V
voltage
OUTP
ramp starting from ground and continuing all the way up
to regulation (see Figure 6). This ability is not possible
with typical Boost converters in which the output is taken
from the cathode of the Schottky diode (CAPP node in
Figure 5).
Table 2. Power-Up Sequences
PUSEQ[1:0] Power-Up Sequence
00
01
10
11
Outputs are disabled, neither output ramps up
V
V
ramps up 1st, followed by V
ramps up 1st, followed by V
OUTN
OUTP
OUTP
OUTN
The LT3582 series incorporates an output disconnect
Both V
& V
ramp up starting at the
OUTN
OUTP
same time.
PMOS allowing V
to be grounded during shutdown.
OUTP
L1
Selecting the 01 or 10 combinations cause one of the out-
SWP
LT3582
puts to start ramping shortly after SHDN rises. The ramp
D1
CAPP
SERIES
V
rate of V
is controlled by the RAMP pin as discussed in
OUTP
OUT
C1
the Soft-Start section. After V
nears its target regula-
OUT
C3
LOAD
tion voltage, the remaining output is activated and ramps
C2
DISCONNECT
CONTROL
V
IN
A
E
V
RAMPP
3582512 F05
0.5V/DIV
Figure 5: Boost Converter Topology
B
D
CAPP
3V/DIV
V
OUTP
3V/DIV
C
I
L2
0.2A/DIV
CAPP
2V/DIV
3582512 F07
50μs/DIV
Figure 7: VOUTP Soft-Start with Excessive Ramp Rate
V
OUTP
2V/DIV
V
RAMPP
0.2V/DIV
I
L2
3582512 F06
0.2A/DIV
5μs/DIV
Figure 6: VOUTP Soft-Start Ramping from Ground
3582512f
15
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
under control of its respective RAMP pin (see Figure 8
below). The power-up sequencing concludes when both
outputs have reached regulation.
PDDIS = 0 disables the power-down discharge causing
the chip to shut down immediately after SHDN falls. The
PDDISbitmustonlybesetinconjunctionwithPUSEQbeing
set to 11. Driving SHDN low, with power-down discharge
enabled (PDDIS = 1) causes the chip to power-down after
first discharging the output voltages. Specifically, driving
SHDN low causes the following sequence of events to
happen:
Evaluating PUSEQ Settings (LT3582 Only): After SHDN
rises, the LT3582 uses the PUSEQ configuration found
in OTP. The effects of differing PUSEQ settings can be
observed without writing to OTP by taking the following
actions:
1. Both converters are turned off.
1. Write the SWOFF bit high, stopping both converters
and discharging the RAMP pins.
2. Discharge currents are enabled to discharge the
output capacitors
2. Write the desired settings to the PUSEQ bits in
REG2.
• See Electrical Charateristics for I
and
VOUTP-PDS
I
which help discharge V
and CAPP
CAPP-PDS
OUTP
3. Set the RSEL2 bit high which selects the REG2
configuration settings.
• SeeElectricalCharateristicsforI
which
VOUTN-PDS
helps discharge V
OUTN
4. Write SWOFF low which restarts both converters.
3. The chip waits until the output voltages have
discharged to within ~0.5V to ~1.5V of ground.
This will initiate the desired power-up sequence that can
be observed with an oscilloscope.
4. Discharge currents are disabled and the LT3582
powers down.
Power-Down Discharge (PDDIS bit)
The PDDIS bit is used to enable power down discharge.
This bit is pre-configured to a “1” for the LT3582-5 and
LT3582-12, thus enabling power-down discharge.Setting
RAMPP
V
RAMPP
RAMPN
0.5V/DIV
V
RAMPN
0.5V/DIV
V
VOUTP
5V/DIV
V
VOUTN
5V/DIV
3582512 F08
5ms/DIV
Figure 8: Power-up Sequencing (PUSEQ=10)
3582512f
16
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
programming to OTP. After 15V has been applied to V ,
Since the LT3582 series won’t power-down until both
outputs are discharged (when power-down sequencing
PP
theWOTPbitissetintheCMDRtostarttheprogramming.
Finally, the WOTP bit is cleared to finish the programming.
An example programming algorithm is given below.
is enabled), make sure V
& V
can be grounded.
OUTP
OUTN
This is not a problem in most topologies. However, read
the section Output Disconnect Operating Limits for ad-
ditional information.
OTP programming draws about 3-6mA per bit from the
V
pin. It is possible to program all 23 bits simultane-
PP
ously(upto~138mA), butitisrecommendedthatonebyte
Configuration Lockout (LOCK bit)
is programmed at a time to reduce noise on V caused
PP
PP
After a desired configuration is programmed into OTP, the
LOCK bit can be set to prohibit subsequent changes to the
configuration. The LT3582-5 and LT3582-12 are precon-
figured with the LOCK bit set to a logic “1” which:
by the sudden change in current. A 1-10μF V bypass
capacitor is also recommended to prevent voltage droop
after programming begins. Also, avoid hot-plugging V
PP
which results in very fast voltage ramp rates and can lead
• Forces the chip to use the OTP configuration
only.
to excessive voltage on the V pin.
PP
Example OTP Programming Algorithm:
2
• Forces all I C reads from addresses 0-2 to return
1. Apply 15V to the V pin. This can be done at any
OTP data.
PP
time before step 5.
• Prohibits any further programming of the OTP
memory.AnyfurtherattemptstoprogramOTPleaves
the OTP memory unchanged and sets the FAULT bit
in the CMDR.
2. Write 50h to the CMDR. This disables the power
switchesduringprogrammingbysettingtheSWOFF
bit in the CMDR. This also clears the FAULT bit.
3. Write desired data to REG0-REG2.
The LOCK OTP bit is set by programming a logic “1” into
2
bit 6 of OTP2. Regardless of the RSEL2 setting, I C reads
4. Write 11h to the CMDR. This selects REG0 for pro-
gramming while keeping the switches off.
of the LOCK bit always indicate the LOCKed or unlocked
state of the OTP memory.
5. Write 91h to the CMDR. This programs the REG0
data to OTP0.
OTP Programming (LT3582 only)
6. Write 11h to the CMDR. This command can be sent
immediately after step 5. This stops the program-
ming.
The LT3582 contains One Time Programmable non-vola-
tile memory to permanently store the chip configuration.
Beforeprogramming, it’srecommendedtosettheSWOFF
bit to disable switching activity and prevent unexpected
chip behavior while the configuration is being changed.
Programming involves the transfer of information from
the REG bytes to the OTP bytes. Therefore, valid data
must first be written to the desired REG bytes. After the
REG bytes are written, they are selected by setting the
correspondingRSELbitsintheCMDR.Thisforcesthechip
into the desired configuration and selects those bytes for
7. Read the CMDR and verify that the FAULT bit is
not set.
8. Repeat steps 4-7 for the remaining bytes that need
programming.
9. Write 10h to the CMDR. This selects the OTP data
for read verification.
3582512f
17
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
10. Read the OTP data and verify the contents.
inductor current without saturating. To minimize radiated
noise, use a toroidal or shielded inductor (note that the
inductance of shielded types will drop more as current
increases, and will saturate more easily).
11. Write00htoCMDR.Thisenablesthepowerswitches
and the chip will operate from the OTP configura-
tion.
Peak Current Rating: Real inductors can experience
a drop in inductance as current and temperature
increase. The inductors should have saturation cur-
rent ratings higher than the peak inductor currents.
The peak inductor currents can be calculated as:
12. Float the V pin. This can be done at any time
PP
after step 8.
Choosing Inductors
Several series of inductors that work well with the LT3582
series are listed in Table 3. This table is not complete, and
there are many other manufacturers and parts that can
be used. Consult each manufacturer for more detailed
information and for their entire selection of related parts,
as many different sizes and shapes are available.
V
LSWON •T
IPK ≅ILIMIT
where:
+
OS mA
L
I
= Peak inductor current
PK
I
Table 3: Inductor Manufacturers
= Typically 350mA for Boost and 600mA for
Inverting
LIMIT
Coilcraft
LPS3008-LPS4018 Series, www.coilcraft.com
XPL2010 Series
L
V
= Inductance in ꢀH
Murata
Sumida
LQH32C, LQH43C Series
www.murata.com
= Maximum inductor voltage when the
LSWON
CDRH26D09, CDRH26D11, www.sumida.com
CDRH3D14 Series
power switch is “on”. Typically max V
IN
for the Boost and Inverting converters.
= 100 for Boost and 125 for Inverting
TDK
VLF and VLCF Series
www.tdk.com
T
OS
Würth
Elektronik
WE-TPC Series Type T, TH, www.we-online.com
XS and S
Maximum Load Currents: Use one of the following equa-
tions to estimate the maximum output load current for the
positive and negative output voltages:
Inductances of 2.2μH-10ꢀH typically result in a good
tradeoff between inductor size and system performance.
More inductance typically yields an increase in efficiency
attheexpenseofincreasedoutputripple. Lessinductance
may be used in a given application depending on required
efficiencyandoutputcurrent.Forhigherefficiency,choose
inductorswithhighfrequencycorematerial,suchasferrite,
to reduce core losses. Also to improve efficiency, choose
inductors with more volume for a given inductance. The
inductor should have low DCR (copper-wire resistance)
IOUTP
=
⎛
⎜
⎝
IN(MIN) ⎞ ⎛
⎞
)
⎟
⎠
V
TOFF _MIN •(VOUTP + 0.5 – V
IN(MIN)
• I
–
•0.8η
⎟ ⎜PK
V
2 •L
⎠ ⎝
OUTP
or IOUTN
=
⎛
⎜
⎜
⎝
⎞
⎛
⎞
V
TOFF _MIN •(|VOUTN |+0.5)
IN(MIN)
⎟
• I
–
•0.8η
⎟
⎜
PK
⎟
2
V
IN(MIN)+|VOUTN
|
2 •L
⎝
⎠
⎠
to reduce I R losses, and must be able to handle the peak
3582512f
18
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Where…
most LT3582 series applications. Always use a capacitor
with a sufficient voltage rating. Many capacitors rated at
2.2μF to 10μF, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired output voltage.
Generally a 1206 capacitor will be adequate. A 0.22μF to
1μF capacitor placed on the CAPP node is recommended
to filter the inductor current while the larger 2.2μF to 10μF
V
V
PK
= Regulation voltage
OUT
IN(MIN)
= Minimum input voltage.
I
= Peak inductor current. See prior section
Peak Current Rating. Use minimum I
rating for these calculations.
= Power conversion efficiency (about 88%
for Boost or 78% for Inverting)
= Minimum switch off time. Typically
100ns for Boost and 125ns for Inverting.
Limit
η
placed on the V
& V
nodes will give excellent
OUTP
OUTN
transient response and stability. Avoid placing large value
T
OFF_MIN
capacitors (generally > 6.8μF) on both CAPP and V
.
OUTP
This configuration can be less stable since it creates two
I
= Output load current
poles, one at the CAPP pin and the other at the V
OUT
OUTP
pin, which can be near each other in frequency. Table 4
shows a list of several capacitor manufacturers. Consult
the manufacturers for more detailed information and for
their entire selection of related parts.
For example, if V
= 10V, V
= –10V, V = 5V, and
OUTN
OUTP
OUTP
OUTN IN
L = 4.7μH then I
= 117mA and I
= 105mA.
Note: The 155mA (Typ) current limit of the output dis-
connect PMOS (see Electrical Characteristics) may limit
Table 4: Ceramic Capacitor Manufacturers
maximum I
unless CAPP is shorted to V
. See
OUTP
OUTP
MANUFACTURER PHONE
URL
Improving Boost Converter Efficiency.
Kemet
408-986-0424
www.kemet.com
www.murata.com
www.t-yuden.com
www.tdk.com
Maximum Slew Rate: Lower inductance causes higher
current slew rates which can lead to current limit over-
shoot. Choose an inductance higher than L
the overshoot:
Murata
Taiyo Yuden
TDK
814-237-1431
408-573-4150
847-803-6100
to limit
MIN
Diode Selection
LMIN = VIN(MAX) •0.2µH
Schottky diodes, with their low forward voltage drops
and fast switching speeds, are recommended for use with
the LT3582 series. The Diodes Inc. B0540WS is a very
good choice in a small SOD-323 package. This diode is
rated to handle an average forward current of 500mA and
performs well across a wide temperature range. Schottky
diodes with very low forward voltage drops are also avail-
able. These diodes may improve efficiency at moderate
and cold temperatures, but will likely reduce efficiency
at higher temperatures due to excessive reverse leakage
currents.
where V
is the maximum input voltage. Using the
IN(MAX)
previous example V = 3V, L
= 0.6μH.
IN
MIN
Capacitor Selection
The small size and low ESR of ceramic capacitors makes
them suitable for most LT3582 series applications. X5R
andX7Rtypesarerecommendedbecausetheyretaintheir
capacitance over wider voltage and temperature ranges
thanothertypessuchasY5VorZ5U. A4.7μFinputcapaci-
tor and a 2.2μF-10μF output capacitor are sufficient for
3582512f
19
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Output Disconnect Operating Limits
Improving Boost Converter Efficiency
The LT3582 series has a PMOS output disconnect switch
The efficiency of the Boost converter can be improved by
connected between CAPP and V
. During normal
shortingtheCAPPpintotheV
pin (see Figure 11). The
OUTP
OUTP
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that
the output load current doesn’t exceed the PMOS current
limit. Exceeding the current limit causes a significant
rise in PMOS power consumption which may damage
the device.
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger V
can adequately filter the output voltage.
capacitor
OUTP
Note that the ripple voltage on V
will typically in-
OUTP
crease in this configuration since the output disconnect
PMOS, when not shorted, helps to create an RC filter at
During shutdown, the PMOS switch is open and CAPP is
isolated from V
up to a voltage difference of 5-5.5V.
the output. Also, if the V
pin is shorted to CAPP,
OUTP
OUTP
In most cases this allows V
to discharge to ground.
the power-down discharge should not be enabled. V
OUTP
OUTP
However, when the Boost inductor input exceeds 5.5V,
the CAPP-V voltage may exceed 5V allowing some
cannot be discharged to ground during shutdown due to
the path from V to V
through the external inductor
OUTP
IN
OUTP
current flow through the PMOS switch. In addition, apply-
ing CAPP-V voltages in excess of 5.7V(typical) may
OUTP
activateinternalprotectioncircuitrywhichturnsthePMOS
“on” (see Figure 10). If the current is not limited, this can
lead to a sharp increase in the PMOS power consumption
and may damage the device. If this situation cannot be
avoided, limit PMOS power consumption to less than 1/3
Watt (about 50mA at 7V) to avoid damaging the device.
RefertotheAbsoluteMaximumRatingstableformaximum
I
CAPP-VOUTP
20ꢀA/DIV
limits on CAPP-V
voltages and currents.
OUTP
3582512 F11
V
1V/DIV
CAPP-VOUTP
180
160
140
120
100
80
Figure 10: PMOS Current vs. Voltage During Shutdown
4
3
12
5
SWN
SWN
SWP
V
IN
11
10
CAPP
CAPP
13
2
GND
C1
I
60
LOAD
LT3582
40
9
V
OUTP
20
V
OUTN
14
15
16
1
V
PP
0
0
100
200
CAPP-V
300
(mV)
400
500
SDA
SCL
CA
OUTP
3582512 F10
8
SHDN
RAMPP RAMPN
Figure 9: PMOS Current vs. Voltage During Normal Operation
7
6
3582512 F12
Figure 11: Improved Efficiency
3582512f
20
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Board Layout Considerations
and diode. Finally, due to the path from V to V
,
IN
OUTP
current will flow through the integrated feedback resistor
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
Tomaximizeefficiency,switchriseandfalltimesaremade
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have sharp rising and falling edges.
Minimize the length and area of all traces connected to
the SWP/SWN pins and always use a ground plane under
the switching regulator to minimize interplane coupling.
Suggested component placement is shown in Figure 12.
Make sure to include the ground plane cuts as shown in
Figure12.Theswitchingactionoftheregulatorscancause
large current steps in the ground plane. The cuts reduce
noise by recombining the current steps into a continuous
flow under the chip, thus reducing di/dt related ground
noise in the ground plane.
whenever voltage is present on V .
IN
Inrush Current
When the Boost inductor input voltage (usually V ) is
IN
stepped from ground to the operating voltage, a high
level of inrush current may flow through the inductor
and Schottky diode into the CAPP capacitor. Conditions
that increase inrush current include a larger more abrupt
voltage step at the inductor input, larger CAPP capacitors
and inductors with low inductances and/or low saturation
currents. For circuits that use output capacitor values
within the recommended range and have input voltages
of less than 5V, inrush current remains low, posing no
hazard to the devices. In cases where there are large
input voltage steps (more than 5V) and/or a large CAPP
capacitor is used, inrush current should be measured to
ensure safe operation.
Thermal Lockout
If the die temperature reaches approximately 147°C, the
part will go into thermal lockout. In this event, the chip
is reset which turns off the power switches and starts to
dischargetheRAMPcapacitors.Thepartwillbere-enabled
when the die temperature drops by about 3.5°C.
3582512f
21
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CA SCL SDA VPP
C
VPP
(OPT)
16
15
14
13
L1
V
1
2
12
OUTN
C
OUTN
17
C
C
CAPP
11
3
4
10
9
L2
GND
C
IN
5
6
7
8
OUTP
V
IN
SHDN
V
OUTP
VIAS TO GROUND PLANE UNDER
PIN 17 REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GROUND PLANE
3582512 G13
Figure 12: Suggested Component Placement (not to scale)
3582512f
22
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
5V Outputs from a Single 2.7V to 3.8V Input
SWN
SWN
SHDN
INPUT
V
IN
D1
L1
2.7V TO 3.8V
6.8ꢀH
SWP
L2 6.8ꢀH
C4 1ꢀF
GND
C1
4.7ꢀF
D2
LT3582
C2
10ꢀF
V
NEG
–5V
CAPP
CAPP
V
OUTN
100mA (V ≥ 2.7V)
125mA (V ≥ 3.3V)
IN
IN
V
POS
5V
SDA
SCL
CA
V
OUTP
2
100mA (V ≥ 2.7V)
124mA (V ≥ 3.3V)
IN
I C
IN
V
INTERFACE
PP
C3
10ꢀF
RAMPP RAMPN
OPTIONAL ON
LT3582-5
C5
22nF
C6
22nF
(
)
3582512 TA02a
REG0/OTP0 = 24h D1-D2: DIODES INC. B0540WS-7
REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML
REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805
C2-C3: 10ꢀF, 6.3V, X5R 0805
C4: 1ꢀF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTP to GND
Efficiency and Power Loss, Load from VOUTN to GND
100
90
80
70
60
50
40
30
20
10
0
95
85
75
65
55
45
35
180
160
140
120
100
80
95
85
75
65
55
45
35
V
= 3.3V
V
= 3.3V
IN
IN
60
40
20
0
100
0.1
1
10
100
0.1
1
10
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3582512 TA02b
3582512 TA02c
Efficiency and Power Loss, Load from VOUTP to VOUTN
300
250
200
150
100
50
95
85
75
65
55
45
35
V
= 3.3V
IN
0
100
0.1
1
10
LOAD CURRENT (mA)
3582512 TA02d
3582512f
23
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
5V Outputs from a Single 2.7V to 3.8V Input (Improved Efficiency)
SWN
SWN
SHDN
INPUT
V
IN
D1
L1
2.7V TO 3.8V
6.8ꢀH
SWP
L2 6.8ꢀH
C3 10ꢀF
GND
C1
4.7ꢀF
D2
LT3582
C2
10ꢀF
V
NEG
–5V
CAPP
CAPP
V
OUTN
100mA (V ≥ 2.7V)
125mA (V ≥ 3.3V)
IN
IN
V
POS
5V
SDA
SCL
CA
V
OUTP
2
110mA (V ≥ 2.7V)
150mA (V ≥ 3.3V)
IN
I C
IN
V
INTERFACE
PP
RAMPP RAMPN
OPTIONAL ON
LT3582-5
C5
22nF
C6
22nF
(
)
3582512 TA03
REG0/OTP0 = 24h D1-D2: DIODES INC. B0540WS-7
REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML
REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805
C2-C3: 10ꢀF, 6.3V, X5R, 0805
C4: 1ꢀF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTP to GND
95
85
75
65
55
45
35
80
70
60
50
40
30
20
10
0
V
= 3.3V
IN
0.1
1
10
100
LOAD CURRENT (mA)
3582512 TA03a
3582512f
24
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
12V and –5V Outputs from a Single 2.7V to 5.5V Input
SWN
SWN
SHDN
INPUT
V
IN
D1
L1
2.7V TO 5.5V
6.8ꢀH
SWP
L2 6.8ꢀH
C4 1ꢀF
GND
C1
D2
LT3582
4.7ꢀF
C2
10ꢀF
V
NEG
CAPP
CAPP
–5V
V
OUTN
100mA
V
POS
12V
SDA
SCL
CA
V
OUTP
2
I C
38mA (V = 2.7)
IN
C3
4.7ꢀF
V
INTERFACE
PP
58mA (V = 3.6)
IN
95mA (V = 5.5)
IN
RAMPP RAMPN
C5
22nF
C6
22nF
3582512 TA04a
REG0/OTP0 = B0h D1-D2: DIODES INC. B0540WS-7
REG1/OTP1 = 4Ch L1-L2: COILCRAFT LPS4018-682ML
REG2/OTP2 = 0Bh C1: 4.7ꢀF, 6.3V, X5R, 0805
C2: 10ꢀF, 6.3V, X5R, 0805
C3: 4.7ꢀF, 16V, X5R, 0805
C4: 1ꢀF, 16V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTN to GND
Efficiency and Power Loss, Load from VOUTP to GND
180
160
140
120
100
80
95
85
75
65
55
45
35
100
90
80
70
60
50
40
30
20
10
0
95
85
75
65
55
45
35
V
= 3.6V
V
= 3.6V
IN
IN
60
40
20
0
100
0.1
1
10
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3582512 TA04c
3582512 TA04b
Efficiency and Power Loss, Load from VOUTP to VOUTN
95
85
75
65
55
45
35
200
180
160
140
120
100
80
V
= 3.6V
IN
60
40
20
0
100
0.1
1
10
LOAD CURRENT (mA)
3582512 TA04d
3582512f
25
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
SWN
SWN
SHDN
INPUT
V
IN
4.5V TO 5.5V
D1
L1
SWP
6.8ꢀH
L2 6.8ꢀH
C4 1ꢀF
GND
C1
4.7ꢀF
D2
LT3582
C2
4.7ꢀF
V
CAPP
CAPP
NEG
–12V
V
OUTN
85mA
V
POS
SDA
SCL
CA
12V
V
OUTP
2
I C
80mA
V
INTERFACE
PP
C3
RAMPP RAMPN
OPTIONAL ON
LT3582-12
(
)
C5
10nF
C6
10nF
3582512 TA05a
REG0/OTP0 = B0h D1-D2: DIODES INC. B0540WS-7
REG1/OTP1 = D8h L1-L2: COILCRAFT XPL2010-682
REG2/OTP2 = 03h C1: 4.7ꢀF, 6.3V, X5R, 0805
C2: 4.7ꢀF, 16V, X5R, 0805
C3: 1× 4.7ꢀF OR 2× 4.7ꢀF OR 10ꢀF
16V, X5R, 0805
C4: 1ꢀF, 16V, X5R, 0603
C5-C6: 10nF, 0603
Figure 13. 12V Outputs from a Single 5V Input
VOUTP Ripple
VOUTN Ripple and C2 Selection
80
60
40
20
0
25
20
15
10
5
4.7ꢀF 16V 0805 X5R
10ꢀF 16V 0805 X5R
2× 4.7ꢀF 16V 0805 X5R
0
0
20
40
60
80
0
20
40
60
80
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3582512 TA05c
3582512 TA05b
Also See Typical Characteristics and Front Page for Additional Data
3582512f
26
LT3582/LT3582-5/LT3582-12
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 p0.05
3.50 p 0.05
2.10 p 0.05
1.45 p 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
3.00 p 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
2
1.45 p 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 p 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3582512f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
27
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
Tiny AMOLED Power Supply is 0.8mm (Max) Thin
Efficiency and Power Loss, Load from VOUTP to VOUTN
90
80
70
60
50
40
30
350
300
250
200
150
100
50
V
= 3.3V
IN
SWN
SWN
SHDN
INPUT
V
IN
2.7V TO 4.2V
L1
D1
SWP
1.5ꢀH
L2 1.5ꢀH
C4 10ꢀF
GND
C1
10ꢀF
D2
LT3582
C2
10ꢀF
V
CAPP
CAPP
NEG
–5V
V
OUTN
90mA
V
POS
SDA
SCL
CA
4.6V
V
OUTP
2
I C
INTERFACE
100mA
V
PP
C3
10ꢀF
0
100
RAMPP RAMPN
0.1
1
10
C5
10nF
C6
10nF
LOAD CURRENT (mA)
3582512 TA06b
3582512 TA06a
REG0/OTP0 = 1Ch D1-D2: PANASONIC M21D3800L LOW V SCHOTTKY
F
REG1/OTP1 = 4Ch L1-L2: TDK MLP3216S1R5L
REG2/OTP2 = 07h C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805
C5-C6: 0402 X5R
RELATED PARTS
PART
DESCRIPTION
COMMENTS
LT1944/-1(Dual)
Dual Output 350mA I , Constant Off-Time, High V : 1.2V to 15V, V
= 34V, I = 20ꢀA, I <1ꢀA, MS10
Q SD
SW
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
Efficiency Step-Up DC/DC Converter
LT1945(Dual)
LT3463/A
Dual Output, Pos/Neg, 350mA I , Constant Off-
V : 1.2V to 15V, V
IN
=
=
34V, I = 20ꢀA, I <1ꢀA, MS10
Q SD
SW
Time, High Efficiency Step-Up DC/DC Converter
Dual Output, Boost/Inverter, 250mA I , Constant V : 2.4V to 15V, V
40V, I = 40ꢀA, I <1ꢀA, DFN
Q SD
SW
IN
Off-Time, High Efficiency Step-Up DC/DC
Converter with Integrated Schottkys
LT3471
Dual Output, Boost/Inverter, 1.3A I , 1.2MHz,
V : 2.4V to 16V, V
=
=
40V, I = 2.5mA, I <1ꢀA, DFN
Q SD
SW
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
High Efficiency Boost-Inverting DC/DC Converter
LT3472
Dual Output, Boost/Inverter, 0.35A I , 1.2MHz,
V : 2.2V to 16V, V
34V, I = 2.8mA, I <1ꢀA, DFN
Q SD
SW
IN
High Efficiency Boost-Inverting DC/DC Converter
LT3477
42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED
Driver
V : 2.5V to 25V, V
= 40V, I = Analog/PWM, I <1ꢀA, QFN,
Q SD
IN
TSSOP-20E
LT3494/A
180/350mA (I ), Low Noise High Efficiency Step- V : 2.3V to 16V, V
= 40V, I = 65ꢀA, I <1ꢀA, 2mm × 3mm DFN
Q SD
SW
IN
Up DC/DC Converter
LT3495/ LT3495B/
LT3495-1/ LT3495B-1 Up DC/DC Converter
650/350mA (I ), Low Noise High Efficiency Step- V : 2.5V to 16V, V
= 40V, I = 60ꢀA, I <1ꢀA, 2mm × 3mm DFN
Q SD
SW
IN
LT1930/A
LT1931/A
LT3467/A
LT1618
1A (I ), 1.2/2.2MHz, High Efficiency Step-Up
V : 2.6V to 16V, V
IN
= 34V, I = 4.2/5.5mA, I <1ꢀA, ThinSOT
Q SD
SW
DC/DC Converter
1A (I ), 1.2/2.2MHz, High Efficiency Inverting
V : 2.6V to 16V, V
IN
= 34V, I = 4.2/5.5mA, I <1ꢀA, ThinSOT
Q SD
SW
DC/DC Converter
1.1A (I ), 1.3/2.1MHz, High Efficiency Step-Up
V : 2.4V to 16V, V
IN
= 40V, I = 1.2mA, I <1ꢀA, ThinSOT
Q SD
SW
DC/DC Converter with Soft-Start
1.5A (I ), 1.4MHz, High Efficiency Step-Up
V : 1.6V to 18V, V
IN
= 35V, I = 1.8mA, I <1ꢀA, MS10, DFN
Q SD
SW
DC/DC Converter
LT1946/A
1.5A (I ), 1.2/2.7MHz, High Efficiency Step-Up
V : 2.6V to 16V, V
IN
= 34V, I = 3.2mA, I <1ꢀA, MS8E
Q SD
SW
DC/DC Converter
3582512f
LT 0509 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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