LTC1608CG_技术文档

LTC1608

High Speed, 16-Bit, 500ksps

Sampling A/D Converter

with Shutdown

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FEATURES

DESCRIPTIO

The LTC^®1608 is a 500ksps, 16-bit sampling A/D con-

verter that draws only 270mW from ±5V supplies. This

high performance device includes a high dynamic range

sample-and-hold, a precision reference and a high speed

parallel output. Two digitally selectable power shutdown

modes provide power savings for low power systems.

■

A Complete, 500ksps 16-Bit ADC

■

90dB S/(N+D) and –100dB THD (Typ)

■

Power Dissipation: 270mW (Typ)

■

No Pipeline Delay

■

No Missing Codes Over Temperature

■

Nap (7mW) and Sleep (10µW) Shutdown Modes

■

Operates with Internal 15ppm/°C Reference

or External Reference

The LTC1608’s full-scale input range is ±2.5V. Outstand-

ing AC performance includes 90dB S/(N+D) and –100dB

THD at a sample rate of 500ksps.

■

True Differential Inputs Reject Common Mode Noise

5MHz Full Power Bandwidth

±2.5V Bipolar Input Range

36-Pin SSOP Package

Theuniquedifferentialinputsample-and-holdcanacquire

single-ended or differential input signals up to its 15MHz

bandwidth. The 68dB common mode rejection allows

users to eliminate ground loops and common mode noise

by measuring signals differentially from the source.

Pin Compatible with the LTC1604

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APPLICATIO S

■

The ADC has µP compatible,16-bit parallel output port.

Thereisnopipelinedelayinconversionresults. Aseparate

convert start input and a data ready signal (BUSY) ease

connections to FlFOs, DSPs and microprocessors.

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

High Speed Data Acquisition

Spectrum Analysis

Imaging Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

Circuitry in the LTC1608 is covered under US Patent #5,764,175

■

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TYPICAL APPLICATIO

5V 10µF

2.2µF

10µF

5V 10µF

10Ω

+

3

36

10

35

9

LTC1608 4096 Point FFT

V

REF

AV

DD

DV

DD

DGND

DD

SHDN

CS

0

33

32

31

30

27

f

= 500kHz

SAMPLE

= 98.754kHz

LTC1608

IN

CONTROL

LOGIC

–20

µP

CONTROL

LINES

SINAD = 86.7dB

THD = –92.6dB

CONVST

RD

REFCOMP

7.5k

AND

4

2.5V

REF

1.75X

–40

–60

TIMING

+

BUSY

22µF

OV

DD

29

28

5V OR

+

3V

–80

10µF

+

OGND

A

1

2

IN

+

–100

–120

–140

DIFFERENTIAL

ANALOG INPUT

±2.5V

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

–

A

IN

D15 TO D0

–

11 TO 26

1608 TA01

AGND AGND AGND AGND

V

SS

34

50

100

250

0

150

200

5

6

7

8

FREQUENCY (kHz)

1608 TA02

10µF

+

–5V

1

LTC1608

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ABSOLUTE AXI U RATI GS

AV_DD= DV_DD= OV_DD= V_DD(Notes 1, 2)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER

+

–

Supply Voltage (V_DD)................................................ 6V

Negative Supply Voltage (V_SS) ............................... –6V

Total Supply Voltage (V_DDto V_SS) .......................... 12V

Analog Input Voltage

(Note 3) ......................... (V_SS– 0.3V) to (V_DD+ 0.3V)

V_REFVoltage (Note 4) ................. –0.3V to (V_DD+ 0.3V)

REFCOMP Voltage (Note 4) ......... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage.................. –0.3V to (V_DD+ 0.3V)

Power Dissipation............................................. 500mW

Operating Temperature Range .................... 0°C to 70°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

A

1

2

3

4

5

6

7

8

9

36 AV

35 AV

PART NUMBER

IN

DD

IN

DD

V

34

V

SS

REF

LTC1608CG

LTC1608ACG

REFCOMP

AGND

33 SHDN

32 CS

AGND

31 CONV

30 RD

AGND

29 OV

DD

DV

28 OGND

27 BUSY

26 D0

25 D1

24 D2

23 D3

22

DD

DGND 10

D15 (MSB) 11

D14 12

D13 13

D12 14

D11

15

D4

D10 16

D9 17

21 D5

20 D6

19 D7

D8 18

G PACKAGE

36-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/W

Consult factory for parts specified with wider operating temperature ranges.

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CO VERTER

CHARACTERISTICS

The ● denotes specifications that apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted.

LTC1608

TYP

LTC1608A

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Transition Noise

Offset Error

●

15

16

±1

0.7

16

±0.5

0.7

(Note 7)

(Note 8)

(Note 9)

±4

±2

LSB

RMS

●

±0.05 ±0.125

% FSR

Offset Tempco

0.5

ppm/°C

Full-Scale Error

Internal Reference

External Reference

±0.125 ±0.25

±0.25

±0.125 ±0.25

±0.25

%

Full-Scale Tempco

I

(Reference) = 0, Internal Reference

OUT

±15

ppm/°C

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The ● denotes specifications that apply over the full operating temperature range, otherwise

A ALOG I PUT

specifications are at T_A= 25°C.

SYMBOL PARAMETER

CONDITIONS

4.75 ≤ V ≤ 5.25V, –5.25 ≤ V ≤ –4.75V,

MIN

TYP

MAX

UNITS

V

Analog Input Range (Note 2)

±2.5

V

IN

DD

SS

–

+

V

≤ (A , A ) ≤ AV

SS

IN IN DD

I

Analog Input Leakage Current

Analog Input Capacitance

CS = High

●

±1

µA

IN

C

Between Conversions

During Conversions

43

5

pF

IN

t

Sample-and-Hold Acquisition Time

380

–1.5

5

ns

ACQ

AP

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Time Jitter

Analog Input Common Mode Rejection Ratio

ps

jitter

RMS

–

+

CMRR

–2.5V < (A = A ) < 2.5V

68

dB

IN

2

LTC1608

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T_A= 25°C (Note 5)

DY A IC ACCURACY

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

S/N

Signal-to-Noise Ratio

5kHz Input Signal

100kHz Input Signal

90

88

dB

S/(N + D)

THD

Signal-to-(Noise + Distortion) Ratio

5kHz Input Signal

100kHz Input Signal (Note 10)

90

84

dB

Total Harmonic Distortion

Up to 5th Harmonic

5kHz Input Signal

100kHz Input Signal

–100

–91

dB

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

100kHz Input Signal

94

–88

5

dB

f

= 29.37kHz, f = 32.446kHz

IN2

IN1

Full Power Bandwidth

MHz

kHz

Full Linear Bandwidth (S/(N + D) ≥ 84dB)

350

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I TER AL REFERE CE CHARACTERISTICS ^T_A^{= 25°C (Note 5)}

PARAMETER

CONDITIONS

MIN

TYP

2.500

±15

MAX

UNITS

V

REF

V

REF

V

REF

Output Voltage

Output Tempco

Line Regulation

I

= 0

2.475

2.515

OUT

ppm/°C

4.75 ≤ V ≤ 5.25V

–5.25V ≤ V ≤ –4.75V

0.01

LSB/V

DD

SS

V

REF

Output Resistance

0 ≤

I

≤ 1mA

OUT

7.5

kΩ

REFCOMP Output Voltage

I

= 0

4.375

V

OUT

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DIGITAL I PUTS A D DIGITAL OUTPUTS ^The● denotes specifications that apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

●

2.4

V

IH

IL

DD

IN

0.8

I

±10

µA

pF

IN

DD

C

V

5

IN

V

DD

V

DD

= 4.75V, I

= –10µA

= –400µA

4.5

V

OH

OUT

●

4.0

V

Low Level Output Voltage

V

= 4.75V, I

= 160µA

= 1.6mA

0.05

0.10

V

OL

DD

OUT

●

0.4

±10

15

I

Hi-Z Output Leakage D15 to D0

Hi-Z Output Capacitance D15 to D0

Output Source Current

V

OUT

= 0V to V , CS High

µA

pF

OZ

DD

C

OZ

CS High (Note 11)

I

V

OUT

V

OUT

= 0V

–10

10

mA

SOURCE

SINK

Output Sink Current

= V

DD

3

LTC1608

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POWER REQUIRE E TS ^The● denotes specifications that apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Notes 12, 13)

(Note 12)

MIN

4.75

TYP

MAX

5.25

UNITS

V

Positive Supply Voltage

Negative Supply Voltage

V

DD

SS

–4.75

–5.25

I

Positive Supply Current

Nap Mode

CS = RD = 0V

●

22

1.5

1

35

2.4

100

mA

µA

DD

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

I

Negative Supply Current

Nap Mode

CS = RD = 0V

32

1

49

100

mA

µA

SS

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

P

Power Dissipation

Nap Mode

CS = RD = 0V

270

7.5

0.01

420

12

1

mW

D

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

Sleep Mode

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TI I G CHARACTERISTICS

The ● denotes specifications that apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

500

1.0

TYP

600

1.45

MAX

UNITS

kHz

µs

f

t

Maximum Sampling Frequency

Conversion Time

●

SMPL(MAX)

1.8

400

2

CONV

Acquisition Time

(Notes 11, 14)

ns

ACQ

Throughput Time (Acquisition + Conversion)

CS to RD Setup Time

1.67

µs

ACQ+CONV(MIN)

(Notes 11, 12, 15)

(Notes 11, 12)

CS = Low (Note 12)

(Note 12)

0

ns

1

2

3

4

5

6

CS↓ to CONVST↓ Setup Time

SHDN↓ to CS↑ Setup Time

SHDN↑ to CONVST↓ Wake-Up Time

CONVST Low Time

10

ns

400

ns

●

40

ns

CONVST to BUSY Delay

C = 25pF

L

36

60

ns

80

t

Data Ready Before BUSY↑

ns

7

●

32

200

–5

t

Delay Between Conversions

Wait Time RD↓ After BUSY↑

Data Access Time After RD↓

(Note 12)

ns

8

9

C = 25pF

L

25

45

30

40

50

ns

10

●

C = 100pF (Note 11)

L

60

75

ns

t

Bus Relinquish Time

50

60

ns

11

●

t

RD Low Time

(Note 12)

t

ns

12

13

14

10

CONVST High Time

40

Aperture Delay of Sample-and-Hold

2

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND, OGND

Note 3: When these pin voltages are taken below V or above V , they

SS DD

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below V or above V without latchup.

SS

DD

and AGND wired together unless otherwise noted.

4

LTC1608

ELECTRICAL CHARACTERISTICS

Note 4: When these pin voltages are taken below V , they will be clamped

Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion

is measured at 100kHz. These results are used to calculate Signal-to-Nosie

Plus Distortion (SINAD).

SS

by internal diodes. This product can handle input currents greater than

100mA below V without latchup. These pins are not clamped to V

.

SS

DD

Note 5: V = 5V, V = –5V, f

otherwise specified.

= 500kHz, and t = t = 5ns unless

Note 11: Guaranteed by design, not subject to test.

Note 12: Recommended operating conditions.

DD

SS

SMPL

r

f

Note 6: Linearity, offset and full-scale specification apply for a single-

Note 13: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For

best performance ensure that CONVST returns high either within 250ns

after conversion start or after BUSY rises.

Note 14: The acquisition time would go up to 400ns and the conversion

time would go up to 1.8µs. However, the throughput time (acquisition +

conversion) is guaranteed by test to be 2µs max.

+

–

ended A input with A grounded.

IN

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Typical RMS noise at the code transitions.

Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code flickers between 0000 0000 0000 0000 and 1111 1111

1111 1111.

Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓.

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TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

S/(N + D) vs Input Frequency

and Amplitude

1.0

0.8

2.0

1.5

100

90

80

70

60

50

40

30

20

10

0

V

= 0dB

IN

0.6

1.0

V

= –20dB

= –40dB

IN

0.4

0.5

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

0

16384

32767

–32768

–16384

0

16384

32767

1k

10k

FREQUENCY (Hz)

100k

1M

–32768

–16384

CODE

1608 G01

1608 G02

1608 G03

Signal-to-Noise Ratio

vs Input Frequency

Spurious-Free Dynamic Range

vs Input Frequency

Distortion vs Input Frequency

100

90

80

70

60

50

40

30

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

THD

3RD

2ND

10k

FREQUENCY (Hz)

1k

10k

100k

1M

10k

INPUT FREQUENCY (Hz)

1k

100k

1M

1k

100k

1M

INPUT FREQUENCY (Hz)

1608 G04

1608 G05

1608 G06

5

LTC1608

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TYPICAL PERFOR A CE CHARACTERISTICS

Power Supply Feedthrough

vs Ripple Frequency

Input Common Mode Rejection

vs Input Frequency

Intermodulation Distortion

0

–20

80

70

60

50

40

30

20

10

0

f

= 500kHz

= 10mV

RIPPLE

f

= 500kHz

SAMPLE

V

SAMPLE

IN1

IN2

= 96.56kHz

–20

= 99.98kHz

–40

–60

–80

–100

–120

–140

–100

–120

–140

A

VDD

V

SS

1k

10k

100k

1M

50

100

150

250

1k

10k

100k

1M

0

200

INPUT FREQUENCY (Hz)

FREQUENCY (kHz)

1608 G08

1608 G07

1608 G14a

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PI FU CTIO S

A_IN⁺(Pin 1): Positive Analog Input. The ADC converts the

OGND (Pin 28): Digital Ground for Output Drivers.

difference voltage between A_IN⁺and A_IN^–with a differen-

OV_DD(Pin 29): Digital Power Supply for Output Drivers.

Bypass to OGND with 10µF tantalum in parallel with 0.1µF

ceramic.

+

tial range of ±2.5V. A_INhas a ±2.5V input range when

–

A_INis grounded.

A_IN^–(Pin2):NegativeAnalogInput. Canbegrounded, tied

RD (Pin 30): Read Input. A logic low enables the output

drivers when CS is low.

+

to a DC voltage or driven differentially with A_IN

.

V_REF(Pin3):2.5VReferenceOutput.BypasstoAGNDwith

2.2µF tantalum in parallel with 0.1µF ceramic.

CONVST (Pin 31): Conversion Start Signal. This active

low signal starts a conversion on its falling edge when CS

is low.

REFCOMP (Pin 4):4.375V (Nominal) Reference Compen-

sation Pin. Bypass to AGND with 22µF tantalum in parallel

with 0.1µF ceramic. This is not recommended for use as

an external reference due to part-to-part output voltage

variations and glitches that occur during the conversion.

CS(Pin32):TheChipSelectInput.MustbelowfortheADC

to recognize CONVST and RD inputs.

SHDN (Pin 33): Power Shutdown. Drive this pin low with

CS low for nap mode. Drive this pin low with CS high for

sleep mode.

AGND(Pins5to8):AnalogGrounds. Tietoanalogground

plane.

V_SS(Pin 34): –5V Negative Supply. Bypass to AGND with

10µF tantalum in parallel with 0.1µF ceramic.

DV_DD(Pin 9): 5V Digital Power Supply. Bypass to DGND

with 10µF tantalum in parallel with 0.1µF ceramic.

AV_DD(Pin 35): 5V Analog Power Supply. Bypass to AGND

with 10µF tantalum in parallel with 0.1µF ceramic.

DGND (Pin 10): Digital Ground for Internal Logic. Tie to

analog ground plane.

AV_DD(Pin 36): 5V Analog Power Supply. Bypass to AGND

with 10µF tantalum in parallel with 0.1µF ceramic and

connect this pin to Pin 35 with a 10Ω resistor.

D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15

is the Most Significant Bit.

BUSY (Pin 27): The BUSY output shows the converter

status. It is low when a conversion is in progress. Data is

valid on the rising edge of BUSY.

6

LTC1608

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W

FU CTIO AL BLOCK DIAGRA

10µF

2.2µF

10µF

5V 10µF

5V

10Ω

+

3

10

36

DD

35

9

V

AV

DD

DV

DGND

REF

DD

SHDN

CS

33

32

31

30

27

CONTROL

LOGIC

µP

CONVST

RD

CONTROL

LINES

REFCOMP

7.5k

AND

4

2.5V

REF

1.75X

TIMING

+

4.375V

BUSY

22µF

OV

DD

29

28

5V OR

+

3V

10µF

+

OGND

1

2

A

IN

+

DIFFERENTIAL

ANALOG INPUT

±2.5V

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

–

A

IN

D15 TO D0

–

11 TO 26

AGND AGND AGND AGND

V

SS

34

1608 BD

5

6

7

8

10µF

+

–5V

TEST CIRCUITS

Load Circuits for Access Timing

Load Circuits for Output Float Delay

5V

1k

DN

1k

C

L

C

L

C

L

(A) Hi-Z TO V AND V TO V

OH OL OH

(B) Hi-Z TO V AND V TO V

OL OH

(A) V TO Hi-Z

OH

(B) V TO Hi-Z

OL

1608 TC01

1608 TC02

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APPLICATIO S I FOR ATIO

CONVERSION DETAILS

During the conversion, the internal differential 16-bit

capacitive DAC output is sequenced by the SAR from the

Most Significant Bit (MSB) to the Least Significant Bit

The LTC1608 uses a successive approximation algorithm

and internal sample-and-hold circuit to convert an analog

signaltoa16-bitparalleloutput. TheADCiscompletewith

a sample-and-hold, a precision reference and an internal

clock. The control logic provides easy interface to micro-

processors and DSPs. (Please refer to the Digital Interface

section for the data format.)

+

–

(LSB). Referring to Figure 1, the A_INand A_INinputs are

acquired during the acquire phase and the comparator

offset is nulled by the zeroing switches. In this acquire

phase,adurationof480nswillprovideenoughtimeforthe

sample-and-hold capacitors to acquire the analog signal.

Duringtheconvertphase,thecomparatorzeroingswitches

open, putting the comparator into compare mode. The

input switches connect the C_SMPLcapacitors to ground,

transferring the differential analog input charge onto the

summing junctions. This input charge is successively

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion, the successive

approximation register (SAR) resets. Once a conversion

cycle has begun, it cannot be restarted.

7

LTC1608

APPLICATIO S I FOR ATIO

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3V Input/Output Compatible

C

SMPL

SAMPLE

+

A

IN

The LTC1608 operates on ±5V supplies, which makes the

device easy to interface to 5V digital systems. This device

can also talk to 3V digital systems: the digital input pins

(SHDN, CS, CONVST and RD) of the LTC1608 recognize

3V or 5V inputs. The LTC1608 has a dedicated output

supply pin (OV_DD) that controls the output swings of the

digital output pins (D0 to D15, BUSY) and allows the part

to talk to either 3V or 5V digital systems. The output is

two’s complement binary.

HOLD

ZEROING SWITCHES

HOLD

C

SMPL

SAMPLE

–

A

IN

HOLD

+C

DAC

+

–C

COMP

–

+V

DAC

Power Shutdown

–V

DAC

The LTC1608 provides two power shutdown modes, Nap

and Sleep, to save power during inactive periods. The Nap

mode reduces the power by 95% and leaves only the

digital logic and reference powered up. The wake-up time

from Nap to active is 200ns. In Sleep mode, all bias

currents are shut down and only leakage current remains

(about 1µA). Wake-up time from Sleep mode is much

longer since the reference circuit must power up and

settle. Sleep mode wake-up time is dependent on the

value of the capacitor connected to the REFCOMP (Pin 4).

The wake-up time is 80ms with the recommended 22µF

capacitor.

16

D15

D0

•

OUTPUT

LATCHES

SAR

1608 F01

Figure 1. Simplified Block Diagram

compared with the binary-weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion, the

differential DAC output balances the A_INand A_INinput

charges. The SAR contents (a 16-bit data word) which

represent the difference of A_INand A_INare loaded into

the 16-bit output latches.

+

–

+

–

Shutdown is controlled by Pin 33 (SHDN). The ADC is in

shutdown when SHDN is low. The shutdown mode is

selected with Pin 32 (CS). When SHDN is low, CS low

selects nap and CS high selects sleep.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro-

cessors as a memory mapped device. The CS and RD

control inputs are common to all peripheral memory

interfacing. A separate CONVST is used to initiate a con-

version.

SHDN

t

3

CS

1608 F02a

Internal Clock

Figure 2a. Nap Mode to Sleep Mode Timing

The A/D converter has an internal clock that runs the A/D

conversion.Theinternalclockisfactorytrimmedtoachieve

a typical conversion time of 1.45µs and a maximum

conversion time of 1.8µs over the full temperature range.

No external adjustments are required. The guaranteed

maximumacquisitiontimeis400ns.Inaddition,athrough-

put time (acquisition + conversion) of 2µs and a minimum

sampling rate of 500ksps are guaranteed.

SHDN

t

4

CONVST

1608 F02b

Figure 2b. SHDN to CONVST Wake-Up Timing

8

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

(e.g., CONVST low time >t_CONV), accuracy is unaffected.

For best results, keep t₅less than 500ns or greater than

CS

CONVST

RD

t

2

t_CONV

.

Figures 5 through 9 show several different modes of

operation. In modes 1a and 1b (Figures 5 and 6), CS and

RDarebothtiedlow.ThefallingedgeofCONVSTstartsthe

conversion. The data outputs are always enabled and data

can be latched with the BUSY rising edge. Mode 1a shows

operationwithanarrowlogiclowCONVSTpulse. Mode1b

shows a narrow logic high CONVST pulse.

t

1

1608 F03

Figure 3. CS top CONVST Setup Timing

4

3

2

1

0

In mode 2 (Figure 7) CS is tied low. The falling edge of

CONVST signal starts the conversion. Data outputs are in

three-stateuntilreadbytheMPUwiththeRDsignal. Mode

2 can be used for operation with a shared data bus.

t

ACQ

CONV

In slow memory and ROM modes (Figures 8 and 9), CS is

tied low and CONVST and RD are tied together. The MPU

starts the conversion and reads the output with the com-

bined CONVST-RD signal. Conversions are started by the

MPU or DSP (no external sample clock is needed).

750

1000

0

250

500

1250

1500 1750

2000

CONVST LOW TIME, t (ns)

5

In slow memory mode, the processor applies a logic low

to RD (= CONVST), starting the conversion. BUSY goes

low, forcing the processor into a wait state. The previous

conversion result appears on the data outputs. When the

conversion is complete, the new conversion results

appear on the data outputs; BUSY goes high, releasing the

processor and the processor takes RD (=CONVST) back

high and reads the new conversion data.

1608 F04

Figure 4. Change in DNL vs CONVST Low Time. Be Sure the

CONVST Pulse Returns High Early in the Conversion or After

the End of Conversion

Timing and Control

Conversion start and data read operations are controlled

by three digital inputs: CONVST, CS and RD. A falling edge

applied to the CONVST pin will start a conversion after the

ADC has been selected (i.e., CS is low). Once initiated, it

cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output. BUSY is

low during a conversion.

In ROM mode, the processor takes RD (=CONVST) low,

startingaconversionandreadingthepreviousconversion

result. Aftertheconversioniscomplete, theprocessorcan

read the new result and initiate another conversion.

DIFFERENTIAL ANALOG INPUTS

Driving the Analog Inputs

We recommend using a narrow logic low or narrow logic

high CONVST pulse to start a conversion as shown in

Figures 5 and 6. A narrow low or high CONVST pulse

prevents the rising edge of the CONVST pulse from upset-

ting the critical bit decisions during the conversion time.

Figure 4 shows the change of the differential nonlinearity

error versus the low time of the CONVST pulse. As shown,

if CONVST returns high early in the conversion (e.g.,

CONVST low time <300ns), accuracy is unaffected. Simi-

larly, if CONVST returns high after the conversion is over

The differential analog inputs of the LTC1608 are easy to

drive.Theinputsmaybedrivendifferentiallyorasasingle-

endedinput(i.e.,theA_IN^–inputisgrounded).TheA_IN⁺and

–

A_INinputs are sampled at the same instant. Any un-

wanted signal that is common mode to both inputs will be

reduced by the common mode rejection of the sample-

and-hold circuit. The inputs draw only one small current

9

LTC1608

APPLICATIO S I FOR ATIO

W U U

U

t

CONV

CS = RD = 0

t

5

CONVST

t

8

6

BUSY

DATA

t

7

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1608 F05

Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

)

t

CS = RD = 0

CONVST

t

8

CONV

t

5

13

t

6

BUSY

DATA

t

7

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1608 F06

Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

)

t

13

t

8

CS = 0

CONV

5

CONVST

BUSY

RD

t

6

t

11

9

t

12

t

10

DATA N

D15 TO D0

DATA

1608 F07

Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD

10

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

t

8

CS = 0

CONV

RD = CONVST

t

11

6

BUSY

DATA

t

7

10

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

1608 F08

Figure 8. Mode 2. Slow Memory Mode Timing

t

8

CONV

CS = 0

RD = CONVST

t

11

6

BUSY

t

10

DATA (N – 1)

D15 TO D0

DATA N

D15 TO D0

DATA

1608 F09

Figure 9. ROM Mode Timing

10

1

spike while charging the sample-and-hold capacitors at

the end of conversion. During conversion, the analog

inputs draw only a small leakage current. If the source

impedance of the driving circuit is low, then the LTC1608

inputs can be driven directly. As source impedance in-

creases so will acquisition time (see Figure 10). For

minimum acquisition time with high source impedance, a

buffer amplifier should be used. The only requirement is

that the amplifier driving the analog input(s) must settle

after the small current spike before the next conversion

starts (settling time must be 200ns for full throughput

rate).

0.1

0.01

1

10

100

1k

10k

SOURCE RESISTANCE (Ω)

1608 F10

Choosing an Input Amplifier

Figure 10. t_ACQvs Source Resistance

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a

lowoutputimpedance(<100Ω)attheclosed-loopband-

width frequency. For example, if an amplifier is used in a

gainof+1andhasaunity-gainbandwidthof50MHz,then

the output impedance at 50MHz should be less than

100Ω. The second requirement is that the closed-loop

bandwidth must be greater than 15MHz to ensure

adequate small-signal settling for full throughput rate. If

slower op amps are used, more settling time can be

provided by increasing the time between conversions.

11

LTC1608

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U

APPLICATIO S I FOR ATIO

The best choice for an op amp to drive the LTC1608 will

dependontheapplication. Generallyapplicationsfallinto

two categories: AC applications where dynamic specifi-

cations are most critical and time domain applications

where DC accuracy and settling time are most critical.

The following list is a summary of the op amps that are

suitable for driving the LTC1608. More detailed informa-

tion is available in the Linear Technology databooks, the

LinearView^TMCD-ROM and on our web site at:

minimize noise. A simple 1-pole RC filter is sufficient for

manyapplications.Forexample,Figure11showsa3000pF

capacitor from A_IN⁺to ground and a 100Ω source resistor

to limit the input bandwidth to 530kHz. The 3000pF

capacitor also acts as a charge reservoir for the input

sample-and-hold and isolates the ADC input from sam-

pling glitch sensitive circuitry. High quality capacitors and

resistors should be used since these components can add

distortion. NPO and silver mica type dielectric capacitors

haveexcellentlinearity.Carbonsurfacemountresistorscan

also generate distortion from self heating and from damage

that may occur during soldering. Metal film surface mount

resistors are much less susceptible to both problems.

www.linear-tech. com.

LT^®1007: Low Noise Precision Amplifier. 2.7mA supply

current, ±5V to ±15V supplies, gain bandwidth product

8MHz, DC applications.

100Ω

LT1097:LowCost, LowPowerPrecisionAmplifier. 300µA

supply current, ±5V to ±15V supplies, gain bandwidth

product 0.7MHz, DC applications.

1

+

ANALOG INPUT

A

V

IN

3000pF

2

3

4

5

–

IN

LTC1608

LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA

supply current, ±5V to ±15V supplies, low noise and low

distortion.

REF

REFCOMP

AGND

22µF

LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup-

ply current, ±5V to ±15V supplies, good AC/DC specs.

1608 F11

LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-

ply current, good AC/DC specs.

Figure 11. RC Input Filter

Input Range

LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback

Amplifiers. 6.3mA supply current per amplifier, good

AC/DC specs.

The±2.5VinputrangeoftheLTC1608isoptimizedforlow

noise and low distortion. Most op amps also perform well

over this same range, allowing direct coupling to the

analog inputs and eliminating the need for special transla-

tion circuitry.

LT1468: 90MHz, 22V/µs 16-Bit Accurate Operational

Amplifier. 3.8mA supply current, excellent DC specs and

very low distortion performance to 100kHz.

Some applications may require other input ranges. The

LTC1608differentialinputsandreferencecircuitrycanac-

commodate other input ranges often with little or no addi-

tional circuitry. The following sections describe the refer-

enceandinputcircuitryandhowtheyaffecttheinputrange.

LT1469: Dual 90MHz, 22V/µs 16-Bit Accurate Operational

Amplifier. 4.1mA supply current, excellent DC specs and

very low distortion performance to 100kHz.

Input Filtering

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1608 noise and distortion. The small-signal band-

width of the sample-and-hold circuit is 15MHz. Any noise

ordistortionproductsthatarepresentattheanaloginputs

will be summed over this entire bandwidth. Noisy input

circuitry should be filtered prior to the analog inputs to

Internal Reference

The LTC1608 has an on-chip, temperature compensated,

curvature corrected, bandgap reference that is factory

trimmedto2.500V.Itisconnectedinternallytoareference

amplifier and is available at V_REF(Pin 3) (see Figure 12a).

LinearView is a trademark of Linear Technology Corporation.

12

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

1

2

3

4

5

R1

7.5k

+

–

A

V

IN

V

ANALOG INPUT

2V TO 2.7V

3

REF

BANDGAP

REFERENCE

2.500V

DIFFERENTIAL

IN

LTC1608

REFCOMP

4

REFERENCE

AMP

2V TO 2.7V

4.375V

LTC1450

REF

R2

12k

REFCOMP

AGND

22µF

R3

16k

AGND

5

LTC1608

1608 F13

1608 F12a

Figure 13. Driving V_REFwith a DAC

Figure 12a. LTC1608 Reference Circuit

Differential Inputs

5V

1

2

3

+

–

A

V

IN

The LTC1608 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

ANALOG

INPUT

V

IN

LT1019A-2.5

+

–

convert the difference of A_IN– A_INindependent of the

common mode voltage (see Figure 15a). The common

mode rejection holds up to extremely high frequencies

(see Figure 14a). The only requirement is that both inputs

can not exceed the AV_DDor V_SSpower supply voltages.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) are independent of the common mode

voltage, however, the bipolar zero error (BZE) will vary.

The change in BZE is typically less than 0.1% of the

common mode voltage. Dynamic performance is also

affected by the common mode voltage. THD will degrade

astheinputsapproacheitherpowersupplyrail,from96dB

with a common mode of 0V to 86dB with a common mode

of 2.5V or –2.5V.

V

OUT

REF

LTC1608

4

REFCOMP

+

22µF

0.1µF

5

AGND

1608 F12b

Figure 12b. Using the LT1019-2.5 as an External Reference

A 7.5k resistor is in series with the output so that it can be

easily overdriven by an external reference or other

circuitry (see Figure 12b). The reference amplifier gains

the voltage at the V_REFpin by 1.75 to create the required

internal reference voltage. This provides buffering

between the V_REFpin and the high speed capacitive DAC.

Thereferenceamplifiercompensationpin(REFCOMP, Pin

4) must be bypassed with a capacitor to ground. The

reference amplifier is stable with capacitors of 22µF or

greater.Usinga0.1µFceramicinparallelisrecommended.

80

70

60

50

40

30

20

10

0

The V_REFpin can be driven with a DAC or other means

showninFigure13.Thisisusefulinapplicationswherethe

peak input signal amplitude may vary. The input span of

the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1608 reference amplifier will limit

the bandwidth and settling time of this circuit. A settling

time of 20ms should be allowed for after a reference

adjustment.

1k

10k

100k

1M

INPUT FREQUENCY (Hz)

1608 G14a

Figure 14a. CMRR vs Input Frequency

13

LTC1608

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U

APPLICATIO S I FOR ATIO

Differential inputs allow greater flexibility for accepting

different input ranges. Figure 14b shows a circuit that

converts a 0V to 5V analog input signal with only an

additional buffer that is not in the signal path.

011...111

011...110

000...001

000...000

111...111

111...110

1

2

+

–

ANALOG INPUT

A

IN

0V TO

5V

3

+

–

V

REF

100...001

100...000

±2.5V

LTC1608

–(FS – 1LSB)

INPUT VOLTAGE (A – A

FS – 1LSB

+

–

)

IN

4

IN

REFCOMP

AGND

1608 F15a

22µF

5

Figure 15a. LTC1608 Transfer Characteristics

1608 F14b

ANALOG

INPUT

1

2

+

–

A

IN

Figure 14b. Selectable 0V to 5V or ±2.5V Input Range

IN

R1

LTC1662

R2

100Ω

40.2k

Full-Scale and Offset Adjustment

CS/LD

SCK

SDI

V

OUTA

GND

V

CC

OUTB

LTC1608

Figure 15a shows the ideal input/output characteristics

for the LTC1608. The code transitions occur midway

between successive integer LSB values (i.e., –FS +

0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,

FS – 0.5LSB). The output is two’s complement binary with

1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3µV.

3

R3

1.5M

V

REF

5V

REF

V

+

2.2µF

4

5

REFCOMP

AGND

+

0.1µF

80.6k

1%

22µF

–5V

OFFSET ADJ RANGE: ±0.125%

FULL-SCALE ADJ RANGE: ±0.25%

1608 F15b

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 15b

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the offset

Figure 15b. Offset and Full-Scale Adjust Circuit

groundplaneisrequired.Layoutshouldensurethatdigital

andanalogsignallinesareseparatedasmuchaspossible.

Particular care should be taken not to run any digital track

alongsideananalogsignaltrackorunderneaththeADC.The

analog input should be screened by AGND.

–

applied to the A_INinput. For zero offset error, apply

+

–38µV (i.e., –0.5LSB) at A_INand adjust the offset at the

A_IN^–input by varying the output voltage of pin V_OUTAfrom

the LTC1662 until the output code flickers between 0000

0000 0000 0000 and 1111 1111 1111 1111. For full-scale

adjustment,aninputvoltageof2.499886V(FS/2–1.5LSBs)

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other

analog grounds should be connected to this single analog

ground point. The REFCOMP bypass capacitor and the

DV_DDbypass capacitor should also be connected to this

analog ground plane. No other digital grounds should be

connected to this analog ground plane. Low impedance

analog and digital power supply common returns are

essential to low noise operation of the ADC and the foil

width for these tracks should be as wide as possible. In

+

is applied to A_INand the output voltage of pin V_OUTBis

adjusted until the output code flickers between 0111 1111

1111 1110 and 0111 1111 1111 1111.

BOARD LAYOUT AND GROUNDING

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best per-

formance from the LTC1608, a printed circuit board with

14

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feedthrough from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversion or by

using three-state buffers to isolate the ADC data bus. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

EXAMPLE LAYOUT

Figures 17a, 17b, 17c, 17d and 17e show the schematic

and layout of an evaluation board. The layout demon-

stratestheproperuseofdecouplingcapacitorsandground

plane with a 4-layer printed circuit board.

DC PERFORMANCE

The noise of an ADC can be evaluated in two ways: signal-

to-noise raio (SNR) in frequency domain and histogram in

time domain. The LTC1608 excels in both. Figure 19a

demonstrates that the LTC1608 has an SNR of over 90dB

in frequency domain. The noise in the time domain histo-

gram is the transition noise associated with a high resolu-

tion ADC which can be measured with a fixed DC signal

applied to the input of the ADC. The resulting output codes

are collected over a large number of conversions. The

shape of the distribution of codes will give an indication of

the magnitude of the transition noise. In Figure 18, the

distribution of output codes is shown for a DC input that

hasbeendigitized4096times.ThedistributionisGaussian

and the RMS code transition noise is about 0.66LSB. This

correspondstoanoiselevelof90.9dBrelativetofullscale.

Adding to that the theoretical 98dB of quantization error

for 16-bit ADC, the resultant corresponds to an SNR level

of 90.1dB which correlates very well to the frequency

domain measurements in Dynamic Performance section.

The LTC1608 has differential inputs to minimize noise

coupling. CommonmodenoiseontheA_IN⁺andA_IN^–leads

will be rejected by the input CMRR. The A_IN^–input can be

+

used as a ground sense for the A_INinput; the LTC1608

+

will hold and convert the difference voltage between A_IN

and A_IN^–. The leads to A_IN⁺(Pin 1) and A_IN^–(Pin 2) should

be kept as short as possible. In applications where this is

not possible, the A_INand A_INtraces should be run side

by side to equalize coupling.

+

–

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10µF or 22µF

bypasscapacitorsshouldbeusedattheV_DDandREFCOMP

pins as shown in Figure 16 and in the Typical Application

on the first page of this data sheet. Surface mount ceramic

capacitors such as Taiyo Yuden’s LMK325BJ106MN and

LMK432BJ226MM provide excellent bypassing in a small

board space. Alternatively, 10µF tantalum capacitors in

parallel with 0.1µF ceramic capacitors can be used. By-

pass capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypass

capacitorsmustbekeptshortandshouldbemadeaswide

as possible.

DYNAMIC PERFORMANCE

The LTC1608 has excellent high speed sampling capabil-

ity. Fast fourier transform (FFT) test techniques are used

to test the ADC’s frequency response, distortions and

1

+

DIGITAL

SYSTEM

LTC1608

AV AV

A

IN

–

A

IN

V

DV

DGND OV

10

OGND

28

REFCOMP AGND

REF

SS

DD

9

DD

29

ANALOG

INPUT

CIRCUITRY

2

3

4

5, 6, 7, 8 34

36

35

+

–

2.2µF

10µF

22µF

10µF 10µF 10µF

10µF

1608 F16

Figure 16. Power Supply Grounding Practice

15

LTC1608

W U U

U

APPLICATIO S I FOR ATIO

E5

3V

E2

–5V

C28

C8

0.1µF

R6

JP1

OV

DD

+

22µF

10Ω

E1

5V

OV

DD

+

C13

22µF

C12

22µF

U5

C7

1µF

E6

GND

TC7SH08FUTE85L

5V

J2

CONVERT

START

E3

REF

R2

R1

R4 10k

U1 LTC1608

R3

R5

V

JP3

C6

1µF

1

2

3

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

10k

51k

5V

10Ω

+

10k

+

A

AV

IN

DD1

C1

0.1µF

J1

CONN20

C11

–

2.2µF

AV

IN

DD2

C5 1µF

E7

GND

1

3

5

7

9

OV

DD

V

SS

REF

U2 MC74HC574ADT

C10 22µF 4

1

20

19

18

17

16

15

14

13

12

11

CLK

MSB

REFCOMP SHDN

OE

D0

D1

D2

D3

D4

D5

D6

D7

V

CC

5

6

7

2

AGND

CS

CONV

RD

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

3

11

4

OV

DD

C9

1µF

5V

8

9

C4 1µF

13

15

17

19

21

23

25

27

29

31

33

35

37

39

5

OV

DD

E4

GND

6

DV

OGND

BUSY

D0

DD

10

11

12

13

14

15

16

17

18

7

DGND

D15

D14

D13

D12

D11

D10

D9

8

9

D1

10

D2

GND CLK

D3

D4

C3 0.1µF

OV

D5

DD

U3 74HC574

D6

1

2

20

19

18

17

16

15

14

13

12

11

OE

D0

D1

D2

D3

D4

D5

D6

D7

V

CC

D8

D7

LSB

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

3

4

5

6

5V

C21

0.1µF

C27

100pF

7

8

R7

50Ω

9

J3

IN

3

2

8

OV

+

DD

+

A

10

+

1

U4A

LT1469

R17

10k

A

C14

1000pF

IN

GND CLK

(U1-1)

JP2

R11

50Ω

R13

50Ω

C20

0.1µF

–

4

U6

C25

100pF

–5V

R8 402Ω

C15 10pF

C17

10pF

TC7SH04F

C24

100pF

C26

1000pF

C18

10pF

R15

100Ω

C16 10pF

R9

6

402Ω

R14

50Ω

R12

–

50Ω

–

7

U4B

LT1469

A

IN

R10

50Ω

(U1-2)

J4

IN

5

C22

100pF

C23

100pF

–

+

A

R16

10k

C19

1000pF

Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic

16

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

Figure 17b. Suggested Evaluation Circuit Board.

Component Side Silkscreen and Signal Traces

Figure 17c. Suggested Evaluation Circuit Board.

Bottom Side Showing Signal Traces

ANALOG GROUND PLANE

DIGITAL GROUND PLANE

ANALOG GROUND PLANE

DIGITAL GROUND PLANE

Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1

Showing Separate Analog and Digital Ground Planes

Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2

Showing Separate Analog and Digital Ground Planes

2500

2000

1500

1000

500

noise at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined for

frequenciesoutsidethefundamental. Figures19aand19b

show typical LTC1608 FFT plots.

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental

input frequency to the RMS amplitude of all other fre-

quency components at the A/D output. The output is band

limited to frequencies from above DC and below half the

sampling frequency. Figure 19a shows a typical spectral

content with a 500kHz sampling rate and a 3kHz input.

0

–4

–5

–3 –2 –1

0

1

2

3

4

5

CODE

1608 F18

Figure 18. Histogram for 4096 Conversions

17

LTC1608

W U U

U

APPLICATIO S I FOR ATIO

98

92

86

80

74

68

62

56

50

16

0

f

= 500kHz

= 2.807kHz

SINAD = 88.9dB

THD = –98dB

SAMPLE

IN

15

14

13

12

11

10

9

–20

–40

–60

–80

–100

–120

–140

8

1k

10k

100k

1M

50

100

150

250

0

200

FREQUENCY (Hz)

FREQUENCY (kHz)

1608 F20

1608 F19a

Figure 20. Effective Bits and Signal/(Noise + Distortion)

vs Input Frequency

Figure 19a. This FFT of the LTC1608’s Conversion of a

Full-Scale 3kHz Sine Wave Shows Outstanding Response

with a Very Low Noise Floor When Sampling at 500ksps

Total Harmonic Distortion

0

f

= 500kHz

SAMPLE

IN

Total harmonic distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD is

expressed as:

= 98.754kHz

–20

SINAD = 86.7dB

THD = –92.6dB

–40

–60

–80

V2²+ V3²+ V4²+...Vn²

THD = 20Log

–100

–120

–140

V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

secondthroughnthharmonics.THDvsInputFrequencyis

shown in Figure 21. The LTC1608 has good distortion

performance up to the Nyquist frequency and beyond.

50

100

150

250

0

200

FREQUENCY (kHz)

1608 F19b

Figure 19b. Even with Inputs at 100kHz, the

LTC1608’s Dynamic Linearity Remains Robust

The dynamic performance is excellent for input frequen-

cies up to and beyond the Nyquist limit of 250kHz.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement of

the resolution of an ADC and is directly related to the

S/(N + D) by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

Iftwopuresinewavesoffrequenciesfaandfbareapplied

where ENOB is the effective number of bits of resolution to the ADC input, nonlinearities in the ADC transfer

and S/(N + D) is expressed in dB. At the maximum function can create distortion products at the sum and

samplingrateof500kHz, theLTC1608maintainsabove14 difference frequencies of mfa ±nfb, where m and n = 0,

bits up to the Nyquist input frequency of 250kHz (refer to 1, 2, 3, etc. Forexample, the2ndorderIMDtermsinclude

Figure 20).

18

LTC1608

W U U

APPLICATIO S I FOR ATIO

U

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

(fa ± fb). If the two input sine waves are equal in

magnitude, the value (in decibels) of the 2nd order IMD

products can be expressed by the following formula:

Amplitude at (fa ± fb)

IMD fa± fb = 20Log

(

)

Amplitude at fa

THD

3RD

2ND

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC. This

value is expressed in decibels relative to the RMS value of

a full-scale input signal.

10k

INPUT FREQUENCY (Hz)

1k

100k

1M

1608 F21

Figure 21. Distortion vs Input Frequency

Full-Power and Full-Linear Bandwidth

0

f

= 500kHz

SAMPLE

IN1

IN2

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is

reduced by 3dB for a full-scale input signal.

= 96.56kHz

–20

= 99.98kHz

–40

–60

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 84dB (13.66 effective bits).

The LTC1608 has been designed to optimize input band-

width, allowingtheADCtoundersampleinputsignalswith

frequenciesabovetheconverter’sNyquistFrequency. The

noise floor stays very low at high frequencies; S/(N + D)

becomes dominated by distortion at frequencies far

beyond Nyquist.

–80

–100

–120

–140

50

100

150

250

0

200

FREQUENCY (kHz)

1608 F22

Figure 22. Intermodulation Distortion Plot

U

PACKAGE DESCRIPTIO

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.67 – 12.93*

(.499 – .509)

5.20 – 5.38**

(.205 – .212)

1.73 – 1.99

(.068 – .078)

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

0° – 8°

7.65 – 7.90

(.301 – .311)

.65

(.0256)

BSC

.13 – .22

.55 – .95

(.005 – .009)

(.022 – .037)

.05 – .21

(.002 – .008)

.25 – .38

(.010 – .015)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G36 SSOP 0501

5

7

8

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1608

U

TYPICAL APPLICATIO

Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System

5V

2.2µF

10µF

5V 10µF

10Ω

36

+

LTC1391

3

35

10

9

1µF

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

+

DV

DD

V

AV

DGND

REF

DD

CH0

V

SHDN 33

CS 32

CH1

CH2

CH3

CH4

CH5

CH6

CH7

D

–

–5V

1µF

LTC1608

CONTROL

LOGIC

AND

TIMING

V

µP

CONTROL

LINES

CONVST 31

RD 30

7.5k

REFCOMP

4

D

OUT

2.5V

REF

1.75X

+

4.375V

D

IN

BUSY 27

22µF

CS

OV

DD

29

5V OR

3V

10µF

CLK

+

–

A

IN

1

+

–

OGND 28

CH7

CH0

GND

+

–

3000pF

16-BIT

SAMPLING

ADC

OUTPUT

BUFFERS

B15 TO B0

16-BIT

PARALLEL

BUS

5V

A

D15 TO D0

2

IN

LTC1391

1µF

11 TO 26

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

+

AGND AGND AGND AGND V

SS

34

V

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

1608 TA03

5

6

7

8

D

–

–5V

10µF

+

V

+

–5V

D

OUT

D

IN

µP

CONTROL

LINES

CS

CLK

–

GND

CH7

RELATED PARTS

SAMPLING ADCs

PART NUMBER

LTC1410

LTC1415

LTC1418

LTC1419

LTC1604

LTC1605

LTC1606

DESCRIPTION

COMMENTS

12-Bit, 1.25Msps, ±5V ADC

71.5dB SINAD at Nyquist, 150mW Dissipation

55mW Power Dissipation, 72dB SINAD

15mW, Serial/Parallel ±10V

12-Bit, 1.25Msps, Single 5V ADC

14-Bit, 200ksps, Single 5V ADC

Low Power 14-Bit, 800ksps ADC

16-Bit, 333ksps, ±5V ADC

True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation

90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608

±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606

±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605

16-Bit, 100ksps, Single 5V ADC

16-Bit, 250ksps, Single 5V ADC

DACs

PART NUMBER

DESCRIPTION

COMMENTS

LTC1595

16-Bit Serial Multiplying I

DAC in SO-8

DAC

±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors

Low Power, Low Gritch, 4-Quadrant Multiplication

OUT

LTC1596

OUT

LTC1597/LTC1591

LTC1650

16-Bit/14-Bit Parallel, Multiplying DACs

16-Bit Serial V DAC

OUT

1608f LT/TP 0601 2K • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 2000


型号：	LTC1608CG
厂家：	Linear
描述：	High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown 高速， 16位， 500KSPS采样A / D转换器，带有关断转换器
文件：	总20页 (文件大小：1003K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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