LTC1759 [Linear]
Smart Battery Charger; 智能电池充电器
| 型号： | LTC1759 |
| 厂家： | 
Linear |
| 描述： | Smart Battery Charger |
| 文件： | 总28页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1759
Smart Battery Charger
U
DESCRIPTIO
FEATURES
The LTC®1759 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construc-
tion of an SBS compliant system. The LTC1759 imple-
ments a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A thermistor
on the battery being charged is monitored for tempera-
ture,connectivityandbatterytypeinformation.TheSMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to it,
including thermistor status (via the ChargerStatus com-
mand). The charger also provides an interrupt to the host
whenever a status change is detected (e.g., battery
removal, AC adapter connection).
■
Single Chip Smart Battery Charger Controller
■
100% Compliant (Rev 1.0) SMBus Support
Allows for Operation with or without Host
■
SMBus Accelerator Improves SMBus Timing
■
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
■
High Efficiency Synchronous Buck Charger
■
0.5V Dropout Voltage; Maximum Duty Cycle > 99.5%
■
AC Adapter Current Limit Maximizes Charge Rate*
■
1% Voltage Accuracy; 5% Current Accuracy
■
Up to 8A Charging Current Capability
■
Dual 10-Bit DACs for Charger Voltage and Current
Programming
■
User-Selectable Overvoltage and Overcurrent Limits
Charging current and voltage are restricted to chemistry
specific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Addi-
tionally,themaximumaveragecurrentfromtheACadapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging cur-
rent. When supplying system load current, charging cur-
rent is automatically reduced to prevent adapter overload.
■
High Noise Immunity Thermistor Sensor
■
Small 36-Lead NUarrow (0.209") SSOP Package
APPLICATIO S
■
Portable Computers
■
Portable Instruments
■
Docking Stations
, LTC and LT are registered trademarks of Linear Technology Corporation.
*US Patent Number 5,723,970
U
TYPICAL APPLICATIO
15.8k
1k
0.033Ω
AC
ADAPTER
INPUT
+
10µF
35V
Al
0.1µF
LTC1759
V
22
21
8
7
16
4
DD
499Ω
UV
V
DCIN
0.1µF
DCDIV
INFET
0.47µF
DD
SYSTEM
POWER
SYNC
SDB
5
32
9
1µF
V
CC
12
25
24
18
17
28
27
11
6
22µF
CHGEN
CLP
CLN
33k
33k
10
2
V
LIMIT
0.1µF
2.2µF
I
TGATE
BOOSTC
GBIAS
BOOST
SW
LIMIT
33
34
1
15µH
0.025Ω
DGND
3.83k
0.68µF
I
+
SET
1µF
22µF
PROG
SMART
BATTERY
0.33µF
0.68µF
1.5k
1k
3
V
C
35
30
29
31
23
26
36
COMP1
AGND
RNR
BGATE
SPIN
200Ω
20
19
14
15
13
SENSE
BAT1
200Ω
THERM
SDA
V
DD
475k
BAT2
68Ω
SCL
V
SET
10k
1k
0.047µF
INTB
PGND
0.015µF
SMBus
INTB
TO
SCL
SDA
HOST
1759 F01
Figure 1. 4A SMBus Smart Battery Charger
1
LTC1759
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Voltage at VCC, UV, BAT1, CLP,CLN, SPIN,
SENSE with respect to AGND ....................–0.3V to 27V
Voltage at DCIN, BAT2 with Respect
BOOST
TGATE
SW
1
2
3
4
5
6
7
8
9
36 PGND
35 BGATE
34 GBIAS
33 BOOSTC
to DGND ....................................................–0.3V to 27V
Voltage at INTB, SDA, SCL, DCDIV with Respect
to DGND ..................................................... – 0.3V to 7V
BOOST, BOOSTC Voltage with Respect to VCC ........ 10V
Voltage at VDD with Respect to DGND ........ –0.3V to 7V
SW Voltage with Respect to AGND .............. –2V to VCC
GBIAS, SYNC ............................................ –0.3V to 10V
VC, PROG, VSET Voltage with Respect
to AGND ......................................................–0.3V to 7V
TGATE, BGATE Current Continuous .................. ±200mA
TGATE, BGATE Output Energy (per Cycle) ................ 2µJ
PGND, DGND with Respect to AGND .................... ±0.3V
Current into Any Pin ......................................... ±100mA
Operating Ambient Temperature Range...... 0°C to 70°C
Operating Junction
SYNC
SDB
LTC1759CG
32
V
CC
AGND
UV
31 BAT1
30 SPIN
29 SENSE
28 PROG
INFET
CLP
CLN 10
COMP1 11
CHGEN 12
INTB 13
27
26
25
24
V
V
V
C
SET
LIMIT
LIMIT
I
SDA 14
23 BAT2
22 DCIN
21 DCDIV
20 RNR
SCL 15
V
16
17
DD
I
SET
DGND 18
19 THERM
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/ W
Temperature Range .............................. –40°C to 125°C
Storage Temperature ........................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply and Reference
DCIN, V Operating Voltage
●
●
●
●
●
11
24
20
V
mA
µA
V
CC
V
Operating Current
V
V
≤ 24V
12
85
CC
CC
DCIN Operating Current
UV Lockout Threshold
UV Pin Input Current
= 24V
150
7.15
5
DCIN
Voltage on UV Pin Rising
0V ≤ V ≤ 8V
6.3
–1
6.7
µA
µA
V
UV
Battery Discharge Current
V
≤ 0.4V, All Connected Pins
40
80
UV
V
V
Operating Voltage
Operating Current
●
3.0
1.6
5.5
DD
DD
Charging, V = 5.5V, Shorted Thermistor
Not Charging, V = 5.5V
1.35
80
2
150
mA
µA
DD
DD
V
Undervoltage Lockout
●
●
2.2
2.9
V
DD
Switching Regulator
Charging Voltage Accuracy (Notes 3, 5)
Charging Current Accuracy (Note 3)
2.465V ≤ V
≤ V
–1
–5
1
5
%
%
BAT2
MAX
R
Tolerance = 1%
SET
2
LTC1759
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
= V + 8V, 0V ≤ V ≤ 20V
MIN
TYP
MAX
UNITS
BOOST Pin Current
V
BOOST
SW
SW
TGATE High
TGATE Low
2
2
3
3
mA
mA
V
Threshold to Turn T
Off
Measured at (V
– V
)
SW
BOOST
GATE
BOOST
(Note 6)
Low to High
Hysteresis
●
6.8
7.1
0.25
7.3
V
V
BOOSTC Pin Current
V
= V + 8V
1
mA
BOOSTC
CC
Sense Amplifier CA1 Gain and Input Offset Voltage 11V ≤ V ≤ 24V, 0V ≤ V
≤ 20V
CC
BAT
(With R = R = 200Ω)
R
R
= 4.93k
= 49.3k
●
●
92
7
100
10
108
13
mV
mV
S2
S3
SET
SET
(Measured Across R ) (Note 4)
S1
CA1 Bias Current (SENSE, BAT1)
V
V
= High
= Low (Shutdown)
–50
–120
–10
µA
µA
SDB
SDB
CA1 Input Common Mode Range
SPIN Input Current
●
●
–0.25
V
– 0.3
V
CC
V
V
= High, V
= Low
= 12.6V
SPIN
2
10
mA
µA
SDB
SDB
CL1 Turn-On Threshold
CL1 Transconductance
CLP Input Current
0.5mA Output Current
87
92
1
97
3
mV
mho
µA
Output Current from 50µA to 500µA
0.5mA Output Current
0.5
1
3
CLN Input Current
0.5mA Output Current
0.8
200
0.6
2
mA
CA2 Transconductance
V = 1V, I = ±1µA
150
300
1
µmho
mho
C
VC
V Transconductance (Note 5)
A
Ouput Current from 50µA to 500µA
0.21
Gate Drivers
V
V
V
V
V
V
≥ 11V, I
≤ 15mA, V = High
SDB
●
●
●
●
●
●
●
8.4
5.6
6.2
8.9
6.6
7.2
9.3
V
V
GBIAS
TGATE
BGATE
TGATE
BGATE
CC
GBIAS
High (V
High
– V
)
I
I
I
I
≤ 20mA
TGAGE
SW
TGATE
BGATE
TGATE
BGATE
≤ 20mA
≤ 50mA
≤ 50mA
V
Low (V
Low
– V
)
0.8
0.8
9
V
TGATE
SW
V
INFET “ON” Clamping Voltage (V – V
)
INFET
6.5
8
7.8
20
V
CC
INFET “ON” Drive Current
INFET “OFF” Clamping Voltage
INFET “OFF” Drive Current
V
V
V
V
= V – 6V
mA
V
INFET
CC
Not Connected, I < –2µA
= 12.4V, (V – V ) ≥ 2V
INFET
1.4
1
CC
INFET
–2.5
mA
V
CC
CC
V
, V
at Shutdown
= Low, I
= I = 10µA
BGATE
●
●
TGATE BGATE
SDB
TGATE
Trip Points
DCDIV Threshold
V
Rising from 0.8V to 1.2V
0.9
1.0
25
1.1
V
mV
nA
DCDIV
DCDIV Hysteresis
DCDIV Input Bias Current
V
= 1V
●
●
100
DCDIV
Power-Fail Indicator (V
≥ V
) (Note 7)
AC_PRESENT = 1, V
AC_PRESENT = 1, V
= 6V
= 6V
0.84
0.9
0.89
0.02
1.4
0.94
V/V
V/V
V
BAT2
DCIN
DCIN
Power-Fail Indicator Hysteresis (V
SYNC Pin Threshold
≥ V
)
DCIN
BAT2
DCIN
2.0
SYNC Pin Input Current
V
V
= 0V
= 2V
–500
–30
µA
µA
SYNC
SYNC
3
LTC1759
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Thermistor Decoder (Note 11)
Combined Input Leakage on RNR and THERM
Thermistor Trip (COLD/OR)
Thermistor Trip (IDEAL/COLD)
Thermistor Trip (HOT/IDEAL)
Thermistor Trip (UR/HOT)
DACs
200
120
33.6
3.36
560
nA
kΩ
kΩ
kΩ
Ω
R
R
R
R
= 475k ±1%
●
●
●
●
80
100
30
WEAK
= 10k ±1%
= 10k ±1%
= 1k ±1%
26.4
2.64
440
NR
NR
UR
3
500
Charging Current Resolution
Charging Current Granularity
Guaranteed Monotonic Above I
/16
10
bits
MAX
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0
1
2
4
8
mA
mA
mA
mA
= 10k ±1%
= 33k ±1%
= Open (or Short to V
)
)
DD
DD
Wake-Up Charging Current (I
) (Note 8)
80
mA
WAKE-UP
Charging Current Limit (I
)
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0
1023
2046
4092
8184
mA
mA
mA
mA
MAX
= 10k ±1%
= 33k ±1%
= Open (or Short to V
I
I
R
25
Ω
µA
SET DS(ON)
I
V
= 2.7V
ISET
●
1
SET OFF
Charging Voltage Resolution
Charging Voltage Granularity
Guaranteed Monotonic (2.5V ≤ V
≤ 21V)
10
bits
BAT
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
= 0
16
16
32
32
32
mV
mV
mV
mV
mV
= 10k ±1%
= 33k ±1%
= 100k ±1%
= Open (or Short to V
)
DD
Charging Voltage Limit
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
= 0
●
●
●
●
8.33
12.50
16.67
20.82
8.432
12.64
16.864
21.056
32.736
8.485
12.72
16.97
21.18
V
V
V
V
V
= 10k ±1%
= 33k ±1%
= 100k ±1%
= Open (or Short to V ) (Note 2)
DD
Logic Levels (Note 12)
SCL/SDA Input Low Voltage (V )
●
●
●
●
●
●
●
●
●
●
0.6
V
V
IL
SCL/SDA Input High Voltage (V )
1.4
IH
SDA Output Low Voltage (V
)
OL
I
= 350µA
0.4
1
V
PULLUP
SCL/SDA Input Current (I )
V
V
, V
= V
= V
µA
µA
V
IL
SDA SCL
IL
SCL/SDA Input Current (I )
, V
1
IH
SDA SCL
IH
INTB Output Low Voltage (V
)
OL
I
= 500µA
PULLUP
0.4
17.5
0.4
INTB Output Pull-Up Current
CHGEN Output Low Voltage (V
V
= V
3.5
10
µA
V
INTB
OL
)
OL
I
I
= 200µA
OL
OH
CHGEN Output High Voltage (V
SDB Shutdown Threshold
SDB Pin Current
)
= –200µA
V
– 0.4
DD
V
OH
1
2
8
V
0V ≤ V
≤ 3V
µA
µs
SDB
Power-On Reset Duration
V
Ramp from 0V to > 3V in < 5µs
100
DD
4
LTC1759
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Charger Timing
V
, V
Rise/Fall Time
1nF Load
25
1
ns
A
TGATE BGATE
TGATE, BGATE Peak Drive Current
Regulator Switching Frequency
10nF Load
●
●
●
●
170
240
85
200
230
280
kHz
kHz
%
Synchronization Frequency
Maximum Duty Cycle in Start-Up Mode (Note 9)
90
t
for Wake-Up Charging a
140
175
210
sec
TIMEOUT
Cold or Underrange Battery
SMBus Timing (refer to System Management Bus Specification, Revision 1.0, section 2.1 for timing diagrams) (Note 12)
SCL Serial Clock High Period (t
)
I
I
= 350µA, C
= 350µA, C
= 150pF
LOAD
= 150pF
= 150pF
●
●
●
●
●
●
●
●
●
4
µs
µs
ns
ns
mA
µs
µs
ns
ns
HIGH
PULLUP
LOAD
LOAD
SCL Serial Clock Low Period (t
)
4.7
LOW
PULLUP
SDA/SCL Rise Time (t )
C
1000
300
r
SDA/SCL Fall Time (t )
30
1
f
SMBus Accelerator Boosted Pull-Up Current
Start Condition Setup Time (t
V
= 3V
2.5
DD
)
4.7
4.0
250
300
SU:STA
Start Condition Hold Time (t
)
HD:STA
SDA to SCL Rising-Edge Setup Time (t
)
SU:DAT
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data (t
)
HD:DAT
t
Between Receiving Valid
●
140
175
210
sec
TIMEOUT
ChargingCurrent() and ChargingVoltage()
Commands (Note 10)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: Power failure bit is set when the battery voltage is above 89% of
the power adapter voltage (V ).
DCIN
Note 2: This limit is greater than the absolute maximum for the charger.
Therefore, there is no effective limitation on voltage when this option is
selected. If the charger is requested to charge with a higher voltage than
the nominal limit, the VOLTAGE_OR bit will be set.
Note 8: The charger provides wake-up current when a battery is inserted
into the connector, prior to the battery requesting charging current and
voltage. See Smart Battery Charger Specification (Revision 1.0), section
6.1.3 and 6.1.8.
Note 3: Total system accuracy from SMBus request to output voltage or
output current.
Note 9: In system start-up, C6 (boost capacitor) has no charge stored in it.
The LTC1759 will keep TGATE off, and turn BGATE on for 0.2µs, thus
charging C6. A comparator senses V
and switches to the normal
BOOST
Note 4: Test Circuit #1.
Note 5: Voltage accuracy is calculated using measured reference voltage,
PWM mode when V
is above its threshold.
BOOST
Note 10: Refer to Smart Battery Charge Specification (Revision 1.0),
section 6.1.2.
obtained from V pin using Test Circuit #2, and VDAC resistor divider
SET
ratio.
Note 11: Maximum total external capacitance on RNR and THERM pins
is 75pF.
Note 6: When supply and battery voltage differential is low, high oscillator
duty cycle is required. The LTC1759 has a unique design to achieve duty
cycle greater than 99% by skipping cycles. Only when V
drops below
Note 12: SMBus operation guaranteed by design from –40°C to 85°C.
BOOST
the comparator threshold, will TGATE be turned off. See Applications
Information section.
5
LTC1759
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Charger Efficiency
SMBus Accelerator Operation
DCDIV Trip Point vs Temperature
100
95
90
85
80
75
70
1.10
1.05
1.00
0.95
0.90
V
C
A
= 5V
CC
LD
16.8V
12.6V
5V
= 200pF
T
= 25°C
V
V
= 5.5V
= 3V
DD
LTC1759
DD
R
= 15k
PULLUP
0V
V
= 20V
IN
0.5
1.5
2.5
3.5
0
10 20 30 40 50 60 70 80
1µs/DIV
TEMPERATURE (°C)
CHARGING CURRENT (A)
1759 G02
1759 G09
1759 G03
Current from Battery vs Battery
Voltage (Does Not Include VDD
Current)
IDD vs VDD (Not Charging)
Programmed Current Accuracy
90
120
110
100
90
0
–10
–20
–30
–40
–50
–60
T
A
= 25°C
T
A
= 25°C
80
70
60
50
40
30
20
10
V
V
= 5.5V
= 3V
DD
DD
80
R
ILIMIT
= 33k
V
V
= 15V
IN
70
= 12V
OUT
T
= 25°C
A
60
3.0
6
8
10 12 14 16 18 20 22 24
(V)
3.5
4.0
V
4.5
(V)
5.0
5.5
256
1256
2256
3256
4256
V
BAT
CHARGING CURRENT (mA)
DD
1759 G04
1759 G05
1759 G06
Charging Voltage Error
Charging Voltage Error
Low Current Mode
0
350
300
250
200
150
100
50
0
–5
R
= 33k
ILIMIT
V
V
A
C
R
= 15V
IN
OUT
V
V
= 5.5V
= 3V
–5
DD
= 12V
T
= 25°C
V
V
= 5.5V
= 3V
= 1nF
DD
PROG
DD
–10
–15
–20
–25
–30
–10
–15
–20
–25
–30
= 3.83k
SET
DD
R
= 33k
R
= 0
VLIMIT
VLIMIT
LOAD CURRENT = 15mA
= 25°C
LOAD CURRENT = 15mA
T
= 25°C
T
A
A
0
0
50
100
150
200
250
300
2000 3000 4000 5000 6000 7000 8000 9000
CHARGING VOLTAGE (mV)
2000
6000
10000
14000
18000
CHARGING CURRENT (mA)
CHARGING VOLTAGE (mV)
1759 G01
1759 G07
1759 G08
6
LTC1759
U
U
U
PIN FUNCTIONS
Input Power-Related Pins
SW (Pin 3): This pin is the reference point for the floating
topside gate drive circuitry. It is the common connection
for the top and bottom side switches and the output
inductor. This pin switches between ground and VCC with
very high dv/dt rates. Care needs to be taken in the PC
layout to keep this node from coupling to other sensitive
nodes. A 1A Schottky clamping diode should be placed
very close to the chip from the ground pin to this pin to
prevent the chip substrate diode from turning on. See
Applications Information for more details.
UV (Pin 7): Charger Section Undervoltage Lockout Pin.
The rising threshold is 6.7V with a hysteresis of 0.5V.
Switching stops in undervoltage lockout. Connect this
input to the input voltage source with no resistor divider.
UV must be pulled below 0.7V when there is no input
voltage source (5k resistor from adapter output to ground
is required) to obtain the lowest quiescent battery current.
INFET (Pin 8): Gate Drive to Input P-channel FET. For very
lowdropoutapplications,useanexternalP-channelFETto
connect the adapter output and VCC. INFET is clamped to
7.8V below VCC.
SYNC(Pin4):ExternalClockSynchronizationInput.Pulse
width range: 10% to 90%.
SDB(ShutdownBar)(Pin5):ActiveLowDigitalInput. The
charger is disabled when asserted. This pin is connected
to the CHGEN pin to enable charger control through the
SMBus interface.
CLP (Pin 9): Positive Input to the Input Current Limit
Amplifier CL1. When used to limit supply current, a filter
(R3 and C1 of Figure 10) is needed to filter out the
switching noise. The threshold is set at 92mV.
CHGEN (Pin 12): Digital Output to Enable Charger Func-
tion. Connect CHGEN to SDB.
CLN (Pin 10): Negative Input to the Input Current Limit
Amplifier CL1. It should be connected to VCC (to the VCC
bypass capacitor C2 for less noise).
ISET (Pin 17): Open-Drain CMOS Switch to DGND. An
external resistor, RSET, is connected from ISET to the
current programming input, the PROG pin of the battery
charger section, which sets the range of the charging
current.
COMP1 (Pin 11): Compensation Node for the Input Cur-
rentLimitAmplifierCL1.Atinputadaptercurrentlimit,this
node rises to 1V. By forcing COMP1 low with an external
transistor, amplifier CL1 will be defeated (no adapter
current limit). COMP1 can source 200µA. Ground (to
AGND) this pin if the adapter current limiting function is
not used.
ILIMIT (Pin 24): An external resistor is connected between
this pin and DGND. The value of the external resistor
programs the range and resolution of the programmed
charger current. See Electrical Characteristics table for
more information.
Battery Charging-Related Pins
BOOST (Pin 1): This pin is used to bootstrap and supply
power for the topside power switch gate drive and control
circuity. In normal operation, VBOOST is powered from an
internally generated 8.6V regulator VGBIAS, VBOOST ≈ VCC
+ 8.9V when TGATE is high. Do not force an external
voltage on BOOST pin.
VLIMIT (Pin 25): An external resistor is connected between
this pin and DGND. The value of the external resistor
programstherangeandresolutionoftheVSET divider. See
Electrical Characteristics table for more information.
VSET (Pin 26): This is the tap point of the programmable
resistor divider, which provides battery voltage feedback
to the charger.
TGATE (Pin 2): This pin provides gate drive to the topside
power FET. When TGATE is driven on, the gate voltage will
be approximately equal to VSW + 6.6V. A series resistor of
5Ω to 10Ω should be used from this pin to the gate of the
topside FET.
7
LTC1759
U
U
U
PIN FUNCTIONS
VC (Pin 27): This is the control signal of the inner loop of
the current mode PWM. Switching starts at 0.9V. Higher
VC corresponds to higher charging current in normal
operation.Acapacitorofatleast0.33µFtoAGNDfiltersout
noise and controls the rate of soft start.
Internal Power Supply Pins
AGND (Pin 6): DC Accurate Ground for Analog Circuitry.
V
DD (Pin 16): Low Voltage Power Supply Input. Bypass
this pin with 0.1µF.
DGND (Pin 18): Ground for Digital Circuitry and DACs.
Should be connected to AGND at the negative terminal
of the charger output filter capacitor.
PROG (Pin 28): This pin is for programming the charging
currentandforsystemloopcompensation.Duringnormal
operation, the pin voltage is approximately 2.465V.
VCC (Pin 32): Power Input for Battery Charger Section.
Bypass this pin with 0.47µF.
SENSE (Pin 29): Current Amplifier CA1 Input. Sensing
must be at the positive terminal of the battery.
GBIAS (Pin 34): 8.6V Regulator Output for Bootstrapping
SPIN (Pin 30): This pin is for the internal amplifier
CA1 bias. It must be connected to RSENSE as shown in
Figure 1.
V
BOOST and VBOOSTC. A bypass capacitor of at least 2µF is
needed. Switching will stop if VBOOST drops below 7.1V.
PGND (Pin 36): High Current Ground Return for Charger
BAT1 (Pin 31): Current Amplifier CA1 Input.
Gate Drivers.
BOOSTC(Pin33):Thispinisusedtobootstrapandsupply
the current sense amplifier CA1 for very low dropout
conditions. VCC can be as low as only 0.4V above the
battery voltage. A diode and a capacitor are needed to get
the voltage from VBOOST. If low dropout is not needed and
VCC is always 3V or greater than VBAT, this pin can be left
floating or tied to VCC. Do not force this pin to a voltage
lower than VCC.
SBS Interface Pins
INTB(InterruptBar)(Pin13):ActiveLowInterruptOutput
toHost.Signalshostthattherehasbeenachangeofstatus
in the charger registers and that the host should read the
LTC1759 status registers to determine if any action on its
part is required. This signal can be connected to the
optional SMBALERT# line of the SMBus. Open drain with
weakcurrentsourcepull-uptoVDD (withSchottkytoallow
it to be pulled to 5V externally, see Figure 2).
BGATE (Pin 35): Drives the gate of the bottom external
N-channel FET of the charger buck converter.
SDA (Pin 14): SMBus Data Signal from Main (Host-
Monitor/Fault Diagnostic Pins
controlled) SMBus.
DCDIV (Pin 21): Supply Divider Input. This is a high
impedance comparator input with a 1V threshold (rising
edge) and hysteresis.
SCL (Pin 15): SMBus Clock Signal from Main (Host-
Controlled) SMBus. External pull-up resistor is required.
THERM (Pin 19): Thermistor Force/Sense Pin to Smart
Battery. See Electrical Characteristics table for more
detail.MaximumallowedcombinedcapacitanceonTHERM
and RNR is 75pF.
DCIN (Pin 22): Input connected to the DC input source to
monitor the DC input for power-fail condition.
BAT2 (Pin 23): Sensing Point for Voltage Control Loop.
Connect this to the positive terminal of the battery.
RNR (Pin 20): Thermistor Force/Sense Pin to Smart
Battery. See Electrical Characteristics table for more
detail.MaximumallowedcombinedcapacitanceonTHERM
and RNR is 75pF.
8
LTC1759
W
BLOCK DIAGRA
V
CC
8V
7
UV
8
INFET
+
–
+
–
0.2V
+
–
BAT1 31
6.7V
6.7V
32
V
CC
1
2
3
BOOST
TGATE
SW
–
+
5
SDB
SHDN
PWM
LOGIC
8.9V
1.3V
34 GBIAS
ONE
SHOT
200kHz
OSC
SYNC
4
S
R
35 BGATE
36 PGND
Q
SLOPE COMP
33
BOOSTC
–
+
B1
30
29
SPIN
+
C1
AGND
6
–
+
SENSE
CA1
–
1k
BAT1
+
+
V
REF
V
C
27
CA2
–
28
PROG
75k
92mV
+
–
+
V
CLP
CLN
9
REF
VA
CL1
–
+
10
11
21
22
DCDIV
DCIN
AC_PRESENT
COMP1
290k
20k
812.5k
65k
–
V
DD
1V
10µA
–
PWR_FAIL
+
23
26
BAT2
INTB
13
12
612k
72k
V
SET
CHARGER
CONTROLLER
10-BIT
CHGEN
VOLTAGE
DAC
THERM
RNR
19
20
THERMISTOR
DECODER
24
25
I
LIMIT
LIMIT
DECODER
V
LIMIT
SCL
15
14
SMBus
CONTROLLER
13
10-BIT
CURRENT
DAC
SDA
17
16
I
SET
DGND 18
V
DD
1759 F02
Figure 2
9
LTC1759
TEST CIRCUITS
Test Circuit 1
SPIN
LTC1759
R
S3
200Ω
SENSE
–
+
+
–
V
C
R
SENSE
10Ω
R
S2
CA1
CA2
200Ω
BAT1
1k
75k
0.047µF
+
V
BAT
V
REF
PROG
1µF
R
SET
300Ω
+
LT1006
1k
1759 TC01
–
+
≈ 0.65V
20k
Test Circuit 2
LTC1759
V
SET
+
VA
V
–
REF
PROG
2k
I
PROG
2nF
–
+
LT1013
1759 TC02
+
0.47µF
R
SET
2.465V
10
LTC1759
U
OPERATIO
Overview (Refer to Block Diagram and Figure 10)
accuracy is achieved with averaging capacitor CPROG
.
Note that IPROG has both AC and DC components. IPROG
generates a ramp signal that is fed to the PWM control
comparator C1 through buffer B1 and level shift resistors
forming the current mode inner loop. The BOOST pin
supplies the top power switch gate drive. The LTC1759
generates a 8.9V VGBIAS for bootstrapping VBOOST and
VBOOSTC as well as to drive the bottom power FET. The
BOOSTC pin supplies the current amplifier CA1 with a
voltage higher than VCC for low dropout applications.
Amplifier VA reduces the charging current when the bat-
tery voltage reaches the set voltage programmed by the
VDAC and the 2.465V reference voltage.
The LTC1759 is composed of a battery charger section, a
charger controller, two 10-bit DACs to control charger
parameters, a thermistor decoder, limit decoder and an
SMBus controller block. If no battery is present, the
thermistor decoder indicates a THERM_OR condition and
charging is disabled by the charger controller (CHGEN =
Low). Charging will also be disabled if AC_PRESENT is
low, or the battery thermistor is decoded as THERM_HOT.
If a battery is inserted or AC power is connected, the
battery will be charged with an 80mA “wake-up” current.
The wake-up current is discontinued after three minutes
if the thermistor is decoded as THERM_UR or
THERM_COLD, and the battery or host doesn’t transmit
charging commands.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (92mV/
RCL). At input current limit, CL1 will supply the program-
ming current IPROG and thus reduce battery charging
current.
The SMBus controller block receives ChargingCurrent()
and ChargingVoltage() commands via the SMBus. If
ChargingCurrent()andChargingVoltage()commandpairs
are received within a three-minute interval, the values are
stored in the current and voltage DACs and the charger
controller asserts the CHGEN line if the decoded ther-
mistor value will allow charging to commence.
ChargingCurrent()andChargingVoltage()valuesarecom-
pared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The INFET pin drives an external input P-channel FET for
low dropout applications.
SMBus Interface
AllcommunicationsovertheSMBusareinterpretedbythe
SMBus controller block. The SMBus controller is an
SMBus slave device. All internal LTC1759 registers may
be updated and accessed through the SMBus controller,
and charger controller as required. The SMBus protocol is
a derivative of the I2CTM bus (Reference “I2C-Bus and How
to Use It, V1.0” by Philips and “System Management Bus
Specification” by the Smart Battery System Organiza-
tion*, for a complete description of the bus protocol
requirements.)
The charger controller will assert INTB whenever a status
change is detected. The host may query the charger, via
the SMBus, to obtain ChargerStatus() information. INTB
will be deasserted upon a successful read of
ChargerStatus() or a successful Alert Response Address
(ARA) request.
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
fallingedgeofSCL.DetectionofanSMBusStopcondition,
or power-on reset via the VDD undervoltage lockout, will
reset the controller to an initial state at any time.
Battery Charger Section
The LTC1759 is synchronous current mode PWM step-
down (Buck) switcher. The battery DC charging current is
programmed with a current DAC via the SMBus interface.
Amplifier CA1 converts the charging current through
The LTC1759 command set is interpreted by the SMBus
controller and passed onto the charger controller block as
control signals or updates to internal registers.
RSENSE to a much lower current IPROG (IPROG = IBAT
•
RSENSE/RS2) fed into the PROG pin. Amplifier CA2 com-
pares the output of CA1 with the programmed current and
drives the PWM loop to force them to be equal. High DC
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
11
LTC1759
U
OPERATIO
Table 1: Supported Charger Functions
SMBus ADDRESS
COMMAND CODE
(8-BIT hex)
FUNCTION
(7-BIT)
ACCESS
DATA TYPE
Register
ChargerSpecInfo()
ChargerMode()
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_001
b0001_100
h11
h12
h13
h14
h15
h16
h3c
h3d
h3e
h3f
r
w
Register
ChargerStatus()
r
Register
ChargingCurrent()
ChargingVoltage()
AlarmWarning()
w
Register
w
Register
w
Control
LTCVersionFunction()
OptionalMfgFunction3()
OptionalMfgFunction2()
OptionalMfgFunction1()
r
Register
–
Not Supported
Not Supported
Not Supported
Interrupt Address
–
–
1
Alert Response Address
N/A
Read Byte
1
Read-byte format. 89h is returned as the interrupt address of the LTC1759. Rev 1.0 SMBus Compliant.
Table 2: SMBus Word Bit Definitions for All Allowed LTC1759 Functions
POWER-ON
WORD BIT
MAPPING
RESET VALUE
(BINARY)
FUNCTION
FIELD
ALLOWED VALUES
ChargerSpecInfo
CHARGER_SPEC
3:0
0001
• The CHARGER_SPEC Reports the Version of the Smart Battery
Charger Specification the Charger Supports
• 0001 – Version 1.0
• All Other Codes Reserved
• Always Returns 0001
• Read Only. Write Will NACK
SELECTOR_SUPPORT
4
0
• 0 – Charger Does Not Support the Optional Smart Battery Selector
Commands
• 1 – Charger Supports the Optional Smart Battery Selector
Commands
• Always Returns 0
• Read Only. Write Will NACK
Reserved
15:5
0
0
0
• These Bits Are Reserved and Must Return Zero
• Read Only. Write Will NACK
ChargerMode()
INHIBIT_CHARGE
• 0 – Enable Charging (Power-On Default)
• 1 – Inhibit Charging
• Write Only. Read Will NACK
• Cleared to Power-On Reset Value When:
1) POR_RESET = 1
2) AC_PRESENT = 0
3) BATTERY_PRESENT = 0
ENABLE_POLLING
POR_RESET
1
2
0
0
• 0 – Disable Polling (Power-On Default for Smart Battery Controlled
Chargers)
• 1 – Enable Polling (Power-On Default for Host Controlled Chargers).
• Ignored by LTC1759
• Write Only. Read Will NACK
• 0 – Mode Unchanged (Default)
• 1 – Set Charger to Power-On Defaults
• This Reset Only Affects the Charger_Controller Block
• Write Only. Read Will NACK
12
LTC1759
U
OPERATIO
POWER-ON
RESET VALUE
(BINARY)
WORD BIT
MAPPING
FUNCTION
FIELD
ALLOWED VALUES
RESET_TO_ZERO
3
0
• 0 – Charging Value Unchanged
• 1 – Set Charging Values to Zero
NOTE:
This function is implemented by forcing the charger to
CHARGING_NONE_STATE and not allowing charge to resume until a
valid ChargingCurrent() and ChargingVoltage() Pair Is received.
• Write Only. Read Will NACK
Reserved
15:4
0
0
0
• Not Implemented. Writes to These Bits Are Ignored.
• Write Only. Read Will NACK
ChargerStatus()
CHARGE_INHIBITED
This Is the ChargerMode() INHIBIT_CHARGE Bit
• 0 – Charger Is Enabled
• 1 – Charger Is Inhibited
• Read Only. Write Will NACK
MASTER_MODE
VOLTAGE_NOTREG
CURRENT_NOTREG
LEVEL_3:LEVEL_2
1
2
0
0
• 0 – Charger Is in Slave Mode (Polling Disabled)
• 1 – Charger Is in Master Mode (Polling Enabled)
• Always Returns 0
• Read Only. Write Will NACK
• 0 – Charger’s Output Voltage Is in Regulation
• 1 – Requested ChargingCurrent() Is Not Being Met
• Not Supported; Always Returns 0
• Read Only. Write Will NACK
3
0
• 0 – Charger’s Output Current Is in Regulation
• 1 – Requested ChargingCurrent() Is Not Being Met
• Not Supported; Always Returns 0
• Read Only. Write Will NACK
5:4
01
• 00 – Reserved
• 01 – Charger Is a Smart Battery Controlled
• 10 – Reserved
• 11 – Charger Is a Host Controlled
• Always Returns 01
• Read Only. Write Will NACK
CURRENT_OR
VOLTAGE_OR
6
7
0
0
• 0 – ChargingCurrent() Value Is Valid
• 1 – ChargingCurrent() Value Is Invalid
• This Value Is Valid Only When Charging with
CHARGE_INHIBITED = 0 or 1
• Read Only. Write Will NACK
• 0 – ChargingVoltage() Value Is Valid
• 1 – ChargingVoltage() Value Is Invalid
• This Value Is Valid Only When Charging with
CHARGE_INHIBITED = 0 or 1
• Read Only. Write Will NACK
THERM_OR
THERM_COLD
THERM_HOT
8
9
Value
Value
Value
• 0 – Thermistor Indicates Not Overrange
• 1 – Thermistor Indicates Overrange
• Read Only. Write Will NACK
• 0 – Thermistor Indicates Not Cold
• 1 – Thermistor Indicates Cold
• Read Only. Write Will NACK
10
• 0 – Thermistor Indicates Not Hot
• 1 – Thermistor Indicates Hot
• Read Only. Write Will NACK
13
LTC1759
U
OPERATIO
POWER-ON
RESET VALUE
(BINARY)
WORD BIT
MAPPING
ALLOWED VALUES
FUNCTION
FIELD
THERM_UR
11
Value
• 0 – Thermistor Indicates Not Underrange
• 1 – Thermistor Indicates Underrange
• Read Only. Write Will NACK
ALARM_INHIBITED
12
0
• 0 – Charger Not Alarm Inhibited
• 1 – Charger Alarm Inhibited. This Bit Is Set but Never Cleared by
AlarmWarning()
• Read Only. Write Will NACK
• Cleared to Power-On Reset Value When:
1) POR_RESET = 1
2) BATTERY_PRESENT = 0
3) AC_PRESENT = 0
4) A Valid ChargingVoltage(), ChargingCurrent() Pair Is Received
POWER_FAIL
BATTERY_PRESENT
AC_PRESENT
13
14
Value
Value
Value
0
• 0 – V /V
< 0.9
> 0.9
BAT DCIN
• 1 – V /V
BAT DCIN
• Read Only. Write Will NACK
• 0 – Battery Is Not Present
• 1 – Battery Is Present
• Read Only. Write Will NACK
15
• 0 – Charge Power Is Not Available
• 1 – Charge Power Is Available
• Read Only. Write Will NACK
ChargingCurrent()
ChargingVoltage()
AlarmWarning()
CHARGING_CURRENT
[15:0]
15:0
• Unsigned Integer Representing Charger Current in mA
• Three Possible Responses
– Supply the Current Requested
– Supply Its Programmatic Maximum Current If the Request Is
Greater Than Its Programmatic Value and Less Than hffff
– Supply Its Maximum Safe Current If the Request Is hffff [Supply
Current Required to Meet ChargingVoltage()].
• Write Only. Read Will NACK
CHARGING_VOLTAGE
[15:0]
15:0
0
• Unsigned Integer Representing Charger Voltage in mV
• Three Possible Responses
– Supply the Voltage Requested
– Supply Its Programmatic Maximum Voltage If the Request Is
Greater Than Its Programmatic Value and Less Than hffff
– Supply Its Maximum Voltage If the Request Is hffff [Supply
Voltage Required to Meet ChargingCurrent()].
• Write Only. Read Will NACK
OVER_CHARGED_
ALARM
15
14
13
12
0
0
0
0
• 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored
TERMINATE_CHARGE_
ALARM
• 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
RESERVED_ALARM1
OVER_TEMP_ALARM
• 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
• 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
14
LTC1759
U
OPERATIO
POWER-ON
RESET VALUE
(BINARY)
WORD BIT
MAPPING
ALLOWED VALUES
FUNCTION
FIELD
TERMINATE_
DISCHARGE_ALARM
11
0
• This Bit May Be Used to Signal That the Charger May Be Restarted
After a Battery Conditioning Cycle Has Been Completed
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored
• Not Supported by LTC1759
Reserved
10
9
–
–
• Not Supported by LTC1759
• Write Only. Read Will NACK
REMAINING_
• Intended for Host
CAPACITY_ALARM
• Not Supported by LTC1759
• Write Only. Read Will NACK
REMAINING_TIME_
ALARM
8
7
–
–
–
–
–
–
• Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
INITIALIZED
DISCHARGING
FULLY_CHARGED
FULLY_DISHARGED
ERROR
• Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
6
• Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
5
• Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
4
• Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
3:0
• Intended for Host
• All Bits Set High Prior to AlarmWarning() Transmission
• Not Supported by LTC1759
• Write Only. Read Will NACK
LTCVersionFunction
()
LTC_VERSION
15:0
0101hex
• Returns LTC Version Number
• Read Only
• Always Returns 0101hex
SMBus Accelerator Pull-Ups
requirements with as much as 150pF on each SMBus
signal.Theimprovedrisetimewillbenefitallofthedevices
which use the SMBus, especially those devices that use
the I2C logic levels. Note that the dynamic pull-up circuits
only pull to VDD, so some SMBus devices that are not
compliant to the SMBus specifications may still have rise
time compliance problems if the SMBus pull-up resistors
are terminated with voltages higher than VDD.
Both SCL and SDA have SMBus accelerator circuits which
reduce the rise time on systems with significant capaci-
tance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
2mA to 5mA pull-up to VDD for approximately 1µs (exter-
nal pull-up resistors are still required to supply DC cur-
rent). This action allows the bus to meet SMBus rise time
15
LTC1759
U
OPERATIO
The charger controller allows the LTC1759 to meet the
following host-controlled (Level 3) Smart Battery charger
requirements.
The Charger Controller Block
The LTC1759 charger operations are handled by the
charger controller block. This block is capable of charging
the selected battery autonomously or under host control.
The charger controller can request communications with
the system management host (SMHost) by asserting
INTB = 0; this will cause the SMHost, if present, to poll the
LTC1759.
1. In a host-controlled system the host is able to operate
as an SMBus master device.
2. The host may determine the appropriate charging algo-
rithmbyqueryingthebatteryorprovidinganalternative
special charging algorithm.
The charger controller receives SMBus slave commands
from the SMBus controller block.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcasting
thechargingcommandstotheLTC1759overtheSMBus.
The charge controller allows the LTC1759 to meet the
following Smart Battery-controlled (Level 2) charger
requirements:
4. The LTC1759 will still respond to Smart Battery critical
warning messages without host intervention.
1. Implements the Smart Battery’s critical warning mes-
sages over the SMBus.
The charger controller block uses the state machine of
Figure 3. The functional features for state transitions and
general control are detailed in Table 3.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output characteristics
accordingly.
15
0
CHARGING_RESET_STATE
19
14
7
1 OR 2
15
15
8 OR 9
CHARGING_WAKE-UP_STATE
20
CHARGING_CONTROLLED_STATE
21
15
3 OR 4 OR 5
OR 6 OR 16
10 OR 11 OR 12
OR 13 OR 16
8 OR 9
CHARGING_NONE_STATE
22
1759 F03
NOTE: NUMBERS REFER TO CONDITIONS AND STATE DESCRIPTION IN TABLE 3
Figure 3. Charger Controller State Machine
16
LTC1759
U
OPERATIO
Table 3. Charger_Controller Functional Features
#
CONDITION
ACTION
0
POWER_ON_RESET = 1
CHARGING_RESET_STATE =1
(Asynchronously Reset the Charger_Controller State Machine During
Power-On Reset)
1
2
3
CHARGING_RESET_STATE = 1 AND the Battery Is Present
AND AC_PRESENT = 1 AND INHIBIT_CHARGE = 0 AND Thermistor Is
Ideal
CHARGING _WAKE-UP_STATE = 1
The Charger_Controller Will “Wake Up” Charge the Battery
at I
Indefinitely
WAKE-UP
CHARGING_RESET_STATE = 1 AND the Battery Is Present
AND AC_PRESENT =1 AND INHIBIT_CHARGE = 0 AND THERM_
UR = 1 OR THERM_COLD = 1
CHARGING_WAKE-UP_STATE = 1
The Charger_Controller Will “Wake Up” Charge the Battery
at I
Until Condition 3 Is Met
WAKE-UP
CHARGING_WAKE-UP_STATE = 1 AND the Time-Out Period
CHARGING_NONE_STATE = 1
Exceeds t
AND THERM_UR = 1 OR THERM_COLD = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
TIMEOUT
4
CHARGING_WAKE-UP_STATE = 1 AND an AlarmWarning() Message
Is Received with Any Bit in the Upper Nibble Set
CHARGING_NONE_STATE =1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
5
CHARGING_WAKE-UP_STATE = 1 (from Condition 1 above) AND
THERM_HOT Changes from 0 to 1 AND THERM_UR = 0
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
6
CHARGING_WAKE-UP_STATE = 1 (from Condition 2 above) AND
THERM_UR Changes from 1 to 0 AND THERM_HOT = 1
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
7
CHARGING_WAKE-UP-STATE = 1 AND INHIBIT_CHARGE Is
Set to 1
CHARGING_WAKE-UP_STATE =1
The Charger_Controller Stops Charging the Selected Battery. The Timer
Continues to Run. The Charger Can Resume “Wake-Up” Charging If
INHIBIT_CHARGE = 0
8
(CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1)
AND (Both ChargingCurrent() AND ChargingVoltage() Commands
CHARGING_CONTROLLED_STATE = 1
The Charger_Controller Will Supply “Controlled Charge” to the
Battery as Specified in the Current and Voltage Commands
Are Received within t
) AND INHIBIT_CHARGE = 0
TIMEOUT
AND THERM_HOT = 0
9
(CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1)
AND (Both ChargingCurrent() AND ChargingVoltage() Commands
CHARGING_CONTROLLED_STATE = 1
The Charger_Controller Will Supply “Controlled Charge” to the
Are Received within t
AND THERM_UR = 1
) AND INHIBIT_CHARGE = 0
Battery as Specified in the Current and Voltage Commands
TIMEOUT
10
11
CHARGING_CONTROLLED_STATE = 1
AND No New ChargingCurrent() and ChargingVoltage() Commands Are
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
Received for a Time-Out Period of t
TIMEOUT
CHARGING_CONTROLLED_STATE = 1
CHARGING_NONE_STATE = 1
The Charger_Controller Is Supplying “Controlled Charge” to the
Battery AND (an AlarmWarning() Message Is Received
with Any Bit in the Upper Nibble Set)
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
17
LTC1759
U
OPERATIO
#
CONDITION
ACTION
12
CHARGING_CONTROLLED_STATE = 1 AND THERM_HOT
Changes from 0 to 1 AND THERM_UR = 0
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
13
CHARGING_CONTROLLED_STATE = 1 AND THERM_UR
Changes from 1 to 0 AND THERM_HOT = 1
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
14
CHARGING_CONTROLLED_STATE = 1
AND INHIBIT_CHARGE Is Set to 1
CHARGING_CONTROLLED_STATE = 1
INHIBIT_CHARGE Asynchronously Inhibits Charging Without
Affecting the Charger_Controller State Machine. This Means the Charger
Stops Charging the Battery but Continues to Accept New
ChargingCurrent() and ChargingVoltage() Commands, Continues to
Monitor the Battery Thermistor Input and Continues to Track the
Communication Time-Out. It Will Resume Charging the Battery If
INHIBIT_CHARGE Is Cleared to 0, Possibly at Different Current and
Voltage If New Commands Have Been Sent in the Interim
15
16
ANY STATE
CHARGING_RESET_STATE= 1
The Charger_Controller Is Set to Its Power-On Default State
The Charger_Controller Is in Any State AND (the Battery Is Removed
OR AC_PRESENT = 0 OR a 1 Is Written to POR_RESET)
NOTE:
Condition 15 Takes Precedence Over Any Other Condition.
(CHARGING_CONTROLLED_STATE = 1) OR
CHARGING_WAKE-UP_STATE = 1) AND
A 1 Is Written to RESET_TO_ZERO
CHARGING_NONE_STATE = 1
The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met.
The Valid Charge Command Timer Is Cleared When RESET_TO_ZERO =
1. This Prevents Charging from Continuing Until After a Valid
ChargeCurrent() and ChargeVoltage() Pair Is Received
18
ANY STATE AND
AC_PRESENT Transitions 0 to 1 or 1 to 0 OR
BATTERY_PRESENT Transitions 0 to 1 or 1 to 0
Alert SMHost of Change by Setting INTB = 0
19
20
21
CHARGING_RESET_STATE = 1
CHGEN = 0
The Charger Is Not Charging
CHARGING _WAKE-UP_STATE = 1
CHARGING_CONTROLLED_STATE = 1
CHGEN = ~INHIBIT_CHARGE
The Charger Will Provide a Wake-Up Current When CHGEN = 1
CHGEN = ~INHIBIT_CHARGE
The Charger Will Provide Specified Charging Voltage and Current
When CHGEN = 1
A Zero Value for ChargingVoltage() Is Handled by Forcing CHGEN = 0
22
CHARGING_NONE_STATE = 1
CHGEN = 0
The Charger Is Not Charging
18
LTC1759
U
OPERATIO
The Thermistor Decoder Block
with RTHERM. The resulting voltage is monitored at
THERM,comparedtoaninternalreferenceandsampled
at the output of the cold and hot comparators. This
detection mode is only activated if OR tested low.
This block measures the resistance of the battery’s ther-
mistor and features high noise immunity at critical trip
points. The low power standby mode supports all SMB
charger reporting requirements when AC is not present.
The thermistor decoder is shown in Figure 4.
3. Underrange Detection. The RNR_SELB switch is off
and the RUR_SELB switch is on. The external RUR and
RWEAK resistors form a voltage divider with RTHERM
.
Thermistor sensing is accomplished by a state machine
thatreconfigurestheswitchesofFigure4usingRNR_SELB
andRUR_SELB.Thethreeallowablemodesareasfollows:
TheresultingvoltageismonitoredatRNR, comparedto
an internal reference and sampled at the output of the
UR comparators. This detection mode is only activated
if HOT tested high.
1. Overrange Detection. The RUR_SELB and RNR_SELB
switches are off and the external RWEAK resistor forms
a voltage divider with RTHERM. The resulting voltage is
monitored at THERM, compared to an internal refer-
ence and sampled at the output of the OR comparator.
This detection mode is always active allowing low
power operation when AC power is not available.
NOTE: The underrange detection scheme is a very impor-
tant feature of the LTC1759. The RUR/RTHERM divider trip
point of 0.333 • VDD (1V) is well above the 0.047 • VDD
(140mV) threshold of a system using a 10k pull-up. A
systemusinga10kpull-upwouldnotbeabletoresolvethe
important underrange to hot transition point with a mod-
est 100mV of ground offset between battery and ther-
mistor detection circuitry. Such offsets are anticipated
when charging at normal current levels.
2. Cold/Ideal/Hot Range Detection. The RNR_SELB
switch is on and the RUR_SELB switch is off. The
externalRNR andRWEAK resistorsformavoltagedivider
V
DD
V
DD
V
R
DD
R
475k
1%
WEAK
RNR_SELB
RUR_SELB
NR
V
DD
R
10k
1%
NR
R
UR
1k
1%
THERM
+
THERM_COLD
THERM_UR
THERM_HOT
THERM_OR
COLD
–
R
THERM
+
TOTAL
PARASITIC
CAPACITANCE
MUST BE LESS
THAN 75pF
UR
–
THERM
LATCH
+
HOT
–
+
OR
–
HYSTERESIS
1759 F04
Figure 4. Thermistor Decoder Block
19
LTC1759
U
OPERATIO
When AC power is not available the thermistor block
supports the following low power operating features:
provide a measure of safety with a hardware restriction on
charging current which cannot be overridden by software.
1. Only the low power THERM_OR detection circuitry is
kept alive to support battery present interrupts.
Table 6. ILIMIT Trip Points and Ranges
EXTERNAL
RESISTOR
NOMINAL
CHARGING
CURRENT RANGE GRANULARITY
2. The ChargeStatus() read function forces the thermistor
blocktoupdatethermistorstatusatthebeginningofthe
read. The low power mode is immediately reentered
upon completion of the read.
(R
ILIMIT
)
I
VOLTAGE
LIMIT
0
V
< 0.09V
0 < I < 1023mA
0 < I < 2046mA
1mA
2mA
ILIMIT
DD
10k ±1%
0.17V
< V
VDD ILIMIT
< 0.34V
VDD
The thermistor impedance is interpreted according to
Table 4.
33k ±1%
0.42V
< 0.59V
< V
0 < I < 4092mA
0 < I < 8184mA
4mA
8mA
VDD
ILIMIT
ILIMIT
Open (>250k, 0.66V
or Short to
< V
VDD
Table 4. Thermistor State Ranges
THERMISTOR
RESISTANCE
CHARGE
STATUS BITS
V
)
DD
DESCRIPTION
0Ω to 500Ω
THERM_UR,
THERM_HOT
Underrange
BATTERY_PRESENT
V
DD
500Ω to 3kΩ
3kΩ to 30kΩ
30kΩ to 100kΩ
Above 100kΩ
THERM_HOT
BATTERY_PRESENT
Hot
AC_PRESENT
(NONE)
BATTERY_PRESENT
Ideal
12.5k
THERM_COLD
BATTERY_PRESENT
Cold
+
–
33k
25k
25k
THERM_OR
THERM_COLD
Overrange
+
4
V
[3:0]
V
LIM
LIMIT
–
ENCODER
+
–
R
The required values for RWEAK, RUR and RNR are shown in
Table 5.
LIMIT
25k
+
–
12.5k
Table 5. Thermistor External Resistor Values
EXTERNAL RESISTOR
VALUE (Ω)
R
475k ±1%
1k ±1%
1759 F05
WEAK
R
R
UR
NR
Figure 5. Simplified VLIMIT Circuit Concept (ILIMIT Is Similar)
10k ±1%
Note: The maximum allowed total external capacitance on THERM and
RNR is 75pF, due to settling time requirements.
The VLIMIT Decoder Block
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are
applied to the charger output value. These limits provide
a measure of safety with a hardware restriction on charg-
ing voltage which cannot be overridden by software.
The ILIMIT Decoder Block
The value of an external resistor connected from this pin
to GND determines one of four current limits that are used
to limit the maximum charging current value. These limits
20
LTC1759
U
OPERATIO
25
20
15
10
5
Table 7. VLIMIT Trip Points and Ranges
NOMINAL
CHARGING
EXTERNAL
RESISTOR
VOLTAGE (V
RANGE
)
OUT
(R
VLIMIT
)
V
LIMIT
VOLTAGE
GRANULARITY
0
V
< 0.09V
2465mV < V
< 8432mV
16mV
VLIMIT
VCCP
OUT
10k ±1% 0.17V
< V
2465mV < V
< 12640mV
16mV
32mV
32mV
32mV
VDD
VLIMIT
OUT
OUT
OUT
OUT
< 0.34V
VDD
33k ±1% 0.42V
< V
2465mV < V
< 16864mV
VCCP
VLIMIT
VLIMIT
VLIMIT
0
< 0.59V
VDD
0
10
15
20
25
30
35
5
PROGRAMMED VALUE (V)
100k ±1% 0.66V
< V
2465mV < V
< 21056mV
VDD
< 0.84V
VDD
NOTE: THE USER MUST ADJUST THE VALUE OF
THE EXTERNAL CURRENT SENSING COMPONENTS
(R , R , R , R ) TO MAINTAIN CONSISTENCY
Open or
0.91V
< V
2465mV < V
< 32768mV
VDD
S1 S2 SENSE SET
WITH I RANGES. SEE APPLICATIONS INFORMATION
Tied to V
LIMIT
DD
1759 F06
Figure 6. Transfer Function of Charger
The Voltage DAC Block
Note that the charge output voltage is offset by VREF
.
Therefore, the value of VREF is subtracted from the SMBus
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 2.465V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage()valueisabovethelimitsetbytheVLIMIT
pin, then the charger output voltage is set to the value
determined by the VLIMIT resistor and the VOLTAGE_OR
bit is set. These limits are demonstrated in Figure 6.
I
PROG
(FROM CA1 AMP)
PROG
SET
+
TO
ERROR
AMP
–
V
REF
R
I
SET
∆-∑
MODULATOR
CHARGINGCURRENT()
VALUE
1759 F07
Figure 7. Current DAC Operation
The Current DAC Block
The current DAC is a delta-sigma modulator which con-
trols the effective value of an external resistor, RSET, used
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulatorandswitchconverttheChargingCurrent()value,
received via the SMBus, to a variable resistance equal to:
AVERAGE CHARGER CURRENT
I
/8
LIMIT
0
1750 F08
~40ms
Figure 8. Charging Current Waveform in Low Current Mode
1.25RSET/ChargingCurrent()/ILIMIT[x]
)
frequency clock having a duty cycle value of 1/8. There-
fore, themaximumoutputcurrentprovidedbythecharger
is IMAX/8. The delta-sigma output gates this low duty cycle
signal on and off. The delta-sigma shift registers are then
clocked at a slower rate, about 45ms/bit, so that the
chargerhastimetosettletotheIMAX/8value.Theresulting
average charging current is equal to that requested by the
ChargingCurrent() value.
Therefore, programmed current is equal to:
0.8VREF/RSET (ChargingCurrent()/ILIMIT[x]),
for ChargingCurrent() < ILIMIT[x]
.
When a value less than 1/16th of the maximum current
allowed by ILIMIT is applied to the current DAC input, the
current DAC enters a different mode of operation. The
current DAC output is pulse width modulated with a high
21
LTC1759
U
OPERATIO
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, inde-
pendent of the ILIMIT setting.
capacitance at the ISET pin should be minimized to keep
these errors small.
The Battery Monitor Block (PWR_FAIL)
Note:
Two internal resistor dividers compare the BAT2 terminal
to the DCIN terminal. When BAT2 is above 89% of the
voltage at DCIN the PWR_FAIL bit is set to 1. A small
amount of proportional hysteresis, ~2%, is used for noise
immunity. The PWR_FAIL bit is set low if AC_PRESENT
is low.
The external resistor connected to the ISET pin must be
multiplied by 0.8 to compensate for the 80% maximum
dutycycleofthesigma-deltamodulator. Notealsothatthe
80% duty cycle converts the rise/fall time mismatches to
a small gain error, rather than a nonlinearity. The parasitic
U
W U U
APPLICATIONS INFORMATION
Adapter Limiting
92mV
CLP
+
+
An important feature of the LTC1759 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
1µF
CL1
500Ω
CLN
–
AC ADAPTER
INPUT
R
*
S4
V
CC
V
IN
+
LTC1759
1759 F09
C
IN
92mV
*R
=
S4
ADAPTER CURRENT LIMIT
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across RS4, connected
betweentheCLPandCLNpins. Whenthisvoltageexceeds
92mV, the amplifier will override programmed charging
current to limit adapter current to 92mV/RS4. A lowpass
filter formed by 500Ω and 1µF is required to eliminate
switching noise. If the current limit is not used, both CLP
and CLN pins should be connected to VCC.
Figure 9. Adapter Current Limiting
Table 7. Common RS4 Resistor Values
ADAPTER
RATING (A)
R
VALUE*
(Ω) 1%
R
POWER
R
POWER
S4
S4
S4
DISSIPATION (W)
RATING (W)
1.5
1.8
2
0.06
0.135
0.25
0.05
0.162
0.25
0.045
0.039
0.036
0.033
0.03
0.18
0.25
2.3
2.5
2.7
3
0.206
0.25
0.225
0.5
0.241
0.5
Setting Input Current Limit
0.27
0.5
* Values shown above are rounded to nearest standard value.
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 5% for the
input current limit tolerance and use that current to deter-
mine the resistor value.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 7).
RS4 = 92mV/ILIMIT
ILIMIT
=
Adapter Min Current – (Adapter Min Current • 5%)
22
LTC1759
U
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APPLICATIONS INFORMATION
and RSET values at all times. Changing the current setting
can result in currents that greatly exceed the requested
value and potentially damage the battery or overload the
wall adapter if no input current limiting is provided.
Charge Termination Issues
Batteries with constant current charging and voltage-
based charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Example Calculations
Setting up the output current to the desired value involves
calculating these values:
Setting Output Current Limit (Refer to Figure 10)
1. RSENSE:Thisresistoristhecurrentsenseresistoronthe
charger output.
The LTC1759 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
2. RSET: This resistor sets the current DAC output pro-
gramming current scale.
Table 8. Recommended Resistor Values
3. RILIMIT: This resistor programs the full-scale value of
the current DAC (IMAX).
I
R
R
R
= R
R
R
ILIMIT
(Ω) 1%
MAX
(A)
SENSE
SENSE
(W)
S1
S2
SET
(Ω) 1%
0.100
0.05
(Ω) 1%
(Ω) 1%
3.83k
3.83k
3.83k
4.02k
1.023
2.046
4.092
8.184
0.25
0.25
0.5
1
200
0
The value of RSENSE and RSET are directly related to each
other based on the values chosen for RS1 and RS2. To
prevent current sense op amp input bias errors, the value
of RS1 and RS2 are kept the same, about 200Ω. RSET is
used to scale the PROG pin current relative to the RSENSE
voltage drop to set the maximum current value.
200
10k
0.025
0.012
200
33k
200
Open
Warning
DONOTCHANGETHEVALUEOFRILIMIT DURINGOPERA-
TION. The value must remain fixed and track the RSENSE
The following example is for a 4A design.
R1
15.8k
R2
1k
R
, 0.033Ω
CL
Q1
AC
ADAPTER
INPUT
C15
10µF
35V
Al
C14
0.1µF
+
LTC1759
R3
499Ω
V
22
21
8
7
16
4
DD
UV
V
DCIN
C9, 0.1µF
C2
DCDIV
INFET
DD
0.47µF
SYSTEM
POWER
SYNC
SDB
C1
1µF
5
32
9
V
CC
C16
12
25
24
18
17
28
27
11
6
CHGEN
CLP
CLN
22µF
R
R
, 33k
10
2
VLIMIT
, 33k
V
LIMIT
ILIMIT
C4, 0.1µF
C5, 2.2µF
Q2
Q3
I
TGATE
BOOSTC
GBIAS
BOOST
SW
LIMIT
L1
15µH
R
SENSE
33
34
1
DGND
0.025Ω
C6
0.68µF
R
SET, 3.83k
I
+
SET
D2
D2
C3
22µF
C11, 1µF
C13, 0.33µF
C12, 0.68µF
PROG
SMART
BATTERY
D1
R4, 1.5k
R7, 1k
3
V
C
35
30
29
31
23
26
36
COMP1
AGND
RNR
BGATE
SPIN
R
R
, 200Ω
, 200Ω
S1
20
19
14
15
13
SENSE
BAT1
S2
THERM
SDA
V
DD
R6
68Ω
BAT2
R
RNR
10k
RUR
1k
SCL
WEAK
475k
V
SET
C8
0.047µF
INTB
PGND
C7
0.015µF
SMBus
INTB
TO
SCL
SDA
HOST
1759 F10
D1: MBRS130LT3
D2: FMMD7000
L1: SUMIDA CDRH127-150
Q1: Si3457DV
Q2, Q3: Si3456DV
Figure 10. 4A SMBus Smart Battery Charger
23
LTC1759
U
W U U
APPLICATIONS INFORMATION
Step 1: Determine RSENSE. Using your chosen IMAX for
your maximum charge current, calculate the sense resis-
tor value and round to the nearest standard value. Any
roundingerrorismadeupbytheRSET resistorcalculation.
The value of the VSENSE voltage is user-definable. A good
trade-off between minimize power dissipation in the cur-
rent sense resistor and maintaining good current scale
accuracy is to use VSENSE = 100mV for full-scale current.
efficiency in the upper range of low current operation. In
practice 15µH is the lowest value recommended for use.
Calculating IC Power Dissipation
The power dissipation of the LTC1759 is dependent upon
the gate charge of Q2 and Q3. The gate charge is deter-
mined from the manufacturer’s data sheet and is depen-
dent upon both the gate voltage swing and the drain
voltage swing of the FET.
RSENSE = VSENSE MAX
/I
RSENSE = 0.1V/4.092A = 0.024Ω
Use RSENSE = 0.025Ω
PD = (VVCC – VGBIAS)[fPWM(QG2 + QG3)] + VVCC • IVCC
Example: VVCC = 18V, VGBIAS = 8.9V, fPWM = 230kHz,
QG2 = QG3 = 20nC, IVCC = 20mA.
Step 2: Determine the value of RSET. VREF is 2.465V.
Round RSET to the nearest standard value.
PD = (18V – 8.9V)(230kHz • 40nC) + 18V • 20mA
= 437mW
RSET = VREF/(1.25 • IMAX) • RS1/RSENSE
RSET = 2.465/(1.25 • 4.092) • 200/0.025 = 3.855k
Use RSET = 3.83kΩ
Soft Start and Undervoltage Lockout
The LTC1759 is soft started by the 0.33µF capacitor on the
VC pin. On start-up, VC pin voltage will rise quickly to 0.5V,
then ramp up at a rate set by the internal 45µA pull-up
current and the external capacitor. Battery charging cur-
rent starts ramping up when VC voltage reaches 0.7V and
full current is achieved with VC at 1.1V. With a 0.33µF
capacitor, time to reach full charge current is about 10ms
and it is assumed that input voltage to the charger will
reach full value in less than 10ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
Step 3: Determine the value of RILIMIT. This is simply a
lookup function based on your IMAX value. See the Electri-
calCharacteristicstableforallowableRILIMIT values.Refer
to Table 8 per recommended resistor values.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
In any switching regulator, conventional timer-based soft
starting can be defeated if the input voltage rises much
slower than the time out period. This happens because the
switching regulators in the battery charger and the com-
puter power supply are typically supplying a fixed amount
of power to the load. If input voltage comes up slowly
compared to the soft start time, the regulators will try to
deliver full power to the load when the input voltage is still
well below its final value. If the adapter is current limited,
it cannot deliver full power at reduced output voltages and
the possibility exists for a quasi “latch” state where the
adapter output stays in a current limited state at reduced
output voltage. For instance, if maximum charger plus
computer load power is 30W, a 15V adapter might be
current limited at 2.5A. If adapter voltage is less than
(30W/2.5A = 12V) when full power is drawn, the adapter
1
VOUT
∆IL =
VOUT 1−
f L
( )( )
V
IN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). Remember the
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductorcurrentreacheszerowhilethebottomMOSFETis
on. Lower inductor values (higher ∆IL) will cause this to
occur at higher load currents, which can cause a dip in
24
LTC1759
U
W U U
APPLICATIONS INFORMATION
voltage will be pulled down by the constant 30W load until
it reaches a lower stable state where the switching regu-
lators can no longer supply full load. This situation can be
prevented by utilizing the DCDIV resistor divider, set
higherthantheminimumadaptervoltagewherefullpower
can be achieved.
V
V
BAT
CC
0.29 (V ) 1 –
BAT
(
)
I
=
RMS
(L1)(f)
For example, VCC = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 200kHz, IRMS = 0.6A.
Input and Output Capacitors
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
maybeaddedtoincreasebatteryimpedanceatthe200kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery imped-
ance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
In the 4A Lithium Battery Charger (Figure 10), the input
capacitor (C14) is assumed to absorb all input switching
ripple current in the converter, so it must have adequate
ripple current rating. Worst-case RMS ripple current will
be equal to one half of output charging current. Actual
capacitance value is not critical. Solid tantalum low ESR
capacitors have high ripple current rating in a relatively
small surface mount package, but caution must be used
when tantalum capacitors are used for input or output
bypass.Highinputsurgecurrentscanbecreatedwhenthe
adapter is hot-plugged to the charger or when a battery is
connected to the charger. Solid tantalum capacitors have
a known failure mechanism when subjected to very high
turn-on surge currents. Only Kemet T495 series of “Surge
Robust” low ESR tantalums are rated for high surge
conditions such as battery to ground.
Charger Crowbar Protection
IfVIN connectorofFigure1chargercanbeinstantaneously
shorted (crowbarred) to ground, then a small
P-channel FET M4 should be used to fast turn off the input
P-channel FET M3 (see Figure 11), otherwise, high surge
current might damage M3. M3 can also be replaced by a
diode if dropout voltage and heat dissipation are not
problems.
The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event.
NotethatLT1759willoperateevenwhenVBAT isgrounded.
If VBAT of Figure 1 charger gets shorted to ground very
quickly (crowbarred) from a high battery voltage, slow
loop response may allow charge current to build up and
damage the topside N-channel FET M1. A small diode D5
(see Figure 12) from SDB pin to VBAT will shut down
switching and protect the charger.
Highest possible voltage rating on the capacitor will mini-
mizeproblems. Consultwiththemanufacturerbeforeuse.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. How-
ever, using ceramic capacitors in the output filter of the
charger can lead to acoustic noise radiation that can be
confused with instability. At low charge currents, the
charger operates in discontinuous current mode at an
audible frequency. Other alternative capacitors include
OSCON capacitors from Sanyo.
Note that M4 and/or D5 are needed only if the charger
system can be potentially crowbarred.
Protecting SMBus Inputs
The SMBus inputs, SCL and SDA, are exposed to uncon-
trolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to ESD which can cause
damage after repeated exposure. Also, if the battery’s
positive terminal makes contact to the connector before
the negative terminal, the SMBus inputs can be forced
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
25
LTC1759
U
W U U
APPLICATIONS INFORMATION
below ground with the full battery potential, causing a
potentialforlatch-upinanyofthedevicesconnectedtothe
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 13.
highest frequency power path loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to
keep the impedance down (see Figure 15).
PCB Layout Considerations
2. Run long power traces in parallel. Best results are
achieved if you run each trace on separate PCB layer
one on top of the other for maximum capacitance
coupling and common mode noise rejection.
The LTC1759 has two layout critical areas. The first is the
I
SET pin and the second is the DC/DC converter switching
circuity.
ISET Pin Layout: The LTC1759 ISET pin lead length is
critical and should be kept to a minimum to reduce
parasitic capacitance. Any parasitic capacitance on this
node will cause errors in the programmed current values.
Place RSET resistor directly next to the ISET pad. The trace
from RSET to the LTC1759 PROG pin pad is not critical.
3. If possible, use a ground plane under the switcher
circuitry to minimize capacitive interplane noise cou-
pling.
4. Keep signal or analog ground separate. Tie this analog
ground back to the power supply at the output ground
using a single point connection.
DC/DC PCB Layout Hints: For maximum efficiency, the
switch node rise and fall time is kept as short as possible.
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary).
5. ForbestcurrentprogrammingaccuracyprovideaKelvin
connection from RSENSE to RS1 and RS2. See Figure 14
as an example.
Interfacing with a Selector
The LTC1759 is designed to be used with a true analog
multiplexer for the thermistor sensing path. Some selec-
tor ICs from various manufacturers may not implement
this. Consult LTC applications department for more infor-
mation.
1. Keep the highest frequency loop path as small and tight
as possible. This includes the bypass capacitors, with
the higher frequency capacitors being closer to the
noise source than the lower frequency capacitors. The
R
S4
M3
V
IN
V
CC
Electronic Loads
M4
The LTC1759 is designed to work with a real battery.
Electronic loads will create instability within the LTC1759
preventing accurate programming currents and voltages.
Consult LTC applications department for more informa-
tion.
TPO610
LTC1759
INFET
1759 F11
Figure 11. VIN Crowbar Protection
V
DD
CHGEN
FOR ESD PROTECTION
TO SYSTEM
100k
LTC1759
CONNECTOR
TO BATTERY
SDB
D5
1N4148
FOR ESD AND LATCH-UP
PROTECTION
1759 F12
V
BAT
1759 F13
Figure 12. VBAT Crowbar Protection
Figure 13
26
LTC1759
U
W U U
APPLICATIONS INFORMATION
a crude voltage level detector looking for voltage going
below approximately one volt on the emitter. The RC
circuit consisting of R4 and C1 filters low pulses from the
Charging Indication
When a CHARGECURRENT() command with a value of
zero is sent to the LTC1759, current stops flowing into the
battery.However,thecommanddoesnotcausetheCHGEN
pin to pull low. This prevents use of the CHGEN pin as a
charge termination indication. Figure 16 shows a circuit
that reliably indicates when the battery is receiving a
charge current.
I
SET pin. Q2 buffers the RC filter circuit allowing a more
logic level type interface. The circuit is powered from the
logic output driver of the CHGEN pin of the LTC1759. The
circuit does not need any capacitive supply bypassing to
function and draws little current. When the CHGEN pin
goes low, the current consumption of the circuit is elimi-
nated. Note that some resistor values must change de-
pending on the supply voltage connected to the VDD pin of
the LTC1759. An optional low power 555 timer can be
added to to give a blinking LED charge indication.
The circuit shown, except for the optional 555 timer IC,
filters out the ISET DAC 80kHz output into a smooth signal.
Q1 and R5 partially isolate the capacitance of C1 from
effecting the ISET pin of the LTC1759. Q1 is configured as
SWITCH NODE
L1
DIRECTION OF CHARGING CURRENT
V
BAT
HIGH
FREQUENCY
CIRCULATING
PATH
R
SENSE
C
D1
C
OUT
V
IN
BAT
IN
1759 F14
TO R AND R
S1
S2
1759 F15
Figure 15. High Speed Switching Path
Figure 14. Kelvin Sensing of Charging Current
V
DD
LMC555
GROUND
R2
1
2
3
4
8
7
6
5
4.7k
V
CC
CHARGE
TRIGGER DISCHARGE
OUTPUT THRESHOLD
R1
R1
C2
0.1µF
R3
2.7M
RESET
CONTROL
VOLTAGE
3.3V = 240Ω
5V = 510Ω
U2
LTC1759
7
16
4
22
21
8
C3
0.1µF
(OPTIONAL, SEE TEXT)
UV
V
DCIN
DCDIV
INFET
V
DD
DD
SYNC
SDB
5
32
33
9
V
CC
R4
4.7M
12
25
24
18
17
28
27
11
6
CHGEN
BOOSTC
CLP
V
LIMIT
D
10
2
G
I
CLN
LIMIT
Q2, 2N7002
S
C1
0.1µF
DGND
TGATE
SW
R5
10k
R6
3
I
SET
35
1
PROG
BGATE
BOOST
GBIAS
SPIN
R6
Q1
MMBT3904
3.3V = 330k
5V = 680k
V
C
34
30
29
31
23
26
36
R7
330k
COMP1
AGND
RNR
20
19
14
15
13
SENSE
BAT1
BAT2
THERM
SDA
SCL
V
SET
INTB
PGND
1759 F16
Figure 16. Battery Charge Indicator Circuit
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1759
U
TYPICAL APPLICATION
4A SMBus Smart Battery Charger
R1
15.8k
R2
1k
R
, 0.033Ω
CL
Q1
AC
ADAPTER
INPUT
C15
10µF
35V
Al
C14
0.1µF
+
LTC1759
R3
499Ω
V
22
21
8
7
16
4
DD
UV
V
DCIN
C9, 0.1µF
C2
DCDIV
INFET
DD
0.47µF
SYSTEM
POWER
SYNC
SDB
C1
1µF
5
32
9
V
CC
C16
12
25
24
18
17
28
27
11
6
CHGEN
CLP
CLN
22µF
R
R
, 33k
10
2
VLIMIT
, 33k
V
LIMIT
ILIMIT
C4, 0.1µF
C5, 2.2µF
Q2
Q3
I
TGATE
BOOSTC
GBIAS
BOOST
SW
LIMIT
L1
15µH
R
SENSE
33
34
1
DGND
0.025Ω
C6
0.68µF
R
SET, 3.83k
I
+
SET
D2
D2
C3
22µF
C11, 1µF
C13, 0.33µF
C12, 0.68µF
PROG
SMART
BATTERY
D1
R4, 1.5k
R7, 1k
3
V
C
35
30
29
31
23
26
36
COMP1
AGND
RNR
BGATE
SPIN
R
R
, 200Ω
, 200Ω
S1
20
19
14
15
13
SENSE
BAT1
S2
THERM
SDA
V
DD
R6
68Ω
BAT2
R
RNR
10k
RUR
1k
SCL
WEAK
475k
V
SET
C8
0.047µF
INTB
PGND
C7
0.015µF
SMBus
INTB
TO
SCL
SDA
HOST
1759 F10
D1: MBRS130LT3
D2: FMMD7000
L1: SUMIDA CDRH127-150
Q1: Si3457DV
Q2, Q3: Si3456DV
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
12.67 – 12.93*
(0.499 – 0.509)
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
0° – 8°
7.65 – 7.90
(0.301 – 0.311)
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
5
7
8
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
G36 SSOP 1098
RELATED PARTS
PART NUMBER
LTC1473
LTC1479
LT1505
DESCRIPTION
Dual PowerPathTM Switch Driver
COMMENTS
Switches Between Two Voltages
PowerPath Controller for Dual Battery Systems
High Efficiency Constant-Current/Constant-Voltage Charger
Monolithic 3A Constant-Current/Constant-Voltage Charger
SMBus Accelerator in SOT-23 Package
Switches Two Batteries, AC Adapter and Charger
Up to 97% Efficiency with Input Current Limiting
Input Current Limiting; No External MOSFETs
Improves SMBus Data Integrity
LT1511
LTC1694
LT1769
Monolithic 2A Constant-Current/Constant-Voltage Charger
Similar to LT1511 but 2A Rating, 28-Pin SSOP Package
PowerPath is a trademark of Linear Technology Corporation.
1759f LT/TP 0500 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 1998
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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