LTC2254CUH_技术文档

LTC2255/LTC2254

14-Bit, 125/105Msps

Low Power 3V ADCs

U

FEATURES

DESCRIPTIO

The LTC^®2255/LTC2254 are 14-bit 125Msps/105Msps,

low power 3V A/D converters designed for digitizing high

frequency, wide dynamic range signals. The LTC2255/

LTC2254 are perfect for demanding imaging and commu-

nications applications with AC performance that includes

72.3dB SNR and 85dB SFDR for signals at the Nyquist

frequency.

■

Sample Rate: 125Msps/105Msps

■

Single 3V Supply (2.85V to 3.4V)

■

Low Power: 395mW/320mW

■

72.4dB SNR

88dB SFDR

No Missing Codes

■

Flexible Input: 1V_P-Pto 2V_P-PRange

■

640MHz Full Power Bandwidth S/H

DCspecsinclude±1LSBINL(typ), ±0.5LSBDNL(typ)and

■

Clock Duty Cycle Stabilizer

no missing codes over temperature. The transition noise

■

Shutdown and Nap Modes

is a low 1.3 LSB_RMS

.

■

Pin Compatible Family

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.3V

logic.

125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)

105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)

80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)

65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)

40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)

25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)

10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)

Asingle-endedCLKinputcontrolsconverteroperation.An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

■

32-Pin (5mm × 5mm) QFN Package

U

APPLICATIO S

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Ultrasound

Spectral Analysis

Portable Instrumentation

■

U

TYPICAL APPLICATIO

LTC2255: SNR vs Input Frequency,

–1dB, 2V Range, 125Msps

75

REFH

FLEXIBLE

REFERENCE

REFL

74

73

72

71

70

69

68

67

66

65

OV

DD

D13

+

14-BIT

PIPELINED

ADC CORE

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

INPUT

S/H

–

D0

OGND

CLOCK/DUTY

CYCLE

CONTROL

0

100 150 200 250 300 350

50

33554 G09

INPUT FREQUENCY (MHz)

22554 TA01a

CLK

22554f

1

LTC2255/LTC2254

W W

U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

OV = V (Notes 1, 2)

DD

Su^Dp^Dply Voltage (V_DD)................................................. 4V

Digital Output Ground Voltage (OGND) .......–0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage .................... –0.3V to (V_DD+ 0.3V)

Digital Output Voltage................–0.3V to (OV_DD+ 0.3V)

Power Dissipation............................................ 1500mW

Operating Temperature Range

TOP VIEW

ORDER PART

NUMBER

32 31 30 29 28 27 26 25

LTC2255CUH

LTC2255IUH

LTC2254CUH

LTC2254IUH

+

–

AIN

1

2

3

4

5

6

7

8

24 D10

23 D9

REFH

REFL

D8

OV

22

21

DD

33

20 OGND

D7

LTC2255C, LTC2254C ............................. 0°C to 70°C

LTC2255I, LTC2254I ...........................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

19

QFN PART*

MARKING

V

18 D6

17 D5

DD

GND

9

10 11 12 13 14 15 16

UH PACKAGE

2255

2254

32-LEAD (5mm × 5mm) PLASTIC QFN

T_JMAX= 125°C, θ_JA= 34°C/W

EXPOSED PAD (PIN 33) IS GND

MUST BE SOLDERED TO PCB

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

*The temperature grade is identified by a label on the shipping container.

U

CO VERTER CHARACTERISTICS ^The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

LTC2255

TYP

LTC2254

TYP

PARAMETER

CONDITIONS

MIN

14

MAX

MIN

14

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

●

Differential Analog Input (Note 5)

Differential Analog Input

(Note 6)

–5

±1

±0.5

±2

5

1

–5.5

–1

±1

±0.5

±2

5.5

1

LSB

–1

LSB

–12

–2.5

12

2.5

–12

–2.5

12

2.5

mV

Gain Error

External Reference

±0.5

±10

±30

±5

±0.5

±10

±30

±5

%FS

Offset Drift

µV/°C

ppm/°C

Full-Scale Drift

Internal Reference

External Reference

SENSE = 1V

Transition Noise

1.3

LSB

RMS

22554f

2

LTC2255/LTC2254

U

A ALOG I PUT

The

●

denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

±0.5V to ±1V

1.5

MAX

UNITS

V

+

–

V

Analog Input Range (A –A

)

2.85V < V < 3.4V (Note 7)

●

IN

DD

Analog Input Common Mode

Differential Input (Note 7)

1

1.9

1

V

IN,CM

+

–

I

t

Analog Input Leakage Current

SENSE Input Leakage

MODE Pin Leakage

0V < A , A < V

DD

–1

–3

µA

ns

IN

0V < SENSE < 1V

3

SENSE

MODE

AP

3

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Time Jitter

Analog Input Common Mode Rejection Ratio

Full Power Bandwidth

0

0.2

80

ps

RMS

JITTER

CMRR

dB

Figure 8 Test Circuit

640

MHz

U W

DY A IC ACCURACY

The

IN

●

denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)

A

LTC2255

TYP

LTC2254

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

dB

SNR

Signal-to-Noise Ratio

5MHz Input

72.4

72.3

72.1

71.7

88

72.5

72.4

72.3

71.7

88

30MHz Input

70MHz Input

140MHz Input

5MHz Input

●

68.9

69.4

SFDR

S/(N+D)

IMD

Spurious Free Dynamic Range

2nd or 3rd Harmonic

30MHz Input

70MHz Input

140MHz Input

5MHz Input

85

88

73

77

68

82

71

79

84

78

80

90

Spurious Free Dynamic Range

4th Harmonic or Higher

30MHz Input

70MHz Input

140MHz Input

5MHz Input

90

72.2

72

72.4

72.2

72

Signal-to-Noise Plus

Distortion Ratio

30MHz Input

70MHz Input

140MHz Input

71.9

70.2

85

68.5

70.6

85

Intermodulation

Distortion

f

= 28.2MHz

= 26.8MHz

IN1

IN2

22554f

3

LTC2255/LTC2254

U U

U

(Note 4)

I TER AL REFERE CE CHARACTERISTICS

PARAMETER

CONDITIONS

= 0

MIN

TYP

MAX

UNITS

V

CM

V

CM

V

CM

V

CM

Output Voltage

Output Tempco

Line Regulation

Output Resistance

I

1.475 1.500 1.525

OUT

±25

3

ppm/°C

mV/V

Ω

2.85V < V < 3.4V

DD

–1mA < I

< 1mA

4

OUT

U

DIGITAL I PUTS A D DIGITAL OUTPUTS

The

●

denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

2

TYP

MAX

UNITS

LOGIC INPUTS (CLK, OE, SHDN)

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

DD

V

DD

V

IN

= 3V

●

V

IH

= 3V

0.8

10

IL

I

= 0V to V

–10

µA

pF

IN

DD

C

IN

Input Capacitance

(Note 7)

3

LOGIC OUTPUTS

OV = 3V

DD

C

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

OE = High (Note 7)

3

pF

mA

OZ

I

V

OUT

V

OUT

= 0V

= 3V

50

SOURCE

SINK

V

High Level Output Voltage

I = –10µA

O

2.995

2.99

V

OH

O

I = –200µA

●

2.7

V

OL

Low Level Output Voltage

I = 10µA

0.005

0.09

V

O

I = 1.6mA

0.4

O

OV = 2.5V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –200µA

2.49

0.09

V

O

I = 1.6mA

O

OV = 1.8V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –200µA

1.79

0.09

V

O

I = 1.6mA

O

W U

POWER REQUIRE E TS

The

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 8)

A

LTC2255

TYP

LTC2254

TYP

SYMBOL

PARAMETER

CONDITIONS

(Note 9)

MIN

2.85

0.5

MAX

3.4

MIN

2.85

0.5

MAX

3.4

UNITS

V

DD

Analog Supply Voltage

Output Supply Voltage

Supply Current

●

3

OV

DD

(Note 9)

3.6

V

IV

DD

132

395

2

156

468

107

320

2

126

378

mA

mW

P

Power Dissipation

Shutdown Power

DISS

SHDN = H,

SHDN

OE = H, No CLK

P

NAP

Nap Mode Power

SHDN = H,

OE = L, No CLK

15

mW

22554f

4

LTC2255/LTC2254

W U

TI I G CHARACTERISTICS ^The

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 4)

A

LTC2255

TYP

LTC2254

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

f

t

Sampling Frequency

CLK Low Time

(Note 9)

●

1

125

1

105

MHz

s

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

(Note 7)

●

3.8

3

4

500

4.5

3

4.76

500

ns

L

t

CLK High Time

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

(Note 7)

●

3.8

3

4

500

4.5

3

4.76

500

ns

H

t

Sample-and-Hold

Aperture Delay

0

ns

AP

D

CLK to DATA delay

C = 5pF (Note 7)

●

1.4

2.7

4.3

5.4

10

1.4

2.7

4.3

5.4

10

ns

L

Data Access Time

C = 5pF (Note 7)

L

After OE↓

BUS Relinquish Time

(Note 7)

●

3.3

6

8.5

3.3

6

8.5

ns

Pipeline Latency

Cycles

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND

Note 5: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

will be clamped by internal diodes. This product can handle input currents

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 00 0000 0000 0000 and

11 1111 1111 1111.

DD

of greater than 100mA below GND or above V without latchup.

Note 7: Guaranteed by design, not subject to test.

DD

Note 4: V = 3V, f

= 125MHz (LTC2255) or 105MHz (LTC2254),

Note 8: V = 3V, f

= 125MHz (LTC2255) or 105MHz (LTC2254),

SAMPLE

DD

SAMPLE

DD

input range = 2V with differential drive, clock duty cycle stabilizer on,

input range = 1V with differential drive.

P-P

unless otherwise noted.

Note 9: Recommended operating conditions.

22554f

5

LTC2255/LTC2254

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2255: 8192 Point FFT,

f = 5MHz, –1dB, 2V Range,

IN

125Msps

LTC2255: Typical INL,

2V Range, 125Msps

LTC2255: Typical DNL,

2V Range, 125Msps

1.0

0.8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

2.0

1.5

0.6

1.0

0.4

0.5

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

60

0

4096

8192

12288

16384

0

10

20

30

40

50

0

4096

8192

12288

16384

CODE

FREQUENCY (MHz)

22554 G03

CODE

22554 G01

22554 G02

LTC2255: 8192 Point FFT,

= 140MHz, –1dB, 2V Range,

LTC2255: 8192 Point FFT,

= 30MHz, –1dB, 2V Range,

LTC2255: 8192 Point FFT,

f = 70MHz, –1dB, 2V Range,

IN

125Msps

f

IN

125Msps

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

60

0

10

20

30

40

50

0

10

20

30

40

50

60

0

10

20

30

40

50

FREQUENCY (MHz)

22554 G05

FREQUENCY (MHz)

22554 G06

FREQUENCY (MHz)

22554 G04

LTC2255: 8192 Point 2-Tone FFT,

= 28.2MHz and 26.8MHz,

LTC2255: Grounded Input

Histogram, 125Msps

f

LTC2255: SNR vs Input Frequency,

–1dB, 2V Range, 125Msps

IN

–1dB, 2V Range, 125Msps

75

74

73

72

71

70

69

68

67

66

65

25000

20000

15000

10000

5000

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

20331

18639

11975

6939

2727

3684

704

419

79

3

26 1

60

8181

8185 8187 8189 8191

0

100

150 200 250 300 350

0

10

20

30

40

50

8183

33554 G09

CODE

22554 G08

INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

22554 G07

22554f

6

LTC2255/LTC2254

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2255: SNR and SFDR vs

LTC2255: SNR vs Input Level,

IN

LTC2255: SFDR vs Input Frequency,

–1dB, 2V Range, 125Msps

Sample Rate, 2V Range,

f

= 70MHz, 2V Range, 125Msps

f

IN

= 5MHz, –1dB

80

100

95

90

80

70

60

dBFS

SFDR

70

60

90

85

80

75

70

50

40

30

20

10

SNR

dBc

0

50

65

–60 –50

–30 –20 –10

0

–70

–40

0

20 40 60 80 100 120 140 160

200

INPUT FREQUENCY (MHz)

300 350

0

50 100 150

250

SAMPLE RATE (Msps)

22554 G11

INPUT LEVEL (dBFS)

22554 G13

22554 G10

LTC2255: SFDR vs Input Level,

IN

LTC2255: I

vs Sample Rate,

VDD

f

= 70MHz, 2V Range, 125Msps

5MHz Sine Wave Input, –1dB

145

140

135

130

125

120

115

110

105

100

95

110

100

90

80

70

60

50

40

30

20

10

0

dBFS

2V RANGE

1V RANGE

dBc

–40 –30

0

20

40

60

80 100 120 140

–80 –70 –60 –50

–20 –10

0

22554 G14

22554 G15

SAMPLE RATE (Msps)

INPUT LEVEL (dBFS)

LTC2255: I

vs Sample Rate,

OVDD

LTC2255: SNR vs SENSE,

= 5MHz, –1dB

5MHz Sine Wave Input, –1dB,

f

O

= 1.8V

IN

VDD

74

73

72

71

70

69

68

67

66

65

64

8

7

6

5

4

3

2

1

0

0.4

0.6 0.7 0.8

SENSE PIN (V)

0.9 1.0 1.1

0.5

20

40

80 100 120 140

0

60

22554 G32

22554 G16

SAMPLE RATE (Msps)

22554f

7

LTC2255/LTC2254

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2254: 8192 Point FFT,

= 5MHz, –1dB, 2V Range,

f

LTC2254: Typical INL,

LTC2254: Typical DNL,

IN

105Msps

2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

2.0

1.5

1.0

0.8

0.6

1.0

0.4

0.5

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

30

FREQUENCY (MHz)

40

0

10

20

50

0

4096

8192

12288

16384

0

4096

8192

CODE

12288

16384

22554 G19

CODE

22554 G17

22554 G018

LTC2254: 8192 Point FFT,

= 30MHz, –1dB, 2V Range,

LTC2254: 8192 Point FFT,

= 70MHz, –1dB, 2V Range,

LTC2254: 8192 Point FFT,

= 140MHz, –1dB, 2V Range,

f

IN

f

IN

105Msps

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

30

20

FREQUENCY (MHz)

40

30

20

FREQUENCY (MHz)

40

0

10

50

0

10

50

30

20

FREQUENCY (MHz)

40

0

10

50

22554 G20

22554 G21

22554 G22

LTC2254: 8192 Point 2-Tone FFT,

= 28.2MHz and 26.8MHz,

LTC2254: Grounded Input

Histogram, 105Msps

LTC2254: SNR vs Input Frequency,

–1dB, 2V Range, 105Msps

f

IN

–1dB, 2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

75

74

73

72

71

70

69

68

67

66

65

20000

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

18027

17646

11299

10516

3380

581

3316

637

54

68

1

3

30

20

FREQUENCY (MHz)

40

0

10

50

8183 8185 8187 8189 8191 8193

200

INPUT FREQUENCY (MHz)

350

33554 G25

0

100 150

250 300

50

22554 G23

22554 G24

CODE

22554f

8

LTC2255/LTC2254

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2254: SNR and SFDR vs

LTC2254: SFDR vs Input Frequency,

–1dB, 2V Range, 105Msps

Sample Rate, 2V Range,

LTC2254: SNR vs Input Level,

IN

f

IN

= 5MHz, –1dB

f

= 70MHz, 2V Range, 105Msps

80

100

95

90

80

70

60

dBFS

SFDR

70

60

90

85

80

75

70

50

40

30

20

10

SNR

dBc

0

65

50

–60 –50

–30 –20 –10

0

200

INPUT FREQUENCY (MHz)

300 350

0

20

40

60

80 100 120 140

–70

–40

0

50 100 150

250

SAMPLE RATE (Msps)

22554 G27

22554 G28

22554 G26

INPUT LEVEL (dBFS)

LTC2254: SFDR vs Input Level,

IN

LTC2254: I

vs Sample Rate,

VDD

f

= 70MHz, 2V Range, 105Msps

5MHz Sine Wave Input, –1dB

110

100

90

80

70

60

50

40

30

20

10

0

120

115

110

105

100

95

dBFS

2V RANGE

1V RANGE

dBc

90

85

80

75

–40 –30

–80 –70 –60 –50

–20 –10

0

20

40

60

120

80

100

22554 G29

INPUT LEVEL (dBFS)

SAMPLE RATE (Msps)

22554 G30

LTC2254: I

vs Sample Rate,

OVDD

LTC2254: SNR vs SENSE,

= 5MHz, –1dB

5MHz Sine Wave Input, –1dB,

= 1.8V

f

O

VDD

IN

74

73

72

71

70

69

68

67

66

65

64

7

6

5

4

3

2

1

0

0.4

0.6 0.7 0.8

SENSE PIN (V)

0.9 1.0 1.1

0.5

0

60

80

100

22554 G31

120

20

40

22554 G33

SAMPLE RATE (Msps)

22554f

9

LTC2255/LTC2254

U

PI FU CTIO S

A_IN+ (Pin 1): Positive Differential Analog Input.

D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,

25, 26, 27): Digital Outputs. D13 is the MSB.

A_IN- (Pin 2): Negative Differential Analog Input.

OGND (Pin 20): Output Driver Ground.

REFH(Pins3,4):ADCHighReference.Shorttogetherand

bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 5, 6 with

an additional 2.2µF ceramic chip capacitor and to ground

with a 1µF ceramic chip capacitor.

OV_DD(Pin 21): Positive Supply for the Output Drivers.

Bypasstogroundwith0.1µFceramicchipcapacitor.OV_DD

can be 0.5V to 3.6V.

OF (Pin 28): Over/Under Flow Output. High when an over

or under flow has occurred.

REFL (Pins 5, 6): ADC Low Reference. Short together and

bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 3, 4 with

an additional 2.2µF ceramic chip capacitor and to ground

with a 1µF ceramic chip capacitor.

MODE (Pin 29): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

offset binary output format and turns the clock duty cycle

stabilizer off. 1/3 V_DDselects offset binary output format

andturnstheclockdutycyclestabilizeron.2/3V_DDselects

2’s complement output format and turns the clock duty

cycle stabilizer on. V_DDselects 2’s complement output

format and turns the clock duty cycle stabilizer off.

V

_DD(Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF

ceramic chip capacitors.

GND (Pin 8): ADC Power Ground.

CLK (Pin 9): Clock Input. The input sample starts on the

positive edge.

SENSE(Pin30):ReferenceProgrammingPin.Connecting

SENSE to V_CMselects the internal reference and a ±0.5V

input range. V_DDselects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±V_SENSE. ±1V is the largest valid input range.

SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-

ing SHDN to GND and OE to GND results in normal

operation with the outputs enabled. Connecting SHDN to

GND and OE to V_DDresults in normal operation with the

outputs at high impedance. Connecting SHDN to V_DDand

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to V_DDand OE to V_DD

results in sleep mode with the outputs at high impedance.

V_CM(Pin 31): 1.5V Output and Input Common Mode Bias.

Bypass to ground with 2.2µF ceramic chip capacitor.

GND (Exposed Pad) (Pin 33): ADC Power Ground. The

exposed pad on the bottom of the package needs to be

soldered to ground.

OE (Pin 11): Output Enable Pin. Refer to SHDN pin

function.

22554f

10

LTC2255/LTC2254

U

W

FUNCTIONAL BLOCK DIAGRA

+

A

IN

INPUT

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

–

A

IN

V

CM

1.5V

REFERENCE

SHIFT REGISTER

AND CORRECTION

2.2µF

RANGE

SELECT

REFH

REFL

INTERNAL CLOCK SIGNALS

OV

DD

REF

BUF

SENSE

OF

D13

D0

CLOCK/DUTY

DIFF

REF

AMP

CONTROL

LOGIC

OUTPUT

DRIVERS

•

CYCLE

CONTROL

22554 BD01

REFH

REFL

0.1µF

2.2µF

OGND

SHDN

OE

CLK

M0DE

1µF

Figure 1. Functional Block Diagram

W U

W

TI I G DIAGRA

Timing Diagram

t

AP

N + 4

N + 2

ANALOG

INPUT

N

N + 3

N + 5

t

H

N + 1

t

L

CLK

t

D

N – 6

N – 5

N – 4

N – 3

N – 2

N – 1

D0-D13, OF

22554 TD01

22554f

11

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

DYNAMIC PERFORMANCE

input tone to the RMS value of the largest 3rd order

intermodulation product.

Signal-to-Noise Plus Distortion Ratio

Spurious Free Dynamic Range (SFDR)

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band limited

to frequencies above DC to below half the sampling

frequency.

Spurious free dynamic range is the peak harmonic or

spurious noise that is the largest spectral component

excluding the input signal and DC. This value is expressed

in decibels relative to the RMS value of a full scale input

signal.

Signal-to-Noise Ratio

Input Bandwidth

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC.

The input bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced by

3dB for a full scale input signal.

Aperture Delay Time

Total Harmonic Distortion

ThetimefromwhenCLKreachesmid-supplytotheinstant

that the input signal is held by the sample and hold circuit.

Total harmonic distortion is the ratio of the RMS sum of all

harmonicsoftheinputsignaltothefundamentalitself.The

out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency. THD is

expressed as:

Aperture Delay Jitter

Thevariationintheaperturedelaytimefromconversionto

conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

THD = 20Log √(V2²+ V3²+ V4²+ . . . Vn²)/V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

secondthroughnthharmonics. TheTHDcalculatedinthis

data sheet uses all the harmonics up to the fifth.

SNR_JITTER= –20log (2π) • f_IN• t_JITTER

CONVERTER OPERATION

As shown in Figure 1, the LTC2255/LTC2254 is a CMOS

pipelined multistep converter. The converter has six

pipelined ADC stages; a sampled analog input will result in

a digitized value six cycles later (see the Timing Diagram

section). For optimal AC performance the analog inputs

should be driven differentially. For cost sensitive applica-

tions, the analog inputs can be driven single-ended with

slightly worse harmonic distortion. The CLK input is

single-ended. The LTC2255/LTC2254 has two phases of

operation, determined by the state of the CLK input pin.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,

etc. The 3rd order intermodulation products are 2fa + fb,

2fb + fa, 2fa – fb and 2fb – fa. The intermodulation

distortion is defined as the ratio of the RMS value of either

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

22554f

12

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

outputbytheresidueamplifier.Successivestagesoperate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

to the ADC core for processing. As CLK transitions from

high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitors still hold the previous sample, a charging glitch

proportionaltothechangeinvoltagebetweensampleswill

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

WhenCLKislow, theanaloginputissampleddifferentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that CLK transitions from low to high, the sampled input is

held. While CLK is high, the held input voltage is buffered

by the S/H amplifier which drives the first pipelined ADC

stage. The first stage acquires the output of the S/H during

this high phase of CLK. When CLK goes back low, the first

stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back

to acquiring the analog input. When CLK goes back high,

the second stage produces its residue which is acquired

by the third stage. An identical process is repeated for the

third, fourth and fifth stages, resulting in a fifth stage

residue that is sent to the sixth stage ADC for final

evaluation.

LTC2255/LTC2254

V

DD

C

SAMPLE

3.5pF

15Ω

A

+

–

IN

C

PARASITIC

1pF

V

DD

SAMPLE

3.5pF

A

C

PARASITIC

1pF

V

DD

CLK

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

thattheresultscanbeproperlycombinedinthecorrection

logic before being sent to the output buffer.

22554 F02

Figure 2. Equivalent Input Circuit

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

+

DNLwillremainunchanged.Forasingle-endedinput,A_IN

Figure 2 shows an equivalent circuit for the LTC2255/

LTC2254 CMOS differential sample-and-hold. The analog

inputsareconnectedtothesamplingcapacitors(C_SAMPLE

should be driven with the input signal and A_IN^–should be

connected to 1.5V or V_CM

.

)

through NMOS transistors. The capacitors shown at-

tached to each input (C_PARASITIC) are the summation of all

other capacitance associated with each input.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing ±0.5V for

the 2V range or ±0.25V for the 1V range, around a

common mode voltage of 1.5V. The V_CMoutput pin (Pin

31) may be used to provide the common mode bias level.

V_CMcan be tied directly to the center tap of a transformer

tosettheDCinputlevelorasareferenceleveltoanopamp

differentialdrivercircuit. TheV_CMpinmustbebypassedto

ground close to the ADC with a 2.2µF or greater capacitor.

During the sample phase when CLK is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to and track the differential input voltage.

When CLK transitions from low to high, the sampled input

voltageisheldonthesamplingcapacitors.Duringthehold

phase when CLK is high, the sampling capacitors are

disconnectedfromtheinputandtheheldvoltageispassed

22554f

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LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

Input Drive Impedance

Figure 5 shows a single-ended input circuit. The imped-

ance seen by the analog inputs should be matched. This

circuit is not recommended if low distortion is required.

As with all high performance, high speed ADCs, the

dynamic performance of the LTC2255/LTC2254 can be

influenced by the input drive circuitry, particularly the

second and third harmonics. Source impedance and reac-

tance can influence SFDR. At the falling edge of CLK, the

sample-and-hold circuit will connect the 3.5pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when CLK rises, holding the

sampled input on the sampling capacitor. Ideally the input

circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2F_ENCODE);however, thisisnotalwayspossibleandthe

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

The25Ωresistorsand12pFcapacitorontheanaloginputs

serve two purposes: isolating the drive circuitry from the

sample-and-hold charging glitches and limiting the

wideband noise at the converter input.

V

CM

2.2µF

0.1µF T1

+

25Ω

A

IN

1:1

ANALOG

INPUT

LTC2255/

LTC2254

0.1µF

25Ω

12pF

–

A

IN

25Ω

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

22554 F03

For the best performance, it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Figure 3. Single-Ended to Differential Conversion

Using a Transformer

V

CM

2.2µF

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

Input Drive Circuits

+

25Ω

A

IN

Figure 3 shows the LTC2255/LTC2254 being driven by an

RF transformer with a center tapped secondary. The

secondary center tap is DC biased with V_CM, setting the

ADC input signal at its optimum DC level. Terminating on

the transformer secondary is desirable, as this provides a

common mode path for charging glitches caused by the

sample and hold. Figure 3 shows a 1:1 turns ratio trans-

former. Other turns ratios can be used if the source

impedance seen by the ADC does not exceed 100Ω for

each ADC input. A disadvantage of using a transformer is

the loss of low frequency response. Most small RF trans-

formers have poor performance at frequencies below

1MHz.

LTC2255/

LTC2254

ANALOG

INPUT

+

CM

12pF

–

A

IN

22554 F04

Figure 4. Differential Drive with an Amplifier

V

CM

2.2µF

1k

25Ω

0.1µF

+

A

IN

ANALOG

INPUT

LTC2255/

LTC2254

12pF

Figure 4 demonstrates the use of a differential amplifier to

convert a single ended input signal into a differential input

signal. Theadvantageofthismethodisthatitprovideslow

frequencyinputresponse;however,thelimitedgainband-

width of most op amps will limit the SFDR at high input

frequencies.

–

IN

25Ω

A

224876 F05

0.1µF

Figure 5. Single-Ended Drive

22554f

14

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

U

For input frequencies above 70MHz, the input circuits of Reference Operation

Figure 6, 7 and 8 are recommended. The balun trans-

Figure 9 shows the LTC2255/LTC2254 reference circuitry

consisting of a 1.5V bandgap reference, a difference

amplifier and switching and control circuit. The internal

voltage reference can be configured for two pin selectable

input ranges of 2V (±1V differential) or 1V (±0.5V differ-

ential). Tying the SENSE pin to V_DDselects the 2V range;

tying the SENSE pin to V_CMselects the 1V range.

former gives better high frequency response than a flux

coupled center tapped transformer. The coupling capaci-

tors allow the analog inputs to be DC biased at 1.5V. In

Figure 8, the series inductors are impedance matching

elements that maximize the ADC bandwidth.

V

CM

The 1.5V bandgap reference serves two functions: its

output provides a DC bias point for setting the common

mode voltage of any external input circuitry; additionally,

the reference is used with a difference amplifier to gener-

ate the differential reference levels needed by the internal

ADC circuitry. An external bypass capacitor is required for

the 1.5V reference output, V_CM. This provides a high

frequency low impedance path to ground for internal and

external circuitry.

2.2µF

0.1µF

+

12Ω

A

8pF

A

IN

ANALOG

INPUT

LTC2255/

LTC2254

0.1µF

25Ω

T1

12Ω

–

IN

T1 = MA/COM, ETC 1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

22554 F06

Figure 6. Recommended Front End Circuit for

Input Frequencies Between 70MHz and 170MHz

The difference amplifier generates the high and low refer-

ence for the ADC. High speed switching circuits are

connected to these outputs and they must be externally

bypassed. Each output has two pins. The multiple output

V

CM

2.2µF

0.1µF

+

A

IN

ANALOG

INPUT

LTC2255/LTC2254

LTC2255/

LTC2254

0.1µF

25Ω

4Ω

V

CM

1.5V BANDGAP

REFERENCE

1.5V

T1

2.2µF

1V

0.5V

–

IN

T1 = MA/COM, ETC 1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

22554 F07

RANGE

DETECT

AND

CONTROL

Figure 7. Recommended Front End Circuit for

Input Frequencies Between 170MHz and 300MHz

TIE TO V FOR 2V RANGE;

DD

SENSE

REFH

TIE TO V FOR 1V RANGE;

CM

RANGE = 2 • V

FOR

< 1V

SENSE

BUFFER

0.5V < V

INTERNAL ADC

HIGH REFERENCE

V

1µF

CM

2.2µF

0.1µF

+

8.2nH

0.1µF

A

IN

ANALOG

INPUT

2.2µF

1µF

LTC2255/

LTC2254

0.1µF

DIFF AMP

25Ω

T1

REFL

0.1µF

8.2nH

–

INTERNAL ADC

IN

T1 = MA/COM, ETC 1-1-13

LOW REFERENCE

RESISTORS, CAPACITORS, INDUCTORS

ARE 0402 PACKAGE SIZE

22554 F08

22554 F09

Figure 8. Recommended Front End Circuit for

Input Frequencies Above 300MHz

Figure 9. Equivalent Reference Circuit

22554f

15

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

CLEAN

SUPPLY

pins are needed to reduce package inductance. Bypass

capacitors must be connected as shown in Figure 9.

4.7µF

FERRITE

BEAD

Other voltage ranges in-between the pin selectable ranges

can be programmed with two external resistors as shown

inFigure10.Anexternalreferencecanbeusedbyapplying

its output directly or through a resistor divider to SENSE.

It is not recommended to drive the SENSE pin with a logic

device. The SENSE pin should be tied to the appropriate

levelasclosetotheconverteraspossible. IftheSENSEpin

is driven externally, it should be bypassed to ground as

close to the device as possible with a 1µF ceramic capacitor.

0.1µF

1k

0.1µF

SINUSOIDAL

CLOCK

CLK

LTC2255/

LTC2254

INPUT

50Ω 1k

NC7SVU04

22554 F11

Figure 11. Sinusoidal Single-Ended CLK Drive

1.5V

V

Figures 12 and 13 show alternatives for converting a

differential clock to the single-ended CLK input. The use of

a transformer provides no incremental contribution to

phase noise. The LVDS or PECL to CMOS translators

provide little degradation below 70MHz, but at 140MHz

will degrade the SNR compared to the transformer solu-

tion. The nature of the received signals also has a large

CM

2.2µF

12k

LTC2255/

LTC2254

0.75V

12k

SENSE

1µF

22554 F10

Figure 10. 1.5V Range ADC

CLEAN

SUPPLY

4.7µF

Input Range

FERRITE

BEAD

The input range can be set based on the application. The

2Vinputrangewillprovidethebestsignal-to-noiseperfor-

mance while maintaining excellent SFDR. The 1V input

range will have better SFDR performance, but the SNR will

degrade by 5.7dB.

0.1µF

CLK

LTC2255/

LTC2254

100Ω

Driving the Clock Input

22554 F12

The CLK input can be driven directly with a CMOS or TTL

levelsignal. Asinusoidalclockcanalsobeusedalongwith

a low-jitter squaring circuit before the CLK pin (see

Figure 11).

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

The noise performance of the LTC2255/LTC2254 can

depend on the clock signal quality as much as on the

analog input. Any noise present on the clock signal will

resultinadditionalaperturejitterthatwillbeRMSsummed

with the inherent ADC aperture jitter.

ETC1-1T

CLK

LTC2255/

LTC2254

5pF-30pF

DIFFERENTIAL

CLOCK

INPUT

In applications where jitter is critical, such as when digitiz-

ing high input frequencies, use as large an amplitude as

possible. Also, if the ADC is clocked with a sinusoidal

signal, filter the CLK signal to reduce wideband noise and

distortion products generated by the source.

22554 F13

0.1µF

FERRITE

BEAD

V

CM

Figure 13. LVDS or PECL CLK Drive Using a Transformer

22554f

16

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

U

require a hundred clock cycles for the PLL to lock onto the

input clock.

bearing on how much SNR degradation will be experi-

enced. For high crest factor signals such as WCDMA or

OFDM,wherethenominalpowerlevelmustbeatleast6dB

to 8dB below full scale, the use of these translators will

have a lesser impact.

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

to make the sampling clock have a 50% (±5%) duty cycle.

The transformer in the example may be terminated with

the appropriate termination for the signaling in use. The

use of a transformer with a 1:4 impedance ratio may be

desirable in cases where lower voltage differential signals

areconsidered. Thecentertapmaybebypassedtoground

through a capacitor close to the ADC if the differential

signals originate on a different plane. The use of a capaci-

tor at the input may result in peaking, and depending on

transmission line length may require a 10Ω to 20Ω ohm

series resistor to act as both a low pass filter for high

frequency noise that may be induced into the clock line by

neighboring digital signals, as well as a damping mecha-

nism for reflections.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

Table 1. Output Codes vs Input Voltage

+

–

A

– A

D13 – D0

IN

(2V Range)

OF

(Offset Binary)

(2’s Complement)

>+1.000000V

+0.999878V

+0.999756V

1

0

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

+0.000122V

0.000000V

–0.000122V

–0.000244V

0

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

Maximum and Minimum Conversion Rates

–0.999878V

–1.000000V

<–1.000000V

0

1

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

The maximum conversion rate for the LTC2255/LTC2254

is 125Msps (LTC2255) and 105Msps (LTC2254). The

lower limit of the LTC2255/LTC2254 sample rate is deter-

mined by droop of the sample-and-hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The specified minimum operat-

ing frequency for the LTC2255/LTC2254 is 1Msps.

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OV_DDand OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures high

performance even if the input clock has a non

50% duty cycle. Using the clock duty cycle stabilizer is

recommended for most applications. To use the clock

dutycyclestabilizer, theMODEpinshouldbeconnectedto

1/3V_DDor 2/3V_DDusing external resistors.

LTC2255/LTC2254

OV

DD

0.5V

TO 3.6V

V

DD

0.1µF

OV

DD

DATA

FROM

LATCH

PREDRIVER

LOGIC

This circuit uses the rising edge of the CLK pin to sample

the analog input. The falling edge of CLK is ignored and

the internal falling edge is generated by a phase-locked

loop. Theinputclockdutycyclecanvaryfrom40%to60%

and the clock duty cycle stabilizer will maintain a constant

50% internal duty cycle. If the clock is turned off for a

long period of time, the duty cycle stabilizer circuit will

43Ω

TYPICAL

DATA

OUTPUT

OE

OGND

22554 F14

Figure 14. Digital Output Buffer

22554f

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LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

circuitry and may eliminate the need for external damping

resistors.

to 1V and must be less than OV_DD. The logic outputs will

swing between OGND and OV_DD.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2255/LTC2254 should drive a

minimal capacitive load to avoid possible interaction be-

tween the digital outputs and sensitive input circuitry. For

full speed operation the capacitive load should be kept

under 10pF.

Output Enable

The outputs may be disabled with the output enable pin,

OE.OEhighdisablesalldataoutputsincludingOF.Thedata

access and bus relinquish times are too slow to allow the

outputs to be enabled and disabled during full speed

operation. TheoutputHi-Zstateisintendedforuseduring

long periods of inactivity.

Lower OV_DDvoltages will also help reduce interference

from the digital outputs.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normaloperation.ConnectingSHDNtoV_DDandOEtoV_DD

results in sleep mode, which powers down all circuitry

includingthereferenceandtypicallydissipates1mW.When

exiting sleep mode it will take milliseconds for the output

datatobecomevalidbecausethereferencecapacitorshave

torechargeandstabilize.ConnectingSHDNtoV_DDandOE

to GND results in nap mode, which typically dissipates

15mW. In nap mode, the on-chip reference circuit is kept

on,sothatrecoveryfromnapmodeisfasterthanthatfrom

sleepmode,typicallytaking100clockcycles.Inbothsleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Data Format

Using the MODE pin, the LTC2255/LTC2254 parallel

digital output can be selected for offset binary or 2’s

complementformat.ConnectingMODEtoGNDor1/3V_DD

selects offset binary output format. Connecting MODE to

2/3V_DDor V_DDselects 2’s complement output format. An

external resistor divider can be used to set the 1/3V_DDor

2/3V_DDlogicvalues. Table2showsthelogicstatesforthe

MODE pin.

Table 2. MODE Pin Function

Clock Duty

Cycle Stablizer

MODE Pin

Output Format

Offset Binary

0

Off

On

Off

1/3V

2/3V

Offset Binary

DD

2’s Complement

Grounding and Bypassing

V

DD

The LTC2255/LTC2254 requires a printed circuit board

with a clean, unbroken ground plane. A multilayer board

withaninternalgroundplaneisrecommended.Layoutfor

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, careshouldbetakennottorunanydigitaltrack

alongside an analog signal track or underneath the ADC.

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV_DD, should be tied

to the same power supply as for the logic being driven. For

exampleiftheconverterisdrivingaDSPpoweredbya1.8V

supply,thenOV_DDshouldbetiedtothatsame1.8Vsupply.

High quality ceramic bypass capacitors should be used at

the V_DD, OV_DD, V_CM, REFH, and REFL pins. Bypass

capacitors must be located as close to the pins as pos-

sible. Of particular importance is the 0.1µF capacitor

between REFH and REFL. This capacitor should be placed

as close to the device as possible (1.5mm or less). A size

0402ceramiccapacitorisrecommended. Thelarge2.2µF

capacitor between REFH and REFL can be somewhat

22554f

OV_DDcan be powered with any voltage from 500mV up to

3.6V.OGNDcanbepoweredwithanyvoltagefromGNDup

18

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

U

further away. The traces connecting the pins and bypass

capacitorsmustbekeptshortandshouldbemadeaswide

as possible.

The lowest phase noise oscillators have single-ended

sinusoidal outputs, and for these devices the use of a filter

close to the ADC may be beneficial. This filter should be

close to the ADC to both reduce roundtrip reflection times,

as well as reduce the susceptibility of the traces between

thefilterandtheADC. Ifyouaresensitivetoclose-inphase

noise, the power supply for oscillators and any buffers

must be very stable, or propagation delay variation with

supply will translate into phase noise. Even though these

clock sources may be regarded as digital devices, do not

operate them on a digital supply. If your clock is also used

todrivedigitaldevicessuchasanFPGA, youshouldlocate

the oscillator, and any clock fan-out devices close to the

ADC, and give the routing to the ADC precedence. The

clock signals to the FPGA should have series termination

at the driver to prevent high frequency noise from the

FPGA disturbing the substrate of the clock fan-out device.

If you use an FPGA as a programmable divider, you must

re-time the signal using the original oscillator, and the re-

timing flip-flop as well as the oscillator should be close to

the ADC, and powered with a very quiet supply.

The LTC2255/LTC2254 differential inputs should run par-

allel and close to each other. The input traces should be as

shortaspossibletominimizecapacitanceandtominimize

noise pickup.

Heat Transfer

Most of the heat generated by the LTC2255/LTC2254 is

transferred from the die through the bottom-side exposed

pad and package leads onto the printed circuit board. For

goodelectricalandthermalperformance, theexposedpad

should be soldered to a large grounded pad on the PC

board. It is critical that all ground pins are connected to a

ground plane of sufficient area.

Clock Sources for Undersampling

Undersampling raises the bar on the clock source and the

higher the input frequency, the greater the sensitivity to

clock jitter or phase noise. A clock source that degrades

SNR of a full-scale signal by 1dB at 70MHz will degrade

SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

For cases where there are multiple ADCs, or where the

clock source originates some distance away, differential

clock distribution is advisable. This is advisable both from

the perspective of EMI, but also to avoid receiving noise

from digital sources both radiated, as well as propagated

in the waveguides that exist between the layers of multi-

layer PCBs. The differential pairs must be close together

and distanced from other signals. The differential pair

should be guarded on both sides with copper distanced at

least 3x the distance between the traces, and grounded

with vias no more than 1/4 inch apart.

In cases where absolute clock frequency accuracy is

relatively unimportant and only a single ADC is required,

a 3V canned oscillator from vendors such as Saronix or

Vectron can be placed close to the ADC and simply

connected directly to the ADC. If there is any distance to

the ADC, some source termination to reduce ringing that

may occur even over a fraction of an inch is advisable. You

must not allow the clock to overshoot the supplies or

performance will suffer. Do not filter the clock signal with

a narrow band filter unless you have a sinusoidal clock

source, as the rise and fall time artifacts present in typical

digital clock signals will be translated into phase noise.

22554f

19

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

22554f

20

LTC2255/LTC2254

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APPLICATIO S I FOR ATIO

U

Silkscreen Top

Topside

Inner Layer 2 GND

22554f

21

LTC2255/LTC2254

W U U

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APPLICATIO S I FOR ATIO

Inner Layer 3 Power

Bottomside

Silkscreen Bottom

22554f

22

LTC2255/LTC2254

U

PACKAGE DESCRIPTIO

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

R = 0.115

0.75 ± 0.05

OR 0.35 × 45° CHAMFER

5.00 ± 0.10

(4 SIDES)

TYP

31 32

0.00 – 0.05

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

(4-SIDES)

(UH32) QFN 1004

0.200 REF

0.25 ± 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

22554f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LTC2255/LTC2254

RELATED PARTS

PART NUMBER

LTC1747

LTC1748

LTC1749

LTC1750

LT1993

DESCRIPTION

COMMENTS

12-Bit, 80Msps ADC

72dB SNR, 87dB SFDR, 48-Pin TSSOP Package

76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package

Up to 500MHz IF Undersampling, 87dB SFDR

Up to 500MHz IF Undersampling, 90dB SFDR

600MHz BW, 75dBc Distortion at 70MHz

14-Bit, 80Msps ADC

12-Bit, 80Msps Wideband ADC

14-Bit, 80Msps Wideband ADC

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12-Bit, 170Msps ADC

LTC2220

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LTC2221

LTC2222

LTC2223

LTC2224

LTC2225

LTC2228

LTC2229

LTC2248

LTC2249

LTC2252

LTC2253

LTC2292

LTC2293

LTC2294

LTC2297

LTC2298

LTC2299

LT5512

890mW, 67.5dB SNR, 9mm x 9mm QFN Package

910mW, 67.5dB SNR, 9mm x 9mm QFN Package

660mW, 67.5dB SNR, 9mm x 9mm QFN Package

475mW, 67.9dB SNR, 7mm x 7mm QFN Package

366mW, 68dB SNR, 7mm x 7mm QFN Package

660mW, 67.5dB SNR, 7mm x 7mm QFN Package

60mW, 71.4dB SNR, 5mm x 5mm QFN Package

210mW, 71dB SNR, 5mm x 5mm QFN Package

230mW, 71.6dB SNR, 5mm x 5mm QFN Package

210mW, 74dB SNR, 5mm x 5mm QFN Package

230mW, 73dB SNR, 5mm x 5mm QFN Package

320mW, 70.2dB SNR, 5mm x 5mm QFN Package

395mW, 70.2dB SNR, 5mm x 5mm QFN Package

240mW, 71dB SNR, 9mm x 9mm QFN Package

410mW, 71dB SNR, 9mm x 9mm QFN Package

445mW, 70.6dB SNR, 9mm x 9mm QFN Package

240mW, 74dB SNR, 9mm x 9mm QFN Package

410mW, 74dB SNR, 9mm x 9mm QFN Package

445mW, 73dB SNR, 9mm x 9mm QFN Package

DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

12-Bit, 185Msps ADC

12-Bit, 135Msps ADC

12-Bit, 105Msps ADC

12-Bit, 80Msps ADC

12-Bit, 135Msps ADC

12-Bit, 10Msps ADC

12-Bit, 65Msps ADC

12-Bit, 80Msps ADC

14-Bit, 65Msps ADC

14-Bit, 80Msps ADC

12-Bit, 105Msps ADC

12-Bit, 125Msps ADC

Dual 12-Bit, 40Msps ADC

Dual 12-Bit, 65Msps ADC

Dual 12-Bit, 80Msps ADC

Dual 14-Bit, 40Msps ADC

Dual 14-Bit, 65Msps ADC

Dual 14-Bit, 80Msps ADC

DC-3GHz High Signal Level Downconverting Mixer

LT5514

Ultralow Distortion IF Amplifier/ADC Driver with Digitally

Controlled Gain

450MHz 1dB BW, 47dB OIP3, Digital Gain Control

10.5dB to 33dB in 1.5dB/Step

LT5522

600MHz to 2.7GHz High Linearity Downconverting Mixer

4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,

NF = 12.5dB, 50Ω Single-Ended RF and LO Ports

22554f

LT/LWI/TP 0605 500 • PRINTED IN USA

24 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2254CUH
厂家：	Linear
描述：	14-Bit, 125/105Msps Low Power 3V ADCs 14位， 125 / 105MSPS低功耗ADC的3V
文件：	总24页 (文件大小：608K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2254CUH [Linear]

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