LTC2754-12 [Linear]
Dual Serial 18-Bit SoftSpan IOUT DACs;
| 型号： | LTC2754-12 |
| 厂家： | 
Linear |
| 描述： | Dual Serial 18-Bit SoftSpan IOUT DACs |
| 文件： | 总24页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2758
Dual Serial 18-Bit
SoftSpan I DACs
OUT
FeaTures
DescripTion
The LTC®2758 is a dual 18-bit multiplying serial-input,
current-output digital-to-analog converter. LTC2758A
provides full 18-bit performance (INL and DNL of 1LꢀS
maximum) over temperature without any adjustments.
18-bit monotonicity is guaranteed in all performance
grades. This ꢀoftꢀpan™ DAC operates from a single 3V
to 5V supply and offers six output ranges (up to 1ꢁV)
that can be programmed through the 3-wire ꢀPI serial
interface or pin-strapped for operation in a single range.
n
Maximum 18-Bit INL Error: 1 LSB Oꢀer Temperature
n
Program or Pin-Strap Six Output Ranges:
0V to 5V, 0V to 10V, –2.5V to 7.5V, 2.5V, 5V, 10V
n
Guaranteed Monotonic Oꢀer Temperature
n
Glitch Impulse 0.4nV•s (3V), 2nV•s (5V)
n
18-Bit Settling Time: 2.1µs
n
2.7V to 5.5V ꢀingle ꢀupply Operation
n
1µA Maximum ꢀupply Current
n
Voltage-Controlled Offset and Gain Trims
n
ꢀerial Interface with Readback of All Registers
Any on-chip register (including DAC output-range set-
tings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
n
Clear and Power-On-Reset to ꢁV Regardless of
Output Range
48-Pin 7mm × 7mm LQFP Package
n
applicaTions
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to ꢁV regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ꢀoftꢀpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
n
Instrumentation
n
Medical Devices
n
Automatic Test Equipment
Process Control and Industrial Automation
n
Typical applicaTion
Dual 18-Bit VOUT DAC with Software-Selectable Ranges
LTC2758 Integral Nonlinearity
REFERENCE
1.0
+
–
5V
LT1012
GAIN A
ADJUST
0.8
0.6
0.4
0.2
0
GE
ADJA
R
INA
R
OFSA
R
COMA
REFA
5V
R
FBA
27pF
V
DD
I
OUT1A
OUT2A
–0.2
–
0.1µF
V
OUTA
DAC A
I
–0.4
+
LT1468
V
V
–0.6
OSADJA
OFFSET A ADJUST
4
SPI WITH
READBACK
LTC2758
R
–0.8
–1.0
FBB
27pF
I
–
OUT1B
0
65536
131072
CODE
196608
262143
V
OUTB
I
DAC B
+
OUT2B
2758 TA01b
LT1468
OFFSET B ADJUST
GND
GE
OSADJB
R
OFSB
REFB
R
R
INB
ADJB
COMB
2758 TA01a
–
+
GAIN B
ADJUST
LT1012
REFERENCE
5V
2758fb
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For more information www.linear.com/LTC2758
LTC2758
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
I
, I
to GND............................................ ꢁ.3V
OUT1X OUT2X
R
, R
, REFX, R , R
, V
,
INX COMX
FSX OFꢀX OꢀADJX
GE
to GND ....................................................... 18V
ADJX
V
to GND..................................................–ꢁ.3V to 7V
DD
Digital Inputs to GND...................................–ꢁ.3V to 7V
Digital Outputs to GND .....–ꢁ.3V to V +ꢁ.3V (max 7V)
Operating Temperature Range
REF A
REF A
1
2
3
4
5
6
7
8
9
36 REF B
35 REF B
34 R
COMB
DD
R
COMA
GE
LTC2758C ................................................ ꢁ°C to 7ꢁ°C
LTC2758I .............................................–4ꢁ°C to 85°C
Maximum Junction Temperature .......................... 15ꢁ°C
ꢀtorage Temperature Range ..................–65°C to 15ꢁ°C
Lead Temperature (ꢀoldering, 1ꢁ sec)...................3ꢁꢁ°C
33 GE
ADJB
ADJA
R
R
32 R
31 R
INA
INB
INA
INB
GND
30 GND
I
I
29 I
28 I
OUT2AS
OUT2BS
OUT2AF
OUT2BF
GND 10
CS/LD 11
SDI 12
27 GND
26 LDAC
25 S2
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
T
JMAX
= 15ꢁ°C, θ = 53°C/W
JA
orDer inForMaTion
http://www.linear.com/product/LTC2758#orderinfo
LEAD FREE FINISH
LTC2758SCLX#PSF
LTC2758SILX#PSF
LTC2758ACLX#PSF
LTC2758AILX#PSF
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2758LX
LTC2758LX
LTC2758LX
LTC2758LX
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
ꢁ°C to 7ꢁ°C
–4ꢁ°C to 85°C
ꢁ°C to 7ꢁ°C
–4ꢁ°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/. ꢀome packages are available in 5ꢁꢁ unit reels through
designated sales channels with #TRMPSF suffix.
2758fb
2
For more information www.linear.com/LTC2758
LTC2758
elecTrical characTerisTics VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2758B
TYP
LTC2758A
SYMBOL
Static Performance
Resolution
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
l
l
l
l
l
18
18
18
18
Sits
Sits
Monotonicity
DNL
INL
GE
Differential Nonlinearity
Integral Nonlinearity
1
2
ꢁ.2
ꢁ.5
6
1
1
LꢀS
LꢀS
Gain Error
All Output Ranges
∆Gain/∆Temp
48
32
LꢀS
Gain Error Temperature Coefficient
Sipolar Zero Error
ꢁ.25
ꢁ.25
1
ppm/°C
LꢀS
l
SZE
All Sipolar Ranges
36
24
Sipolar Zero Temperature Coefficient
Unipolar Zero-ꢀcale Error
Power ꢀupply Rejection
ꢁ.2
ꢁ.2
ꢁ.ꢁ3
ppm/°C
LꢀS
l
Unipolar Ranges (Note 3)
ꢁ.ꢁ3
3.2
3.2
l
l
PꢀR
V
DD
V
DD
= 5V, 1ꢁ0
= 3V, 1ꢁ0
1.6
4
ꢁ.1
ꢁ.3
ꢁ.8
2
LꢀS/V
LꢀS/V
I
I
Leakage Current
T = 25°C
MIN
ꢁ.ꢁ5
2
5
ꢁ.ꢁ5
2
5
nA
nA
LKG
OUT1
A
l
T
to T
MAX
VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Pins
l
l
l
l
l
l
Reference Inverting Resistors
DAC Input Resistance
Feedback Resistors
(Note 4)
16
8
2ꢁ
1ꢁ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
R
R
R
R
R
(Notes 5, 6)
(Note 6)
REF
8
1ꢁ
FS
Sipolar Offset Resistors
Offset Adjust Resistors
Gain Adjust Resistors
Output Capacitance
(Note 6)
16
2ꢁ
OFꢀ
1ꢁ24
2ꢁ48
128ꢁ
256ꢁ
VOꢀADJ
GEADJ
IOUT1
C
Full-ꢀcale
Zero-ꢀcale
9ꢁ
4ꢁ
Dynamic Performance
Output ꢀettling Time
ꢀpan Code = ꢁꢁꢁꢁ, 1ꢁV ꢀtep. To ꢁ.ꢁꢁꢁ40
Fꢀ (Note 7)
2.1
μs
Glitch Impulse
V
V
= 5V (Note 8)
= 3V (Note 8)
2
ꢁ.4
nV•s
nV•s
DD
DD
Digital-to-Analog Glitch Impulse
Reference Multiplying SW
Multiplying Feedthrough Error
V
V
= 5V (Note 9)
= 3V (Note 9)
2.6
ꢁ.6
nV•s
nV•s
DD
DD
ꢁV to 5V Range,
Code = Full ꢀcale, –3dS Sandwidth
1
MHz
ꢁV to 5V Range, V
ꢀine Wave
=
1ꢁV, 1ꢁkHz
ꢁ.4
mV
REF
Analog Crosstalk
(Note 1ꢁ)
–1ꢁ9
–11ꢁ
13
dS
dS
THD
Total Harmonic Distortion
Output Noise Voltage Density
(Note 11) Multiplying
(Note 12) at I
nV/√Hz
OUT1
2758fb
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For more information www.linear.com/LTC2758
LTC2758
elecTrical characTerisTics VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
l
l
V
ꢀupply Voltage
2.7
5.5
2
V
DD
I
DD
V
ꢀupply Current
Digital Inputs = ꢁV or V
DD
ꢁ.5
μA
DD
Digital Inputs
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
3.3V ≤ V ≤ 5.5V
2.4
2
V
V
IH
DD
2.7V ≤ V < 3.3V
DD
l
l
V
IL
4.5V < V ≤ 5.5V
ꢁ.8
ꢁ.6
V
V
DD
2.7V ≤ V ≤ 4.5V
DD
Hysteresis Voltage
ꢁ.1
V
µA
pF
l
l
I
IN
Digital Input Current
Digital Input Capacitance
V
V
= GND to V
DD
1
6
IN
IN
C
= ꢁV (Note 13)
IN
Digital Outputs
l
l
V
OH
V
OL
I
I
= 2ꢁꢁµA
= 2ꢁꢁµA
2.7V ≤ V ≤ 5.5V
V – ꢁ.4
DD
V
V
OH
OL
DD
2.7V ≤ V ≤ 5.5V
ꢁ.4
DD
TiMing characTerisTics The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= 4.5V to 5.5V
l
l
l
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
t
t
ꢀDI Valid to ꢀCK ꢀet-Up
ꢀDI Valid to ꢀCK Hold
ꢀCK High Time
7
7
ns
ns
1
2
11
11
9
ns
3
ꢀCK Low Time
ns
4
CS/LD Pulse Width
ns
5
LꢀS ꢀCK High to CS/LD High
CS/LD Low to ꢀCK Positive Edge
CS/LD High to ꢀCK Positive Edge
ꢀRO Propagation Delay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/LD High to RFLAG High
ꢀCK Frequency
4
ns
6
4
ns
7
4
ns
8
C
= 1ꢁpF
18
ns
9
LOAD
36
15
ns
1ꢁ
11
12
13
ns
C
C
= 1ꢁpF (Note 13)
= 1ꢁpF (Note 13)
5ꢁ
4ꢁ
4ꢁ
ns
LOAD
ns
LOAD
5ꢁ0 Duty Cycle (Note 14)
MHz
V
DD
= 2.7V to 3.3V
l
l
l
l
l
l
t
t
t
t
t
t
ꢀDI Valid to ꢀCK ꢀet-Up
ꢀDI Valid to ꢀCK Hold
ꢀCK High Time
9
9
ns
ns
ns
ns
ns
ns
1
(Note 13)
2
3
4
5
6
C = 1ꢁpF
L
15
15
12
5
ꢀCK Low Time
CS/LD Pulse Width
LꢀS ꢀCK High to CS/LD High
2758fb
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For more information www.linear.com/LTC2758
LTC2758
TiMing characTerisTics The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
5
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
CS/LD Low to ꢀCK Positive Edge
CS/LD High to ꢀCK Positive Edge
ꢀRO Propagation Delay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/LD High to RFLAG high
ꢀCK Frequency
7
5
ns
8
C
LOAD
= 1ꢁpF
26
ns
9
6ꢁ
2ꢁ
ns
1ꢁ
11
12
13
ns
C
C
= 1ꢁpF (Note 13)
= 1ꢁpF (Note 13)
7ꢁ
6ꢁ
25
ns
LOAD
ns
LOAD
5ꢁ0 Duty Cycle (Note 14)
MHz
Note 1: ꢀtresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 8: Measured at the major carry transition, ꢁV to 5V range. Output
amplifier: LT1468; C = 5ꢁpF.
FS
Note 9: Full-scale transition; REF = ꢁV.
Note 10: Analog Crosstalk is defined as the AC voltage ratio V
/V
,
OUTS REFA
expressed in dS. REFS is grounded, and DAC S is set to ꢁV-5V span and
zero-, mid- or full- scale code. V is a 3V , 1kHz sine wave.
REFA
RMꢀ
Note 3: Calculation from feedback resistance and I
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
leakage current
OUT1
Note 11: REF = 6V
amplifier = LT1468.
Note 12: Calculation from V = √4kTRB, where k = 1.38E-23 J/°K
(Soltzmann constant), R = resistance (Ω), T = temperature (°K), and S =
bandwidth (Hz). ꢁV to 5V Range; zero-, mid-, or full-scale.
at 1kHz. ꢁV to 5V range. DAC code = Fꢀ. Output
RMꢀ
n
Note 4: Input resistors measured from R to R
; feedback resistors
INX
COMX
measured from R
to REFX.
COMX
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
and from the specified pin to I
Note 13: Guaranteed by design; not production tested.
Note 14: When using ꢀRO, maximum ꢀCK frequency f
is limited by
MAX
I
.
OUT2X
OUT1X
ꢀRO propagation delay t as follows:
9
Note 7: Using LT1468 with C
= 27pF. A ꢁ.ꢁꢁꢁ40 settling time
FEEDSACK
⎛
⎞
1
of 1.8µs can be achieved by optimizing the time constant on an individual
basis. ꢀee Application Note 12ꢁ, 1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
fMAX
=
⎜
⎟
, where t is the setup time of the receiving device.
ꢀ
2 t + t
(
)
⎝
⎠
9
ꢀ
2758fb
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For more information www.linear.com/LTC2758
LTC2758
Typical perForMance characTerisTics
VDD = 5V, V(RINX) = 5V, TA = 25°C, unless otherwise noted.
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL ꢀs Output Range
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–2.5V –2.5V 0V
–5V
TO
5V
0V
TO
10V
–10V
TO
10V
0
65536
131072
CODE
196608
262143
0
65536
131072
CODE
196608
262143
TO
TO
TO
5V
2.5V 7.5V
2758 G01
2758 G02
OUTPUT RANGE
2758 G03
INL ꢀs Temperature
DNL ꢀs Temperature
Gain Error ꢀs Temperature
1.0
0.8
1.0
0.8
32
28
24
20
16
12
8
0ꢀ25ꢁꢁpm°C TꢂP
2ꢀ5ꢃ
0V TO 10V RANGE
0V TO 10V RANGE
5ꢃ
10ꢃ
0.6
0.6
0ꢃ TO 5ꢃ
+INL
0ꢃ TO 10ꢃ
0.4
0.4
–2ꢀ5ꢃ TO 7ꢀ5ꢃ
0.2
0.2
+DNL
0
0
–INL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–DNL
4
0
–40
–20
0
20
40
60
8085
–40
–20
0
20
40
60
8085
–40
–20
0
20
40
60
8085
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2758 G04
2758 G05
2758 G06
Bipolar Zero Error
ꢀs Temperature
DNL ꢀs Reference Voltage
INL ꢀs Reference Voltage
16
12
8
1.0
0.8
1.0
0.8
0ꢁ15ꢂꢂpm°C TꢃP
5V RꢀNGꢁ
5V RꢀNGꢁ
0.6
0.6
+INL
–INL
+INL
–INL
0.4
0.4
4
0.2
0.2
+DNL
–DNL
+DNL
–DNL
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–4
–8
–12
–16
5ꢀ
10ꢀ
2ꢁ5ꢀ
–2ꢁ5ꢀ TO 7ꢁ5ꢀ
40 60 8085
TEMPERATURE (°C)
–40
–20
0
20
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
V(R ) (V)
V(R ) (V)
IN
IN
2758 G07
2758 G08
2758 G09
2758fb
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For more information www.linear.com/LTC2758
LTC2758
Typical perForMance characTerisTics
VDD = 5V, V(RINX) = 5V, TA = 25°C, unless otherwise noted.
Multiplying Frequency Response
ꢀs Digital Code
INL ꢀs VDD
DNL ꢀs VDD
1.0
0.8
1.0
0.8
ALL BITS ON
D17
D16
D15
D14
D13
D12
D11
D10
D9
0
–20
0V TO 10V RANGE
0V TO 10V RANGE
0.6
0.6
+INL
–INL
0.4
0.4
–40
0.2
0.2
+DNL
–DNL
D8
–60
D7
0
0
D6
D5
–80
D4
D3
D2
D1
D0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
0V TO 5V OUTPUT RANGE
LT1468 OUTPUT AMPLIFIER
FEEDBACK
ALL BITS OFF
C
= 15pF
100
1k
10k
100k
1M
10M
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
(V)
DD
FREQUENCY (Hz)
DD
2758 G10
2758 G11
2758 G12
Settling Full-Scale Step
Mid-Scale Glitch (VDD = 3V)
Mid-Scale Glitch (VDD = 5V)
0.4nV•s TYP
2nV•s TYP
CS/LD
5V/DIV
CS/LD
5V/DIV
CS/LD
5V/DIV
GATED
SETTLING
WAVEFORM
100µV/DIV
(AVERAGED)
V
OUT
V
OUT
5mV/DIV
5mV/DIV
(AVERAGED)
(AVERAGED)
2758 G14
2758 G13
2758 G15
500ns/DIV
500ns/DIV
500ns/DIV
0V TO 5V RANGE
LT1468 AMP; C
= 20pF
0V TO 5V RANGE
FEEDBACK
LT1468 OUTPUT AMPLIFIER
0V TO 10V STEP
LT1468 OUTPUT AMPLIFIER
C
= 50pF
FEEDBACK
V
= –10V; SPAN CODE = 0000
= 1.8µs to 0.0004% (18 BITS)
C
= 50pF
REF
FEEDBACK
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
t
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
SETTLE
Supply Current
ꢀs Logic Input Voltage
Logic Threshold
ꢀs Supply Voltage
Supply Current
ꢀs Update Frequency
2
1.75
1.5
5
4
3
2
1
0
100
10
ALTERNATING ZERO-SCALE
AND FULL-SCALE
CLR, LDAC, SDI, SCK,
CS/LD TIED TOGETHER
RISING
1
V
DD
= 5V
1.25
1
0.1
FALLING
V
DD
= 3V
0.01
0.001
V
= 5V
DD
3
0.75
0.5
V
= 3V
DD
2
0.0001
2.5
3.5
4
4.5
5
5.5
3
0
1
4
5
1
100
10k
1M
100M
V
(V)
DD
DIGITAL INPUT VOLTAGE (V)
SCK FREQUENCY (Hz)
2758 G16
2758 G18
2758 G17
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LTC2758
pin FuncTions
REFA (Pins 1, 2): Feedback Resistor for the DAC A Refer-
ence Inverting Amplifier, and Reference Input for DAC A.
The 2ꢁk feedback resistor is connected internally from
SRO (Pin 14): ꢀerial Readback Output. Data is clocked out
on the falling edge of ꢀCK. Readback data begins clocking
out after the last address bit Aꢁ is clocked in. ꢀRO is an
active output only when the chip is selected (i.e., when
CS/LDislow). Otherwise ꢀROpresents a high-impedance
output in order to allow other parts to control the bus.
REFA to R . For normal operation tie this pin to the
COMA
output of the DAC A reference inverting amplifier (see
Typical Application). Typically –5V; accepts up to 15V.
Pins 1 and 2 are internally shorted together.
V
(Pin16):PositiveꢀupplyInput;2.7V≤V ≤5.5V. Sy-
DD
DD
R
(Pin 3): Virtual Ground Point for the DAC A Ref-
pass with a ꢁ.1μF low-EꢀR ceramic capacitor to ground.
COMA
erence Amplifier Inverting Resistors. The 2ꢁk reference
CLR (Pin 19): Asynchronous Clear Input. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
inverting resistors are connected internally from R to
INA
R
COMA
and from R
to REFA, respectively (see Slock
COMA
Diagram). For normal operation tie R
to the negative
COMA
RFLAG (Pin 20): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
input of the external reference inverting amplifier (see
Typical Application).
GE
(Pin 4): Gain Adjust Pin for DAC A. This control pin
ADJA
DNC (Pin 21): Do Not Connect.
canbeusedtonullgainerrorortocompensateforreference
errors. The gain change expressed in LꢀS is the same for
anyoutputrange.ꢀeeSystemOffsetandGainAdjustments
in the Operation section. Tie to ground if not used.
M-SPAN (Pin 22): Manual ꢀpan Control Pin. M-ꢀPAN is
used in conjunction with pins ꢀ2, ꢀ1 and ꢀꢁ (Pins 25, 24
and 23) to configure all DACs for operation in a single,
fixed output range.
R
(Pins 5, 6): Input Resistor for the DAC A External
INA
Reference Inverting Amplifier. The 2ꢁk input resistor is
To configure the part for manual-span use, tie M-ꢀPAN
connected internally from R to R
. For normal op-
INA
COMA
directly to V . The DAC output range is then set via
DD
eration tie R to the external positive reference voltage
INA
hardware pin strapping of pins ꢀ2, ꢀ1 and ꢀꢁ (rather than
through the ꢀPI port); and Write and Update commands
have no effect on the active output span.
(seeTypicalApplication).Eitherorbothoftheseprecision-
matched resistor sets (each set comprising R , R
INX COMX
and REFX) may be used to invert positive references to
provide the negative voltages needed by the DACs. Typi-
cally 5V; accepts up to 15V. Pins 5 and 6 are internally
shorted together.
Toconfigurethepartforꢀoftꢀpanuse,tieM-ꢀPANdirectly
to GND. The output ranges are then individually control-
lable through the ꢀPI port; and pins ꢀ2, ꢀ1 and ꢀꢁ have
no effect.
GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to
ground.
ꢀeeManualSpanConfigurationintheOperationsection.M-
ꢀPANmust be connectedeitherdirectly to GND (ꢀoftꢀpan
I
, I
(Pins 8, 9): DAC A Current Output
OUT2AS OUT2AF
configuration) or to V (manual-span configuration).
DD
Complement ꢀense and Force Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Applications Information section).
S0 (Pin 23): ꢀpan Sit ꢁ Input. In Manual ꢀpan mode (M-
ꢀPAN tied to V ), Pins ꢀꢁ, ꢀ1 and ꢀ2 are pin-strapped
DD
to select a single fixed output range for all DACs. These
pins should be tied to either GND or V even if they are
DD
CS/LD (Pin 11): ꢀynchronous Chip ꢀelect and Load Input
Pin.
unused.
S1 (Pin 24): ꢀpan Sit 1 Input. In Manual ꢀpan mode (M-
SDI (Pin 12): ꢀerial Data Input. Data is clocked in on the
rising edge of the serial clock (ꢀCK) when CS/LD is low.
ꢀPAN tied to V ), Pins ꢀꢁ, ꢀ1 and ꢀ2 are pin-strapped to
DD
select a single fixed output range for all DACs. These pins
shouldbetiedtoeitherGNDorV eveniftheyareunused.
SCK (Pin 13): ꢀerial Clock Input.
DD
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pin FuncTions
S2 (Pin 25): ꢀpan Sit 2 Input. In Manual ꢀpan mode (M-
R
(Pins 37, 38): Sipolar Offset Resistor for DAC S.
OFSB
These pins provide the translation of the output voltage
range for bipolar spans. Accepts up to 15V; for normal
ꢀPAN tied to V ), Pins ꢀꢁ, ꢀ1 and ꢀ2 are pin-strapped to
DD
select a single fixed output range for all DACs. These pins
operation tie to the positive reference voltage atR (Pins
31, 32). Pins 37 and 38 are internally shorted together.
shouldbetiedtoeitherGNDorV eveniftheyareunused.
INS
DD
LDAC (Pin 26): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
R
(Pins 39, 40): DAC S Feedback Resistor. For normal
FBB
operation tie to the outputofthe I/V converteramplifierfor
DAC S (see Typical Application). The DAC output current
I
, I
(Pins 28, 29): DAC S Current Output
OUT2BF OUT2BS
from I
R
flows through the feedback resistor to the
OUT1S
Complement Force and ꢀense Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Applications Information section).
pins. Pins 39 and 4ꢁ are internally shorted together.
FSS
I
(Pin 41): DAC S Current Output. This pin is a virtual
OUT1B
ground when the DAC is operating and should reside at
ꢁV. For normal operation tie to the negative input of the
I/VconverteramplifierforDACS(seeTypicalApplication).
R
(Pins 31, 32): Input Resistor for the DAC S External
INB
Reference Inverting Amplifier. The 2ꢁk input resistor is
V
(Pin 42): DAC S Offset Adjust Pin. This voltage-
connected internally from R to R
. For normal op-
OSADJB
INS
COMS
control pin can be used to null unipolar offset or bipolar
zero error. The offset change expressed in LꢀS is the same
for any output range. ꢀee System Offset and Gain Adjust-
ments in the Operation section. Tie to ground if not used.
eration tie R to the external positive reference voltage
INS
(seeTypicalApplication).Eitherorbothoftheseprecision-
matched resistor sets (each set comprising R , R
INX COMX
and REFX) may be used to invert positive references to
provide the negative voltages needed by the DACs. Typi-
cally 5V; accepts up to 15V. Pins 31 and 32 are internally
shorted together.
V
(Pin 43): DAC A Offset Adjust Pin. This voltage-
OSADJA
control pin can be used to null unipolar offset or bipolar
zero error. The offset change expressed in LꢀS is the same
for any output range. ꢀee System Offset and Gain Adjust-
ments in the Operation section. Tie to ground if not used.
GE
(Pin 33): Gain Adjust Pin for DAC S. This control
ADJB
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LꢀS is
the same for any output range. ꢀee System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
I
(Pin 44): DAC A Current Output. This pin is a virtual
OUT1A
ground when the DAC is operating and should reside at
ꢁV. For normal operation tie to the negative input of the
I/VconverteramplifierforDACA(seeTypicalApplication).
R
(Pin 34): Virtual Ground Point for the DAC S Ref-
R
(Pins 45, 46): DAC A Feedback Resistor. For normal
COMB
FBA
erence Amplifier Inverting Resistors. The 2ꢁk reference
operation tie to the outputofthe I/V converteramplifier for
DAC A (see Typical Application). The DAC output current
inverting resistors are connected internally from RINS to
R
and from R
to REFS, respectively (see Slock
COMS
from I
flows through the feedback resistor to the
COMS
OUT1A
Diagram). For normal operation tie R
to the negative
R
FSA
pins. Pins 45 and 46 are internally shorted together.
COMS
input of the external reference inverting amplifier (see
Typical Application).
R
(Pins 47, 48): Sipolar Offset Resistor for DAC A.
OFSA
This pin provides the translation of the output voltage
range for bipolar spans. Accepts up to 15V; for normal
REFB (Pins 35, 36): Feedback Resistor for the DAC S
Reference Inverting Amplifier, and Reference Input for
DAC S. The 2ꢁk feedback resistor is connected internally
operation tie to the positive reference voltage at R
(Pins 5, 6). Pins 47 and 48 are internally shorted together.
INA
from REFS to R
. For normal operation tie this pin to
COMS
the output of the DAC S reference inverting amplifier (see
Typical Application). Typically –5V; accepts up to 15V.
Pins 35 and 36 are internally shorted together.
2758fb
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LTC2758
block DiagraM
V
DD
16
31,32
INB
5,6
INA
R
R
2.56M
GE
2.56M
ADJB
GE
ADJA
33
34
20k
20k
4
3
20k
20k
R
COMB
R
COMA
LTC2758
1,2
REFA
35,36
REFB
37,38
OFSB
47,48
OFSA
R
R
39,40
FBB
45,46
FBA
CODE REGISTERS
CODE REGISTERS
R
R
18
3
18
3
DAC REG INPUT REG
INPUT REG DAC REG
DAC A
18-BIT WITH
SPAN SELECT
DAC B
18-BIT WITH
SPAN SELECT
I
I
OUT1A
OUT1B
44
8
41
29
28
SPAN REGISTERS
SPAN REGISTERS
I
I
OUT2AS
OUT2BS
DAC REG INPUT REG
INPUT REG DAC REG
I
I
OUT2AF
OUT2BF
9
V
V
OSADJA
OSADJB
43
42
POWER-ON
RESET
CONTROL AND READBACK LOGIC
7, 10, 15, 17,
18, 27, 30
GND
M-SPAN
S0
S1
S2
RFLAG
CLR
CS/LD
SDI
SCK
LDAC
SRO
22
23
24
25
20
19
11
12
13
26
14
2758 BD
TiMing DiagraM
t
1
t
6
t
t
t
2
3
4
1
2
31
32
SCK
SDI
t
8
LSB
t
t
7
5
CS/LD
LDAC
SRO
t
11
t
9
Hi-Z
LSB
2758 TD
2758fb
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LTC2758
operaTion
V
V
Output Ranges
DD
DD
TheLTC2758isadual,current-output,serial-inputprecision
multiplyingDACwithselectableoutputranges.Rangescan
either be programmed in software for maximum flexibility
(each of the DACs can be programmed to any one of six
output ranges) or hardwired through pin-strapping. Two
unipolarrangesareavailable(ꢁVto5VandꢁVto1ꢁV), and
four bipolar ranges ( 2.5V, 5V, 1ꢁV and –2.5V to 7.5V).
These ranges are obtained when an external precision 5V
reference is used. The output ranges for other reference
voltagesareeasytocalculatebyobservingthateachrange
is a multiple of the external reference voltage. The ranges
can then be expressed: ꢁ to 1×, ꢁ to 2×, ꢁ.5×, 1×, 2×,
and –ꢁ.5× to 1.5×.
LTC2758
–
+
DAC A
DAC B
10V
M-SPAN
S2
S1
–
+
10V
S0
CS/LD SDI SCK
2754 F01
Figure 1. Using M-SPAN to Configure the LTC2758
for Single-Span Operation ( 10V Range Shown)
capabilitytosimultaneouslyupdatethespan(outputrange)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Manual Span Configuration
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2758 to operate in a single span
without additional operational overhead, tie the M-ꢀPAN
Each set of double-buffered registers comprises an Input
register and a DAC register.
pin directly to V . The active output range for all DACs is
DD
then set via hardware pin strapping of pins ꢀ2, ꢀ1 and ꢀꢁ
(rather than through the ꢀPI port); and Write and Update
commands have no effect on the active output span. ꢀee
Figure 1 and Table 3.
Input register: The Write operation shifts data from the
ꢀDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
Tie the M-ꢀPAN pin to ground for normal ꢀoftꢀpan
operation.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Input and DAC Registers
The LTC2758 has 5 internal registers for each DAC, a total
of 1ꢁ registers (see Slock Diagram). Each DAC channel
has two sets of double-buffered registers, one set for
the code data, and one for the output range of the DAC,
plus one readback register. Double buffering provides the
Note that updates always include both Code and ꢀpan
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been altered via a Write operation.
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LTC2758
operaTion
Serial Interface
data occupies the first 18 bits of the 24-bit field; and the
span bits are the last four bits of the second data byte
when checking the output range. In both cases, all other
bits in the 24-bit data field are filled by zeros. Figure 2
shows the input and readback sequences.
When the CS/LD pin is taken low, the data on the ꢀDI pin
is loaded into the shift register on the rising edge of the
clock (ꢀCK pin). The loading sequence required for the
LTC2758 is one byte consisting of a 4-bit command word
(C3 C2 C1 Cꢁ) and a 4-bit address word (A3 A2 A1 Aꢁ),
then three bytes (24 bits) of data.
The data outputted by ꢀRO is always in the same position
and sequence as the input data. Note, however, that this
means that the ꢀRO data shifts out one-half clock cycle
earlier than the corresponding bit shifting in on ꢀDI. For
example, code bit D9, which is shifted in to ꢀDI on the
rising edge of ꢀCK clock 17, is clocked out of ꢀRO on the
falling edge of clock 16. This allows D9 to be clocked to an
external microprocessor on the rising edge of clock 17.
When writing a code, the code data is left (MꢀS) justified;
so that the 24-bit data field consists of 18 code bits fol-
lowed by 6 don’t-care bits.
When writing an output range, the span data should oc-
cupy the last 4 bits of the second data byte, ordered ꢀ3
through ꢀꢁ. Figure 2 shows the ꢀDI input word syntax
for writing.
For Read commands, the requested data is shifted out
of ꢀRO in the 3-byte (24-bit) data field immediately after
the command/address byte. There is no instruction-cycle
latencyforReadcommands;thedatashiftsoutinthesame
instruction cycle in which it was requested.
When CS/LD is low, the ꢀRO pin (ꢀerial Readback Output)
is an active output. The readback data begins after the
command (C3-Cꢁ) and address (A3-Aꢁ) words have been
shifted in to ꢀDI. ꢀRO outputs a logic low from the falling
edge of CS/LD until the Readback data begins.
For non-read (i.e., Write and/or Update) commands, ꢀRO
automatically shifts out the contents of the buffer that
was acted upon in the preceding command. This “rolling
readback” default mode of operation can dramatically re-
duce the number of instruction cycles needed, since most
commands can be verified during subsequent commands
with no additional overhead. A conceptual flow diagram
is shown in Figure 3. Table 1 shows, for each anteced-
ent command, which register (‘readback pointer’) will be
copiedintotheReadbackregisterandoutputtedfromꢀRO
during the following instruction cycle.
When CS/LD is high, the ꢀRO pin presents a high imped-
ance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
Span Readback in Manual Span Configuration
Thecodesforthecommand(C3-Cꢁ)aredefinedinTable1;
Table 2 defines the codes for the address (A3-Aꢁ).
If a ꢀpan DAC register is chosen for readback, ꢀRO re-
sponds by outputting the actual output span; this is true
whethertheLTC2758isconfiguredforꢀoftꢀpan(M-ꢀPAN
Readback
tied to GND) or manual span (M-ꢀPAN tied to V ).
In addition to the Code and ꢀpan register sets, each DAC
hasoneReadbackregisterassociatedwithit.Everyinstruc-
tion cycle, the contents of one of the on-chip registers is
copied into a Readback register and serially shifted out
through the ꢀRO pin.
DD
In ꢀoftꢀpan configuration, ꢀRO outputs the span code
from the ꢀpan DAC register (programmed through the
ꢀPI port). In manual span configuration, the active output
range is controlled by pins ꢀ2, ꢀ1 and ꢀꢁ, so ꢀRO outputs
the logic values of these pins. The span code bits ꢀ2, ꢀ1
and ꢀꢁ always appear in the same order and positions in
the ꢀRO output sequence; see Figure 2.
Readback data always appears in the 24-bit data field,
starting on the falling ꢀCK edge immediately after the last
addressbitisshiftedinonꢀDI. Whenreadingacode, code
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operaTion
Table 1. Command Codes
CODE
READBACK POINTER–
CURRENT INPUT WORD W
READBACK POINTER–
NEXT INPUT WORD W
C3
C2
C1
C0
COMMAND
0
+1
ꢁ
ꢁ
1
ꢁ
Write ꢀpan DAC n
Write Code DAC n
Update DAC n
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
Input ꢀpan Register DAC n
Input Code Register DAC n
DAC ꢀpan Register DAC n
DAC Code Register DAC n
DAC ꢀpan Register DAC n
ꢁ
ꢁ
1
1
ꢁ
1
ꢁ
ꢁ
ꢁ
1
ꢁ
1
Update All DACs
ꢁ
1
1
ꢁ
Write ꢀpan DAC n
Update DAC n
ꢁ
1
1
1
ꢁ
ꢁ
1
ꢁ
ꢁ
1
ꢁ
1
Write Code DAC n
Update DAC n
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
DAC Code Register DAC n
DAC ꢀpan Register DAC n
DAC Code Register DAC n
Write ꢀpan DAC n
Update All DACs
Write Code DAC n
Update All DACs
1
1
1
1
1
ꢁ
ꢁ
1
1
1
1
1
ꢁ
ꢁ
1
ꢁ
1
ꢁ
1
1
Read Input ꢀpan Register DAC n
Read Input Code Register DAC n
Read DAC ꢀpan Register DAC n
Read DAC Code Register DAC n
No Operation
Input ꢀpan Register DAC n
Input Code Register DAC n
DAC ꢀpan Register DAC n
DAC Code Register DAC n
ꢀet by Previous Command
DAC Code Register DAC n
DAC ꢀpan Register DAC A
DAC ꢀpan Register DAC A
–
–
ꢀystem Clear
–
–
Initial Power-Up or Power Interrupt
Codes not shown are reserved–do not use
Table 2. Address Codes
Table 3. Span Codes
n
DAC A
A3
ꢁ
A2
ꢁ
A1
ꢁ
A0
×
S3 S2 S1 S0 SPAN
×
×
×
×
×
×
ꢁ
ꢁ
ꢁ
ꢁ
1
1
ꢁ
ꢁ
1
1
ꢁ
ꢁ
ꢁ
1
ꢁ
1
ꢁ
1
Unipolar ꢁV to 5V
Unipolar ꢁV to 1ꢁV
Sipolar –5V to 5V
×
ꢁ
ꢁ
1
DAC S
×
1
1
1
All DACs (Note 1)
Sipolar –1ꢁV to 1ꢁV
Sipolar –2.5V to 2.5V
Sipolar –2.5V to 7.5V
Codes not shown are reserved–do not use.
× = Don’t Care.
Note 1. If readback is taken using the All DACs address, the LTC2758
defaults to DAC A.
Codes not shown are reserved–do not use.
× = Don’t Care.
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LTC2758
operaTion
Examples
2. Load DAC S with 2.5V range with its output at zero
volts. Use readback to check Input register contents
before updating the DAC output (i.e., before copying
Input register contents into DAC registers). Note that
after power-on, the code in Input registers is zero.
1. Load DAC A with ꢁV to 1ꢁV range, output at zero
volts; and DAC S with 1ꢁV range, output at zero
volts. Note the DAC outputs should change at the
same time.
a) CS/LD↓. Clock ꢀDI:
a) CS/LD↓. Clock ꢀDI:
ꢁꢁ11ꢁꢁ1ꢁ 1ꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁXXXXXX
ꢁꢁ1ꢁ1111 ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁ11 ꢁꢁꢁꢁꢁꢁꢁꢁ
b) CS/LD↑
b) CS/LD↑
Code Input register- DAC S set to mid-scale.
ꢀpan Input register- Range of DACs set to bipolar 1ꢁV.
c) CS/LD↓. Clock ꢀDI:
c) CS/LD↓. Clock ꢀDI:
ꢁꢁ1ꢁꢁꢁ1ꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁ1ꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ
Data out on ꢀRO:
ꢁꢁ1ꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁ1 ꢁꢁꢁꢁꢁꢁꢁꢁ
d) CS/LD↑
1ꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ
Verifies Code Input register- DAC S set to mid-scale.
ꢀpan Input register- Range of DAC A set to unipolar
ꢁV to 1ꢁV.
d) CS/LD↑
e) CS/LD↓. Clock ꢀDI:
ꢀpan Input register- Range of DAC S set to Sipolar
2.5V range.
ꢁꢁ111111 1ꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁXXXXXX
f) CS/LD↑
e) CS/LD↓. Clock ꢀDI:
Code Input register- Code of all DACs set to mid-scale.
1ꢁ1ꢁꢁꢁ1ꢁ XXXXXXXX XXXXXXXX XXXXXXXX
Data Out on ꢀRO:
g) CS/LD↓. Clock ꢀDI:
ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁ1ꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ
Verifies ꢀpan Input register- DAC S set to Sipolar
2.5V Range.
ꢁꢁ11ꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁꢁꢁꢁꢁꢁꢁ ꢁꢁXXXXXX
h) CS/LD↑
Code Input register- Code of DAC A set to zero.
CS/LD↑
i) CS/LD↓. Clock ꢀDI:
f) CS/LD↓. Clock ꢀDI:
ꢁ1ꢁꢁ1111 XXXXXXXX XXXXXXXX XXXXXXXX
ꢁ1ꢁꢁꢁꢁ1ꢁ XXXXXXXX XXXXXXXX XXXXXXXX
j) CS/LD↑
g) CS/LD↑
Update all DACs for both Code and Range.
Update DAC S for both Code and Range
k) Alternatively steps i and j could be replaced with
h) Alternatively steps f and g could be replaced with
LDAC
.
LDAC
.
2758fb
14
For more information www.linear.com/LTC2758
LTC2758
operaTion
System Offset and Reference Adjustments
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2758, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
The V
pins have an input impedance of 1.28MΩ.
OꢀADJX
These pins should be driven with a Thevenin-equivalent
impedance of 1ꢁk or less to preserve the settling perfor-
mance of the LTC2758. They should be shorted to GND
if not used.
Theoffset adjustpinsV
canbe used to null unipolar
OꢀADJX
offset or bipolar zero error. The offset change expressed
in LꢀS is the same for any output range:
TheGE
pinshaveaninputimpedanceof2.56MΩ, and
ADJX
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
⎛
⎞
5V
⎜
⎟
V
⎝
⎠
REF
Power-On Reset and Clear
A 5V control voltage applied to V
produces ∆V
=
Oꢀ
OꢀADJX
–2ꢁ48 LꢀS in any output range, assuming a 5V reference
voltage at R
When power is first applied to the LTC2758, all DACs
power-up in unipolar 5V mode (ꢀ3 ꢀ2 ꢀ1 ꢀꢁ = ꢁꢁꢁꢁ). All
internal DAC registers are reset to ꢁ and the DAC outputs
initialize to zero volts.
.
INX
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
1
∆V = –( / )V
[ꢁV to 5V, 2.5V spansꢂ
Oꢀ
128 OꢀADJX
1
∆V = –( / )V
[ꢁV to 1ꢁV, 5V, –2.5V to
7.5V spansꢂ
Oꢀ
64 OꢀADJX
1
∆V = –( / )V
[ 1ꢁV spanꢂ
Oꢀ
32 OꢀADJX
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to ꢁ and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
The gain error adjust pins GE
can be used to null
ADJX
gain error or to compensate for reference errors. The
gain error change expressed in LꢀS is the same for any
output range:
V(GEADJX
)
∆GE=
•2ꢁ48
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
V(RINX
)
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V(REFX). In voltage terms, the
V(REFX) delta is inverted and attenuated by a factor of
128.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply V dips below
DD
approximately2V;andstaysasserteduntilanyvalidUpdate
1
∆V(REFX) = –( / )GE
128
ADJX
command is executed.
The nominal input range of these pins is 5V; other volt-
ages of up to 15V may be used if needed. However, do
2758fb
15
For more information www.linear.com/LTC2758
LTC2758
operaTion
2758fb
16
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LTC2758
operaTion
WRITE CODE
DAC A
WRITE CODE
DAC B
WRITE SPAN
DAC A
WRITE SPAN
DAC B
UPDATE
ALL DACs
...
SDI
READ
CODE INPUT
REGISTER DAC A
READ
CODE INPUT
REGISTER DAC B
READ
SPAN INPUT
REGISTER DAC A
READ
SPAN INPUT
REGISTER DAC B
READ
...
SRO
CODE DAC
REGISTER DAC A
2758 F03
Figure 3. Rolling Readback
2758fb
17
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LTC2758
applicaTions inForMaTion
Op Amp Selection
Table 4. Coefficients for the Equations of Table 5
OUTPUT RANGE
A1
1.1
2.2
2
A2
2
A3
1
A4
A5
1
Secause of the extremely high accuracy of the 18-bit
LTC2758, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
5V
1ꢁV
3
ꢁ.5
1
1.5
1.5
2.5
1
5V
2
1
1
1ꢁV
4
4
ꢁ.83
1.4
ꢁ.7
2.5V
1
1
1
–2.5V to 7.5V
1.9
3
ꢁ.5
1.5
Tables 4 and 5 contain equations for evaluating the ef-
fects of op amp parameters on the LTC2758’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
Table 6 contains a partial list of LTC precision op amps
recommended for use with the LTC2758. The easy-to-use
designequationssimplifytheselectionofopampstomeet
the system’s specified error budget. ꢀelect the amplifier
from Table 6 and insert the specified op amp parameters
in Table 5. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part.Arithmeticsummationgivesan(unlikely)worst-case
effect. A root-sum-square (RMꢀ) summation produces a
more realistic estimate.
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inꢀerting Amp.
UNIPOLAR
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
BIPOLAR GAIN
ERROR (LSB)
OP AMP
INL (LSB)
5V
DNL (LSB)
5V
OFFSET (LSB)
5V
REF
5V
REF
5V
REF
5V
REF
V
(mV)
(nA)
V
•12.1•
V
•3.1•
A3•V
•52.4•
A3•V
•78.6•
V
•52.4•
V
I
•52.4•
(V
(V
(V
(V
(V
(V
)
)
)
)
)
)
)
)
OS1
OS1
OS1
OS1
OS1
OS1
OS1
REF
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
I
I
B1
•0.0012•
I
•0.00032•
I
•0.524•
I
•0.524•
I
•0.0072•
•0.0072•
(V
(V
B1
B1
B1
B1
B1
B1
)
(V
(V
(V
(V
REF
)
)
)
66
VOL1
6
VOL1
524
VOL1
524
VOL1
A
A
(V/mV)
(mV)
A1•
A2•
0
0
0
0
0
A5•
A5•
VOL1
)
)
(A
0
(A
)
)
(A
(A
5V
REF
5V
REF
5V
REF
V
0
A4•V
•52.4•
V
•104.8•
V
•104.8•
•1.048•
OS2
OS2
OS2
OS2
(V
)
(V
(V
)
)
5V
REF
5V
REF
5V
I
B2
(nA)
0
0
0
0
A4•I •0.524•
I
B2
•1.048•
I
B2
B2
(V
)
)
)
(V
(V
REF
262
VOL2
524
(A
524
(A
(V/mV)
A4•
VOL2
)
(A
)
)
VOL2
VOL2
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2758 with Releꢀant Specifications
AMPLIFIER SPECIFICATIONS
VOLTAGE CURRENT
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
t
POWER
SETTLING
V
I
A
VOL
NOISE
NOISE
with LTC2758 DISSIPATION
OS
B
AMPLIFIER
LTC115ꢁ
LT1ꢁꢁ1
µV
1ꢁ
25
25
5ꢁ
75
nA
ꢁ.ꢁ5
2
V/mV
56ꢁꢁ
8ꢁꢁ
nV/√Hz
pA/√Hz
µs
1ꢁms
12ꢁ
12ꢁ
12ꢁ
2.1
mW
24
9ꢁ
1ꢁ
14
14
5
ꢁ.ꢁꢁ18
ꢁ.12
3
2.5
ꢁ.8
1
ꢁ.25
ꢁ.2
ꢁ.2
22
46
LT1ꢁ12
ꢁ.1
ꢁ.35
1ꢁ
2ꢁꢁꢁ
25ꢁꢁ
5ꢁꢁꢁ
ꢁ.ꢁ2
11.4
11
LT1ꢁ97
ꢁ.ꢁꢁ8
ꢁ.6
ꢁ.7
9ꢁ
LT1468
117
2758fb
18
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LTC2758
applicaTions inForMaTion
Op amp offset contributes mostly to DAC output offset
and gain error, and has minimal effect on INL and DNL.
For example, consider the LTC2758 in unipolar 5V output
range. (Note that for this example, the LꢀS size is 19µV.)
An op amp offset of 35µV will cause 1.8LꢀS of output
offset, and 1.8LꢀS of gain error; but ꢁ.4LꢀS of INL, and
just ꢁ.1LꢀS of DNL.
and a high gain-bandwidth product (3ꢁMHz typ). The high
speed path consists of an LTC624ꢁHV, which is an 18MHz
ultralow bias current amplifier, followed by an LT136ꢁ, a
5ꢁMHz fast-slewing amplifier which provides additional
gain and the ability to swing to 1ꢁV at the output. Com-
pensation is taken from the output of the LTC624ꢁHV,
allowing the use of a much larger compensation capacitor
than if taken after the gain-of-five stage. An LTC2ꢁ54HV
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
auto-zero amplifier senses the voltage at I
and drives
OUT1
the non-inverting input of the LTC624ꢁHV to eliminate the
offset of the high speed path. The 1ꢁꢁ:1 attenuator and
input filter reduce the low frequency noise in this stage
while maintaining low DC offset.
an op amp’s data sheet to find the worst-case V and I
Oꢀ
S
over temperature. Then, plug these numbers in the V
Oꢀ
and I equations from Table 5 and calculate the tempera-
S
ture-induced effects.
Precision Voltage Reference Considerations
For applications where fast settling time is important, Ap-
plication Note 12ꢁ, 1ppm ꢀettling Time Measurement for
a Monolithic 18-Sit DAC, offers a thorough discussion of
18-bit DAC settling time and op amp selection.
Much in the same way selecting an operational amplifier
for use with the LTC2758 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2758
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
Recommendations
For DC or low-frequency applications, the LTC115ꢁ is the
simplest 18-bit accurate output amplifier. An auto-zero
amp, its exceptionally low offset (1ꢁµV max) and offset
drift (ꢁ.ꢁ1µV/°C) make nulling unnecessary. For swings
above 8V, use an LT1ꢁ1ꢁ buffer to boost the load current
capability. Thesettlingofauto-zeroampsisaspecialcase;
seeApplicationNote12ꢁ,1ppmꢀettlingTimeMeasurement
for a Monolithic 18-Sit DAC, Appendix E, for details.
There are three primary error sources to consider
when selecting a precision voltage reference for 18-bit
applications:outputvoltageinitialtolerance,outputvoltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
( ꢁ.ꢁ50),minimizesthegainerrorcausedbythereference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
TheLT1ꢁ12andLT1ꢁꢁ1aregoodintermediateoutput-amp
solutionsthatachievemoderatespeedandgoodaccuracy.
They are also excellent choices for the reference inverting
amplifier in fixed-reference applications.
Areference’soutputvoltagetemperaturecoefficientaffects
not only the full-scale error, but can also affect the circuit’s
INL and DNL performance. If a reference is chosen with
a loose output voltage temperature coefficient, then the
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coefficient can be
achieved by choosing a precision reference with a low
output voltage temperature coefficient and/or tightly con-
trolling the ambient temperature of the circuit to minimize
For high speed applications, the LTC1468 settles in 2.1µs.
Note that the 75µV max offset will degrade the INL at the
DAC output by up to ꢁ.9LꢀS. For high-speed applications
demanding higher precision, the amplifier offset can be
nulled with a digital potentiometer.
TheTypicalApplicationonthelastpageshowsacomposite
output amplifier that achieves fast settling (8µs) and very
low offset (3µV max) without offset nulling. This circuit
offers high open-loop gain (1ꢁꢁꢁV/mV min), low input
bias current (ꢁ.15nA max), fast slew rate (25V/µs min),
temperature gradients.
2758fb
19
For more information www.linear.com/LTC2758
LTC2758
applicaTions inForMaTion
Table 7. Partial List of LTC Precision References Recommended
Grounding
for Use with the LTC2758 with Releꢀant Specifications
As with any high-resolution converter, clean grounding
is important. A low-impedance analog ground plane is
necessary, as are star grounding techniques. Keep the
board layer used for star ground continuous to minimize
ground resistances; that is, use the star-ground concept
INITIAL
TEMPERATURE 0.1Hz to 10Hz
REFERENCE
TOLERANCE
DRIFT
NOISE
LT1ꢁ19A-5,
LT1ꢁ19A-1ꢁ
ꢁ.ꢁ50 max
ꢁ.ꢁ50 max
ꢁ.ꢁ750 max
5ppm/°C max
12µV
P-P
LT1236A-5,
LT1236A-1ꢁ
5ppm/°C max
1ꢁppm/°C max
3µV
P-P
without using separate star traces. The I
pins are
OUT2
LT146ꢁA-5,
LT146ꢁA-1ꢁ
2ꢁµV
12µV
P-P
of particular concern; INL will be degraded by the code-
dependent currents carried by the I and I
OUT2XF
OUT2Xꢀ
LT179ꢁA-2.5
LTC6652A-5
ꢁ.ꢁ50 max
ꢁ.ꢁ50 max
ꢁ.ꢁ250 max
1ꢁppm/°C max
5ppm/°C max
2ppm/°C max
P-P
pins if voltage drops to ground are allowed to develop.
The best strategy here is to tie the pins to the star ground
planebymultipleviaslocateddirectlyunderneaththepart.
Alternatively, the pins may be routed to the star ground
point if necessary; join the force and sense pins together
at the part and route one trace for each channel of no more
than 3ꢁ squares of 1oz copper.
2.8ppm
P-P
LTC6655A-2.5
LTC6655A-5
ꢁ.25ppm
P-P
As precision DAC applications move to 18-bit perfor-
mance, reference output voltage noise may contribute a
dominantshareofthesystem’snoisefloor.Thisinturncan
degrade system dynamic range and signal-to-noise ratio.
Care should be exercised in selecting a voltage reference
with as low an output noise voltage as practical for the
system resolution desired. Precision voltage references
like the LT1236 or LTC6655 produce low output noise in
the ꢁ.1Hz to 1ꢁHz region, well below the 18-bit LꢀS level
in 5V or 1ꢁV full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Figure 4). Note, however, that the volt-
age offset of the ground buffer amp directly contributes to
the effects on accuracy specified in Table 5 under ‘V ’.
Oꢀ1
The combined effects of the offsets can be calculated by
substituting the total offset from I
Oꢀ1
to I
for
OUT1X
OUT2Xꢀ
V
in the equations.
2758fb
20
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LTC2758
applicaTions inForMaTion
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
8
8
9
I
OUT2AS
I
OUT2AS
200Ω
200Ω
–
+
2
3
–
2
6
I
9
LT1012
6
OUT2AF
1000pF
LT1468
I
OUT2AF
1
2
+ 3
1
2
ZETEX
BAT54S
ZETEX*
BAT54S
3
3
*SCHOTTKY BARRIER DIODE
V
REF
5V
R
OFSA
INA
R
FBA
45, 46
44
47, 48
R
15pF
5, 6
I
I
–
OUT1A
2
3
+ 3
GE
ADJA
4
6
6
V
LT1468
DAC A
OUTA
LT1012
OUT2A
8, 9
43
+
3 R
–
2
COMA
V
OSADJA
150pF
REFA
1, 2
–
+
DAC B
LTC2758
2758 F05
Figure 4. Optional Circuits for Driꢀing IOUT2 from GND with a Force/Sense Amplifier
2758fb
21
For more information www.linear.com/LTC2758
LTC2758
package DescripTion
Please refer to http://www.linear.com/product/LTC2758#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
5.50 REF
9.00 BSC
7.00 BSC
48
48
SEE NOTE: 4
1
2
1
2
0.50 BSC
9.00 BSC
7.00 BSC
5.50 REF
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
1.00 REF
0.50
BSC
0.09 – 0.20
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
e 3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
COMPONENT
PIN “A1”
LX48 LQFP 0113 REV A
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
2758fb
22
For more information www.linear.com/LTC2758
LTC2758
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
ꢁ9/13 Fixed R
(Pin 3) description
8
COMA
Updated Typical Application
24
19
S
11/16 Updated amplifier part numbers
2758fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2758
Typical applicaTion
Composite Amplifier Circuit Achieꢀes Both Fast Settling and 18-Bit Precision with No Adjustments
15V
IN
OUT
LTC6655-5
LT1012
100pF
+
–
0.1µF
10µF
–15V
47, 48 5, 6 37, 38
34
31, 32
3
1, 2, 35, 36
REFA, REFB
R
R
R
R
R
R
COMA
OFSA
INA OFSB
COMB
INB
45, 46
R
FBA
V
OUTA
16
V
DD
1k
44
I
OUT1A
10k
10k
5V
26
19
LDAC
CLR
100pF
10k
10k
5V
15V
–
+
LTC2054HV
LT1360
1k
–
+
+
–
1µF
LTC6240HV
–5V
10Ω
8, 9
5pF
I
OUT2A
–15V
–5V
1µF
43
4
V
OSADJA
4.02k
GE
ADJA
42
33
22
25
24
23
1k
LTC2758
V
OSADJB
39, 40
GE
ADJB
R
V
OUTB
FBB
1k
41
M-SPAN
S2
I
I
OUT1B
5V
100pF
10k
10k
5V
15V
–
+
LTC2054HV
LT1360
1k
–
+
+
–
S1
1µF
LTC6240HV
S0
–5V
10Ω
28, 29
5pF
OUT2B
–15V
–5V
1µF
4.02k
7, 10, 15, 17,
18, 27, 30
GND
CS/LD SDI SCK SRO
1k
2758 TA02
11
12
13
14
SPI BUS
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTC2757
LTC1592
LTC2752
LTC2754-12
LTC27ꢁ4-12
References
LTC6655
LT1236
ꢀingle Parallel 18-Sit I
ꢀoftꢀpan DAC
1LꢀS INL/DNL, ꢀoftware-ꢀelectable Ranges, 7mm × 7mm LQFP-48 Package
1LꢀS INL, DNL, ꢀoftware-ꢀelectable Ranges, 16-Lead ꢀꢀOP Package
1LꢀS INL/DNL, ꢀoftware-ꢀelectable Ranges, 7mm × 7mm LQFP-48 Package
1LꢀS INL/DNL, ꢀoftware-ꢀelectable Ranges, 7mm × 8mm QFN-52 Package
1LꢀS INL/DNL, ꢀoftware-ꢀelectable Ranges, Integrated Amplifiers
OUT
ꢀingle ꢀerial 16-/14-/12-Sit I
ꢀoftꢀpan DACs
OUT
Dual ꢀerial 16-Sit I
ꢀoftꢀpan DAC
OUT
Quad ꢀerial 16-/12-Sit I
ꢀoftꢀpan DACs
OUT
Quad ꢀerial 16-/14-/12-Sit V
ꢀoftꢀpan DACs
OUT
Low Drift Precision Suffered Reference
Precision Reference
ꢁ.ꢁ250 Max Tolerance, 2ppm/°C Max, ꢁ.25ppm ꢁ.1Hz to 1ꢁHz Noise
P-P
ꢁ.ꢁ50 Max Tolerance, 5ppm/°C Max, 3µV ꢁ.1Hz to 1ꢁHz Noise
P-P
LT146ꢁ
Micropower Precision ꢀeries Reference
Micropower Low Dropout Reference
ꢁ.ꢁ750 Max Tolerance, 1ꢁppm/°C Max, 2ꢁµV ꢁ.1Hz to 1ꢁHz Noise
P-P
LT179ꢁ
ꢁ.ꢁ50 Max Tolerance, 1ꢁppm/°C Max, 12µV ꢁ.1Hz to 1ꢁHz Noise
P-P
LTC6652
Amplifiers
LTC115ꢁ
LT1ꢁ12
Precision Low Drift Low Noise Suffered Reference ꢁ.ꢁ50 Max Tolerance, 5ppm/°C Max, 2.1ppm ꢁ.1Hz to 1ꢁHz Noise
P-P
Zero-Drift Op Amp with Internal Capacitors
Precision Op Amp
1ꢁµV Max Offset, 16V High Voltage Operation, 1.8µV Noise
P-P
25µV Max Offset, 1ꢁꢁpA Max Input Current, ꢁ.5µV Noise, 38ꢁµA ꢀupply Current
P-P
LT1ꢁꢁ1
Precision Op Amp
25µV Max Offset, ꢁ.3µV Noise, High Output Drive
P-P
LT1468
ꢀingle 16-Sit Accurate Op Amp
9ꢁꢁns ꢀettling, 9ꢁMHz GSW, 22V/μs ꢀlew Rate, 75µV Max Offset
2758fb
LT 1116 REV B • PRINTED IN USA
LinearTechnology Corporation
163ꢁ McCarthy Slvd., Milpitas, CA 95ꢁ35-7417
24
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(4ꢁ8)432-19ꢁꢁ FAX: (4ꢁ8) 434-ꢁ5ꢁ7 www.linear.com/LTC2758
LINEAR TECHNOLOGY CORPORATION 2011
相关型号：
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