LTC3569EFE-TRPBF_技术文档

LTC3569

Triple Buck Regulator With

1.2A and Two 600mA Outputs and

Individual Programmable References

DESCRIPTION

FEATURES

The LTC^®3569 contains three monolithic, synchronous

step-downDC/DCconverters.Intendedformediumpower

applications, it operates over a 2.5V to 5.5V input voltage

range. The operating frequency is adjustable from 1MHz

to 3MHz, allowing the use of tiny, low cost capacitors and

inductors. The three output voltages are independently

programmable by toggling the EN pins up to 15 times,

loweringthe800mVFBreferencesby25mVpercycle. The

ﬁrst buck regulator sources load currents up to 1200mA.

The other two buck regulators each provide 600mA.

n

Three Independent Current Mode Buck DC/DC

Regulators (1.2A and 2x 600mA)

n

Single Pin Programmable V Servo Voltages from

FB

800mV Down to 425mV (in 25mV Steps)

Pull V High to Make Each 600mA Buck a Slave for

FB

Higher Current Operation

Pulse Skip or Burst Mode^®Operation

Programmable Switching Frequency

(1MHz to 3MHz) or Fixed 2.25MHz

Synchronizable (1.2MHz to 3MHz)

n

V Range 2.5V to 5.5V

IN

The two 600mA buck regulators can also be conﬁgured

to operate as slave power stages, running in parallel with

another internal buck regulator to supply higher load

currents. When operating as parallel, slave output stages,

discrete external components are shared and available

output currents sum together.

All Regulators Internally Compensated

PGOOD Output Flag

Quiescent Current <100μA (All Regulators in Burst

Mode Operation)

n

Zero Shutdown Current

Overtemperature and Short-Circuit Protection

Tiny 3mm × 3mm 20-Lead QFN and Thermally

Enhanced TSSOP FE-16 Packages

L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131, 7170195.

APPLICATIONS

n

Portable Applications with Multiple Supply Rails

n

General Purpose Step-Down DC/DC

n

Dynamic Voltage Scaling Applications

TYPICAL APPLICATION

V

Efﬁciency vs Load Current

IN

2.2μH

OUT1 = 2.5V

1200mA

100

SV

IN

PV

IN

SW1

22μF

V

= 3V

IN

20pF

510k

240k

10μF

4.7μF

90

80

70

60

50

40

30

20

10

0

EN1

EN2

EN3

FB1

V

= 5V

IN

LTC3569

2.5μH

OUT2 = 1.8V

600mA

SW2

FB2

MODE

300k

240k

R

T

PGOOD

BURST

PULSE SKIP

OUT1 = 2.5V

OUT3 = 1.2V

600mA

SW3

FB3

150k

300k

0.01

0.1

1

10

(mA)

100 1000 10000

I

LOAD

3569 TA01b

SGND PGND

3569 TA01a

3569f

1

LTC3569

(Notes 1, 6)

ABSOLUTE MAXIMUM RATINGS

SV Voltage.......................... –0.3V to 6V (7V Transient)

I

, I

(DC)........................................................1.3A

IN

SW2 SW3

PV Voltage.........................S – 0.3V to S + 0.3V

Operating Temperature Range.................. –40°C to 85°C

Storage Temperature Range................... –65°C to 125°C

Maximum Junction Temperature (Note 6) ............ 125°C

Peak Reﬂow Temperature ..................................... 260°C

INX

VIN

ENx, MODE, PGOOD, SWx, FBx ......–0.3V to S + 0.3V

VIN

R Voltage.................................................... –0.3V to 6V

T

SW1

I

(DC).................................................................2.5A

PIN CONFIGURATION

TOP VIEW

FB3

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FB1

FB2

SV

20 19 18 17 16

IN

SW3

PGND3

EN1

15

14

13

12

11

SW2

1

2

3

4

5

SGND

R

T

PV

IN2

EN3

EN2

EN1

SW3

MODE

17

21

8

PGOOD

EN2

MODE

PV

IN2

EN3

R

T

SW2

SW1

6

7

9 10

PV

IN1

FE PACKAGE

16-LEAD PLASTIC TSSOP

UD PACKAGE

20-LEAD (3mm × 3mm) PLASTIC QFN

T

= 125°C, θ = 38°C/W

JA

JMAX

T

= 125°C, θ = 68°C/W

JA

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3569EUD#PBF

LTC3569IUD#PBF

LTC3569EFE#PBF

LTC3569IFE#PBF

TAPE AND REEL

PART MARKING

LDQF

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3569EUD#TRPBF

LTC3569IUD#TRPBF

LTC3569EFE#TRPBF

LTC3569IFE#TRPBF

–40°C to 85°C

20-Lead (3mm × 3mm) Plastic QFN

16-Lead Plastic TSSOP

LDQF

3569FE

16-Lead Plastic TSSOP

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3569f

2

LTC3569

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 3.6V unless otherwise noted (Notes 2, 7).

SYMBOL

SV

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Input Supply Voltage

2.5

5.5

V

IN

I

Input Current Pulse Skip Mode

Input Current Burst Mode Operation

EN1 = S , EN2, EN3 = 0, I , = 0A,

OUT1

230

47

365

82

μA

VIN

FB1 = 0.9V (Note 3)

I

Additional Input Current per Buck,

Pulse Skip

QX

(Note 3) V = 0.9V

140

22

225

36

μA

FB

Burst Mode Operation

I

Quiescent Current at SGND Pin in Shutdown

Mode

EN1, EN2, EN3 = 0V

0.1

1

QSHDN

PK1

V

= V

= 0V

SW3

SW1

SW2

I

Peak Inductor Current SW1

Peak Inductor Current SW2, SW3

Maximum Feedback Voltage

Feedback Reference Step Size

Minimum Feedback Voltage

Feedback Programming Range

Feedback Pin Input Current

Switch Pin Leakage Current

1.8

2.0

1.0

2.5

1.3

A

, I

0.780

0.784

PK2 PK3

l

V

0.8

0.816

V

FBX(MAX)

FBX(STEP)

FBX(MIN)

PROGFBX

FBX

Each Toggle on ENx

ENx Toggle 15 Times

25

mV

V

0.405

0.425

0.44

0.8

0.2

1

V

I

V

FB

= 0.8V

μA

V

SWX

V

FBX

= 0V or SV , V

= SV ,

LKSWX

IN ENX IN

= 0.9V

D

R

Maximum Duty Cycle

FBx = 0V

100

%

mΩ

kΩ

X

R

DSON

R

DSON

R

DSON

R

DSON

of PSW for SW1

I

= 100mA (Note 5)

= –100mA (Note 5)

195

180

265

250

2.3

P1

N1

SW1

of NSW for SW1

, R

of PSW for SW2, SW3

of NSW for SW2, SW3

, I

= 100mA (Note 5)

P2 P3

SW2 SW3

, R

, I

= –100mA (Note 5)

N2 N3

SW2 SW3

RSWx_PD

SWx Pull-Down in Shutdown

ENx = 0V, V

(FBx < SV

= 1.2V,

SWX

IN

)

Reference Voltage Line Regulation

Output Voltage Load Regulation

Soft Start Reference Ramp Rate

Enable Turn-On Delay

S

= 2.5V to 5.5V

0.04

0.5

0.2

%/V

%

ΔV

VIN

LINEREG

Pulse Skip Mode (Note 4)

ΔV

LOADREG

t

SS

t

EN

0.75

125

V/ms

μs

From Last ENx Rise to Begin of Soft

Start Ramp

240

t

I

Enable Turn-Off Delay

Enable Pulse Width

Enable Leakage Current

Mode Leakage Current

Input Low Voltage

From ENx Fall to Shutdown

170

330

55

μs

μA

V

OFF

0.06

PW

V

= 3.6V

0.02

ENX

MODE

ENX

= 3.6V

MODE

V

MODE, ENx

0.4

IL

Input High Voltage

1.2

V

IH

T

Pulse Width Applied to MODE Pin for

Synchronizing

100

ns

MODEPW

3569f

3

LTC3569

ELECTRICAL CHARACTERISTICS

The ^ldenotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 3.6V unless otherwise noted (Notes 2, 7).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PGOOD

Power Good Threshold

V

FBX

V

FBX

Ramping Up

Ramping Down

–8

–12

%

T

PGOOD Delay

2

μs

Ω

PGOOD

R

PGOOD Pull-Down On-Resistance

Undervoltage Lockout

Fixed Oscillator Frequency

V

< 0.4V

380

525

2.5

2.8

PGOOD

FBX

l

UVLO

V

f

= S

1.9

3.0

2.25

MHz

OSC

RT

VIN

Maximum Programmable Oscillator Frequency R = 100k

CLK(MAX)

CLK(MIN)

SYNC

T

Minimum Programmable Oscillator Frequency R = 453k

1.0

3

T

Sync Frequency

R = 100k

1.2

T

Note 6: This IC includes over-temperature protection that is intended

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

to protect the device during momentary overload conditions. Junction

temperature exceeds 125°C when over-temperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 2: Current into a pin is positive and current out of a pin is negative.

Note 7: The LTC3569E is guaranteed to meet speciﬁed performance from

0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating temperature

range are assured by design characterization and correlation with

statistical process controls. The LTC3569I is guaranteed to meet speciﬁed

performance over the full –40°C to 85°C operating temperature range.

All voltages referenced to SGND.

Note 3: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 4: Speciﬁcation is guaranteed by design and not 100% tested in

production.

Note 5: Switch on-resistance veriﬁed by correlation to wafer level

measurements.

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, unless otherwise noted.

Efﬁciency vs Load Current

OUT2 = 1.8V

Efﬁciency vs Load Current

OUT3 = 1.2V

I_SVINvs Temperature

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 3V

IN

V

= 3V

IN

BUCK1 ONLY PULSE SKIP V = 3.5V

IN

V

= 5V

IN

SLOPE ≅ 185nA/°C

V

= 5V

IN

BUCK1 ONLY Burst Mode OPERATION

V

= 3.5V

IN

BURST

PULSE SKIP

BURST

PULSE SKIP

SLOPE ≅ 132nA/°C

NO LOAD

100 150

0

–50

0

50

0.01

0.1

1

10

(mA)

100

1000

0.01

0.1

1

10

(mA)

100

1000

TEMPERATURE (°C)

I

LOAD

I

LOAD

3569 G01

3569 G02

3569 G03

3569f

4

LTC3569

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs V_SUPPLY

OUT1 = 1.8V

Efﬁciency vs V_SUPPLY

OUT2 = 1.2V

Efﬁciency vs V_SUPPLY

OUT3 = 1.5V

95

90

85

80

75

70

65

95

90

85

80

75

70

65

95

90

85

80

75

70

65

BUCK1 ONLY

BUCK2 ONLY

BUCK3 ONLY

I

= 270mA

= 220mA

= 170mA

= 120mA

I

= 210mA

= 170mA

= 110mA

= 70mA

I

= 210mA

= 170mA

= 110mA

= 70mA

LOAD

2

3

4

5

6

2

3

4

5

6

2

3

4

5

6

V

(V)

V

(V)

V

(V)

SUPPLY

3569 G04

3569 G05

3569 G06

Oscillator Frequency

vs Temperature

R_DS(ON)SW1

R_DS(ON)SW2 and SW3

vs V_SUPPLYand Temperature

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

2.40

2.30

2.20

2.10

2.00

0.35

0.30

0.25

0.20

0.15

0.10

NSW2 & 3

PSW3 & 3

NSW1

PSW1

V

= 5.5V

IN

100°C

25°C

100°C

25°C

V

= 3.5V

IN

V

= 2.5V

IN

–50°C

V

= SV

IN

RT

2

3

4

5

6

–50

0

50

100

150

2

3

4

5

6

V

(V)

TEMPERATURE (°C)

V

(V)

SUPPLY

3569 G09

3569 G07

3569 G08

I_SVIN

V_FBvs Temperature

I_SVINvs V_SUPPLYPulse Skip

vs V_SUPPLYBurst Mode Operation

120

100

80

60

40

20

0

0.3

0.2

700

600

500

400

300

200

100

0

V

SET TO MAX

REF

ALL 3

0.1

2 BUCKS ENABLED

0.0

1 BUCK ENABLED

–0.1

–0.2

–0.3

V

FB1

FB2

FB3

NO LOAD

2

3

4

5

6

–50

0

50

100

150

2

3

4

5

6

V

(V)

TEMPERATURE (°C)

V

(V)

SUPPLY

3569 G12

3569 G10

3569 G11

3569f

5

LTC3569

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Buck1 Load Regulation

Buck2 Load Regulation

0.6

0.4

0.6

0.4

BUCK1, 3 OFF

BUCK2, 3 OFF

V

= 5.5V

V

= 5.5V

IN

V

= 4.5V

IN

V

= 4.5V

0.2

PULSE SKIP

0.2

IN

PULSE SKIP

0.0

–0.2

–0.4

–0.6

V

= 2.5V

IN

–0.2

–0.4

–0.6

V

= 2.5V

V

= 3.5V

IN

= 3.5V

IN

0

0.1

0.2

0.3

0.4

0.5

0.6

0

0.2

0.4

0.6

0.8

1

1.2

I

(A)

I

(A)

LOAD

3569 G14

3569 G13

Line Regulation

Buck3 Load Regulation

0.6

0.4

0.15

0.10

BUCK1, 2 OFF

EACH BUCK TESTED INDIVIDUALLY

BUCK2 = 1.2V

BUCK1 = 1.8V

0.2

0.05

0.0

0.00

PULSE SKIP

BUCK3 = 1.5V

–0.2

–0.4

–0.6

–0.05

–0.10

–0.15

PULSE SKIP MODE

I

= 200mA

= 150mA

LOAD1

LOAD2, 3

V

= 1.5V

OUT3

0

0.1

0.2

0.3

0.4

0.5

0.6

2

3

4

5

6

I

(A)

V

(V)

SUPPLY

LOAD

3569 G15

3569 G16

FB Pin Leakage

I_QSDvs Temperature

1000

100

10

10000

1000

100

10

V

= 5.5V

V

= 5.5V

IN

SLAVE

DETECTOR = 250nA

I

1

FB2,3

I

0.1

FB1

1

0.01

0.001

0.1

0

1

2

3

4

5

6

–50

0

50

100

150

V

(V)

TEMPERATURE (°C)

FB

3569 G17

3569 G18

3569f

6

LTC3569

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Load Step Cross Talk, Pulse Skip,

V_IN= 3.6V, CH1 = V_OUT1, CH2 =

V_OUT2, CH3 = V_OUT3, CH4 = I_LOAD1

Load Step Cross Talk, Pulse Skip,

V_IN= 3.6V, CH1 = V_OUT1, CH2 =

V_OUT2, CH3 = V_OUT3, CH4 = I_LOAD2

CH1

P-P

20mV/DIV

100mV/DIV

CH1

P-P

9.6mV

310mV

CH2

100mV/DIV

CH2

246mV

P-P

16.8mV

20mV/DIV

P-P

CH3

20mV/DIV

12mV

8mV

P-P

CH4

1.2A

CH4

600mA

500mA/DIV

3569 G19

3569 G20

20μs/DIV

Load Step Cross Talk, Pulse Skip,

V_IN= 3.6V, CH1 = V_OUT1, CH2 =

V_OUT2, CH3 = V_OUT3, CH4 = I_LOAD3

I_SWLeakage vs V_SUPPLYBuck 1

10000

1000

100

10

V

= 3.6V

= 0.9V

IN

FB

CH1

20mV/DIV

11.6mV

P-P

BUCK2, BUCK3 OFF

CH2

11.2mV

P-P

85°C

CH3

P-P

100mV/DIV

500mA/DIV

266mV

1

25°C

CH4

600mA

0.1

–50°C

3569 G21

0.01

0.001

20μs/DIV

0

1

2

3

3.6

V

SW

(V)

3569 G22

Soft-Start Into Heavy Load, PS, V_IN

=

Soft-Start Into Light Load, PS, V_IN=

3.6V, CH1 = V_OUT1, CH2 = V_OUT2, CH3

= V_OUT3, CH4 = I_IN, R3 = PGOOD

3.6V, CH1 = V_OUT1, CH2 = V_OUT2, CH3

= V_OUT3, CH4 = I_IN, R2 = PGOOD

CH1 500mV/DIV

CH3 500mV/DIV

CH2 500mV/DIV

CH3 500mV/DIV

CH2 500mV/DIV

R2

2V/DIV

R3

2V/DIV

CH4

500mA/DIV

CH4

50mA/DIV

3569 G23

3569 G24

400μs/DIV

3569f

7

LTC3569

PIN FUNCTIONS ^(QFN/TSSOP)

SW2(Pin1/Pin10):Buck2Switch.ConnecttotheInductor

SV (Pin 9/Pin 2): Main Supply Pin. Decouple to SGND

IN

for Buck 2. This pin swings from PV to PGND2.

with a low ESR 1μF capacitor.

IN2

PV (Pin2/Pin11):MainSupplyPinforBuck2.Decouple

SGND (Pin 10/Pin 3): Main Ground Pin. Decouple to

IN2

to PGND2 with a low ESR 4.7μF capacitor.

SV .

IN

PGOOD (Pin 3/Pin 12): The Power Good Pin. This open-

drain output is released when an enabled output has risen

to within 8% of the regulation voltage. When multiple

outputs are enabled, PGOOD is the AND of each internal

PGOOD.

EN3 (Pin 11/Pin 4): Enable Pin for Buck 3. Toggle up to

15timestoprogramreferencefeedbacklevelfrom800mV

down to 425mV.

EN2 (Pin 12/Pin 5): Enable Pin for Buck 2. Toggle up to 15

times to program reference feedback level from 800mV

down to 425mV.

MODE (Pin 4/Pin 13): Combination Mode Selection and

Oscillator Synchronization Pin. This pin controls the

EN1 (Pin 13/Pin 6): Enable Pin for Buck 1. Toggle up to 15

times to program reference feedback level from 800mV

down to 425mV.

operating mode of the device. When tied to SV , Burst

IN

Mode operation is selected. When tied to SGND, pulse-

skipping mode is selected. The internal clock frequency

synchronizes to an external oscillator applied to this pin.

When synchronizing to an external clock, drive this pin

with a logic-level signal with high and low pulse widths of

at least 100ns. When synchronizing to an external clock,

pulse skip mode is automatically selected.

PGND3 (Pin 14/NA): Main Power Ground Pin for Buck 3.

Connect to the (–) terminal of C

IN3

, and (–) terminal of

OUT3

C

.

SW3(Pin15/Pin7):Buck3Switch.ConnecttotheInductor

for Buck 3. This pin swings from PV to PGND3.

IN3

R (Pin 5/Pin 14): Timing Resistor Pin. The free-running

T

PV (Pin 16/NA): Main Supply Pin for Buck 3. Decouple

IN3

oscillator frequency is programmed by connecting a re-

to PGND3 with a low ESR 4.7μF capacitor.

sistor from this pin to ground. Tie to SV to get a ﬁxed

IN

PV (Pin17/Pin8):MainSupplyPinforBuck1.Decouple

IN1

2.25MHz operating frequency.

to PGND1 with a low ESR 4.7μF capacitor.

FB2 (Pin 6/Pin 15): Receives the feedback voltage from

the external resistive divider across the output of Buck 2.

Nominal voltage for this pin is programmed with the EN2

SW1(Pin18/Pin9):Buck1Switch.ConnecttotheInductor

for Buck 1. This pin swings from PV to PGND1.

IN1

pin from 800mV down to 425mV. When pulled to SV ,

IN

PGND1 (Pin 19/NA): Main Power Ground Pin for Buck 1.

Buck 2 is put into slave mode, following Buck 1.

Connect to the (–) terminal of C

IN1

, and (–) terminal of

OUT1

C

.

FB1 (Pin 7/Pin 16): Receives the feedback voltage from

the external resistive divider across the output of Buck 1.

Nominal voltage for this pin is programmed with the EN1

pin from 800mV down to 425mV.

PGND2 (Pin 20/NA): Main Power Ground Pin for Buck 2.

Connect to the (–) terminal of C , and (–) terminal of

OUT2

C

IN2

.

FB3 (Pin 8/Pin 1): Receives the feedback voltage from

the external resistive divider across the output of Buck 3.

Nominal voltage for this pin is programmed with the EN3

Exposed Pad (Pin 21/Pin 17): Exposed paddle must be

connected to PCB ground for rated thermal performance

and electrical connection of the TSSOP package.

pin from 800mV down to 425mV. When pulled to SV ,

IN

Buck 3 is put into slave mode, following Buck 2.

3569f

8

LTC3569

BLOCK DIAGRAM

SV

IN

PV

IN1

EN1

ON1

P-CHANNEL

N-CHANNEL

PG1

REF1

+

–

SW1

DAC1

EA1

EA2

EA3

BUCK 1.2A

FB1

NG1

PGND1

OFF

PGOOD1

PON1

NOFF1

PV

IN2

EN2

FB2

ON2

P-CHANNEL

N-CHANNEL

PG2

REF2

+

–

SW2

DAC2

BUCK 0.6A

NG2

OFF

PGND2

BG

PGOOD2

PON2

NOFF2

PV

IN3

EN3

ON3

P-CHANNEL

N-CHANNEL

PG3

REF3

+

–

DAC3

SW3

BUCK 0.6A

OFF

FB3

NG3

CLK

RPGOOD

PGND3

ISLOPE1

OSC ISLOPE2

ISLOPE3

MODE/SYNC

PGOOD3

PGOOD

800mV

PGOOD1

PGOOD2

PGOOD3

PGOODB

R

T

R

GND

T

3569BD

Figure 1. Detailed Block Diagram

3569f

9

LTC3569

OPERATION

Introduction

Each of the buck regulators supports 100% duty cycle

operation (low dropout mode) when their input voltage

drops very close to their output voltage. The switching

regulators also include soft-start to limit inrush current

when powering on, and short circuit current protection.

The LTC3569 contains three constant-frequency, current-

mode buck DC/DC regulators. Both the P-channel and

synchronous rectiﬁer (N-channel) switches are internal

to each buck. The operating frequency is determined by

the value of the R resistor, or is ﬁxed to 2.25MHz by pull-

T

Main Control Loop

ing the R pin to SV , or is synchronized to an external

T

IN

During normal operation, the top power switch (P-chan-

nel MOSFET) is turned on at the beginning of a clock

cycle. The P-channel current ramps up as the inductor

charges. The peak inductor current is controlled by the

oscillator tied to the MODE pin. Users may select pulse

skip or Burst Mode operation to trade-off output ripple for

efﬁciency. Independent programmable reference levels

allow the LTC3569 to suit a variety of applications.

internally compensated error ampliﬁer output, I . The

TH

The LTC3569 offers different power levels, a single 1.2A

buck as well as two 600mA bucks. These three bucks

may be conﬁgured in different parallel conﬁgurations, for

versatile high-current operation. The power stage of buck

2 can be conﬁgured as a slave to buck 1, by pulling FB2

current comparator (PCOMP) turns off the P-channel and

turns on the N-channel synchronous rectiﬁer when the

inductor current reaches the I level minus the offset of

TH

the slope compensation ramp. The energy stored in the

inductor continues to ﬂow through the bottom switch

(N-channel) and into the load until either the inductor

current approaches zero, or the next clock cycle begins.

If the inductor current approaches zero the N compara-

to SV . The power stage of buck 3, can be conﬁgured to

IN

be a slave to buck 2, by pulling the FB3 pin to SV . To

IN

enable the slave power stage, pull the respective EN pin

high. However if the master is disabled, the slave power

stage is Hi-Z.

BURST

CLAMP

MODE

ON

SLOPE

+

–

+

–

V

REF

P COMP

I

LIM

SOFT

START

P

VIN

SLAVE

SD

CLK

I

LIM

P-CHANNEL

I

S

Q

NOR

TH

SWITCHING

LOGIC,

BLANKING,

EEAA

SW

P-LATCH

V

FB

NAND

GATE

R

ANTI SHOOT-THRU

S

VIN

SLAVE

N-CHANNEL

P

ON

FROM MASTER

SLEEP

N

OFF

P

GND

PGOOD

ON

SLAVE

V

REF

NOR

N

COMP

–

+

3569 F02

Figure 2. Buck Block Diagram

3569f

10

LTC3569

OPERATION

tor (NCOMP) signals to turn-off the N-channel switch, so

that is does not discharge the output capacitor. When a

rising clock edge occurs, the P-channel switch turns on

repeating the cycle.

Pulseskipmodeisintendedforloweroutputvoltageripple

at light load currents. Here, the peak P-channel current is

compared with the value determined by the error ampliﬁer

output.Then,theP-channelisturnedoffandtheN-channel

switch is turned on until either the next cycle begins or the

N-channel comparator (NCOMP) turns off the N-channel

switch. If the NCOMP trips, the SW node goes Hi-Z and

the buck operates discontinuously. In pulse skip mode

the LTC3569 continues to switch at a constant frequency

down to very low currents; where it eventually begins

skipping pulses. Because the LTC3569 remains active at

lighter load currents in pulse skip mode, the efﬁciency

performance is traded off against output voltage ripple

and electromagnetic interference (EMI).

Thepeakinductorcurrentiscontrolledbytheerrorampliﬁer

(EA)andisinﬂuencedbytheslopecompensation.Theerror

ampliﬁer compares the FB pin voltage to the programmed

internal reference (REF). When the load current increases,

the FB voltage decreases. When the FB voltage falls below

the reference voltage, the error ampliﬁer output rises

to increase the peak inductor current until the average

inductor current matches the new load current. With the

inductor current equal to the load current, the duty cycle

will stabilize to a value equal to V /V .

OUT IN

Dropout Operation

Low Current Operation

When the input supply voltage decreases towards the out-

putvoltagethedutycycleautomaticallyincreasesto100%;

which is the dropout condition. In dropout, the P-channel

switch is turned on continuously with the output voltage

being equal to the input voltage minus the voltage drop

across the internal P-channel switch and the inductor.

At light loads, the FB voltage may rise above the refer-

ence voltage. If this occurs the error ampliﬁer signals

the control loop to go to sleep, and the P-channel turns

off immediately. The inductor current then discharges

through the N-channel switch until the inductor current

approaches zero; whereupon the SW goes Hi-Z, and the

output capacitor supplies power to the load. When the

load discharges the output capacitor the feedback voltage

falls and the error amp wakes up the buck, restarting the

main control loop as if a clock cycle has just begun. This

sleep cycle helps minimize the switching losses which are

dominatedbythegatechargelossesofthepowerdevices.

Twooperatingmodesareavailabletocontroltheoperation

of the LTC3569 at low currents, Burst Mode operation and

pulse skip mode.

Low Supply Operation

TheLTC3569incorporatesanundervoltagelockoutcircuit

which shuts down the part when the input voltage drops

below 2.5V to prevent unstable operation. The UVLO

function does not reset the reference voltage DAC. (See

Programming the Reference.)

Slave Power Stage

WhentheFBpinofoneofthetwo600mAregulatorsistied

Select Burst Mode operation to optimize efﬁciency at low

output currents. In Burst Mode operation the inductor cur-

rent reaches a ﬁxed current before the P-channel switch

compares inductor current against the value determined

to SV that regulator’s control circuits are disabled and

IN

the regulator’s switch pin is conﬁgured to follow a master

regulator; either the ﬁrst 600mA regulator (regulator 2) or

the 1.2A regulator (regulator 1). In this way, two regulator

powerstagesaregangedtogether(e.g.switchpinsshorted

together to a single inductor) to support higher current

levels. This permits three permutations of power levels:

three independent regulators at 1.2A, 600mA and 600mA;

by I . This burst clamp causes the output voltage to rise

TH

abovetheregulationvoltageandforcesalongersleepcycle.

Thisgreatlyreducesswitchinglossesandaveragequiescent

current at light loads, at the cost of higher ripple voltage.

3569f

11

LTC3569

OPERATION

PGOOD Pin

twoindependentregulatorsat1.2Aeach,whereregulator3

is placed in slave mode to regulator 2 and regulator 1 op-

erates independently; or one 1.8A regulator and a second

600mAregulator,whereregulator2isplacedinslavemode

to regulator 1, and regulator 3 is independent.

ThePGOODpinisanopen-drainoutputthatindicateswhen

all of the enabled regulator’s output voltages have risen to

within 92% of their programmed levels. The three bucks

each have separate PGOOD comparators with hysteresis.

The PGOOD ﬂag drops if one of the enabled regulator’s

output voltages drops below 88% of the programmed

level. Output voltage transient drops of duration less than

2μs are blanked and not reported at the PGOOD pin. The

PGOOD pin open-drain driver is disabled if PGOOD is

Whenregulator2isoperatingasaslave, pullpinsEN2and

FB2 up to SV to enable the slave power stage. Likewise

IN

when regulator 3 is operated as a slave, pull pins EN3 and

FB3 up to SV to enable the slave power stage. If the EN

IN

pin of the slave device is pulled low, then the slave power

pulled up to a voltage above SV .

stage is disabled and that SW pin is Hi-Z.

IN

Programming the Reference

Shutdown And Soft-Start

The full-scale reference voltage for each regulator is 0.8V.

The reference can be programmed in –25mV steps by

toggling the respective EN pin up to 15 times for a range

from800mVdownto425mV.ThisisillustratedinFigure3.

The EN pins require a minimum pulse width of 60ns, but

no more than 55μs, as the toggle counter times out after

ThemaincontrolloopisshutdownafterpullingtheENxpin

to ground and waiting for the t delay period to expire.

OFF

When in shutdown, but not in slave mode, a 2k resistor

to PGND discharges the output capacitor. When all three

regulators are turned off the LTC3569 enters low power

shutdown where all functions are disabled, and quiescent

current drops to below 1μA.

the EN pin remains high for around 125μs (t ). After

EN

the t timeout, the counter state is latched and sent on

EN

A soft-start is enabled when any buck is initially turned

on, or following a thermal shutdown. Soft-start ramps the

programmedinternalreferenceatarateofabout0.75V/ms.

The output voltage follows the internal reference voltage

ramp throughout the soft-start period. While in soft-start,

the LTC3569 is forced into pulse skip mode until the

PGOOD ﬂag indicates that the output voltage is nearing

the programmed regulation voltage. Once the PGOOD ﬂag

has tripped, if the MODE pin is high the regulator then

operates in Burst Mode, otherwise the LTC3569 continues

to operate in pulse skip mode.

to the reference voltage DAC, and the counter is reset to

full-scale. If the EN pin begins to toggle again, the counter

decrements on each falling edge. If the EN pin is toggled

morethan15times,thecounterremainsﬁxedatthelowest

DAC reference level. To reprogram the DAC to full-scale,

hold the EN pin low for 170μs (t ), turning off the buck,

OFF

and then pull EN high once. The buck then initiates a soft-

start as V ramps up to the full-scale value.

REF

If the DAC is reprogrammed without forcing a shutdown,

the soft start ramp is not engaged and the reference

steps to the new value. Avoid using the full-scale 0.8V

reference in programmable output voltage applications

if the application cannot tolerate the transition through

shutdownandsoft-startwhenswitchingbetweendifferent

reference levels.

Thermal Protection

If the die junction temperature exceeds 150°C, a thermal

shutdown circuit disables all functions in the LTC3569,

and the SW nodes will be pulled low with 2k pull-downs.

After the die temperature drops below 125°C the LTC3569

restartswithoutchangingtheprogrammedreferencevolt-

age DAC; but a soft-start is initiated upon exiting thermal

shutdown.

3569f

12

LTC3569

OPERATION

t

170μs (TYP)

OFF

t

EN

60ns < WIDTH < 55μs

EN

t

= 125μs (TYP)

EN

COUNTER INCREMENTS ON COUNTER RESETS TO FULL-SCALE IF EN COUNTER RESETS TO FULL-SCALE IF EN

FALLING EDGES OF EN

STAYS HIGH FOR MORE THAN 125μs

STAYS LOW FOR MORE THAN 170μs

V

REF

15

14

15 15

15

14

COUNTER

(15:0)

13

12

11

10

9

DAC LOADS COUNTER VALUE IF

EN STAYS HIGH FOR MORE THAN 125μs

13

15

DAC

(15:0)

9

COUNT15 = 800mV

COUNT13 = 750mV

COUNT9

= 650mV

SOFT-START

0mV

V

REF

SOFT-START

SHUTDOWN

BUCK ON

BUCK OFF

3569 TD

Figure 3. V_REFand ENx Timing Diagram

3569f

13

LTC3569

APPLICATIONS INFORMATION

Operating Frequency

Minimum On-Time And Duty-Cycle

Selection of the operating frequency is a tradeoff between

efﬁciency and component size. High frequency operation

allowsforsmallerinductorandcapacitorvalues.Operation

at lower frequencies improves the efﬁciency by reducing

internal gate charge losses but requires larger inductance

values and/or capacitance to maintain low output ripple

voltage.

The maximum usable operating frequency is limited by

the minimum on-time and the required duty cycle. In buck

regulators, the duty cycle (DC) is the ratio of output to

input voltage: DC = V /V = t /(t + t ). At low duty

OUT IN ON OFF ON

cycles, the SW node is high for a small fraction of the total

clock period. As this time period approaches the speed

of the gate drive circuits and the comparators internal to

the LTC3569, the dynamic loop response suffers. To avoid

minimum on-time issues it is recommended to adjust the

operating frequency down so as to keep the minimum

duty cycle pulse width above 80ns. Thus, the maximum

operating frequency should be selected such that the duty

cycle does not demand SW pulse widths below the mini-

Theoperatingfrequency,f ,oftheLTC3569isdetermined

CLK

by an external resistor that is connected between the R

T

pin and ground. The value of the resistor sets the ramp

current that charges and discharges an internal timing

capacitor within the oscillator. The relationship between

oscillator frequency and R is calculated by the following

T

mum on-time. The maximum clock frequency, f

,

CLKMAX

equation:

is selected from either the internal ﬁxed frequency clock,

11

–1.027

R = (5.1855e )•(f

)

or a timing resistor at the R pin, or synchronizing clock

T

CLK

T

applied to the MODE pin. The minimum on-time require-

Or may be selected following the graph in Figure 4.

ment is met by adhering to the following formula:

4.1

f

= (V /V

)/t

V

A

= 3.6V

IN

CLKMAX

OUT IN(MAX) MIN-ON

T

= 25°C

3.6

3.1

2.6

2.1

1.6

1.1

0.6

0.1

For example, if V

is 0.8V and V ranges up to 5.5V,

IN

OUT

the maximum clock frequency is limited to no more than

1.8MHz.

Mode Selection And Frequency Synchronization

TheMODEpinisamulti-purposepinwhichprovidesmode

selection and frequency synchronization. Connecting this

pin to SV enables Burst Mode operation, which provides

IN

0

0.1

0.2

0.3

0.4

0.5

0.6

the best low current efﬁciency at the cost of a higher out-

put voltage ripple. When this pin is connected to ground,

pulse skipping operation is selected which provides the

lowest output voltage and current ripple at the cost of low

current efﬁciency.

R

(MΩ)

T

3569 F04

Figure 4. f_CLKvs R_T

The minimum frequency is limited by leakage and noise

coupling due to the large resistance of R .

T

Synchronize the LTC3569 to an external clock signal by

tying a clock source to the MODE pin. Select the R pin

If the R pin is tied to SV the oscillation frequency is

T

IN

resistance so that the internal oscillator frequency is set

to 20% lower than the applied external clock frequency to

ensure adequate slope compensation, since slope com-

pensation is derived from the internal oscillator. During

synchronization, the mode is set to pulse skipping.

ﬁxed at 2.25MHz.

Keepexcesscapacitanceandnoise(e.g.fromtheSWpins)

away from the R pin. It is recommended to remove the

T

GND plane beneath the R pin trace, and to route the R

T

pin PCB trace away from the SW pins.

3569f

14

LTC3569

APPLICATIONS INFORMATION

TheexternalclocksourceappliedtotheMODEpinrequires

Inductor Selection

minimum low and high pulse widths of about 100ns.

Although the inductor does not inﬂuence the operat-

ing frequency, the inductor value has a direct effect on

Setting the Output Voltages

ripple current. The inductor ripple current ΔI decreases

L

The LTC3569 develops independent internal reference

voltages for each of the feedback pins. These reference

voltages are programmed from 0.8V down to 0.425V in

–25mV increments by toggling the appropriate EN pin.

The output voltage is set by a resistive divider according

to the following formula (refer to Figure 9 for resistor

designations):

with higher inductance and increases with higher V or

IN

V

:

OUT

ΔI = V /(f •L )•(1–V /V )

L

OUT CLK

OUT IN

Accepting larger values of ΔI allows the use of low induc-

L

tances, but results in higher output voltage ripple, greater

core losses, and lower output current capability.

V

= V

(1 + R1/R2),

A reasonable starting point for setting ripple current is

OUT1

REF1

ΔI = 0.3•I

, where I

is the maximum

L

OUT(MAX)

where V

is programmed by toggling the EN1 pin.

REF1

load current. The largest ripple current ΔI occurs at the

L

V

= V

(1 + R3/R4),

OUT2

REF2

maximuminputvoltage.Toguaranteethattheripplecurrent

stays below a speciﬁed maximum, choose the inductor

value according to the following equation:

where V

is programmed by toggling the EN2 pin.

REF2

V

= V

(1 + R5/R6),

OUT3

REF3

L = V /(f •ΔI )•(1 – V /V )

OUT IN(MAX)

OUT CLK

L

where V

is programmed by toggling the EN3 pin.

REF3

The inductor value also has an effect on Burst Mode

operation. The transition to low current operation begins

when the peak inductor current falls below a level set by

the burst clamp. Lower inductor values result in higher

ripple current which causes this to occur at lower load

currents. This causes a dip in efﬁciency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values increase the burst frequency and

reduces efﬁciency.

Keeping the current small (<5μA) in these resistors

maximizes efﬁciency, but making the current too small

may allow stray capacitance to cause noise problems and

reduce the phase margin of the error amp loop.

To improve the frequency response, use a feedforward

capacitor, C , on the order of 20pF across the leading

F

feedback resistor (R1, R3, and R5). Take care to route

each FB line away from noise sources, such as the induc-

tor or the SW line. Remove the ground plane from below

the FB PCB routes to limit stray capacitance to GND on

these pins.

Choose an inductor with a DC current rating at least 1.5

times larger than the maximum load current to ensure

that the inductor core does not saturate during normal

operation. Ifanoutputshortcircuitisapossiblecondition,

select an inductor that is rated to handle the maximum

peak current speciﬁed for the regulators. To maximize

efﬁciency, choose an inductor with a low DC resistance;

2

as power loss in the inductor is due to I R losses. Where

2

I is the square of the average output current and R is the

ESR of the inductor.

3569f

15

LTC3569

APPLICATIONS INFORMATION

Input/Output Capacitor Selection

The second factor that inﬂuences the selection of the

output capacitor is the effect of output capacitor ESR

on the output voltage ripple as a result of the inductor

Use low equivalent series resistance (ESR) ceramic

capacitors at the switching regulator outputs as well as

at the input supply pins. It is recommended to use only

X5R or X7R ceramic capacitors because they retain their

capacitance over wider voltage and temperature ranges

than other ceramic types.

ripple current. The amplitude of voltage ripple, ΔV , is

OUT

determined by:

ΔV

≈ ΔI (ESR + 1/(8•f •C ))

L CLK OUT

OUT

Where ΔI is the ripple current in the inductor, and ESR

L

For good transient response and stability the input and

output capacitors should retain at least 50% of rated ca-

pacitance value over temperature and bias voltage. Check

with capacitor data sheets to ensure that bias voltage and

temperature derating is taken into account when selecting

capacitors.

is the equivalent series resistance of the output capacitor.

Using ceramic capacitors, this voltage ripple is usually

negligible.

Printed Circuit Board Layout Considerations

There are three main considerations to take into account

while designing a PCB layout for the LTC3569. The ﬁrst

consideration is regarding switching noise coupling onto

In continuous mode, the input supply current is a square

waveofdutycycleV /V .Themaximuminputcapacitor

OUT IN

the FB pin traces and the R pin trace, or causing radiated

ripple current is approximated by:

T

electromagnetic induction (EMI). The noise is mitigated

by placing the inductors and input decoupling capacitors

as close as possible to the LTC3569. Furthermore, careful

placement of a contiguous ground plane directly under

the high-frequency switching node traces of the LTC3569

mitigates EMI; since high-frequency eddy currents follow

the ground plane in loops. The larger the area of the cur-

rent return loops the larger EMI that is radiated. Placing

input decoupling capacitors close to the corresponding

1/2

C required I

≈ I

(V (V –V )) /V

IN

RMS

OUT(MAX) OUT IN OUT

IN

This formula’s maximum is approximately I =I

/2.

RMS OUT(MAX)

In an output short circuit situation, the input capacitor

ripple current is approximately:

C required I

IN

≈ I /√3

PK

RMS

Thus, the ripple current in an output short circuit is about

2.5 times larger than for nominal operation. Take care

in selecting the input capacitor so as not to exceed the

capacitormanufacturer’sspeciﬁcationforselfheatingdue

to the ripple current.

PV /PGND pins directly reduces the area (and therefore

IN

the inductance) of ground returns. Also, place a group of

vias directly under the grounded backside of the package

leading to an internal ground plane. Place the ground

plane on the second layer of the PCB to minimize parasitic

inductance.

Two factors inﬂuence the selection of the output capacitor.

The ﬁrst is load voltage droop, V

output capacitor ESR effect on ripple voltage.

, the second is the

DROOP

The second consideration is stray capacitance on the FB

Load voltage droops on a load current step, ΔI , where

OUT

pin traces and the R pin trace to GND. This is taken into

T

the output capacitor supports the output voltage for typi-

cally 2 to 3 clock cycles until the inductor current charges

up to the load step current level. A good estimate of output

capacitor value required to maintain a droop of less than

account by cutting the ground plane beneath these traces.

However, wherever the ground plane is cut, add additional

decoupling capacitors across the break to provide a path

for high-frequency ground return currents to ﬂow.

V

is given by:

DROOP

C

≈ 2.5•ΔI /(f •V

)

OUT

OUT CLK DROOP

3569f

16

LTC3569

APPLICATIONS INFORMATION

Finally,thethirdconsiderationisstrayimpedancebetween

the SW node and the inductor when operating with a slave

powerstage. Itisimportanttokeepthestrayinductanceof

the slave power device to a minimum, by keeping the trace

from slave SW to the main SW as short as possible. This

requirement is necessary to ensure that the slave power

device’sshareoftheinductorcurrentdoesnotexceedthat

of the master as well as to keep the current density in the

slave device under control. The inductor should be placed

close to the master SW pin to minimize stray impedance

and allow the master to control the inductor current.

The junction temperature, T , is given by:

J

T = t

+ T .

A

J

RISE

Where T is the ambient temperature.

A

As an example, consider the case when the LTC3569 is

in dropout at an input voltage of 2.7V with load currents

of 1000mA, 500mA and 500mA for bucks 1, 2 and 3

respectively, at an ambient temperature of 85°C. From

the Typical Performance Characteristics, the R

buck1 is 0.190ꢀ, and for buck2 and buck3 it is 0.265ꢀ.

Therefore, power dissipated by the LTC3569 is:

of

DS(ON)

2

P = I

D

R

+ I

R

+ I

R

Thermal Considerations

1

DS(ON)1

2

DS(ON)2

3 DS(ON)3

= 190mV + 66.25mW + 66.25mV

= 322.5mW

In the majority of applications, the LTC3569 does not dis-

sipate much heat due to its high efﬁciency. However, in

applicationswheretheLTC3569isrunningathighambient

temperature with low supply voltage and high duty cycles,

such as in dropout, the heat dissipated may exceed the

maximum junction temperature of the part. If the junction

temperature reaches approximately 150°C, the LTC3569

will be turned off and 2k resistive pull-downs are tied to

all the SW nodes.

At 85°C ambient the junction temperature is:

T = 322.5mW•68°C/W + 85°C = 106.9°C.

J

Thisjunctiontemperatureisbelowtheabsolutemaximum

junction temperature of 125°C.

Design Example 1: 2.5V, 1.8V and 1.2V From a

Li-Ion Battery

To prevent the LTC3569 from exceeding maximum junc-

tion temperature, the user will need to do some thermal

analysis. The goal of the thermal analysis is to determine

whetherthepowerdissipatedexceedsthemaximumjunc-

tion temperature of the part. Temperature rise is:

As a design example, consider using the LTC3569 in a

portable application with a Li-Ion battery source. The bat-

tery provides an SV from 2.9V to 4.2V. The loads require

IN

2.5V, 1.8V and 1.2V with current requirements of up to

800mA, 400mA and 400mA respectively when active. The

ﬁrst load, with the 2.5V rail has no standby requirements,

however loads 2 and 3 each require a current of 1mA in

standby. Since two of the loads require low current opera-

t

= P •θ

D JA

RISE

Where P is the power dissipated by the regulator and

D

θ

JA

is the thermal resistance from the junction of the die

to the ambient temperature.

tion, Burst Mode operation is selected. With V

at

IN(MAX)

4.2V and V

= 1.2V, the maximum clock frequency

OUT(MIN)

is 3.57MHz based on minimum on-time requirements.

To simplify the board layout, the ﬁxed 2.25MHz internal

frequency is selected.

3569f

17

LTC3569

APPLICATIONS INFORMATION

Selecting The Inductors

The output capacitor values are calculated as:

Calculating the inductor values for 30% ripple current at

C

= 2.5•800mA/(2.25MHz•125mV) = 7.1μF

= 2.5•400mA/(2.25MHz•90mV) = 4.9μF

= 2.5•400mA/(2.25MHz•60mV) = 7.4μF

OUT1

OUT2

OUT3

maximum SV :

IN

L1 = 2.5V/(2.25MHz•240mA)•(1–2.5V/4.2V)= 1.9μH

L2 = 1.8V/(2.25MHz•120mA)•(1–1.8V/4.2V)= 3.8μH

L3 = 1.2V/(2.25MHz•120mA)•(1–1.2V/4.2V)= 3.1μH

Choosing the closest standard values gives, C

OUT2

= 10μF,

OUT1

C

= 4.7μF and C

= 10μF.

OUT3

Choosing a vendor’s closest values gives L1 = 2.2μH, L2

= L3 = 3.3μH. These values result in the maximum ripple

currents of:

A 22μF input capacitor is selected since the Li-Ion battery

has sufﬁciently low output impedance.

Setting The Output Voltages

ΔI = 2.5V/(2.25MHz•2.2μH)•(1–2.5V/4.2V) = 204mA

L1

Without toggling the EN pins the LTC3569 develops a 0.8V

referencevoltageforeachofthefeedbackpins. Theoutput

voltages are set by a resistive divider as follows:

ΔI = 1.8V/(2.25MHz•3.3μH)•(1–1.8V/4.2V) = 139mA

L2

ΔI = 1.2V/(2.25MHz•3.3μH)•(1–1.2V/4.2V) = 115mA

L3

V

= 0.8•(1 + R2/R1)

OUT

Selecting The Output Capacitors

The resistors in Figure 5 are selected as the nearest 1%

standard resistor values. To improve frequency response

feedforward capacitors of 10pF and 20pF are used.

The value of the output capacitors are calculated based

on a 5% load droop for maximum load current step. The

output droop is usually about 2.5 times the linear drop

of the ﬁrst cycle and is estimated based on the following

formula:

C

= 2.5•I

/(f •V

OUT(MAX) CLK DROOP

)

OUT

V

IN

2.9V TO 4.2V

2.2μH

3.3μH

OUT1

2.5V AT 800mA

SV

PV

SW1

FB1

IN

Design Example 1: Burst Mode Operation

22μF

243k

115k

10pF

20pF

10μF

100

90

80

70

60

50

V

= 2.9V TO 4.2V

IN

EN1

EN2

EN3

LTC3569

OUT2

1.8V AT 400mA

SW2

FB2

R

T

187k

150k

MODE

4.7μF

470k

PGOOD

OUT3

1.2V AT 400mA

SW3

FB3

BUCK1 = 2.5V

BUCK2 = 1.8V

BUCK3 = 1.2V

187k

374k

10μF

SGND PGND

0.1

1

10

100

(mA)

1000

10000

I

LOAD

3569 F05b

3569 F05a

Figure 5. Triple Buck DC/DC Regulators: 800mA, 400mA, 400mA

3569f

18

LTC3569

APPLICATIONS INFORMATION

Design Example 2: Dual Bucks, 1.8V at 1.8A and 1.5V

at 600mA

Calculating the value of the output capacitors:

C

OUT1

C

OUT2

= 2.5•1800mA/(2.25MHz•90mV) = 22μF

For this example, the LTC3569 is conﬁgured to deliver two

ﬁxed voltages of 1.8V and 1.5V from a generic supply over

the full operating range, 2.5V to 5.5V. The load require-

ments range from <1mA in standby mode up to 1.8A for

the 1.8V supply and 600mA for the 1.5V supply.

= 2.5•600mA/(2.25MHz•75mV) = 8.9μF

An input capacitor of 22μF is selected to support the

maximum ripple current of 1.2A. An additional 0.1μF low

ESR capacitor is placed between SV and SGND.

IN

The resistor values shown in Figure 6 are selected as the

closest standard 1% resistors to obtain the correct output

voltages with the full-scale reference voltages of 0.8V. And

20pFfeedforwardcapacitorsareplacedacrosstheleading

feedback resistors.

The ﬁxed internal clock frequency of 2.25MHz meets the

minimum on-time requirements. Burst Mode operation

is selected for high efﬁciency at the low standby current

level. Calculating the inductor values for 30% ripple cur-

rent at max SV :

IN

L1 = 1.8V/(2.25MHz•540mA)•(1–1.8V/5.5V) = 1.0μH

L2 = 1.5V/(2.25MHz•180mA)•(1–1.5V/5.5V) = 2.2μH

V

2.5V TO 5.5V

22μF

IN

Design Example 2: 1.8A Load Step on Buck1

with Buck2 Slave, Burst Mode Operation

1μH

OUT1

1.8V AT 1.8A

PV

SW1

SW2

FB1

IN

187k

150k

20pF

22μF

CH1

SW1/2

2V/DIV

EN1

EN2

EN3

CH3

OUT1

LTC3569

200mV/DIV

V

336mV

V

FB2

P-P

R

T

IN

CH2

LOAD

1.8A

MODE

2.2μH

I

OUT3

511k

SW3

FB3

1.5V AT 600mA

1A/DIV

PGOOD

174k

200k

CH4

20pF

10μF

I

V

SV

IN

L1

IN

1.94A

3569 F06b

0.1μF

10μs/DIV

SGND PGND

3569 F06a

Figure 6. Dual Buck DC/DC Regulators: 1.8V at 1800mA, and 1.5V at 600mA

3569f

19

LTC3569

APPLICATIONS INFORMATION

Design Example 3: Dual Programmable Bucks

standby voltages: 1.8V/1.2V = 1.5. The 0.75V and 0.5V

reference levels mach this ratio. The resistors shown in

Figure 7 are selected to obtain the correct feedback ratio

fromstandard1%resistors.Calculatingtheinductorvalues

In this example consider two buck regulators operating

from a 2.5V to 5.5V unregulated supply that are required

togeneratetwoindependentlyprogrammablesuppliesthat

must step from 1.2V in standby up to 1.8V when active,

with a maximum load current of 1.2A when active and

1mA in standby. Additionally, this application anticipates

possible output short circuits, and is required to operate

without damage in such a situation.

for 30% ripple current at maximum SV :

IN

L = 1.8V/(2.25MHz•360mA)•(1–1.8V/5.5V)= 1.5μH.

The output capacitor values are selected as the nearest

standard value to obtain 5% voltage droop at maximum

load current step.

Buck 1 is selected for the ﬁrst regulator, and buck 3 is

conﬁgured as a slave power stage in parallel with buck 2

C

= 2.5•1200mA/(2.25MHz•90mV) ≈ 15μF.

OUT

Select an output capacitor with an ESR of less than 50mꢀ

to obtain an output voltage ripple of less than 30mV.

Finally select an input capacitor rated for the worst-case

short-circuit ripple current of 2 I /√3 ≈ 2.5A, when both

outputs are shorted to GND.

bypullingFB3uptoV toobtaintherequiredcurrentlevel

IN

for the second regulator. Burst Mode operation is selected

to achieve high efﬁciency during standby operation. The

internal2.25MHzclockfrequencyisselected,asitsatisﬁes

the minimum on-time requirement. Next, two reference

voltages are selected to match the ratio of the active to

PK

V

2.5V TO 5.5V

IN

Design Example 3: Soft-Start to Standby (1.2V)

1.5μH

OUT1 1200mA

1.2V STANDBY

1.8V ACTIVE

SV

PV

SW1

FB1

IN

22μF

294k

210k

20pF

15μF

500mV/DIV

EN1

EN2

EN3

DIGITAL

CONTROL

CH1

OUT1

LTC3569

V

IN

OUT2 1200mA

1.2V STANDBY

1.8V ACTIVE

SW2

SW3

FB2

MODE

CH2

2V/DIV

OUT2

294k

210k

R

T

CH3

PGOOD

CH4

511k

PGOOD

EN1 = EN2

FB3

V

3569 F07b

IN

200μs/DIV

SGND PGND

3569 F07a

Figure 7. Dual Programmable Buck DC/DC Regulators: 1200mA, 1200mA

3569f

20

LTC3569

APPLICATIONS INFORMATION

Design Example 4: Dual Programmable Bucks

tolerate a voltage droop when switching from standby to

active,the0.7Vand0.525Vreferencesareselectedtomatch

the ratio of output voltages. With this ratio, the buck does

not need to be shutdown as it would if the full scale 0.8V

referencelevelwaschosen.TheresistorsshowninFigure8

are selected to obtain the nearest feedback ratio from

standard 1% resistors. Calculating the inductor values

In this example consider two buck regulators operating

from a 2.5V to 5.5V unregulated supply that are required

togeneratetwoindependentlyprogrammablesuppliesthat

must step from 1.2V in standby up to 1.6V when active,

withamaximumloadcurrentof0.8Awhenactiveand1mA

in standby. Furthermore, when switching between active

and standby, the load voltage should not droop.

for 30% ripple current at maximum SV :

IN

L = 1.6V/(2.25MHz•240mA)•(1–1.6V/5.5V) ≈ 2.2μH.

Buck 1 is selected for the ﬁrst regulator, and buck 3 is

conﬁgured as a slave power stage in parallel with buck 2

The output capacitor values are selected as the nearest

standard value to obtain 5% voltage droop at maximum

load current step.

bypullingFB3uptoV toobtaintherequiredcurrentlevel

IN

for the second regulator. Burst Mode operation is selected

to achieve high efﬁciency during standby operation. The

internal2.25MHzclockfrequencyisselected,asitsatisﬁes

the minimum on-time requirement. Next, two reference

voltages are selected to match the ratio of the active to

standby voltages: 1.6V/1.2V = 1.3333. There are three

reference value ratios that match this ratio: 0.8V and 0.6V,

0.7V and 0.525V, and 0.6V and 0.45V. As the load cannot

C

= 2.5•800mA/(2.25MHz•90mV) ≈ 10μF.

OUT

Select an output capacitor with an ESR of less than 50mꢀ

to obtain an output voltage ripple of less than 30mV.

Finally select an input capacitor rated for the worst-case

short-circuit ripple current of 2 I /√3 ≈ 2.5A, when both

PK

outputs are shorted to GND.

Design Example 4: Dual 1A Bucks

V_OUT= 1.6V, Burst Mode Operation

V

2.5V TO 5.5V

IN

2.2μH

OUT1 800mA

1.2V STANDBY

1.6V ACTIVE

100

90

80

70

60

50

40

SV

PV

SW1

FB1

IN

22μF

210k

162k

20pF

10μF

V

= 2.5V

IN

EN1

EN2

EN3

DIGITAL

CONTROL

LTC3569

V

IN

V

= 5.5V

IN

OUT2 800mA

1.2V STANDBY

1.6V ACTIVE

SW2

SW3

FB2

MODE

210k

162k

R

T

511k

PGOOD

FB3

V

IN

BUCK 1

BUCK 2, 3

SGND PGND

3569 F08

0.1

1

10

100

(mA)

1000

10000

I

LOAD

3569 F08b

Figure 8. Dual Programmable Buck DC/DC Regulators

3569f

21

LTC3569

PACKAGE DESCRIPTION

UD Package

20-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1720 Rev A)

0.70 0.05

3.50 0.05

(4 SIDES)

1.65 0.05

2.10 0.05

PACKAGE

OUTLINE

0.20 0.05

0.40 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH

R = 0.20 TYP

OR 0.25 × 45°

CHAMFER

R = 0.115

TYP

0.75 0.05

3.00 0.10

(4 SIDES)

R = 0.05

TYP

19 20

PIN 1

TOP MARK

(NOTE 6)

0.40 0.10

1

2

1.65 0.10

(4-SIDES)

(UD20) QFN 0306 REV A

0.200 REF

0.20 0.05

0.40 BSC

0.00 – 0.05

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3569f

22

LTC3569

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 0.10

2.94

(.116)

4.50 0.10

SEE NOTE 4

6.40

(.252)

BSC

2.94

(.116)

0.45 0.05

1.05 0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BB) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3569f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC3569

TYPICAL APPLICATION

V

IN

2.2μH

OUT1

SV

PV

SW1

FB1

IN

22μF

1200mA

R1

R2

20pF

10μF

EN1

EN2

EN3

DIGITAL

CONTROL

LTC3569

OUT2

600mA

SW2

FB2

MODE

R3

R4

R

T

4.7μF

511k

PGOOD

OUT3

600mA

SW3

FB3

R5

R6

4.7μF

SGND PGND

3569 TA02

Figure 9. Triple Programmable Buck DC/DC Regulators

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ThinSOT is a trademark of Linear Technology Corporation.

3569f

LT 0109 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3569EFE-TRPBF
厂家：	Linear
描述：	Triple Buck Regulator With 1.2A and Two 600mA Outputs and Individual Programmable References 三联降压稳压器1.2A和两个600毫安输出和可编程的个人参考稳压器
文件：	总24页 (文件大小：399K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3569EFE-TRPBF [Linear]

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