LTC6417CUDC#TRPBF [Linear]
LTC6417 - 1.6GHz Low Noise High Linearity Differential Buffer/16-Bit ADC Driver with Fast Clamp; Package: QFN; Pins: 20; Temperature Range: 0°C to 70°C;
| 型号： | LTC6417CUDC#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC6417 - 1.6GHz Low Noise High Linearity Differential Buffer/16-Bit ADC Driver with Fast Clamp; Package: QFN; Pins: 20; Temperature Range: 0°C to 70°C 放大器 |
| 文件： | 总32页 (文件大小：1308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6417
1.6GHz Low Noise High Linearity
Differential Buffer/16-Bit ADC
Driver with Fast Clamp
DescripTion
FeaTures
The LTC®6417 is a differential unity gain buffer that can
drive a 50Ω load with extremely low noise and excellent
linearity. It is well suited for driving high speed 14- and
16-bit pipeline ADCs with input signals from DC to beyond
600MHz. Differentialinputimpedanceis18.5kΩ, allowing
1:4 and 1:8 transformers to be used at the input providing
additional system gain in 50Ω systems.
n
1.6GHz –3dB Small Signal Bandwidth
n
Low Distortion Driving 50Ω Load, 2.4V Out
P-P
–100dBc/–69dBc HD2/HD3 at 140MHz
–80dBc IM3 and 46dBm OIP3 at 140MHz
–100dBc/–66dBc HD2/HD3 at 380MHz
–68dBc IM3 and 39dBm OIP3 at 380MHz
1.5nV/√Hz Output Noise
n
n
n
4.3pA/√Hz Input Current Noise
With no external biasing or gain setting components and
a flow-through pinout, the LTC6417 is very easy to use. It
can be DC-coupled and has a common mode output offset
of –60mV. The LTC6417 input pins are internally biased to
provide an output common mode voltage that is set by
Programmable High Speed, Fast Recovery
Output Clamping
n
4.28V Maximum Output Swing on a 50Ω
P-P
Differential Load
DC-Coupled Signal Path
n
n
n
the voltage on the V pin for AC-coupled applications.
CM
Operates on Single 4.75V to 5.25V Supply
Power: 615mW on 5V, Can Be Reduced to 370mW,
Shutdown Mode 120mW
Supplycurrentistypically123mAandtheLTC6417operates
on supply voltages ranging from 4.75V to 5.25V. Power
consumption can be reduced to 74mA via the PWRADJ
pin. The LTC6417 also has a hardware shutdown feature
which reduces current consumption to 24mA.
n
3mm × 4mm 20-Lead QFN Package
TheLTC6417featuresfast,adjustableoutputvoltageclamp-
ing to help protect subsequent circuitry. The CLHI pin sets
the maximum swing, while a symmetric minimum swing
applicaTions
n
Differential ADC Driver
n
CCD Buffer
is set up internally. LTC6417 V pin will signal overrange
OR
n
Cable Driver
when the clamps limit output voltage.
n
50Ω Buffer
The LTC6417 is packaged in a 20-lead 3mm × 4mm QFN
package.Pinoutisoptimizedforplacementdirectlyadjacent
to Linear Technology’s high speed 14- and 16-bit ADCs.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC6417 Driving LTC2209
16-Bit ADC 32K Point FFT,
Typical applicaTion
LTC6417 Driving an LTC2209 16-Bit ADC at 140MHz IF
fIN = 140MHz, –1dBFS, PGA = 0
3.3V
5V
0
HD2 = –88dBc
HD3 = –94dBc
SFDR = 88dBc
SNR = 75.4dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
C43
E1
C45
–10
–20
E3
2.2µF
27pF
18pF
680pF
0.1µF
1,6,
11,16
51nH
75nH
–30
R36
60.4Ω
R42
300Ω
–40
T1
+
5
10Ω
10Ω
V
f
= 153.6Msps
–50
S
WBC4-14LB
2
PWRADJ
DEMO BOARD DC1685A
–60
8
9
4
3
C40
+
CLHI
+
–
19
R53
120Ω
C41
12pF
IN
100Ω
100Ω
A
A
IN
IN
12pF
–70
+
E5
51nH
16
OUT
OUT
2
50Ω
LTC2209
PGA = 0
LTC6417
–
–80
–
R12
60.4Ω
C10
12pF
R43
300Ω
•
•
V
–90
IN
OR
18
+
V
CM
6
1
–
V
CM
14
1k
SHDN
–100
–110
–120
15
GND
0.01µF
C44
27pF
C46
18pF
12
E2
51nH
E3
75nH
0.01µF
CLOCK
(153.6MHz)
3,7,10,
17, 20,21
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
6417 TA01b
6417 TA01a
2.2µF
6417f
1
LTC6417
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
+
Total Supply Voltage (V to GND).............................5.5V
Input Current (CLHI, V ).................................... 10mA
CM
20 19 18 17
+
–
+
Input Current (IN , IN )........................................ 30mA
+
+
–
1
16
15
14
V
V
V
V
Output Current (OUT , OUT )............................. 100mA
CLHI
GND
2
3
4
5
6
CM
Output Current (V ) ........................................... 10mA
OR
OR
21
GND
Operating Temperature Range
NC
13 NC
(T ) (Note 2) .......................................... –40°C to 105°C
C
PWRADJ
12 SHDN
+
+
Specified Temperature Range
V
11 V
(T ) (Note 3) .......................................... –40°C to 105°C
C
7
8
9 10
Storage Temperature Range .................. –65°C to 150°C
Junction Temperature (T
).............................. 150°C
JMAX
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
= 150°C, θ = 52°C/W, θ = 6.8°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC6417CUDC#PBF
LTC6417IUDC#PBF
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6417CUDC#TRPBF
LTC6417IUDC#TRPBF
LFVN
LFVN
0°C to 70°C
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 105°C (T )
C
*Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Dc elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input/Output Characteristics
G
Differential Gain
V
= 1.2V Differential
INDIFF
–0.15
–0.2
–0.1
0.0002
4.28
0
0
dB
dB
DIFF
l
l
TCG
Differential Gain Temperature
Coefficient
dB/°C
DIFF
V
V
V
Differential Output Voltage Swing
Output Voltage Swing Low
Output Voltage Swing High
V
, V
= 2.3V
4
3.3
V
V
SWINGDIFF
SWINGMIN
SWINGMAX
OUTDIFF INDIFF
P-P
P-P
l
l
l
+
–
–
Single-Ended Measurement of OUT , OUT
= 2.3V
0.19
0.28
0.4
V
V
V
INDIFF
+
Single-Ended Measurement of OUT , OUT
= 2.3V
2.25
2.05
2.33
V
V
V
INDIFF
6417f
2
LTC6417
Dc elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
Single-Ended Measurement of OUT , OUT
MIN
TYP
MAX
UNITS
+
–
l
I
Output Current Drive (Notes 1, 4)
Differential Input Offset Voltage
100
mA
OUT
+
–
V
OS
IN = IN = 1.25V, V = V /G
OUTDIFF DIFF
–3.2
–4
–0.1
3.2
4
mV
mV
OS
l
l
TCV
Differential Input Offset Voltage Drift
1
µV/°C
OS
V
Common Mode Offset Voltage, Input
to Output
V
– V
INCM
–120
–140
–60
–10
0
mV
mV
IOCM
OUTCM
l
l
+
–
IVR
Input Voltage Range, IN , IN
Defined by Output Voltage Swing Test
Defined by Output Voltage Swing Test
0.1
V
MIN
(Minimum) (Single-Ended)
+
–
l
IVR
Input Voltage Range IN , IN
2.4
V
MAX
(Maximum) (Single-Ended)
+
–
+
–
I
Input Bias Current, IN , IN
IN = IN = 1.25V
–13
–18
2
13
18
µA
µA
B
l
l
R
Differential Input Resistance
V
= 1.2V
12
11
18.5
25
27.5
kΩ
kΩ
INDIFF
INDIFF
C
INDIFF
Differential Input Capacitance
1
pF
+
–
R
Input Common Mode Resistance
IN = IN = 0.65V to 1.85V
5.8
5
9.25
13
15
kΩ
kΩ
INCM
l
l
+
–
CMRR
Common Mode Rejection Ratio
IN = IN = 0.65V to 1.85V,
63
60
91
dB
dB
CMRR = (V
/G /1.2V)
OUTDIFF DIFF
R
Differential Output Resistance
Input Noise Voltage Density
Input Noise Current Density
3
Ω
nV/√Hz
pA/√Hz
OUTDIFF
e
N
f = 100kHz
f = 100kHz
1.5
4.3
i
N
Output Common Mode Voltage Control
G
V
Pin Common Mode Gain
V
V
V
= 0.65V to 1.85V
0.82
0.8
0.92
1.25
15
V/V
V/V
CM
CM
CM
l
l
l
l
l
l
l
l
l
+
–
V
V
V
V
V
V
V
Default Input Common Mode Voltage
Offset Voltage, V to V
. IN , IN , V Pin Floating
1.15
1.1
1.35
1.4
V
V
INCMDEFAULT
INCM
CM
(V – V
)
– V , V = 1.25V
INCM CM
–85
–90
115
135
mV
mV
OS CM
INCM
CM
INCM
CM
Default Output Common Mode Voltage Inputs Floating, V Pin Floating
1.1
1
1.2
1.3
1.35
V
V
OUTCMDEFAULT
CM
(V – V
)
Offset Voltage, V to V
V
CM
V
CM
V
CM
– V , V = 1.25V
OUTCM CM
–50
–45
75
200
230
mV
mV
OS CM
OUTCM
CM
OUTCM
Output Common Mode Voltage Range
(Minimum)
= 0.1V
= 2.4V
0.29
2.25
1.25
2.7
0.63
0.65
V
V
OUTCMMIN
OUTCMMAX
CMDEFAULT
Output Common Mode Voltage Range
(Maximum)
2
1.85
V
V
V
Pin Default Voltage
1.15
1.1
1.35
1.4
V
V
CM
R
VCM
V
Pin Input Resistance
V
V
= 0.65V to 1.85V
= 1.25V
2
1.9
3.4
3.7
kΩ
kΩ
CM
CM
CM
C
VCM
V
V
Pin Input Capacitance
Pin Bias Current
1
1
pF
CM
CM
I
–15
–27.5
15
27.5
µA
µA
BVCM
l
6417f
3
LTC6417
Dc elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Clamping Characteristics
V
V
V
Default Output Clamp Voltage, High
) Offset Voltage, CLHI to V
2.4
2.48
20
2.55
2.6
V
V
CLHIDEFAULT
l
l
l
l
l
l
l
2.35
(CLHI – V
–60
–85
80
85
mV
mV
OS
OS
OUTCM
OUTCM
+
(CLLO – V
)
Offset Voltage, CLLO to V
V
= 2.0V, V = 1.25V, IN = 2.4V,
–100
–110
10
100
110
mV
mV
OUT
OUT
CLHI
CM
–
IN = 0.1V
+
G
G
R
Low Side Clamp Gain with Respect to
CLHI Pin
V
= 2.0V, V = 1.25V, IN = 2.4V,
–1.2
–1.25
–1
–0.8
–0.75
V/V
V/V
LOHI
CLHI
–
CM
IN = 0.1V
+
Low Side Clamp Gain with Respect to
CM Pin
V
= 2.0V, V = 1.25V, IN = 2.4V,
1.65
1.5
1.9
4.8
3
2.2
2.25
V/V
V/V
LOCM
CLHI
CLHI
–
CM
IN = 0.1V
CLHI Pin Input Resistance
V
V
= 1.5V to 2.5V
= 2.5V
3.4
3.1
5.7
6
kΩ
kΩ
CLHI
IB
CLHI Pin Bias Current
–12
–12.5
18
18.5
µA
µA
CLHI
CLHI
Power Supply
l
l
l
V
Supply Voltage Range
Supply Current
4.75
5.25
V
S
I
S
100
95
123
72
140
145
mA
mA
PSRR
Power Supply Rejection Ratio
V = 4.75V to 5.25V
S
65
63
dB
dB
SHDN Pin
IS
Shutdown Current
V
= 5V
SHDN
17
15
24
29
35
mA
mA
SHDN
l
l
l
l
V
V
V
Default Shutdown Voltage
SHDN Input Low Voltage
SHDN Input High Voltage
SHDN Input Low Current
0.1
2
V
V
V
SHDNDEFAULT
IL,SHDN
3.5
IH,SHDN
I
SHDN = 0V
SHDN = 5V
–1.6
–2
0
1.6
2
µA
µA
IL,SHDN
l
l
I
SHDN Input High Current
275
250
380
450
475
µA
µA
IH,SHDN
C
SHDN Pin Input Capacitance
SHDN Pin Input Resistance
1
pF
SHDN
R
SHDN = 2.5V to 5V
6
5
10.5
14
15
kΩ
kΩ
SHDN
l
PWRADJ Pin
V
Default PWRADJ Voltage
Supply Low Current
PWRADJ Floating
PWRADJ = 0V
PWRADJ = 0V
PWRADJ = 5V
1.5
1.65
74
1.8
V
V
PWRADJDEFAULT
1.45
1.85
IS
45
40
105
110
mA
mA
L
l
l
l
I
I
PWRADJ Input Low Current
PWRADJ Input High Current
PWRADJ Pin Input Capacitance
–145
–165
–120
240
1
–80
–75
µA
µA
IL,PWRADJ
210
200
290
300
µA
µA
IH,PWRADJ
C
pF
PWRADJ
6417f
4
LTC6417
Dc elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
PWRADJ Pin Input Resistance
PWRADJ = 2.5V to 5.0V
10.5
10
14.5
19
20
kΩ
kΩ
PWRADJ
l
V
OR
Pin
V
Maximum Voltage on V Pin
V
V
V
= 5.0V, V = 1.25V
3.25
3.2
3.35
–770
1
3.55
3.6
V
V
OR(HI)
OR
CL
CM
l
l
l
I
Default Pull-Down Current on V Pin
= 50V, V = 1.25V
–900
–1150
–650
–500
µA
µA
OR(DEFAULT)
OR(MAX)
OR
CL
CM
+
I
Maximum Pull-Down Current Both
Clamps are Active
= 2.0V, V = 1.25V, IN = 2.4V,
1.5
2
µA
µA
CL
–
CM
IN = 0.1V
ac elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Differential AC Characteristics
–3dBBW
0.1dBBW
0.5dBBW
1/f
–3dB Bandwidth
0.1dB Bandwidth
0.5dB Bandwidth
1/f Noise Corner
Slew Rate
200mV
200mV
200mV
Differential
Differential
Differential
1.6
0.18
0.45
25
GHz
GHz
GHz
kHz
V/ns
ns
P-P,OUT
P-P,OUT
P-P,OUT
SR
Differential
2V
10
t
t
t
t
t
t
1% Settling Time
Shutdown Time
Enable Time
0.8
40
S1%
P-P,OUT
SHDN = 0V to 5V
SHDN = 5V to 0V
PWRADJ = 5V to 0V
PWRADJ = 0V to 5V
ns
OFF
15
ns
ON
PWRADJ Off Time
PWRADJ On Time
10
ns
PWRADJ,OFF
PWRADJ,ON
5
ns
+
10% Clamp Release Time
CLHI = 1.5V, V = 1.25V, IN = 1.625V to 1.25V,
1
ns
CL,OFF
CM
–
IN = 1.25V to 0.875V
+
t
10%
Clamp Engage Time
CLHI = 1.5V, V = 1.25V, IN = 1.25V to 1.625V,
5
ns
CL,ON
CM
–
IN = 1.25V to 0.875V
Common Mode AC Characteristics (V Pin)
CM
–3dBBW
SR
V
Pin Small Signal –3dB BW
V
= 0.1V , Measured Single-Ended at Output
10
2
MHz
V/µs
CM
CM
P-P
Common Mode Slew Rate
Overrange AC Characteristics (V Pin)
Measured Single-Ended at Output
CM
OR
+
–
–3dBBW
V
Pin Small Signal –3dB BW
V
= 0.1V , CLHI = 2V, IN = 2.4V, IN = 0.1V,
VOR
200
40
MHz
V/µs
OR
OR
P-P
R
= 1k, Measured Single-Ended at Output
SR
VOR
Overrange Slew Rate
AC Clamping Characteristics
Overdrive Recovery Time
Measured Single-Ended at Output
t
1.9V
2
ns
OVDR
P-P,OUT
6417f
5
LTC6417
ac elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Linearity
10MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–89
–93
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–100
–110
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
56
dBm
dBm
OUTDIFF
P-P
L
P1dB
16.1
70MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–74
–77
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–86
–96
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
48
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.8
140MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–69
–73
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–80
–91
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
46
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.8
200MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–68
–71
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–78
–87
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
44
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.8
240MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–67
–70
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–76
–85
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
43
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.7
300MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–66
–69
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
6417f
6
LTC6417
ac elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–73
–79
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
41
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.6
380MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–66
–68
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
V
V
= 2.4V , R = 50Ω
–68
–77
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
OIP3
Output Third Order Intercept
Output 1dB Compression Point
V
= 2.4V , R = 50Ω
36
39
dBm
dBm
OUTDIFF
P-P
L
P1dB
15.3
400MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–65
–68
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
Output Third Order Intercept
V
V
= 2.4V , R = 50Ω
–68
39
dBc
dBm
dBm
OUTDIFF
OUTDIFF
P-P
L
OIP3
= 2.4V , R = 50Ω
P-P L
P1dB
Output 1dB Compression Point
15.3
500MHz Signal
HD3
Third Harmonic Distortion
V
V
= 2.4V , R = 50Ω
–65
–67
dBc
dBc
OUTDIFF
OUTDIFF
P-P
P-P
L
= 2.4V
IM3
Third Order Intermodulation Distortion
Output Third Order Intercept
V
V
= 2.4V , R = 50Ω
–64
37
dBc
dBm
dBm
OUTDIFF
OUTDIFF
P-P
L
OIP3
= 2.4V , R = 50Ω
P-P L
P1dB
Output 1dB Compression Point
15.0
600MHz Signal
HD3
Third Harmonic Distortion
V
V
V
= 2.4V , R = 50Ω
–60
–58
34
dBc
dBc
OUTDIFF
OUTDIFF
OUTDIFF
P-P
L
IM3
Third Order Intermodulation Distortion
Output Third Order Intercept
Output 1dB Compression Point
= 2.4V , R = 50Ω
P-P L
OIP3
= 2.4V , R = 50Ω
dBm
dBm
P-P
L
P1dB
14.7
700MHz Signal
HD3
Third Harmonic Distortion
V
V
V
= 2.4V , R = 50Ω
–55
–52
31
dBc
dBc
OUTDIFF
OUTDIFF
OUTDIFF
P-P
L
IM3
Third Order Intermodulation Distortion
Output Third Order Intercept
Output 1dB Compression Point
= 2.4V , R = 50Ω
P-P L
OIP3
= 2.4V , R = 50Ω
dBm
dBm
P-P
L
P1dB
14.2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC6417C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 105°C case temperature range but is not
tested or QA sampled at these temperatures. The LT6417I is guaranteed to
meet specified performance from –40°C to 105°C case temperature range.
Note 2: The LTC6417C/LTC6417I is guaranteed functional over the case
temperature operating range of –40°C to 105°C. θ = 6.8°C/W.
Note 4: This parameter is pulse tested.
JC
6417f
7
LTC6417
Typical perForMance characTerisTics
HD3 at 30MHz
HD3 at 30MHz
vs VCM Over Temperature
HD3 at 30MHz vs VCM Over V+
vs PWRADJ Over Temperature
–50
–60
–50
–60
–50
–60
+
P
= 11dBm
P
= 11dBm
P
= 11dBm
OUT
OUT
OUT
V
V
V
= 4.75V
= 5.0V
+
+
= 5.25V
85°C
105°C
–70
–70
–70
85°C
105°C
25°C
–80
–80
–80
–40°C
25°C
–40°C
0.5
–90
–90
–90
–100
–100
–100
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
1
1.5
2
2.5
3
3.5
4
4.5
5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
V
PWRADJ (V)
V
(V)
CM
CM
6417 G01
6417 G03
6417 G02
HD3 at 70MHz
vs PWRADJ Over Temperature
HD3 at 70MHz
vs VCM Over Temperature
HD3 at 70MHz vs VCM Over V+
–50
–60
–45
–55
–65
–75
–85
–95
–50
–60
+
+
+
P
= 11dBm
P
= 11dBm
P
= 11dBm
OUT
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
85°C
85°C
–70
–70
105°C
–80
–80
25°C
25°C
0.5
105°C
–40°C
–90
–90
–40°C
–100
–100
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G05
6417 G04
6417 G06
HD3 at 140MHz
vs VCM Over Temperature
HD3 at 140MHz
vs PWRADJ Over Temperature
HD3 at 140MHz vs VCM Over V+
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
+
+
+
P
= 11dBm
P
= 11dBm
OUT
OUT
P
= 11dBm
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
105°C
85°C
105°C
85°C
25°C
25°C
–40°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
V
PWRADJ (V)
V
CM
CM
6417 G07
6417 G09
6417 G08
6417f
8
LTC6417
Typical perForMance characTerisTics
HD3 at 240MHz
vs VCM Over Temperature
HD3 at 240MHz
vs PWRADJ Over Temperature
HD3 at 240MHz vs VCM Over V+
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–35
–45
–55
–65
–75
–85
+
+
+
P
= 11dBm
P
= 11dBm
P
= 11dBm
OUT
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
105°C
85°C
105°C
85°C
25°C
25°C
–40°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
V
PWRADJ (V)
V
CM
CM
6417 G11
6417 G12
6417 G10
HD3 at 380MHz
vs VCM Over Temperature
HD3 at 380MHz
vs PWRADJ Over Temperature
HD3 at 380MHz vs VCM Over V+
–25
–35
–45
–55
–65
–75
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
+
+
+
P
= 11dBm
P
= 11dBm
OUT
P
= 11dBm
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
105°C
105°C
85°C
25°C
85°C
25°C
–40°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G13
6417 G14
6417 G15
HD3 at 500MHz
vs VCM Over Temperature
HD3 at 500MHz
vs PWRADJ Over Temperature
HD3 at 500MHz vs VCM Over V+
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
+
+
+
P
= 11dBm
P
= 11dBm
P
= 11dBm
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
OUT
–30
–40
–50
–60
–70
–80
85°C
105°C
85°C
105°C
25°C
25°C
–40°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G16
6417 G17
6417 G18
6417f
9
LTC6417
Typical perForMance characTerisTics
HD3 at 600MHz
vs VCM Over Temperature
HD3 at 600MHz
vs PWRADJ Over Temperature
HD3 at 600MHz vs VCM Over V+
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
+
+
+
P
= 11dBm
P
= 11dBm
P
= 11dBm
OUT
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
105°C
85°C
25°C
–40°C
105°C
85°C
25°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
V
(V)
PWRADJ (V)
V
CM
CM
6417 G19
6417 G21
6417 G20
HD3 at 700MHz
vs PWRADJ Over Temperature
HD3 at 700MHz
HD3 at 700MHz vs VCM Over V+
vs VCM Over Temperature
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
+
+
+
P
= 11dBm
P
= 11dBm
OUT
P
= 11dBm
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
85°C
105°C
105°C
85°C
25°C
–40°C
25°C
–40°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G23
6417 G22
6417 G24
OIP3 at 30MHz
vs VCM Over Temperature
OIP3 at 30MHz
vs PWRADJ Over Temperature
OIP3 at 30MHz vs VCM Over V+
55
50
45
40
35
30
25
55
50
45
40
35
30
25
55
50
45
40
35
30
25
25°C
25°C
85°C
–40°C
85°C
–40°C
105°C
105°C
P
= 5dBm/TONE
OUT
∆FREQ = 1MHz
+
V
V
V
= 4.75V
= 5.0V
= 5.25V
+
+
P
= 5dBm/TONE
∆FREQ = 1MHz
P
= 5dBm/TONE
OUT
OUT
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5 1.5
1
2
2.5
3
3.5
4
4.5
5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
V
PWRADJ (V)
V
CM
CM
6417 G25
6417 G27
6417 G26
6417f
10
LTC6417
Typical perForMance characTerisTics
OIP3 at 70MHz
vs VCM Over Temperature
OIP3 at 70MHz
vs PWRADJ Over Temperature
OIP3 at 70MHz vs VCM Over V+
55
50
45
40
35
30
25
55
50
45
40
35
30
25
55
50
45
40
35
30
25
P
= 5dBm/TONE
OUT
–40°C
∆FREQ = 1MHz
–40°C
25°C
25°C
85°C
105°C
85°C
105°C
+
+
+
V
V
V
= 4.75V
= 5.0V
= 5.25V
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
∆FREQ = 1MHz
OUT
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5 1.5
1
2
2.5
3
3.5
4
4.5
5
V
V
CM
PWRADJ (V)
CM
6417 G28
6417 G29
6417 G30
OIP3 at 100MHz
vs VCM Over Temperature
OIP3 at 100MHz
vs PWRADJ Over Temperature
OIP3 at 100MHz vs VCM Over V+
55
50
45
40
35
30
25
55
50
45
40
35
30
25
55
50
45
40
35
30
25
P
= 5dBm/TONE
OUT
–40°C
∆FREQ = 1MHz
–40°C
25°C
25°C
85°C
105°C
105°C
85°C
+
+
+
V
V
V
= 4.75V
= 5.0V
= 5.25V
P
= 5dBm/TONE
∆FREQ = 1MHz
P
= 5dBm/TONE
OUT
OUT
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5 1.5
1
2
2.5
3
3.5
4
4.5
5
V
PWRADJ (V)
V
CM
CM
6417 G32
6417 G33
6417 G31
OIP3 at 140MHz
vs VCM Over Temperature
OIP3 at 140MHz
OIP3 at 140MHz vs VCM Over V+
vs PWRADJ Over Temperature
55
50
45
40
35
30
25
55
50
45
40
35
30
25
55
50
45
40
35
30
25
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
OUT
∆FREQ = 1MHz
∆FREQ = 1MHz
105°C
25°C
–40°C
85°C
25°C
–40°C
85°C
105°C
+
+
+
V
V
V
= 4.75V
= 5.0V
= 5.25V
P
= 5dBm/TONE
OUT
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G34
6417 G35
6417 G36
6417f
11
LTC6417
Typical perForMance characTerisTics
OIP3 at 240MHz
vs VCM Over Temperature
OIP3 at 240MHz
vs PWRADJ Over Temperature
OIP3 at 240MHz vs VCM Over V+
55
50
45
40
35
30
25
50
45
40
35
30
25
20
55
50
45
40
35
30
25
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
OUT
25°C
∆FREQ = 1MHz
∆FREQ = 1MHz
–40°C
–40°C
25°C
85°C
85°C
105°C
105°C
+
+
+
V
V
V
= 4.75V
= 5.0V
P
= 5dBm/TONE
OUT
= 5.25V
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G38
6417 G37
6417 G39
OIP3 at 380MHz
vs VCM Over Temperature
OIP3 at 380MHz
vs PWRADJ Over Temperature
OIP3 at 380MHz vs VCM Over V+
50
45
40
35
30
25
20
55
50
45
40
35
30
25
55
50
45
40
35
30
25
+
+
+
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
P
= 5dBm/TONE
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
∆FREQ = 1MHz
∆FREQ = 1MHz
∆FREQ = 1MHz
–40°C
25°C
–40°C
25°C
85°C
105°C
85°C
105°C
0.5
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
CM
PWRADJ (V)
CM
6417 G40
6417 G41
6417 G42
OIP3 at 500MHz
vs VCM Over Temperature
OIP3 at 500MHz
vs PWRADJ Over Temperature
OIP3 at 500MHz vs VCM Over V+
50
45
40
35
30
25
20
50
45
40
35
30
25
20
50
45
40
35
30
25
20
P
= 5dBm/TONE
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
OUT
OUT
∆FREQ = 1MHz
∆FREQ = 1MHz
∆FREQ = 1MHz
25°C
–40°C
–40°C
25°C
105°C
85°C
85°C
+
+
+
V
V
V
= 4.75V
= 5.0V
= 5.25V
105°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
CM
PWRADJ (V)
CM
6417 G43
6417 G44
6417 G45
6417f
12
LTC6417
Typical perForMance characTerisTics
OIP3 at 600MHz
vs VCM Over Temperature
OIP3 at 600MHz
vs PWRADJ Over Temperature
OIP3 at 600MHz vs VCM Over V+
45
40
35
30
25
20
15
45
40
35
30
25
20
15
45
40
35
30
25
20
15
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
OUT
∆FREQ = 1MHz
∆FREQ = 1MHz
25°C
25°C
–40°C
–40°C
105°C
85°C
85°C
105°C
+
+
+
V
V
V
= 4.75V
= 5.0V
P
= 5dBm/TONE
OUT
= 5.25V
∆FREQ = 1MHz
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
PWRADJ (V)
CM
CM
6417 G46
6417 G47
6417 G48
OIP3 at 700MHz
vs VCM Over Temperature
OIP3 at 700MHz
vs PWRADJ Over Temperature
OIP3 at 700MHz vs VCM Over V+
45
40
35
30
25
20
15
45
40
35
30
25
20
15
45
40
35
30
25
20
15
+
+
+
P
= 5dBm/TONE
P
= 5dBm/TONE
P
= 5dBm/TONE
OUT
OUT
OUT
V
V
V
= 4.75V
= 5.0V
= 5.25V
∆FREQ = 1MHz
∆FREQ = 1MHz
∆FREQ = 1MHz
25°C
25°C
–40°C
–40°C
85°C
85°C
105°C
105°C
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
V
CM
PWRADJ (V)
CM
6417 G49
6417 G50
6417 G51
Output 1dB Compression
vs Frequency and Supply Voltage
Supply Current vs Supply Voltage
Supply Current vs PWRADJ
140
120
100
80
130
120
110
100
90
20
18
16
14
12
10
+
+
+
V
V
V
= 5.25V
= 5.0V
= 4.75V
60
40
80
20
0
70
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
100
200
300
400
500
600
700
SUPPLY VOLTAGE (V)
PWRADJ (V)
FREQUENCY (MHz)
6417 G53
6417 G54
6417 G52
6417f
13
LTC6417
Typical perForMance characTerisTics
Small Signal Transient Response,
Falling Edge
Small Signal Transient Response,
Falling Edge with Input
Small Signal Transient Response,
Rising Edge
62.5mV/
DIV
62.5mV/
DIV
20mV/
DIV
62.5mV/
DIV
6417 G57
6417 G55
6417 G56
1.25ns/DIV
1.25ns/DIV
1.25ns/DIV
Overdrive Recovery and
Overrange Response
Differential Input Return Loss
(S11) vs Frequency
Differential Reverse Isolation
(S12) vs Frequency
–60
–80
0
–10
–20
–30
–40
DEMO BOARD DC1660B
DEMO BOARD DC1660B
R = 0Ω
R = 23.7Ω
600mV/
DIV
R = 0Ω
R = 23.7Ω
–100
–120
10mV/
DIV
6417 G58
10ns/DIV
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
6417 G60
6417 G59
LTC6417 Driving LTC2209
16-Bit ADC, 32K Point FFT,
Differential Forward Gain (S21)
vs Frequency
Differential Output Return Loss
(S22) vs Frequency
fIN = 69.5MHz, –1dBFS, PGA = 0
10
5
0
–10
0
–10
–20
–30
–40
1
DEMO BOARD DC1660B
HDR = –92dBc
R = 0Ω
HD3 = –86dBc
SFDR = 86dBc
SNR = 76.2dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
–20
–30
R = 0Ω
–40
R = 23.7Ω
f
= 153.6Msps
–50
S
DEMO BOARD DC1685A
0
–60
–70
3
R = 23.7Ω
–80
–5
–10
–90
2
–100
–110
–120
DEMO BOARD DC1660B
10
100
1000
0
10 20 30 40 50 60 70 80
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6417 G61
6417 G63
6417 G62
6417f
14
LTC6417
Typical perForMance characTerisTics
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 0
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 270MHz, –1dBFS, PGA = 0
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 380MHz, –1dBFS, PGA = 0
0
–10
0
–10
0
–10
1
HD2 = –81dBc
HD3 = –80dBc
SFDR = 80dBc
SNR = 73.3dB
SEE FIGURE 1/
TABLE 1
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–50
1:4 BALUN
–50
f
= 153.6Msps
S
–60
–60
–60
DEMO BOARD
DC1685A
–70
–70
–70
–80
–80
–80
3
2
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6417 G66
6417 G64
6417 G65
LTC6417 Driving LTC2209 16-Bit ADC,
32K Point FFT, fIN = 69.5MHz and
70.5MHz, –7dBFS/Tone, PGA = 0
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 139.5MHz and
140MHz, –7dBFS/Tone, PGA = 0
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 269.5MHz and
270.5MHz, –7dBFS/Tone, PGA = 0
0
–10
0
–10
0
–10
IM3 = –85dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
IM3 = –75dBc
SEE FIGURE 1/
TABLE 1
IM3 = –80dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
–20
–20
–20
f
= 153.6Msps
1:4 BALUN
S
f = 153.6Msps
–30
S
–30
–30
DEMO BOARD DC1685A
f
= 153.6Msps
DEMO BOARD DC1685A
S
–40
–40
–40
DEMO BOARD
DC1685A
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6417 G67
6417 G69
6417 G68
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 379.5MHz and
380.5MHz, –7dBFS/Tone, PGA = 0
Input Referred Noise Voltage
Input Referred Noise Voltage
vs Frequency and Noise Figure for
the DC1660B with 1:1 Input Balun
vs Frequency and Noise Figure for
the DC1660B with 1:4 Input Balun
24
20
16
12
8
24
0
–10
28
24
20
16
12
8
28
24
20
16
12
8
NOISE FIGURE PWRADJ = 5V
NOISE FIGURE PWRADJ = 0V
NOISE DENSITY PWRADJ = 5V 20
NOISE DENSITY PWRADJ = 0V
NOISE FIGURE PWRADJ = 5V
NOISE FIGURE PWRADJ = 0V
NOISE DENSITY PWRADJ = 5V
NOISE DENSITY PWRADJ = 0V
IM3 = –72dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
–20
f
= 153.6Msps
S
–30
DEMO BOARD DC1685A
16
12
8
–40
–50
–60
–70
–80
–90
–100
–110
–120
4
4
4
4
0
0
0
0
0
10 20 30 40 50 60 70 80
0.001 0.01
0.1
1
10
100
1k
0.001 0.01
0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6417 G70
6417 G72
6417 G71
6417f
15
LTC6417
pin FuncTions
+
V (Pins1, 6, 11, 16):PositivePowerSupply. Typically5V.
PWRADJ (Pin 5): Power Adjust Voltage. The voltage
applied to this pin scales the bias current internal to the
LTC6417. The PWRADJ pin will float to a 1.6V default
voltage. PWRADJ has a Thevenin equivalent resistance of
approximately 14.5k and can be overdriven by an external
voltage. The PWRADJ pin should be bypassed with a high
quality ceramic bypass capacitor of at least 0.01µF.
Split supplies are possible as long as the voltage between
+
V and GND is 4.75V to 5.25V. Bypass capacitors of 680pF
and 0.1µF as close to the part as possible should be used
between the supplies.
CLHI (Pin 2): High Side Clamp Voltage. The voltage ap-
plied to the CLHI pin defines the upper voltage limit of
+
–
+
–
the OUT and OUT pins. This voltage should be set at
least 300mV above the upper voltage range of the ADC.
On a 5V supply, the CLHI pin will float to a 2.5V default
voltage. CLHI has a Thevenin equivalent of approximately
4.8kΩ and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high quality ceramic
bypass capacitor of at least 0.01µF.
IN , IN (Pin 8, Pin 9): Non-inverting and inverting input
pins of the buffer, respectively. These pins are high imped-
ance, approximately 9.5k. If AC-coupled, these pins will
self bias to the voltage applied to the V pin.
CM
SHDN (Pin 12): This pin puts the LTC6417 in sleep mode
when pulled high. If no voltage is applied to the SHDN pin,
it floats down to the same potential as GND.
GND (Pins 3, 7, 10, 17, 20, Exposed Pad Pin 21): Nega-
tive Power Supply. Normally tied to ground. All pins and
the exposed pad must be tied to the same voltage. GND
may be tied to a voltage other than ground as long as the
V
(Pin 14): Overrange Output. This pin, by default at
OR
3.4V, will be pulled down to GND, when one or both input
signals go beyond the minimum or maximum swing set
by the CLHI and V pins.
CM
+
voltage between V and GND is 4.75V to 5.25V. If the GND
V
(Pin15):Thispinsetstheoutputcommonmodevolt-
pins are not tied to ground, bypass each with 680pF and
0.1µF capacitors as close to the package as possible. The
exposed pad must be soldered to the printed circuit board
ground plane for good heat transfer.
CM
+
–
+
–
age seen at OUT and OUT by driving IN and IN through
a buffer with a high output resistance of 9.5k. The V
CM
pin has a Thevenin equivalent resistance of approximately
2.7k and can be overdriven by an external voltage. If no
NC (Pins 4, 13): No Connection. These pins are not con-
nected internally.
voltage is applied to V , it will float to a default voltage of
CM
approximately 1.25V on a 5V supply. The V pin should
CM
be bypassed with a high quality ceramic bypass capacitor
of at least 0.01µF.
–
+
OUT , OUT (Pin 18, Pin 19): Outputs.
6417f
16
LTC6417
Dc TesT circuiT scheMaTic
+
V
1, 6, 11, 16
+
V
15
2
V
V
CM
CM
19
18
CLHI
CLHI
–
+
+
–
+
–
OUT
+
–
V
V
= IN – IN
V
V
= OUT – OUT
8
INDIFF
OUTDIFF
OUT
+
–
+
IN
IN
IN
+
–
+
–
LTC6417
V
C
LOAD
R
LOAD
IN + IN
OUT + OUT
9
–
=
=
OUTCM
INCM
IN
OUT
2
2
OUT
5
6417 TC
PWRADJ
OR
PWRADJ
SHDN
14
V
OR
12
3, 7, 10, 17, 20, 21
block DiagraM
LTC6417 Simplified Schematic
+
V
I1
I2
V
OVER
OR
RANGE
DETECT
QN1
QP3
+
IN
QN3
QP1
+
OUT
×1
CLHI
–
CLLO
+
×2
V
CM
×1
QN2
QP4
–
IN
QN4
QP2
–
OUT
PWRADJ
SHDN
REFERENCE AND
BIAS CONTROL
I3
I4
GND
6417 BD
6417f
17
LTC6417
applicaTions inForMaTion
Circuit Operation
Input Impedance and Matching
The LTC6417 is a low noise and low distortion fully dif-
ferential unity gain ADC driver with a –3dB bandwidth
spanning DC to 1.6GHz, a differential input impedance of
18.5kΩ, and a differential output impedance of 3Ω. The
LTC6417 is composed of a fully differential buffer with
output common mode voltage control circuitry and high
speed voltage-limiting clamps at the output. Lowpass or
bandpass filters are easily implemented with just a few
external components. The LTC6417 is very flexible in
terms of I/O coupling. It can be AC- or DC-coupled at the
inputs, the outputs or both. When using the LTC6417 with
DC-coupled inputs, best performance is obtained with an
input common mode voltage between 1V and 1.5V. For
AC-coupled operation, the LTC6417 will take the voltage
The LTC6417 has a high differential input impedance of
18.5kΩ. The differential inputs may need to be terminated
to a lower value impedance, e.g. 50Ω, in order to provide
an impedance match for the source. Figure 1 shows input
matchingandsingle-endedtodifferentialconversionusing
a 1:1 balun, while Figure 2 shows a similar circuit using
a 1:4 balun to achieve an additional 6dB of voltage gain.
These circuits provide a wideband impedance match.
The balun and matching resistors must be placed close
to the input pins in order to minimize the rejection due to
input mismatch. In Figures 1 and 2, the capacitor center-
tapping the two input termination resistors improves high
frequency common mode rejection. As an alternative to
this wideband approach, a narrowband impedance match
can be used at the inputs of the LTC6417 for frequency
selection and/or noise reduction.
applied to the V pin and use it to bias the inputs so
CM
that the output common mode voltage equals V , thus
CM
no external circuitry is needed. The V pin has been
CM
designed to directly interface with the V pin found on
CM
Linear Technology’s high speed ADC families.
T1
0.1µF
MABA-007159-000000
8
9
19
18
+
+
–
IN
OUT
24.9Ω
24.9Ω
1:1
0.1µF
5
4
1
3
50Ω
LTC6417
–
+
0.1µF
0.1µF
V
IN
–
IN
OUT
6417 F01
Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun
T1
0.1µF
0.1µF
TCM4-19+
8
9
19
18
4
6
3
2
+
+
IN
OUT
0.1µF
100Ω
100Ω
50Ω
LTC6417
–
0.1µF
V
IN
+
–
–
IN
OUT
1
6417 F02
Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun
6417f
18
LTC6417
applicaTions inForMaTion
The noise figure of the LTC6417 application circuit also
depends upon the input termination. For example, the
input 1:4 balun in Figure 2 improves noise figure by add-
ing 6dB of voltage gain at the inputs. A trade-off between
gainandnoiseisobviouswhenconstantnoisefigurecircle
and constant gain circle are plotted within the same input
Smith Chart. This technique can be used to determine
the optimal source impedance for a given gain and noise
requirement.
matching for the 1:1 balun is desired, resistors of 23.7Ω
should be inserted in series with each LTC6417 output.
This is shown in Figure 4 where the LTC6417 is driving a
differential 100Ω load impedance.
As mentioned above, the LTC6417 can drive an ADC with-
out external output impedance matching, but improved
performance can usually be obtained with the addition of
a few components. Figure 5 shows a 6th order bandpass
filter with a 148MHz center frequency, –3dB points of
85MHz and 210MHz used for driving the LTC2209 16-bit
ADC. In the passband the filter has less than 1 dB ripple.
This higher order filter has a sharp roll-off outside its
passband, therefore it rejects noise and suppresses dis-
tortion components in its stopband. To double the filter
center frequency, halve the capacitor and inductor values,
and maintain resistor values; this also doubles the filter
bandwidth.
Output Match and Filter
The LTC6417 provides an output resistance of 1.5Ω at
each output. In most cases, the LTC6417 can be used
to drive an ADC without back termination but for testing
purposes, Figure 3 shows the LTC6417 driving a differ-
ential 50Ω load impedance using a 1:1 balun. If output
T2
0.1µF
0Ω
MABA-007159-000000
8
9
18
19
+
+
IN
OUT
50Ω
LTC6417
–
0.1µF
0Ω
–
6417 F03
IN
OUT
Figure 3. LTC6417 with No Back Termination Driving a
50Ω Load Using a 1:1 Balun
T2
0.1µF
0.1µF
23.7Ω
23.7Ω
MABA-007159-000000
8
9
19
18
+
+
IN
OUT
3
1
4
5
50Ω
LTC6417
–
–
6417 F04
IN
OUT
Figure 4. Output Termination for Differential 50Ω Load
Using a 1:1 Balun
6417f
19
LTC6417
applicaTions inForMaTion
5V
3.3V
C43
27pF
C45
18pF
680pF
0.1µF
2.2µF
E1
51nH
E3
75nH
1,6,
11,16
R36
R42
T1
+
5
10Ω
60.4Ω
300Ω
V
WBC4-14LB
2
PWRADJ
4
3
8
9
C40
0Ω
0Ω
+
CLHI
+
–
100Ω
100Ω
19
IN
A
A
IN
IN
12pF
+
R53
C41
12pF
E5
51nH
16
2
OUT
OUT
50Ω
120Ω
LTC2209
LTC6417
–
–
R12
60.4Ω
•
•
C10
12pF
R43
300Ω
V
IN
OR
18
+
–
V
CM
6
1
10Ω
V
PGA = 0
14
1k
CM
SHDN
15
GND
0.01µF
C44
27pF
C46
18pF
12
0.01µF
E2
51nH
E3
75nH
CLOCK
(153.6MHz)
3,7,10,
17, 20,21
6417 F05
2.2µF
Figure 5. DC1685A Simplified Schematic with Suggested Bandpass Filter for Driving an LTC2209 16-Bit ADC at 140MHz
Table 1. Bandpass Filter Component Values for Different Input Frequencies
INPUT FREQUENCIES
COMPONENTS
R12 = R36
C43 = C44
E1 = E2
70MHz
60.4Ω
56pF
140MHz
60.4Ω
27pF
270MHz
60.4Ω
15pF
380MHz
60.4Ω
12pF
100nH
47pF
51nH
12pF
27nH
12pF
18nH
10pF
C41
C10 = C40
E5
13pF
12pF
3.3pF
27nH
300Ω
120Ω
10pF
2.7pF
18nH
300Ω
120Ω
8.2pF
27nH
100nH
300Ω
120Ω
39pF
51nH
300Ω
120Ω
18pF
R42 = R43
R53
C45 = C46
E3 = E4
150nH
75nH
39nH
6417f
20
LTC6417
applicaTions inForMaTion
Output Common Mode Adjustment
LTC6417
+
For AC-coupled applications, the output common mode
V
voltage is set by the V pin. An internal buffer, as shown
1.5Ω
CM
IN+
OUT+
OUT–
in Figure 6, couples the voltage on the V pin to the
CM
x1
x1
10.8k
3.6k
inputs via high impedance resistors. Because the input
common mode voltage is approximately the same as the
output common mode voltage, both are approximately
9.25k
9.25k
V
CM
x1
1.5Ω
IN–
equaltothevoltageappliedtotheV pin.ForDC-coupled
CM
applications, the internal V is overdriven by the input
CM
GND
signal. The V pin has a Thevenin equivalent resistance
CM
of 2.7k and can be overdriven by an external voltage. The
6417 F06
V
pin floats to a default voltage of 1.25V on a 5V supply.
CM
The output common mode voltage is capable of tracking
Figure 6. LTC6417 Internal Topology Showing
the Common Mode Buffer Biasing the Inputs
V
V
in a range from 0.29V to 2.25V on a 5.0V supply. The
pin can be floated, but it should always be bypassed
CM
CM
close to the LTC6417 with a 0.1µF bypass capacitor to
GND. When interfacing with A/D converters such as the
LTC6417
LTC22xx families, the V pin can be connected to the
CM
+
V
V
output pin of the ADC, as shown in Figure 5.
CM
9.6k
Clamping, the CLHI Pin and the V Pin
CLHI
CM
CLHI (INT)
x1
–
The CLHI pin is used to set the high side clamp voltage
of the high speed internal circuitry.
9.6k
CLLO (INT)
+
V
CM
This limits the single-ended maximum and minimum
voltage excursion at each of the outputs. This feature is
extremely important in applications with input signals
having very large peak-to-average ratios such as cellular
base station receivers.
x2
GND
6417 F07
Figure 7. Internal Circuitry Generating Symmetric
Clamp Voltages with Respect to VCM
Internal circuitry generates a symmetric low side clamp
voltage with respect to the common mode voltage V
CM
(Figures 7 and 8). The LTC6417 clamp control circuitry
features two additional mechanisms. First, internally im-
posedmaximumswingof2.5Vandminimumswingof0.2V
ensure that the transistors do not go into deep saturation.
Thisensuresaquickrecoveryaftertheclampsarereleased.
CLHI
V
CM
CLLO
Second, if CLHI voltage is less than V , internal CLLO
CM
6417 F08
starts to track CLHI. This limits output swing and protects
output transistors. Since the clamp response is on the
order of 5ns to clamp and 1ns to release, clamp circuit
becomes less effective at frequencies beyond 160MHz.
Figure 8. Symmetric High- and Low-Side Clamp
Voltages with Respect to VCM
6417f
21
LTC6417
applicaTions inForMaTion
If a very large signal arrives at the LTC6417, the voltages
The V pin, as shown in Figure 9, is internally connected
OR
applied to the CLHI and V pins will determine the maxi-
to a current source sourcing 2mA, plus an internal 20k
resistor pull-down to GND. An internal clamp limits the
maximum output to 3.4V. As soon as one of the inputs
goes beyond the limits, and therefore engages one of the
CM
mum and minimum output swing. Once the input signal
returnstothenormaloperatingrange,theLTC6417returns
to linear operation within 2ns. For DC-coupled operation,
the common mode of the input signals might be different
clamps, the output current, hence, the V voltage goes
OR
than the voltage on the V pin. The minimum swing will
to zero. The dynamic response of the V pin can be ad-
CM
OR
stillbesetbythevoltagesappliedtotheV andCLHIpins.
justed with an external resistor and an optional external
CM
capacitor. For a high speed operation, add a 50Ω resistor
CLHI is a high impedance input. It has an input impedance
of 4.8k. On a 5V supply, CLHI self-biases to 2.5V. To limit
the signal swing to a subsequent stage’s power supply,
e.g. an ADC such as the LTC2165, simply connect CLHI
to the positive supply pin of the LTC2165. The CLHI pin
should be bypassed with a 0.1µF capacitor as close to the
LTC6417 as possible.
from V to GND, resulting in a high speed signal with
OR
100mV swing.
The PWRADJ Pin
The voltage applied to the PWRADJ pin scales the supply
current and performance of the LTC6417. This is useful
for reducing power consumption in applications where
linearity of the LTC6417 exceeds the linearity of the other
components in the system; hence LTC6417’s linearity can
bederatedwithouteffectingsystemperformance.PWRADJ
is a high impedance input. It has an input impedance of
14.5k.Ona5Vsupply,PWRADJself-biasesto1.6V.Forfull
The V Pin
OR
The V , overrange pin signals an overrange condition
OR
whenoneorbothinputsexceedtheminimumormaximum
signal swing limits set by the CLHI and V pins.
CM
+
The LTC6417 V pin can be used by a control system to
power, simply connect PWRADJ to the positive supply V .
OR
limit the input power dynamically. This is very useful in
applications where the overload response of the complete
system would be too slow.
For minimum power, short the PWRADJ pin to GND. The
PWRADJpinshouldbebypassedwitha0.1µFcapacitoras
close to the LTC6417 as possible. LTC6417 performance
vs PWRADJ can be found in the graphs.
LTC6417
+
V
The SHDN Pin
2mA
Whenpulledhigh, theSHDNpinputstheLTC6417insleep
mode,significantlyreducingsupplycurrent.SHDNisahigh
impedance input. It has an input impedance of 10.5kΩ. If
theSHDNpinisnotdrivenwithanexternalvoltage,itfloats
down to the same potential as GND, keeping the LTC6417
enabled. The SHDN pin should be bypassed with a 0.1µF
capacitor as close to the LTC6417 as possible.
V
OR
20k
I
CL
GND
6417 F09
In sleep mode, the input and output stages are turned off,
but the input and output clamps are kept alive to protect
the part against overvoltage.
Figure 9. LTC6417 Internal Topology Showing
VOR Pin with Pull-Down Resistor and Clamp
The supply current in sleep mode is only 24mA, instead
of the typical 125mA. But should the clamps turn on, the
current drawn from the supply can be as high as 180mA.
6417f
22
LTC6417
applicaTions inForMaTion
This can be avoided by following a few precautions when
putting the LTC6417 in sleep mode:
Noise figure (NF) is calculated from the ratio of these
noise powers:
e2no
•ꢀ Doꢀnotꢀforceꢀtheꢀoutputsꢀbelowꢀtheꢀinputs,ꢀthisꢀwillꢀturnꢀ
the output stages on.
NF = 10log 1+
e2
no(mR )
S
•ꢀ EitherꢀfloatꢀCLHIꢀorꢀtieꢀitꢀtoꢀV . This will allow a wider
CC
signalrangeattheinputsbeforetheclampsareactivated.
•ꢀ MaintainꢀtheꢀinputsꢀbelowꢀCLHIꢀorꢀ2.5Vꢀwhicheverꢀisꢀ
lower, otherwise the input clamps will be activated.
•ꢀ DoꢀnotꢀshortꢀV or the outputs to GND, in either case
CM
1:m
the output clamps will turn on. Current drawn from the
supply can be as high as 180mA.
LTC6417
R
S
R
T
TRANSFORMER
6417 F10
•ꢀ Floatꢀtheꢀoutputsꢀifꢀpossible.ꢀTheꢀoutputsꢀwillꢀbeꢀpulledꢀ
down by internal resistors to V
.
CM
Heeding these precautions will protect the LTC6417 as
well any part it is driving, while maintaining a low current
consumption in sleep mode.
Figure 10. LTC6417 with a Transformer
Noise and Noise Figure
TheLTC6417’sdifferentialinputreferredvoltageandcurrent
noisedensitiesare 1.5nV/√Hzand4.3pA/√Hz,respectively.
LTC6417
mR
S
R
T
6417 F11
Before presenting a noise model, the circuit with the
transformer in Figure 10 will be simplified. In Figure 11,
the circuit is redrawn with the source impedance reflected
to the secondary side of the transformer. The source
impedance is multiplied by the impedance ratio m of the
transformer. In Figure 12, noise sources associated with
the amplifier and resistors have been added. Based on
this noise model of the LTC6417, the total output noise
power excluding the noise contribution of the source is:
Figure 11. Source Resistance Referred to the Secondary
2
e
ni
2
e
no
2
2
2
LTC6417
mR
S
i
R
T
i
i
ni
mRS
RT
2
e no2 = e2 + i •R
+ i2 •R2
R
EQ
T
(
)
)
ni
ni
EQ
6417 F12
2
4kT
RT
= e2 + i •R
+
•R2
EQ
(
ni
ni
EQ
Figure 12. LTC6417 Simplified Noise Model
where R = mR ||R is the equivalent impedance seen
EQ
S
T
at the input of the LTC6417. The output noise power due
to the noise of source resistance is given by:
2
e no(mR ) = i2
•R2
mR
EQ
S
S
4kT
mRS
=
•R2
EQ
6417f
23
LTC6417
applicaTions inForMaTion
Interfacing the LTC6417 to A/D Converters
In most cases the termination resistor will be matched to
thesourceresistance,e.g.R =mR .FortheLTC6417with
T
S
The LTC6417 has been specially designed to interface
directly with high speed A/D converters. It is possible
to drive the ADC directly from the LTC6417. In practice,
however, better performance may be obtained by adding
a few external components at the output of the LTC6417.
Figure 5 shows the LTC6417 driving an LTC2209 16-bit
ADC.ThedifferentialoutputsoftheLTC6417arebandpass
filtered, then drive the differential inputs of the LTC2209.
In many applications, a filter like this is desirable to limit
the wideband noise of the amplifier. This is especially
true in high performance 16-bit designs. The minimum
recommendednetworkbetweentheLTC6417andtheADC
is simply two 10Ω series resistors, which are used to help
eliminateresonancesassociatedwiththestraycapacitance
ofPCBtracesandthestrayinductanceoftheinternalbond
wires at the ADC input pins and the driver output pins.
a wide-band terminated transformer, a plot of output and
input noise density and NF versus termination resistor is
shown in Figure 13. To get the best noise performance in
thesystem,usetheLTC6417matchedtoatransformerwith
high impedance ratio. Although the output noise density
will be higher, noise figure will improve because of the
additional gain realized in the transformer. An impedance
ratio greater than 8 is not recommended, as the increased
terminationresistancewiththeLTC6417inputcapacitance
will limit signal bandwidth. Consult Table 2 for a quick
estimate of the LTC6417’s output noise density and NF
for different transformer impedance ratios. Measured NF
numbers will be higher as the simple noise model does
not take the insertion loss in the transformer into account.
Table 2. Output Noise Density and NF of the LTC4617 with a
Wide-Band Terminated Transformer, RS = 50Ω
Single-Ended Signals
TRANSFORMER TERMINATION
OUTPUT NOISE
IMPEDANCE
RATIO m
RESISTOR R
(Ω)
GAIN
(V/V)
DENSITY e
NF
T
no
The LTC6417 has not been designed to convert single-
ended signals to differential signals. A single-ended input
signal can be converted to a differential signal via a balun
connected to the inputs of the LTC6417. Figure 5 shows
the LTC6417 driven by a 1:4 transformer which provides
6dB of voltage gain while also performing a single-ended
to differential conversion.
(nV/√Hz)
(dB)
1
2
4
8
50
1.0
1.4
2.0
2.8
1.57
1.64
1.80
2.14
11.2
8.9
7.0
5.9
100
200
400
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
12
11
10
9
NF
Power Supply Considerations
e
no
e
ni
For best linearity, the LTC6417 should have a positive
+
supply of V = 5V. For ESD protection, the LTC6417 has
an internal edge-triggered supply voltage clamp. The
timing mechanism of the clamp enables the LTC6417’s
protection circuit during ESD events. This internal clamp
can also be activated by voltage overshoot and rapid slew
8
7
6
+
rateonthepositivesupplyV pin. TheLTC6417shouldnot
5
be hot-plugged into a powered socket because there is a
risk of activating this internal ESD clamp circuit. Bypass
capacitors of 680pF and 0.1µF should be connected to the
4
50 100 150 200 250 300 350 400
TERMINATION RESISTANCE (Ω)
6417 F13
+
V pin, as close as possible to the LTC6417.
Figure 13. LTC4617 Output and Input Noise
Density and NF vs Termination Resistance
Interfacing the LTC6417 with Active Mixers for
Ultrawide IF Bandwidth
TheLTC6417isanexcellentinterfaceamplifierforusewith
active downconverting mixers like the LTC5567. By using
6417f
24
LTC6417
applicaTions inForMaTion
the LTC6417 as a post-amplifier for the LTC5567, it is pos-
sible to achieve IF bandwidths in excess of 500MHz, while
addingbandpassfiltering.Akeytoachievingthisextremely
wide IF bandwidth is the use of pre-emphasis inductors
in series with the LTC6417 inputs to compensate for the
inherent rolloff caused by the LTC6417 input capacitance
interacting with the interface impedance. In the example
seen in Figure 14, a value of 33nH for each pre-emphasis
inductorgivesexcellentwidebandperformance. Figure15
shows performance for various values of L. For L = 33nH,
overall conversion gain remains within 1dB from 90MHz
to 590MHz, resulting in 500MHz of IF bandwidth.
demonstration circuit for the LTC6417. The board layout
and the schematic are shown in Figures 16 and 17. These
circuits include a 1:4 input balun and a 1:1 output balun
forsingle-ended-to-differentialconversion,allowingdirect
analysisusinga2-portnetworkanalyzer.Includingtheinput
and output baluns, the –3dB bandwidth is approximately
600MHz. A 1:4 input balun before the LTC6417 inputs
provides 6dB of voltage gain, but results in better noise
figure performance compared to a 1:1 input balun. Noise
figure measurements for both input baluns can be found
in the graphs.
TestcircuitBisDC1685A.ItconsistsofanLTC6417driving
an LTC2209 16-bit 153.6Msps ADC. It is intended for use
in conjunction with DC890B (computer interface board)
and proprietary Linear Technology evaluation software
to evaluate the performance of both parts together. Both
the DC1685A board layout and the schematic can be seen
Figures 18 and 19.
Test Circuits
Due to the fully differential design of the LTC6417 and its
usefulnessinapplicationsbothwithandwithoutADCs,two
test circuits have been used to generate the information
in this data sheet. Test circuit A is DC1660B, a two-port
LO
1.65GHz
1nF
L
IF+
1nF
LTC5567
23.2Ω
1:1
249Ω
390n
390n
127Ω
127Ω
RF
1.69GHz
TO
IF
OUT
V
LTC6417
CC
50Ω
10nF
1nF
2.39GHz
L
249Ω
23.2Ω
1nF
IF–
6417 F14
Figure 14
2
1
L = 33nH
L = 18nH
0
–1
–2
–3
–4
–5
–6
–7
LPF
L = 0nH
40 140 240 340 440 540 640 740
IF FREQUENCY (MHz)
6417 F15
Figure 15
6417f
25
LTC6417
applicaTions inForMaTion
Figure 16. Demo Board DC1660B Layout
6417f
26
LTC6417
applicaTions inForMaTion
V +
1
V +
1 6
1 5
1 4
1 3
H I C L
2
C V M
N D G
3
O R
N C
N C
4
R A W D P J
N W
H S U T D O
1 2
5
6
V +
V +
1 1
6417f
27
LTC6417
applicaTions inForMaTion
Figure 18. Demo Board DC1685A Layout
6417f
28
LTC6417
applicaTions inForMaTion
6417f
29
LTC6417
applicaTions inForMaTion
6417f
30
LTC6417
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
2.65 ± 0.05
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ± 0.05
× 45° CHAMFER
1.50 REF
19 20
R = 0.05 TYP
3.00 ± 0.10
0.40 ± 0.10
1
2
PIN 1
TOP MARK
(NOTE 6)
2.65 ± 0.10
1.65 ± 0.10
4.00 ± 0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6417f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6417
Typical applicaTion
DC1685A Simplified Schematic with Suggested Output Termination for Driving an LTC2209 16-Bit ADC at 140MHz
5V
3.3V
C43
27pF
C45
18pF
680pF
0.1µF
2.2µF
E1
51nH
E3
75nH
1,6,
11,16
R36
R42
T1
+
5
10Ω
60.4Ω
300Ω
V
WBC4-14LB
2
PWRADJ
4
3
8
9
C40
+
CLHI
+
–
100Ω
100Ω
19
IN
A
A
IN
12pF
+
R53
C41
12pF
E5
51nH
16
2
OUT
OUT
50Ω
120Ω
LTC2209
LTC6417
–
–
R12
60.4Ω
•
•
C10
12pF
R43
300Ω
V
IN
IN
OR
18
+
V
CM
6
1
10Ω
–
V
PGA = 0
14
1k
CM
SHDN
15
GND
0.01µF
C44
27pF
C46
18pF
12
0.01µF
E2
51nH
E3
75nH
CLOCK
(153.6MHz)
3,7,10,
17, 20,21
6417 TA02
2.2µF
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
–71dBc IM3 at 240MHz 2V Composite, I = 90mA, A = 8dB, 14dB,
Fixed Gain IF Amplifiers/ADC Drivers
LTC6400-8/LTC6400-14/ 1.8GHz Low Noise, Low Distortion Differential
LTC6400-20/LTC6400-26 ADC Drivers
P-P
S
V
20dB, 26dB
LTC6420-20
Dual 1.8GHz Low Noise, Low Distortion Differential Dual Version of the LTC6400-20, A = 8dB, 14dB, 20dB, 26dB
V
ADC Drivers
LTC6401-8/LTC6401-14/ 1.3GHz Low Noise, Low Distortion Differential
LTC6401-20/LTC6401-26 ADC Drivers
–74dBc IM3 at 140MHz 2V Composite, I = 50mA, A = 8dB, 14dB,
P-P S V
20dB, 26dB
LTC6421-20
Dual 1.3GHz Low Noise, Low Distortion Differential Dual Version of the LTC6401-20, A = 8dB, 14dB, 20dB, 26dB
V
ADC Drivers
IF Amplifiers/ADC Drivers with Variable Gain
LTC6412
LT5554
LT5514
LT5524
800MHz, 31dB Range Analog-Controlled VGA
Continuously Adjustable Gain Control, –14dB to 17dB Linear-in-dB
Gain Range
High Dynamic Range 7-Bit Digitally Controlled IF
VGA/ADC Driver
OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB Steps
Ultra-Low Distortion IF Amplifier/ADC Driver with OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB Steps
Digitally Controlled Gain
Low Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB Steps
Baseband Differential Amplifiers
LT6416
2GHz Low Noise Differential 16-Bit ADC Buffer
–84dBc IM3 at 160MHz 2V Composite, A = 1, e = 1.8nV/√Hz, 42mA
P-P V n
LTC6409
LTC6406
10GHz 1.1nV√Hz ADC Driver
AC- or DC-Coupled 0MHz to 100MHz
3GHz Rail-to-Rail Input Differential Amplifier/
ADC Driver
–65dBc IM3 at 50MHz 2V Composite, Rail-to-Rail Inputs,
P-P
e = 1.6nV/√Hz, 18mA
n
LTC6404-1/LTC6404-2/
LTC6404-4
Low Noise Rail-to-Rail Output Differential
Amplifier/ADC Driver
16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, e = 1.5nV/√Hz,
n
LTC6404-1 is Unity-Gain Stable, LTC6404-2 is Gain-of-2 Stable
LTC6403-1
Low Noise Rail-to-Rail Output Differential
Amplifier/ADC Driver
16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, e = 2.8nV/√Hz
n
ADCs
LTC2209
LTC2208
16-Bit 160Msps ADC
16-Bit 130Msps ADC
77.3dBFS Noise Floor, 100dB SFDR
78dBFS Noise Floor, 100dB SFDR
6417f
LT 0712 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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