LTC6993CS6-3#TRMPBF [Linear]
LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C;型号: | LTC6993CS6-3#TRMPBF |
厂家: | Linear |
描述: | LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C 时钟 光电二极管 逻辑集成电路 |
文件: | 总28页 (文件大小:418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
TimerBlox: Monostable
Pulse Generator (One Shot)
FeaTures
DescripTion
n
Pulse Width Range: 1µs to 33.6 Seconds
The LTC®6993 is a monostable multivibrator (also known
as a “one-shot” pulse generator) with a programmable
pulse width of 1µs to 33.6 seconds. The LTC6993 is part
oftheTimerBlox® familyofversatilesilicontimingdevices.
n
Configured with 1 to 3 Resistors
n
Pulse Width Max Error:
n
<2.3% for Pulse Width > 512µs
n
<3.4% for Pulse Width of 8µs to 512µs
A single resistor, R , programs an internal master os-
SET
n
<4.9% for Pulse Width of 1µs to 8µs
cillator frequency, setting the LTC6993’s time base. The
n
Four LTC6993 Options Available:
output pulse width is determined by this master oscillator
n
Rising-Edge or Falling-Edge Trigger
Retriggerable or Non-Retriggerable
and an internal clock divider, N , programmable to eight
DIV
n
21
settings from 1 to 2 .
n
Configurable for Positive or Negative Output Pulse
Fast Recovery Time
n
n
n
n
n
n
n
NDIV •RSET
tOUT
=
•1µs, NDIV = 1, 8, 64,...,221
2.25V to 5.5V Single Supply Operation
70µA Supply Current at 10µs Pulse Width
500µs Start-Up Time
CMOS Output Driver Sources/Sinks 20mA
–55°C to 125°C Operating Temperature Range
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
50kΩ
The output pulse is initiated by a transition on the trigger
input(TRIG).Eachpartcanbeconfiguredtogenerateposi-
tive or negative output pulses. The LTC6993 is available
in four versions to provide different trigger signal polarity
and retrigger capability.
DEVICE
INPUT POLARITY
Rising-Edge
Rising-Edge
Falling-Edge
Falling-Edge
RETRIGGER
LTC6993-1
LTC6993-2
LTC6993-3
LTC6993-4
No
Yes
No
applicaTions
n
Watchdog Timer
n
Frequency Discriminators
Yes
n
Missing Pulse Detection
Envelope Detection
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
The LTC6993 also offers the ability to dynamically adjust
thewidthoftheoutputpulseviaaseparatecontrolvoltage.
n
n
n
For easy configuration of the LTC6993, download the
TimerBlox Designer tool at www.linear.com/timerblox.
L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical applicaTion
Envelope Detector
80kHz CARRIER
TRIG
SIGNAL
MODULATED
CARRIER
TRIG
GND
SET
OUT
2V/DIV
ENVELOPE
LTC6993-2
3.3V
+
V
16µs
0.1µF
OUT
2V/DIV
DIV
R
SET
69931234 TA01a
800k
69931234 TA01b
50µs/DIV
69931234fc
1
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
absoluTe MaxiMuM raTings (Note 1)
+
Supply Voltage (V ) to GND ........................................6V
Specified Temperature Range (Note 3)
Maximum Voltage on Any Pin
LTC6993C................................................ 0°C to 70°C
LTC6993I.............................................–40°C to 85°C
LTC6993H.......................................... –40°C to 125°C
LTC6993MP....................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
..................................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6993C............................................–40°C to 85°C
LTC6993I.............................................–40°C to 85°C
LTC6993H.......................................... –40°C to 125°C
LTC6993MP....................................... –55°C to 125°C
S6 Package.......................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
+
6
5
4
OUT
GND
TRIG
V
1
2
3
TRIG 1
GND 2
SET 3
6 OUT
7
DIV
SET
+
5 V
4 DIV
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
= 150°C, θ = 64°C/W, θ = 10.6°C/W
T
JMAX
= 150°C, θ = 192°C/W, θ = 51°C/W
JMAX
JA
JC
JA
JC
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
6-Lead (2mm × 3mm) Plastic DFN
SPECIFIED TEMPERATURE RANGE
LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LDXH
LTC6993IDCB-1#TRMPBF LTC6993IDCB-1#TRPBF LDXH
LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LDXH
LTC6993CDCB-2#TRMPBF LTC6993CDCB-2#TRPBF LDXK
LTC6993IDCB-2#TRMPBF LTC6993IDCB-2#TRPBF LDXK
LTC6993HDCB-2#TRMPBF LTC6993HDCB-2#TRPBF LDXK
LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LFMJ
LTC6993IDCB-3#TRMPBF LTC6993IDCB-3#TRPBF LFMJ
LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LFMJ
LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LFMM
LTC6993IDCB-4#TRMPBF LTC6993IDCB-4#TRPBF LFMM
LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF LFMM
0°C to 70°C
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6993CS6-1#TRMPBF LTC6993CS6-1#TRPBF
LTC6993IS6-1#TRMPBF LTC6993IS6-1#TRPBF
LTDXG
LTDXG
LTDXG
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
LTC6993HS6-1#TRMPBF LTC6993HS6-1#TRPBF
6-Lead Plastic TSOT-23
69931234fc
2
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
LTC6993CS6-2#TRMPBF LTC6993CS6-2#TRPBF
LTC6993IS6-2#TRMPBF LTC6993IS6-2#TRPBF
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTDXJ
LTDXJ
LTDXJ
LTFMH
LTFMH
LTFMH
LTFMK
LTFMK
LTFMK
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6993HS6-2#TRMPBF LTC6993HS6-2#TRPBF
LTC6993CS6-3#TRMPBF LTC6993CS6-3#TRPBF
LTC6993IS6-3#TRMPBF
LTC6993IS6-3#TRPBF
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6993HS6-3#TRMPBF LTC6993HS6-3#TRPBF
LTC6993CS6-4#TRMPBF LTC6993CS6-4#TRPBF
LTC6993IS6-4#TRMPBF
LTC6993IS6-4#TRPBF
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
LTC6993HS6-4#TRMPBF LTC6993HS6-4#TRPBF
LTC6993MPS6-1#TRMPBF LTC6993MPS6-1#TRPBF LTDXG
LTC6993MPS6-2#TRMPBF LTC6993MPS6-2#TRPBF LTDXJ
LTC6993MPS6-3#TRMPBF LTC6993MPS6-3#TRPBF LTFMH
LTC6993MPS6-4#TRMPBF LTC6993MPS6-4#TRPBF LTFMK
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
Output Pulse Width
Pulse Width Accuracy (Note 4)
1µ
33.55
sec
OUT
∆t
N
≥ 512
1.7
2.4
3.6
4.0
2.3
3.0
%
%
OUT
DIV
l
l
l
l
8 ≤ N ≤ 64
3.4
4.4
%
%
DIV
N
= 1 (LTC6993-1 or LTC6993-2)
= 1 (LTC6993-3 or LTC6993-4)
4.9
6.0
%
%
DIV
DIV
N
5.3
6.4
%
%
l
l
∆t /∆T
OUT
Pulse Width Drift Over Temperature
Pulse Width Change With Supply
N
N
≥ 512
≤ 64
0.006
0.008
%/°C
%/°C
DIV
DIV
+
+
l
l
N
≥ 512
V = 4.5V to 5.5V
–0.6
–0.4
–0.2
–0.1
%
%
DIV
V = 2.25V to 4.5V
+
+
l
l
l
8 ≤ N ≤ 64
V = 4.5V to 5.5V
–0.9
–0.7
–1.1
–0.2
–0.2
–0.1
%
%
%
DIV
V = 2.7V to 4.5V
0.4
0.9
+
V = 2.25V to 2.7V
69931234fc
3
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
Pulse Width Jitter (Note 10)
N
DIV
= 1
V = 5.5V
0.85
0.45
%
P-P
%
P-P
V = 2.25V
N
DIV
N
DIV
N
DIV
N
DIV
= 8
0.20
0.05
0.20
0.03
%
%
%
%
P-P
P-P
P-P
= 64
= 512
= 4096
P-P
t
Pulse Width Change Settling Time (Note 9)
t
= t /N
OUT DIV
6 • t
µs
S
MASTER
MASTER
Power Supply
+
l
l
V
Operating Supply Voltage Range
2.25
5.5
V
V
Power-On Reset Voltage
Supply Current (Idle)
1.95
+
+
l
l
I
R = ∞, R = 50k, N ≤ 64
V = 5.5V
165
125
200
160
µA
µA
S(IDLE)
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 50k, N ≥ 512 V = 5.5V
135
105
175
140
µA
µA
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 800k, N ≤ 64 V = 5.5V
70
60
110
95
µA
µA
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 800k, N ≥ 512 V = 5.5V
65
55
100
90
µA
µA
L
SET
DIV
V = 2.25V
Analog Inputs
Voltage at SET Pin
Drift Over Temperature
l
l
l
l
l
V
0.97
1.00
75
1.03
800
V
SET
∆V /∆T
V
µV/°C
kΩ
V
SET
SET
R
Frequency-Setting Resistor
DIV Pin Voltage
50
0
SET
DIV
+
V
V
+
∆V /∆V DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
DIV
1.5
%
DIV
+
V
/V = (DIVCODE + 0.5)/16
l
DIV Pin Input Current
Digital I/O
10
nA
TRIG Pin Input Capacitance
TRIG Pin Input Current
2.5
20
pF
nA
V
+
TRIG = 0V to V
(Note 6)
10
+
l
l
V
V
High Level TRIG Pin Input Voltage
Low Level TRIG Pin Input Voltage
Output Current
0.7 • V
IH
+
(Note 6)
+
0.3 • V
V
IL
I
V = 2.7V to 5.5V
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7)
V = 5.5V
I
I
= –1mA
= –16mA
5.45
4.84
5.48
5.15
V
V
OH
OUT
OUT
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
Low Level Output Voltage (Note 7)
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OL
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
69931234fc
4
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
t
Trigger Propagation Delay
V = 5.5V
11
17
28
ns
ns
ns
PD
+
V = 3.3V
+
V = 2.25V
+
t
t
t
Minimum Recognized TRIG Pulse Width
Recovery Time (LTC6993-1/LTC6993-3)
V = 3.3V
5
ns
ns
WIDTH
ARM
–4
+
Time Between Trigger Signals
(LTC6993-2/LTC6993-4)
N
DIV
N
DIV
= 1
> 1
V = 3.3V
10
50
ns
ns
RETRIG
+
V = 3.3V
+
t
t
Output Rise Time (Note 8)
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
r
f
+
V = 3.3V
+
V = 2.25V
+
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6993C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V . Typical values can
be estimated at any supply voltage using:
+
+
V
V
≈ 0.55 • V + 185mV and
TRIG(RISING)
+
≈ 0.48 • V – 155mV
TRIG(FALLING)
Note 7: To conform to the Logic IC Standard, current out of a pin is
Note 3: The LTC6993C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6993C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6993I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6993H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6993MP is
guaranteed to meet specified performance from –55°C to 125°C.
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within 1% of the final pulse width after a 0.5× or 2× change in I
Note 10: Jitter is the ratio of the deviation of the output pulse width to the
mean of the pulse width. This specification is based on characterization
and is not 100% tested.
.
SET
Note 4: Pulse width accuracy is defined as the deviation from the t
OUT
equation, assuming R is used to program the pulse width.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
69931234fc
5
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
tOUT Drift vs Temperature
(NDIV ≤ 64)
tOUT Drift vs Temperature
(NDIV ≤ 64)
t
OUT Drift vs Temperature
(NDIV ≤ 64)
1.5
1.0
0.5
0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
R
SET
= 800k
R
SET
= 50k
R
SET
= 200k
3 PARTS
3 PARTS
3 PARTS
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
69931234 G03
69931234 G01
69931234 G02
tOUT Drift vs Temperature
(NDIV ≥ 512)
tOUT Drift vs Temperature
(NDIV ≥ 512)
tOUT Drift vs Temperature
(NDIV ≥ 512)
1.5
1.0
0.5
0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
R
SET
= 800k
R
SET
= 200k
R
SET
= 50k
3 PARTS
3 PARTS
3 PARTS
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
69931234 G06
69931234 G05
69931234 G04
tOUT Drift vs Supply Voltage
(NDIV = 1, Rising Edge)
tOUT Drift vs Supply Voltage
(NDIV = 1, Falling Edge)
tOUT Drift vs Supply Voltage
(NDIV > 1)
1.0
0.8
1.0
0.8
1.0
0.8
+
LTC6993-1/LTC6993-2
DIVCODE = 0
REFERENCED TO V = 4V
LTC6993-3/LTC6993-4
REFERENCED TO V = 4V
DIVCODE = 0
+
+
REFERENCED TO V = 4V
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
R
R
R
= 50k
= 200k
= 800k
R
R
R
= 50k
= 200k
= 800k
R
SET
R
SET
R
SET
= 50k, N = 8
DIV
SET
SET
SET
SET
SET
SET
= 50k TO 800k, N ≥ 512
DIV
= 800k, N = 8
DIV
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
SUPPLY (V)
SUPPLY (V)
SUPPLY (V)
69931234 G07
69931234 G08
69931234 G09
69931234fc
6
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
t
OUT Error vs RSET
tOUT Error vs RSET
(8 ≤ NDIV ≤ 64)
tOUT Error vs RSET
(NDIV ≥ 512)
(NDIV = 1, Rising Edge)
5
4
5
5
4
3 PARTS
3 PARTS
LTC6993-1/LTC6993-2
DIVCODE = 0
3 PARTS
4
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
50
100
200
(kΩ)
400
800
50
100
200
(kΩ)
400
800
50
100
200
(kΩ)
400
800
R
R
SET
R
SET
SET
69931234 G11
69931234 G12
69931234 G10
tOUT Error vs RSET
tOUT Error vs DIVCODE
(Rising Edge)
tOUT Error vs DIVCODE
(Falling Edge)
(NDIV = 1, Falling Edge)
5
4
5
4
5
4
LTC6993-3/LTC6993-4
DIVCODE = 0
3 PARTS
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
R
= 50k
R
= 50k
SET
SET
3 PARTS
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
50
100
200
(kΩ)
400
800
R
DIVCODE
DIVCODE
SET
69931234 G13
69931234 G14
69931234 G15
VSET Drift vs ISET
VSET Drift vs Supply Voltage
VSET vs Temperature
1.0
0.8
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO I
= 10µA
REFERENCED TO V = 4V
SET
0
10
(µA)
15
20
2
4
5
6
5
3
–50
0
25
50
75 100 125
–25
I
SUPPLY (V)
TEMPERATURE (°C)
SET
69931234 G16
69931234 G17
69931234 G18
69931234fc
7
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Typical VSET Distribution
Supply Current vs Supply Voltage
Supply Current vs Temperature
250
200
150
100
50
300
250
250
200
150
100
50
2 LOTS
DFN AND SOT-23
1274 UNITS
“ACTIVE” = 50% TIMING DUTY CYCLE
“ACTIVE” = 50% TIMING DUTY CYCLE
R
SET
= 50k, ÷1, ACTIVE
R
= 50k
SET
÷1, ACTIVE
200
150
R
= 50k
SET
R
= 50k, ÷1, IDLE
SET
÷1, IDLE
R
SET
= 100k, ÷8, ACTIVE
R
SET
= 100k, ÷8, ACTIVE
100
50
0
R
SET
= 100k, ÷8, IDLE
R
= 100k, ÷8, IDLE
SET
R
SET
= 800k, ÷512
R
SET
= 800k, ÷512
C
R
= 5pF
= ∞
C
= 5pF
= ∞
LOAD
LOAD
LOAD
R
LOAD
0
0
0.98
0.996
V
1.004
(V)
1.012
1.02
0.988
2
3
4
5
6
–50 –25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SET
69931234 G19
69931234 G20
69931234 G21
Supply Current
vs TRIG Pin Voltage
Supply Current vs tOUT (5V)
Supply Current vs tOUT (2.5V)
250
200
150
100
50
250
200
150
100
50
250
200
150
100
50
ACTIVE CURRENT MEASURED
WITH TRIGGER PERIOD = 2 • t
(50% DUTY CYCLE)
ACTIVE CURRENT MEASURED
WITH TRIGGER PERIOD = 2 • t
(50% DUTY CYCLE)
OUT
OUT
5V
5V
TRIG FALLING
TRIG RISING
÷1
÷8
÷64
3.3V
TRIG RISING
3.3V
TRIG FALLING
÷1
÷512
÷8
÷64
÷512
+
+
V
C
R
= 5V
V
C
R
= 2.5V
C
R
= 5pF
= ∞
LOAD
LOAD
= 5pF
= ∞
= 5pF
= ∞
LOAD
LOAD
LOAD
ACTIVE
IDLE
LOAD
ACTIVE
IDLE
0
0
0
0
0.2
0.4
0.6
0.8
1.0
0.001
0.01
0.1
1
(ms)
10
100
0.001
0.01
0.1
1
10
100
+
V
/V (V/V)
t
t
(ms)
TRIG
OUT
OUT
69931234 G23
69931234 G24
69931234 G22
TRIG Threshold Voltage
vs Supply Voltage
Typical ISET Current Limit vs V+
Peak-to-Peak Jitter vs tOUT
1000
800
600
400
200
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.9
0.8
0.7
PEAK-TO-PEAK t
VARIATION
MEASURED OVER
30s INTERVALS
SET PIN SHORTED TO GND
OUT
÷1, 5.5V
POSITIVE GOING
0.6
0.5
NEGATIVE GOING
÷1, 2.25V
0.4
0.3
0.2
0.1
0
÷8, 5.5V
÷512
÷8, 2.25V
0.01
÷64
÷4096
2
3
4
5
6
2
3
4
5
6
0.001
0.1
1
10
100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
t
(ms)
OUT
69931234 G27
69931234 G25
69931234 G26
69931234fc
8
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Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Output Resistance vs Supply
Trigger Propagation Delay (tPD
)
Rise and Fall Time
vs Supply Voltage
Voltage
vs Supply Voltage
50
3.0
2.5
2.0
1.5
1.0
0.5
0
30
25
C
= 5pF
C
= 5pF
LOAD
LOAD
45
40
35
30
25
20
15
10
5
20
15
OUTPUT SOURCING CURRENT
t
RISE
t
FALL
10
5
OUTPUT SINKING CURRENT
0
0
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
69931234 G30
6990 G29
69931234 G28
69931234fc
9
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
pin FuncTions (DCB/S6)
V (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This
supply should be kept free from noise and ripple. It should
bebypasseddirectlytotheGNDpinwitha0.1µFcapacitor.
+
toleranceand50ppm/°Corbettertemperaturecoefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (V ) is internally converted
DIV
into a 4-bit result (DIVCODE). V may be generated by
DIV
+
regulating the V voltage.
a resistor divider between V and GND. Use 1% resistors
SET
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
TRIG (Pin 4/Pin 1): Trigger Input. Depending on the ver-
sion, a rising or falling edge on TRIG will initiate the output
pulse. LTC6993-1 and LTC6993-2 are rising-edge sensi-
tive.LTC6993-3andLTC6993-4arefalling-edgesensitive.
to less than 100pF so that V settles quickly. The MSB of
DIV
DIVCODE (POL) determines the polarity of the OUT pins.
When POL = 0 the output produces a positive pulse. When
POL = 1 the output produces a negative pulse.
TheLTC6993-2andLTC6993-4areretriggerable,allowing
thepulsewidthtobeextendedbyadditionaltriggersignals
that occur while the output is active. The LTC6993-1/
LTC6993-3 will ignore additional trigger inputs until the
output pulse has terminated.
SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
SET
amount of current sourced from the SET pin (I ) pro-
SET
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
plane for best performance.
grams the master oscillator frequency. The I
current
SET
range is 1.25µA to 20µA. The output pulse will continue
indefinitely if I drops below approximately 500nA,
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
SET
+
and will terminate when I
increases again. A resistor
GND to V with an output resistance of approximately
SET
connected between SET and GND is the most accurate
way to set the pulse width. For best performance, use
a precision metal or thin film resistor of 0.5% or better
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
+
V
TRIG
OUT
LTC6993
+
V
+
GND
SET
V
C1
0.1µF
R1
R2
DIV
69931234 PF
R
SET
69931234fc
10
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
block DiagraM (S6 package pin numbers shown)
5
+
V
R1
POL
DIV
4-BIT A/D
DIGITAL
FILTER
4
1
CONVERTER
R2
TRIGGER/
TRIG
RETRIGGER
LOGIC
S
OUTPUT
POLARITY
OUT
Q
6
MASTER OSCILLATOR
1µs
50kΩ
V
I
SET
SET
PROGRAMMABLE DIVIDER
t
=
•
t
OUT
MASTER
MCLK
R
÷1, 8, 64, 512, 4096,
15 18 21
2
, 2 , 2
POR
HALT OSCILLATOR
IF I
< 500nA
SET
I
SET
+
–
+
1V
V
= 1V
–
SET
SET
3
GND
2
69931234 BD
I
SET
R
SET
69931234fc
11
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
operaTion
The LTC6993 is built around a master oscillator with a 1µs
DIVCODE
minimum period. The oscillator is controlled by the SET
+
TheDIVpinconnectstoaninternal,V referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6993:
pin current (I ) and voltage (V ), with a 1µs/50kΩ
SET
SET
conversion factor that is accurate to 1.7% under typical
conditions.
1. DIVCODE determines the frequency divider setting,
1µs VSET
50kΩ ISET
N
DIV
.
tMASTER
=
•
2. DIVCODE determines the polarity of OUT pin, via the
POL bit.
A feedback loop maintains V
at 1V 30mV, leaving
SET
+
I
as the primary means of controlling the pulse width.
SET
V
may be generated by a resistor divider between V
DIV
The simplest way to generate I is to connect a resistor
SET
and GND as shown in Figure 1.
(R ) between SET and GND, such that I = V /R .
The master oscillator equation reduces to:
SET
SET
SET SET
2.25V TO 5.5V
+
V
RSET
50kΩ
R1
R2
LTC6993
tMASTER = 1µs •
DIV
From this equation, it is clear that V drift will not affect
SET
GND
the pulse width when using a single program resistor
69931234 F01
(R ). Error sources are limited to R
tolerance and
SET
SET
the inherent pulse width accuracy ∆t
of the LTC6993.
Figure 1. Simple Technique for Setting DIVCODE
OUT
R
may range from 50k to 800k (equivalent to I
SET
SET
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
between 1.25µA and 20µA).
A trigger signal (rising or falling edge on TRIG pin) latches
theoutputtotheactivestate,beginningtheoutputpulse.At
the same time, the master oscillator is enabled to time the
durationoftheoutputpulse. Whenthedesiredpulsewidth
is reached, the master oscillator resets the output latch.
correspondingN andPOLvaluesfortherecommended
DIV
resistor pairs. Other values may be used as long as:
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
tor tolerances and temperature effects).
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
If the voltage is generated by other means (i.e., the output
The LTC6993 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
15 18
21
+
512, 4096, 2 , 2 or 2 . This extends the pulse width
of a DAC) it must track the V supply voltage. The last
duration by those same factors. The divider ratio N is
column in Table 1 shows the ideal ratio of V
to the
DIV
DIV
set by a resistor divider attached to the DIV pin.
supply voltage, which can also be calculated as:
NDIV VSET
50kΩ ISET
VDIV DIVCODE+0.5
tOUT
=
•
•1µs
=
±1.5%
V+
16
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
With R in place of V /I the equation reduces to:
SET
SET SET
is 4, V = 0.281 • 3.3V = 928mV 50mV.
DIV
NDIV •RSET
50kΩ
tOUT
=
•1µs
Figure 2 illustrates the information in Table 1, showing
that N is symmetric around the DIVCODE midpoint.
DIV
69931234fc
12
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operaTion
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
Recommended t
1µs to 16µs
R1 (k)
Open
976
R2 (k)
Short
102
V
DIV
/V
DIV
OUT
0
1
1
≤ 0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥ 0.96875 0.015
0
8
8µs to 128µs
2
0
64
512
64µs to 1.024ms
512µs to 8.192ms
4.096ms to 65.54ms
32.77ms to 524.3ms
262.1ms to 4.194sec
2.097sec to 33.55sec
2.097sec to 33.55sec
262.1ms to 4.194sec
32.77ms to 524.3ms
4.096ms to 65.54ms
512µs to 8.192ms
64µs to 1.024ms
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
4,096
32,768
262,144
2,097,152
2,097,152
262,144
32,768
4,096
512
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
64
182
1
8
8µs to 128µs
102
976
1
1
1µs to 16µs
Short
Open
POL BIT = 0
POL BIT = 1
10000
1000
100
10
7
8
6
9
5
10
11
4
12
3
1
2
13
0.1
1
14
0.01
0.001
0
15
+
+
0V
0.5•V
V
INCREASING V
DIV
69931234 F02
Figure 2. Pulse Width Range and POL Bit vs DIVCODE
69931234fc
13
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
operaTion
Monostable Multivibrator (One Shot)
Negative Trigger Versions
The LTC6993 is a monostable multivibrator. A trigger
signal on the TRIG input will force the output to the active
(unstable) state for a programmable duration. This type
of circuit is commonly referred to as a one-shot pulse
generator.
Inadditiontotheretriggeroption, theLTC6993familyalso
includesnegativeinput(falling-edge)versions.Thesefour
combinations are detailed in Table 2.
Table 2. Retrigger and Input Polarity Options
DEVICE
INPUT POLARITY
Rising-Edge
Rising-Edge
Falling-Edge
Falling-Edge
RETRIGGER
LTC6993-1
LTC6993-2
LTC6993-3
LTC6993-4
No
Yes
No
Figures 3 details the basic operation. A rising edge on
the TRIG pin initiates the output pulse. The pulse width
(t ) is determined by the N setting and by the resis-
OUT
DIV
Yes
tor (R ) connected to the SET pin. Subsequent rising
SET
edges on TRIG have no affect until the completion of the
Output Polarity (POL Bit)
one shot and for a short rearming time (t ) thereafter.
ARM
Each variety of LTC6993 also offers the ability to invert
the output, producing negative pulses. This option is
To ensure proper operation, positive and negative TRIG
pulses should be at least t wide.
WIDTH
programmed, along with N , by the choice of DIVCODE.
DIV
The LTC6993-2 and LTC6993-4 allow the output pulse to
be “retriggered”. As shown in Figure 4, the output pulse
(TheprevioussectiondescribeshowtoprogramDIVCODE
using the DIV pin).
will stay high until t
after the last rising-edge on TRIG.
OUT
Successive trigger signals can extend the pulse width in-
definitely. Consecutive trigger signals must be separated
by t
to be recognized.
RETRIG
t
WIDTH
TRIG
OUT
t
PD
t
PD
t
ARM
69931234 F03
t
t
OUT
t
OUT
OUT
Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0)
t
t
WIDTH
RETRIG
TRIG
OUT
t
PD
t
PD
t
PD
t
PD
69931234 F04
t
t
t
OUT
OUT
OUT
Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0)
69931234fc
14
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
operaTion
Changing DIVCODE After Start-Up
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t . The OUT pin
Following start-up, the A/D converter will continue
monitoring V for changes. Changes to DIVCODE will
DIV
START
be recognized slowly, as the LTC6993 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
is held low during this time. The typical value for t
START
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N ):
DIV
t
= 500 • t
MASTER
START(TYP)
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before an output pulse can be
generated. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
t
= 16 • (∆DIVCODE + 6) • t
MASTER
DIVCODE
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the output pulse is active during the transition, the
pulse width can take on a value between the two settings.
+
pin so it will properly track V . Less than 100pF will not
extend the start-up time.
TheDIVCODEsettingisrecognizedattheendofthestartup
up. If POL = 1, the output will transition high. Otherwise
(if POL = 0) OUT simply remains low. At this point, the
LTC6993 is ready to respond to rising/falling edges on
the TRIG input.
DIV
500mV/DIV
512µs
TRIG
2V/DIV
4µs
OUT
2V/DIV
+
V
256µs
200µs/DIV
69931234 F05a
LTC6993-1
+
V
R
= 3.3V
= 200k
SET
TRIG
t
Figure 5a. DIVCODE Change from 0 to 2
START
POL = 0
(TRIG IGNORED)
OUT
POL = 1
69931234 F06
DIV
t
OUT
500mV/DIV
512µs
TRIG
2V/DIV
Figure 6. Start-Up Timing Diagram
4µs
OUT
2V/DIV
256µs
69931234 F05b
LTC6993-1
200µs/DIV
+
V
R
= 3.3V
= 200k
SET
Figure 5b. DIVCODE Change from 2 to 0
69931234fc
15
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
applicaTions inForMaTion
Basic Operation
Step 4: Calculate and Select R
.
SET
The simplest and most accurate method to program
The final step is to calculate the correct value for R
using the following equation:
SET
the LTC6993 is to use a single resistor, R , between
SET
the SET and GND pins. The design procedure is a four
step process. Alternatively, Linear Technology offers the
easy-to-use TimerBlox Designer tool to quickly design
any LTC6993 based circuit. Download the free TimerBlox
Designer software at www.linear.com/timerblox.
50k tOUT
1µs NDIV
RSET
=
•
(2)
Select the standard resistor value closest to the calculated
value.
Step 1: Select the POL Bit Setting.
Example: Design a one-shot circuit that satisfies the fol-
lowing requirements:
The LTC6993 can generate positive or negative output
pulses, depending on the setting of the POL bit. The POL
bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1
and produces active-low pulses.
• t
OUT
= 100µs
• Negative Output Pulse
• Rising-Edge Trigger Input
• Retriggerable Input
Step 2: Select LTC6993 Version.
• Minimum power consumption
Two input-related choices dictate the proper LTC6993 for
a given application:
Step 1: Select the POL Bit Setting.
• Is TRIG a rising or falling-edge input?
• Should retriggering be allowed?
For inverted (negative) output pulse, choose POL = 1.
Step 2: Select the LTC6993 Version.
Use Table 2 to select a particular variety of LTC6993.
A rising-edge retriggerable input requires the LTC6993-2.
Step 3: Select the N Frequency Divider Value.
DIV
Step 3: Select the N Frequency Divider Value.
DIV
As explained earlier, the voltage on the DIV pin sets the
Choose an N
value that meets the requirements of
DIVCODE which determines both the POL bit and the N
DIV
DIV
Equation (1), using t
= 100µs:
value. For a given output pulse width (t ), N should
OUT
OUT
DIV
be selected to be within the following range:
6.25 ≤ N ≤ 100
DIV
tOUT
16µs
tOUT
1µs
Potential settings for N include 8 and 64. N = 8 is
≤NDIV
≤
DIV
DIV
(1)
the best choice, as it minimizes supply current by us-
ing a large R resistor. POL = 1 and N = 8 requires
SET
DIV
To minimize supply current, choose the lowest N value.
DIV
DIVCODE = 14. Using Table 1, choose R1 = 102k and
R2 = 976k values to program DIVCODE = 14.
However,insomecasesahighervalueforN willprovide
DIV
better accuracy (see Electrical Characteristics).
Step 4: Select R
.
SET
Table 1 can also be used to select the appropriate N
DIV
values for the desired t
.
OUT
Calculate the correct value for R using Equation (2):
SET
With POL already chosen, this completes the selection of
50k 100µs
RSET
=
•
= 625k
DIVCODE. Use Table 1 to select the proper resistor divider
1µs
8
+
or V /V ratio to apply to the DIV pin.
DIV
69931234fc
16
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
applicaTions inForMaTion
Since 625k is not available as a standard 1% resistor,
TRIG
GND
SET
OUT
substitute 619k if a –0.97% shift in t
is acceptable.
OUT
+
LTC6993
V
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
+
V
C1
0.1µF
R1
R
MOD
The completed design is shown in Figure 7.
V
DIV
CTRL
R
SET
R2
69931234 F08
TRIG
GND
SET
OUT
LTC6993-2
2.25V TO 5.5V
Figure 8. Voltage-Controlled Pulse Width
+
V
0.1µF
R1
102k
Digital Pulse Width Control
DIVCODE = 14
DIV
R
SET
R2
976k
The control voltage can be generated by a DAC (digital-to-
analog converter), resulting in a digitally-controlled pulse
width. Many DACs allow for the use of an external refer-
625k
69931234 F07
Figure 7. 100µs Negative Pulse Generator
ence. If such a DAC is used to provide the V
voltage,
CTRL
the V dependency can be eliminated by buffering V
SET
SET
Voltage-Controlled Pulse Width
and using it as the DAC’s reference voltage, as shown in
With one additional resistor, the LTC6993 output pulse
widthcanbemanipulatedbyanexternalvoltage.Asshown
Figure 9. The DAC’s output voltage now tracks any V
SET
variation and eliminates it as an error source. The SET pin
cannot be tied directly to the reference input of the DAC
because the current drawn by the DAC’s REF input would
affect the pulse width.
in Figure 8, voltage V
sources/sinks a current through
CTRL
R
to vary the I
current, which in turn modulates
MOD
SET
the pulse width as described in Equation (3).
NDIV •RMOD
50kΩ
1µs
tOUT
=
•
(3)
RMOD VCTRL
1+
–
RSET
VSET
TRIG
GND
SET
OUT
+
LTC6993
V
+
+
V
V
0.1µF
C1
R1
0.1µF
DIV
+
–
1/2
LTC6078
R2
+
V
69931234 F09
0.1µF
N
• R
50kΩ
1µs
DIV
MOD
t
=
•
OUT
R
R
D
4096
MOD
IN
1+
–
V
REF
CC
SET
D
IN
D
IN
= 0 TO 4095
R
MOD
V
OUT
CLK
µP
LTC1659
CS/LD
R
SET
GND
Figure 9. Digitally Controlled Pulse Width
69931234fc
17
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
applicaTions inForMaTion
I
Extremes (Master Oscillator Frequency Extremes)
Coupling Error
SET
When operating with I
outside of the recommended
The current sourced by the SET pin is used to bias the in-
ternalmasteroscillator.TheLTC6993respondstochanges
SET
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
in I
almost immediately, which provides excellent
SET
settling time. However, this fast response also makes the
SET pin sensitive to coupling from digital signals, such
as the TRIG input.
The oscillator will still function with reduced accuracy for
I
< 1.25µA. At approximately 500nA, the oscillator will
SET
stop. Under this condition, the output pulse can still be
Even an excellent layout will allow some coupling between
initiated, but will not terminate until I
the master oscillator starts again.
increases and
TRIG and SET. Additional error is included in the speci-
SET
fied accuracy for N = 1 to account for this. Figure 11
DIV
shows that ÷1 supply variation is dependent on coupling
from rising or falling trigger inputs and, to a lesser extent,
output polarity.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
TRIG (or any other fast-edge, wide-swing signal).
Settling Time
Following a 2× or 0.5× step change in I , the output
pulse width takes approximately six master clock cycles
SET
(6 • t
) to settle to within 1% of the final value. An
1.0
0.8
MASTER
exampleisshowninFigure10,usingthecircuitinFigure 8.
0.6
LTC6993-1
POL = 1
0.4
0.2
LTC6993-1
POL = 0
V
CTRL
2V/DIV
0
TRIG
5V/DIV
OUT
–0.2
–0.4
–0.6
–0.8
–1.0
LTC6993-3
POL = 0
5V/DIV
LTC6993-3
POL = 1
PULSE WIDTH
2µs/DIV
R
N
= 50k
= 1
SET
DIV
69931234 F10
LTC6993-1
20µs/DIV
2
3
4
5
6
+
V
= 3.3V
SUPPLY (V)
DIVCODE = 0
R
R
t
= 200k
MOD
= 3µs AND 6µs
69931234 F11
SET
= 464k
Figure 11. tOUT Drift vs Supply Voltage
OUT
Figure 10. Typical Settling Time
69931234fc
18
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
applicaTions inForMaTion
Power Supply Current
250
+
V
= 3.3V
DUTY CYCLE = f • t
IN OUT
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting to be triggered).
200
150
100
50
÷1, R
= 50k
SET
÷8, R
= 50k
SET
I
varies with the programmed t
and the supply
S(IDLE)
OUT
voltage. Once triggered, the instantaneous supply current
increases to I while the timing circuit is active.
÷1, R
÷1, R
= 100k
= 800k
SET
SET
S(ACTIVE)
I
= I
+ ∆I
S(IDLE) S(ACTIVE)
S(ACTIVE)
C
= 5pF
The average increase in supply current ∆I
pends on the output duty cycle (or negative duty cycle,
if POL = 1), since that represents the percentage of time
de-
LOAD
LOAD
S(ACTIVE)
R
= ∞
0
IDLE
20
40
60
80
100
DUTY CYCLE (%)
that the circuit is active. I
and ∆I
can be
69931234 F12
S(IDLE)
S(ACTIVE)
estimated using the equations in Table 2.
Figure 12. IS(ACTIVE) vs Output Duty Cycle
Figure 12 shows how the supply current increases from
I
as the input frequency increases. The increase is
S(IDLE)
smaller at higher N settings.
DIV
Table 2. Typical Supply Current
CONDITION
TYPICAL I
TYPICAL ∆I
*
S(IDLE)
S(ACTIVE)
V+ • N • 7pF+4pF
V+
500kΩ
Duty Cycle
tOUT
V+ •
• N • 5pF +18pF +CLO
(
DIV
(
)
DIV
N
DIV
≤ 64
+
+2.2 •ISET +50
tOUT
V+ •NDIV • 7pF
V+
500kΩ
Duty Cycle
tOUT
V+ •
•CLOA
N
DIV
≥ 512
+
+1.8 •ISET +50
tOUT
*Ignoring resistive loads (assumes R
= ∞)
LOAD
69931234fc
19
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
applicaTions inForMaTion
Supply Bypassing and PCB Layout Guidelines
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
TheLTC6993isanaccuratemonostablemultivibratorwhen
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place R
as close as possible to the SET pin and
SET
Figure13showsexamplePCBlayoutsforboththeSOT-23
andDCBpackagesusing0603sizedpassivecomponents.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6993. These layouts are
a guide and need not be followed exactly.
make a direct, short connection. The SET pin is a cur-
rent summing node and currents injected into this pin
directlymodulatetheoutputpulsewidth.Havingashort
connection minimizes the exposure to signal pickup.
4. Connect R directly to the GND pin. Using a long path
SET
+
1. Connect the bypass capacitor, C1, directly to the V and
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
GND pins using a low inductance path. The connection
+
from C1 to the V pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
TRIG
GND
SET
OUT
LTC6993
+
+
V
V
C1
0.1µF
R1
R2
DIV
R
SET
+
+
V
+
C1
V
R1
C1
V
OUT
GND
TRIG
TRIG
OUT
+
DIV
SET
GND
SET
V
R2
DIV
R1
R
SET
R
SET
R2
69931234 F13
DCB PACKAGE
TSOT-23 PACKAGE
Figure 13. Supply Bypassing and PCB Layout
69931234fc
20
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical applicaTions
Missing Pulse Detector
25kHz INPUT
64µs
TRIG
GND
SET
OUT
TRIG
LTC6993-2
3.3V
2V/DIV
0.1µF
+
V
R1
102k
OUT
2V/DIV
DIV
R
SET
R2
402k
DIVCODE = 14
(N = 8, POL = 1)
69931234 TA02b
976k
50µs/DIV
DIV
69931234 TA02a
Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within t
= 64µs.
OUT
1.5ms Radio Control Servo Reference Pulse Generator
5V
20ms
FRAME RATE
GENERATOR
1.5ms
REFERENCE
PULSE
R7
10k
20ms PERIOD
RESET = OPEN
RUN = GND (CLOSED)
RST
GND
SET
OUT
TRIG
OUT
1.5ms PULSE
C2
LTC6991
LTC6993-1
5V
5V
+
+
V
GND
SET
V
C1
0.01µF
R4
976k
R1
0.01µF
1M
DIV
DIV
R8
143k
R3
121k
R5
102k
R2
280k
R6
10k
69931234 TA03
1.5ms CAL TRIM
Pulse Delay Generator
100µs
DELAY
GENERATOR
10µs
OUTPUT PULSE
GENERATOR
PULSE IN
TRIG
GND
SET
OUT
TRIG
GND
SET
OUT
OUT
LTC6993-1
LTC6993-1
5V
5V
+
+
V
V
C1
0.01µF
C2
0.1µF
R4
182k
R1
976k
DIV
DIV
R6
78.7k
R3
61.9k
R5
976k
R2
102k
10µs PULSE IN
100µs DELAY
10µs PULSE OUT
69931234fc
21
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical applicaTions
RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval
1.5ms
PULSE
GENERATOR
R9
10k
TRIG
OUT
PULSE OUT
TRIGGER
LTC6993-1
5V
+
GND
SET
V
C2
0.1µF
R1
1M
M1
2N7002
DIV
TRIGGER PULSE IN
R3
R2
280k
147k
1.5ms PULSE OUT
20ms
RETRIGGER
LOCKOUT INTERVAL
20ms RETRIGGER LOCKOUT
RETRIGGER LOCKOUT TIME
OUT
TRIG
GND
SET
R5
100k
LTC6993-1
+
5V
V
0.1µF
R6
1M
DIV
R4
243k
R7
392k
69931234 TA05
Staircase Generator with Reset
R8
4.99k
R7
10k
PULSE FREQUENCY-TO-VOLTAGE CONVERTER
5V
0.1µF
5V
0.1µF
–
STAIRCASE
OUT
–
D1
1N4148
U3
LT1490
R11
2k
V
OUT
+
U2
R10
10k
LT1490
C1
1µF
+
PULSES IN
R6
20k
R9
100k
U4
2N7002
RESET
RESET
RETRIGGERABLE
STAIRCASE RESET
PULSE GENERATOR
RAMP
STAIRCASE RESET
TRIG
GND
SET
OUT
STAIRCASE OUT
PULSES IN
C2
0.1µF
RESETS AFTER 1.5ms IF NO PULSES APPLIED
LTC6993-2
5V
+
69931234 TA06
V
R1
280k
DIV
R3
147k
R2
1M
69931234fc
22
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical applicaTions
Pulse Stretcher
5V
R4
4.99k
VOLTAGE VARIABLE
OUTPUT PULSE WIDTH
R1
10k
U2
Q4
2N2219A
LT1009
2.5V
PULSE OUT
STRETCHED
PULSE OUT
TRIG
GND
SET
OUT
LTC6993-3
5V
0.1µF
+
5V
V
C4
0.1µF
R14
976k
–
R16
140k
Q1
2N2907
Q2
2N2907
U4
LT1638
DIV
RAMP
Q3
R15
102k
+
R13
113k
R6
C1
10k 2200pF
2N2219A
R7
10k
RAMP VOLTAGE PROPORTIONAL
TO INPUT PULSE WIDTH
PULSE IN
TRIG
GND
SET
OUT
500µs RAMP RESET TIMER
1µs TO 10µs INPUT
PULSE WIDTH
LTC6993-1
5V
+
V
C2
0.1µF
R2
182k
DIV
R3
392k
R5
976k
69931234 TA07
69931234fc
23
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical applicaTions
On-Time Programmable Pulsed Solenoid Driver
Safety Time-Out Relay Driver
24V
12V
TIMED (5s) TURN-OFF AFTER
L
LOSS OF INPUT PULSES
100mA
C
1
5 SECONDS ON
RUN
D1
D1
SOLENOID
NO
1N4004
1N4148
DANFOSS 042 N024D
TYPE AK024D
RESET
OUT
TRIGGER IN
OFF
R4
2k
R4
10k
COTO 1022 RELAY
9001-12-01
Q1
2N2219A
Q1
2N2219A
TRIGGER
TRIG
OUT
ENABLE PULSES
TRIG
GND
SET
LTC6993-1
LTC6993-2
5V
5V
+
+
GND
V
V
C2
0.1µF
C2
R1
1M
R1
1M
0.1µF
SET
DIV
DIV
R3
118k
R3
118k
R2
887k
R2
887k
69931234 TA08
69931234 TA09
69931234fc
24
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6993#packaging for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 0.05
ꢀ.65 0.05
3.55 0.05
(2 SIDES)
2.ꢀ5 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
ꢀ.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.ꢀꢀ5
2.00 0.ꢀ0
(2 SIDES)
0.40 0.ꢀ0
TYP
R = 0.05
TYP
4
6
3.00 0.ꢀ0 ꢀ.65 0.ꢀ0
(2 SIDES)
(2 SIDES)
PIN ꢀ BAR
TOP MARK
(SEE NOTE 6)
PIN ꢀ NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
ꢀ
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
ꢀ.35 0.ꢀ0
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
ꢀ. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
69931234fc
25
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6993#packaging for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
69931234fc
26
For more information www.linear.com/LTC6993-1
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
1 to 3
A
7/11
Revised Description section
Added text to Basic Operation paragraph in Applications Information section
Added MP-grade
15
B
C
1/12
1, 2, 3, 5
11/15 Web Links Added
Conditions for VOH Specification from V = 5.5V, I
All
+
+
= –16mA, changed to V = 3.3V, I
= –10mA
OUT
4
6
OUT
Correction to graph “t
vs Supply Voltage (N –1, Rising Edge)”. Curves were offset low, and corrected upward.
DIV
OUT
Correction to circuit “Safety Time-Out Relay Driver”, R4 changed from 15k to 10k.
23
69931234fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
27
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
Typical applicaTion
Consecutive Test Sequencer
START
TEST
2s TO 30s
DELAY
DELAY
5V
TEST 1
TEST 2
5V
TEST 3
SEQUENCE
TRIG OUT
TRIG OUT
TRIG OUT
LTC6993-3
TRIG OUT
LTC6994-1
+
LTC6993-1
+
LTC6993-3
+
0.1µF
0.1µF
5V
5V
5V
30s
+
GND
SET
V
GND
SET
V
GND
SET
V
GND
SET
V
R9
274k
R10
25k
DELAY
ADJUST
0.1µF
0.1µF
R2
1000k
R5
DIV
DIV
DIV
DIV
1000k
2s
R1
63.4k
R3
887k
R6
191k
R7
191k
R8
191k
R4
681k
69931234 TA10
SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS
START
TEST 1
DELAY
TEST 2
TEST 3
ONE SECOND DURATION SEQUENTIAL TEST PULSES
AFTER AN ADJUSTABLE DELAY TIME
relaTeD parTs
PART NUMBER
LTC1799
DESCRIPTION
COMMENTS
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
Wide Frequency Range
Low Power, Wide Frequency Range
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
Micropower, I
= 35µA at 400kHz
SUPPLY
LTC6930
LTC6990
LTC6991
LTC6992
LTC6994
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox: Voltage-Controlled Silicon Oscillator
TimerBlox: Resettable Low Frequency Oscillator
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Fixed-Frequency or Voltage-Controlled Operation
Clock Periods up to 9.5 hours
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
TimerBlox: Delay Block/Debouncer
Simple PWM with Wide Frequency Range
Delay Rising Edge, Falling Edge or Both Edges
69931234fc
LT 1115 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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LINEAR TECHNOLOGY CORPORATION 2010
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC6993-1
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