EVM-915-250-CFS_技术文档

Warning: Linx radio frequency ("RF") products may be

!

Table of Contents

used to control machinery or devices remotely, including machinery

or devices that can cause death, bodily injuries, and/or property

damage if improperly or inadvertently triggered, particularly in industrial

settings or other applications implicating life-safety concerns. No Linx

Technologies product is intended for use in any application without

redundancies where the safety of life or property is at risk.

1 Description

2 Ordering Information

2 Absolute Maximum Ratings

3 Electrical Speciﬁcations

4 Pin Assignments

5 Pin Descriptions

6 Theory of Operation

7 Module Description

8 Module Operation

The customers and users of devices and machinery controlled with

RF products must understand and must use all appropriate safety

procedures in connection with the devices, including without limitation,

using appropriate safety procedures to prevent inadvertent triggering by

the user of the device and using appropriate security codes to prevent

triggering of the remote controlled machine or device by users of other

remote controllers.

10 Low-Power States

12 Reset to Factory Default

12 Compatibility Mode

12 Automatic Gain Control and Manual Gain Control

12 Exception Engine

Do not use this or any Linx product to trigger an action directly

from the data line or RSSI lines without a protocol or encoder/

decoder to validate the data. Without validation, any signal from

another unrelated transmitter in the environment received by the module

could inadvertently trigger the action.

14 Networking Modes

20 Extended Preamble

All RF products are susceptible to RF interference that can prevent

communication. RF products without frequency agility or hopping

implemented are more subject to interference. This module does have

a frequency hopping protocol built in, but the developer should still be

aware of the risk of interference.

22 Voltage Supply Rise Time

22 Using the Buffer Empty (BE) Line

22 Using the Exception (EX) Line

22 Using the Processing Incoming Packet (PR_PKT) Line

23 Receive Signal Strength Indication (RSSI)

24 Using the RESET Line

26 Using the Command Response (CMD_RSP) Line

27 The CMD Line

28 The UART Interface

Do not use any Linx product over the limits in this data guide.

Excessive voltage or extended operation at the maximum voltage could

cause product failure. Exceeding the reﬂow temperature proﬁle could

cause product failure which is not immediately evident.

Do not make any physical or electrical modiﬁcations to any Linx

product. This will void the warranty and regulatory and UL certiﬁcations

and may cause product failure which is not immediately evident.

28 Conﬁguration Command Formatting

30 Module Conﬁguration

34 Writing to Registers

34 Reading from Registers

35 Conﬁguration Registers

58 Typical Applications

TRM-915-R250

58 Power Supply Requirements

59 Antenna Considerations

59 Helpful Application Notes from Linx

60 Interference Considerations

61 Microstrip Details

RF Transceiver Module

Data Guide

Description

1.200”

(30.48mm)

The 250 Series RF transceiver module is

designed for reliable bi-directional transfer

of serial data over distances of up to 4 miles

(6.4km) line of sight. Operating in the 902 to

928MHz frequency band, the module is capable

of generating +23.5dBm into a 50-ohm load

and achieves an outstanding typical sensitivity

of –105dBm. This high output power gives

the module exceptional range and also helps

overcome noisy environments at shorter ranges.

62 Pad Layout

1.200”

(30.48mm)

62 Board Layout Guidelines

64 Production Guidelines

64 Hand Assembly

64 Automated Assembly

66 General Antenna Rules

68 Common Antenna Styles

70 Regulatory Considerations

0.170”

(4.32mm)

Figure 1: Package Dimensions

The module implements a Frequency Hopping Spread Spectrum (FHSS)

protocol along with networking and assured delivery features. It has a

Universal Asynchronous Receiver Transmitter (UART) serial interface that

can be directly connected to microcontrollers, RS-232 converters or USB

adaptors. The module automatically handles all radio functions resulting

in a UART-to-antenna wireless link. All conﬁguration settings and data are

accessed through the UART interface.

Features

•ꢀ True UART to antenna solution

•ꢀ Frequency Hopping (FHSS)

•ꢀ 153.6kbps max RF data rate

•ꢀ Low Power Standby, Sleep and

Deep Sleep modes

•ꢀ Adjustable output power

•ꢀ Includes robust protocol (CSMA, •ꢀ 32-bit unique address

assured delivery, addressing)

•ꢀ 5 volt tolerant I/O

Applications

•ꢀ Direct RS-232/422/485 Wire

replacement

•ꢀ Remote data logging

•ꢀ Fleet management

•ꢀ Asset tracking

•ꢀ Trafﬁc and display signs

•ꢀ Mass-transit communications

•ꢀ Oil and gas sensing

•ꢀ Automated meter reading

•ꢀ Industrial/home automation

•ꢀ Wireless sensors

A large-print version of this document is available at

www.linxtechnologies.com.

•ꢀ Long-range data links

–

1

Revised 3/18/2015

Ordering Information

Electrical Speciﬁcations

Ordering Information

250 Series Transceiver Speciﬁcations

Product Part No.

Description

Radiotronix Part No.

Parameter

Symbol

Min.

Typ.

Max.

Units Notes

Embedded Wireless

Module, 250mW (900MHz)

Power Supply

TRM-915-R250

Wi.232FHSS-250-R

Operating Voltage

TX Supply Current

@+8dBm

V_CC

2.7

3.3

3.6

VDC

1,2

Embedded Wireless

l_CCTX

TRM-915-R250-CFT Module, 250mW

(900MHz), Mexico

Wi.232-FHSS-250-CFTC-R

54

71

mA

Pinned, Pre-Certiﬁed

EVM-915-250-FCx

Wi.232FHSS-250-FCC-xx-R

Wi.232FHSS-250-FCC-CFTC-xx-R

@+13dBm

Module, 250mW (900MHz)

@+18dBm

109

190

25

Pinned, Pre-Certiﬁed

Module, 250mW

(900MHz), Mexico

EVM-915-250-CFx

@+23.5dBm

RX Supply Current

Standby Current

Sleep Current

l_CCRX

l_STD

mA

µA

1

x = ‘R’ for right angle connector, ‘S’ for straight connector

Transceivers are supplied in trays of 50 pieces

1.5

3

l_SLP

Figure 2: Ordering Information

Deep Sleep Current

RF Section

I_DSLP

Absolute Maximum Ratings

Operating Frequency Band

Center Frequency Accuracy

Number of Channels

Channel Spacing

Hop Sequences

Max Data Rate

Antenna Port

F_C

902.2

927.8

4

MHz

PPM

Chan.

kHz

2

32

750

6

3

4

Absolute Maximum Ratings

Supply Voltage V_cc

0

to

4.2

5.0

1

VDC

ms

Any Input or Output Pin

Max Supply Voltage Rise Time (GND to 2.7V)

Max RF Input

115.2

-40

kbps

Ω

12

to

dBm

ºC

Operating Temperature

Storage Temperature

–40

+85

RF Impedance

R_{I N}

50

to

ºC

Environmental

Exceeding any of the limits of this section may lead to permanent damage to the device.

Furthermore, extended operation at these maximum ratings may reduce the life of this

device.

Operating Temp. Range

Receiver Section

Receiver Sensitivity

9.6kbps

+85

ºC

5

Figure 3: Absolute Maximum Ratings

–105

–102

–100

–24

dBm

dBc

38.4kbps

153.6kbps

Warning: This product incorporates numerous static-sensitive

components. Always wear an ESD wrist strap and observe proper ESD

handling procedures when working with this device. Failure to observe

this precaution may result in module damage or failure.

Input IP3

6

7

Adjacent Channel Rejection

IF Bandwidth

60

200

kHz

Transmitter Section

Max Output Power

Harmonic Emissions

Frequency Deviation

P_O

P_H

23.5

–50

50

24

dBm

dBc

kHz

2

F_DEV

–

3

2

Pin Descriptions

250 Series Transceiver Speciﬁcations

Parameter

Symbol

Min.

Typ.

Max.

Units Notes

Pin Descriptions

Interface Section

Input Logic Low

Input Logic High

Output Logic Low

I_OL= 8.5mA

Pin Number

Name

I/O Description

V_{I L}

V_{I H}

V_OL

0

0.8

V_CC

VDC

Processing Packet Indicator. This line goes

high when the module is processing a valid

or potentially valid packet.

1

2

PR_PKT

O

2.0

UART Transmit Data Output. This is the

output line for the conﬁguration command

responses as well as the data received over

the air.

0.6

0.1

VDC

TXD

NC

O

I_OL= 10µA

3, 4, 5, 8, 17,

18

No Electrical Connection. Do not connect

any traces to these lines.

I_OL= 25mA

1.0

—

Output Logic High

I_OH= -3mA

V_OH

Reset line. This line is normally an input that

acts as an active low hardware reset line.

It does occasionally act as an output, so

please see the Reset section for details.

V_CC–0.7

V_CC–0.1

VDC

6

7

9

RESET

C2D

I/O

—

O

I_OH= -10µA

I_OH= -10mA

V_CC-0.8

Reserved

Flash Speciﬁcations (Non-Volatile Registers)

Flash Write Duration

Command Response. This line is low when

the data on the TXD line is a response to a

command and not data received over the

air.

16

ms

CMD_RSP

Flash Write Cycles

20k

100k

cycles

Exception Output. A mask can be set

to take this line high when an exception

occurs. The line is lowered when the

exception register is read (regEXCEPTION)

1. V_CC= 3.3V

2. Into a 50-ohm load

3. At 25ºC

7. Desired signal 3dB above input

sensitivity level, CW interferer power

level increased until BER = 10^-2,

+/–1MHz

10

EX

O

4. 26 channels each

11, 12, 13, 23

14

GND

RSSI

—

O

Ground

5. At 10^-3BER

6. P_in= -20dBm, 2 CW interferers, F_RF

915MHz, F₁= F_RF+ 3MHz, F₂= F_RF

6MHz, max gain, high-sensitivity

=

+

This line outputs an analog voltage that is

proportional to the strength of the incoming

signal.

Command Input. This line sets the serial

data as either command data to conﬁgure

the module or packet data to be sent over

the air. Pull low for command data; pull high

for packet data.

Figure 4: Electrical Speciﬁcations

15

CMD

I

Pin Assignments

26

25

24

Buffer Empty. This line goes high when the

UART input buffer is empty, indicating that

all data has been transmitted.

16

19

20

BE

O

I

1

2

PR_PKT

TXD

GND

ANT

GND

RXD

CTS

NC

23

22

21

20

19

18

17

16

15

14

UART Clear To Send, active low. This line

indicates to the host microcontroller when

the module is ready to accept data. When

CTS is high, the module is busy. When CTS

is low, the module is ready for data.

3

NC

CTS

RXD

4

NC

5

NC

6

RESET

C2D

UART Receive Data Input. This is the input

line for the conﬁguration commands as well

as data to be sent over the air.

7

NC

8

NC

BE

22

ANT

VCC

—

50-ohm RF Antenna Port

Supply Voltage

9

CMD_RSP

EX

CMD

RSSI

24, 25, 26

10

11

12

13

Figure 6: 250 Series Transceiver Pin Descriptions

Figure 5: 250 Series Transceiver Pin Assignments (Top View)

–

5

4

Theory of Operation

Module Description

The 250 Series transceiver is a low-cost, high-performance synthesized

FSK transceiver. Its wideband operation gives it outstanding range while

still meeting regulatory requirements. Figure 7 shows a block diagram for

The 250 Series RF transceiver module has a Universal Asynchronous

Receiver Transmitter (UART) serial interface and is designed to create

a complete UART-to-antenna wireless solution capable of direct wire

replacement in most embedded RS-232/422/485 applications.

the module.

TEMP

OFFSET

SENSOR

CORRECTION

Note: Although the module is capable of supporting the serial data

communications required by RS-232, RS-422, and RS-485 networks,

it is not compatible with the electrical interfaces for these types of

networks. The module has CMOS inputs and outputs and requires an

appropriate converter for the particular type of network being used.

LNA

FSK/ASK

DATA

MUX

DEMODULATOR

SYNCHRONIZER

FILTER

SWITCH

FILTER

7-BIT ADC

IF FILTER

RSSI

GAIN

OFFSET

CORRECTION

ANTENNA

AGC

CONTROL

Tx/Rx

CONTROL

FSK MOD

CONTROL

GAUSSIAN

FILTER

Σ-Δ

MODULATOR

AFC

CONTROL

UART /

INTERFACE

PROCESSOR

DIVIDERS/

MUXING

DIV P

N/N + 1

PA

FILTER

The module is designed to interface directly to a host UART. Three lines are

used to transfer data between the module and the host UART: TXD, RXD,

and CTS. TXD is the data output from the module. RXD is the data input

to the module. The CTS output indicates if the module is ready to accept

data. The UART interface is capable of operating in full duplex at baud

rates from 2.4 to 115.2kbps.

SERIAL

PORT

VCO

FILTER

CP

PFD

CLK

DIV

DIV R

OSC

Figure 7: 250 Series Transceiver Block Diagram

The 250 Series transceiver is designed for operation in the 902 to 928MHz

frequency band. The RF synthesizer contains a VCO and a low-noise

fractional-N PLL. The receive and transmit synthesizers are integrated,

enabling them to be automatically conﬁgured to achieve optimum phase

noise, modulation quality and settling time.

The module has a built-in protocol that automatically transmits the data

input on the UART. All encoding, transmitting, receiving and decoding

functions are handled by the internal processor, so no overhead is required

by an external processor. The networking modes in the protocol allow

for point-to-point and broadcast transmissions as well as allowing for the

creation of subnets and more complicated network topologies.

The transmitter output power is programmable from +8dBm to +23.5dBm

with automatic PA ramping to meet transient spurious speciﬁcations.

The ramping and frequency deviation are optimized to deliver the highest

performance over a wide range of data rates.

The module can be put into a Sleep mode through serial commands. In

Sleep mode, the RF section is completely shut down and the protocol

processor is in an idle state. Once the module has been placed in the sleep

mode, it can be awakened by sending a power-up sequence through the

serial port.

The receiver incorporates highly efﬁcient low-noise ampliﬁers that provide

up to –105dBm sensitivity.

An onboard controller performs the radio control and management

functions. A processor performs the higher level protocol functions and

controls the serial and hardware interfaces.

If the current draw in sleep mode is too high for a particular application,

power to the module can be switched through an external FET to turn off

the module when it is not needed. If this technique is used, the volatile

registers are reset to the values in their non-volatile mirrors, so any changes

from the default will have to be reloaded.

Every module has a 32-bit GUID address that can be used by the host

application to uniquely identify each module. This address can be read

through the serial interface.

–

7

6

If acknowledgements are enabled for assured delivery, then once the

packet is sent the module looks for an ACK from the other side. If the

ACK is not received, a retry is performed and the transmission is sent

again. If the number of transmission retries exceeds the value in the

regMAXTXRETRY register, an exception (EX_NORFACK) is raised.

Module Operation

The module employs a Frequency Hopping Spread Spectrum (FHSS)

algorithm. It has 32 channels spaced on 750kHz boundaries with a guard

band on either side. These channels are pseudo-randomly arranged into

six unique hopping tables comprised of 26 channels. The order of these

tables is chosen so that cross-correlation is minimized, allowing multiple

networks to operate in proximity with minimal interference.

Once the packet is sent, the transmitter deactivates but remains tuned to

the current channel until its hop time expires. If another packet is queued

for transmission, the module transmits this packet once the CSMA

mechanism allows access to the channel. Once the hop timer expires, the

module hops to the next channel.

When the module is not actively transmitting or receiving packets, it is in a

scan state. It cycles through the channels in the hop sequence looking for

a synchronizing packet. If it detects a preamble, it pauses to wait for the

start code and packet header. If the packet is addressed to it, the module

processes the packet and outputs the payload on the UART. If the packet

is not addressed to the module or the start code and header fail their

checks, the module resumes scanning for another packet.

Synchronization is lost whenever there is no more data to transfer and the

module has detected two consecutive hop indices without data present.

The module then returns to scan mode.

If another unit is transmitting when the module is ready to transmit a

packet, the module receives that data before attempting to transmit its

data. If the UART receive buffer gets full, the CTS line goes high to prevent

the host UART from over-running the receive buffer.

When data is input on the RXD line for transmission, the module ﬁlls

a buffer. Once the UART has buffered enough data to send (either

regUARTMTU bytes input or regTXTO has expired between bytes on the

RXD line), it transmits the data. The protocol engine makes a best-effort

attempt to keep the data in at least regUARTMTU-sized packets, but splits

the data based on the remaining dwell time before hopping. New data is

not sent within the last 5% of the hop sequence, but data which is already

in the process of being sent is processed normally.

The CSMA mechanism introduces a variable delay to the transmission if

it detects that the channel is occupied. This delay is the sum of a random

period and a weighted period that is dependent on the number of times

that the module has tried and failed to access the channel. For applications

that guarantee that only one module is transmitting at any given time, the

CSMA mechanism can be turned off to avoid this delay.

The module preﬁxes the data with a packet header and postﬁxes the data

with a 16-bit CRC. The 16-bit CRC error checking can be disabled to allow

the host application to do its own error checking.

Initially, the transmission of the packet begins on a random hop index within

the current hop sequence, and follows the hop sequence thereafter until

synchronization is lost. The module uses a Carrier-Sense-Multiple-Access

(CSMA) protocol to determine if another module is already transmitting on

the selected channel. If the channel is occupied then the module waits for it

to clear before transmitting its data.

Once the module gains access to the channel, if it is not already

synchronized, it assigns itself master status, and sends a synchronizing

preamble. Following a hop, the module that sends the ﬁrst transmission

assigns itself master status, sends a synchronizing preamble, and

communications resume.

–

9

8

Standby

Low-Power States

Standby is selected by writing a 0x02 to regOPMODE. In this mode,

the internal oscillator of the module’s protocol controller is lowered to its

slowest setting. The transmitter and receiver hardware is in power-down,

but the radio’s oscillator is enabled and running. The module wakes from

standby in less than 6ms. A low pulse on the RXD line wakes the module.

This pulse should be at least 1 bit-time in duration, so sending any byte to

the UART wakes it with the low start bit. Because the module’s oscillator

is not capable at running at ultra-low speeds, use of this mode is not

recommended for new applications. The RAM contents are preserved

during standby. If the RAM fails an integrity check, the module issues itself

a software reset to force re-initialization.

The module supports three power saving modes: Standby, Sleep and Deep

Sleep. Standby and Sleep are included primarily for legacy compatibility

with DTS and EUR Series modules. The hardware required to support

these two low-power modes fully is not present in the 25 Series modules.

As a result, the current consumption in these two modes is considerably

higher than their DTS / EUR counterparts. It is recommended that

applications utilize the Deep Sleep mode for power savings.

In the Sleep and Deep Sleep modes, the transceiver is powered down

and does not synchronize with other modules. Sleep mode draws more

current than Deep Sleep mode. In Deep Sleep mode the module draws the

least current. To wake the module up from this mode the RESET line must

be held low for at least 20µs and then taken high. The module does not

monitor the receive channel in either mode. Therefore, a sleeping module

cannot be woken through the RF interface.

Sleep

Sleep is selected by writing a 0x01 to regOPMODE. The internal oscillator

of the module’s protocol controller is lowered to its slowest setting, and

all radio services are stopped (receiver, transmitter, oscillator, etc.). The

module wakes from sleep in less than 6ms. A low pulse on the RXD line

wakes the module. This pulse should be at least 1 bit-time in duration, so

sending any byte to the UART wakes it with the low start bit. Because the

module’s oscillator is not capable at running at ultra-low speeds, use of

this mode is not recommended for new applications. The RAM contents

are preserved during sleep. If the RAM fails an integrity check, the module

issues itself a software reset to force re-initialization.

If regACKONWAKE is enabled, the module transmits a 0x06 character on

the TXD line once awakened from a low-power mode or power-off state.

This indicates that the module is ready to resume operations.

Figure 8 indicates the line states while in a low-power mode.

250 Series Transceiver Low-Power Line States

Line Name Pin Number Pin State

Deep Sleep

PR_PKT

TXD

1

2

Driven low

Deep sleep is selected by writing a 0x03 to regOPMODE. When the

module is put into deep sleep, the CTS line is brought high to indicate that

the module is not ready to accept UART data. The radio is placed in its

lowest power mode and all services are stopped. The protocol controller’s

oscillator is also stopped and all non-essential functions are turned off.

While powered, this mode consumes the least amount of current. The

module wakes from deep sleep in less than 6ms. A low pulse of at least

20µs on the RESET line starts the waking process, but the module doesn’t

begin executing wake instructions until the RESET line is returned high.

As with the other low-power modes, the RAM contents are preserved.

If the RAM fails an integrity check, the module issues itself a software

reset to force re-initialization. Note that, if the volatile data rate register is

changed during the host application initialization (regUARTDATARATE),

the re-initialization returns the module to the value in the non-volatile

counterpart (regNVUSERDATARATE).

Input with weak pull-up

Driven low

RESET

C2D

6

7

CMD_RSP

EX

9

10

14

15

16

19

20

RSSI

Driven low

CMD

BE

Input with weak pull-up

In Standby, Sleep: Driven Low, In Deep Sleep: Driven High

Input with weak pull-up

CTS

RXD

Figure 8: 250 Series Transceiver Low-Power Line States

–

11

10

Exception Codes

Reset to Factory Default

Exception codes are organized by type for ease of masking. Figure 9 lists

the exception codes and their meanings. All other values are reserved.

It may be necessary to reset the non-volatile registers to their factory

defaults. To reset the module, hold the CMD line low and cycle power to

hardware-reset the module. The CMD line must remain low for a minimum

of 600ms after resetting the module. Once the CMD line is released, the

module’s non-volatile registers are reset to factory defaults.

250 Series Transceiver Exception Codes

Exception Code Exception Name

Description

0x08

0x09

0x13

EX_BUFOVFL

EX_RFOVFL

Internal UART buffers overﬂowed.

Internal RF packet buffer overﬂowed.

Compatibility Mode

The 250 Series modules support a mode that allows them to communicate

with the smaller, lower power 25 Series modules. The 250 Series operates

at a much narrower receive bandwidth (200kHz) than the 25 Series

(600kHz). To allow interoperability, the 250 and 25 Series transceivers

support a compatibility mode that allows the modules to communicate

effectively with each other.

EX_WRITEREGFAILED Attempted write to register failed.

Acknowledgement packet not received

EX_NORFACK

0x20

after maximum number of retries.

0x40

0x42

0x43

0x44

EX_BADCRC

Bad CRC detected on incoming packet.

Bad CRC detected in packet header.

Sequence ID was incorrect in ACK packet.

Unsupported frame type speciﬁed.

EX_BADHEADER

EX_BADSEQID

EX_BADFRAMETYPE

Compatibility mode reduces the maximum RF data rate to 76.8kbps. All

UART baud rates are supported, although the RF data rates associated

with baud rates 31,250; 38,400; 57,600 and 115,200 are reduced.

Figure 9: 250 Series Transceiver Exception Codes

Exception Masking

The EX line can be asserted to indicate to the host that an error has

occurred. The exception mask provides a simple method of choosing

which errors cause the line to toggle. If the result of ANDing the exception

code with the exception mask is non-zero, the EX line is asserted. The

regEXCEPTION register must be read to reset the line. Figure 10 lists some

example exception masks.

Automatic Gain Control and Manual Gain Control

The gain setting of the receiver’s low noise ampliﬁer (LNA) is adjustable.

By default, the 250 Series is factory-conﬁgured to use its internal automatic

gain control (AGC) circuit to manage receiver sensitivity. Reducing the gain

increases the linearity of the receiver, but reduces maximum sensitivity;

increasing the gain does the opposite. Generally speaking, higher

linearity (increased third order input intercept point, IIP3) gives improved

performance in high-interference environments; high gain yields better

performance in low-interference environments.

250 Series Transceiver Example Exception Masks

Exception Mask Exception Name

0x08

0x10

0x20

Allows only EX_BUFOVFL and EX_RFOVFL to trigger the EX line

Allows only EX_WRITEREGFAILED to trigger the EX line

Allows only EX_NORFACK to trigger the EX line

The module contains an AGC circuit that manages these settings

automatically, and it should be used whenever possible. However, when

attempting to make analog RSSI measurements, ﬁxing the LNA gain

produces more meaningful results. Digital RSSI readings are internally

compensated and may be taken with AGC enabled.

Allows only EX_BADCRC, EX_BADHEADER, EX_BADSEQID and

EX_BADFRAMETYPE exceptions to trigger the EX line

0x40

Allows EX_BADCRC, EX_BADHEADER, EX_BADSEQID, EX_

0x60

0xFF

BADFRAMETYPE and EX_NORFACK exceptions to trigger the EX

line

Allows all exceptions to trigger the EX line

Exception Engine

The modules are equipped with an internal exception engine. If errors occur

during module operation, an exception is raised. Exception codes are

stored in the regEXCEPTION register and are cleared once they are read.

If an exception code is already present in regEXCEPTION when an error

occurs, the new exception code overwrites the old value.

Figure 10: 250 Series Transceiver Example Exception Masks

The exception mask has no effect on the exceptions stored in the

exception register. It only controls which exceptions affect the EX line.

–

13

12

GUID Networking Mode

Networking Modes

GUID networking mode is the simplest mode and supports point-to-point

and broadcast communications. Each module is programmed at

the factory with a unique 4-byte ID number that cannot be changed.

These bytes are found in the non-volatile read only MYGUID registers

(regMYGUID[0-3]). GUID networking mode uses these IDs as addresses.

The transmitting unit’s GUID is used as the source address and the

intended receiver’s GUID is written into the destination address register

(regDESTGUID[0-3]). All modules within range hear the transmission, but

only the module with the ID that matches the destination address outputs

the data on its UART. All others ignore the transmission.

The module has a very ﬂexible addressing and networking scheme selected

with the regNVNETWORKMODE and regNETWORKMODE registers. It

can be changed during operation. The transmitting module addresses

packets according to the network mode conﬁguration. The receiving

module processes all addressing types regardless of the network mode

conﬁguration. If the received message matches the addressing criteria, it is

output on the UART. Otherwise it is discarded.

There are three networking modes: GUID, User and Extended User. Each

mode offers different communications schemes, but all use source and

destination addressing. The source address is for the transmitting unit,

the destination address is the intended receiver. Each mode uses different

registers for the source and destination addresses.

A broadcast message is created when the destination address is

0xFFFFFFFF. In this case, all modules within range output the data. It is not

recommended to send broadcast messages when acknowledgements are

enabled. Figure 11 lists some examples of how GUID networking works.

The module supports an automatic addressing mode that reads the

Source Address from a received packet and uses it to ﬁll the Destination

Address register. This makes sure that a response is sent to the device that

transmitted the original message. This also allows the host microcontroller

to read out the address of the sending unit.

250 Series Transceiver GUID Network Mode Examples

Sender

Receiver

MyGUID

Network

Mode

Destination

GUID

MyGUID

Response

The automatic addressing is enabled for the different networking modes

with register regAUTADD and regNVAUTADD.

0x00002000 Data output by both modules.

No RF ACK sent by either

0x04

(GUID)

0x00001000 0xFFFFFFFF

0x00003000

module.

0x00002000 Data output by both modules.

No ACK sent by either module.

0x14

(GUID + 0x00001000 0xFFFFFFFF

ACK)

This conﬁguration causes

0x00003000

transmission problems.

0x00002000 Not processed – discarded.

0x14

(GUID + 0x00001000 0x00003000

ACK)

Data output. RF ACK sent to

0x00003000

0x00001000

0x00002000 Data output. No RF ACK sent.

0x00003000 Not processed – discarded.

0x04

0x00001000 0x00002000

(GUID)

Figure 11: 250 Series Transceiver GUID Network Mode Examples

–

15

14

User Networking Mode

250 Series Transceiver User Network Mode Examples

User Networking Mode is a more complicated scheme than GUID

mode. It uses the customer ID bytes (regCUSTID[0-1]) and two of the

user destination bytes (regUSERDESTID[0-1]) as a destination address.

The customer ID bytes are programmed at the factory and cannot be

changed. The module’s local address is contained in two of the user

source ID registers (regUSERSRCID[0-1]). Each module also has a user ID

mask (regUSERIDMASK[0-1]) that provides an additional logical layer of

addressing and can be used to create sub-networks. The receiving module

masks its local address and the received destination address by calculating

the logical AND with the user ID mask. If the results are equal, then the

payload is output on the UART. The customer ID bytes are not masked, but

must match the local value.

Destination

ID from

Result of Result of

Receiver Receiver

Dest

AND

Mask

Source

AND

Source

ID

User ID

Mask

Action

Received

Packet

Mask

The results are equal, so

the payload is output on

the UART.

2000

3000

2000

The results are equal, so

the payload is output on

the UART. The destination

ID and the source ID

match, so an ACK is

transmitted if enabled.

3000

E000

2000

The results do not match,

so the packet is discarded.

4000

2000

4000

2000

The results do not match,

so the packet is discarded.

If acknowledgements are enabled, only the module with a user source ID

that matches the transmitted user destination ID responds. The mask is not

used for this determination.

The results are equal, so

the payload is output on

the UART. The destination

ID and the source ID

3000

E000

3000

F000

E000

3000

E000

3000

match, so an ACK is

transmitted if enabled.

If the result of the user ID Mask AND the received user destination address

equals the same value as the user ID mask, then the payload data is output

on the UART. This acts as a broadcast message to the network.

The results do not match,

so the packet is discarded.

4000

2000

3000

4000

2000

4000

The destination ID matches

the user ID mask, so the

data is output on the UART.

Setting the mask to 0xFFFF removes the mask and only the source and

destination addresses are used for networking. When using user network

mode to send packets to multiple users and the mask is not equal to

0xFFFF, acknowledgements must be disabled. Failure to do so could cause

extreme delays in transmission and loss of data.

Figure 12: 250 Series Transceiver User Network Mode Examples

250 Series Transceiver User Network Mode Examples

As an example, if the mask is 0xFFF0 and the destination address

transmitted by the sender is 1234, then all modules with a source ID of

123x respond. This gives a subnet of 16 modules (where x = 0 to F) and

acts as a broadcast message to the sub-net. Acknowledgements should

be disabled.

Sender

Receiver

User

Network User

Mode

User

IDMASK

Response

SRCID

DESTID SRCID

0x2000 0XFFFF

0x3000 0xFFFF

0x2000 0xFFFF

0x06

(User)

Data output by both modules. No

ACK sent by either module.

0x1000 0xFFFF

Data output by both modules. No

ACK sent by either module. This

conﬁguration causes transmission

problems.

0x16

(User +

ACK)

Figure 14 shows this example and Figure 12 and Figure 13 show some

more examples of user networking mode.

0x3000 0xFFFF

0x2000 0xE000

0x3000 0xE000

Data output. No ACK sent.

0x16

(User +

ACK)

0x1000 0x3000

Data output. ACK sent to

0x1000.

0x2000 0xF000

0x3000 0xF000

Not processed – discarded.

Data output. No ACK sent.

0x6

(User)

Figure 13: 250 Series Transceiver User Network Mode Examples

–

17

16

Assured Delivery (Acknowledgement)

250 Series Transceiver User Network Mode Examples

While not an addressing mode on its own, assured delivery can be

enabled for each of the addressing modes. When a module transmits

with assured delivery enabled, it obligates the receiving module to return

an acknowledgement packet. The transmitting module waits for this

acknowledgement for a preset amount of time based on the data rate.

If an acknowledgement is not received, it retransmits the packet. If the

receiver receives more than one of the same packet, it discards the packet

contents but sends an acknowledgment. This way, duplicate data is not

output by the module. It is extremely important that assured delivery be

used only when the unmasked user/extended user Destination ID or

Destination GUID points to a speciﬁc module. Failure to speciﬁcally address

a valid module could cause the module to appear slow or unresponsive

due to repeated retransmissions. This also serves to congest the network,

impeding valid communications.

Destination

ID from

Result of Result of

Receiver Receiver

Dest

AND

Mask

Source

AND

Source

ID

User ID

Mask

Action

Received

Packet

Mask

The results are equal, so

the payload is output on

the UART.

Any

module

with

1234

FFF0

1230

123x

Do not enable

acknowledgements

Figure 14: 250 Series Transceiver User Network Mode Examples

Extended User Addressing Mode

Extended User Networking Mode is the same as User Networking Mode

but uses longer addresses. The two customer ID bytes are still used

(regCUSTID[0-1]) but all four bytes are used for the user destination

address (regUSERDESTID[0-3]), user source ID (regUSERSRCID[0-3])

and user ID mask (regUSERIDMASK[0-3]). This provides more addressing

capabilities at the expense of more overhead in the packet. Otherwise all

functionality is the same.

If the received destination address matches the local address, the receiving

module immediately sends an RF ACK packet. This packet lets the sending

module know that the message has been received. An RF ACK packet is

sent immediately following reception; CSMA delay is not applied to RF ACK

packets. When the sending module receives the RF ACK packet, it marks

the current block of data as completed. If this is the last message in the

queue, the sending module asserts the BE line to indicate the state of the

incoming buffer.

250 Series Transceiver Extended User Network Mode Examples

Sender

Receiver

Network User

User

DESTID

User

SRCID

User

IDMASK

Response

Mode

SRCID

0x20000001 0XFFFFFFFF Data output by

both modules. No

0x20000002 0xFFFFFFFF

0x07

0x10000000 0xFFFFFFFF

Troubleshooting Hint: If modules are unable to communicate with each

other, check the following:

ACK sent by either

module.

0x20000001 0xFFFFFFFF Data output by

both modules.

•ꢀ Check to make sure that both modules are set to the same data rate.

Modules programmed with different data rates will not communicate or

share an RF channel with one another.

No ACK sent by

0x17

0x10000000 0xFFFFFFFF

either module. This

0x20000002 0xFFFFFFFF

conﬁguration will

cause transmission

problems.

Data output. No

ACK sent.

0x20000001 0xE0000000

0x30000001 0xE0000000

0x20000001 0xF0000000

0x30000001 0xF0000000

•ꢀ Ensure that the network mode and addressing is conﬁgured to properly

access the module of interest. Also, ensure that a speciﬁc module is

addressed when using acknowledgment. Failure to do so causes large

delays and loss of data.

0x17

0x07

0x10000000 0x30000001

0x10000000 0x30000002

Data output. ACK

sent to 0x1000.

Not processed –

discarded.

Data output. No

ACK sent.

Figure 15: 250 Series Transceiver Extended User Network Mode Examples

–

19

18

Extended Preamble

As the receivers scan the hop sequence channels they look for the

preamble from a transmitter. When they detect this preamble, they stop

scanning and wait for a packet header. From the packet header they are

able to lock on to the transmitter and synchronize the timing.

It is an advantage in some applications to keep the receivers asleep for

long periods of time and wake them up only periodically to look for data. In

this scenario it is quite possible for the receivers to miss the preamble from

the transmitter and go to sleep without ﬁnding the transmission.

To address this issue, the modules can send an extended preamble. The

extended preamble is much longer than the normal preamble and gives

modules a larger window to detect and lock on to the transmitter.

There are two types of packets sent by the transmitter: synchronizing

packets and data packets. The receivers use the synchronizing packets

to lock on to the transmitters and follow them through the next hop. This

packet is the ﬁrst packet sent after every hop. The packets sent after the

synchronizing packet and before the next hop are data packets. Receivers

can catch and process data packets, but do not lock on and follow the

transmitter unless they process the synchronizing packet.

It is important to note that an extended preamble packet may not be

a synchronizing packet. If it is a data packet the receiver processes

the packet and begins scanning again. It is important for the external

processor or application to keep modules awake long enough to catch the

synchronizing packet on the next hop. This ensures that the modules lock

on to the transmitting module and receive all of the data.

The dwell time on each channel is approximately 395ms plus the times per

baud rate shown in Figure 39. This can be shorter if the host processor

determines that the necessary information has been received. Additionally

the PR_PKT line can be used to determine that the module is processing a

packet and keep it awake.

This page is intentionally blank.

–

21

20

Voltage Supply Rise Time

Receive Signal Strength Indication (RSSI)

The power supply rise time is extremely important. It must rise from ground

to 2.7V in less than 1ms. If this speciﬁcation cannot be met, an external

reset supervisor circuit must be used to hold the module in reset until the

power supply stabilizes. Failure to ensure adequate power supply rise time

can result in loss of important module conﬁguration information.

The RSSI line outputs an analog voltage that is proportional to the signal

strength present on the channel at the time. In normal operation, the

module is hopping rapidly from channel to channel. In this case, the

RSSI value varies greatly and does not provide much useful information.

However, it can be used to keep a module awake by sampling the RSSI

line to determine if the module is processing a packet before putting it to

sleep.

Using the Buffer Empty (BE) Line

The BE line indicates the state of the module’s UART buffer. When the

module receives data in the RXD line and the CMD line is high, the BE line

is lowered until all data in the buffer has been processed by the protocol

engine. If acknowledgement is not enabled, the BE line is raised as soon as

the protocol engine processes the outgoing packets. If acknowledgement

is enabled, the buffer is not updated until either the data transmissions

are acknowledged by the remote end or delivery fails after the maximum

number of retries. When the BE line returns high, the EX line may be

sampled, or the regEXCEPTION register polled to determine if an error

occurred during transmission.

The 250 Series module has an internal digital RSSI indication of the

immediate ambient environment and of the last good packet received.

Additionally, the PR_PKT line can be used to indicate the state of the

protocol engine.

RSSI level is dependent on the power of the signal received at the antenna

port and the mode the LNA is in. regLNAMODE controls the mode of the

internal LNA. Figure 16 shows typical traces of RSSI voltage versus signal

strength.

2500

Using the Exception (EX) Line

High Sens

The EX line indicates whether or not a module exception has occurred.

The line is normally low, but it is raised if an exception occurs that passes

masking. When the regEXCEPTION register is read, the exception is

cleared and the EX line returns low. If more than one exception occurs

before the regEXCEPTION register is read, the old exception is overwritten

by the new one. Please see the Exception Engine section for more details.

Mid IIP3

2000

High IIP3

Auto Gain

1500

1000

500

Using the Processing Incoming Packet (PR_PKT) Line

The PR_PKT line indicates whether the protocol engine has determined

there to be valid or potentially valid data incoming. The line is normally low

(not processing). When awake and not transmitting, the protocol engine

is constantly searching for incoming data. When scoring indicates that a

potential packet is inbound, this line is raised until either the scoring falls

below a given threshold or the complete packet is received. It is possible

that the packet scoring will fall below the threshold during reception,

causing the line to be lowered. Such an instance can occur when the

module hops to a channel late in the transmitter’s extended preamble.

Since there aren’t a large number of valid bits to score, the line may fall

during the packet start sequence. Once this sequence arrives, the PR_PKT

signal rises and latches for the duration of the packet reception.

0

-102 -98 -94 -90 -86 -82 -78 -74 -70 -66 -62 -58 -54 -50 -46 -42 -38 -34 -30 -26 -22

RF IN (dBm)

Figure 16: 250 Series Transceiver P_INvs RSSI Voltage

–

23

22

Using the RESET Line

VCC

The RESET line has different functions depending on the state the module

is in. It is an open-drain input/output line with an integrated weak pull-up,

so it is normally high. Because it periodically operates as an output,

external control should only pull this line low, not high.

2.70

2.55

V_RST

2.0

Hardware Reset (Input)

1.0

During normal operation, the RESET line functions as an active-low

hardware reset input. Taking this line low for at least 15µs forces the

module’s controller into hardware reset. While the line is low, execution of

module operations are suspended and all module lines revert to open-drain

inputs with weak pull-ups. This behavior can be exploited during power-up

if the V_CCramp time exceeds 1ms. By suspending execution, the dangers

associated with slow V_CCramp are eliminated.

t

RESET

Logic HIGH

Logic LOW

T_PORDelay

Wake from Deep Sleep (Input)

VCC

Monitor

Reset

Power-On

Reset

When the module is in deep sleep, all execution is suspended in the

controller and the radio is in its lowest power mode. The RESET line must

be lowered for at least 15µs to wake the module. When the RESET line is

raised, execution begins in the controller. The module maintains its state

engine while asleep. Because of this, it can detect whether the hardware

reset was intended to cause a hard reset or wake the module. The

controller’s RAM is preserved during deep sleep. The RAM is checked prior

to entering deep sleep, and examined upon waking. If the RAM contents

are corrupted upon wake, the module issues itself a software reset to

reinitialize the module.

Figure 17: 250 Series Transceiver Reset Timing Diagram

250 Series Transceiver Reset Circuit Speciﬁcations

Parameter

Min. Typ. Max. Units Notes

RESET Output Low Voltage

RESET Input Pull-up Current

0.6

40

V

µA

V

V_CC= 2.7 – 3.6V

RESET = 0.0V

25

V_CCMonitor Threshold (V_RST

)

2.40 2.55 2.70

15

Minimum RESET Low Time to

Generate a Hardware Reset

µs

Hardware Reset Indicator (Output)

When the module starts from power-off, or is reset by the internal V_CC

monitor circuitry, the RESET line is driven low to indicate the reset state.

During power-on reset, assuming the V_CCramp time is valid, RESET is

driven low from the time that V_CCreaches approximately 1V until V_CC

reaches V_RST+ T_PORDelay. T_PORDelayis the power-on reset delay imposed by the

controller’s hardware.

Power-on Reset Delay (T_PORDelay

)

<300

1

µs

V_CCRamp Time is Valid

Allowed/Valid V_CCRamp Time

ms

Figure 18: 250 Series Transceiver Reset Circuit Speciﬁcations

Warning: If the RESET line experiences noise, it can cause multiple

triggers (wake from sleep, hardware reset, hardware reset, etc.) and

cause the volatile registers to be reloaded with their non-volatile values. If

the circuit introduces noise onto this line, a bypass capacitor or RC ﬁlter

should be placed on the line as close to the module as is practical.

The other event that drives the RESET line low is a low-voltage or

brown-out condition. In this case, the V_CCmonitor holds the module in

reset, thus driving the RESET line low. It remains low until the power drops

below the operating threshold for that circuit (becoming indeterminate),

or until the module’s power supply returns to V_RST. Figure 17 illustrates the

operation of RESET as an output.

–

25

24

Using the Command Response (CMD_RSP) Line

The CMD_RSP line is normally high, but the module lowers this line when

responding to a UART command. This indicates to an external processor

that the data on the TXD line is a response to a command and not data

received over-the-air.

The CMD Line

The CMD line is used to inform the module where incoming UART data

should be routed. When the line is high or left ﬂoating, all incoming UART

data is treated as payload data and is routed to the transmitter to be sent

over the air. If the CMD line is low, the incoming UART data is routed to

the command parser for processing. Since the module’s controller looks

at UART data one byte at a time, the CMD line must be held low for the

entire duration of the command plus a 20µs margin for processing. Leaving

the line low for additional time (for example, until the ACK byte is received

by the application) does not adversely affect the module. If RF packets are

received while the CMD line is active, they are still processed and output on

the module’s UART. Figure 19 shows this timing.

The module outputs received RF data immediately following the command

response. The CMD_RSP line does rise before resuming RF data, but

some processors cannot react quickly enough to this signal and may not

able to separate the command responses from RF data.

The regCMDHALT register controls the behavior of the TXD line when the

CMD line is low and the external processor is conﬁguring the module.

If this register is set to 0x01 and the CMD line is low, the module stops

outputting the RF data and internally buffers it. Once the CMD line is raised,

the buffered RF data is output on the TXD line. This allows the external

processor to have separate conﬁguration times and data times instead of

potentially having to handle both at once.

0xFF

...

B1

B0

RXD

CMD

≥20µs

Figure 19: 250 Series Transceiver CMD Line Timing

The CMD line is also used during the module startup process to determine

whether or not to reload the non-volatile registers with factory defaults. The

module startup process is executed when the module is powered on from

an off state or is issued a software or hardware reset. When the module

goes through this startup process, it checks the state of the CMD line. If it

is low, the module clears the non-volatile registers and re-populates them

with factory default values. It is important to ensure that CMD is held high

or left ﬂoating during power-up under normal conditions.

Possible reset sources that could cause the module to reboot are power

supply brown-out, power supply instability and noise present on the RESET

line, noise/voltage spikes on digital I/O lines, issuing a reset command

through the command interface, and toggling the RESET line when not in

deep sleep.

–

27

26

src_len) or the register number and value to write (two bytes, pass 2 into

src_len). It is also assumed that the *dest buffer has enough space for the

two header characters plus the encoded command and the null terminator.

The UART Interface

The module uses a standard UART interface for both data to be sent over

the air and for conﬁguring the module. The CMD line is used to tell the

module if the data on the UART is for conﬁguration or transmission. The

lines follow the standard UART naming convention, so RXD is the data

input into the module and TXD is the data output from the module. The

UART interface expects 1 start bit, 8 data bits (LSB ﬁrst), and 1 stop bit per

byte with no parity (8-N-1).

int EscapeString(char *src, char src_len, char *dest)

{

// The following function copies and encodes the ﬁrst

// src_len characters from *src into *dest. This

// encoding is necessary for module command formats.

// The resulting string is null terminated. The size

// of this string is the function return value.

// ---------------------------------------------------

char src_idx, dest_idx;

The module has a 256 byte buffer for incoming data. The module can be

programmed to automatically transmit when the buffer reaches a limit or

based on the time between bytes on the UART. This allows the designer to

optimize the module for ﬁxed length and variable length data. The module

supports streaming data as well. To optimize the module for streaming

data, regUARTMTU should be set to 128, and regTXTO should be set to a

value greater than 1 UART byte time at the current UART data rate (10 bit

times rounded up) or 2, whichever is greater.

// Save space for the command header and size bytes

// ------------------------------------------------

dest_idx = 2;

// Loop through source string and copy/encode

// ------------------------------------------

for (src_idx = 0; src_idx < src_len; src_idx++)

{

If the buffer gets nearly full (about 224 bytes), the module pulls the CTS line

high, indicating that the host should not send any more data. Data sent

by the host while the buffer is full is lost, so the the CTS line provides a

warning and should be monitored. When there is data in the UART receive

buffer, the BE line is low; when this buffer is empty, BE is high.

if (src[src_idx] > 127)

{

dest[dest_idx++] = 0xFE;

}/*if*/

Conﬁguration Command Formatting

dest[dest_idx++] = (src[src_idx] & 0x7F);

}/*for*/

The 250 Series module contains several volatile and non-volatile registers

that control its conﬁguration and operation. The volatile registers all

have non-volatile mirror registers that are used to determine the default

conﬁguration when power is applied to the module. During normal

operation, the volatile registers are used to control the module.

// Add null terminator

// -------------------

dest[dest_idx] = 0;

// Add command header

// ------------------

Placing the module in the command mode allows these registers to be

programmed. Byte values in excess of 127 (0x80 or greater) must be

changed into a two-byte escape sequence of the format:

dest[0] = 0xFF;

dest[1] = dest_idx – 2;

// Return escape string size

// -------------------------

return dest_idx;

0xFE, [value - 128]

}

For example, the value 0x83 becomes 0xFE, 0x03. The function in Figure

20 prepends a 0xFF header and size speciﬁer to a command sequence

and creates escape sequences as needed. It is assumed that *src is

populated with either the register number to read (one byte, pass 1 into

Figure 20: Command Conversion Code

–

29

28

Module Conﬁguration

250 Series Volatile Read / Write Conﬁguration Registers Continued

The 250 Series module contains several registers that control its

conﬁguration and operation. The module’s default settings allow it to

operate out of the box without any changes; however the registers allow

the link to be customized to better suit the application if necessary. The

register settings are stored in two types of memory inside the module.

Volatile memory is quick to access, but it is lost when power is removed

from the module. Non-volatile memory takes longer to access, but is

retained when power is removed.

Name

Address Description

regOPMODE

regACKONWAKE

0x58

0x59

Sets operating mode

Enable / Disable ACK sent to UART upon wake

Destination Address for Extended User Networking

Mode

regUSERDESTID[3]

regUSERDESTID[2]

regUSERDESTID[1]

regUSERDESTID[0]

regUSERSRCID[3]

regUSERSRCID[2]

regUSERSRCID[1]

regUSERSRCID[0]

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

Destination Address for Extended User Networking

Mode

Destination Address for User and Extended User

Networking Mode

All of the conﬁguration settings have registers in both types of memory.

The settings are read from non-volatile registers on power up and saved in

volatile registers. The values in the volatile registers are used during normal

operation since it is faster to read and write the volatile memory locations.

There are commands to read and write both locations.

Destination Address for User and Extended User

Networking Mode

Source Address for Extended User Networking

Mode

Source Address for Extended User Networking

Mode

Source Address for User and Extended User

Networking Mode

Figure 21 shows the volatile read-only registers. Figure 22 shows the

volatile read and write registers. Figure 23 shows the non-volatile read-only

registers. Figure 24 shows the non-volatile read and write registers.

Source Address for User and Extended User

Networking Mode

regUSERIDMASK[3]

regUSERIDMASK[2]

0x62

0x63

Address Mask for Extended User Networking Mode

250 Series Volatile Read-Only Conﬁguration Registers

Address Mask for User and Extended User

Networking Mode

Name

Address Description

regUSERIDMASK[1]

regUSERIDMASK[0]

0x64

0x65

regEXCEPTION

regLGPRSSI

regIMMEDRSSI

0x79

0x7B

0x7C

Stores latest exception code

Address Mask for User and Extended User

Networking Mode

Last Good Packet RSSI value

Current RSSI value

regDESTGUID[3]

regDESTGUID[2]

regDESTGUID[1]

regDESTGUID[0]

regEXCEPTIONMASK

regCMDHALT

0x68

0x69

0x6A

0x6B

0x6C

0x6E

0x6F

GUID Networking Mode Destination Address

Exception and Mask used to activate the EX line

Half RF trafﬁc when the CMD line is low

Receiver LNA gain / linearity setting

Figure 21: 250 Series Volatile Read Only Conﬁguration Registers

250 Series Volatile Read / Write Conﬁguration Registers

Name

Address Description

regCRCERRCOUNT

regHOPTABLE

regPWRMODE

regUARTDATARATE

regNETWORKMODE

regTXTO

0x40

0x4B

0x4D

0x4E

0x4F

0x50

0x52

0x53

0x54

0x56

CRC error count value

regLNAMODE

Hop table

Compatibility mode for 25 and 250

intercommunication

regCOMPATMODE

regAUTADD

0x70

0x71

Power ampliﬁer setting

Sets automatic addressing

UART data rate

Sets the networking mode

UART to transmit timeout

Maximum times to retry packet transmission

Enable / Disable CRC checking

Minimum transmission unit

Enable / Disable CSMA

Figure 22: 250 Series Volatile Read / Write Conﬁguration Registers

regMAXTXRETRY

regUSECRC

Warning: Modules that are not conﬁgured in the same way will not be

able to communicate reliably, causing poor performance or outright

failure of the wireless link. All modules in a network must have compatible

conﬁgurations to ensure interoperability.

regUARTMTU

regCSMAMODE

–

31

30

250 Series Non-Volatile Read-Only Registers

250 Series Non-Volatile Read / Write Registers Continued

Name

Address Description

Factory Default

Name

Address Description

Destination Address for

Factory programmed GUID used in GUID Networking

regMyGUID[3]

0x34

0x35

0x36

0x37

regNVUSERDESTID[0]

0x12

User and Extended User

Networking Mode

0xFF

Mode

Factory programmed GUID used in GUID Networking

Mode

regMYGUID[2]

regMYGUID[1]

regMYGUID[0]

Source Address for Extended

User Networking Mode

regNVUSERSRCID[3]

regNVUSERSRCID[2]

0x13

0x14

0xFF

Factory programmed GUID used in GUID Networking

Mode

Source Address for Extended

User Networking Mode

Factory programmed GUID used in GUID Networking

Mode

Source Address for User and

Extended User Networking

Mode

regNVUSERSRCID[1]

regNVUSERSRCID[0]

0x15

0x16

0xFF

regCUSTID[1]

0x39

0x3A

0x78

Factory programmed customer ID, default 0xFF

Holds release number indicating h/w and f/w

regCUSTID[0]

Source Address for User and

Extended User Networking

Mode

regRELEASENUM

Address Mask for Extended

User Networking Mode

regNVUSERIDMASK[3]

regNVUSERIDMASK[2]

0x17

0x18

0xFF

Figure 23: 250 Series Non-volatile Read-Only Conﬁguration Registers

Address Mask for Extended

User Networking Mode

250 Series Non-Volatile Read / Write Registers

Address Mask for User and

Extended User Networking

Mode

Name

Address Description

Factory Default

0

regNVUSERIDMASK[1]

regNVUSERIDMASK[0]

0x19

0x1A

0xFF

regNVHOPTABLE

regNVPWRMODE

regNVUARTDATARATE

regNVNETWORKMODE

regNVTXTO

0x00

0x02

0x03

0x04

0x05

Hop table

Address Mask for User and

Extended User Networking

Mode

Power ampliﬁer setting

UART data rate

3 (High Power)

0 (2400)

GUID Networking Mode

Destination Address

Sets the networking mode

UART to transmitter timeout

4 (MAC/GUID)

16 (15–16ms)

regNVDESTGUID[3]

regNVDESTGUID[2]

regNVDESTGUID[1]

regNVDESTGUID[0]

regNVEXCEPTIONMASK

regNVCMDHALT

0x1D

0x1E

0x1F

0x20

0x21

0x23

0x24

0xFF

GUID Networking Mode

Destination Address

Maximum times to retry packet

transmission

regNVMAXTXRETRY

0x07

26

GUID Networking Mode

Destination Address

0xFF

regNVUSECRC

regNVUARTMTU

0x08

0x09

Enable/Disable CRC checking

Minimum transmission unit

1 (Enable)

GUID Networking Mode

Destination Address

64 (64 bytes)

0xFF

Enable/disable startup

message

regNVSHOWVERSION

0x0A

1 (Enabled)

Used to mask exception for

the EX line

0xFF (All)

0 (Disabled)

0 (Auto)

regNVCSMAMODE

regNVOPMODE

0x0B

0x0D

Enable/Disable CSMA

Sets operating mode

1 (Enable)

0 (Awake)

Halt RF trafﬁc when the CMD

line is low

Receiver LNA gain / linearity

setting

Enable/Disable ACK sent to

UART upon wake from

regNVLNAMODE

regNVACKONWAKE

regNVUSERDESTID[3]

0x0E

0x0F

1 (Enable)

0xFF

Compatibility mode for 25 and

250 intercommunication

Destination Address for

Extended User Networking

Mode

regNVCOMPATMODE

regNVAUTADD

0x25

0x26

0 (Disabled)

Sets automatic addressing

Destination Address for

Extended User Networking

Mode

regNVUSERDESTID[2]

regNVUSERDESTID[1]

0x10

0x11

0xFF

Figure 24: 250 Series Non-volatile Read / Write Conﬁguration Registers

Destination Address for

User and Extended User

Networking Mode

–

33

32

Writing to Registers

Conﬁguration Registers

Writing to a volatile register is nearly instantaneous. Writing to a non-volatile

register typically takes 16ms. Because the packet size can vary based on

the need for encoding, there are two possible packet structures. The ﬁrst

structure writes a value that is less than 128 (0x80) and the second writes

a value that is higher. The higher value must be split into two values. Figure

25 shows the byte sequences for writing a register in each case.

The following sections give details on each conﬁguration register. Green

addresses in the tables are volatile locations and blue are non-volatile.

CRC Error Count - Address = 0x40

The value in the regCRCERRCOUNT register is incremented each time

a packet is received that fails CRC check. Writing 0x00 to this register

initializes the count. Figure 27 shows the command and response.

250 Series Write to Conﬁguration Register Command

Command for a Value less than 128 (0x80)

Header Size Address Value

250 Series CRC Error Count

Read Command

Read Response

0xFF

0x02

REG

V1

Header

0xFF

Size

Escape Address

ACK

0x06

Address

0x40

Value

V1

Command for a Value greater than 128 (0x80)

0x02

0xFE

0x40

Value

1

Value

2

Write Command

Header Size Address

0xFF 0x03 REG

Header

0xFF

Size

Address

0x40

Value

V1

0xFE

V2

0x02

Figure 25: 250 Series Write to Conﬁguration Register Command

Figure 27: 250 Series CRC Error Count Command and Response

The module responds with an ACK (0x06). If it is not received, the

command should be resent. The module responds with a NACK (0x15) if a

write is attempted to a read-only or invalid register.

Channel Hop Table - Address = 0x4B; NV Address = 0x00

The module supports 6 different hop sequences with minimal correlation.

The sequence is set by the value in the regHOPTABLE register. Changing

the hop sequence changes the physical band utilization, much the same

way that a channel does in a static transmitter. Valid values are 0-5. Figure

28 shows the command and response.

Warning: The module must remain powered for the duration of the

register write or important conﬁguration information could be lost.

Reading from Registers

A register read command is constructed by placing an escape character

(0xFE) before the register number. The module responds by sending an

ACK (0x06) followed by the register number and register value. The register

value is sent unmodiﬁed, so if the register value is 0x83, 0x83 is returned.

If the register number is invalid, the module responds with a NACK (0x15).

The command and response are shown in Figure 26.

250 Series Channel Hop Table

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x4B

0xFE

0x4B

0x00

0x02

0x00

Write Command

250 Series Read From Conﬁguration Register

Header

0xFF

Size

Address

Value

V1

Command

0x4B

0x00

0x02

Header

0xFF

Size

Escape Address

0x02

0xFE

REG

Figure 28: 250 Series Channel Hop Table Command and Response

Response

ACK

Figure 29 shows the RF channels used by the 250 Series and the hop

sequences referenced by channel number. The default hop sequence is 0.

Address

REG

Value

V1

0x06

Figure 26: 250 Series Read from Conﬁguration Register Command and Response

–

35

34

Power Mode - Address = 0x4D; NV Address = 0x02

The value in the regPWRMODE register sets the module’s output power.

250 Series RF Channels and Hop Sequences

Hop Sequence by Channel Number

Channel Frequency

Number

(MHz)

0

1

15

30

29

26

21

10

20

8

2

3

4

22

7

5

Figure 30 shows the command and response and Figure 31 available

power settings and typical power outputs for the module. The default

setting is 0x03.

0

902.971

903.723

904.475

905.226

905.978

906.730

907.482

908.234

908.986

909.737

910.489

911.241

911.993

912.745

913.496

914.248

915.000

915.752

916.504

917.255

918.007

918.759

919.511

920.263

921.015

921.766

922.518

923.270

924.022

924.774

925.525

926.277

16

1

3

28

11

10

7

9

1

20

21

24

29

8

24

23

20

15

4

2

8

3

5

11

16

27

17

29

20

3

250 Series Power Mode

4

10

21

11

23

14

29

27

22

12

24

17

3

2

Read Command

Read Response

5

23

1

6

30

10

1

14

2

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

PWR

7

21

30

15

17

22

0

0x4D

0xFE

0x4D

0x02

8

17

2

11

28

30

3

0x02

9

16

14

9

Write Command

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

4

1

Header

0xFF

Size

Address

Value

PWR

9

28

18

30

23

9

0x4D

0x02

19

7

31

11

4

13

1

0x02

20

27

9

14

28

24

16

0

8

Figure 30: 250 Series Power Mode Command and Response

22

26

2

22

18

10

26

27

29

0

7

5

13

21

5

15

31

30

28

25

19

6

29

13

14

16

19

25

6

250 Series Power Mode Register Settings

18

17

15

12

6

PWR

0x00

0x01

0x02

0x03

Power Setting

Low

Typical Output Power (dBm)

1

4

3

2

+8

+13

6

31

25

12

19

0

Mid – Low

Mid – High

High

12

25

18

5

6

+18

25

0

19

12

31

+23.5

13

26

31

18

13

Figure 31: 250 Series Power Mode Settings

Figure 29: 250 Series RF Channels and Hop Sequences

–

37

36

UART Data Rate - Address = 0x4E; NV Address = 0x03

Network Mode - Address = 0x4F; NV Address = 0x04

The value in regUARTDATARATE sets the data rate of the UART interface.

Changing the non-volatile register changes the data rate on the following

power-up or reset. Changing the volatile register changes the data rate

immediately following the command acknowledgement. Figure 32 shows

the command and response and Figure 33 shows the valid settings.

The module supports three networking modes: GUID, User, and Extended

User. For each of these modes, assured delivery (acknowledgement) and

extended preamble can be either enabled or disabled.

Figure 34 shows the command and response and Figure 35 shows the

valid settings.

250 Series UART Data Rate

Read Command

Read Response

250 Series Network Mode

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

Read Command

Read Response

0x4E

0xFE

0x4E

0x03

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x02

0x03

0x4F

0xFE

0x4F

0x04

0x02

Write Command

0x04

Header

0xFF

Size

Address

Value

V1

Write Command

0x4E

0x03

Header

0xFF

Size

Address

Value

V1

0x02

0x4F

0x04

0x02

Figure 32: 250 Series UART Data Rate Command and Response

Figure 34: 250 Series Network Mode Command and Response

250 Series UART Data Rate Register Settings

250 Series Network Mode Register Settings

V1

Baud Rate

2,400

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Network Mode

0x04

Meaning

9,600

GUID Networking Mode

User Networking Mode

19,200

38,400

57,600

115,200

10,400*

31,250*

0x06

0x07

Extended User Networking Mode

0x0C

GUID Networking Mode with Extended Preamble

User Networking Mode with Extended Preamble

0x0E

0x0F

Extended User Network Mode with Extended Preamble

GUID Networking Mode with Acknowledgement

User Networking Mode with Acknowledgement

0x14

* These data rates are not supported by PC serial ports.

Selection of these rates may cause the module to fail to

respond to a PC, requiring a reset to factory defaults.

0x16

0x17

Extended User Networking Mode with Acknowledgement

GUID Networking Mode with Acknowledgement & Extended

Preamble

0x1C

0x1E

0x1F

Figure 33: 250 Series UART Data Rate Settings

User Networking Mode with Acknowledgement & Extended

Preamble

If the UART rate is different than the host processor UART rate then the

module will not communicate correctly. If mismatched, every rate can be

tested until the correct one is found or the module can be reset to factory

defaults.

Extended User Networking Mode with Acknowledgement &

Extended Preamble

Figure 35: 250 Series Network Mode Register Settings

–

39

38

Transmit Wait Timeout - Address = 0x50; NV Address = 0x05

When a byte is received from the UART, the module starts a timer that

counts down every millisecond. The timer is restarted when each byte is

received. The value for the regTXTO register is the number of milliseconds

to wait before transmitting the data in the UART receive buffer. The default

setting for this register is 0x10 (~16ms delay).

Maximum Transmit Retries - Address = 0x52; NV Address = 0x07

regMAXTXRETRY sets the number of transmission retries if an

acknowledgement is not received. If an acknowledgement is not received

after the last retry, EX_NORFACK is raised. Figure 38 shows examples of

the command.

250 Series Maximum Transmit Retries

Read Command

Read Response

If the timer reaches zero before the next byte is received from the UART,

the module begins transmitting the data in the buffer. This timeout value

should be greater than one byte time at the current UART data rate with a

minimum of 0x02. It should not be set to a value of 0x01 or any value less

than one byte time as unpredictable results could occur.

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x52

0xFE

0x52

0x07

0x02

0x07

Write Command

Header

0xFF

Size

Address

Value

V1

0x52

0x07

If the timeout value is set to 0x00, the transmit wait timeout is deactivated.

In this case, the transceiver waits until a number of bytes equal to the

Minimum Transmission Unit (MTU) have been received by the UART. All

of the bytes are sent once the MTU has been reached. Figure 36 shows

examples of the commands. Figure 37 shows the minimum timeout values

based on baud rate.

0x02

Figure 38: 250 Series Maximum Transmit Retries Command and Response

The time between retries depends on the current baud rate. Figure 39

shows the time between retries based on baud rate. The retry number

times the timeout times gives the potential latency before a new message

can be sent.

250 Series Transmit Wait Timeout

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

250 Series Acknowledgement Timeout Times

0x50

0xFE

0x50

0x05

0x02

0x05

Baud Rate

2400

Timeout Time

170ms

75ms

Write Command

Header

0xFF

Size

Address

Value

V1

9600

0x50

0x05

19200

38400

57600

115200

45ms

0x02

30ms

Figure 36: 250 Series Transmit Wait Timeout Command and Response

30ms

250 Series Minimum TXTO Values

Figure 39: 250 Series Acknowledgement Timeout Times

Baud Rate

2,400

Minimum TXTO

6ms

3ms

2ms

9,600

19,200

38,400

57,600

115,200

Figure 37: 250 Series Transmit Wait Timeout Minimum Values

–

41

40

CRC Control - Address = 0x53; NV Address = 0x08

UART Minimum Transmission Unit - Addr = 0x54; NV Addr = 0x09

This register determines the UART buffer level that triggers the transmission

of a packet. The minimum value is decimal 1 and the maximum value

is 192. The default value for this register is 64, which provides a good

mix of throughput and latency. At the maximum data rate, a value of

128 optimizes throughput. This register does not guarantee a particular

transmission unit size; rather, it speciﬁes the minimum desired size. If there

is not enough time left in a hop, for instance, the protocol engine sends as

many characters as it can to ﬁll the current hop, and sends the remaining

characters in the next hop. Figure 42 shows examples of the commands.

The 250 Series protocol includes a Cyclic Redundancy Check on the

received packets to make sure that there are no errors. Any packets

with errors are discarded and not output on the UART. This feature can

be disabled if it is desired to perform error checking outside the module.

Set the regUSECRC register to 0x01 to enable CRC checking, or 0x00

to disable it. The default CRC mode setting is enabled. Figure 40 shows

examples of the commands and Figure 41 shows the available values.

250 Series CRC Control

Read Command

Read Response

250 Series UART MTU

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

Read Command

Read Response

0x53

0xFE

0x53

0x08

0x02

0x08

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

Write Command

0x54

0xFE

0x54

0x09

0x02

0x09

Header

0xFF

Size

Address

Value

V1

Write Command

0x53

0x08

0x02

Header

0xFF

Size

Address

Value

V1

0x54

0x09

0x02

Figure 40: 250 Series CRC Control Command and Response

Figure 42: 250 Series UART MTU Command and Response

250 Series CRC Control Register Settings

V1

Mode

0x00

0x01

CRC Disabled

CRC Enabled

Figure 41: 250 Series CRC Control Register Settings

–

43

42

Show Version - Address = 0x0A

CSMA Enable - Address = 0x56; NV Address = 0x0B

Setting this register to 0x00 suppresses the start-up message, including

ﬁrmware version, which is sent to the UART when the module is reset. A

value of 0x01 causes the message to be output after reset. By default,

the module start-up message is output. Figure 43 shows examples of the

commands and Figure 44 shows the available values.

Carrier-Sense Multiple Access (CSMA) is a transmission protocol that

listens to the channel before transmitting a message. If another module is

already transmitting when a message is queued, the module waits before

sending its payload. This helps to eliminate RF message corruption at the

expense of additional latency. Setting the regCSMAMODE register to 0x01

enables CSMA and 0x00 disables CSMA. By default, CSMA is enabled.

Figure 45 shows examples of the commands and Figure 46 shows the

available values.

250 Series Show Version

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

0x0A

Value

V1

250 Series CSMA Enable

0x02

0xFE

0x0A

Read Command

Read Response

Write Command

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

Header

0xFF

Size

Address

0x0A

Value

V1

0x56

0xFE

0x56

0x0B

0x02

0x0B

Write Command

Figure 43: 250 Series Show Version Command and Response

Header

0xFF

Size

Address

Value

V1

0x56

0x0B

0x02

250 Series Show Version Register Settings

V1

Meaning

Startup message is NOT output on reset or power-up.

Figure 45: 250 Series CSMA Enable Command and Response

0x00

Startup message is output on reset or power-up. This is a blocking

call, and any incoming UART data is lost during the transmission of

this message through the TXD line. All UART commands must be

sent after this message has completed.

0x01

0x02

250 Series CSMA Enable Register Settings

V1

Mode

Startup message is displayed upon reset or power-up. This is

a non-blocking call. Any incoming UART data is buffered, and

incoming UART commands are processed. If a change of baud

rate is commanded while the startup message is being output, the

current byte ﬁnishes at the current baud rate, and subsequent bytes

are transmitted at the new baud rate.

0x00

0x01

Disable CSMA

Enable CSMA

Figure 46: 250 Series CSMA Enable Register Settings

Figure 44: 250 Series Show Version Register Settings

–

45

44

Operating Mode - Address = 0x58; NV Address = 0x0D

ACK on Wake - Address = 0x59; NV Address = 0x0E

The value in the regOPMODE register sets the operating mode of the

transceiver. If the module remains properly powered, and is awakened from

a low power mode properly, the volatile registers retain their values when

awakened. If the volatile registers become corrupted during low power, a

software reset is forced and the module reboots.

When the module powers up and is ready for operation, it can output an

acknowledge (ACK) character (0x06) on the TXD line. This indicates that

the module is ready to accept data and commands. Setting this register to

0x00 disables the ACK, 0x01 enables the ACK. The default value is 0x01.

Figure 49 shows examples of the commands and Figure 50 shows the

available values.

Awake mode is the normal operating mode. This is the only mode in which

the RF circuitry is able to receive and transmit RF messages.

250 Series ACK on Wake

Read Command

Read Response

Standby leaves the RF oscillator circuit operating for faster wakeup,

whereas Sleep does not. One byte of 0x0F to the module’s RXD line at the

current baud rate wakes the modules.

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x59

0xFE

0x59

0x0E

0x02

0x0E

Write Command

Header

0xFF

Size

Address

Value

V1

Deep Sleep mode disables all circuitry on-board the module. This is the

lowest-power mode available for the module. A low pulse on the RESET

line of at least 15µs wakes the module. The module begins the wake

process once the RESET line is returned high.

0x59

0x0E

0x02

Figure 49: 250 Series ACK on Wake Command and Response

Please see the Low Power States section for more details. Figure 47 shows

examples of the commands and Figure 48 shows the available values.

250 Series ACK on Wake Register Settings

V1

Mode

250 Series Operating Mode

0x00

0x01

Disable ACK

Enable ACK

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x58

0xFE

0x58

0x0D

0x02

0x0D

Figure 50: 250 Series ACK on Wake Register Settings

Write Command

Header

0xFF

Size

Address

Value

V1

0x58

0x0D

0x02

Figure 47: 250 Series Operating Mode Command and Response

250 Series Operating Mode Register Settings

V1

Mode

0x00

0x01

0x02

0x03

Awake Mode

Sleep Mode

Standby Mode

Deep Sleep Mode

Figure 48: 250 Series Operating Mode Register Settings

–

47

46

User Destination ID

User ID Mask

These registers contain the address of the destination module when

User Networking mode or Extended User Networking mode are enabled.

User Networking mode uses bytes 0 and 1 to determine the destination

address. Extended User Networking mode uses all four bytes. Please see

the Networking Modes section for more details. Each register byte is read

and written separately.

These registers contain the user ID mask when User Networking mode

or Extended User Networking mode are enabled. User Networking mode

uses bytes 0 and 1 and Extended User Networking mode uses all four

bytes. Please see the Networking Modes section for more details. Each

register byte is read and written separately.

Figure 53 shows the User ID Mask Registers.

Figure 51 shows the User Destination ID Registers.

250 Series User ID Mask Registers

250 Series User Destination ID Registers

Volatile Non-Volatile

Name

Description

Address

Volatile Non-Volatile

Name

Description

Address

regUSERIDMASK[3]

regUSERIDMASK[2]

0x62

0x17

MSB of the extended mask

Byte 2 of the extended mask

MSB of the extended destination

address

0x63

0x18

regUSERDESTID[3]

regUSERDESTID[2]

0x5A

0x0F

Byte 1 of the extended mask

MSB of the short mask

regUSERIDMASK[1]

regUSERIDMASK[0]

0x64

0x65

0x19

0x1A

Byte 2 of the extended destination

address

0x5B

0x5C

0x5D

0x10

0x11

0x12

LSB of the extended mask and short

mask

Byte 1 of the extended destination

address, MSB of the short destination

address

regUSERDESTID[1]

regUSERDESTID[0]

Figure 53: 250 Series User ID Mask Registers

LSB of the extended destination

address and short destination address

Figure 51: 250 Series User Destination ID Registers

Destination GUID

User Source ID

These registers contain the address of the destination module when GUID

Networking Mode is enabled. Please see the Networking Modes section for

more details. Each register byte is read and written separately.

These registers contain the address of the source module when User

Networking mode or Extended User Networking mode are enabled. User

Networking mode uses bytes 0 and 1 to determine the source address.

Extended User Networking mode uses all four bytes. Please see the

Networking Modes section for more details. Each register byte is read and

written separately.

Figure 54 shows the Destination ID Registers.

250 Series Destination GUID Registers

Volatile Non-Volatile

Name

Description

Address

Figure 52 shows the User Source ID Registers.

regDESTGUID[3]

regDESTGUID[2]

0x68

0x1D

MSB of the destination GUID

Byte 2 of the destination GUID

250 Series User Source ID Registers

0x69

0x1E

Volatile Non-Volatile

Name

Description

Byte 1 of the destination GUID

Address

regDESTGUID[1]

regDESTGUID[0]

0x6A

0x6B

0x1F

0x20

MSB of the short destination GUID

regUSERSRCID[3]

regUSERSRCID[2]

0x5E

0x13

MSB of the extended source address

Byte 2 of the extended source address

LSB of the extended and short

destination GUID

0x5F

0x14

Byte 1 of the extended source address

MSB of the short source address

regUSERSRCID[1]

regUSERSRCID[0]

0x60

0x61

0x15

0x16

Figure 54: 250 Series Destination GUID Registers

LSB of the extended source address

and short source address

Figure 52: 250 Series User Source ID Registers

–

49

48

Exception Mask - Address = 0x6C; NV Address = 0x21

CMD Halts Trafﬁc- Address = 0x6E; NV Address = 0x23

The module has a built-in exception engine that can notify the host

processor of an unexpected event. When an exception occurs, this register

is ANDed with the exception code. A non-zero result causes the EX line to

be asserted. Reading the regEXCEPTION register clears the exception and

resets the EX line. If the result is zero, the EX line is not asserted but the

exception code is stored in the regEXCEPTION register.

When conﬁguring the module’s register settings, it is possible that incoming

RF transmissions can intermix with the module’s response, making it

difﬁcult to determine if your commands were successfully processed.

Changing this register setting to 0x01 causes the module to store incoming

RF trafﬁc (up to the RF buffer overﬂow) while the CMD line is low. When the

CMD line is returned high, the module outputs all buffered data.

Figure 55 shows examples of the commands and Figure 56 shows the

available values.

Figure 57 shows examples of the commands and Figure 58 shows the

available values.

250 Series Exception Masks

250 Series CMD Halts Trafﬁc

Read Command

Read Response

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x6C

0xFE

0x6C

0x21

0x6E

0xFE

0x6E

0x23

0x02

0x21

0x23

Write Command

Header

0xFF

Size

Address

Value

V1

Header

0xFF

Size

Address

Value

V1

0x6C

0x21

0x6E

0x23

0x02

Figure 55: 250 Series Transceiver Exception Mask Command and Response

Figure 57: 250 Series Transceiver CMD Halts Trafﬁc Command and Response

250 Series Example Exception Masks

250 Series CMD Halts Trafﬁc Register Settings

V1

Exception Name

V1

Mode

0x08

0x10

0x20

Allows only EX_BUFOVFL and EX_RFOVFL to trigger the EX line

Allows only EX_WRITEREGFAILED to trigger the EX line

Allows only EX_NORFACK to trigger the EX line

0x00

0x01

Disable Halt

Enable Halt

Allows only EX_BADCRC, EX_BADHEADER, EX_BADSEQID and EX_

BADFRAMETYPE exceptions to trigger the EX line

0x40

Figure 58: 250 Series CMD Halts Trafﬁc Register Settings

Allows EX_BADCRC, EX_BADHEADER, EX_BADSEQID, EX_BADFRAMETYPE

and EX_NORFACK exceptions to trigger the EX line

0x60

0xFF

Allows all exceptions to trigger the EX line

Figure 56: 250 Series Transceiver Example Exception Masks

–

51

50

Receiver LNA Mode - Address = 0x6F; NV Address = 0x24

By default, the module is factory-conﬁgured to use its internal Automatic

Gain Control (AGC) circuit to manage receiver sensitivity. Reducing the gain

increases the linearity of the receiver, but reduces maximum sensitivity;

increasing the gain does the opposite. Generally speaking, higher

linearity (increased third order input intercept point, IIP3) gives improved

performance in high-interference environments; high gain yields better

performance in low-interference environments.

Compatibility Mode - Address = 0x70; NV Address = 0x25

Compatibility mode allows the 250 Series modules to communicate with

the 25 Series modules. Please see the Compatibility Mode section for more

details. Figure 61 shows examples of the commands and Figure 62 shows

the available values.

250 Series Compatibility Mode

Read Command

Read Response

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x70

0xFE

0x70

0x25

The module contains an AGC circuit that manages these settings

automatically, and it should be used whenever possible. When reading the

digital RSSI registers (regIMMEDRSSI, regLGPRSSI), the internal calculation

automatically compensates for the current LNA gain setting. However,

when attempting to make analog RSSI measurements, ﬁxing the LNA gain

produces more meaningful results.

0x02

0x25

Write Command

Header

0xFF

Size

Address

Value

V1

0x70

0x25

0x02

Figure 61: 250 Series Transceiver Compatibility Mode Command and Response

Figure 59 shows examples of the commands and Figure 60 shows the

available values.

250 Series Compatibility Mode Register Settings

250 Series LNA Mode

V1

Mode

Read Command

Read Response

0x00

0x01

Disable Compatibility Mode

Enable Compatibility Mode

Header

0xFF

Size

Escape Address

ACK

0x06

Address

Value

V1

0x6F

0xFE

0x6F

0x24

0x02

0x24

Figure 62: 250 Series Compatibility Mode Register Settings

Write Command

Header

0xFF

Size

Address

Value

V1

Auto Addressing - Address = 0x71; NV Address = 0x26

0x6F

0x24

When this register is enabled, the module reads the Source Address from

a received packet and uses it to ﬁll the Destination Address registers.

This makes sure that a response is sent to the device that transmitted the

original message.

0x02

Figure 59: 250 Series Transceiver LNA Mode Command and Response

250 Series LNA Mode Register Settings

The non-volatile register only uses the lower 4 bits to conﬁgure the

automatic addressing. The upper 4 bits are not used.

V1

Meaning

IIP3 Increase

Variable

Sensitivity Decrease

Variable

0x00

0x01

0x02

0x03

AGC Enabled

High Sensitivity

Mid Linearity

High Linearity

The volatile register is split in half with the lower 4 bits conﬁguring the

automatic addressing, the same as the non-volatile register.

Reference

19.1dB

Reference

6.5dB

41.8dB

9.5dB

The upper 4 bits indicate the type of packet that was last received. This

indication is the same as the Network Mode register setting. These bits

are not used by the module and are only written by the module after

successfully receiving a packet.

Figure 60: 250 Series Transceiver LNA Mode Register Settings

–

53

52

As an example, if regAUTADD is set to 0x0F (Any Auto Address) and a

GUID packet is received from another module, then regAUTADD reads

back as 0x4F. The lower 4 bits indicate that the module is set to any auto

address (0xF). The upper 4 bits indicate that the packet that was just

received was a GUID Network Mode packet (0x4).

My GUID

These registers contain the factory-programmed read-only GUID address.

This address is unique for each module and is used by all packet types as

a unique origination address.

Figure 65 shows the GUID Registers.

Figure 63 summarizes the conﬁguration values for the lower 4 bits of the

register.

250 Series GUID Registers

Non-Volatile

Name

Description

Address

250 Series Auto Addressing Register Settings

regMYGUID[3]

regMYGUID[2]

regMYGUID[1]

regMYGUID[0]

0x34

MSB of the GUID address

Byte 2 of the GUID address

Byte 1 of the GUID address

LSB of the GUID address

Auto Address Value Meaning

Action

0x35

Destination Registers not

populated

0x00

0x04

0x06

0x07

0x0F

Auto Addressing disabled

0x36

Auto-populates GUID Address

Destination Register Only

0x37

GUID Auto Address

Auto-populates User Address

Destination Register

User Auto Address Mode

Figure 65: 250 Series GUID Registers

Extended User Auto Address Auto-populates User Address

Mode

Destination Register

Release Number - NV Address = 0x78

Auto-populates GUID Address

Destination Register

This register contains a hard-coded release number corresponding to a

ﬁrmware version and hardware platform. Figure 66 shows examples of the

commands and Figure 67 lists current releases to date.

Any Auto Address Mode

Figure 63: 250 Series Transceiver Auto Addressing Register Settings

250 Series Release Number

Figure 64 shows the Network Mode values that the module writes to the

upper 4 bits after successfully receiving a packet.

Read Command

Read Response

Header

0xFF

Size

Escape Address

0xFE 0x78

ACK

0x06

Address

0x78

Value

V1

250 Series Auto Addressing Network Mode Indicator

0x02

Network Mode

Meaning

0x4

0x6

0x7

GUID Networking Mode

User Networking Mode

Extended User Networking Mode

Figure 66: 250 Series Transceiver Release Number Command and Response

250 Series Release Number Register Settings

V1

Release Number

1.0.5

Figure 64: 250 Series Transceiver Auto Addressing Network Mode Indicator

0x0D

0x10

0x11

0x14

1.0.5a

1.1.0

1.1.0 (Brazil)

Figure 67: 250 Series Transceiver Release Number Register Settings

–

55

54

Exception - Address = 0x79

Last Good Packet RSSI - Address = 0x7B

The module has a built-in exception engine that can notify the host

processor of an unexpected event. If an exception occurs, the exception

code is stored in this register. Reading from this register clears the

exception and, if applicable, resets the EX line. If an exception occurs

before the previous exception code is read, the previous value is

overwritten. Figure 68 shows examples of the commands and Figure 69

shows the available values.

This register holds the received signal strength in dBm of the last

successful received packet. A successful packet reception is one that

causes payload data to be output on the UART interface. The value in this

register is overwritten each time a new packet is successfully processed.

The register value is an 8-bit signed integer representing the RSSI in dBm.

It is accurate to 3dB and has 2dB linearity. The values take the LNA gain

into account.

250 Series Last Good Packet RSSI

250 Series Exception

Read Command

Read Response

Read Command

Read Response

Header

0xFF

Size

Escape Address

0xFE 0x7B

ACK

0x06

Address

0x7B

Value

V1

Header

0xFF

Size

Escape Address

0xFE 0x79

ACK

0x06

Address

0x79

Value

V1

0x02

Figure 71: 250 Series Transceiver Last Good Packet RSSI Command and Response

Figure 68: 250 Series Transceiver Exception Command and Response

250 Series Transceiver Exception Codes

Immediate RSSI - Address = 0x7C

This register returns the current receive signal strength indication in dBm.

The signal strength is measured as soon as the command is registered and

the value is loaded into the regIMMEDRSSI register. The register value is an

8-bit signed integer representing the RSSI in dBm. It is accurate to 3dB

and has 2dB linearity. The values take the LNA gain into account.

V1

Exception Name

EX_BUFOVFL

EX_RFOVFL

Description

0x08

0x09

0x13

Internal UART buffers overﬂowed.

Internal RF packet buffer overﬂowed.

EX_WRITEREGFAILED Attempted write to register failed.

Acknowledgement packet not received

EX_NORFACK

0x20

after maximum number of retries.

250 Series Immediate RSSI

0x40

0x42

0x43

0x44

EX_BADCRC

Bad CRC detected on incoming packet.

Bad CRC detected in packet header.

Sequence ID was incorrect in ACK packet.

Unsupported frame type speciﬁed.

Read Command

Read Response

EX_BADHEADER

EX_BADSEQID

Header

0xFF

Size

Escape Address

0xFE 0x7C

ACK

0x06

Address

0x7C

Value

V1

0x02

EX_BADFRAMETYPE

Figure 72: 250 Series Transceiver Immediate RSSI Command and Response

Figure 69: 250 Series Transceiver Exception Codes

Custom ID

These registers contain the factory-programmed custom ID. A value is

assigned to OEM customer with a custom version of the module. Contact

Linx for details. Figure 70 shows the GUID Registers.

250 Series Custom ID Registers

Non-Volatile

Address

Name

Description

regCUSTID[1]

regCUSTID[0]

0x39

MSB of the custom ID

LSB of the custom ID

0x3A

Figure 70: 250 Series Transceiver Custom ID

–

57

56

Typical Applications

Antenna Considerations

Figure 73 shows a circuit using the 250 Series transceiver.

The choice of antennas is a critical and

often overlooked design consideration.

The range, performance and legality of

an RF link are critically dependent upon

the antenna. While adequate antenna

performance can often be obtained by

trial and error methods, antenna design

and matching is a complex task.

VCC

GND

1

2

3

4

5

6

7

8

9

23

22

21

20

19

18

17

16

15

14

NC

TXD

NC

RESET

C2D

NC

CMD_RSP

EX

GND

ANT

GND

RXD

CTS

NC

BE

CMD

RSSI

GND

RXD

µ

GPIO

Figure 75: Linx Antennas

GPIO

10

Professionally designed antennas such as those from Linx (Figure 75) help

ensure maximum performance and FCC and other regulatory compliance.

Linx transmitter modules typically have an output power that is higher

than the legal limits. This allows the designer to use an inefﬁcient antenna

such as a loop trace or helical to meet size, cost or cosmetic requirements

and still achieve full legal output power for maximum range. If an efﬁcient

antenna is used, then some attenuation may be needed.

GND

Figure 73: 250 Series Transceiver Basic Application Circuit

The transceiver UART is connected to a microcontroller UART for

communication of conﬁguration data and data to be sent over the air. The

microcontroller is connected to the CMD-RSP, EX, CMD, BE and CTS

lines to monitor the current state of the module. It monitors the RSSI line to

monitor the strength of the incoming RF signal.

It is usually best to utilize a basic quarter-wave whip until your prototype

product is operating satisfactorily. Other antennas can then be evaluated

based on the cost, size and cosmetic requirements of the product.

Helpful Application Notes from Linx

There is no need for buffering or other circuitry between the transceiver and

microcontroller provided that both are operating on the same voltage.

It is not the intention of this manual to address in depth many of the issues

that should be considered to ensure that the modules function correctly

and deliver the maximum possible performance. We recommend reading

the application notes listed in Figure 76 which address in depth key areas

of RF design and application of Linx products. These applications notes

are available online at www.linxtechnologies.com or by contacting the Linx

literature department.

Power Supply Requirements

The module does not have an internal

Vcc TO

MODULE

voltage regulator, therefore it requires a clean,

well-regulated power source. The power supply

10Ω

noise should be less than 20mV. Power supply Vcc IN

noise can signiﬁcantly affect the module’s

performance, so providing a clean power supply

for the module should be a high priority during

+

Helpful Application Note Titles

10µF

Note Number

AN-00100

AN-00126

AN-00130

AN-00140

AN-00500

AN-00501

Note Title

RF 101: Information for the RF Challenged

Considerations for Operation Within the 902–928MHz Band

Modulation Techniques for Low-Cost RF Data Links

The FCC Road: Part 15 from Concept to Approval

Antennas: Design, Application, Performance

Understanding Antenna Speciﬁcations and Operation

design.

Figure 74: Supply Filter

A 10Ω resistor in series with the supply followed by a 10µF tantalum

capacitor from V_ccto ground helps in cases where the quality of supply

power is poor (Figure 74). This ﬁlter should be placed close to the module’s

supply lines. These values may need to be adjusted depending on the

noise present on the supply line.

Figure 76: Helpful Application Note Titles

–

59

58

Interference Considerations

Microstrip Details

The RF spectrum is crowded and the potential for conﬂict with unwanted

sources of RF is very real. While all RF products are at risk from

interference, its effects can be minimized by better understanding its

characteristics.

A transmission line is a medium whereby RF energy is transferred from

one place to another with minimal loss. This is a critical factor, especially

in high-frequency products like Linx RF modules, because the trace

leading to the module’s antenna can effectively contribute to the length

of the antenna, changing its resonant bandwidth. In order to minimize

loss and detuning, some form of transmission line between the antenna

and the module should be used unless the antenna can be placed very

close (<1/8in) to the module. One common form of transmission line is a

coax cable and another is the microstrip. This term refers to a PCB trace

running over a ground plane that is designed to serve as a transmission line

between the module and the antenna. The width is based on the desired

characteristic impedance of the line, the thickness of the PCB and the

dielectric constant of the board material. For standard 0.062in thick FR-4

board material, the trace width would be 111 mils. The correct trace width

can be calculated for other widths and materials using the information in

Figure 77 and examples are provided in Figure 78. Software for calculating

Interference may come from internal or external sources. The ﬁrst step

is to eliminate interference from noise sources on the board. This means

paying careful attention to layout, grounding, ﬁltering and bypassing in

order to eliminate all radiated and conducted interference paths. For

many products, this is straightforward; however, products containing

components such as switching power supplies, motors, crystals and other

potential sources of noise must be approached with care. Comparing your

own design with a Linx evaluation board can help to determine if and at

what level design-speciﬁc interference is present.

External interference can manifest itself in a variety of ways. Low-level

interference produces noise and hashing on the output and reduces the

link’s overall range.

microstrip lines is also available on the Linx website.

Trace

Board

High-level interference is caused by nearby products sharing the same

frequency or from near-band high-power devices. It can even come from

your own products if more than one transmitter is active in the same area.

It is important to remember that only one transmitter at a time can occupy

a frequency, regardless of the coding of the transmitted signal. This type of

interference is less common than those mentioned previously, but in severe

cases it can prevent all useful function of the affected device.

Ground plane

Although technically not interference, multipath is also a factor to be

understood. Multipath is a term used to refer to the signal cancellation

effects that occur when RF waves arrive at the receiver in different phase

relationships. This effect is a particularly signiﬁcant factor in interior

environments where objects provide many different signal reﬂection paths.

Multipath cancellation results in lowered signal levels at the receiver and

shorter useful distances for the link.

Figure 77: Microstrip Formulas

Example Microstrip Calculations

Width / Height

Ratio (W / d)

Effective Dielectric

Constant

Characteristic

Impedance (Ω)

Dielectric Constant

4.80

4.00

2.55

1.8

2.0

3.0

3.59

3.07

2.12

50.0

51.0

48.8

Figure 78: Example Microstrip Calculations

–

61

60

Pad Layout

Make sure internal wiring is routed away from the module and antenna and

is secured to prevent displacement.

The pad layout diagram in Figure 79 is designed to facilitate both hand and

automated assembly.

1.200”

(30.48mm)

Do not route PCB traces directly under the module. There should not be

any copper or traces under the module on the same layer as the module,

just bare PCB. The underside of the module has traces and vias that could

short or couple to traces on the product’s circuit board.

0.200”

(5.08mm)

0.400”

(10.16mm)

0.400”

(10.16mm)

0.150”

0.120”

(3.04mm)

(3.81mm)

The Pad Layout section shows a typical PCB footprint for the module. A

ground plane (as large and uninterrupted as possible) should be placed on

a lower layer of your PC board opposite the module. This plane is essential

for creating a low impedance return for ground and consistent stripline

performance.

0.130”

(3.30mm)

0.100”

(2.54mm)

1.200”

(30.48mm)

0.075”

(1.91mm)

Use care in routing the RF trace between the module and the antenna

or connector. Keep the trace as short as possible. Do not pass it under

the module or any other component. Do not route the antenna trace on

multiple PCB layers as vias add inductance. Vias are acceptable for tying

together ground layers and component grounds and should be used in

multiples.

0.120”

(3.04mm)

0.150”

(3.81mm)

Figure 79: Recommended PCB Layout

Board Layout Guidelines

The module’s design makes integration straightforward; however, it

is still critical to exercise care in PCB layout. Failure to observe good

layout techniques can result in a signiﬁcant degradation of the module’s

performance. A primary layout goal is to maintain a characteristic

50-ohm impedance throughout the path from the antenna to the module.

Grounding, ﬁltering, decoupling, routing and PCB stack-up are also

important considerations for any RF design. The following section provides

some basic design guidelines.

Each of the module’s ground pins should have short traces tying

immediately to the ground plane through a via.

Bypass caps should be low ESR ceramic types and located directly

adjacent to the pin they are serving.

A 50-ohm coax should be used for connection to an external antenna.

A 50-ohm transmission line, such as a microstrip, stripline or coplanar

waveguide should be used for routing RF on the PCB. The Microstrip

Details section provides additional information.

During prototyping, the module should be soldered to a properly laid-out

circuit board. The use of prototyping or “perf” boards results in poor

performance and is strongly discouraged. Likewise, the use of sockets

can have a negative impact on the performance of the module and is

discouraged.

In some instances, a designer may wish to encapsulate or “pot” the

product. There are a wide variety of potting compounds with varying

dielectric properties. Since such compounds can considerably impact

RF performance and the ability to rework or service the product, it is

the responsibility of the designer to evaluate and qualify the impact and

suitability of such materials.

The module should, as much as reasonably possible, be isolated from

other components on your PCB, especially high-frequency circuitry such as

crystal oscillators, switching power supplies, and high-speed bus lines.

When possible, separate RF and digital circuits into different PCB regions.

–

63

62

Reﬂow Temperature Proﬁle

Production Guidelines

The single most critical stage in the automated assembly process is the

reﬂow stage. The reﬂow proﬁle in Figure 82 should not be exceeded

because excessive temperatures or transport times during reﬂow will

irreparably damage the modules. Assembly personnel need to pay careful

attention to the oven’s proﬁle to ensure that it meets the requirements

necessary to successfully reﬂow all components while still remaining

within the limits mandated by the modules. The ﬁgure below shows the

The module is housed in a hybrid SMD package that supports hand and

automated assembly techniques. Since the modules contain discrete

components internally, the assembly procedures are critical to ensuring

the reliable function of the modules. The following procedures should be

reviewed with and practiced by all assembly personnel.

Hand Assembly

recommended reﬂow oven proﬁle for the modules.

Pads located on the bottom

of the module are the primary

300

Soldering Iron

Tip

Recommended RoHS Profile

Max RoHS Profile

Recommended Non-RoHS Profile

mounting surface (Figure 80).

Since these pads are inaccessible

during mounting, castellations

that run up the side of the module

have been provided to facilitate

solder wicking to the module’s

underside. This allows for very

255°C

250

200

150

100

50

235°C

217°C

Solder

185°C

180°C

PCB Pads

Castellations

125°C

Figure 80: Soldering Technique

quick hand soldering for prototyping and small volume production. If the

recommended pad guidelines have been followed, the pads will protrude

slightly past the edge of the module. Use a ﬁne soldering tip to heat the

board pad and the castellation, then introduce solder to the pad at the

module’s edge. The solder will wick underneath the module, providing

reliable attachment. Tack one module corner ﬁrst and then work around the

device, taking care not to exceed the times in Figure 81.

0

30

60

90

120

150

Time (Seconds)

180

210

240

270

300

330

360

Figure 82: Maximum Reﬂow Temperature Proﬁle

Shock During Reﬂow Transport

Since some internal module components may reﬂow along with the

Warning: Pay attention to the absolute maximum solder times.

Absolute Maximum Solder Times

components placed on the board being assembled, it is imperative that

the modules not be subjected to shock or vibration during the time solder

is liquid. Should a shock be applied, some internal components could be

lifted from their pads, causing the module to not function properly.

Hand Solder Temperature: +225ºC for 10 seconds

Reﬂow Oven: +225ºC max (see Figure 82)

Figure 81: Absolute Maximum Solder Times

Washability

The modules are wash-resistant, but are not hermetically sealed. Linx

recommends wash-free manufacturing; however, the modules can be

subjected to a wash cycle provided that a drying time is allowed prior

to applying electrical power to the modules. The drying time should be

sufﬁcient to allow any moisture that may have migrated into the module

to evaporate, thus eliminating the potential for shorting damage during

power-up or testing. If the wash contains contaminants, the performance

may be adversely affected, even after drying.

Automated Assembly

For high-volume assembly, the modules are generally auto-placed.

The modules have been designed to maintain compatibility with reﬂow

processing techniques; however, due to their hybrid nature, certain aspects

of the assembly process are far more critical than for other component

types. Following are brief discussions of the three primary areas where

caution must be observed.

–

65

64

plane as possible in proximity to the base of the antenna. In cases

where the antenna is remotely located or the antenna is not in close

proximity to a circuit board, ground plane or grounded metal case, a

metal plate may be used to maximize the antenna’s performance.

General Antenna Rules

The following general rules should help in maximizing antenna performance.

1. Proximity to objects such as a user’s hand, body or metal objects will

cause an antenna to detune. For this reason, the antenna shaft and tip

should be positioned as far away from such objects as possible.

5. Remove the antenna as far as possible from potential interference

sources. Any frequency of sufﬁcient amplitude to enter the receiver’s

front end will reduce system range and can even prevent reception

entirely. Switching power supplies, oscillators or even relays can also

be signiﬁcant sources of potential interference. The single best weapon

against such problems is attention to placement and layout. Filter the

module’s power supply with a high-frequency bypass capacitor. Place

adequate ground plane under potential sources of noise to shunt noise

to ground and prevent it from coupling to the RF stage. Shield noisy

board areas whenever practical.

2. Optimum performance is obtained from a ¼- or ½-wave straight whip

mounted at a right angle to the ground plane (Figure 83). In many

cases, this isn’t desirable for practical or ergonomic reasons, thus,

an alternative antenna style such as a helical, loop or patch may be

utilized and the corresponding sacriﬁce in performance accepted.

6. In some applications, it is advantageous to place the module and

antenna away from the main equipment (Figure 85). This can avoid

interference problems and allows the antenna to be oriented for

optimum performance. Always use 50Ω coax, like RG-174, for the

remote feed.

OPTIMUM

NOT RECOMMENDED

USABLE

Figure 83: Ground Plane Orientation

3. If an internal antenna is to be used, keep it away from other metal

components, particularly large items like transformers, batteries,

PCB tracks and ground planes. In many cases, the space around the

antenna is as important as the antenna itself. Objects in close proximity

to the antenna can cause direct detuning, while those farther away will

alter the antenna’s symmetry.

CASE

GROUND PLANE

(MAY BE NEEDED)

NUT

4. In many antenna designs, particularly ¼-wave whips, the ground plane

Figure 85: Remote Ground Plane

acts as a counterpoise, forming, in essence,

VERTICAL λ/4 GROUNDED

ANTENNA (MARCONI)

a ½-wave dipole (Figure 84). For this reason,

adequate ground plane area is essential.

The ground plane can be a metal case or

ground-ﬁll areas on a circuit board. Ideally, it

should have a surface area less than or equal

to the overall length of the ¼-wave radiating

element. This is often not practical due to

size and conﬁguration constraints. In these

instances, a designer must make the best use

of the area available to create as much ground

E

DIPOLE

ELEMENT

λ/4

I

GROUND

PLANE

VIRTUAL λ/4

λ/4

DIPOLE

Figure 84: Dipole Antenna

–

67

66

Loop Style

Common Antenna Styles

A loop or trace style antenna is normally printed

directly on a product’s PCB (Figure 89). This

makes it the most cost-effective of antenna

styles. The element can be made self-resonant or

externally resonated with discrete components,

but its actual layout is usually product speciﬁc.

Despite the cost advantages, loop style antennas

are generally inefﬁcient and useful only for short

range applications. They are also very sensitive to changes in layout and

PCB dielectric, which can cause consistency issues during production.

In addition, printed styles are difﬁcult to engineer, requiring the use of

expensive equipment including a network analyzer. An improperly designed

loop will have a high VSWR at the desired frequency which can cause

instability in the RF stage.

There are hundreds of antenna styles and variations that can be employed

with Linx RF modules. Following is a brief discussion of the styles most

commonly utilized. Additional antenna information can be found in Linx

Application Notes AN-00100, AN-00140, AN-00500 and AN-00501. Linx

antennas and connectors offer outstanding performance at a low price.

Figure 89: Loop or Trace Antenna

Whip Style

A whip style antenna (Figure 86) provides

outstanding overall performance and stability.

A low-cost whip can be easily fabricated from

a wire or rod, but most designers opt for the

consistent performance and cosmetic appeal of

a professionally-made model. To meet this need,

Linx offers a wide variety of straight and reduced

height whip style antennas in permanent and

Linx offers low-cost planar (Figure 90) and chip

antennas that mount directly to a product’s PCB.

These tiny antennas do not require testing and

provide excellent performance despite their small

size. They offer a preferable alternative to the often

problematic “printed” antenna.

connectorized mounting styles.

Figure 86: Whip Style Antennas

The wavelength of the operational frequency determines

234

an antenna’s overall length. Since a full wavelength

is often quite long, a partial ½- or ¼-wave antenna

is normally employed. Its size and natural radiation

resistance make it well matched to Linx modules.

The proper length for a straight ¼-wave can be easily

determined using the formula in Figure 87. It is also

possible to reduce the overall height of the antenna by

L =

F

MHz

Figure 87:

L = length in feet of

quarter-wave length

F = operating frequency

in megahertz

Figure 90: SP Series

“Splatch” Antenna

using a helical winding. This reduces the antenna’s bandwidth but is a great

way to minimize the antenna’s physical size for compact applications. This

also means that the physical appearance is not always an indicator of the

antenna’s frequency.

Specialty Styles

Linx offers a wide variety of specialized antenna

styles (Figure 88). Many of these styles utilize helical

elements to reduce the overall antenna size while

maintaining reasonable performance. A helical

antenna’s bandwidth is often quite narrow and the

Figure 88: Specialty Style

Antennas

antenna can detune in proximity to other objects, so

care must be exercised in layout and placement.

–

69

68

Questions regarding interpretations of the Part 2 and Part 15 rules or the

measurement procedures used to test intentional radiators such as Linx RF

modules for compliance with the technical standards of Part 15 should be

addressed to:

Regulatory Considerations

Note: Linx RF modules are designed as component devices that require

external components to function. The purchaser understands that

additional approvals may be required prior to the sale or operation of

the device, and agrees to utilize the component in keeping with all laws

governing its use in the country of operation.

Federal Communications Commission

Equipment Authorization Division

Customer Service Branch, MS 1300F2

7435 Oakland Mills Road

Columbia, MD, US 21046

Phone: + 1 301 725 585 | Fax: + 1 301 344 2050

Email: labinfo@fcc.gov

When working with RF, a clear distinction must be made between what

is technically possible and what is legally acceptable in the country where

operation is intended. Many manufacturers have avoided incorporating RF

into their products as a result of uncertainty and even fear of the approval

and certiﬁcation process. Here at Linx, our desire is not only to expedite the

design process, but also to assist you in achieving a clear idea of what is

involved in obtaining the necessary approvals to legally market a completed

product.

ETSI Secretaria

650, Route des Lucioles

06921 Sophia-Antipolis Cedex

FRANCE

Phone: +33 (0)4 92 94 42 00

Fax: +33 (0)4 93 65 47 16

For information about regulatory approval, read AN-00142 on the Linx

website or call Linx. Linx designs products with worldwide regulatory

approval in mind.

International approvals are slightly more complex, although Linx modules

are designed to allow all international standards to be met. If the end

product is to be exported to other countries, contact Linx to determine the

speciﬁc suitability of the module to the application.

In the United States, the approval process is actually quite straightforward.

The regulations governing RF devices and the enforcement of them are

the responsibility of the Federal Communications Commission (FCC). The

regulations are contained in Title 47 of the United States Code of Federal

Regulations (CFR). Title 47 is made up of numerous volumes; however,

all regulations applicable to this module are contained in Volume 0-19.

It is strongly recommended that a copy be obtained from the FCC’s

website, the Government Printing Ofﬁce in Washington or from your local

government bookstore. Excerpts of applicable sections are included

with Linx evaluation kits or may be obtained from the Linx Technologies

website, www.linxtechnologies.com. In brief, these rules require that any

device that intentionally radiates RF energy be approved, that is, tested for

compliance and issued a unique identiﬁcation number. This is a relatively

painless process. Final compliance testing is performed by one of the many

independent testing laboratories across the country. Many labs can also

provide other certiﬁcations that the product may require at the same time,

such as UL, CLASS A / B, etc. Once the completed product has passed,

an ID number is issued that is to be clearly placed on each product

manufactured.

All Linx modules are designed with the approval process in mind and thus

much of the frustration that is typically experienced with a discrete design is

eliminated. Approval is still dependent on many factors, such as the choice

of antennas, correct use of the frequency selected and physical packaging.

While some extra cost and design effort are required to address these

issues, the additional usefulness and proﬁtability added to a product by RF

makes the effort more than worthwhile.

–

71

70


型号：	EVM-915-250-CFS
厂家：	Linx Technologies
描述：	TRM-915-R250 RF Transceiver Module
文件：	总39页 (文件大小：2156K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVM-915-250-CFS [LINX]

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