SP721 [LITTELFUSE]
Electronic Protection Array for ESD and Overvoltage Protection; 用于ESD和过压保护的电子保护阵列
| 型号： | SP721 |
| 厂家： | 
LITTELFUSE |
| 描述： | Electronic Protection Array for ESD and Overvoltage Protection |
| 文件： | 总6页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
The SP721 is an array of SCR/Diode bipolar structures for ESD and
over-voltage protection to sensitive input circuits. The SP721 has 2
protection SCR/Diode device structures per input. There are a total of
6 available inputs that can be used to protect up to 6 external signal or
bus lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins
5 - 7) to V+ or V-.
The SCR structures are designed for fast triggering at a threshold of one
+V
diode threshold above V+ (Pin 8) or a -V
diode threshold below
BE
BE
V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient
pulse causes the input to be increased to a voltage level greater than
one V
one V
above V+. A similar clamp to V- is activated if a negative pulse,
less than V-, is applied to an IN input. Standard ESD Human
BE
BE
Body Model (HBM) Capability is:
Features
HBM
STANDARD
• ESD Interface Capability for HBM Standards
MODE
R
C
ESD (V)
>15kV
>4kV
- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV
- IEC 61000-4-2, Direct Discharge,
- Single Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2)
- Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4)
IEC 61000-4-2
Air
330Ω 150pF
330Ω 150pF
330Ω 150pF
1.5kΩ 100pF
Direct
Direct, Dual Pins
>8kV
MIL-STD-3015.7 Direct, In-Circuit
>15kV
• High Peak Current Capability
- IEC 61000-4-5 (8/20µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A
- Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . ±2A
- Single Pulse, 4µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . ±5A
Refer to Figure 1 and Table 1 for further detail. Refer to Application
Notes AN9304 and AN9612 for additional information.
• Designed to Provide Over-Voltage Protection
Ordering Information
- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V
- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
TEMP. RANGE
PKG.
NO.
Min.
Order
o
PART NO.
SP721AP
( C)
PACKAGE
8 Ld PDIP
• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Rise Time
• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25oC Typical
• Low Input Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF Typical
• An Array of 6 SCR/Diode Pairs
-40 to 105
-40 to 105
-40 to 105
E8.3
2000
SP721AB
8 Ld SOIC
M8.15
M8.15
1960
2500
SP721ABT
8 Ld SOIC
Tape and Reel
• Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40oC to 105oC
Pinout
Applications
• Microprocessor/Logic Input Protection
SP721 (PDIP, SOIC)
TOP VIEW
• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp
IN
IN
IN
V-
1
2
3
4
8
7
6
5
V+
IN
IN
IN
Functional Block Diagram
V+
IN
V-
8
1
4
3, 5-7
IN
2
IN
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Absolute Maximum Ratings
Thermal Information
(oC/W)
JA
Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +35V
Thermal Resistance (Typical, Note 1)
θ
Forward Peak Current, I to V
IN
, I to GND
CC IN
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Maximum Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature (Plastic Package) . . . .. . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . . .. . . . . . . . . . . .300oC
(SOIC Lead Tips Only)
(Refer to Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2A, 100µs
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications T A = -40oC to 105oC, V = 0.5V
, Unless Otherwise Specified
IN CC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range,
V
-
2 to 30
-
V
SUPPLY
V
= [(V+) - (V-)]
SUPPLY
Forward Voltage Drop
IN to V-
IN to V+
V
I
= 1A (Peak Pulse)
IN
-
-
2
2
-
-
V
V
FWDL
V
FWDH
Input Leakage Current
Quiescent Supply Current
Equivalent SCR ON Threshold
Equivalent SCR ON Resistance
Input Capacitance
I
-20
5
50
1.1
1
+20
nA
nA
V
IN
QUIESCENT
5
I
-
-
-
-
-
200
Note 3
/I
-
-
-
-
V
; Note 3
Ω
FWD FWD
C
3
pF
ns
IN
Input Switching Speed
NOTES:
t
2
ON
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the
V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should
be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- Pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here
for thumb-rule information to determine peak current and dissipation under EOS conditions.
TABLE 1. ESD TEST CONDITIONS
ESD Capability
ESD capability is dependent on the application and defined test standard.The
STANDARD
TYPE/MODE
R
C
±V
D
D
D
evaluation results for various test standards and methods based on Figure 1
are shown in Table 1.
MIL-STD-3015.7 Modified HBM
Standard HBM
1.5kΩ 100pF 15kV
1.5kΩ 100pF 6kV
For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit”
method of ESD testing, the V+ and V- pins have a return path to ground and
the SP721 ESD capability is typically greater than 15kV from 100pF through
1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing,
the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results
were determined from AT&T ESD Test Lab measurements.
IEC 61000-4-2
EIAJ IC121
HBM, Air Discharge
330Ω 150pF 15kV
HBM, Direct Discharge 330Ω 150pF 4kV
HBM, Direct Discharge, 330Ω 150pF 8kV
Two Parallel Input Pins
Machine Model
0kΩ 200pF 1kV
The HBM capability to the IEC 61000-4-2 standard is greater than 15kV
for air discharge (Level 4) and greater than 4kV for direct discharge
(Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess
of 8kV (Level 4).
R
D
R
1
CHARGE
SWITCH
DISCHARGE
SWITCH
C
D
IN
H.V.
For ESD testing of the SP721 to EIAJ IC121 Machine Model (MM) standard,
the results are typically better than 1kV from 200pF with no series resistance.
SUPPLY
DUT
±V
D
IEC 1000-4-2: R 50 to 100MΩ
1
MIL-STD-3015.7:R 1 to 10MΩ
1
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
100
80
2.5
2
o
o
C
T
= 25
C
T
= 25
A
A
SINGLE PULSE
SINGLE PULSE
60
1.5
1
40
20
0
I
FWD
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
V
FWD
0.5
0
600
800
1000
1200
0
1
2
3
FORWARD SCRVOLTAGE DROP (mV)
FORWARD SCRVOLTAGE DROP (V)
FIGURE 2. LOW CURRENT SCR FORWARDVOLTAGE DROP
CURVE
FIGURE 3. HIGH CURRENT SCR FORWARDVOLTAGE DROP
CURVE
+V
+V
CC
CC
INPUT
DRIVERS
OR
SIGNAL
SOURCES
LINEAR OR
DIGITAL IC
INTERFACE
TO +V
V+
IN 1 - 3
IN 5 - 7
CC
SP721
V-
SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN)
FIGURE 4. TYPICALAPPLICATION OFTHE SP721 AS AN INPUT CLAMPFOR OVER-VOLTAGE, GREATERTHAN 1V ABOVE V+ OR
BE
LESSTHAN -1V
BELOW V-
BE
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Peak Transient Current Capability of the SP721
VARIABLETIME DURATION
CURRENT PULSE GENERATOR
The peak transient current capability rises sharply as the width of the
current pulse narrows. Destructive testing was done to fully evaluate the
SP721’s ability to withstand a wide range of peak current pulses vs time.
The circuit used to generate current pulses is shown in Figure 5.
+
R
1
V
X
CURRENT
SENSE
-
(-)
The test circuit of Figure 5 is shown with a positive pulse input. For a
negative pulse input, the (-) current pulse input goes to an SP721 ‘IN’
input pin and the (+) current pulse input goes to the SP721 V- pin. The
V+ to V- supply of the SP721 must be allowed to float. (i.e., It is not tied
to the ground reference of the current pulse generator.) Figure 6 shows
the point of overstress as defined by increased leakage in excess of the
data sheet published limits.
(+)
1
IN
IN
IN
V-
V+
IN
IN
IN
8
7
6
5
2
3
4
SP721
+
-
C1
VOLTAGE
PROBE
The maximum peak input current capability is dependent on the ambient
temperature, improving as the temperature is reduced. Peak current
curves are shown for ambient temperatures of 25oC and 105oC and a 15V
power supply condition. The safe operating range of the transient peak
current should be limited to no more than 75% of the measured over-
stress level for any given pulse width as shown in the curves of Figure 6.
R
~ 10Ω TYPICAL
ADJ. 10V/ATYPICAL
1
V
X
C1 ~ 100µF
Note that adjacent input pins of the SP721 may be paralleled to improve
current (and ESD) capability. The sustained peak current capability is
increased to nearly twice that of a single pin.
FIGURE 5. TYPICAL SP721 PEAK CURRENT TEST CIRCUIT
WITH AVARIABLEPULSEWIDTH INPUT
5
7
CAUTION: SAFE OPERATING CONDITIONS LIMIT
THE MAXIMUM PEAK CURRENT FOR A GIVEN
6
5
4
3
2
1
0
PULSEWIDTH TO BE NO GREATER THAN 75%
OF THE VALUES SHOWN ON EACH CURVE.
o
T
= 25 C
A
V+ TO V- SUPPLY = 15V
o
T
= 105 C
A
0.001
0.01
0.1
1
10
100
1000
PULSEWIDTH TIME (ms)
FIGURE 6. SP721TYPICALSINGLE PULSE PEAKCURRENT CURVES SHOWINGTHE MEASURED POINT OF OVERSTRESS IN
AMPERES vsPULSEWIDTH TIME IN MILLISECONDS
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
N
E1
INDEX
AREA
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
D
E
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
A
-
1
D1
e
eC
B S
C
D
5
5
6
5
-
B
eB
D1
E
0.010 (0.25) M
C
A
0.325
0.280
8.25
7.11
NOTES:
E1
e
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
7
4
9
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
-
0.430
0.150
-
10.92
3.81
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
L
0.115
2.93
N
8
8
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
N
INDEX
AREA
0.25(0.010)
M
B M
H
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
E
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
-B-
1
2
3
L
9
-
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
SEATING PLANE
A
3
4
-
-A-
o
h x 45
D
-C-
0.050 BSC
1.27 BSC
µ
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
6
7
-
B
0.10(0.004)
L
0.25(0.010) M
C
A M B S
N
µ
8
8
NOTES:
o
o
o
o
0
8
0
8
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
5
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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