L29C520PC22 [LOGIC]
Pipeline Register ; 管线注册\n
| 型号： | L29C520PC22 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Pipeline Register
|
| 文件： | 总8页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L29C520/521
4 x 8-bit Multilevel Pipeline Register
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The S1-0 select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
❑ Four 8-bit Registers
❑ ImplementsDouble2-StagePipeline
or Single 4-Stage Pipeline Register
❑ Hold, Shift, and Load Instructions
❑ Separate Data In and Data Out Pins
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
❑ High-Speed,LowPowerCMOS
Technology
❑ Three-State Outputs
TABLE 1.
L29C520 INSTRUCTION TABLE
❑ Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
The Instruction pins, I1-0, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I1-0
may be set to prevent any register
from changing.
❑ Package Styles Available:
I1 I0 Description
• 24-pin PDIP
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
• 28-pinPLCC, J-Lead
HOLD HOLD
D➞R3
R3➞R4
H
H
D➞R1 R1➞R2 HOLD
HOLD
H
ALL REGISTERS ON HOLD
TABLE 2.
L29C521 INSTRUCTION TABLE
I1 I0 Description
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
HOLD HOLD
D➞R3
HOLD
HOLD
H
H
D➞R1 HOLD
HOLD
L29C520/521 BLOCK DIAGRAM
H
ALL REGISTERS ON HOLD
TABLE 3. OUTPUT SELECT
S1 S0 Register Selected
8
L
L
L
H
L
Register 4
Register 3
Register 2
Register 1
D8-0
REG 1
H
H
8
REG 2
Y
7-0
H
REG 3
REG 4
OE
2
S
1-0
2
I
1-0
CLK
Pipeline Registers
08/02/2000–LDS.520/1-P
1
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –15.0 mA
VCC = Min., IOL = 24.0 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Input Current
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
ICC1
ICC2
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
30 mA
1.5 mA
(Note 7)
Pipeline Registers
08/02/2000–LDS.520/1-P
2
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
L29C520/521–
22
14*
Symbol Parameter
Min
Max
Min
Max
tPD
tSEL
tPW
tSI
Clock to Output Delay
22
14
Select to Output Delay
20
13
Clock Pulse Width
10
10
3
7
5
1
5
1
Instruction Setup Time
tHI
Instruction Hold Time
tSD
tHD
tENA
tDIS
Data Setup Time
10
3
Data Hold Time
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
21
15
15
12
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
L29C520/521–
*
30
*
24
*
16
Symbol Parameter
Min
Max
Min
Max
Min
Max
tPD
tSEL
tPW
tSI
Clock to Output Delay
30
24
16
Select to Output Delay
30
22
15
Clock Pulse Width
15
15
5
10
10
3
8
6
2
6
2
Instruction Setup Time
tHI
Instruction Hold Time
tSD
tHD
tENA
tDIS
Data Setup Time
15
5
10
3
Data Hold Time
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
25
20
22
16
16
13
*DISCONTINUED SPEED GRADE
SWITCHING WAVEFORMS
I
1-0
t
SI
tHI
D7-0
t
SD
tHD
t
PW
CLK
tPW
S1-0
t
PD
t
SEL
OE
tDIS
tENA
HIGH IMPEDANCE
Y7-0
Pipeline Registers
08/02/2000–LDS.520/1-P
3
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
11. For the tENA test, the transition is
ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
tended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulationsofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/turn-off times.
Asaresult, caremustbeexercisedinthe
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
V
TH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtestconditionsmayvaryfrom
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH*
Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tioncanbeaccuratelyapproximatedby:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximumsinceworst-caseoperationof
anydevicealwaysprovidesdatawithin
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Pipeline Registers
08/02/2000–LDS.520/1-P
4
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C520 — ORDERING INFORMATION
24-pin — 0.3" wide
28-pin
1
24
23
22
21
20
19
18
17
16
15
14
13
V
S
S
Y
Y
Y
Y
Y
Y
Y
Y
CC
I
I
0
1
0
1
2
3
4
5
6
7
2
0
4
3
2
1
28 27 26
25
3
1
D
D
D
D
D
D
D
D
5
D
D
D
D
D
D
1
2
3
4
5
6
NC
4
0
6
24
23
22
21
20
19
Y0
Y1
Y2
Y3
Y4
Y5
5
1
7
6
2
Top
View
8
7
3
9
8
4
10
11
9
5
NC
10
11
12
6
12 13 14 15 16 17 18
7
CLK
OE
GND
Plastic DIP
(P2)
Plastic J-Lead Chip Carrier
(J4)
Speed
0°C to +70°C — COMMERCIAL SCREENING
22 ns
L29C520PC22
L29C520JC22
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Pipeline Registers
08/02/2000–LDS.520/1-P
5
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C520 — ORDERING INFORMATION
24-pin
24-pin — 0.209" wide
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
I
I
0
1
0
1
2
3
4
5
6
7
V
S
S
Y
Y
Y
Y
Y
Y
Y
Y
CC
0
I
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
V
S
S
Y
Y
Y
Y
Y
Y
Y
Y
CC
0
I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
1
0
0
1
1
2
2
3
3
4
4
9
5
5
10
11
12
6
10 15
11 14
12 13
6
CLK
GND
7
CLK
7
OE
GND
OE
Discontinued Package
Discontinued Package
Ceramic Flatpack
(M1)
Plastic SSOP
(S1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
22 ns
Pipeline Registers
08/02/2000–LDS.520/1-P
6
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C521 — ORDERING INFORMATION
24-pin — 0.3" wide
28-pin
1
24
23
22
21
20
19
18
17
16
15
14
13
V
S
S
Y
Y
Y
Y
Y
Y
Y
Y
CC
I
0
1
0
1
2
3
4
5
6
7
2
0
I
4
3
2
1
28 27 26
25
3
1
D
D
D
D
D
D
D
D
5
D
D
D
D
D
D
1
2
3
4
5
6
NC
4
0
6
24
23
22
21
20
19
Y0
Y1
Y2
Y3
Y4
Y5
5
1
7
6
2
Top
View
8
7
3
9
8
4
10
11
9
5
NC
10
11
12
6
12 13 14 15 16 17 18
7
CLK
OE
GND
Discontinued Package
Plastic DIP
(P2)
Plastic J-Lead Chip Carrier
(J4)
Speed
0°C to +70°C — COMMERCIAL SCREENING
22 ns
L29C521PC22
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Pipeline Registers
08/02/2000–LDS.520/1-P
7
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C521 — ORDERING INFORMATION
24-pin
I
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
V
S
S
Y
Y
Y
Y
Y
Y
Y
Y
CC
0
I
D
D
D
D
D
D
D
D
1
0
1
2
3
4
9
5
10
11
12
6
CLK
GND
7
OE
Discontinued Package
Ceramic Flatpack
(M1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Pipeline Registers
08/02/2000–LDS.520/1-P
8
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