L29C818KMB30 [LOGIC]

Pipeline Register, 8-Bit, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28;


型号：	L29C818KMB30
厂家：	LOGIC DEVICES INCORPORATED
描述：	Pipeline Register, 8-Bit, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28 外围集成电路
文件：	总10页 (文件大小：105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

L29C818

8-bit Serial Scan Shadow Register

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L29C818 is a high-speed octal

Also, data present on the SDI pin is

loaded into the least significant

❑ Octal Register with Additional 8-bit

Shiftable Shadow Register

applications using serial-scan diagnos- position of the S register on the rising

❑ Serial Load/ Verify of Writable

tics or writable control store. It is pin

and functionally compatible with the

AMD Am29818 bipolar device.

edge of CLK S. In this mode, the S

tion with the contents of each bit

position replaced by the value in the

next least significant location. The

value in S7 is shifted out on the serial

data output (SDO) pin. The SDI and

SDO pins allow serial connection of

multiple L29C818 devices into a

diagnostic loop. When MODE is

LOW, the operation of the P and S

registers are completely independent

and no timing relationship is enforced

between CLK P and CLK S.

Control Store RAM

❑ Serial Stimulus/ Observation of

Sequential Logic

❑ High-Speed, Low Power CMOS

The L29C818 consists of an octal

connected to an 8-bit shift register, the

S register. Each has its own corres-

ponding clock pin and the P register

has a three-state output control.

Technology

❑ Replaces AMD Am29818

❑ DECC SMD No. 5962-90515

❑ Available 100% Screened to

MIL-STD-883, Class B

An input control signal, MODE, in

combination with the S register serial

data input (SDI) pin controls data

routing within the L29C818. When

the MODE input is LOW, indicating

normal operation, data present on the

D7-0 pins is loaded into the P register

on the rising edge of CLK P. The

contents of the P register are visible on

the output pins Y7-0 when the OE

control line is LOW.

❑ Package Styles Available:

• 24-pin Plastic DIP

• 24-pin Sidebraze, Hermetic DIP

• 28-pin Ceramic LCC

When MODE is HIGH, the internal

multiplexers route data between the S

and P registers and the Y port. The

contents of the S register are loaded

into the P register on the rising edge of

L29C818 BLOCK DIAGRAM

SDI

SDO

CLK S

MODE

S REGISTER

S7-0

SDI

D7-0

SDO

MODE

D Q

MUX

CLK S

CLK P

P REGISTER

P7-0

OBSOLETE

S REGISTER

Y7-0

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

CLK P. In diagnostic applications, this is required. When MODE is HIGH,

D output remains enabled until the

first rising edge of CLK S during

allows a data value input via serial

scan to be loaded into the active data

path of the machine.

the SDI input drives the SDO output

directly, bypassing the S register. This which either SDI or MODE is LOW.

means that the SDI value will apply

simultaneously to all L29C818s in a

serial loop. However, to ensure

proper operation of a given device,

the user must ensure that the SDI

setup time to CLK S is extended by

the sum of the SDI to SDO delays of

Thus to load a control store RAM,

data would be shifted in with MODE

LOW. When an entire control store

word is present in the serial S regis-

ters, the SDI and MODE pins are

brought HIGH for one or more cycles,

preventing further shifting of the S

When the MODE pin is HIGH, CLK S

causes a parallel, rather than serial,

load of the S register. In this mode,

the S register is loaded from the Y7-0

pins at the rising edge of CLK S. This

is useful in writable control store

applications for read-back of the

control store via the serial path.

all previous devices in the serial path. registers and enabling the contents

onto the D port for writing into the

The D7-0 port is normally used as the

RAM.

input port to the D register. For

When MODE is HIGH, the SDI pin is

used as a control input to enable or

disable the loading of the S register. It

also affects routing of the S register

contents onto the D7-0 outputs. When

SDI is LOW, the S register is enabled

for loading as above. When SDI is

HIGH however, CLK S is prevented

from reaching the S register and no

load occurs. In order to allow the SDI

pin to serve as an enable signal for all

L29C818 devices in a serial configura-

tion, special handling of the SDI input

writable control store applications

however, this port is connected to the

I/ O pins of the RAM used as a control D register in the normal fashion.

store. In order to load this RAM Then, the D contents are transferred in

through the serial path, it is necessary parallel to the S register by driving

to drive the S register contents onto

the D7-0 pins. This is accomplished

when MODE and SDI are HIGH and a serially by returning MODE LOW and

CLK S rising edge occurs. Note from

above that with SDI HIGH, no loading

of the S register occurs. However, a

flip-flop is set which synchronously

enables the D port output buffer. The

To verify the contents of a control

store RAM, the RAM is read into the

MODE HIGH with SDI LOW. The S

applying CLK S pulses.

TABLE 1. FUNCTION TABLE

Inputs

Outputs

Action

MODE

SDI

CLK S

CLK P

P REG

N/A

S REG

SHIFT

N/A

Y7-0

D7-0

HI-Z

SDO

Normal

Input*

LOAD D

N/A

Input

HI-Z

LOAD Y

HOLD

N/A

SDI

N/A

Normal

Output

HI-Z

LOAD S

*If OE is LOW, the P register value will be loaded into the S register. If OE is HIGH, a value may be applied externally to the Y7-0 pins.

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

OPERATING CONDITIONS To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

0°C to +70°C

Supply Voltage

4.75 V ≤ VCC ≤ 5.25 V

4.50 V ≤ VCC ≤ 5.50 V

Active Operation, Commercial

Active Operation, Military

–55°C to +125°C

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Symbol Parameter

Test Condition

Min

Typ

Max Unit

VOH

VOL

VIH

Output High Voltage

VCC = Min., IOH = –12.0 mA

VCC = Min., IOL = 24.0 mA

2.4

Output Low Voltage

Input High Voltage

Input Low Voltage

0.5

VCC

0.8

2.0

0.0

VIL

(Note 3)

IIX

Input Current

Ground ≤ VIN ≤ VCC (Note 12)

Ground ≤ VOUT ≤ VCC (Note 12)

(Notes 5, 6)

±20

µA

IOZ

ICC1

ICC2

Output Leakage Current

VCC Current, Dynamic

VCC Current, Quiescent

15 mA

1.0 mA

(Note 7)

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

SWITCHING CHARACTERISTICS — NORMAL REGISTER OPERATION

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tPWP

tPDY

tSDP

tHDP

tSMP

tHMP

tENA

tDIS

CLK P Pulse Width

CLK P to Y7-0

D7-0 to CLK P Setup Time

CLK P to D7-0 Hold Time

MODE to CLK P Setup Time

CLK P to MODE Hold Time

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tPWP

tPDY

tSDP

tHDP

tSMP

tHMP

tENA

tDIS

CLK P Pulse Width

CLK P to Y7-0

D7-0 to CLK P Setup Time

CLK P to D7-0 Hold Time

MODE to CLK P Setup Time

CLK P to MODE Hold Time

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

SWITCHING WAVEFORMS — NORMAL REGISTER OPERATION

MODE

tSMP

tSDP

tHMP

D^7-0

tHDP

tPWP

CLK P

Y^7-0

tPWP

HIGH IMPEDANCE

OBSOLETE

tPDY

tENA

tDIS

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

SWITCHING CHARACTERISTICS — SERIAL SHIFT OPERATION

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tPWS

tDSSO

tSSIS

tHSSI

tSMS

CLK S Pulse Width

CLK S to SDO

SDI to CLK S Setup Time

CLK S to SDI Hold Time

MODE to CLK S Setup Time

CLK S to MODE Hold Time

MODE to SDO

tHSM

tDMSO

tDSISO

SDI to SDO

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tPWS

tDSSO

tSSIS

tHSSI

tSMS

CLK S Pulse Width

CLK S to SDO

SDI to CLK S Setup Time

CLK S to SDI Hold Time

MODE to CLK S Setup Time

CLK S to MODE Hold Time

MODE to SDO

tHSM

tDMSO

tDSISO

SDI to SDO

SWITCHING WAVEFORMS — SERIAL SHIFT OPERATION

MODE

tSMS

tHSM

SDI

tSSIS

tHSSI

CLK S

tPWS

tDMSO

tDSISO

tPWS

SDO

OBSOLETE

tDSSO

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

SWITCHING CHARACTERISTICS — PIPELINE LOAD FROM SHADOW

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSMP

tHPM

tSSP

MODE to CLK P

CLK P to MODE Hold Time

CLK S to CLK P

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSMP

tHPM

tSSP

MODE to CLK P

CLK P to MODE Hold Time

CLK S to CLK P

SWITCHING WAVEFORMS — PIPELINE LOAD FROM SHADOW

MODE

SMP

tHPM

CLK P

CLK S

SSP

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

SWITCHING CHARACTERISTICS — SHADOW LOAD FROM Y PORT

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSYS

tHSY

tSMS

tHSM

tSSIS

tHSSI

Y7-0 to CLK S Setup Time

CLK S to Y7-0 Hold Time

MODE to CLK S Setup Time

CLK S to MODE Hold Time

SDI to CLK S Setup Time

CLK S to SDI Hold Time

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSYS

tHSY

tSMS

tHSM

tSSIS

tHSSI

Y7-0 to CLK S Setup Time

CLK S to Y7-0 Hold Time

MODE to CLK S Setup Time

CLK S to MODE Hold Time

SDI to CLK S Setup Time

CLK S to SDI Hold Time

SWITCHING WAVEFORMS — SHADOW LOAD FROM Y PORT

EXTERNALLY DRIVEN

Y7-0

SYS

HSY

CLK S

MODE

SDI

SMS

SSIS

tHSM

HSSI

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

SWITCHING CHARACTERISTICS — SHADOW READ VIA D PORT

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSMS

tHSM

tSSIS

tHSSI

tENAD

tDISD

MODE to CLK S Setup Time

CLK S to MODE Hold Time

SDI to CLK S Setup Time

CLK S to SDI Hold Time

CLK S to D7-0 Enable Delay (Note 11)

CLK S to D7-0 Disable Delay (Note 11)

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C818–

Symbol Parameter

Min

Max

tSMS

tHSM

tSSIS

tHSSI

tENAD

tDISD

MODE to CLK S Setup Time

CLK S to MODE Hold Time

SDI to CLK S Setup Time

CLK S to SDI Hold Time

CLK S to D7-0 Enable Delay (Note 11)

CLK S to D7-0 Disable Delay (Note 11)

SWITCHING WAVEFORMS — SHADOW READ VIA D PORT

MODE

SMS

SSIS

HSM

SMS

HSM

HSSI

SDI

HSSI

ENAD

tSSIS

CLK S

DISD

HIGH IMPEDANCE

D7-0

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

NOTES

1. Maximum Ratings indicate stress 9. AC specifications are tested with

specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point

11. For the tENA test, the transition is

ation ofthese products at values beyond output reference levels of 1.5 V (except

those indicated in the Operating Condi-

with datasheet loads. For the tDIS test,

the transition is m easu red to the

tDIS test), and input levels of nominally

tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200m V level from the m easured

maximum rating conditions for ex- resistive divider which provides for steady-state ou tp u t v oltage w ith

tended periods may affect reliability.

±10m A load s. The balancing volt-

age, VTH , is set at 3.5 V for Z-to-0

specified IOH and IOL at an output

voltage of VOH min and VOL max

2. The products described by this spec-

ification include internal circuitry de-

signed to protect the chip from damag-

ing substrate injection currents and ac-

cumulations ofstaticcharge. Neverthe-

less, conventional precautions should

be observed during storage, handling,

and use of these circuits in order to This device has high-speed outputs ca-

avoid exposure to excessive electrical pable of large instantaneous current

respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-

bridge with upper and lower current to-1 and 1-to-Z tests.

sources of IOH and IOL respectively,

12. These parameters are only tested at

and a balancing voltage of 1.5 V may be

the high temperature extreme, which is

used. Parasitic capacitance is 30 pF

the worst case for leakage current.

minimum, and may be distributed.

FIGURE A. OUTPUT LOADING CIRCUIT

stress values.

pulses and fast turn-on/ turn-off times.

As a result, care must be exercised in the

testing of this device. The following

measures are recommended:

DUT

3. Thisdeviceprovideshard clamping of

transient undershoot and overshoot. In-

put levels below ground or above VCC

will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be

VCC + 0.6 V. The device can withstand installed between VCC and Ground

indefinite operation with inputs in the leads as close to the Device Under Test

range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors

FIGURE B. THRESHOLD LEVELS

ENA

tDIS

tion will not be adversely affected, how-

ever, input current levels will be well in and the tester common, and device

should be installed between device VCC

1.5 V

excess of 100 mA.

ground and tester common.

3.5V Vth

1.5 V

0.2 V

4. Actualtest conditions may vary from

b. Ground and VCC supply planes

those designated but operation is guar- must be brought directly to the DUT

anteed as specified. socket or contactor fingers.

0V Vth

VOL*

Measured VOL with IOH = –10mA and IOL = 10mA

5. Supply current for a given applica- c. Input voltages should be adjusted to

OH* Measured VOH with IOH = –10mA and IOL = 10mA

tion can be accurately approximated by:

compensatefor inductiveground and VCC

noise to maintain required DUT input

levels relative to the DUT ground pin.

NCV F

where

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

specified as a minimum since the exter-

nal system must supply at least that

much time to meet the worst-case re-

quirements ofall parts. Responses from

the internal circuitry are specified from

the point of view of the device. Output

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with all outputs changing ev-

ery cycle and no load, at a 5 MHz clock

rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

OBSOLETE

delay, for example, is specified as a

maximum since worst-case operation of

any device always provides data within

that time.

8. These parameters are guaranteed

but not 100% tested.

Shadow Registers

03/04/99–LDS.818-L

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

ORDERING INFORMATION

24-pin — 0.3" wide

28-pin

VCC

MODE

CLK S

28 27 26

Top

View

12 13 14 15 16 17 18

SDO

SDI

CLK P

GND

Plastic DIP

(P2)

Sidebraze

Hermetic DIP (D2)

Ceramic Leadless Chip Carrier

(K1)

Speed

0°C to +70°C — COMMERCIAL SCREENING

25 ns

L29C818PC25

–55°C to +125°C — COMMERCIAL SCREENING

30 ns

–55°C to +125°C — MIL-STD-883 COMPLIANT

L29C818DMB30

L29C818KMB30

OBSOLETE

Shadow Registers

03/04/99–LDS.818-L

L29C818KMB30 [LOGIC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E