L6116CMB20L [LOGIC]

Standard SRAM, 2KX8, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24;


型号：	L6116CMB20L
厂家：	LOGIC DEVICES INCORPORATED
描述：	Standard SRAM, 2KX8, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24 CD 静态存储器内存集成电路
文件：	总8页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

L6116

2K x 8 Static RAM (Low Power)

DEVICES INCORPORATED

FEATURES

DESCRIPTION

q 2K x 8 Static RAM with Chip Select The L6116 is a high-performance, low- (typical) respectively, at 3 V, allowing

Powerdown, Output Enable

q Auto-Powerdown™Design

q Advanced CMOS Technology

q High Speed — to 15 ns maximum

q Low Power Operation

Active:

power CMOS Static RAM. The

storage circuitry is organized as 2048

words by 8 bits per word. The 8 Data

In and Data Out signals share I/O

pins. These devices are available in

three speeds with maximum access

times from 15 ns to 25 ns.

effective battery backup operation.

The L6116 provides asynchronous

(unclocked) operation with matching

access and cycle times. An active-low

Chip Enable and a three-state I/O bus

with a separate Output Enable control

simplify the connection of several

chips for increased storage capacity.

425 mW typical at 25 ns

Standby (typical):

400 µW (L6116)

Inputs and outputs are TTL compat-

ible. Operation is from a single +5 V

power supply. Power consumption

for the L6116 is 425 mW (typical) at

25 ns. Dissipation drops to 60 mW

(typical) for the L6116 and 50 mW

(typical) for the L6116-L when the

memory is deselected.

Memory locations are specified on

address pins A0 through A10. Reading

from a designated location is

200 µW (L6116-L)

q Data Retention at 2 V for Battery

Backup Operation

q DESC SMD No.

accomplished by presenting an

address and driving CE and OE LOW,

while WE remains HIGH. The data in

the addressed memory location will

then appear on the Data Out pins

within one access time. The output

pins stay in a high-impedance state

when CE or OE is HIGH, or WE is

LOW.

5962-84036 — L6116

5962-89690 — L6116

5962-88740 — L6116-L

Two standby modes are available.

Proprietary Auto-Powerdown™

circuitry reduces power consumption

automatically during read or write

accesses which are longer than the

minimum access time or when the

memory is deselected. In addition,

data may be retained in inactive

storage with a supply voltage as low

as 2 V. The L6116 and L6116-L

consume only 30 µW and 15 µW

q Available 100% Screened to

MIL-STD-883, Class B

q Plug Compatible with IDT6116,

Cypress CY7C128/CY6116

q Package Styles Available:

• 24-pin Plastic DIP

Writing to an addressed location is

accomplished when the active-low CE

and WE inputs are both LOW. Either

signal may be used to terminate the

write operation. Data In and Data Out

signals have the same polarity.

• 24-pin CerDIP

• 24-pin Plastic SOJ

• 24-pin Ceramic Flatpack

• 28-pin Ceramic LCC

• 32-pin Ceramic LCC

Latchup and static discharge pro-

tection are provided on-chip. The

L6116 can withstand an injection

current of up to 200 mA on any pin

without damage.

L6116 BLOCK DIAGRAM

128 x 16 x 8

MEMORY

ARRAY

ROW

ADDRESS

COLUMN SELECT

& COLUMN SENSE

I/O7-0

CONTROL

COLUMN ADDRESS

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2)

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 200 mA

OPERATING CONDITIONS To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

0°C to +70°C

Supply Voltage

4.5 V ≤ VCC ≤ 5.5 V

2.0 V ≤ VCC ≤ 5.5 V

Active Operation, Commercial

Active Operation, Industrial

Active Operation, Military

Data Retention, Commercial

Data Retention, Industrial

Data Retention, Military

–40°C to +85°C

–55°C to +125°C

0°C to +70°C

–40°C to +85°C

–55°C to +125°C

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5)

L6116

L6116-L

Typ Max Unit

Symbol Parameter

Test Condition

Min

Typ

Max

Min

VOH

VOL

VIH

Output High Voltage

VCC = 4.5 V, IOH = –4.0 mA

IOL = 8.0 mA

2.4

Output Low Voltage

Input High Voltage

0.4

2.2

VCC

2.2

VCC

+0.3

VIL

Input Low Voltage

(Note 3)

–3.0

–10

0.8 –3.0

0.8

IIX

Input Leakage Current

Output Leakage Current

VCC Current, TTL Inactive

VCC Current, CMOS Standby

VCC Current, Data Retention

Input Capacitance

Ground ≤ VIN ≤ VCC

(Note 4)

+10

–10

+10 µA

15 mA

150 µA

50 µA

IOZ

ICC2

ICC3

ICC4

CIN

COUT

(Note 7)

(Note 8)

300

150

VCC = 3.0 V (Note 9)

Ambient Temp = 25°C, VCC = 5.0 V

Test Frequency = 1 MHz (Note 10)

Output Capacitance

L6116-

Symbol Parameter

VCC Current, Active

Test Condition

15 Unit

160 mA

ICC1

(Note 6)

115

135

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

SWITCHING CHARACTERISTICS Over Operating Range

READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)

L6116–

Symbol Parameter

Min Max Min Max Min Max

tAVAV

tAVQV

tAXQX

tCLQV

tCLQZ

tCHQZ

tOLQV

tOLQZ

tOHQZ

tPU

Read Cycle Time

Address Valid to Output Valid (Notes 13, 14)

Address Change to Output Change

Chip Enable Low to Output Valid (Notes 13, 15)

Chip Enable Low to Output Low Z (Notes 20, 21)

Chip Enable High to Output High Z (Notes 20, 21)

Output Enable Low to Output Valid

Output Enable Low to Output Low Z (Notes 20, 21)

Output Enable High to Output High Z (Notes 20, 21)

Input Transition to Power Up (Notes 10, 19)

Power Up to Power Down (Notes 10, 19)

Chip Enable High to Data Retention (Note 10)

tPD

tCHVL

READ CYCLE — ADDRESS CONTROLLED Notes 13, 14

tAVAV

ADDRESS

tAVQV

DATA OUT

PREVIOUS DATA VALID

DATA VALID

tAXQX

tPU

tPD

ICC

READ CYCLE — CE/OE CONTROLLED Notes 13, 15

tAVAV

tCLQV

tCLQZ

tCHQZ

tOLQV

tOLQZ

tOHQZ

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA OUT

DATA VALID

tPU

tPD

ICC

50%

DATA RETENTION Note 9

DATA RETENTION MODE

VCC

4.5 V

≥ 2 V

tCHVL

VIH

tAVAV

VIH

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

SWITCHING CHARACTERISTICS Over Operating Range

WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)

L6116–

Symbol Parameter

Min Max Min Max Min Max

tAVAV

tCLEW

tAVBW

tAVEW

tEWAX

tWLEW

tDVEW

tEWDX

tWHQZ

tWLQZ

Write Cycle Time

Chip Enable Low to End of Write Cycle

Address Valid to Beginning of Write Cycle

Address Valid to End of Write Cycle

End of Write Cycle to Address Change

Write Enable Low to End of Write Cycle

Data Valid to End of Write Cycle

End of Write Cycle to Data Change

Write Enable High to Output Low Z (Notes 20, 21)

Write Enable Low to Output High Z (Notes 20, 21)

WRITE CYCLE — WE CONTROLLED Notes 16, 17, 18, 19

tAVAV

ADDRESS

tCLEW

tAVEW

tEWAX

tWLEW

DATA IN

DATA OUT

ICC

tAVBW

tDVEW

DATA-IN VALID

tEWDX

tWLQZ

tPU

tWHQZ

HIGH IMPEDANCE

tPD

tPU

WRITE CYCLE — CE CONTROLLED Notes 16, 17, 18, 19

tAVAV

ADDRESS

tAVBW

tCLEW

tAVEW

tEWAX

tWLEW

tDVEW

tEWDX

DATA IN

DATA-IN VALID

HIGH IMPEDANCE

DATA OUT

ICC

tPU

tPD

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

NOTES

1. MaximumRatingsindicatestressspecifi- 11. Test conditions assume input transition 20. At any given temperature and voltage

cations only. Functional operation of these times of less than 3 ns, reference levels of condition, output disable time is less than

products at values beyond those indicated

in the Operating Conditions table is not

implied. Exposure to maximum rating con- levels of 0 to 3.0 V (Fig. 2).

ditions for extended periods may affect re-

liability of the tested device.

output enable time for any given device.

1.5 V, output loading for specified IOL and

IOH plus 30 pF (Fig. 1a), and input pulse

21. Transition is measured ±200 mV from

steady state voltage with specified loading

12. Each parameter is shown as a minimum in Fig. 1b. This parameter is sampled and

or maximum value. Input requirements are not 100% tested.

2. The products described by this specifica- specified from the point of view of the exter-

tion include internal circuitry designed to nal system driving the chip. For example,

22. All address timings are referenced from

the last valid address line to the first transi-

tioning address line.

protect the chip from damaging substrate

injection currents and accumulations of external system must supply at least that

tAVEW is specified as a minimum since the

static charge. Nevertheless, conventional much time to meet the worst-case require- 23. CE or WE must be inactive during ad-

precautions should be observed during ments of all parts. Responses from the inter- dress transitions.

storage, handling, and use of these circuits nal circuitry are specified from the point of

24. This product is a very high speed device

in order to avoid exposure to excessive elec- view of the device. Access time, for ex-

and care must be taken during testing in

trical stress values.

ample, is specified as a maximum since

worst-case operation of any device always

provides data within that time.

order to realize valid test information. In-

adequate attention to setups and proce-

dures can cause a good part to be rejected as

faulty. Long high inductance leads that

cause supply bounce must be avoided by

bringing the VCC and ground planes di-

rectly up to the contactor fingers. A 0.01 µF

3. This product provides hard clamping of

transient undershoot. Input levels below

ground will be clamped beginning at –0.6 V. 13. WE is high for the read cycle.

A current in excess of 100 mA is required to

14. The chip is continuously selected (CE

reach –2.0 V. The device can withstand in-

low).

definite operation with inputs as low as –3 V

subject only to power dissipation and bond 15. All address lines are valid prior-to or high frequency capacitor is also required

wire fusing constraints.

coincident-with the CE transition to active.

between VCC and ground. To avoid signal

reflections, proper terminations must be

used.

16. The internal write cycle of the memory

is defined by the overlap of CE active and

WE low. All three signals must be active to

initiate a write. Any signal can terminate a

write by going inactive. The address, data,

and control input setup and hold times

should be referenced to the signal that be-

comes active last or becomes inactive first.

4. Tested with GND ≤ V OUT ≤ VCC. The

device is disabled, i.e., CE = VCC.

5. A series of normalized curves is available

to supply the designer with typical DC and

ACparametricinformationforLogicDevices

Static RAMs. These curves may be used to

determine device characteristics at various

temperatures and voltage levels.

FIGURE 1a.

1 480Ω

+5 V

OUTPUT

17. If WE goes low before or concurrent

with the latter ofCEgoing active, the output

remains in a high impedance state.

6. Tested with all address and data inputs

changing at the maximum cycle rate. The

device is continuously enabled for writing,

i.e., CE ≤ VIL, WE ≤ VIL. Input pulse levels

are 0 to 3.0 V.

255

30 pF

INCLUDING

JIG AND

SCOPE

Ω

18. IfCE goes inactive before or concurrent

with WE going high, the output remains in

a high impedance state.

7. Tested with outputs open and all address

and data inputs changing at the maximum

19. Powerup from ICC2 to ICC1 occurs as a

read cycle rate. The device is continuously result of any of the following conditions:

FIGURE 1b.

disabled, i.e., CE ≥ VIH.

a. Falling edge of CE.

8. Tested with outputs open and all address

and data inputs stable. The device is con-

R1 480Ω

b. Falling edge of WE (CE active).

+5 V

c. Transition on any address line (CE

active).

tinuously disabled, i.e., CE = VCC. Input

levels are within 0.2 V of VCC or GND.

OUTPUT

9. Data retention operation requires that d. Transition on any data line (CE, and WE

255

INCLUDING

JIG AND

SCOPE

5 pF

active).

VCC never drop below 2.0 V. CE must be

≥ VCC – 0.2 V. All other inputs must meet

VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V to ensure

full powerdown. For low power version (if

applicable), thisrequirementappliesonlyto

CE and WE; there are no restrictions on data

and address.

Ω

The device automatically powers down

from ICC1 to ICC2 after tPD has elapsed from

any of the prior conditions. This means that

power dissipation is dependent on only

cycle rate, and is not on Chip Select pulse

width.

FIGURE 2.

10. These parameters are guaranteed but

not 100% tested.

+3.0 V

90%

10%

<3 ns

90%

10%

GND

<3 ns

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

ORDERING INFORMATION

24-pin — 0.3" wide

24-pin — 0.6" wide

A10

I/O

GND

Plastic DIP

(P2)

Ceramic DIP

(C1)

Plastic DIP

(P1)

Ceramic DIP

(C4)

Speed

0°C to +70°C — COMMERCIAL SCREENING

20 ns

15 ns

L6116PC20*

L6116PC15*

L6116CC20*

L6116CC15*

L6116NC20*

L6116NC15*

L6116IC20*

L6116IC15*

–40°C to +85°C — COMMERCIAL SCREENING

20 ns

15 ns

L6116PI20*

L6116PI15*

L6116NI20*

L6116NI15*

–55°C to +125°C — COMMERCIAL SCREENING

25 ns

20 ns

15 ns

L6116CM25*

L6116IM25*

L6116IM20*

L6116IM15*

L6116CM20*

L6116CM15*

–55°C to +125°C — MIL-STD-883 COMPLIANT

L6116CMB25*

25 ns

20 ns

15 ns

L6116IMB25*

L6116IMB20*

L6116IMB15*

L6116CMB20*

L6116CMB15*

*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L6116CMB15L)

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

ORDERING INFORMATION

24-pin — 0.3" wide

24-pin

VCC

A10

I/O7

I/O6

I/O5

I/O4

I/O3

I/O

I/O0

I/O1

I/O2

GND

I/O

10 15

11 14

12 13

GND

Plastic SOJ

(W1)

Ceramic Flatpack

(M1)

Speed

0°C to +70°C — COMMERCIAL SCREENING

L6116WC20*

20 ns

15 ns

L6116MC20*

L6116MC15*

L6116WC15*

–40°C to +85°C — COMMERCIAL SCREENING

20 ns

15 ns

L6116WI20*

L6116WI15*

–55°C to +125°C — COMMERCIAL SCREENING

25 ns

20 ns

15 ns

L6116MM25*

L6116MM20*

L6116MM15*

–55°C to +125°C — MIL-STD-883 COMPLIANT

25 ns

20 ns

15 ns

L6116MMB25*

L6116MMB20*

L6116MMB15*

*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L6116MMB15L)

16K Static RAMs

03/21/95–LDS.6116-F

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

ORDERING INFORMATION

28-pin

32-pin

32 31 30

28 27 26

A10

Top

View

Top

View

A10

I/O

12 13 14 15 16 17 18

14 15 16 17 18 19 20

Ceramic Leadless Chip Carrier

(K1)

Ceramic Leadless Chip Carrier

(K7)

Speed

0°C to +70°C — COMMERCIAL SCREENING

20 ns

15 ns

L6116KC20*

L6116KC15*

L6116TC20*

L6116TC15*

–40°C to +85°C — COMMERCIAL SCREENING

20 ns

15 ns

–55°C to +125°C — COMMERCIAL SCREENING

25 ns

20 ns

15 ns

L6116KM25*

L6116KM20*

L6116KM15*

L6116TM25*

L6116TM20*

L6116TM15*

–55°C to +125°C — MIL-STD-883 COMPLIANT

L6116KMB25*

25 ns

20 ns

15 ns

L6116TMB25*

L6116TMB20*

L6116TMB15*

L6116KMB20*

L6116KMB15*

*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L6116KMB15L)

16K Static RAMs

03/21/95–LDS.6116-F

L6116CMB20L [LOGIC]

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