L7710QI10 [LOGIC]
FFT Processor, 16-Bit, CMOS, PQFP160, PLASTIC, QFP-160;
| 型号： | L7710QI10 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | FFT Processor, 16-Bit, CMOS, PQFP160, PLASTIC, QFP-160 时钟 外围集成电路 |
| 文件： | 总14页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L7710
High-Speed FFT Processor
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L7710, a high-speed Fast Fourier
coefficients are presented to the
❑ 100 MHz Operation
Transform Processor,allows extremely processor core every 10ns and output
❑ Computes up to a 1024 Point
fast FFT computations to take place
within a single monolithic device. All
data buffering and working storage
required for up to a 1024 point com-
plex FFT operation are on-chip. This
eliminates the need for expensive,
high-speed externalmemories while
decreasing internal computation time.
is clocked out at the same rate giving
the processing performances indicated.
Complex FFT in 18 µs* using a
single Processor
❑ 4Programmable ComplexFFTPoint
Sizes: 16 Point (240 ns), 64 Point
(1.2 µs), 256 Point (3.4 µs), and 1024
Point (18 µs)**
Severalprogrammable options are
available on the device to perform FIR
filtering, forward/ inversetransform,
complex input data windowing,
transform overlap, and exponential
averaging of the output. The 20-bit
block floating point precision is
achieved with scaling logic. Exact
user specified scaling is also an option
through the use of a scaling register.
The data interface to the device
❑ Supports Both Forward and Inverse
Fast Fourier Transforms
The core transform processor is
❑ Configurable as a FIR Filter with up
comprised of a DragonFlyTM processor
which computes 4-point complex
transforms in approximately 10ns
when the pipeline is fully loaded. It
consists of several multipliers and
to 1024 Complex Taps
❑ Contains Seven Built-In Windowing
Functions in ROM
❑ Window Buffer (2Kx16-bit)enables
appears to the user as if it were a
UserstoProgram theirown Complex
adders in parallel to achieve this high, synchronous SRAM with all appropri-
Window Functions through Inde-
pendent Address and Data Input
Lines
sustained computation throughput
rate. Input data and twiddle factor
ate signals.
❑ Standby Modes result in Significant
Power Savings while simultaneously
Retaining InternalMemory Data
L7710 BLOCK DIAGRAM
❑ 16-bit Fixed Point Data Precision (96
dB Dynamic Range) on Output with
20-bit InternalComputation Preci-
sion
CB
FILT
FF
DRD/DWE
WRD/WWE
16
EF
❑ 224K-bit Internal RAM
❑ 1.5M-bit Internal Function ROM
❑ 3.3 Volt Power Supply
❑ 5 Volt Tolerant I/ O
❑ Package Styles Available:
• 160-pin Plastic Quad Flatpack
• 160-pin Flatpack
DIN15-0
16
WIN15-0
11
16
11
DOUT15-0
ADOUT10-0
AIN10-0
2
CACC1-0
CTM
2
OVC1-0
TEN
High-Speed
FFT
Processor
ORD/OWE
OE
XYMODE
WD2-0
SZ1-0
3
2
INV
EOT
DBO
AVG
OVF
SCTRL
HOLD
6
SCL5-0
*
1024 Complex FFT Computation time based
on XY Mode with 25% Input Overlap. 1024
Complex FFT with No Overlap and Averaged
Linear or Decibel Power is computed in 24 µs.
PRELIMINARY
STDBY
CE
RESET
CPINS
PLL1-0
OCLK
ACOP
** All Computation times based on XY Mode
2
with 25% Input Overlap.
CLK
Logic Products
07/06/99–LDS.7710-A
1
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
Some applications of the L7710 in the
telecommunication field are:Wireless
Base Stations, Satellite Communica-
tions, Software Defined Radios, Cable
Modems and OFDM Applications.
Some sample instrumentation applica-
tions include: Digital Spectrum
FIGURE 1. INPUT AND WINDOW DATA FORMATS
Input Data Window Data
15 14 13
2
1
0
15 14 13
–215 214 213
2
1
0
–215 214 213
(Sign)
22 21 20
22 21 20
(Sign)
Analyzers, Modulation Analyzers, and
Distortion Analyzers.
FIGURE 2. INPUT AND WINDOW ADDRESS FORMATS
SIGNALDEFINITIONS
Power
Input Data Address
10 9
Window Data Address
10 9 0
8
2
1
0
8
2
1
VCC andGND
210 29 28
22 21 20
210 29 28
22 21 20
+3.3 V power supply. All pins must be
connected.
Clock
FIGURE 3. DATA OUTPUT FORMATS
CLK — Master Clock
Real/Imaginary Mode
XY Mode (Averaged)
The rising edge of CLK strobes all
enabled registers and input memory
latches.
15 14 13
2
1
0
15 14 13
2
1
0
–215 214 213
22 21 20
–215 214 213
22 21 20
(Sign)
(Sign)
OCLK — Output Clock
The rising edge of OCLK strobes the
outputbuffermemoryand thefollowing
flags: EF, OVF and EOT.
Linear Power Mode
Averaged Linear Power Mode
14 13 12
214 213 212
2
1
0
14 13 12
214 213 212
2
1
0
22 21 20
22 21 20
Inputs
DIN15-0 — Data Input
DIN15-0 is the 16-bit registered bidirec-
tional data input port. The direction is
dependent on CACC1-0 (Table 5) and
the DRD/ DWE pin. Data is latched on
the rising edge ofCLK, provided DRD/
DWE is held LOW. The data format is
two’scomplement.
Decibel Mode
Averaged Decibel Mode
15 14 13
-215 214 213
2
1
0
15 14 13
2
1
0
22 21 20
-215 214 213
22 21 20
(Sign)
(Sign)
Data is latched on the rising edge of
CLK, provided WRD/ WWEis held
LOW. The data format is two’s
complement.
ADOUT10-0 — Data Output Address
AIN10-0 — Data/Window Input Address
ADOUT10-0 is the registered bidirec-
tional address bus for DOUT15-0. In
Continuous Mode (CTM=1),the
LF7710 outputs data output address
information automatically and sequen-
tially. To read out data from DOUT15-0
in any order, present addresses to
ADOUT10-0 while in Non-Continuous
Mode(CTM=0).
AIN10-0 is the input address bus for
DIN15-0 and WIN15-0 and is controlled
by CACC1-0 (Table 5).
PRELIMINARY
Outputs
WIN15-0 — Window Input
DOUT15-0 — Data Output
WIN15-0 is the 16-bit registered data
input port. This input port is actually
bidirectional. Depending on the value
present on CACC1-0 and WRD/ WWE,
this port may act as an output port.
DOUT15-0 is the 16-bit registered data
output port. See Figure 3.
Logic Products
07/06/99–LDS.7710-A
2
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
TABLE 4. TRANFORM LENGTH CONTROL
TABLE 1. OVERLAP MODE
SZ1-0
Transform Length
DF Passes
PLL CLKS/Pass
OVC1-0
0 0
Configuration
No Overlap
25%
0 0
16
64
2
3
4
5
19
31
0 1
0 1
1 0
256
1024
79
1 0
50%
1 1
271
1 1
75%
TABLE 2. WINDOW MODE
TABLE 5. ADDRESS LINE CONTROL (CTM = 0 & CB =0)
WD2-0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Configuration
Rectangular Window
Bartlett
CACC1-0
Active Loading Location
Active Corresponding Data Bus
0 0
Control Register
WIN15-0
0 1
Window RAM
WIN15-0
Hamming
1 0
Data Input RAM
DIN15-0
Hanning
1 1
Data Input & Window RAM
DIN15-0 & WIN15-0
Trapezoidal
Blackman-Harris
Welch
TABLE 6. ADDRESS LINE CONTROL (CTM = 1 & CB=0)
CACC1-0
Active Loading Location
Control Register
Window RAM
N/A
Active Corresponding Data Bus
Buffer
0 0
WIN15-0
WIN15-0
N/A
0 1
TABLE 3. PLL MODE
1 0
1 1
Window RAM
WIN15-0
PLL1-0
BusOptions
0 0
x1
x2
x3
x4
0 1
TABLE 7. BUFFER RESET (CB=1)
TABLE 8. STANDBY MODES
1 0
CACC1-0
0 0
Location to be Cleared
Control Register
Window RAM
STDBY HOLD
Operation
Normal Operation
Output Buffer Held
Soft Standby
1 1
0
0
1
1
0
1
0
1
0 1
SCL5-0 — Output Scaling Factor
1 0
Input RAM
SCL5-0 is the registered output scaling
factor for the current transform being
read from the output buffer. The scale
factor becomes valid with the first data
read after an EOT.
1 1
Output RAM
Hard Standby
the device performs block floating
point which acts as an automatic
internal scale to prevent overflow. If
SCALE is set to any value other than 0,
the user should monitor OVF.
HIGH at all other times. EF will
automatically become LOW upon
system reset.
EOT — End of Transform
Controls
The EOT signal goes HIGH when the
transform has completed and goes
LOW again when either a new TEN is
pulsed in Non-Continuous Mode or
the window stage of the next transform
FF — Full Flag
CTM —ContinuousTransformMode
FF will go LOW indicating that the
data input buffer is full. FF will be
HIGH at all other times. FF will
automatically become HIGH upon
system reset.
When CTM is LOW, Non-Continuous
Transform operation is possible.
When TEN is pulsed LOW, the trans-
form starts (or restarts if the previous
transform was in mid-computation).
When CTM is HIGH, Continuous
Transform Mode is enabled, which
places the device in synchronous
operation. While in Continuous
PRELIMINARY
is completed in Continuous Mode.
OVF — Overflow Flag
EF — Empty Flag
When OVF goes HIGH, this indicates an
internal data overflow. OVF will not
go HIGH if SCALE has been set to the
default mode, all zeros. In this mode,
EF will go LOW indicating that the
data output buffer is empty. EF will be
Logic Products
07/06/99–LDS.7710-A
3
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
TABLE 9. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR CTM=1
Full Complex Transform
TECHNICALNOTE:
OVC1-0 PLL1-0 Mode x1 (100 MHz)
00
01
10
11
ValidOperation
ValidOperation
ValidOperation
ValidOperation
When operating in Continuous Transform Mode, (CTM=1), Data Startvation
is only possible if the Automatic Continuous Operation pin is disabled,
(ACOP=0). In this case, the core FFT processor, will continuously run,
without regard to the state of the input and output buffers, and it is up to the
user to properly throttle the core using the HOLD pin.
OVC1-0 PLL1-0 Mode x2 (50 MHz)
When ACOP = 1 however, Data Starvation is not possible, because the
core is automatically throttled based on the states of the input and output
buffers. In this case, the core will wait for the input buffer, reading the data
as it becomes available. Then it will run until both output buffers are full.
Once both output buffers are full, the core will automatically halt, until an
output buffer becomes available to write. In this case, the input buffer may
become full, halting the user from writting the input buffer based on their
output read rate. This possibility can be calculated based on the following
formula:
00
01
10
11
DataStarvation
DataStarvation
ValidOperation
ValidOperation
OVC1-0 PLL1-0 Mode x3 (33 MHz)
00
01
10
11
DataStarvation
DataStarvation
DataStarvation
ValidOperation
Input Clock
Boundary Latency
Caculation Calculation
+
(
(
Passes
Length
Input Latency
+
C L K
F F T T I M E
=
P L L C L K
Output Clock
Boundary Latency
Output
Latency
+
OVC1-0 PLL1-0 Mode x4 (25 MHz)
+
O C L K
00
01
10
11
DataStarvation
DataStarvation
DataStarvation
ValidOperation
* See Calulating Transform Time
The above formula should also be used to calculate the ideal PLL factor for
continuousoperation.
HOLD — Hold Output Buffer Data
DBO —Linear Power/dBOutput
Transform Mode, the part acts like a
“Data Pump.” Data MUST be made
available on the input buffers when
expected and likewise, output will be
shifted out in a FIFO-like autonomous
fashion. Note: In either mode, the user
should follow the recommended
combinations ofOverlap Modes
(OVC1-0) and PLL Modes (PLL1-0) in
order to avoid unexpected data on the
output. See Table 9.
Holds output buffer contents steady
while HOLD is held HIGH. When
HOLD is held LOW, the output buffer
allows data to be changed. When the
device is in Standby Mode, the data in
all the buffers is static, regardless of the
status of HOLD. If HOLD and STDBY
are HIGH, the device is in a “hard
standby mode”. Refer toTable 8 for
standby modes.
When DBO is HIGH, dB Output format
is selected. When DBO is LOW, Linear
Power format is selected. See Table 10.
XYMODE—XYMode
When XYMODE is HIGH, the device is
in XY Mode. The output mode can be
either Real/ Imaginary or XY Mode
(Averaged)depending on the value of
AVG. If XYMODE is LOW the device
is in Power Mode. The output can be
in one of the following modes: Linear
Power,Decibel,Averaged Linear
TEN — Transform Enable Control
SCTRL — Scale Control
When the device is in Continous
When SCTRL is LOW, scaling is
PRELIMINARY
Transform Mode(CTM=1),TEN should
be held LOW. When the device is in
Non-ContinuousMode(CTM=0),TEN
can be pulsed LOW to start a transform.
Should TEN be pulsed LOW in the
middle ofa transform computation, the
transform willrestart.
automatically handled internally
through block floating point. When
SCTRL is HIGH, scaling is achieved
through the scaling registers and is
under user control.
Power,and Averaged DecibelPower.
See Table 10.
AVG — Average Real and Imaginary
When AVG is enabled, Exponential
Window Averaging on Power is
performed. See Table 10.
Logic Products
07/06/99–LDS.7710-A
4
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
INV—Forward/InverseTransformControl
It also determines the buffer location to
be cleared depending on the value of
CB. For instance, in order for the user
to read the Control Register 1, CACC1-0
should be set to 00. The value 001h
would then be loaded through AIN10-
0. Data from Control Register 1 would
then be made available at WIN15-0.
Refer to Tables 5-7 for CACC1-0
mapping. See Figure 4 for the Control
Register Map. See Figures 5 and 6 for
Control Register 0 and 1 Internal
Mapping.
FIGURE 4. CONTROL REGISTER
When INV is LOW, Forward Transform
isselected. When INVisHIGH, Inverse
Transform is selected. This signal
controlled internally when the device
is in Filter Mode.
MAP (CACC1-0=00)
XX
XX 7FFh
SZ1-0 — Complex Transform Length
XX
XX 004h
003h
ALPHA
SCALE
SZ1-0 is the 2-bit Transform Length
selector and is selected from the four
predefined configurations. See Table 4.
002h
CR1
001h
CR0
000h
OVC1-0 — Overlap Control
15
0
CPINS — Control Pins
OVC1-0 is the 2-bit Overlap Control
which determines the type of overlap
used and is selected from the four
predefined configurations. See Table 1.
CPINS changes control from the
external control pins to the control
registers. If CPINS is HIGH, control of
the device is determined by the external
control pins. If CPINS is LOW, control
of the device is determined by the
internal control registers.
FILT—FFT/FIROperation Mode
When FILT is held LOW, the device is
in FFT Mode. When FILT is held
HIGH, the device is in FIR Mode.
PLL1-0 — PLL Mode
PLL1-0 is the 2-bit PLL mode selector
and is selected from the four pre-
defined configurations. When using
the PLL, PLL clock rates over ƒPLL are
not guaranteed. See Table 3.
WD2-0 — Window Configuration
WD2-0 is the 3-bit Window Configuration
mode select which determines the type
of Window used and is selected from
theseven predefined configurations
stored in the Window Configuration
ROM or the user-definable Window
RAM. See Table 2.
OE—Output Enable
Data is available on the output port
(DOUT15-0) on the falling edge of CLK
while OE is held LOW. When OE is
HIGH, DOUT15-0 is placed in a high-
impedance state. CLKOUT is not
affected by OE.
CACC1-0 — Control Access
CACC1-0 determines the active buffer
loading location (i.e. Control Register,
Window RAM and/ or Data Input
RAM) depending on the value of CTM.
FIGURE 5. CONTROL REGISTER 0 MAP
0
0
EOT
13
OVF
12
INV
11
WD
2
WD
1
WD
0
FILT
7
AVG XYMODE DBO SCTRL HOLD TEN
CTM
0
15
14
10
9
8
6
5
4
3
2
1
RESERVED BITS: 15, 14
EOT AND OVF ARE READ-ONLY BITS, THE REST ARE READ-WRITEABLE
FIGURE 6. CONTROL REGISTER 1 MAP
PRELIMINARY
0
0
0
0
0
0
PLL
9
1
PLL
0
0
7
0
6
OVC
1
OVC
4
0
0
3
0
2
SZ
1
SZ
0
0
15
14
13
12
11
10
8
5
1
RESERVED BITS: 15 - 10, 7, 6, 3, 2
ALL BITS ARE READ/WRITABLE
Logic Products
07/06/99–LDS.7710-A
5
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
FIGURE 7. INPUT BUFFER
MEMORY MAP
FIGURE 8. WINDOW BUFFER
MEMORY MAP
FIGURE 9.
OUTPUT BUFFER
MEMORY MAP
XY MODE
I
1023
1023
1022
1022
7FFh
I
1023
1023
1022
1022
7FFh
(XYMODE=1)
R
I
R
I
I
R
I
R
1023
1023
1022
1022
7FFh
R
R
I
1
I
1
R1
R1
I
R
0
I
R
0
I
R
I
1
0
000h
0
000h
1
15
0
15
0
0
R0
000h
DRD/DWE—DataRead/WriteEnable
STDBY — Standby Mode
15
0
If DRD/ DWE is held LOW while CE is By asserting STDBY to HIGH, the
held LOW, data on DIN15-0 is written to device is placed in a standby state.
FIGURE 10. OUTPUT BUFFER
MEMORY MAP
the corresponding location associated
with CACC1-0 on the rising edge of
Power consumption drops, because the
FFT engine has been powered down.
POWER MODE
(XYMODE=0)
CLK. If DRD/ DWE is HIGH while CE The data in all the buffers is static,
is LOW, DIN15-0 is placed in an output regardless of the status of HOLD. If
mode in order to read data. If CE is
HIGH, DIN15-0 is tri-stated.
both STDBY and HOLD are held
HIGH, additional power savings is
achieved by powering down the PLL
(hard standby mode). To return from
the hard standby state, the user must
drop HOLD to a logic LOW and wait
at least a tPLL time in order to allow
the PLLto restart before dropping
STDBY. Refer to Table 8 for standby
modes.
P
P
P
P
1023
1022
1021
1020
3FFh
WRD/WWE—WindowRead/WriteEnable
If WRD/ WWE is held LOW while CE
is held LOW, data on WIN15-0 is
written to the corresponding location
associated with CACC1-0 on the rising
edge of CLK. If WRD/ WWE is HIGH
while CE is LOW, DIN15-0 is placed in
an output mode in order to read data.
If CE is HIGH, DIN15-0 is tri-stated.
P3
P2
P1
P0
000h
ACOP — AutomaticContinuous
Operation
15
0
CE — Chip Enable
not necessary when ACOP and CTM
are active, except for standby modes.
ACOP is not valid when CTM is low.
The ACOP signal automatically
controls the FFT engine based on the
user read-rate ofthe output buffer
when in Continous Transfer Mode.
ACOP allows the device to guarantee
succesive completed transforms
without loss of output data and user
intervention, i.e. HOLD and/ or STDBY
going HIGH. When both ACOP and
CTM are HIGH, the output buffer will
not be written over until the empty flag,
EF, is asserted. However, the input
buffer may go full, i.e. the FF flag is
asserted, waiting for the user to read
the output buffer. The HOLD signal is
If CE is LOW, DIN15-0 and WIN15-0
are active as either input or output
ports determined by DRD/ DWEand
WRD/ WWE. If CE is HIGH, both
ports are tri-stated. Only WIN15-0 is
affected when CTM=1.
RESET—SystemReset
The RESET signal resets all pointers to
the buffers with the exception of the
control registers. All values inside
CB — Clear Buffer
PRELIMINCon
A
trol Regist
are reset to zero.
R
ers 0, 1, Alpha and Scale
Y
Clears the Input Buffer,Output Buffer,
Control Register or Window Buffer to
all zeros when pulsed HIGH for one
clock cycle depending on the value
present at CACC1-0. Refer to Table 7
for buffer selection.
Logic Products
07/06/99–LDS.7710-A
6
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
USER ACCESSIBLERESOURCES
Continuous Transform Mode
address present on ADOUT10-0 for the of the transform, EOT will go HIGH
given address setup time and OE
indicating results are available on the
asserted LOW. Illegal combinations of output data bus.
PLL Modes and OVC Modes with
Addresses of desired output locations
In Continuous Transform Mode
(CTM=1), the device DIN15-0 is clocked
synchronously with CLK. The L7710
expects new data on every CLK when
DRD/ DWE is LOW until the input
buffer is full, signified by the FF Flag.
Transforms are continuosly ran as
long as data is available and TEN is
LOW.
CTM=1 are shown in Table 9.
are driven via an external device (e.g.
DSP or DMA controller). Between EOT
and the next TEN assertion, new input
data, as well as any new window data,
Addresses of input data are automati-
cally generated in consideration of the
overlap mode. EOT will be generated
after the first output is received into the can be entered into the device with
internal output buffer. This is designed timing based on tCYC. The Input and
to prevent user access prior to any post Window buffers may be written before
transform computations, such as log or the completion of the prevous trans-
averaging operations.
form, but only upon completion of the
windowing pass by the processor core.
Since there are no flags to indicate
completion of the windowing pass, the
user must be mindful of the number of
clock cycles.
For example, if the PLL mode is x2
(PLL1-0=01), and overlap is in 50%
overlap (OVC1-0=10) and the clock
input is 50 MHz, then synchronous
data should be clocked into the device
Non-Continuous Transform Mode
In non-continuous mode (CTM=0),the
user has direct control over addressing
at a 50 MHz input rate according to the the input and output data. The user is
The user must be aware that if the
overlap control is in any mode other
than (OVC10=00) then aged data
(located at lower addresses) is over-
written by more recent data prior to
EOT assertion. For example, in 25%
overlap mode (OVC10=01) and a 1024
point complex transform (SZ10=11);
real and imaginary points 768 and
higher (600h-7FFh) are copied to the
first 256 real and imaginary locations
of the buffer (000h-1FFh). (See Figure 7
for the Input Buffer Memory Map). In
this example, the user should start
addressing the most recent data
beginning at 200h (point 256 and
higher).
input memory map and the size of the
transform specified.
free to place data anywhere in the 2K
input memory map by writing to its
corresponding memory location
directly according the input buffer
memory map (See Figure 7).
There will be 2N (N is specified by
SZ1-0 in Table 4) locations which are
automatically sequenced for both input
and output, beginning with zero, and
appear at their respective address
lines. This allows the device to be
directly interfaced to a parallel type
A/ D converter at the input or to a
parallel DAC, Digital Signal Processor
or DMA controller at the output.
Data on the DIN15-0 and WIN15-0 pins
is latched into the buffer memories via
the use of DRD/ DWE and WRD/
WWE along with CE. With CE held
LOW,DRD/ DWEor WRD/ WWE(or
both) are used to latch the data into the
corresponding internal buffers at the
address specified by the individual
address lines, AIN10-0.
Output data is memory mapped
according to the output mode selected
(see Figure 10). Output is streamed
through the use of an onboard FIFO to
the DOUT15-0 pins, following an
Once data has been clocked into the
device, a logic LOW on TEN will start
transform operations. On completion
TABLE 10. OUTPUT MODES FOR COMBINATIONS OF AVG, XYMODE AND DBO
AVG
XYMODE
DBO
DFPasses
OutputModes
0
0
0
0
1
1
1
1
0
0
0
1
1
1
Linear Power Mode (Refer to Figure 10)
Decibel Mode (Refer to Figure 10)
PRELIMINARY
1
1
0
0
1
1
0
1
0
1
0
1
0
X
2
2
1
X
Real/Imaginary Mode (Refer to Figure 9)
InvalidMode
AveragedLinearPowerMode(RefertoFigure10)
Averaged Decibel Power Mode (Refer to Figure 10)
XY Mode (Averaged) (Refer to Figure 9)
InvalidMode
Logic Products
07/06/99–LDS.7710-A
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L7710
DEVICES INCORPORATED
High-Speed FFT Processor
FIGURE 12. EIGHT STAGES OF THE 1024 POINT FFT DATA FLOW
STAGE 1. (271 CYCLES)
STAGE 2. (271 CYCLES)
STAGE 3. (271 CYCLES)
Twiddle
ROM
Twiddle
ROM
Window
Memory/
ROM
Input
Memory
A
Window
B
A
DF
B
A
DF
B
STAGE 4. (271 CYCLES)
STAGE 5. (271 CYCLES)
STAGE 6. (271 CYCLES)
Twiddle
ROM
Twiddle
ROM
Twiddle
ROM
A
DF
B
A
DF
B
A
DF
B
Control Register 1 also consists of 16
bits, however 10 bits are reserved. All
6 of the non-reserved bits are read/
writeable. See the Signal Definitions
STAGE 7. (271 CYCLES)
STAGE 8. (271 CYCLES)
Exponential
A
B
for descriptions for each bit.
Average
The SCALE control register at location
002h is for input “power-of-two”
scaling. The device scales each stage
of the processing by a fixed value of 20
to 24, in the event the user does not
wish to use the block-floating point
scaling provided by the hardware.
Output
Memory
A
SQUARE
B
Output
Mode
Bit
Reversal
Warning: Internal computations may
overflow if the user is not careful about
input scaling. When SCALE is set to
other than 0 (which is the default reset
state), the device will not automatically
scale internally to prevent an overflow
condition. Should an overflow condi-
tion occur, the overflow flag (OVF)will
go HIGH.
000h and 001h (See Figure 4). Figures
5 and 6 show the mapping format of
Control Registers 0 and 1. Control
Register 0 consists of 16 bits which are
readable and writable with the excep-
tion of EOT which is read-only.
Control Register Mapping
PRELIMINARY
By setting CACC1-0 to 00 and CB to 0,
the window buffer is disabled and
causes the first four locations to be
treated as “configuration” registers.
Control Registers 0 and 1 are found in
the corresponding first two locations
Logic Products
07/06/99–LDS.7710-A
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L7710
DEVICES INCORPORATED
High-Speed FFT Processor
The ALPHA control register at location window pass of the L7710. The L7710 Output Modes
then processes the data through the
DragonFly processor core. The
Twiddle Factor numbers for the
DragonFly processor are built into the
L7710 ROM.
003h is the value associated with
exponential averaging of the output.
The equation is:
For the Linear Power and Decibel
Modes, the L7710 requires one extra
stage (Figure 12) to complete all the
computations in the sum of the squares
calculations. The square root and the
decibel calculations are done during
α OUTPUT +(1−α) LAST_ OUTPUT
This register is a positive value in the
range of 0000h-7FFFh (representing a
positive fractionalmagnitude between
0.0 and 1.0). When the ALPHA
register is non-zero, it is used to
compute the “moving average”
The number ofstages required by the
L7710 is dependent upon the FFT size. the output buffering.
Table 4 shows the number of
DragonFly passes required for each of
the transform lengths. Each pass
requires (N/ 4 + 15) clock cycles to
complete the DragonFly.
The L7710 will also require an extra
stage if averaging (AVG=1) is selected.
Refer to Control Register Mapping for
the equation of ALPHA, the exponen-
tial value associated with averaging.
represented by the equation above.
To maintain optimum data flow, the
L7710 has two working storage buffers
as shown in Figure 12. These storage
buffers allow the input and output
buffers to be continously accessed by
the user while the calculations are in
progress. Transform results are output
according to the output format chosen
by the user (Table 10) and in like
manner to the input, occupy the first
2N output buffer locations. Depending
on the ouput format chosen, the L7710
may require additional computational
passes for Power (Linear and dB) and
Averaging calculations. Figure 12
shows Stages 7 and 8 as these compu-
tational passes.
The L7710 does the bit reversal map-
ping as the user reads the output
buffer. Figures 9 and 10 show the
output memory maps for Power and
XYmodes.
Operational Modes - FFT
This device has three operation modes,
functioning as an FFT, IFFT or as an
FIRfilter. In FFTmode (FILT=0,
INV=0), an FFT is executed according
to the size specified by SZ1-0 bits as is
shown in Table 4.
IFFT MODE
In IFFTMode (Filt=0, INV=1), an IFFT
is executed according to the following
formula:
Data is loaded into the unit (according
to the status of CTM) and only to 2N
memory locations, N being the trans-
form size. Data up to the first 2N input
memory locations willbe pre-multi-
plied (complex) by the user window
specifed. Upon application of the
TEN, the input data is fed through the
IFFT= conj(fft(conj(data)))
The L7710 completes all conjucating
internally. The frequency domain data
is available in the output buffer at the
assertion of EOT. The IFFT requires the
same number of calculation passes as
FIGURE 13. FIR MODE
Time Domain
FIR Coefficents
Frequency Domain
FIR Coefficents
L7710
Window Buffer
FFT
I
F
F
T
F
PRELIMINARY
DIN
F
T
DOUT
PLLx2
Logic Products
07/06/99–LDS.7710-A
9
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
an FFT. The conjucations do not
require any extra calculation passes or
clock cycles.
To acheive continuous operation in
Filter Mode, the L7710 PLL should be
set to at least a 2x factor of CLK and
CLK and OCLK should be tied to-
gether.
2 or 3 PLLCLK cycles because of the
ambiguity of the asyncronous clock
boundary.
All data formats and controls are
equivalent to the FFTmode.
The number of calculation passes is
dependent on the transform length.
This one more than the number of
DrangonFly passes because of the
window pass plus the additional
output mode passes required. See
Tables 4 and 10.
Data Handling Formats
FIR MODE
There are a variety ofoutput modes
which affect the presentation of output
data and in some cases, its format. For
example,in Real/ Imaginary mode
(XYMODE=1), at the completion ofa
transform, data appears at the output
buffer asinterleaved realand imaginary
(See Figure 10) and in 16-bit two’s
complement format (SeeFigure3). In
In FIR mode (FILT=1), a FIR filter is
implemented. The filter takes a little
more than twice as long to operate
since it must, of necessity, perform two
transforms, an FFT and an inverse FFT.
After the first FFTtransform is com-
pleted, the results are multiplied by the
data found in the window buffer. The
window buffer acts as coefficient
The calculation length is the transform
size/ 4 + 15. See Table 4.
The PLLCLK is equal to CLK times the
PLLCLK multiply factor. See Table 3.
storage for the filter. Finally, a second Linear Power mode, data is presented to
The Output Clock Boundary Latency is
the syncronization of the PLLCLK with
the OCLK. This latency is dependent on
a syncronization circuit and may
require 2 or 3 OCLK cycles because of
the ambiguity of the asyncronous clock
boundary.
inverse transform is executed and
the operation is complete. The results
on the output buffer are the filtered
data. The data is output in a similar
fashion to that of the FFT output,
however, the EOT will not be asserted
until the second transform is com-
pleted. The INV pin and register is
toggled internally by the device and
must be set to zero in this mode. Since
the window buffer is used for coeffi-
cient storage, the user is limited to
using one of the built-in window
functions for the first FFT pass.
the first half (N) output buffer locations
and is in 15-bit magnitude format. In
DecibelOutput mode (DBO=1),data is
presented to the output buffer in
negative magnitude format (16bits wide
but bit 15 is always 1) indicating a
maximum of 0 dB at 0 and descending
negativelyfrom there.
Output Latency is the pipelined data
path registers after the ouptut RAM.
This data path requires 5 CLK cycles.
In the continuous mode (CTM=1),the
address lines are driven from the device
and are sequenced from 0to 2N memory
locations for XYMODE=1or N memory
locationsfor power mode(XYMODE=0).
Example 1.
1K FFT in XYMODE in Non-Continu-
ous Transfer Mode at 100MHz.
CLK=PLLCLK=OCLK
Calculating Transform Time
Calculating And Loading Coefficients
FFTTIME = 2/ CLK + (2+(6*271))/
PLLCLK) + (2+5)/ OCLK = 16.37 µs
The formula for calculating the tranform
time as shown in Table 9:
The coefficients used by the L7710 in
the FIR Filter Mode are calculated by
taking the FFT of the normal impulse
response coefficients. This is required,
because the L7710 will filter in the
frequency domain. Since the L7710
handles all the bit reversal require-
ments, the control FILT=1 must be set
before the coefficients are loaded, and
the coefficients must be loaded in
normal sequence. See Figure 13.
Input Latency is the pipelined data path
registers before the input ram. This data
path requires 2 CLK cycles.
Example 2.
1KFFTin Averaged dBPower Mode in
Continuous Transfer Mode at 50MHz
CLK=OCLK & PLLCLK = CLKx2
The Input Clock Boundary Latency is
the syncronization of the CLK with the
PLLCLK. This latency is dependent on a
syncronization circuit and may require
FFTTIME = 2/ CLK + (2+(8*271))/
PLLCLK) + (2+5)/ OCLK = 21.88 µs
TABLE 11. PIN CONFIGURATIONS
Data Handling and Formats
PRELIMINARY
Pin
Filt
FFTMode
IFFTMode
FIR Mode
The data is input according the SZ1-0
and the status of CTM up to 2N
locations, N being the filter size.
0
0
0
1
1
0
INV
WD
PLL
≠
7
User
Table 9
User
Table 9
≥2x
Logic Products
07/06/99–LDS.7710-A
10
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storagetemperature ............................................................................................................. –65°C to +150°C
Operatingambienttemperature ............................................................................................. –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground........................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output .................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchupcurrent ................................................................................................................................ > 400 mA
ESD(MIL-STD-883EMethod3015.7) ................................................................................................ > 2000 V
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
TemperatureRange(Ambient)
0°C to +70°C
Supply Voltage
3.00 V ≤ VCC ≤ 3.60 V
3.00 V ≤ VCC ≤ 3.60 V
ActiveOperation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS OverOperatingConditions(Note4)
Symbol Parameter
TestCondition
Min
Typ
Max Unit
VOH
VOL
VIH
OutputHighVoltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
2.4
V
OutputLowVoltage
Input High Voltage
Input Low Voltage
0.4
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
InputCurrent
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±10
±10
µA
µA
IOZ
OutputLeakageCurrent
VCC Current, Dynamic
VCC Current, Quiescent
VCC Current, Quiescent
InputCapacitance
ICC1
ICC2
ICC3
CIN
800 mA
10 mA
Soft Standby, PLL Running (Note 7)
Hard Standby, PLL Disabled (Note 7)
TA = 25°C, f = 1 MHz
2
mA
pF
10
PRELIMINARY
COUT
OutputCapacitance
TA = 25°C, f = 1 MHz
10
pF
Logic Products
07/06/99–LDS.7710-A
11
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
L7710
10
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Cycle Time
10
Clock Pulse Width
4
3
0
Input Setup Time
tH
Input Hold Time
tD
OutputDelay
7
10
10
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
L7710
12
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Cycle Time
12
Clock Pulse Width
5
4
0
Input Setup Time
tH
Input Hold Time
tD
OutputDelay
8
12
12
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
PRELIMINARY
Logic Products
07/06/99–LDS.7710-A
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L7710
DEVICES INCORPORATED
High-Speed FFT Processor
NOTES
1. Maximum Ratings indicate stress input transition times less than 3 ns, case operation ofany device always pro-
specifications only. Functional oper- output reference levels of 1.5 V (except vides data within that time.
ation ofthese products at values beyond tENA/ tDIS test), and input levels of
11. Transition is measured ±200 mV
from steady-state voltage with specified
loading.
those indicated in the Operating Condi- nominally 0 to 3.0 V. Output loading
tions table is not implied. Exposure to m ay be a resistive d ivid er w hich
maximum rating conditions for ex- provides for specified IOH and IOL at an
tended periods may affect reliability.
output voltage ofVOH min and VOLmax
respectively. Alternatively, a diode
bridge with upper and lower current
sources ofIOH and IOL respectively,and
a balancing voltage of1.5Vmay be used.
Parasiticcapacitance is 30pFminimum,
and may bedistributed. For tENABLEand
tDISABLE m easu rem ents, the load
current is increased to 10 mA to reduce
the RC d elay com p onent of the
measurement.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
2. The products described by this speci-
fication include internal circuitry de-
signedtoprotect the chipfrom damaging
substrate injection currents and accu-
mulationsofstaticcharge. Nevertheless,
conventional precautions should be ob-
served during storage, handling, and
use of these circuits in order to avoid
exposure to excessive electrical stress
values.
FIGURE A. INPUT CIRCUIT
VCC
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measuresarerecommended:
3. Thisdeviceprovideshard clampingof
transient undershoot and overshoot. In-
putlevelsbelow ground oraboveVCCwill
be clamped beginning at –0.6 V and VCC
+ 0.6 V. The device can withstand indefi-
nite operation with inputs in the range of
p
10Ω
300Ω
n
–0.5Vto+7.0V. Deviceoperation willnot a. A 0.1 µF ceramic capacitor should be
beadverselyaffected,however,inputcur- installed between VCC and Ground
rentlevelswillbewellin excessof100mA. leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actualtest conditions may vary from
should be installed between device VCC
FIGURE B. OUTPUT CIRCUIT
those designated but operation is guar-
and the tester common, and device
anteed as specified.
VCC
ground and tester common.
5. Supply current for a given application
can be accurately approximated by:
b. Ground and VCC supply planes must
be brought directly to the DUTsocket or
n
contactor fingers.
2
NCV F
c. Input voltages should be adjusted to
compensate for inductive ground and
VCC noise to maintain required DUT in-
putlevelsrelativetotheDUTground pin.
where
4
OUTPUT
n+
N = total number of device outputs
C = capacitive load per output
V = supply voltage
D1
p–
n
10. Each parameter is shown as a mini-
mum or maximum value.Input require-
mentsarespecified from thepointofview
of the external system driving the chip.
Setup time,for example,is specified as a
minimum sincetheexternalsystem must
supply atleastthatmuch timetomeetthe
worst-case requirements of all parts.
Responsesfrom theinternalcircuitry are
specified from the point of view of the
device. Output delay, for example, is
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a X MHz clock
rate.
FIGURE C. THRESHOLD LEVELS
t
DIS
tENA
PRELIMINARY
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
OE
0.2 V
0.2 V
HIGH IMPEDANCE
TRISTATE
OUTPUTS
8. These parameters are guaranteed but
not 100% tested.
0.2 V
0.2 V
9. AC specifications are tested with specified as a maximum since worst-
Logic Products
07/06/99–LDS.7710-A
13
L7710
DEVICES INCORPORATED
High-Speed FFT Processor
ORDERING INFORMATION
160-pin
GND
CTM
SZ1
1
2
3
4
5
6
7
8
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
VCC
FILT
INV
DBO
SZ0
OVC1
OVC0
VCC
AVG
XYMODE
DOUT15
DOUT14
DOUT13
DOUT12
GND
GND
DIN15
DIN14
DIN13
DIN12
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
DOUT11
DOUT10
DOUT9
DOUT8
GND
ORD/OWE
/EF
VCC
DOUT7
DOUT6
DOUT5
DOUT4
GND
GND
DIN11
DIN10
DIN9
DIN8
VCC
/FF
DRD/DWE
GND
Top
View
DIN7
DIN6
DIN5
DIN4
VCC
VCC
DOUT3
DOUT2
DOUT1
DOUT0
GND
GND
DIN3
DIN2
DIN1
DIN0
VCC
VCC
STDBY
HOLD
CLKO
GND
SCL0
SCL1
GND
CACC1
CACC0
CB
AIN10
AIN9
82
81
SCL2
GND
VCC
Plastic Quad Flatpack
(Q6)
Flatpack
(F4)
Speed
0°Cto+70°C—COMMERCIAL SCREENING
10 ns
L7710QC10
–40°Cto+85°C—INDUSTRIAL SCREENING
10 ns
L7710QI10
PRELIMINARY
–55°Cto+125°C—MIL-STD-883COMPLIANT
12 ns
L7710FMB12
Logic Products
07/06/99–LDS.7710-A
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