L7C109DEB20 [LOGIC]
Standard SRAM, 128KX8, 20ns, CMOS, CDIP32;
| 型号： | L7C109DEB20 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Standard SRAM, 128KX8, 20ns, CMOS, CDIP32 CD 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L7C108
L7C109
128K x 8 Static RAM
Pin Configuration
FEATURES
128K x 8 Static RAM with Chip
32-pin Ceramic DIP
32-pin Ceramic SOJ
Select Powerdown, Output Enable
and Single or Dual Chip Selects
32-pin Quad CLCC
32-pin Ceramic LCC
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
V
A
CE
CC
15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
V
A
CE
WE
CC
15
A
A
A
16
14
12
A16
A14
A12
4
3
2
1
32 31 30
29
2
2
WE
5
6
7
8
9
A7
A6
A5
A4
A3
WE
A13
A8
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
OE
A10
CE
DQ
DQ
DQ
DQ
DQ
13
8
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
13
Data Retention at 2 V for Battery
Backup Operation
28
27
26
25
24
23
22
21
8
9
9
A9
11
Top
View
11
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
A11
OE
A10
CE1
DQ8
9
9
OE
A10
A2 10
A1 11
A0 12
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Package Styles Available:
CE
DQ
DQ
DQ
DQ
DQ
8
7
6
5
4
8
7
6
5
4
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ꢀ
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DQ1 13
DQ
DQ
DQ
DQ
DQ
DQ
14 15 16 17 18 19 20
VSS
VSS
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OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
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devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
Memory locations are specified on
address pins A0 through A16. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE1 and OE
LOW while WE remains HIGH. For the
L7C109, CE1 and OE must be LOW
while CE2 and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE1 or OE is
HIGH, or CE2ꢀꢆ/ꢌ&ꢈꢅꢍꢉꢀRUꢀ:(ꢀLVꢀ/2:ꢊ
Writing to an addressed location is
accomplished when the active-low CE1
and WE inputs are both LOW, and CE2
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Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
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retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
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matching access and cycle times. The
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
1
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
L7C108-109 Block Diagram
128 K x 8
MEMORY ARRAY
9
ROW
ADDRESS
CE1
WE
OE
8
COLUMN SELECT
& COLUMN SENSE
CONTROL
I/O7 - 0
CE2
(L7C109 only)
8
COLUMN ADDRESS
TRUTH
TABLE
Mode
Standby
Standby
Standby
Standby
Read
OE
X
CE1
CE2*
WE
X
DQ
POWER
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6WDQGE\ꢀꢆI&&ꢂꢉꢀ
6WDQGE\ꢀꢆI&&ꢁꢉꢀ
6WDQGE\ꢀꢆI&&ꢁꢉ
Active
X
t VIH
High - Z
High - Z
High - Z
High - Z
4
X
d VIL
X
X
X
X
t VCC - 0.2 V
X
X
d GND + 0.2 V
X
L
L
X
L
H
H
H
H
High - Z
H
Active
Read
Write
X
H
D
L
L
Active
* Note: for L7C109 only
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
2
L7C108
L7C109
128K x 8 Static RAM
MAXIMUM
RATINGS Above which useful life may be impaired (Notes 1, 2)
Storage temperature…………………………………………...….……............……
Operating ambient temperature………………………………………......….......…
Vcc supply voltage with respect to ground…………….…………………….......….
Input signal with respect to ground.………………………….………………..…..…
Signal applied to high impedance output……………………………………........…
-65°C to +150°C
-55°C to +125°C
-0.5 V to +7.0 V
-3.0 V to +7.0 V
-3.0 V to +7.0 V
Output current into low outputs………………………………………….…......................……
25 mA
Latchup current….........................……………..…………………………...……................
>200 mA
OPERATING
CONDITIONS To meet specified electrical and switching characteristics
Supply Voltage
4.5 V d VCC d 5.5 V
2.0 V d VCC d 5.5 V
Mode
Temperature Range (Ambient)
-55°C to +125°C
Active, Operation, Military
Data Retention, Military
-55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5)
L7C108/109
L7C108/109-L
Symbol Parameter
Test Condition
Min
Max
Min
Max
Unit
Output High Voltage
2.4
V
VOH
VOL
VIH
2.4
VCC = 4.5V, IOH = -4 mA
0.4
Vcc
+0.5
0.8
+10
+10
25
Output Low Voltage
Input High Voltage
V
V
0.4
Vcc
+0.3
0.8
+10
+10
25
IOL = 8 mA
2.2
2.2
Input Low Voltage
-0.5
-10
-10
V
VIL
IIx
-3.0
-10
-10
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μA
μA
mA
mA
mA
pF
Input Leakage Current
Output Leakage Current
VCC Current, TTL Standby
VCC Current, CMOS Standby
VCC Current, Data Retention
Input Capacitance
GND < VIN < VCC
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ICC2
ICC3
ICC4
CIN
ꢆ1RWHꢀꢌꢉ
10
5
ꢆ1RWHꢀꢎꢉ
-
0.75
8
VCC = ꢂꢀ9ꢀꢆ1RWHVꢀꢍꢏꢀꢈꢅꢉ
Ambient Temp = 25°C, VCC = 5 V
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8
8
pF
Output Capacitance
COUT
8
L7C108/109
L7C108/109-L
Symbol Parameter
Test Condition
15 20 25 35 45 15 20 25 35 45 Unit
VCC Current, Active
ICC1
ꢆ1RWHꢀꢐꢉ
mA
140 140 140 135 125 140 140 140 130 125
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
3
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
35/35-L
15/15-L
25/25-L
20/20-L
45/45-L
Min Max Min Max Min Max Min Max Min Max
Symbol Parameter
tAVAV
t$949
t$94;
t(/49
t(/4;
t(+4=
t*/49
t*/4;
t*+4=
tPU
15
20
25
35
45
Read Cycle Time
15
15
20
20
25
25
35
35
45
45
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Address Change to Output Change
3
3
3
3
3
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Output Enable Low to Output Valid
3
3
3
3
3
7
8
8
10
10
15
15
20
20
10
0
0
0
0
0
0
0
0
0
0
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6
6
10
15
20
READ CYCLE - ADDRESS CONTROLLED Notes 13, 14
tAVAV
ADDRESS
tAVQV
DATA OUT
PREVIOUS DATA VALID
tAVQX
DATA VALID
tPD
tPU
ICC
READ CYCLE - CE/OE CONTROLLED NOTES 13, 15
tAVAV
CE
t
EHQZ
t
ELQV
t
ELQX
OE
t
GHQZ
t
GLQV
t
GLQX
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
50%
t
PD
tPU
50%
Icc
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
4
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
tPD
Parameter
Min
Min
Min Max Min Max Min Max
Max
Max
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15
20
25
35
45
0
0
0
0
0
tCDR
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DATA RETENTION Notes 9, 10
DATA RETENTION MODE
V
CC
4.5 V
4.5 V
≥ 2 V
t
CDR
t
PD
CE
VIH
VIH
WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Min
Min
Min Max Min Max Min Max
Max
Max
Symbol Parameter
tAVAV
tELWH
tAVWL
tAVWH
tWHAX
tWLWH
tDVWH
tWHDX
t:+4;
t:/4=
Write Cycle Time
35
45
15
12
0
20
12
0
25
20
0
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Setup to End of Write Cycle
Address Hold After End Of Write
Write Enable Pulse Width Low
25
0
35
0
25
0
35
0
15
0
17
0
20
0
30
20
0
40
20
0
12
7
15
10
0
20
12
0
Data Setup to End of Write Cycle
Data Hold to End of Write
0
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5
5
5
5
5
7
8
10
25
30
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
5
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS Over Operating Range
WRITE CYCLE - WE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
t
ELWH
CE
t
WHAX
tAVWH
WE
t
WLWH
t
DVWH
t
AVWL
t
WHDX
DATA IN
DATA -IN VALID
t
WLQZ
t
WHQX
HIGH IMPEDANCE
DATA OUT
t
PD
t
PU
t
PU
ICC
WRITE CYCLE - CE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
tAVWL
t
AELWH
CE
t
AVWH
t
WHAX
tWLWH
WE
t
DVWH
DATA-IN VALID
HIGH IMPEDANCE
PU PD
t
WHDX
DATA IN
DATA OUT
t
t
I
CC
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
6
L7C108
L7C109
128K x 8 Static RAM
PACKAGE INFORMATION
PKG K: 32L CERAMIC DUAL LCC (MD-K11)
PIN 1
IDENTIFIER
0.070 0.007
0.082 0.008ꢀ
0.825 0.008
0.055 0.006
0.400 0.005
0.085 0.008
0.050 TYP
See
detail A
0.006 ~ 0.22 TYP
0.025 0.00ꢀ
0.050 TYP
0.00ꢀ ~ 0.015
detail A
*All measurements in inches
SMD 5962-89598 Case ‘U’ / Ordering Code ‘K’
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
7
L7C108
L7C109
128K x 8 Static RAM
PACKAGE INFORMATION
PKG KA: 32L CERAMIC QUAD LCC (MD-KA1)
0.065 0.006
0.450 + 0.008
- 0.005
0.0821 0.007ꢀ
+ 0.10
- 0.05
0.550
0.020 0.002
0.ꢀ00 0.005
0.085 0.008
0.050 TYP
0.400 0.005
See detail A
0.008R
detail A
0.050 0.005
0.025 0.00ꢀ
*All measurements in inches
SMD 5962-89598 Case ‘M’ / Ordering Code “KA”
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
8
L7C108
L7C109
128K x 8 Static RAM
PACKAGE INFORMATION
PKG Y: 32L CERAMIC SOJ (MD-Y1)
0.1ꢀ2 0.020ꢀ
0.005 TYP
ꢀ2
1
0.822 0.008
0.750 0.007
16
17
0.050 BSC
0.425 0.006
0.445 MAX
0.0205 0.0ꢁ1
0.012 0.001ꢀ
0.005 MIN
0.025 REF
0.025 0.00ꢀ TYP
0.0ꢀ8 TYP
0.010 REF
0.075 REF
0.0ꢀ5 0.010
CHAMFER
0.0ꢀ5R TYP
0.020 REF
0.017 0.002
0.ꢀ70 0.010
(Note: Case ‘Y’ ships for Case ‘7’ as compatible replacement)
*All measurements in inches
SMD 5962-89598 Case ‘Y’ and ‘7’ / Ordering Code ‘Y’
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
9
L7C108
L7C109
128K x 8 Static RAM
PACKAGE INFORMATION
PKG D: 32L CERAMIC DIP (MD-D12)
0.1ꢀ5 0.005
0.05 0.0775
0.1471 0.006ꢀ
0.100 0.05 TYP
1.600 0.016
0.018 0.002
0.050 0.002 TYP
0.ꢀ17 0.011
0.170 0.005
0.ꢀ78 0.005
0.050 0.010
0.22 0.015
Lead Location
Guage Plane
Seating Plane
Base Plane
0.010 + 0.002
- 0.001
0.400 0.005
*All measurements in inches
SMD 5962-89598 Case ‘Z’ / Ordering Code ‘D’
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
10
L7C108
L7C109
128K x 8 Static RAM
SMD Cross Reference Table
SMD Part #
LOGIC Part #
LOGIC Part #
SMD Part #
L7C109DMB45
L7C109DMB35
L7C109DMB25
L7C109DMB20
L7C109DMB15
L7C109YMB45
L7C109YMB35
L7C109YMB25
L7C109YMB20
L7C109YMB15
L7C109YMB45
L7C109YMB35
L7C109YMB25
L7C109YMB20
L7C109YMB15
L7C109KAMB45
L7C109KAMB35
L7C109KAMB25
L7C109KAMB20
L7C109KAMB15
L7C109KMB45
L7C109KMB35
L7C109KMB25
L7C109KMB20
L7C109KMB15
5962-8959835MZA
5962-8959836MZA
5962-8959837MZA
5962-8959838MZA
5962-8959841MZA
5962-8959835M7A
5962-8959836M7A
5962-8959837M7A
5962-8959838M7A
5962-8959841M7A
5962-8959835MYA
5962-8959836MYA
5962-8959837MYA
5962-8959838MYA
5962-8959841MYA
5962-8959835MMA
5962-8959836MMA
5962-8959837MMA
5962-8959838MMA
5962-8959841MMA
5962-8959835MUA
5962-8959836MUA
5962-8959837MUA
5962-8959838MUA
5962-8959841MUA
L7C108DMB45
L7C108DMB35
L7C108DMB25
L7C108DMB20
L7C108DMB15
L7C108YMB45
L7C108YMB35
L7C108YMB25
L7C108YMB20
L7C108YMB15
L7C108YMB45
L7C108YMB35
L7C108YMB25
L7C108YMB20
L7C108YMB15
5962-8959827MZA
5962-8959828MZA
5962-8959829MZA
5962-8959839MZA
5962-8959844MZA
5962-8959827M7A
5962-8959828M7A
5962-8959829M7A
5962-8959839M7A
5962-8959844M7A
5962-8959827MYA
5962-8959828MYA
5962-8959829MYA
5962-8959839MYA
5962-8959844MYA
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
11
L7C108
L7C109
128K x 8 Static RAM
SMD Cross Reference Table
SMD Part #
LOGIC Part #
LOGIC Part #
SMD Part #
L7C109DMB45L
L7C109DMB35L
L7C109DMB25L
L7C109DMB20L
L7C109YMB45L
L7C109YMB35L
L7C109YMB25L
L7C109YMB20L
L7C109YMB45L
L7C109YMB35L
L7C109YMB25L
L7C109YMB20L
L7C109KAMB45L
L7C109KAMB35L
L7C109KAMB25L
L7C109KAMB20L
L7C109KMB45L
L7C109KMB35L
L7C109KMB25L
L7C109KMB20L
L7C109FMB20L
L7C108DMB45L
L7C108DMB35L
L7C108DMB25L
L7C108DMB20L
L7C108DMB15L
5962-8959818MZA
5962-8959819MZA
5962-8959820MZA
5962-8959821MZA
5962-8959818M7A
5962-8959819M7A
5962-8959820M7A
5962-8959821M7A
5962-8959818MYA
5962-8959819MYA
5962-8959820MYA
5962-8959821MYA
5962-8959818MMA
5962-8959819MMA
5962-8959820MMA
5962-8959821MMA
5962-8959818MUA
5962-8959819MUA
5962-8959820MUA
5962-8959821MUA
5962-8959821MTA
5962-8959810MZA
5962-8959811MZA
5962-8959812MZA
5962-8959840MZA
5962-8959848MZA
L7C108YMB45L
L7C108YMB35L
L7C108YMB25L
L7C108YMB20L
L7C108YMB15L
L7C108YAMB45L
L7C108YMB35L
L7C108YMB25L
L7C108YMB20L
L7C108YMB15L
5962-8959810M7A
5962-8959811M7A
5962-8959812M7A
5962-8959840M7A
5962-8959848M7A
5962-8959810MYA
5962-8959811MYA
5962-8959812MYA
5962-8959840MYA
5962-8959848MYA
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
12
L7C108
L7C109
128K x 8 Static RAM
ORDERING INFORMATION
L 7C 108 D M B 15 L
Indicates a LOGIC Devices product
SRAM
PART NUMBER:
108 = 1M SRAM with single chip enable (available in packages ‘D’and ‘Y’)
109 = 1M SRAM with dual chip enables (available in ALL packages)
PACKAGE CODE:
D = 32 pin Sidebrazed DIP 400mil
K = 32 pin Ceramic LCC
KA = 32 pin Quad Ceramic LCC
Y = 32 pin Ceramic SOJ
SCREENING LEVEL:
M = Military Temperature, -55ºC to +125ºC
E = Extended Temperature, -40ºC to +105ºC
I = Industrial Temperature, -40ºC to +85ºC
COMPLIANCE:
B = MIL-STD-883 Compliant
SPEED GRADE:
[M]: 15/20/25/35/45
[E]: 15/20/25/35/45
[I]: 15/20/25/35/45
LOW POWER OPTION:
L = Low Power
No Mark Means Standard Power
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
13
L7C108
L7C109
128K x 8 Static RAM
NOTES
1. Maximum Ratings indicate stress specifica-
tions only. Functional operation of these products
at values beyond those indicated in the Operat-
ing Conditions table is not implied. Exposure to
maximum rating conditions for extended periods
may affect reliability of the tested device.
loading for specified IOL and IO+ꢀSOXVꢀꢁꢅꢀS)ꢀꢆ)LJꢊꢀ
ꢈDꢉꢏꢀDQGꢀLQSXWꢀSXOVHꢀOHYHOVꢀRIꢀꢅꢀWRꢀꢁꢊꢅꢀ9ꢀꢆ)LJꢊꢀꢂꢉꢊ
21. Transition is measured ±200 mV from steady
state voltage with specified loading in Fig. 1b.
This parameter is sampled and not 100% tested.
12. Each parameter is shown as a minimum or
maximum value. Input requirements are speci-
fied from the point of view of the external system
driving the chip. For example, tAVEW is specified
as a minimum since the external system must
supply at least that much time to meet the worst-
case requirements of all parts. Responses from
the internal circuitry are specified from the point
of view of the device. Access time, for example,
is specified as a maximum since worst-case
operation of any device always provides data
within that time.
22. All address timings are referenced from the
last valid address line to the first transitioning
address line.
2. The products described by this specifica-
tion include internal circuitry designed to pro-
tect the chip from damaging substrate injection
currents and accumulations of static charge.
Nevertheless, conventional precautions should
be observed during storage, handling, and use
of these circuits in order to avoid exposure to
excessive electrical stress values.
23. CE1, CE2, or WE must be inactive during
address transitions.
24. This product is a very high speed device and
care must be taken during testing in order to real-
ize valid test information. Inadequate attention to
setups and procedures can cause a good part
to be rejected as faulty. Long high inductance
leads that cause supply bounce must be avoided
by bringing the VCC and ground planes directly
up to the contactor fingers. A 0.01 μF high fre-
quency capacitor is also required between VCC
and ground. To avoid signal reflections, proper
terminations must be used.
3. This product provides hard clamping of tran-
sient undershoot. Input levels below ground will
be clamped beginning at –0.6 V. A current in
excess of 100 mA is required to reach –2.0 V.
The device can withstand indefinite operation
with inputs as low as –3 V subject only to power
dissipation and bond wire fusing constraints.
13. WE is high for the read cycle.
ꢈꢄꢊꢀ7KHꢀFKLSꢀLVꢀFRQWLQXRXVO\ꢀVHOHFWHGꢀꢆ&(1 low,
CE2ꢀKLJKꢉꢊ
15. All address lines are valid prior-to or coinci-
dent-with the CE1 and CE2 transition to active.
4. Tested with GND d VOUT d VCC. The device is
disabled, i.e., CE1 = VCC, CE2 = GND.
16. The internal write cycle of the memory is
defined by the overlap of CE1 and CE2 active
and WE low. All three signals must be active to
initiate a write. Any signal can terminate a write
by going inactive. The address, data, and control
input setup and hold times should be referenced
to the signal that becomes active last or becomes
inactive first.
5. A series of normalized curves is available to
supply the designer with typical DC and AC
parametric information for Logic Devices Static
RAMs. These curves may be used to determine
device characteristics at various temperatures
and voltage levels.
Figure 1a.
R
1 480
+5 V
OUTPUT
17. If WE goes low before or concurrent with the
latter of CE1 and CE2 going active, the output
remains in a high impedance state.
6. Tested with all address and data inputs chang-
ing at the maximum cycle rate. The device is con-
tinuously enabled for reading, i.e., CE1 d VIL, CE2
t VIH, WE t VIH, with outputs disabled, OE t VIH.
Input pulse levels are 0 to 3.0 V.
R
2
30 pF
INCLUDING
JIG AND
SCOPE
255
18. If CE1 and CE2 goes inactive before or con-
current with WE going high, the output remains in
a high impedance state.
7. Tested with outputs open and all address and
data inputs stable. The device is continuously
disabled, i.e., CE1 t VIH, CE2 d VIL.
19. Powerup from ICC2 to ICC1 occurs as a result
of any of the following conditions:
Figure 1b.
a. Rising edge of CE2ꢀꢆ&(1ꢀDFWLYHꢉꢀRUꢀWKHꢀIDOOLQJꢀꢀꢀ
edge of CE1ꢀꢆ&(2ꢀDFWLYHꢉꢊ
R1 480
8. Tested with outputs open and all address and
data inputs stable. The device is continuously
disabled, i.e. CE1 = VCC, CE2 = GND. Input
levels are within 0.2 V of VCC or GND.
+5 V
Eꢊꢀꢀ)DOOLQJꢀHGJHꢀRIꢀ:(ꢀꢆ&(1, CE2ꢀDFWLYHꢉꢊ
OUTPUT
Fꢊꢀꢀ7UDQVLWLRQꢀRQꢀDQ\ꢀDGGUHVVꢀOLQHꢀꢆ&(1, CE2,
ꢀꢀꢀꢀDFWLYHꢉꢊ
R
2
255
9. Data retention operation requires that VCC
never drop below 2.0V. CE1 must be t VCC -
0.2 V or CE2 must be d 0.2 V. All other inputs
must meet VIN t VCC - 0.2 V or VIN d 0.2 V to
HQVXUHꢀIXOOꢀSRZHUGRZQꢊꢀꢀ)RUꢀORZꢀSRZHUꢀYHUVLRQꢀꢆLIꢀ
DSSOLFDEOHꢉꢏꢀWKLVꢀUHTXLUHPHQWꢀDSSOLHVꢀRQO\ꢀWRꢀ&(1,
CE2, and WE; there are no restrictions on data
and address.
INCLUDING
5 pF
JIG AND
SCOPE
Gꢊꢀꢀ7UDQVLWLRQꢀRQꢀDQ\ꢀGDWDꢀOLQHꢀꢆ&(1, CE2, and
ꢀꢀꢀꢀꢀ:(ꢀDFWLYHꢉꢊ
The device automatically powers down from ICC1
to ICC2 after tPD has elapsed from any of the prior
conditions. This means that power dissipation is
dependent on only cycle rate, and is not on Chip
Select pulse width.
Figure 2
+3.0 V
90%
10%
<3 ns
10. These parameters are guaranteed but not
100% tested.
90%
20. At any given temperature and voltage con-
dition, output disable time is less than output
enable time for any given device.
10%
GND
11. Test conditions assume input transition times
of less than 3 ns, reference levels of 1.5 V, output
<3 ns
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
14
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
Revision History L7C108/L7C109
Revision Engineer Issue Date Description Of Change
Initial Release
10/8/2008
10/30/2008
07/02/2009
A
B
C
COM
-0
Datasheet Format Revision
Updated specs:
'+ꢑ-0
1.
2.
3.
4.
5.
6.
7.
Added 10ns & 12 speed columns in ICC1 table
Added 10ns speed and AC specs in the AC table
Updated all DC power specs in DC table
Corrected symbol names in AC and Timing diagrams
Added speed bin to ordering info table
Removed commercial temp offering
Added an extended temp offering
06/11/10
Revisions:
D
DH
1.
2.
3.
4.
5.
6.
7.
8.
9.
Removed 10 & 12ns bins
5HPRYHGꢀꢁꢂ/'ꢀ)3ꢀꢆWRꢀEHꢀUHꢃLQWURGXFHGꢀZLKWꢀRXUꢀVLOLFRQꢏꢀLIꢀPDUNHWꢀZDUUDQWVꢉ
5HPRYHGꢀ62-ꢀSDFNDJHꢀYDULDQWꢀv<$w
$GGꢀQRWDWLRQꢀIRUꢀ60'ꢀꢋꢍꢐꢂꢃꢎꢍꢋꢍꢎꢀWKDWꢀ3DFNDJHꢀt<uꢀZLOOꢀEHꢀVXSSOLHGꢀDVꢀDꢀvꢌwꢀFRPSDWLEOHꢀSDFNDJH
Increased ICC1, ICC2, and ICC4@2V for standard power
Increased ICC2 and ICC4@2V for low power
Removed appropriate DSCC and LOGIC part numbers from ordering tables and PN generator
0RGLILHGꢀ/2*,&ꢀ'HYLFHVꢀv<$wꢀSDFNDJHꢀUHIHUHQFHꢀWRꢀt<u
&RUUHFWLRQVꢀWRꢀSDFNDJHꢀGLPHQVLRQVꢀIRUꢀ0'ꢃ.ꢈꢈꢀDQGꢀ0'ꢃ<ꢈ
Updated mechanical drawings for all packages
Revisions:
07/30/10
08/11/10
E
F
-0
DH
1.
2.
3.
4.
5HPRYHGꢀDOOꢀꢈꢅꢎꢀ.$ꢀꢆTXDGꢀ/&&ꢉꢀDQGꢀ.ꢀꢆGXDOꢀ/&&ꢉꢀSDFNDJHꢀYDULDQWVꢀIURPꢀ60'ꢀFURVVꢀUHIHUHQFHꢀWDEOHꢊ
Updated order information chart to reflect current package availabilities.
Changed ICC2 conditions to match ICC3 conditions.
Changed operating current to be calculated during the READ cycle.
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its
products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant informa-
tion before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out
of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of
LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursu-
ant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical compo-
nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
15
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