LMU08 [LOGIC]
8 x 8-bit Parallel Multiplier; 8 ×8位并行乘法器
| 型号： | LMU08 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | 8 x 8-bit Parallel Multiplier |
| 文件： | 总7页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMU08/8U
8 x 8-bit Parallel Multiplier
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LMU08 and LMU8U are high-
speed, low power 8-bit parallel
multipliers. They are pin-for-pin
equivalents with TRW TMC208K and
TMC28KU type multipliers. Full
military ambient temperature range
operation is attained by the use of
advanced CMOS technology.
This facilitates use of the LMU08
product as a double precision operand
in 8-bit systems. The LMU8U oper-
ates on unsigned data, producing an
unsigned magnitude result.
❑ 20 ns Worst-Case Multiply Time
❑ LowPowerCMOSTechnology
❑ LMU08 Replaces TRW TMC208K
❑ LMU8UReplacesTRWTMC28KU
❑ Two’sComplement(LMU08),or
Both the LMU08 and the LMU8U
feature independently controlled
registers for both inputs and the
product, which along with three-state
outputs allows easy interfacing with
microprocessor busses. Provision is
Unsigned Operands (LMU8U)
❑ Three-State Outputs
❑ Package Styles Available:
Both the LMU08 and the LMU8U
produce the 16-bit product of two
8-bit numbers. The LMU08 accepts
• 40-pin PDIP
• 44-pinPLCC, J-Lead
operands in two’s complement format, made in the LMU08 and LMU8U for
and produces a two’s complement proper rounding of the product to
result. The product is provided in two 8-bit precision. The round input is
halves with the sign bit replicated as loaded at the rising edge of the logical
the most significant bit of both halves. OR of CLK A and CLK B for the
LMU08. The LMU8U latches RND on
the rising edge of CLK A only. In
either case, a ‘1’ is added in the most
LMU08/8U BLOCK DIAGRAM
significant position of the lower
A
7-0
B7-0
product byte when RND is asserted.
Subsequent truncation of the least
significant product byte results in a
correctly rounded 8-bit result.
8
8
CLK A
CLK B
A REGISTER
B REGISTER
LMU08 Only
RND
16
8
8
CLK R
RESULT
REGISTER
OEM
OEL
8
8
R
15-8
R7-0
Multipliers
08/16/2000–LDS.08/8U-R
1
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
FIGURE 1A. INPUT FORMATS
AIN
BIN
LMU08 Fractional Two’s Complement
7
6
5
2
1
0
7
6
5
2
1
0
–20 2–1 2–2
2–5 2–6 2–7
–20 2–1 2–2
2–5 2–6 2–7
(Sign)
(Sign)
LMU08 Integer Two’s Complement
7
6
5
2
1
0
7
6
5
2
1
0
–27 26 25
22 21 20
–27 26 25
22 21 20
(Sign)
(Sign)
LMU8U Unsigned Fractional
7
6
5
2
1
0
7
6
5
2
1
0
2–1 2–2 2–3
2–6 2–7 2–8
2–1 2–2 2–3
2–6 2–7 2–8
LMU8U Unsigned Integer
7
6
5
2
1
0
7
6
5
2
1
0
27 26 25
22 21 20
27 26 25
22 21 20
FIGURE 1B. OUTPUT FORMATS
MSP
LSP
LMU08 Fractional Two’s Complement
15 14 13
10
9
8
7
6
5
2
1
0
–20 2–1 2–2
2–5 2–6 2–7
–20 2–8 2–9
2–12 2–13 2–14
(Sign)
(Sign)
LMU08 Integer Two’s Complement
15 14 13
10
9
8
7
6
5
2
1
0
–214 213 212
29 28 27
–214 26 25
22 21 20
(Sign)
(Sign)
LMU8U Unsigned Fractional
15 14 13
2–1 2–2 2–3
10
9
8
7
6
5
2
1
0
2–6 2–7 2–8
2–9 2–10 2–11
2–14 2–15 2–16
LMU8U Unsigned Integer
15 14 13
215 214 213
10
9
8
7
6
5
2
1
0
210 29 28
27 26 25
22 21 20
Multipliers
08/16/2000–LDS.08/8U-R
2
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
VOH
VOL
VIH
Parameter
Test Condition
Min
Typ
Max Unit
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
ICC1
ICC2
8
24 mA
1.0 mA
(Note 7)
Multipliers
08/16/2000–LDS.08/8U-R
3
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LMU08/8U–
*
70
*
20
50
35
Symbol Parameter
Min Max Min Max Min Max Min Max
tMC
tPW
tS
Clocked Multiply Time
70
50
35
20
Clock Pulse Width
20
14
4
20
14
0
10
14
0
8
10
0
Input Register Setup Time
Input Register Hold Time
Output Delay
tH
tD
25
24
22
20
22
20
20
22
20
18
15
15
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LMU08/8U–
*
90
*
60
*
45
*
25
Symbol Parameter
Min Max Min Max Min Max Min Max
tMC
tPW
tS
Clocked Multiply Time
90
60
45
25
Clock Pulse Width
25
20
5
20
15
2
15
15
2
10
15
2
Input Register Setup Time
Input Register Hold Time
tH
tD
Output Delay
35
35
35
22
24
22
22
24
22
20
20
20
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS
tS
tH
INPUT
tPW
tPW
CLK A
CLK B
tMC
CLK R
tD
OEL
OEM
tDIS
tENA
HIGH IMPEDANCE
R15-0
*DISCONTINUED SPEED GRADE
Multipliers
08/16/2000–LDS.08/8U-R
4
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
tended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulationsofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/turn-off times.
Asaresult, caremustbeexercisedinthe
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
V
TH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtestconditionsmayvaryfrom
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
tioncanbeaccuratelyapproximatedby:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximumsinceworst-caseoperationof
anydevicealwaysprovidesdatawithin
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Multipliers
08/16/2000–LDS.08/8U-R
5
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
LMU08 — ORDERING INFORMATION
40-pin — 0.6" wide
44-pin
R
10
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R
R
R
R
11
12
13
14
R
9
2
R
8
3
CLK R
OEM
OEL
4
5
RSM (R15
)
6
5
4
3
2
1
44 43 42 41 40
39
7
OEL
NC
6
BS (B )
7
8
38
37
36
35
34
33
32
31
30
29
(R7
) RSL
BS (B7)
(R7
) RSL
7
B
6
5
9
R6
R5
R4
R3
R2
R1
R0
A0
B
B
6
R
R
R
R
R
R
R
A
A
A
A
A
A
6
5
4
3
2
1
0
0
1
2
3
4
5
8
B
10
11
12
13
14
15
16
17
5
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
B
V
B
B
B
B
4
Top
View
B
V
B
B
B
B
4
CC
3
CC
3
2
2
1
0
1
RND
NC
0
18 19 20 21 22 23 24 25 26 27 28
CLK B
CLK A
AS (A7)
A6
Plastic DIP
(P3)
Plastic J-Lead
Chip Carrier (J1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
50 ns
35 ns
LMU08JC50
LMU08JC35
LMU08PC35
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multipliers
08/16/2000–LDS.08/8U-R
6
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
LMU8U — ORDERING INFORMATION
40-pin — 0.6" wide
44-pin
R10
R9
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R11
R12
R13
R14
R15
B7
2
R8
3
CLK R
OEM
OEL
R7
4
6
5
4
3
2
1
44 43 42 41 40
39
5
7
OEL
NC
6
8
38
37
36
35
34
33
32
31
30
29
R7
R6
R5
R4
R3
R2
R1
R0
A0
B
B
B
7
6
5
7
B6
9
R6
8
B5
10
11
12
13
14
15
16
17
R5
9
GND
B4
GND
R4
10
11
12
13
14
15
16
17
18
19
20
Top
View
B
V
B
B
B
B
4
R3
VCC
B3
CC
3
R2
R1
B2
2
R0
B1
1
A0
B0
NC
0
A1
RND
CLK B
CLK A
A7
18 19 20 21 22 23 24 25 26 27 28
A2
A3
A4
A5
A6
Plastic DIP
(P3)
Plastic J-Lead
Chip Carrier (J1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
LMU8UPC50
LMU8UJC50
LMU8UJC35
50 ns
35 ns
LMU8UPC35
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multipliers
08/16/2000–LDS.08/8U-R
7
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