LMU18JC35 [LOGIC]
16 x 16-bit Parallel Multiplier; 16× 16位并行乘法器
| 型号： | LMU18JC35 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | 16 x 16-bit Parallel Multiplier |
| 文件： | 总7页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMU18
16 x 16-bit Parallel Multiplier
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LMU18 is a high-speed, low by the ENA and ENB controls. When
power 16-bit parallel multiplier. HIGH, these controls prevent appli-
The LMU18 is an 84-pin device cation of the clock to the respective
which provides simultaneous access register. The TCA and TCB controls
❑ 35 ns Worst-Case Multiply Time
❑ Low Power CMOS Technology
❑ Full 32-bit Output Port —
No Multiplexing Required
to all outputs.
specify the operands as two’s com-
plement when HIGH, or unsigned
magnitude when LOW.
❑ Two’s Complement, Unsigned, or
Mixed Operands
The LMU18 produces the 32-bit
product of two 16-bit numbers.
❑ Three-State Outputs
❑ 84-pin PLCC, J-Lead
Data present at the A inputs, along RNDisloadedontherisingedgeofCLK,
with the TCA control bit, is loaded providing either ENA or ENB are LOW.
into the A register on the rising edge RND, when HIGH, adds ‘1’ to the
of CLK. B data and the TCB control most significant bit position of the
bit are similarly loaded. Loading of least significant half of the product.
the A and B registers is controlled Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
LMU18 BLOCK DIAGRAM
Attheoutput, theRightShiftcontrol(RS)
selects either of two output formats. RS
TCA
A
15-0
TCB
B15-0
LOW produces a 31-bit product with a
copy of the sign bit inserted in the MSB
postion of the least significant half. RS
HIGH gives a full 32-bit product. Two
16-bit output registers are provided to
hold the most and least significant
halves of the result (MSP and LSP) as
definedbyRS. Theseregistersareloaded
on the rising edge of CLK, subject to the
ENRcontrol. WhenENRisHIGH, clock-
ing of the result registers is prevented.
16
A REGISTER
16
B REGISTER
CLK
ENA
ENB
RND
RS
For asynchronous output these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
32
FORMAT ADJUST
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP outputs to
be driven by the most significant half of
the result. MSPSEL HIGH routes the
least significant half of the result to the
MSP pins. The MSB of the result is avail-
able in both true and complemented
form to aid implementation of higher
precision multipliers.
16
16
FT
ENR
RESULT
REGISTER
MSPSEL
OEM
OEL
16
16
R
31
R
31-16
R15-0
Multipliers
08/16/2000–LDS.18-O
1
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
FIGURE 1A. INPUT FORMATS
AIN
BIN
Fractional Two’s Complement (TCA, TCB = 1)
15 14 13
2
1
0
15 14 13
2
1
0
–20 2–1 2–2
2–13 2–14 2–15
–20 2–1 2–2
2–13 2–14 2–15
(Sign)
(Sign)
Integer Two’s Complement (TCA, TCB = 1)
15 14 13
2
1
0
15 14 13
2
1
0
–215 214 213
22 21 20
–215 214 213
22 21 20
(Sign)
(Sign)
Unsigned Fractional (TCA, TCB = 0)
15 14 13
2–1 2–2 2–3
2
1
0
15 14 13
2–1 2–2 2–3
2
1
0
2–14 2–15 2–16
2–14 2–15 2–16
Unsigned Integer (TCA, TCB = 0)
15 14 13
215 214 213
2
1
0
15 14 13
215 214 213
2
1
0
22 21 20
22 21 20
FIGURE 1B. OUTPUT FORMATS
MSP
LSP
Fractional Two’s Complement (RS = 0)
31 30 29
18 17 16
2–13 2–14 2–15
15 14 13
2
1
0
–20 2–1 2–2
–20 2–16 2–17
2–28 2–29 2–30
(Sign)
(Sign)
Fractional Two’s Complement (RS = 1)
31 30 29
18 17 16
2–12 2–13 2–14
15 14 13
2–15 2–16 2–17
2
1
0
–21 20 2–1
2–28 2–29 2–30
(Sign)
Integer Two’s Complement (RS = 1)
31 30 29
18 17 16
218 217 216
15 14 13
215 214 213
2
1
0
–231 230 229
22 21 20
(Sign)
Unsigned Fractional (RS = 1)
31 30 29
2–1 2–2 2–3
18 17 16
2–14 2–15 2–16
15 14 13
2–17 2–18 2–19
2
1
0
2–30 2–31 2–32
Unsigned Integer (RS = 1)
31 30 29
231 230 229
18 17 16
218 217 216
15 14 13
215 214 213
2
1
0
22 21 20
Multipliers
08/16/2000–LDS.18-O
2
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Input Current
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
ICC1
ICC2
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
25
45 mA
1.5 mA
(Note 7)
Multipliers
08/16/2000–LDS.18-O
3
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LMU18–
*
65
*
20
45
35
Symbol Parameter
Min Max Min Max Min Max Min Max
tMC
tMUC
tPW
tS
Clocked Multiply Time
Unclocked Multiply Time
Clock Pulse Width
65
85
45
65
35
55
20
30
15
15
5
15
15
5
15
12
5
9
11
1
Input Setup Time
tH
Input Hold Time
tD
Output Delay
30
25
25
24
30
25
20
20
28
25
20
20
18
18
18
18
tSEL
tENA
tDIS
Output Select Delay
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LMU18–
*
75
*
55
*
45
*
25
Symbol Parameter
Min Max Min Max Min Max
tMC
tMUC
tPW
tS
Clocked Multiply Time
75
95
55
85
45
65
25
38
Unclocked Multiply Time
Clock Pulse Width
20
15
5
15
15
5
15
12
5
10
12
2
Input Setup Time
tH
Input Hold Time
tD
Output Delay
35
30
25
24
35
30
20
20
33
30
20
20
20
20
20
20
tSEL
tENA
tDIS
Output Select Delay
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS
t
S
tH
INPUT
ENA, ENB
ENR
tS
tH
tPW
tPW
tPW
CLOCK
t
D
tMC
t
MUC
MSPSEL
t
SEL
OEM
OEL
t
DIS
tENA
HIGH IMPEDANCE
R
31-0
*DISCONTINUED SPEED GRADE
Multipliers
08/16/2000–LDS.18-O
4
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured
maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with
tended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulationsofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/turn-off times.
Asaresult, caremustbeexercisedinthe
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
V
TH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtestconditionsmayvaryfrom
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tioncanbeaccuratelyapproximatedby:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximumsinceworst-caseoperationof
anydevicealwaysprovidesdatawithin
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Multipliers
08/16/2000–LDS.18-O
5
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
ORDERING INFORMATION
84-pin
11 10
12
9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
B
B
B
B
B
B
10
11
12
13
14
15
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
A
A
A
A
A
11
12
13
14
15
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ENA
RND
TCA
TCB
ENB
CLK
OEL
GND
VCC
Top
View
VCC
GND
GND
MSPSEL
FT
R
0
1
2
3
4
5
6
7
8
9
R
R
R
R
R
R
R
R
R
RS
OEM
ENR
R
R
R
R
31
31
30
29
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Plastic J-Lead Chip Carrier
(J3)
Speed
0°C to +70°C — COMMERCIAL SCREENING
45 ns
35 ns
LMU18JC45
LMU18JC35
Multipliers
08/16/2000–LDS.18-O
6
LMU18
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
ORDERING INFORMATION
84-pin
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
B
9
B
7
B
6
8
B
4
B
1
2
0
B
3
1
0
A
2
3
4
A
5
6
A
7
9
A
8
A
11
13
14
B
B
B
12
13
15
B
B
B
10
11
14
B
B5
B
B
A
A
A
A
A
A
A
A
A
10
12
A
A
15 ENA
Top View
Through Package
(i.e., Component Side Pinout)
OEL CLK GND
V
CC TCA TCB
R
R
R
R
R
R
0
1
4
6
7
9
ENB
VCC
GND GND RND
R
R
R
2
5
8
R
3
RS
FT MSPSEL
ENR OEM
R17
R18
R22
R21
R20
R
R
R
30
29
26
R
R
R
31
31
28
K
L
R
R
10
12
R
R
11
13
R
R
14 GND
V
CC
R
R
24
23
R
27
25
15
R
16
R19
R
Discontinued Package
Ceramic Pin Grid Array
(G3)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multipliers
08/16/2000–LDS.18-O
7
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