LMU217 [LOGIC]

16 x 16-bit Parallel multiplier; 16× 16位并行乘法器


型号：	LMU217
厂家：	LOGIC DEVICES INCORPORATED
描述：	16 x 16-bit Parallel multiplier 16× 16位并行乘法器
文件：	总6页 (文件大小：181K)
中文：	中文翻译
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LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

LMU217

16 x 16-bit Parallel multiplier

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LMU217 is a high-speed, low RND is loaded on the rising edge of

❑ 25 ns Worst-Case Multiply Time

❑ Low Power CMOS Technology

power 16-bit parallel multiplier.

CLK, provided either ENA or ENB are

LOW. RND, when HIGH, adds ‘1’ to

the most significant bit position of the

least significant half of the product.

Subsequent truncation of the 16 least

significant bits produces a result

correctly rounded to 16-bit precision.

❑ Replaces Cypress CY7C517,

The LMU217 produces the 32-bit prod-

uct of two 16-bit numbers. Data present

at the A inputs, along with the TCA

control bit, is loaded into the A register

on the rising edge of CLK. B data and

the TCB control bit are similarly

IDT 7217L, and AMD Am29517

❑ Single Clock Architecture with

❑ Two’s Complement, Unsigned, or

Mixed Operands

loaded. Loading of the A and B At the output, the Right Shift control

registers is controlled by the ENA and (RS) selects either of two output formats.

ENB controls. When HIGH, these con- RS LOW produces a 31-bit product

trols prevent application of the clock to withacopyofthesignbitinsertedinthe

the respective register. The TCA and MSBpostionoftheleastsignificanthalf.

TCB controls specify the operands as RSHIGHgivesafull32-bitproduct. Two

two’s complement when HIGH, or 16-bit output registers are provided to

❑ Three-State Outputs

❑ 68-pin PLCC, J-Lead

unsigned magnitude when LOW.

hold the most and least significant

halves of the result (MSP and LSP) as

defined by RS. These registers are

loaded on the rising edge of CLK, subject

to the ENR control. When ENR is

HIGH, clocking of the result registers is

prevented.

LMU217 BLOCK DIAGRAM

15-0

TCA

15-0

TCB

A REGISTER

For asynchronous output, these registers

may be made transparent by setting the

feed through control (FT) HIGH and

ENR LOW.

CLK

ENA

ENB

B REGISTER

The two halves of the product may be

routed to a single 16-bit three-state

output port (MSP) via a multiplexer.

MSPSEL LOW causes the MSP outputs

to be driven by the most significant half

of the result. MSPSEL HIGH routes the

least significant half of the result to the

MSP pins. In addition, the LSP is

available via the B port through a sepa-

rate three-state buffer.

RND

FORMAT ADJUST

ENR

RESULT

MSPSEL

OEM

OEL

31-16

Multipliers

08/16/2000–LDS.217-H

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

FIGURE 1A. INPUT FORMATS

AIN

BIN

Fractional Two’s Complement (TCA, TCB = 1)

15 14 13

–2⁰2^–12^–2

2^–132^–142^–15

–2⁰2^–12^–2

2^–132^–142^–15

(Sign)

Integer Two’s Complement (TCA, TCB = 1)

15 14 13

–2¹⁵2¹⁴2¹³

2²2¹2⁰

–2¹⁵2¹⁴2¹³

2²2¹2⁰

(Sign)

Unsigned Fractional (TCA, TCB = 0)

15 14 13

2^–12^–22^–3

15 14 13

2^–12^–22^–3

2^–142^–152^–16

Unsigned Integer (TCA, TCB = 0)

15 14 13

2¹⁵2¹⁴2¹³

15 14 13

2¹⁵2¹⁴2¹³

2²2¹2⁰

FIGURE 1B. OUTPUT FORMATS

MSP

LSP

Fractional Two’s Complement (RS = 0)

31 30 29

18 17 16

2^–132^–142^–15

15 14 13

–2⁰2^–12^–2

–2⁰2^–162^–17

2^–282^–292^–30

(Sign)

Fractional Two’s Complement (RS = 1)

31 30 29

18 17 16

2^–122^–132^–14

15 14 13

2^–152^–162^–17

–2¹2⁰2^–1

2^–282^–292^–30

(Sign)

Integer Two’s Complement (RS = 1)

31 30 29

18 17 16

2¹⁸2¹⁷2¹⁶

15 14 13

2¹⁵2¹⁴2¹³

–2³¹2³⁰2²⁹

2²2¹2⁰

(Sign)

Unsigned Fractional (RS = 1)

31 30 29

2^–12^–22^–3

18 17 16

2^–142^–152^–16

15 14 13

2^–172^–182^–19

2^–302^–312^–32

Unsigned Integer (RS = 1)

31 30 29

2³¹2³⁰2²⁹

18 17 16

2¹⁸2¹⁷2¹⁶

15 14 13

2¹⁵2¹⁴2¹³

2²2¹2⁰

Multipliers

08/16/2000–LDS.217-H

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

OPERATING CONDITIONS To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

0°C to +70°C

Supply Voltage

4.75 V ≤ VCC ≤ 5.25 V

4.50 V ≤ VCC ≤ 5.50 V

Active Operation, Commercial

Active Operation, Military

–55°C to +125°C

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Symbol Parameter

Test Condition

Min

Typ

Max Unit

VOH

VOL

VIH

Output High Voltage

VCC = Min., IOH = –2.0 mA

VCC = Min., IOL = 8.0 mA

2.4

Output Low Voltage

Input High Voltage

Input Low Voltage

0.5

VCC

0.8

2.0

0.0

VIL

(Note 3)

IIX

Input Current

Ground ≤ VIN ≤ VCC (Note 12)

Ground ≤ VOUT ≤ VCC (Note 12)

(Notes 5, 6)

±20

µA

IOZ

ICC1

ICC2

Output Leakage Current

VCC Current, Dynamic

VCC Current, Quiescent

25 mA

1.0 mA

(Note 7)

Multipliers

08/16/2000–LDS.217-H

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

SWITCHING CHARACTERISTICS

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

LMU217–

Symbol Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

tMC

Clocked Multiply Time

tMUC

tPW

Unclocked Multiply Time

Clock Pulse Width

Input Setup Time

Input Hold Time

Output Delay

tSEL

tENA

tDIS

Output Select Delay

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

LMU217–

Symbol Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

tMC

Clocked Multiply Time

tMUC

tPW

Unclocked Multiply Time

Clock Pulse Width

Input Setup Time

Input Hold Time

Output Delay

tSEL

tENA

tDIS

Output Select Delay

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

SWITCHING WAVEFORMS

INPUT

ENA, ENB

ENR

tPW

CLK

tMC

tMUC

MSPSEL

tSEL

OEM

OEL

tDIS

tENA

HIGH IMPEDANCE

31-0

*DISCONTINUED SPEED GRADE

Multipliers

08/16/2000–LDS.217-H

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

NOTES

1. Maximum Ratings indicate stress 9. AC specifications are tested with

11. For the tENA test, the transition is

specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point

ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except

those indicated in the Operating Condi-

with datasheet loads. For the tDIS test,

the transition is measured to the

tDIS test), and input levels of nominally

tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured

maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with

tended periods may affect reliability.

±10mA loads. The balancing volt-

age, VTH, is set at 3.5 V for Z-to-0

specified IOH and IOL at an output

voltage of VOH min and VOL max

2. The products described by this spec-

ification include internal circuitry de-

signedto protect the chipfrom damag-

ing substrate injection currents and ac-

cumulationsofstaticcharge. Neverthe-

less, conventional precautions should

be observed during storage, handling,

and use of these circuits in order to This device has high-speed outputs ca-

avoid exposure to excessive electrical pable of large instantaneous current

respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-

bridge with upper and lower current to-1 and 1-to-Z tests.

sources of IOH and IOL respectively,

12. These parameters are only tested at

and a balancing voltage of 1.5 V may be

the high temperature extreme, which is

used. Parasitic capacitance is 30 pF

the worst case for leakage current.

minimum, and may be distributed.

FIGURE A. OUTPUT LOADING CIRCUIT

stress values.

pulses and fast turn-on/turn-off times.

Asaresult, caremustbeexercisedinthe

testing of this device. The following

measures are recommended:

DUT

3. Thisdeviceprovideshardclampingof

transient undershoot and overshoot. In-

put levels below ground or above VCC

will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be

VCC + 0.6 V. The device can withstand installed between VCC and Ground

indefinite operation with inputs in the leads as close to the Device Under Test

range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors

FIGURE B. THRESHOLD LEVELS

ENA

tDIS

tion will not be adversely affected, how-

ever, input current levels will be well in and the tester common, and device

should be installed between device VCC

1.5 V

excess of 100 mA.

ground and tester common.

3.5V Vth

1.5 V

OL*

0.2 V

4. Actualtestconditionsmayvaryfrom

b. Ground and VCC supply planes

those designated but operation is guar- must be brought directly to the DUT

anteed as specified. socket or contactor fingers.

OH*

0V Vth

VOL*

Measured VOL with IOH = –10mA and IOL = 10mA

OH* Measured VOH with IOH = –10mA and IOL = 10mA

5. Supply current for a given applica- c. Input voltages should be adjusted to

tioncanbeaccuratelyapproximatedby:

compensateforinductivegroundand VCC

noise to maintain required DUT input

levels relative to the DUT ground pin.

NCV F

where

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

specified as a minimum since the exter-

nal system must supply at least that

much time to meet the worst-case re-

quirementsofallparts. Responsesfrom

the internal circuitry are specified from

the point of view of the device. Output

delay, for example, is specified as a

maximumsinceworst-caseoperationof

anydevicealwaysprovidesdatawithin

that time.

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with all outputs changing ev-

ery cycle and no load, at a 5 MHz clock

rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed

but not 100% tested.

Multipliers

08/16/2000–LDS.217-H

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

ORDERING INFORMATION

68-pin

64-pin

68 67 66 65 64 63 62 61

R31

R30

R29

R28

R27

R26

R25

R24

R23

R22

R21

R20

R19

R18

R17

R16

Top

View

OEL

CLK

ENB

OEL

CLK

ENB

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Discontinued Package

Plastic J-Lead

Chip Carrier (J2)

Ceramic Flatpack

(F4)

Speed

0°C to +70°C — COMMERCIAL SCREENING

LMU217JC35

35 ns

25 ns

LMU217JC25

–55°C to +125°C — COMMERCIAL SCREENING

–55°C to +125°C — MIL-STD-883 COMPLIANT

Multipliers

08/16/2000–LDS.217-H

LMU217 [LOGIC]

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