PL3150 [LUNSURE]

lonworks; LonWorks技术


型号：	PL3150
厂家：	Lunsure Electronic
描述：	lonworks LonWorks技术
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PL 3120 and PL 3150 Power Line Smart Transceivers

Models 15310-1000, 15320-960, 15311R-1000, and 15321R-960

Combines an ANSI-709.2 compliant Power Line Transceiver

with an ANSI 709.1 compliant Neuron^®3120 or Neuron 3150

processor core

Designed to comply with FCC, Industry Canada, Japan MPT,

and European CENELEC EN 50065-1 power line communica-

tions regulations

Supports CENELEC A-band and C-band operation

Dual carrier frequency mode and digital signal processing

4K Bytes of embedded EEPROM for application code and

conﬁguration data on the PL 3120 Power Line Smart Transceiver

and 0.5K Bytes of embedded EEPROM for conﬁguration data

on the PL 3150 Power Line Smart Transceiver

Overview

Interface for external memory for applications with larger mem-

ory requirements (PL 3150 Power Line Smart Transceiver only)

The PL 3120 and PL 3150 Power Line Smart Transceivers

2K Bytes of embedded RAM for buffering network data and

network variables

integrate a Neuron processor core with a power line transceiver,

making them ideal for appliance, audio/video, lighting,

heating/cooling, security, metering, and irrigation applications.

Essentially a system-on-a-chip, the Power Line Smart Transceivers

feature a highly reliable narrow-band power line transceiver, an

8-bit Neuron processor core for running applications and managing

network communications, a choice of on-board or external

memory, and an extremely small form factor – all at a price that

is compelling for even the most cost-sensitive consumer product

applications.

Full duplex hardware UART and SPI serial interfaces

12 I/O pins with 38 programmable standard I/O modes to

minimize external interface circuitry

-40 to +85°C operating temperature range

• Unique dual carrier frequency feature automatically selects

an alternate secondary communication frequency should the

primary frequency be blocked by noise;

• Highly efficient, patented, low-overhead forward error

correction (FEC) algorithm to overcome errors induced by

noise;

A Global Product

Compliant with FCC, Industry Canada, Japan MPT, and

European CENELEC EN50065-1 regulations, the PL 3120 and PL

3150 Power Line Smart Transceivers can be used in applications

worldwide.

The Power Line Smart Transceivers implement the CENELEC

access protocol, which can be enabled or disabled by the user. This

eliminates the need for users to develop the complex timing and

access algorithms mandated under CENELEC EN50065-1.

Additionally, the Power Line Smart Transceivers can operate in

either the CENELEC utility (A-band) or general signaling

(C-band) bands, eliminating the need to stock multiple parts for

different applications.

• Sophisticated digital signal processing, noise cancellation,

and distortion correction algorithms. These features correct

for a wide variety of signaling impediments, including

impulsive noise, continuous tone noise, and phase distortion;

• High output, low distortion external ampliﬁer design that

can deliver 1Ap-p into low impedance loads, eliminating

the need for expensive phase couplers in typical residential

applications.

The combination of these special features enable the Power

Line Smart Transceivers to operate reliably in the presence of

consumer electronics, power line intercoms, motor noise, electron-

ic ballasts, dimmers, and other typical sources of interference. The

Power Line Smart Transceivers can communicate over virtually

any AC or DC power mains, as well as unpowered twisted pair, by

way of a low-cost, external coupling circuit.

The PL 3120 Power Line Smart Transceiver is targeted at very

low cost designs that require up to 4K Bytes of application code,

and an ultra-compact 38 TSSOP package. The chip includes 4K

Unmatched Performance

Intermittent noise sources, impedance changes, and attenuation

make the power line a hostile signaling environment. The PL 3120

and PL 3150 Power Line Smart Transceivers incorporate a variety

of technical innovations to insure reliable operation:

Bytes of EEPROM and 2K Bytes of RAM. The Neuron system

ﬁrmware and software application libraries are contained in on-

chip ROM.

The PL 3150 Power Line Smart Transceiver is intended for

applications that need to address up to 58K Bytes of external

memory (16K Bytes is dedicated to the Neuron system ﬁrmware)

using a 64 LQFP package. The chip includes 0.5K Bytes of

EEPROM and 2K Bytes of RAM.

The PL 3120 and PL 3150 Power Line Smart Transceivers

operate at either 6.5536MHz or 10.0MHz. The 6.5536MHz clock

frequency enables the Power Line Smart Transceiver to communi-

cate in the CENELEC A-band, which is used for metering and

utility applications. The 10MHz clock frequency supports the

CENELEC C-band, which is used for general purpose signaling

and all non-utility related applications.

Application programs stored in the embedded EEPROM

(PL 3120 Power Line Smart Transceiver) or in the external non-

volatile memory (PL 3150 Power Line Smart Transceiver) may be

updated over the power line network. This valuable feature enables

products to be updated without physically accessing them, i.e.,

from a local PC with a power line interface or from a remote

service center through an i.LON^®Internet Server. The embedded

EEPROM may be written up to 10,000 times with no data loss.

Data stored in the EEPROM will be retained for at least ten years.

Flexible I/O, Simple Conﬁguration

The PL 3120 and PL 3150 Power Line Smart Transceivers

provide 12 I/O pins which can be conﬁgured to operate in one or

more of 38 predeﬁned standard input/output modes. Combining a

wide range of I/O models with two on-board timer/counters

enables the PL 3120 and PL 3150 Power Line Smart Transceivers

to interface with application circuits using minimal external logic

or software development. The Power Line Smart Transceivers also

feature a full duplex hardware UART supporting baud rates of up

to 115kbps, and an SPI interface that operates up to 625kbps.

External Components

Only a small number of inexpensive external components are

required to create a complete Power Line Smart Transceiver-based

device (see the PL 3120 / PL 3150 Power Line Smart Transceiver

Block Diagram). These components include:

• Discrete interface circuitry comprised of roughly ﬁfty

components, primarily resistors and capacitors. This circuitry

provides “front-end” ﬁltering for the on-chip A/D, and implements

the power ampliﬁer that drives the on-chip D/A transmit signal

onto the power line. Echelon offers a comprehensive Development

Support Kit* (DSK) with which customers can implement this

interface circuitry. Contact your salesperson for details about

purchasing a DSK.

• Coupling circuit consisting of approximately ten components,

mainly capacitors and inductors, which acts as a simple high-pass

ﬁlter located between the Power Line Smart Transceiver and the

power mains. This circuitry provides surge and line transient

protection in addition to blocking the low frequency, 50Hz/60Hz

AC mains signal. Detailed schematics are provided in the PL 3120

/ PL 3150 Power Line Smart Transceiver Data Book.

• The new RoHS compliant Revision B Power Line Smart

Transceivers eliminate the need for an external inverter, thereby

reducing the cost of external components. Circuits without an

external inverter can only be used with Revision B parts (15311R-

1000 PL 3120 Power Line Smart Transceiver and 15321R-960

PL 3150 Power Line Smart Transceiver).

Inexpensive Power Supply

The PL 3120 and PL3150 Power Line Smart Transceivers use

+8.5 to +18VDC and +5VDC power supplies and support very low

receive mode current consumption. The wide power supply range

and very low receive power requirements allow the use of inex-

pensive power supplies.

Additionally, the Power Line Smart Transceivers incorporate a

power management feature that constantly monitors the status of

the device’s power supply. If during transmission the power supply

voltage falls to a level that is insufficient to ensure reliable signal-

ing, the transceiver stops transmitting until the power supply

voltage rises to an acceptable level. This unique feature allows the

use of a power supply with one-third the current capacity other-

wise required. The net result is a reduction in the size, cost, and

thermal dissipation of the power supply. Power management is

especially useful for high volume, low-cost consumer products

such as electrical switches, motion detectors, outlets, light sensors,

and dimmers.

*Echelon Corporation has developed and patented certain methods of implementing

circuitry external to the PL 3120 and PL 3150 Power Line Smart Transceiver chips.

These patents are licensed pursuant to the Echelon PL 3120 / PL 3150 Power Line

Smart Transceiver Development Support Kit (DSK) License Agreement.

PL 3120 / PL 3150 Power Line Smart Transceiver Block Diagram

General Speciﬁcations

Function

Emissions compliance

Description

Designed to be compliant with FCC, Industry Canada, Japan MPT, and CENELEC EN50065-1

speciﬁcation for low-voltage signaling

Bit rate

Communication technique

Carrier frequencies

5.4kbps raw bit rate in CENELEC C-band and 3.6kbps in CENELEC A-band

Dual Frequency BPSK with DSP-enhanced receiver

132kHz (primary) and 115kHz (secondary) in CENELEC C-band and

86kHz (primary) and 75kHz (secondary) in CENELEC A-band

Models 15311R-1000 and 15321R-960 are designed to be compliant with European Directive

2002/95/EC on Restriction of Hazardous Substances (RoHS) in electrical and electronic

equipment.

RoHS Compliance

PL 3120 Power Line Smart Transceiver Pinout Diagram

38 Pin TSSOP

NOTE:

¹The schematic, bill of materials, and layout plots for the Discrete Interface Circuitry are provided in the Development Support Kit (DSK).

PL 3150 Power Line Smart Transceiver Pinout Diagram

64 Pin LQFP

PL 3120 and PL 3150 Power Line Smart Transceiver Pin Descriptions

Pin Name

Type

Pin Functions

PL 3120-E4T10

PL 3150-L10

38 TSSOP Pin No.

64 LQFP Pin No.

XIN

XOUT

RESET

Input

Output

Oscillator connection or external clock input.

Oscillator connection.

Reset pin (active LOW).

Digital I/O (Built-in Pull-up)

Note: The maximum external capacitance is 1000pF.

SERVICE

Digital I/O

(Built-in Conﬁgurable Pull-up)

Service pin (active LOW).

CLKSEL

IO0-IO3

Digital Input

Digital I/O

Tie to V_DD5

2, 3, 4, 5

Large current-sink capacity (20mA). General purpose I/O.

The output of timer/counter 1 may be routed to IO0.

The output of timer/counter 2 may be routed to IO1.

General purpose I/O. The input of timer/counter 1 may be

62, 63, 64, 1

IO4-IO7, IO11 Digital I/O

6, 7, 8, 9, 33

2, 3, 4, 13, 47

(Built-in Conﬁgurable Pull-up) one of IO4-IO7. The input of timer/counter 2 is IO4.

IO8

Digital I/O

General purpose I/O. UART RX. SPI slave clock input.

SPI master clock output.

General purpose I/O. SPI slave data output. SPI master

data input.

General purpose I/O. SPI slave data input. SPI master

data output.

IO9

IO10

D0-D7

R/W

I/O

Output

Bi-directional data bus

Read/write control output for external memory

N/A

12, 11, 10, 9, 8, 7, 6, 5

Pin Name

Type

Pin Functions

PL 3120-E4T10

38 TSSOP Pin No.

N/A

PL 3150-L10

64 LQFP Pin No.

38, 39, 40, 41, 42, 43,

44, 45, 57, 58, 60, 59,

53, 56, 55, 54

18, 32, 51

Output

Enable clock control output for external memory

Memory address output port

A0-A15

N/A

V_DD5

Power

Power input (5V nom). All V_DD5pins must be

connected together externally.

Power input (5V nom). Supplies on-chip analog

circuitry.

13, 27, 37

V_DD5A

Power

GND

Power

Power input (0V, GND). All GND pins must be

connected together externally.

In-circuit test mode control. Driving ICTMode high and

RESET low will place all outputs in high impedance mode

for in-circuit test. Tie to GND for normal operation.

Packet Detect LED driver.

1, 23, 28, 38

28, 33, 52, 61

ICTMode

Digital Input

PKD

BIU

RXIN

Digital Output

Analog Input

Band in Use LED driver.

Receiver input.

INTIN,INTOUT Analog I/O

Integrator input and output.

Receive signal.

Comparator to detect when energy storage power supply

lacks sufficient energy to transmit a packet. Tie to VCORE

if not used.

17, 18

22, 23

RXC

Analog Input

OOGAS

VCORE

TXON

Power

Output of internal 1.8V regulator. Requires 0.1µF

external capacitor.

High when transmitting. Used to drive LED to show

packet transmission.

Digital Output

TXDAC

TXSENSE

TXBIAS

Analog Output

Analog Input

Analog Output

Transmit waveform DAC output.

Transmit ampliﬁer sense feedback.

Transmit ampliﬁer bias generator.

Recommended Operating Conditions

Symbol

V_DD5

Parameter

Min.

4.75

4.60

-40

Typ.

5.00

Max.

5.25

Unit

V_DD5Supply Voltage

V_DD5A

T_A

V_DD5ASupply Voltage

Ambient Temperature

ºC

F_A-band

XIN Frequency for A-band Operation

(6.5536MHz 200ppm)

XIN Frequency for C-band Operation

(10.0000MHz 200ppm)

6.5523

6.5536

6.5549

MHz

F_C-band

9.9980

10.0000

10.0020

MHz

Electrical Characteristics (over recommended operating conditions)

Symbol

V_IL

V_IH

Parameter

Min.

Typ.

Max.

0.8

Unit

Digital Input Low-Level Voltage

Digital Input High-Level Voltage

Digital Output Low-Level Voltage

I_out<20µA

2.0

V_OL

0.1

0.4

0.8

0.4

0.5

IO4-IO11, A0-A14, D0-D7, R/W, E (I_OL= 1.4mA)

IO0-IO3, SERVICE, RESET (I_OL= 20mA)

IO0-IO3, SERVICE, RESET (I_OL= 10mA)

PKD, BIU, TXON (I_OL= 12mA)

Digital Output High-Level Voltage

|I_out|<20µA

V_OH

V_DD5-0.1

V_DD5-0.5

V_DD5-0.4

IO4-IO11, A0-A14, D0-D7, R/W, E (I_OH= -1.4mA)

IO0-IO3, SERVICE, RESET (I_OH= -1.4mA)

PKD, BIU, TXON (I_OH= -12mA)

Digital Input Hysteresis

V_DD5-0.5

V_hys

I_in

175

-10

µA

Input Current (Excluding Pull-ups)²

NOTE:

²IO4-IO7 and SERVICE pins have configurable pull-ups. The RESET pin has a permanent pull-up.

Symbol

I_pu

I_DD

Parameter

Min.

Typ.

Max.

300

Unit

µA

Pull-up Source Current (Vout=0, Output=High-Z)²

PL 3120 Power Line Smart Transceiver V_DD5

Current (not including I/O or internal pull-up current)

PL 3150 Power Line Smart Transceiver V_DD5V_DD5ASupply

Current (not including I/O or internal pull-up current)

_DD5LVI Trip Point

V_DD5ASupply

I_DD

V_LVI

4.0

4.45

External Memory Interface Timing - PL 3150 Power Line Smart Transceiver (over recommended

operating conditions) ^{See Figures 1 to 6 for detailed measurement information}

Parameter

Description

Min.

Max.

Unit

t_cyc

Memory Cycle Time

(Input Clock 10MHz, +/- 200ppm)

199.96

200.04

t_cyc

Memory Cycle Time

(Input Clock 6.5536MHz, +/- 200ppm)

Pulse Width, E High³

305.12

305.79

PW_EH

PW_EL

t_AD

t_AH

t_RD

t_RH

t_WR

t_WH

_cyc/2-5

_cyc/2+5

Pulse Width, E Low

Delay, E High to Address Valid

Address Hold Time After E High

Delay, E High to R/W Valid Read

R/W Hold Time Read After E High

Delay, E High to R/W Valid Write

R/W Hold Time Write After E High

Read Data Setup Time to E High

Data Hold Time Read After E High

Data Hold Time Write After E High⁴

Delay, E Low to Data Valid

t_DSR

t_DHR

t_DHW

t_DDW

140

t_acc

External Read Access Time (t_acc= t_cyc-t_AD-t_DSR) at 10MHz Input Clock

Recommended Operating Conditions for Power Line Smart Transceiver Discrete Interface Circuitry¹

Symbol

V_ARX

V_ATX

T_A

Parameter

Min.

8.5

10.8

-40

Typ.

12.0

Max.

18.0

Unit

V_ASupply Voltage - Receive Mode⁶

V_ASupply Voltage - Transmit Mode⁶

Ambient Temperature

ºC

Electrical Characteristics of Power Line Smart Transceiver Discrete Interface Circuitry¹(over

recommended operating conditions)

Symbol

I_ARX

I_ATX

V_OTX

I_TXLIM

Z_INRX

Parameter

Min.

Typ.

350

120

1.0

500

Max.

500

250

Unit

µA

Vp-p

Ap-p

Ω

V_ASupply Current - Receive Mode

V_ASupply Current - Transmit Mode

Transmit Output Voltage

Transmit Output Current Limit

Input Impedance - Receive Mode

(with recommended RXCOMP inductor)

Output Impedance - Transmit Mode

Power Management - Upper V_AThreshold

Power Management - Lower V_AThreshold

Z_OTX

V_PMU

V_PML

0.9

12.1

7.9

Ω

11.2

7.3

13.0

8.6

NOTES:

³t_cyc= 2/f where f is the input clock (XIN) frequency (10 or 6.5536MHz).

⁴The data hold parameter, t_DHW, is measured to disable levels shown in Figure 6, rather than to the traditional data invalid levels.

⁵This parameter considers only the memory read access time from address to data. This does not allow for chip enable decode. See Neuron 3150 Chip External Memory Interface Engineering Bulletin (005-0013-01D) for memory

decode timing analysis examples.

⁶Minimum value can be 8.5V under certain conditions (refer to Data Book for details).

Maximum value must also satisfy the following: V_ATXAVE< (150-T_AMAX)/(8*D_MAX);

Where: V_ATXAVE= Average V_Asupply voltage while transmitting

T_AMAX= Maximum ambient temperature (ºC)

D_MAX= Maximum transmit duty cycle of the device (expressed as decimal number)

Figure 1. External Memory Interface Timing Diagram

Figure 2. Signal Loading for Timing Speciﬁcations

Figure 3. Test Point Levels for E Pulse Width Measurements

Figure 4. Drive Levels and Test Point Levels for Timing Speciﬁcations Unless Otherwise Speciﬁed

Figure 5. Test Point Levels for High Impedance-to-Drive Time Measurements

Figure 6. Test Point Levels for Driven-to-High Impedance Time Measurements

Absolute Maximum Ratings⁷

Ambient operating temperature

-40 to 85ºC

Storage temperature

-55 to 125ºC

Voltage on V_DD5and V_DD5Apins with respect to GND

Voltage on each pin with respect to GND⁸

Voltage on TXBIAS, TXSENSE, OOGAS pins

Maximum voltage on VCORE pin with respect to GND

-0.3 to 6.0V

-0.3 to (V^DD5+ 0.3V)

-0.3 to 1.89V

1.89V

_DD5,V_DD5A,or GND current per pin

50mA

Input clamp current, I_IK⁸(V_I<0 or V_I>V_DD5

)

10mA

Output clamp current, I_OK(V_I<0 or V_I>V_DD5

)

10mA

Output current per pin⁵

25mA

Power dissipation

250mW

Reﬂow soldering temperature profile

Reﬂow soldering temperature

Refer to Joint Industry Standard document IPC/JEDEC J-STD-020C (July 2004)

235ºC (Models 15310-1000 and 15320-960)

260ºC (Models 15311R-1000 and 15321R-960)

Recommended Pad Layout for PL 3120-E4T10 Power Line Smart Transceiver (38 TSSOP)

NOTES:

⁷Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation under these conditions is not implied.

⁸Applies to all pins except V_DD5, V_DD5A, VCORE, TXBIAS, TXSENSE, and OOGAS.

Recommended Pad Layout for PL 3150-L10 Power Line Smart Transceiver (64 LQFP)

PL 3120-E4T10 Power Line Smart Transceiver Package Diagram

Symbol

mm (prevailing dimensions)

inch

Min.

Nom.

1.00

Max.

Min.

Nom.

0.039

Max.

0.047

0.006

0.041

0.011

0.0079

0.385

1.20

0.15

1.05

0.27

0.20

9.80

0.05

0.80

0.17

0.09

9.60

0.002

0.031

0.0067

0.0035

0.378

θ1

9.70

0.381

6.40 BSC

0.50 BSC

4.40

0.60

0.252 BSC

0.0197 BSC

0.173

4.30

0.45

0°

4.50

0.75

8°

0.169

0.0177

0º

0.177

0.030

8º

0.023

PL 3150-L10 Power Line Smart Transceiver Package Diagram

Symbol

mm (prevailing dimensions)

inch

Min.

0.05

1.35

0.17

0.09

Nom.

1.40

0.22

0.16

Max.

Min.

0.002

0.053

0.007

0.0035

Nom.

0.055

0.009

0.0063

Max.

0.063

0.006

0.057

0.011

0.0079

1.60

0.15

1.45

0.27

0.20

12.00 BSC

10.00 BSC

7.50 BSC

0.50 BSC

12.00 BSC

10.00 BSC

7.50 BSC

0.60

0.472 BSC

0.394 BSC

0.295 BSC

0.0197 BSC

0.472 BSC

0.394 BSC

0.295 BSC

0.0236

0.45

0.75

0.0177

0.0295

1.00 REF

3.5º

0.0394 REF

3.5º

0º

7º

0º

7º

Ordering Information

Power Line Smart

Transceiver IC

Model

RoHS

Maximum

Input

EEPROM

RAM

ROM

External

Memory

Interface

Development

Support Kit (DSK)

Model Number

Number

Compliant

Package

Product Number

Clock

PL 3120-E4T10

PL 3150-L10

15310-1000

15320-960

10MHz

4K Bytes

2K Bytes

24K Bytes

N/A

38 TSSOP

64 LQFP

17010

17020

0.5K Bytes

Yes

17050-20-271,

17050-20-272,

17060-20-272

PL 3120-E4T10

PL 3150-L10

15311R-1000

15321R-960

Yes

10MHz

4K Bytes

2K Bytes

24K Bytes

N/A

38 TSSOP

64 LQFP

17050-20-271,

17050-20-272,

17060-20-272

0.5K Bytes

Yes

Documentation

The PL 3120 / PL 3150 Power Line Smart Transceiver Data Book may be downloaded from Echelon’s web site or ordered through

Echelon’s literature fulﬁllment department.

Document

Echelon Part Number

PL 3120 / PL 3150 Power Line Smart Transceiver Data Book

005-0154-01

Copyright © 2003-2005 Echelon Corporation. Echelon, LON, LONWORKS, LONMARK, LonBuilder, NodeBuilder, LonManager, LonTalk, LonUsers, LonPoint, Digital Home, Neuron, 3120, 3150, LNS, i.LON, LONWORLD, ShortStack,

Panoramix, LonMaker, the Echelon logo, and the LonUsers logo are trademarks of Echelon Corporation registered in the United States and other countries. Pyxos, LonLink, LonResponse, LonSupport, LONews, Open Systems

Alliance, Powered by Echelon, LNS Powered by Echelon, Panoramix Powered by Echelon, LONWORKS Powered by Echelon, Networked Energy Services Powered by Echelon, NES Powered by Echelon, Digital Home Powered

by Echelon, and Thinking Inside the Box are trademarks of Echelon Corporation. Other trademarks belong to their respective holders.

Disclaimer

Neuron Chips, Smart Transceivers, and other OEM Products were not designed for use in equipment or systems which involve danger to human health or safety or a risk of property damage and Echelon assumes no responsibility or

liability for use of the Neuron Chips or Smart Transceivers in such applications. ECHELON MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR IN ANY COMMUNICATION

WITH YOU, AND ECHELON SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

003-0378-01F

w w w . e c h e l o n . c o m

PL3150 [LUNSURE]

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