LY61L10248AML-12_技术文档

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

REVISION HISTORY

Revision

Description

Initial Issued

Issue Date

2012/2/21

Rev. 1.0

Rev. 1.1

July.19. 2012

≧

≦

1.“CE# V_CC- 0.2V” revised as ”CE# 0.2” for TEST

CONDITION of Average Operating Power supply Current

Icc1 on page3

2.Revised ORDERING INFORMATION Page11

1.Revise “TEST CONDITION” for VOH, VOL on page 4

Rev. 1.2

Rev. 1.3

June. 04. 2013

I_OH= -8mA revised as -4mA

I^OL=4mA revised as 8mA

2.Revise VIH(max) & VIL(min) note on page 4

VIH(max) = VCC + 2.0V for pulse width less than 6ns.

VIL(min) = VSS - 2.0V for pulse width less than 6ns.

Revised the address pin sequence of TSOP-II pin configuration on

page 3 in order to be compatible with industry convention. (No

function specifications and applications have been changed and all

the characteristics are kept all the same as Rev 1.2 )

Oct. 30. 2013

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

0

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

FEATURES

GENERAL DESCRIPTION

The LY61L10248A is a 8M-bit high speed CMOS

static random access memory organized as 1,024K

words by 8 bits. It is fabricated using very high

performance, high reliability CMOS technology. Its

standby current is stable within the range of

operating temperature.

Fast access time : 8/10/12ns

Very low power consumption:

Operating current:

90/80/70mA(TYP. 8/10/12ns)

Standby current(Normal version):

3mA(TYP.)

Single 3.3V power supply

All inputs and outputs TTL compatible

Fully static operation

The LY61L10248A operates from a single power

supply of 3.3V and all inputs and outputs are fully

TTL compatible

Tri-state output

Data retention voltage : 1.5V (MIN.)

Green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mmx8mm TFBGA

PRODUCT FAMILY

Power Dissipation

Speed

Product

Family

LY61L10248A

LY61L10248A(I)

LY61L10248A

LY61L10248A(I)

Operating

Temperature

0 ~ 70℃

-40 ~ 85℃

0 ~ 70℃

Vcc Range

Standby(ISB1,TYP.) Operating(Icc1,TYP.)

3.0 ~ 3.6V

2.7 ~ 3.6V

8/10/12ns

10/12ns

3mA

90/80/70mA

80/70mA

-40 ~ 85℃

10/12ns

80/70mA

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

1

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A19

Address Inputs

DQ0 – DQ7 Data Inputs/Outputs

Vcc

Vss

CE#

WE#

OE#

V_CC

V_SS

Chip Enable Inputs

Write Enable Input

Output Enable Input

Power Supply

1024Kx8

MEMORY ARRAY

A0-A19

DECODER

Ground

NC

No Connection

I/O DATA

CIRCUIT

DQ0-DQ7

COLUMN I/O

CE#

WE#

OE#

CONTROL

CIRCUIT

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

2

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

PIN CONFIGURATION

44-pin TSOP(Type II)

48-ball 6mmx8mm TFBGA

NC OE# A0

A1

A4 CE# NC

A6 NC DQ4

A2

NC

A

B

C

D

E

F

NC NC

DQ0 NC

A3

A5

Vss DQ1 A17 A7 DQ5 Vcc

Vcc DQ2 NC A16 DQ6 Vss

DQ3 NC A14 A15 NC DQ7

NC NC A12 A13 WE# NC

G

H

A18 A8

A9 A10 A11 A19

1

2

3

4

5

6

TFBGA

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

3

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

ABSOLUTE MAXIMUN RATINGS*

PARAMETER

SYMBOL

VT1

RATING

-0.5 to 4.6

-0.5 to VCC+0.5

0 to 70(C grade)

-40 to 85(I grade)

-65 to 150

UNIT

V

Voltage on VCC relative to VSS

Voltage on any other pin relative to VSS

VT2

Operating Temperature

TA

℃

Storage Temperature

TSTG

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum

rating conditions for extended period may affect device reliability.

TRUTH TABLE

CE#

H

OE#

X

WE#

X

SUPPLY CURRENT

MODE

I/O OPERATION

High-Z

Standby

I_SB1

I_CC

Output Disable

Read

L

H

High-Z

L

H

D_OUT

Write

L

X

L

D_IN

Note: H = V_IH, L = V_IL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

SYMBOL

TEST CONDITION

-8

MIN.

3.0

2.7

2.2

- 0.3

- 1

TYP. ^*4

3.3

MAX.

3.6

V_CC+0.3

0.8

UNIT

PARAMETER

Supply Voltage

V

V_CC

-10/12

3.3

*1

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Leakage

Current

V_IH

V_IL

-

*2

I_LI

V

_CC≧ V_IN≧ V_SS

_CC≧ V_OUT≧ V_SS,

Output Disabled

1

A

µ

I_LO

- 1

2.4

-

1

-

A

µ

Output High Voltage

Output Low Voltage

V_OHI_OH= -4mA

V

V_OL

Icc

I_OL=8mA

0.4

V

110

100

90

80

140

130

120

110

100

-8

-

mA

CE# = V_IL, I_I/O= 0mA

;f=max

-10

-12

-8

-10

-12

Average Operating

Power supply Current

≦

CE# 0.2, Other pin is

Icc₁

at 0.2V or Vcc-0.2V

I_I/O= 0mA;f=max

CE# ≧Vih

Other pin is at Vil or Vih

CE# ≧V_CC- 0.2V;

70

Standby Power

Supply Current

Standby Power

Supply Current

Isb

-

40

25

mA

I_SB1

3

Other pin is at 0.2V or Vcc-0.2V

Notes:

1. V_IH(max) = V_CC+ 2.0V for pulse width less than 6ns.

2. V_IL(min) = V_SS- 2.0V for pulse width less than 6ns.

3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.

4. Typical values are included for reference only and are not guaranteed or tested.

Typical valued are measured at V_CC= V_CC(TYP.) and T_A= 25℃

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

4

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

CAPACITANCE (TA = 25℃, f = 1.0MHz)

PARAMETER

Input Capacitance

Input/Output Capacitance

SYMBOL

MIN.

-

MAX

8

10

UNIT

pF

C_IN

C_I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

speed

8ns/10/12ns

0.2V to Vcc-0.2V

3ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Reference Levels 1.5V

C_L= 30pF + 1TTL,

I^OH/IOL = -4mA/8mA

Output Load

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

LY61L10248A

-8

LY61L10248A

-10

LY61L10248A

-12

PARAMETER

SYM.

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Chip Enable to Output in Low-Z

Output Enable to Output in Low-Z

Chip Disable to Output in High-Z

Output Disable to Output in High-Z

Output Hold from Address Change

t_RC

t_AA

8

-

8

4.5

-

10

-

10

4.5

-

4

-

12

-

12

5

-

5

-

ns

t_ACE

t_OE

t_CLZ

t_OLZ

t_CHZ

t_OHZ

t_OH

-

*

2

0

-

2

0

-

2

3

0

-

2

-

3

-

(2) WRITE CYCLE

PARAMETER

LY61L10248A

-8

MIN. MAX. MIN. MAX. MIN. MAX.

LY61L10248A

-10

LY61L10248A

-12

SYM.

UNIT

Write Cycle Time

t_WC

t_AW

t_CW

t_AS

t_WP

t_WR

t_DW

8

6.5

0

6.5

0

-

10

8

0

8

-

12

10

0

10

0

-

ns

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

0

Data to Write Time Overlap

5

-

6

-

7

-

ns

Data Hold from End of Write Time

Output Active from End of Write

Write to Output in High-Z

t_DH

t_OW

t_WHZ

0

2

-

3

0

2

-

4

0

2

-

5

ns

*

*These parameters are guaranteed by device characterization, but not production tested.

TIMING WAVEFORMS

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

5

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout

tAA

tOH

Previous Data Valid

Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

tACE

OE#

tOE

tOLZ

tOH

tOHZ

tCHZ

tCLZ

High-Z

Dout

High-Z

Data Valid

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low_.

3.Address must be valid prior to or coincident with CE# = low_,; otherwise t_AAis the limiting parameter.

4.t_CLZ, t_OLZ, t_CHZand t_OHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, t_CHZis less than t_CLZ, t_OHZis less than t_OLZ.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

6

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

tAW

CE#

tCW

tAS

tWP

tWR

WE#

Dout

Din

tWHZ

TOW

High-Z

(4)

tDW

tDH

Data Valid

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tWC

Address

tAW

CE#

tAS

tWR

tCW

tWP

WE#

Dout

Din

tWHZ

High-Z

(4)

tDW

tDH

Data Valid

Notes :

1.WE#, CE# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#.

3.During a WE# controlled write cycle with OE# low, t_WPmust be greater than t_WHZ+ t_DWto allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

6.t_OWand t_WHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

7

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

DATA RETENTION CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

V_CCfor Data Retention

V_DRCE# ≧ V_CC- 0.2V

_CC=1.5V

1.5

-

3.6

V

-

Data Retention Current

I_DR

3

25

mA

CE# ≧V_CC- 0.2V;

Other pin is at 0.2V or Vcc-0.2V

Chip Disable to Data

Retention Time

Recovery Time

See Data Retention

Waveforms (below)

t_CDR

t_R

0

-

ns

t_RC

*

t_{RC = Read Cycle Time}

*

DATA RETENTION WAVEFORM

VDR ≧ 1.5V

Vcc(min.)

Vcc

Vcc(min.)

tCDR

tR

V^IH

CE# ≧ Vcc-0.2V

VIH

CE#

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

8

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

PACKAGE OUTLINE DIMENSION

Ⅱ

44-pin 400mil TSOP-

Package Outline Dimension

DIMENSIONS IN MILLMETERS

DIMENSIONS IN MILS

SYMBOLS

MIN.

-

NOM.

-

MAX.

1.20

0.15

1.05

0.45

0.21

18.618

12.014

10.363

-

MIN.

-

NOM.

-

MAX.

47.2

5.9

41.3

17.7

8.3

733

473

408

-

A

A1

A2

b

0.05

0.95

0.30

0.12

18.212

11.506

9.957

-

0.10

1.00

-

2.0

37.4

11.8

4.7

717

453

392

-

3.9

39.4

-

c

-

D

18.415

11.760

10.160

0.800

0.50

0.805

-

725

463

400

31.5

19.7

31.7

-

E

E1

e

L

0.40

-

0.60

-

15.7

-

23.6

-

ZD

y

-

0.076

6^o

-

3

0^o

3^o

0^o

3^o

6^o

Θ

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

9

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

48-ball 6mm × 8mm TFBGA Package Outline Dimension

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

10

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

ORDERING INFORMATION

Package Type

44Pin(400mil)

Access Time

(Speed)(ns)

Temperature

Packing

Type

Lyontek Item No.

Range(℃)

8

Tray

LY61L10248AML-8

LY61L10248AML-8T

LY61L10248AML-8I

LY61L10248AML-8IT

LY61L10248AML-10

LY61L10248AML-10T

LY61L10248AML-10I

℃

~70

0

TSOP-II

Tape Reel

Tray

℃

-40 ~85

Tape Reel

Tray

10

℃

~70

0

Tape Reel

Tray

℃

-40 ~85

Tape Reel

Tray

LY61L10248AML-10IT

LY61L10248AML-12

LY61L10248AML-12T

LY61L10248AML-12I

LY61L10248AML-12IT

LY61L10248AGL-8

12

℃

~70

0

Tape Reel

Tray

℃

-40 ~85

Tape Reel

Tray

48-ball(6mmx8mm)

TFBGA

8

℃

~70

0

Tape Reel

Tray

LY61L10248AGL-8T

LY61L10248AGL-8I

LY61L10248AGL-8IT

LY61L10248AGL-10

LY61L10248AGL-10T

LY61L10248AGL-10I

LY61L10248AGL-10IT

LY61L10248AGL-12

LY61L10248AGL-12T

LY61L10248AGL-12I

LY61L10248AGL-12IT

℃

-40 ~85

Tape Reel

Tray

10

12

℃

~70

0

Tape Reel

Tray

℃

-40 ~85

Tape Reel

Tray

℃

~70

0

Tape Reel

Tray

℃

-40 ~85

Tape Reel

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

11

®

LY61L10248A

1M X 8 BIT HIGH SPEED CMOS SRAM

Rev. 1.3

THIS PAGE IS LEFT BLANK INTENTIONALLY.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan

TEL: 886-3-6668838

FAX: 886-3-6668836

12


型号：	LY61L10248AML-12
厂家：	Lyontek Inc.
描述：	1M X 8 BIT HIGH SPEED CMOS SRAM 静态存储器
文件：	总13页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LY61L10248AML-12 [LYONTEK]

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