LY61L1288RL-15T [LYONTEK]

128K X 8 BIT HIGH SPEED CMOS SRAM;
LY61L1288RL-15T
型号: LY61L1288RL-15T
厂家: Lyontek Inc.    Lyontek Inc.
描述:

128K X 8 BIT HIGH SPEED CMOS SRAM

静态存储器
文件: 总12页 (文件大小:280K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Rev. 1.2  
Description  
Initial Issue  
Delete Icc1 Spec.  
Added I Grade Spec.  
Issue Date  
Jul.25.2004  
Sep.21.2004  
Apr.20.2009  
Revised Test Condition of ICC/ISB1/IDR  
Revised VTERM to VT1 and VT2  
FEATURES ORDERING INFORMATION  
Lead  
Revised  
&
free and green package available to Green package available  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
ORDERING INFORMATION  
Added packing type in  
Adding PKG type : 32 TSOP-II  
Rev. 1.3  
Jan.5.2010  
PACKAGE OUTLINE DIMENSION  
Revised  
Revised  
Revised  
in page 8  
in page 8  
Rev. 1.4  
Rev. 1.5  
May.7.2010  
Aug.25.2010  
PACKAGE OUTLINE DIMENSION  
ORDERING INFORMATION  
in page 10  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
FEATURES  
GENERAL DESCRIPTION  
The LY61L1288 is a 1,048,576-bit high speed  
CMOS static random access memory organized as  
131,072 words by 8 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
„ Fast access time : 8/10/12/15ns  
„ Low power consumption:  
Operating current : 80/75/70/65mA (TYP.)  
Standby current : 0.6mA (TYP.)  
„ Single 3.3V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
The LY61L1288 is well designed for high speed  
system application. Easy expansion is provided by  
using an active LOW Chip Enable(CE#). The active  
LOW Write Enable(WE#) controls both writing and  
reading of the memory.  
„ Tri-state output  
„ Data retention voltage : 2.0V (MIN.)  
„ Green package available  
„ Package : 32-pin 8mm x 13.4mm STSOP  
32-pin 400 mil TSOP-II  
The LY61L1288 operates from a single power  
supply of 3.3V and all inputs and outputs are fully  
TTL compatible  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
LY61L1288  
LY61L1288  
Operating  
Temperature  
0 ~ 70℃  
Vcc Range  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
3.15 ~ 3.6V  
3.0 ~ 3.6V  
3.15 ~ 3.6V  
3.0 ~ 3.6V  
3.15 ~ 3.6V  
3.0 ~ 3.6V  
8/10ns  
12/15ns  
8/10ns  
0.6mA  
0.6mA  
0.6mA  
0.6mA  
0.6mA  
0.6mA  
80/75mA  
70/65mA  
80/75mA  
70/65mA  
80/75mA  
70/65mA  
0 ~ 70℃  
-20 ~ 80℃  
-20 ~ 80℃  
-40 ~ 85℃  
-40 ~ 85℃  
LY61L1288(E)  
LY61L1288(E)  
LY61L1288(I)  
LY61L1288(I)  
12/15ns  
8/10ns  
12/15ns  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
Vcc  
Vss  
A0 - A16  
DQ0 – DQ7 Data Inputs/Outputs  
128Kx8  
A0-A16  
DECODER  
MEMORY ARRAY  
CE#  
WE#  
OE#  
VCC  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Power Supply  
VSS  
Ground  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
WE#  
OE#  
CONTROL  
CIRCUIT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
PIN CONFIGURATION  
A0  
A1  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A16  
A15  
A14  
A13  
OE#  
DQ7  
DQ6  
Vss  
Vcc  
DQ5  
DQ4  
A12  
A11  
A10  
A9  
A2  
3
A3  
4
CE#  
DQ0  
DQ1  
Vcc  
Vss  
DQ2  
DQ3  
WE#  
A4  
5
6
7
8
LY61L1288  
9
10  
11  
12  
13  
14  
15  
16  
A5  
A6  
A7  
A8  
STSOP  
A0  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A16  
A15  
A14  
A13  
OE#  
DQ7  
DQ6  
VSS  
VCC  
DQ5  
DQ4  
A12  
A11  
A10  
A9  
A1  
A2  
3
A3  
4
CE#  
DQ0  
DQ1  
VCC  
VSS  
DQ2  
DQ3  
WE#  
A4  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
A5  
A6  
A7  
A8  
TSOP-II  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 4.6  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
-0.5 to VCC+0.5  
V
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
Operating Temperature  
TA  
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
OE#  
WE#  
SUPPLY CURRENT  
MODE  
I/O OPERATION  
H
X
X
Standby  
High-Z  
ISB,ISB1  
ICC  
L
L
L
H
L
H
H
L
Output Disable  
Read  
High-Z  
DOUT  
DIN  
ICC  
X
Write  
ICC  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
-8/-10  
MIN.  
3.15  
3.0  
2.0  
- 0.3  
- 1  
TYP. *4  
3.3  
MAX.  
3.6  
3.6  
VCC+0.5  
0.8  
UNIT  
PARAMETER  
Supply Voltage  
V
V
V
V
VCC  
-12/-15  
3.3  
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
V
V
CC VIN VSS  
CC VOUT VSS,  
Output Disabled  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -4mA  
VOL IOL = 8mA  
2.4  
-
-
-
V
V
-
-
-
-
-
-
0.4  
150  
120  
100  
90  
10  
3 *5  
80  
75  
70  
65  
3
-8  
mA  
mA  
mA  
mA  
mA  
Cycle time = Min.  
-10  
-12  
-15  
Average Operating  
Power supply Current  
ICC  
CE# = VIL , II/O = 0mA  
Other pins at VIH or VIL  
ISB  
CE# = VIH, others at VIH or VIL  
CE# VCC - 0.2V,  
Other pins at 0.2V or VCC-0.2V  
Standby Power  
Supply Current  
ISB1  
-
0.6  
mA  
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
5. 1mA for special request  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
CAPACITANCE (TA = 25, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
UNIT  
LY61L1288 LY61L1288 LY61L1288 LY61L1288  
-8 -10 -12 -15  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z tOLZ  
Chip Disable to Output in High-Z tCHZ  
Output Disable to Output in High-Z tOHZ  
Output Hold from Address Change tOH  
tRC  
tAA  
tACE  
tOE  
tCLZ  
8
-
-
-
8
8
4
-
10  
-
-
-
10  
10  
5
-
-
5
5
-
12  
-
-
-
12  
12  
6
-
-
6
6
-
15  
-
-
-
15  
15  
7
-
-
7
7
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
-
-
*
*
*
*
2
0
-
-
3
2
0
-
-
3
3
0
-
-
3
4
0
-
-
3
-
4
4
-
(2) WRITE CYCLE  
PARAMETER  
SYM.  
UNIT  
LY61L1288 LY61L1288 LY61L1288 LY61L1288  
-8 -10 -12 -15  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Write Cycle Time  
tWC  
8
6.5  
6.5  
0
6.5  
0
5
0
1.5  
-
-
-
-
-
-
-
-
-
-
10  
8
8
0
8
0
6
0
2
-
-
-
-
-
-
-
-
-
-
12  
10  
10  
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
15  
12  
12  
0
10  
0
8
0
4
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time tDH  
Output Active from End of Write  
Write to Output in High-Z  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
tOW  
tWHZ  
*
*
5
6
7
8
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tAS  
tWP  
tWR  
WE#  
Dout  
Din  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN.  
TYP.  
MAX.  
UNIT  
VCC for Data Retention  
VDR CE# VCC - 0.2V  
2.0  
-
3.6  
V
VCC = 2.0V  
Data Retention Current  
IDR  
CE# VCC - 0.2V  
others at 0.2V or VCC - 0.2V  
See Data Retention  
Waveforms (below)  
-
0.4  
2
mA  
Chip Disable to Data  
Retention Time  
Recovery Time  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
VDR 2.0V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# Vcc-0.2V  
VIH  
CE#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
PACKAGE OUTLINE DIMENSION  
32 pin 8mm x 13.4mm STSOP Package Outline Dimension  
HD  
c
L
12° (2x)  
12° (2x)  
32  
1
17  
16  
"A"  
y
Seating Plane  
D
12° (2X)  
16  
17  
GAUGE PLANE  
0
SEATING PLANE  
L
12° (2X)  
L1  
"A" DATAIL VIEW  
1
32  
UNIT  
INCH(BASE)  
0.049 (MAX)  
MM(REF)  
1.25 (MAX)  
SYM.  
A
A1  
A2  
b
±
±
0.004 0.002 0.10 0.05  
±
±
0.039 0.002 1.00 0.05  
±
±
0.009 0.002 0.22 0.05  
c
±
±
0.006 0.002 0.155 0.055  
D
±
±
0.465 0.008 11.80 0.20  
E
±
±
0.315 0.008 8.00 0.20  
e
0.020 (TYP) 0.50 (TYP)  
HD  
L
±
±
13.40 0.20.  
±
0.50 0.20  
0.528 0.008  
±
0.02 0.008  
L1  
y
Θ
±
±
0.031 0.005 0.8 0.125  
0.003 (MAX) 0.076 (MAX)  
o
o
o
o
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
32-pin 400mil TSOP-  
Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
ORDERING INFORMATION  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY61L1288  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.5  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  

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