LY69L6416AGL-45SLT [LYONTEK]
SRAM,;型号: | LY69L6416AGL-45SLT |
厂家: | Lyontek Inc. |
描述: | SRAM, 静态存储器 |
文件: | 总14页 (文件大小:528K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
REVISION HISTORY
Revision
Rev. 1.0
Description
Initial Issue
Issue Date
Mar.19.2020
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
FEATURES
GENERAL DESCRIPTION
The LY69L6416A is a 1,048,576-bit low power
CMOS static random access memory organized as
65,536 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
Fast access time : 45/55ns
Low power consumption:
Operating current : 12/10mA (TYP.)
Standby current : 1A (TYP.)
Single 2.7V ~ 3.6V power supply
ECC : 1-bit error correction per byte
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 1.5V (MIN.)
Green package available
Package : 44-pin 400mil TSOP II
48-ball 6mm*8mm TFBGA
The LY69L6416A embeds error-correcting code
(ECC) which can correct single-bit error per byte. It
is well designed for low power application, and
particularly well suited for battery back-up
nonvolatile memory application.
The LY69L6416A operates from a single power
supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible.
PRODUCT FAMILY
Power Dissipation
Speed
Product
Family
LY69L6416A
Operating
Temperature
0 ~ 70℃
V
CC Range
Standby(ISB1,TYP.) Operating(ICC,TYP.)
2.7 ~ 3.6V
2.7 ~ 3.6V
45/55ns
45/55ns
1µA
1µA
12/10mA
12/10mA
-40 ~ 85℃
LY69L6416A(I)
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
A0 - A15
DQ0 – DQ15 Data Inputs/Outputs
CE#
WE#
OE#
LB#
UB#
VCC
Chip Enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
Power Supply
VSS
Ground
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
PIN CONFIGURATION
A4
A3
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A2
3
A7
A1
4
OE#
UB#
LB#
DQ15
DQ14
DQ13
DQ12
Vss
A0
5
CE#
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE#
A15
A14
A13
A12
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Vcc
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
TSOP II
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
-0.5 to 4.6
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
VT2
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
I/O OPERATION
MODE
Standby
CE# OE# WE# LB# UB#
SUPPLY CURRENT
DQ0-DQ7
DQ8-DQ15
H
X
X
X
X
X
X
H
X
H
High – Z
High – Z
High – Z
High – Z
ISB1
L
L
L
L
L
L
L
L
H
H
L
L
L
X
X
X
H
H
H
H
H
L
L
X
L
H
L
L
H
L
X
L
H
L
L
H
L
High – Z
High – Z
DOUT
High – Z
DOUT
DIN
High – Z
DIN
High – Z
High – Z
High – Z
DOUT
DOUT
High – Z
DIN
Output Disable
Read
ICC,ICC1
ICC,ICC1
ICC,ICC1
Write
L
L
L
DIN
Note: H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
2.7
2.2
TYP. *4
3.0
MAX.
3.6
VCC+0.3
0.6
UNIT
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
VCC
V
V
V
*1
VIH
VIL
-
-
*2
- 0.2
Input Leakage Current
ILI
- 1
-
1
A
µ
≧
≧
≧
VSS
VCC
VCC
VIN
Output Leakage
Current
≧
VOUT
VSS,
ILO
- 1
-
1
A
µ
Output Disabled
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = -1mA
IOL = 2mA
2.2
-
2.7
-
-
V
V
0.4
Cycle time = Min.
12
10
20
17
-45
-55
-
-
mA
ICC
≦
CE# 0.2V, II/O = 0mA
mA
Average Operating
Others at 0.2V or VCC-0.2V
Power supply Current
Cycle time = 1 s
µ
ICC1
-
3
5
mA
CE# = 0.2V , II/O = 0mA
Other pins at 0.2V or VCC - 0.2V
SL*5
℃
℃
-
-
-
-
1
1
1
1
3
3
10
15
A
µ
A
µ
25
40
≧
SLI*5
CE# VCC - 0.2V
Standby Power
Supply Current
ISB1
Others at 0.2V or
VCC - 0.2V
SL
SLI
A
µ
A
µ
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25
5. This parameter is measured at VCC = 3.0V
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
tRC
UNIT
LY69L6416A-45
LY69L6416A-55
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
45
-
-
-
55
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
45
45
25
-
55
55
30
-
tACE
tOE
tCLZ
tOLZ
tCHZ
-
-
*
*
*
10
5
-
-
10
-
10
5
-
-
10
-
-
-
15
15
-
45
20
-
20
20
-
55
25
-
tOHZ
tOH
tBA
*
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
tBHZ
tBLZ
*
*
-
10
-
10
(2) WRITE CYCLE
PARAMETER
SYM.
tWC
tAW
tCW
tAS
UNIT
LY69L6416A-45
LY69L6416A-55
MIN.
45
40
40
0
MAX.
MIN.
55
50
50
0
MAX.
Write Cycle Time
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
-
-
tWP
tWR
tDW
tDH
tOW
35
0
-
-
45
0
-
-
20
0
-
-
25
0
-
-
*
5
-
5
-
tWHZ
*
-
35
15
-
-
45
20
-
tBW
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOLZ
tBLZ
tCLZ
tOHZ
tBHZ
tCHZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
WRITE CYCLE 1 (WE# Controlled) (1,2,4,5)
WRITE CYCLE 2 (CE# Controlled) (1,4,5)
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
WRITE CYCLE 3 (LB#,UB# Controlled)
(1,4,5)
Notes :
1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
3.During this period, I/O pins are in the output state, and input signals must not be applied.
4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
VCC - 0.2V
MIN. TYP. MAX. UNIT
VDR
1.5
-
3.6
3
V
≧
CE#
℃
℃
-
-
-
-
1
1
1
1
A
25
40
SL
SLI
µ
µ
µ
µ
VCC = 1.5V
3
5
10
A
A
A
Data Retention Current
IDR
≧
CE#
VCC - 0.2V
Other pins at 0.2V or VCC-0.2V
SL
SLI
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC*
tRC*
= Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
LB#,UB# ≧ Vcc-0.2V
VIH
LB#,UB#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP II Package Outline Dimension
DIMENSIONS IN MILLMETERS
DIMENSIONS IN MILS
SYMBOLS
MIN.
-
NOM.
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.618
12.014
10.363
-
MIN.
NOM.
-
MAX.
A
A1
A2
b
-
47.2
5.9
41.3
17.7
8.3
733
473
408
-
0.05
0.95
0.30
0.12
18.212
11.506
9.957
-
0.10
1.00
-
2.0
37.4
11.8
4.7
717
453
392
-
3.9
39.4
-
c
-
-
D
18.415
11.760
10.160
0.800
0.50
0.805
-
725
463
400
31.5
19.7
31.7
-
E
E1
e
L
0.40
-
0.60
-
15.7
-
23.6
-
ZD
y
-
0o
0.076
6o
-
0o
3
6o
3o
3o
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
ORDERING INFORMATION
Package Type
Access Time
(Speed)(ns)
45
Power Type
Temperature
Packing
Type
Lyontek Item No.
Range(℃)
44-pin(400 mil)
TSOP II
Tray
LY69L6416AML-45SL
Special Ultra
Low Power
℃
℃
~70
0
Tape Reel LY69L6416AML-45SLT
Tray LY69L6416AML-45SLI
Tape Reel LY69L6416AML-45SLIT
Tray LY69L6416AML-55SL
Tape Reel LY69L6416AML-55SLT
Tray LY69L6416AML-55SLI
Tape Reel LY69L6416AML-55SLIT
Tray LY69L6416AGL-45SL
Tape Reel LY69L6416AGL-45SLT
Tray LY69L6416AGL-45SLI
Tape Reel LY69L6416AGL-45SLIT
Tray LY69L6416AGL-55SL
Tape Reel LY69L6416AGL-55SLT
Tray LY69L6416AGL-55SLI
Tape Reel LY69L6416AGL-55SLIT
℃
-40 ~85
℃
55
45
55
Special Ultra
Low Power
℃
℃
~70
0
℃
-40 ~85
℃
48-ball
Special Ultra
Low Power
℃
℃
~70
0
(6mm x 8mm)
TFBGA
℃
-40 ~85
℃
Special Ultra
Low Power
℃
℃
~70
0
℃
-40 ~85
℃
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
LY69L6416A
64K X 16 BIT LOW POWER CMOS SRAM
With Error-Correcting Code (ECC)
Rev. 1.0
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
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