SXT6051 [LevelOne]
Terminator, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208;
| 型号： | SXT6051 |
| 厂家： | 
LEVEL ONE |
| 描述： | Terminator, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总144页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MAY 1998
Revision 1.1
SXT6051
STM-1/0 SDH Overhead Terminator
General Description
Features
The SXT6051 Overhead Terminator implements the
Regenerator Section Termination, Multiplexer Section
Termination and Higher Order Path Termination in STM-0
(51Mb/s) and STM-1 (155mB/s) multiplexers. It provides
micro-controller access for performance monitoring, alarm
detection and configuration for transmit and receive paths.
When used with the SXT6251 (21E1 Mapper), a complete
solution for a 21 E1 or a 63 E1 Multiplexer is created.
• Performs Regenerator Section, Multiplexer Section,
and Higher Order Path Overhead Processing for
STM-1 and STM-0 signals.
• Byte parallel interface for STM-1 or STM-0, with
byte alignment performed internally. Serial NRZ or
B3ZS interface option for STM-0.
• Demultiplexes STM-0/STM-1 signals to Telecom Bus
output with optional pointer processor re-timing.
• Multiplexes Telecom Bus data into STM-0 or STM-1
signals with pointer processing.
The SXT6051 is compliant with the latest releases of ITU-
T G.703 and G.707. It provides all the alarm and control
features to easily implement the multiplexer described in
ITU-T G.783.
• Compatible with 1+1 protected ITU architecture.
• Records all RSOH, MSOH, and HPOH alarms. One
second counters for B1, B2, B3, M1 REI and G1 REI.
• Full J0/J1 trace identifier processing
Applications
• Serial access to STM-1 user-defined, media-depen-
dent and national bytes.
• Dedicated pins for serial access or pass-through fea-
ture for E1, E2, F1, F2, F3, D1-D3 & D4-D12 bytes.
• SDH Terminal Mux/ADM for microwave radio
• ADM fiber ring Mux
• Low power CMOS technology with 3.3V core and 5V
I/O in PQFP-208 package.
• Digital Loop Carrier (NGDLC) Systems
• Digital Cross-Connect System
• IEEE 1149.1 Boundary Scan (JTAG) support.
SXT6051
System Block Diagram
SETS
POH
Serial Accesses
MMSP
Bus
SOH
Serial Accesses
SXT 6051
Transm it
Master
Clock In
OHT
TX
4
TBus Tim ing
AU-3/4 &
VC-3/4
Transm it Processor
STM -0 / STM -1
Transm it Section
Term ination &
Protection Function
(RST, M ST, M SP)
Transm it
Tx Clock out
Telecom
Bus Add
Interface
6.48M/19.44M Clock
Telecom Bus Data
Data
(HPT, M SA(PP))
1
8
or 8 (S TM -0)
(STM -1)
SXT 6251
21 Channel
Mapper
STM -0/1
Line
Interface
Microcontroller Interface (Intel/Motorola selectable)
1
8
or
8 (S TM -0)
(STM -1)
Data
Clock
LOS
Receive
Telecom
Bus
Drop
Interface
AU-3/4 &
VC-3/4
Receive Processor
STM -0 / STM -1
Receive Section
Term ination &
Telecom Bus Data
6.48M/19.44M Clock
Protection Function
(RST, M ST, M SP)
TBus Tim ing
(M SA,HPT&Retim ing)
4
RX
optional retim ing
Clock&tim ing
POH
Serial Accesses
DMSP
Bus
SOH
Serial Accesses
SXT6051 STM-1/0 SDH Overhead Terminator
Table Of Contents
Pin Assignments And Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmit Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reference Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Repeater Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Terminal Mode Configuration (No Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Receive Side Telecom Bus Timing Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Add and Drop Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Receive Side Telecom Bus Timing Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Updating the Transmit AU Pointer Justification Event Counters. . . . . . . . . . . . . . 25
Terminal Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Receive Side Telecom Bus Timing Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Receiver Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Distribution and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Framer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Regenerator Section Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multiplexer Section Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Multiplexer Section Protection (MSP) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pointer Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Higher Order Path Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Re-Timing Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Transmitter Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Higher Order Path Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Transmit Pointer Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Transmit Multiplex Section Protection (MSP Block) . . . . . . . . . . . . . . . . . . . . . . . 35
Multiplexer Section Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Regenerator Section Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock Distribution and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Transmit Frame Parallel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
SXT6051
Transmit Frame Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Receive Re-timing Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Telecom Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multiplexer Telecom Bus Terminal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multiplexer Telecom Bus ADM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Demultiplexer Telecom Bus (Terminal or ADM) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 47
Protection Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Transmitter “Master” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Transmitter “Slave” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Receive”Master” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Receive “Slave” Configuration (1+1 Protection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
OverHead Byte Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
F2 and F3 Digital Channel Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Transmit side access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Receive side access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
E1, E2 and F1 Orderwire Channel Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Receive timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HPOH Bytes Serial Access Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Transmit serial HPOH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Receive Serial HPOH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SOH Overhead Access Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Transmit Side SOH Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Receive Side SOH Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
D1 to D3 Data Communication Channel Functional Timing. . . . . . . . . . . . . . . . . . . . . . 61
Transmit Side Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Receive Side Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
D4 to D12 Data Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Transmit Side Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Receive Side Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
BIP Receive Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Microprocessor Interface & Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Intel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Motorola interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Status Registers Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
C2, K3, K2, K1 and S1 Receive Byte Registers Access . . . . . . . . . . . . . . . . . . . . 83
Counter Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3
SXT6051 STM-1/0 SDH Overhead Terminator
Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
OCR1—Operational Configuration 1 (50H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
OCR2—Operational Configuration 2 (51H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CHIP_ID—Chip ID Number (52H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
BUF_ACNTS—Buffer All Counters (54H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Receive Regenerator Section Termination Registers. . . . . . . . . . . . . . . . . . . . . . . . 92
R_RSTC1—Receive RST Configuration 1 (40H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
R_RSTC2—Receive RST Configuration 2 (47H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LOF_LMN—Loss of Frame L, M, & N Configuration (41–42H) . . . . . . . . . . . . . . . . . . . 93
OOF_ECNT—Out Of Frame Event Counter (44–43H) . . . . . . . . . . . . . . . . . . . . . . . . . 94
B1_ERRCNT—B1 Error Counter (46–45H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Receive Regenerator and Multiplexer Section Termination Registers . . . . . . . . . . . 95
J0_RSTR_C—J0 Expected String Control (0EH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
J0_RSTR_D—J0 Expected String Data (0FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH) . . . . . . . . . . . . . . . . . . 96
CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH) . . . . . . . . . . . . . . . 96
E#_EXCWIN—Number of Errs/Win for Excessively Errored Window (1EH). . . . . . . . . 96
WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H) . . . . . . . . . . . . . . . . . . . 96
CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H) . . . . . . . . . . . . . . 97
E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored Window (18H). . . . 97
B2_BLKCNT—B2 Block Error Counter (11–10H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B2_BIPCNT—B2 BIP Error Counter (14–12H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MR_BLKCNT—MST REI Block Error Counter (0A–09H) . . . . . . . . . . . . . . . . . . . . . . . 98
MR_BIPCNT—MST REI BIP Error Counter (0D–0BH) . . . . . . . . . . . . . . . . . . . . . . . . . 98
R_K1—Received K1 byte (00H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
R_K2—Received K2 Byte (01H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
R_S1—Received S1 byte (02H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
R_NU1_8—Received Nu1_8 byte (03H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
R_NU1_9—Received Nu1_9 byte (04H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
R_NU2_8—Received Nu2_8 byte (05H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
R_NU2__9—Received Nu2_9 byte (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
R_NU9_8—Received Nu9_8 byte (07H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
R_NU9_9—Received Nu9_9 byte (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Receive Multiplexer Section Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . 100
R_MSP_C—Receive MSP Configuration (20H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
R_MSP_OP—Receive MSP Operational (21H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
R_PROTK1—Received K1 byte on Protection Bus from Slave (22H). . . . . . . . . . . . . 101
R_PROTK2—Received K2 byte on Protection Bus from Slave (23H). . . . . . . . . . . . . 101
Receive Multiplexer Section Adaptation Registers . . . . . . . . . . . . . . . . . . . . . . . . . 101
R_MSA_C—Receive MSA Configuration (90H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
R_AU_NCNT—Receive Negative AU Pointer Justification Event Counter (92–91H) . 102
R_AU_PCNT—Receive Positive AU Pointer Justification Event Counter (94–93H) . . 102
Receive HighOrder Path Termination Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4
SXT6051
R_HPT_C1—Receive HPT Configuration 1 Register (80H) . . . . . . . . . . . . . . . . . . . . 103
R_HPT_C2—Receive HPT Configuration 2 Register (81H) . . . . . . . . . . . . . . . . . . . . 104
J1_RSTR_C—J1 Expected String Control Register (8AH) . . . . . . . . . . . . . . . . . . . . . 105
J1_RSTR_D—J1 Expected String Data Register (8BH) . . . . . . . . . . . . . . . . . . . . . . . 105
EXP_C2—Expected C2 byte Register (82H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
R_C2—Received C2 byte Register (83H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
R_K3—Received K3 byte Register (84H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
R_HPT_RDI—Received HPT RDI Bits Register (85H) . . . . . . . . . . . . . . . . . . . . . . . . 106
B3_ECNT—B3 Error Event Counter (87–86H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HPTREI_CNT—HPT REI Counter (89–88H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Transmit Regenerator and Multiplexer Section Termination Registers . . . . . . . . . . 107
T_RMST_OP1—Transmit RMST Operational 1 Register (30H) . . . . . . . . . . . . . . . . . 107
T_RMST_OP2—Transmit RMST Operational 2 Register (1AH) . . . . . . . . . . . . . . . . . 108
T_SC1_SOH—Transmit Source Configuration 1 for SOH bytes Register (60H). . . . . 109
T_SC2_SOH—Transmit Source Configuration 2 for SOH bytes Register (61H). . . . . 110
T_SC3_SOH—Transmit Source Configuration 3 for SOH Bytes Register (62H). . . . . 111
T_SC4_SOH—Transmit Source Configuration 4 for SOH Bytes Register (63H). . . . . 112
J0_TSTR_C—J0 Transmit String Control Register (3AH) . . . . . . . . . . . . . . . . . . . . . . 113
JO_TSTR_D—J0 Transmit String Data Register (3BH) . . . . . . . . . . . . . . . . . . . . . . . 114
MP_TNU1_8—Microprocessor Provided Transmit Nu1_8 Byte (31H) . . . . . . . . . . . . 114
MP_TNU1_9—Microprocessor Provided Transmit Nu1_9 Byte Register (32H) . . . . . 114
MP_TNU2_8—Microprocessor Provided Transmit Nu2_8 Byte (33H) . . . . . . . . . . . . 114
MP_TNU2_9—Microprocessor Provided Transmit Nu2_9 Byte Register (34H) . . . . . 114
MP_TNU9_8—Microprocessor Provided Transmit Nu9_8 Byte (35H) . . . . . . . . . . . . 115
MP_TNU9_9—Microprocessor Provided Transmit Nu9_9 Byte (36H) . . . . . . . . . . . . 115
MP_TK1—Microprocessor Provided Transmit K1 Byte Register (37H). . . . . . . . . . . . 115
MP_TK2—Microprocessor Provided Transmit K2 Byte Register (38H). . . . . . . . . . . . 115
MP_TS1—Microprocessor Provided Transmit S1 Byte Register (39H). . . . . . . . . . . . 115
Transmit Multiplexer Section Adaptation Registers. . . . . . . . . . . . . . . . . . . . . . . . . 116
T_AU_NCNT—Transmit Negative AU Pointer Justification Event Counter (E3–E2H) 116
T_AU_PCNT—Transmit Positive AU Pointer Justification Event Counter (E5–E4H) . 116
Transmit HighOrder Path Termination Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 117
T_SC_HPOH—Transmit Source Configuration for HPOH bytes (70H). . . . . . . . . . . . 117
T_HPT_C—Transmit HPT Configuration (71H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MP_TC2—Microprocessor Provided Transmit C2 Byte (72H). . . . . . . . . . . . . . . . . . . 119
MP_TK3—Microprocessor Provided Transmit K3 Byte (73H) . . . . . . . . . . . . . . . . . . . 119
J1_TSTR_C—J1 Transmit String Control (75H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
J1_TSTR_D—J1 Transmit String Data (76H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Interrupt Source Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
IS_RG—Receive Regenerator Section Interrupt Source (A0H). . . . . . . . . . . . . . . . . . 121
IS_RGMUX—Receive Regenerator and Multiplexor Section Interrupt Source (A1H) . 121
IS_MUX—Receive Multiplexor Section Interrupt Source (A2H). . . . . . . . . . . . . . . . . . 122
IS_PROT—Receive Protection Section Interrupt Source (A3H) . . . . . . . . . . . . . . . . . 122
IS_A_HPT—Receive Adaptation and HPT Interrupt Source (A4H) . . . . . . . . . . . . . . . 123
IS_HPT—Receive HPT Interrupt Source (A5H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5
SXT6051 STM-1/0 SDH Overhead Terminator
IS_RETIME—Receive Retiming Interrupt Source (A6H) . . . . . . . . . . . . . . . . . . . . . . . 124
IS_XMT—Transmit Interrupt Source (E0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
IS_GLOB—Global Interrupt Source (D1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
IE_RG—Receive Regenerator Section Interrupt Enable (B0H). . . . . . . . . . . . . . . . . . 126
IE_RGMUX—Receive Regenerator and Multiplexer Section Interrupt Enable (B1H) . 126
IE_MUX—Receive Multiplexor Section Interrupt Enable (B2H). . . . . . . . . . . . . . . . . . 126
IE_PROT—Receive Protection Section Interrupt Enable (B3H) . . . . . . . . . . . . . . . . . 126
IE_A_HPT—Receive Adaptation and HPT Interrupt Enable (B4H) . . . . . . . . . . . . . . . 126
IE_HPT—Receive HPT Interrupt Enable (B5H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
IE_RETIME—Receive Retiming Interrupt Enable (B6H) . . . . . . . . . . . . . . . . . . . . . . . 126
IE_XMT—Transmit Interrupt Enable (E1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
S_RG—Receive Regenerator Section Status (C0H). . . . . . . . . . . . . . . . . . . . . . . . . . 127
S_RGMUX—Receive Regenerator and Multiplexer Section Status (C1H) . . . . . . . . . 127
S_PROT—Receive Protection Section Status (C3H) . . . . . . . . . . . . . . . . . . . . . . . . . 128
S_A_HPT—Receive Adaptation and HPT Status (C4H) . . . . . . . . . . . . . . . . . . . . . . . 128
S_HPT—Receive HPT Status (C5H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
S_AIS_PROT—Receive AIS & Protection Switch Status (D0H) . . . . . . . . . . . . . . . . . 130
Testability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
IEEE 1149.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Instruction Register and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Summary Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6
SXT6051 Pin Assignments And Signal Description
PIN ASSIGNMENTS AND SIGNAL DESCRIPTION
Figure 1: SXT6051 Pin Assignment
C
C
C
NC
GND_5
MMSPPDATA0
MMSPPDATA1
MMSPPDATA2
MMSPPDATA3
MMSPPDATA4
MMSPPDATA5
MMSPPDATA6
MMSPPDATA7
MMSPPAUEN
1
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
151
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VCC_5
2
OEN
DMSPPDATA0
DMSPPDATA1
DMSPPDATA2
DMSPPDATA3
DMSPPDATA4
DMSPPDATA5
DMSPPDATA6
DMSPPDATA7
GND_5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
MMSPPCKI
MMSPPCKO
MMSPPJOEN
VCC_5
TSOH
DMSPPCKO
DMSPPCKI
DMSPPJOEN
DMSPPAUEN
DMSPPSF
DMSPPSD
VCC_3
TSOHEN
TSOHFR
TROW
GND_3
TOWC
RSOH
TMOW
TDOW
RSOHEN
RSOHFR
VCC_5
TOWBYC
TRD
RROW
TRDC
ROWC
TMD
ROWBYC
RMOW
TMDC
XXXX XXXX
GND_5
TPOH
RDOW
(Date C ode) (Trace Code)
RRD
TPOHCK
TPOHFR
TPOHEN
TPOW1
TPOW2
TPOWC
TPOWBYC
VCC_3
GND_3
VCC_5
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND_5
A7
RRDC
RMD
RMDC
B2OUT
SXT6051Q E
GND_5
RPOH
RPOHCK
RPOHFR
RPOHEN
RPOW1
XXXXXX
RPOW2
RPOWC
(Lot #)
RPOWBYC
B3OUT
DRETFRMI
DRETCLK
SCANEN
JTCK
JTMS
JTRS
A6
JTDI
A5
JTD0
A4
VCC_5
VCC_5
7
SXT6051 STM-1/0 SDH Overhead Terminator
Table 1: Signal Description Nomenclature
Type
Description
I
Standard input signal
Standard output signal
Input and output signal
Supports TTL input levels
O
I/O
TTLin1
HiZ1
High Impedance
1. Out and I/O signals indicate buffer strength. For example, HiZ-4ma indicates a
high-impedance buffer capable of sourcing 4 ma.
Table 2: Signal Description (Sheet 1 of 11)
Pin #
Name
Type
Description
STM-0 Transmit/ Receive Serial Format
159
160
161
206
205
204
DHPOSD
I
Positive B3ZS or NRZ Data Receive. Input for STM-0 data at
51.84 Mbit/s supplied by the STM-0 line interface unit.
TTLin
DHNEGD
DHICLK
MHPOSD
MHNEGD
MICLK
I
Negative B3ZS Data Receive. Input for STM-0 data at 51.84
Mbit/s when B3ZS coding is used.
TTLin
I
Serial Data Clock Input. Receive STM-0 clock at 51.84 MHz
provided by the external STM-0 line interface unit.
TTLin
O
Positive B3ZS or NRZ Data Transmit. Output of STM-0 data
at 51.84 Mbit/s; either NRZ or B3ZS
HiZ-8ma
O
Negative B3ZS Data Transmit. Output of STM-0 data at
51.84 Mbit/s when B3ZS coding is used.
HiZ-8ma
O
Serial Data Clock Output. The serial output clock of the mul-
tiplexer. This signal is to be used with the serial data MHPOSD
and MHNEGD when needed.
HiZ-8ma
STM1/STM-0 Transmit Receive Parallel Format
172, 171, DHBDATA<7:0>
170, 169,
I
Parallel NRZ Data Receive. Parallel input data in STM-1 or
STM-0 mode.
TTLin
168, 167,
166, 165
173
DHBCLK
I
Parallel Data Clock Input. Parallel input data clock at either
TTLin
19.44 MHz for STM-1 or 6.48 MHz for STM-0
203, 202, MHBDATA<7:0>
201, 200,
O
Parallel NRZ Data Transmit. Parallel output data in STM-1
or STM-0 mode.
HiZ-4ma
198, 197,
196, 195
194
MHBCLKO
O
Parallel Data Clock Output. Parallel output data clock at
HiZ-8ma
either 19.44 MHz for STM-1 or 6.48 MHz for STM-0.
8
SXT6051 Pin Assignments And Signal Description
Table 2: Signal Description (Sheet 2 of 11)
Pin #
Name
Type
Description
External References
Internal TX Frame Alignment Output. This signal is syn-
185
186
163
187
MFRMO
O
HiZ-4ma
chronous with the multiplexer frame and is used to synchronize
other transmitters. See Figures 12 and 13.
MFRMI
LOS
I
External TX Frame Alignment Input. An 8 KHz signal used
to align the start of a transmit multiplexer frame. If not needed,
this input is grounded.
TTLin
I
Loss of Signal Input. Input from the Line Interface circuit that
can be used either with a parallel interface or with a serial inter-
face. Active High.
TTLin
MHICLK
I
Multiplexer System Serial Clock. An external STM-0 (51.84
MHz) reference frequency input for the multiplexer and can be
used by the demultiplexer section during Blue Signal /AIS Sig-
nal generation.
TTLin
188
86
MHBCLKI
MMFRMI
I
Multiplexer System Parallel Clock. An external STM-0 (6.48
MHz) or STM-1 (19.44 MHz) reference frequency input for the
multiplexer and can be used by the demultiplexer section dur-
ing Blue Signal /AIS Signal generation.
TTLin
I
External Multiframe Alignment. A 2 KHz input signal (25%
duty cycle) that can be used, in terminal mode only, to reset the
internal H4 byte counter.
TTLin
192
191
113
MMSAJ1EN
MMSAPAYEN
DRETFRMI
O
Test Point For J1 Position on TX framed signal. Provided for
testing purposes.
HiZ-2ma
O
Test point for Payload Enable on TX framed signal. Provided
for testing purposes.
HiZ-2mA
I
Demultiplexer Receive Re-timing Frame. An 8 KHz pulse
synchronous with DRETCLK, used by the receive re-timing
function to synchronize the position of the VC3 or VC4 pay-
load. It is always needed.
TTLin
112
DRETCLK
I
Demultiplexer Receive Re-timing Clock Synchronization. A
parallel clock input at either 6.48 MHz (STM-0) or 19.44 MHz
(STM-1). It is used to generate the clocking for the VC-3 or
VC-4 container on DTBDATA<7:0> when the retiming func-
tion is enabled.
TTLin
Serial Overhead Byte Access
15
16
TSOH
I
Transmit RSOH and MSOH Serial Access. Input for serially
sourced RSOH and MSOH transmit data. The data is clocked
in synchronous to MMSPPCKO at 19.44 MHz for STM-1 and
6.48 MHz for STM-0.
TTLin
TSOHEN
O
Transmit RSOH and MSOH Serial Access Clock Enable.
Used to enable clocking of RSOH and MSOH data at the
TSOH input using MMSPPCKO.
HiZ-4ma
9
SXT6051 STM-1/0 SDH Overhead Terminator
Table 2: Signal Description (Sheet 3 of 11)
Pin #
Name
TSOHFR
Type
Description
17
O
Transmit RSOH and MSOH Serial Access Frame Position.
This is an 8 KHz synchronization pulse indicating the start
(MSB of A1) of the 72 bytes of STM-1 RSOH/MSOH or 24
bytes of STM-0 RSOH/MSOH input at TSOH. It is synchro-
nous with MMSPPCKO.
HiZ-4ma
137
RSOH
O
Receive RSOH and MSOH Serial Access. Serial output of
received RSOH and MSOH data. The data is clocked out syn-
chronous to DMSPPCKO at 19.44 MHz for STM-1 and 6.48
MHz for STM-0.
HiZ-4ma
136
135
RSOHEN
RSOHFR
O
Receive RSOH and MSOH Serial Access Clock Enable.
Used to enable clocking of RSOH and MSOH data at the
RSOH output using DMSPPCKO.
HiZ-4ma
O
Receive RSOH and MSOH Serial Access Frame Position.
This is an 8 KHz synchronization pulse indicating the start
(MSB of A1) of the 72 bytes of STM-1 RSOH/MSOH or 24
bytes of STM-0 RSOH/MSOH output at RSOH. It is synchro-
nous with DMSPPCKO.
HiZ-4ma
28
29
31
30
TPOH
I
Transmit HPOH Serial Access. Input for serially sourced
HPOH transmit data.
TTLin
TPOHCK
TPOHEN
TPOHFR
O
Transmit HPOH Serial Access Clock. Used to clock in the
TPOH data at 19.44 clock for STM-1 or 6.48 MHz for STM-0.
HiZ-4ma
O
Transmit HPOH Serial Access Clock Enable. Used to enable
TPOHCK clocking of TPOH input data.
HiZ-4ma
O
Transmit HPOH Serial Access Frame Position. This is an 8
KHz synchronization pulse indicating the start (MSB of J1) of
the 9 bytes of HPOH input at TPOH. It is synchronous with
TPOHCK.
HiZ-4ma
122
121
119
120
RPOH
O
Receive HPOH Serial Access. Serial output of received
HPOH data.
HiZ-4ma
RPOHCK
RPOHEN
RPOHFR
O
Receive HPOH Serial Access Clock. Used to clock out the
RPOH data at 19.44 clock for STM-1 or 6.48 MHz for STM-0.
HiZ-4ma
O
Receive HPOH Serial Access Clock Enable. Used to enable
RPOHCK clocking of received RPOH data.
HiZ-4ma
O
Receive HPOH Serial Access Frame Position. This is an 8
KHz synchronization pulse indicating the start (MSB of J1) of
the 9 bytes of HPOH input at RPOH. It is synchronous with
RPOHCK.
HiZ-4ma
177
124
B1OUT
B2OUT
O
B1 Error Output (BIP). This pin goes High when an error is
detected by the regenerator section overhead. It is synchronous
to DMSPPCK0.
HiZ-2ma
O
B2 Error Output (BIP) This pin goes High when an error is
detected by the terminal section overhead. It is synchronous to
DMSPPCK0
HiZ-2ma
10
SXT6051 Pin Assignments And Signal Description
Table 2: Signal Description (Sheet 4 of 11)
Pin #
Name
B3OUT
Type
Description
114
O
B3 Error Output (BIP) This pin goes High when an error is
detected by the higher order path overhead. It is synchronous to
RPOHCK.
HiZ-2ma
11
SXT6051 STM-1/0 SDH Overhead Terminator
Table 2: Signal Description (Sheet 5 of 11)
Pin #
Name
Type
Description
Configuration & Alarm Monitoring
181
OOF
O
Out of Frame Indicator. Active High when framer enters in
an out of frame state. Minimum pulse width is 125 us (1
frame).
HiZ-2ma
180
182
183
179
184
176
LOF
SD
O
Loss of Frame Indicator. Active High when the framer enters
a loss of frame state. Minimum pulse width is 125 us (1 frame).
HiZ-2ma
O
Signal Degrade. State of register 21H<bit 1> bit value.
HiZ-2ma
SF
O
Signal Fail. State of register C1H<bit 5> bit value.
HiZ-2ma
AISRX
O
Receive AIS Signal Indicator. Indicates that an AIS has been
detected in the received VC3 or VC4. Active High.
HiZ-2ma
SCRAMSEL
STMMODE
I
Scrambler Disable. This pin should be tied to Low during nor-
mal operation. Active High.
TTLin
I
Mode Select. Low selects STM-0, High selects an STM-1.
TTLin
Orderwire and Data Byte Access Transmit Side
18
19
20
21
22
32
33
34
TROW
I
Transmit RSOH E1 Orderwire. A 64 Kb/s data input for
orderwire byte E1. Data is synchronized with TOWBYC and
clocked by TOWC.
TTLin
TOWC
O
Transmit RSOH and MSOH Orderwire Clock. A reference
clock output at 64 KHz to be used for transmit E1, E2 and F1
byte clocking.
HiZ-2ma
TMOW
TDOW
I
Transmit MSOH E2 Orderwire. A 64 Kb/s data input for
orderwire byte E2. Data is synchronized with TOWBYC and
clocked by TOWC.
TTLin
I
Transmit RSOH F1 Orderwire. A 64 Kb/s data input for
orderwire byte F1. Data is synchronized with TOWBYC and
clocked by TOWC.
TTLin
TOWBYC
TPOW1
TPOW2
TPOWC
O
Transmit RSOH and MSOH Orderwire Synchronization
Signal. An 8 KHz signal used to byte synchronize the transmit-
ted E1, F1 and E2 data streams.
HiZ-2ma
I
Transmit HPOH F2 Orderwire. A 64 Kb/s data input for
orderwire byte F2. Data is synchronized with TPOWBYC and
clocked by TPOWC.
TTLin
I
Transmit HPOH F3 Orderwire. A 64 Kb/s data input for
orderwire byte F3 Data is synchronized with TPOWBYC and
clocked by TPOWC.
TTLin
O
Transmit HPOH Orderwire Clock. A reference clock output
HiZ-2ma
at 64 KHz to be used for F2 and F3 transmit byte clocking.
12
SXT6051 Pin Assignments And Signal Description
Table 2: Signal Description (Sheet 6 of 11)
Pin #
Name
TPOWBYC
Type
Description
35
O
Transmit HPOH Orderwire Synchronization Signal. An 8
KHz signal used to byte synchronize the F2 and F3 transmit
data streams.
HiZ-2ma
23
24
25
26
TRD
I
Transmit RSOH D1-D3 Data. A 192 Kb/s data input for
RSOH D1-D3 data. Data is clocked in by TRDC.
TTLin
TRDC
TMD
TMDC
O
Transmit RSOH D1-D3 Data Clock. A 192 KHz reference
signal used to clock in TRD data.
HiZ-2ma
I
Transmit MSOH D4-D12 Data. A 576 Kb/s data input for
MSOH D4-D12 data. Data is clocked in by TMDC.
TTLin
O
Transmit MSOH D4-D12 Data Clock. A 576 KHz reference
HiZ-2ma
signal used to clock in TMD data.
Orderwire and Data Byte Access Receive Side
133
132
131
130
129
118
117
RROW
O
Receive RSOH E1 Orderwire. A 64 Kb/s data output for
received orderwire byte E1. Data is synchronized with
ROWBYC and clocked by ROWC.
HiZ-2ma
ROWC
O
Receive RSOH and MSOH Orderwire Clock. A reference
clock output at 64 KHz to be used for receive E1, E2 and F1
byte clocking.
HiZ-2ma
ROWBYC
RMOW
RDOW
RPOW1
RPOW2
O
Receive RSOH and MSOH Orderwire Synchronization
Signal. An 8 KHz signal used to byte synchronize the received
E1, E2 and F1data streams.
HiZ-2ma
O
Receive MSOH E2 Orderwire. A 64 Kb/s data output for
received orderwire byte E2. Data is synchronized with
ROWYC and clocked by ROWC.
HiZ-2ma
O
Receive MSOH F1 Orderwire. A 64 Kb/s data output for
received orderwire byte F1. Data is synchronized with ROW-
BYC and clocked by ROWC.
HiZ-2ma
O
Receive HPOH F2 Orderwire. A 64 Kb/s data output for
received orderwire byte F2. Data is synchronized with
RPOWBYC and clocked by RPOWC
HiZ-2ma
O
Receive HPOH F3 Orderwire. A 64 Kb/s data output for
received orderwire byte F3. Data is synchronized with
RPOWBYC and clocked by RPOWC
HiZ-2ma
116
115
RPOWC
O
Receive HPOH Orderwire Clock. A reference clock output at
64 KHz to be used for F2 and F3 receive byte clocking.
HiZ-2ma
RPOWBYC
O
Receive HPOH Orderwire Synchronization Signal. An 8
KHz signal used to byte synchronize the F2 and F3 receive data
streams.
HiZ-2ma
128
127
RRD
O
Receive RSOH D1-D3 Data. A 192 Kb/s data output for
RSOH D1-D3 data. Data is clocked out by RRDC.
HiZ-2ma
RRDC
O
Receive RSOH D1-D3 Data Clock. A 192 KHz reference sig-
HiZ-2ma
nal used to clock out RRD data.
13
SXT6051 STM-1/0 SDH Overhead Terminator
Table 2: Signal Description (Sheet 7 of 11)
Pin #
Name
Type
Description
126
RMD
O
Receive MSOH D4-D12 Data. A 576 Kb/s data output for
HiZ-2ma
MSOH D4-D12 data. Data is clocked out by RMDC.
125
RMDC
O
Receive MSOH D4-D12 Data Clock. A 576 KHz reference
HiZ-2ma
signal used to clock out RMD data.
Telecom Bus Interface
66, 67, 68, MTBDATA<7:0>
69, 70, 71,
72, 73
I
Multiplexer Telecom Bus Data. A byte-wide data input at
19.44 Mbit/s for STM-1 or 6.48 Mbit/s for STM-0. Non-pay-
load byte timeslots (i.e., RSOH, AU pointer, MSOH and
HPOH timeslots) can either have a 0 or 1 inserted.
TTLin
74
75
MTBPAR
MTBCKI
I
Multiplexer Telecom Bus Parity. This is a parity check calcu-
lated on each MTBDATA<7:0> byte. It is an odd parity.
TTLin
I
Multiplexer Telecom Bus Clock Input. A 6.48MHz (STM-0)
or 19.44 MHz (STM-1) input signal used to clock MTB-
DATA<7:0>. It is used when the SXT6051 is configured as an
ADM. In other configurations the pin should be tied to ground.
TTLin
76
77
MTBCKO
O
Multiplexer Telecom Bus Clock Output. A 6.48MHz (STM-
0) or 19.44 MHz (STM-1) output signal. It is used when the
SXT6051 is used in a Terminal configuration.
HiZ-8ma
MTBJ0J1EN
I/O
TTLin-4ma
Multiplexer Telecom Bus Frame Indicator. It indicates the
presence of J0 and J1 bytes on the transmit bus. In an ADM
configuration the pin is set up as an input while in the terminal
mode it is set up as an output.
78
79
80
81
MTBTUGEN1
MTBTUGEN2
MTBTUGEN3
MTBPAYEN
O
Multiplexer Telecom Bus Payload Enable 1. Indicates the
presence of TUG3#1 in the case of STM-1. In the case of STM-
0 this pin is internally pulled High. In ADM it is not used.
HiZ-4ma
O
Multiplexer Telecom Bus Payload Enable 2. Indicates the
presence of TUG3#2 in the case of STM-1. In the case of STM-
0 this pin is internally pulled High. In ADM it is not used.
HiZ-4ma
O
Multiplexer Telecom Bus Payload Enable 3. Indicates the
presence of TUG3#3 in the case of STM-1. In the case of STM-
0 this pin is internally pulled High. In ADM it is not used.
HiZ-4ma
I/O
TTLin-4ma
Multiplexer Telecom Bus Payload Enable Signal. Indicates
the presence of VC-4 in the STM-1 mode or VC-3 in the STM-
0 mode. This signal is used as an output when the SXT6051 is
configured in a Terminal mode and an input in ADM mode.
82
MTBH4EN
TTLin-4ma
Multiplexer Telecom Bus H4 Multi-Frame Indicator. As an
output, it is a 2 KHz signal that indicates the location of the 00
value of H4. The signal goes High after H4 equals “00 “and
Low after H4 equals” 01”. Used as an output when the
SXT6051 is configured in a Terminal Mode. As an input (in
ADM) it is sampled at the J1 byte location.
14
SXT6051 Pin Assignments And Signal Description
Table 2: Signal Description (Sheet 8 of 11)
Pin # Name Type
Description
103, 102, DTBDATA<7:0>
O
Demultiplexer Telecom Bus Data. This is a byte wide data
output at 19.44 Mb/s for STM-1 or 6.48 Mb/s for STM-0. The
RSOH, MSOH and HPOH values are present on the bus when
receive re-timing is disabled (see register 51H).
101, 100,
99, 98, 97,
96
HiZ-4ma
94
93
92
91
DTBPAR
O
Demultiplexer Telecom Bus Parity. A parity check calculated
on each output byte on the Telecom Bus. It is an odd parity.
HiZ-4ma
DTBCK
O
Demultiplexer Telecom Bus Clock Output. A 6.48MHz
(STM-0) or 19.44 MHz (STM-1) output signal.
HiZ-8ma
DTBJ0J1EN
DTBTUGEN1
O
Demultiplexer Telecom Bus Frame Indicator. It indicates the
presence of J0 and J1 bytes on the receive telecom bus.
HiZ-4ma
O
Demultiplexer Telecom Bus Payload Enable 1. Indicates the
presence of TUG3#1 in the case of STM-1. In the case of
STM-0 this pin is internally pulled High.
HiZ-4ma
90
89
DTBTUGEN2
DTBTUGEN3
O
Demultiplexer Telecom Bus Payload Enable 2. Indicates the
presence of TUG3#2 in the case of STM-1. In the case of
STM-0 this pin is internally pulled High.
HiZ-4ma
O
Demultiplexer Telecom Bus Payload Enable 3. Indicates the
presence of TUG3#3 in the case of STM-1. In the case of STM-
0 this pin is internally pulled High.
HiZ-4ma
88
87
DTBPAYEN
DTBH4EN
O
Demultiplexer Telecom Payload Enable. Indicates the pres-
ence of VC-4 in the STM-1 mode or VC-3 in the STM-0 mode.
HiZ-4ma
O
Demultiplexer Multi-Frame Indicator. A 2 KHz signal that
HiZ-4ma
indicates a value of “00” for H4.
Multiplexer/Demultiplexer Protection Interface
9, 8, 7, 6, MMSPPDATA<7:0> I/O
Multiplexer Protection Data Bus. This is byte wide data at
19.44 Mb/s for STM-1 or 6.48 Mb/s for STM-0. It is an output
when the SXT6051 is a Master in a 1-for-1 protection. It is an
input when the SXT6051 is a Slave in a 1- for-1 protection.
5, 4, 3, 2
TTLin-4ma
11
MMSPPCKI
MMSPPCKO
I
Multiplexer Protection Clock. A 6.48MHz (STM-0) or 19.44
MHz (STM-1) input signal used to clock MSPPDATA<7:0>.
This input is only used when the SXT6051 is configured as
Slave in a 1-for-1 protection.
TTLin
12
13
O
Multiplexer Protection Clock A 6.48MHz (STM-0) or 19.44
MHz (STM-1) output signal used to clock MSPPDATA<7:0>.
This output is used when the SXT6051 is configured as Master
in a 1-for-1 protection. This clock is also used to clock the
TSOH serial data stream.
HiZ-8ma
MMSPPJ0EN
I/O
TTLin-4ma
Multiplexer Protection Frame Indicator An 8 KHz pulse
that indicates the presence of the J0 byte on
MMSPPDATA<7:0> bus. The pin is programmed as an input
in a Slave configuration and an output in a Master configura-
tion.
15
SXT6051 STM-1/0 SDH Overhead Terminator
Table 2: Signal Description (Sheet 9 of 11)
Pin #
Name
Type
Description
10
MMSPPAUEN
O
Multiplexer Protection Payload Enable. Indicates the pres-
ence of the VC-4 (in STM-1 mode) or VC-3 (in STM-0 mode)
on the MMSPPDATA<7:0> bus. This pin is only used in a
Master configuration.
HiZ-4ma
147, 148, DMSPPDATA<7:0>
I/O
TTLin-4ma
Demultiplexer Protection Data Bus. This is byte wide data at
19.44 MHz (STM-1) or 6.48 MHz (STM-0). It is an input in a
Master configuration and an output in a Slave configuration.
149, 150,
151, 152,
153, 154
144
DMSPPCKI
DMSPPCKO
I
Demultiplexer Protection clock. A 6.48 MHz (STM-0) or
19.44 MHz (STM-1) signal used to clock DMSPPDATA<7:0>.
This input is only used in a Master configuration.
TTLin
145
O
Demultiplexer Protection clock. A 6.48 MHz (STM-0) or
19.44 MHz (STM-1) signal used to clock DMSPPATA<7:0> in
a Slave configuration or to clock the RSOH serial output data
in a master configuration.
HiZ-8ma
143
142
141
DMSPPJ0EN
DMSPPAUEN
DMSPPSF
I/O
TTLin-4ma
Demultiplexer Protection Frame Indicator. An 8 KHz pulse
that indicates the presence of the J0 byte on the
DMSPPDATA<7:0> bus. The pin is programmed as an output
in a Slave configuration and an input in a Master configuration.
I/O
TTLin-4ma
Demultiplexer Protection Payload Enable. Indicates the
presence of VC-4 (STM-1) or VC-3 (STM-0) data on the
DMSPPDATA<7:0> bus. This pin is programmed as an output
in a Slave configuration and an input in a Master configuration.
I/O
TTLin-2ma
Signal Fail Indicator. This pin is programmed as an input in a
Master configuration and as an output in a Slave configuration.
In the Master configuration the value of this pin is reflected in
register C3H<bit 3>. In the Slave configuration the value of
this pin is the same as C1H<bit 5>.
140
DMSPPSD
I/O
TTLin-2ma
Signal Degrade Indicator. The pin is programmed as an input
in a Master configuration and an output in a Slave configura-
tion. In the Master configuration the value of this pin is
reflected in register C3H<bit 2>. In the Slave configuration the
value of this pin is the same as 21H<bit 1>.
16
SXT6051 Pin Assignments And Signal Description
Table 2: Signal Description (Sheet 10 of 11)
Pin # Name Type
Description
Microprocessor Bus
48, 49, 50, A<7:0>
51, 54, 55,
I
Address Bus. Eight bit address port for register selection dur-
ing read/write accesses.
TTLin
56, 57
39, 40, 41, DATA<7:0>
42, 43, 44,
I/O
TTLin-6ma
Data Bus. Eight bit I/O to read and write data, commands, and
status to and from the device.
45, 46
60
WR
RW
I
Intel Write Strobe. Signal is Low during write accesses.
DATA<7:0> is clocked into the addressed register on the rising
WR edge when CS is Low.
TTLin
Motorola Read/Write Strobe. The SXT6051 drives
DATA<7:0> with the contents of the addressed register when
CS is Low and both RW and E are High. The contents of
DATA<7:0> are clocked into the addressed register on the fall-
ing E edge when both CS and RW are Low.
61
RD
I
Intel Read Strobe. Signal is Low during read accesses. The
SXT6051 drives DATA<7:0> with the contents of the
addressed register when both RD and CS are Low.
TTLin
Motorola Bus Enable Strobe. Signal is High during SXT6051
register accesses.
E
63
58
59
INT
O
Interrupt Request. Signal is Low when there is an unmasked
active interrupt.
Hiz-4ma
CS
AS
I
Chip Select. Active Low chip select that must be asserted dur-
ing all register accesses.
TTLin
I
Address Strobe Enable. Used by chip for systems where the
address and data are multiplexed. Latches A<7:0> on the fall-
ing edge. If address and data are not multiplexed, this pin
should be tied High.
TTLin
64
62
MCUTYPE
RST
I
Motorola/Intel Interface Select. A High indicates a Motorola
and a Low an Intel Microprocessor.
TTLin
I
Chip Master Reset. A Low resets all registers to default con-
TTLin
ditions.
(48 K pull up)
155
OEN
I
Master Chip Output Enable. A Low on this pin causes all
TTLin
I/O and outputs to be High impedance.
(48K pull up)
17
SXT6051 STM-1/0 SDH Overhead Terminator
Table 2: Signal Description (Sheet 11 of 11)
Pin #
Name
Type
Description
JTAG test ports
110
109
JTCK
JTMS
I
JTAG Clock. Clock for all boundary scan circuitry.
Test Mode Select. Determine state of TAP controller.
TTLin
I
TTLin
(48K pull up)
108
JTRS
I
Reset. Active Low.
TTLin
(35K pull
down)
107
106
JTDI
I
Data Input. Input signal used to shift in instructions and data.
TTLin (48K
pull up)
JTDO
O
Data Output. Output signal used to shift out instructions and
2mA
data.
Scan input pins
158
SCANTEST
I
Scan test mode. Active Low.
Scan Enable. Active Low.
TTLin (48 K
pull up)
111
SCANEN
I
TTLin (48K
pull up)
Table 3: Power, Ground, and No Connects
Pin # Name
14, 38, 52, 65, 95, 105, 134, 156, 178, 208 VCC_5
Type
Power Supply
5V Supply.
1, 27, 47, 53, 83, 104, 123, 146, 157, 199
36, 84, 139, 175, 193
GND_5
VCC_3
GND_3
NC
GND 5 Volts. Ground pins for 5 Volt supply.
3 V supply.
37, 85, 138, 174, 190
GND 3 Volts. Ground pins for 3 Volt supply.
Not Connected. Unused. Leave unconnected.
162, 164, 189, 207
18
Functional Description
FUNCTIONAL DESCRIPTION
Thus both transmitters are synchronous in a 1-for-1 hot
stand-by configuration.
Transmit Data Flow
Figure 2 shows the functional blocks of the SXT6051. For
the transmitter (lower half of the diagram), the input inter-
face is the Multiplexer Telecom Bus with byte wide data
MTBDATA <7:0> and timing signals for the parallel clock
MTBCK, the frame indicator MTBJ0J1EN, and the pay-
load active signal MTBPAYEN. The MTBPAR signal pro-
vides parity checking on the MTBDATA <7:0> byte data.
Next, the MST function adds the Multiplexer Section
OverHead (MSOH):
• The K1 and K2 bytes are sourced from the micropro-
cessor programmable register or TSOH input. In the
particular case of K2, an internal process inserts the
MS-RDI bits (K2<2:0>) based on the receive infor-
mation if automatic MS-RDI insertion is enabled by
the microprocessor.
The data flow starts with the Higher Order Path Termina-
tion section which adds the VC-3 or VC-4 path overhead:
• The D4-D12 bytes are sourced from the TMD input or
received D4-D12 bytes in ADM mode. A 576 KHz
reference clock is supplied at TMDC.
• The 16 or 64 byte J1 string is sourced from the micro-
processor programmable registers or TPOH input.
The microprocessor must calculate the CRC7 byte of
the 16 byte J1 transmit string and store it in the first
byte of the registers storing the string.
• S1 is sourced from the microprocessor programmable
register or TSOH input.
• M1 is sourced from the TSOH input or an internal
process that sets M1 based on the receive B2 byte(s)
errors from the receive portion of the SXT6051 if
automatic MS-REI insertion is enabled by the micro-
processor.
• The B3 byte is calculated internally and inserted. The
microprocessor can invert the values of B3 for system
testing purposes.
• The C2 byte is sourced from the microprocessor pro-
grammable register or TPOH input.
• E2 is sourced from the TMOW input or, in ADM
mode, received E2 byte. A 64 KHz reference clock is
supplied at TROWC and an 8 KHz sync pulse at
TROWBYC.
• The G1 byte is sourced from the microprocessor pro-
grammable register, TPOH input, or from the receive
portion of the chip if automatic RDI and REI insertion
is enabled by the microprocessor
• The B2 byte is calculated internally and inserted. The
microprocessor can invert the values of B2 for system
testing purposes.
• The F2 and F3 bytes are two 64 Kbit/s channels
sourced from TPOW1 and TPOW2 or the received F2
and F3 bytes. TPOWC (at 64 KHz) and TPOWBYC
(at 8 KHz) provide the timing references for these
channels.
Finally, the Regenerator Section OverHead (RSOH) is
added by the Regenerator Section Termination (RST).
• The K3 byte is sourced from the microprocessor pro-
grammable register or TPOH input.
• J0 byte is sourced from the microprocessor, TSOH
input or received J0 byte. The microprocessor must
calculate the CRC7 byte of the J0 transmit string and
store it in the first byte of the registers storing the
string.
After the HPOH data has been added, the Higher Order
Connection Supervision block can insert an “unequipped”
payload if configured by the microprocessor to do so (see
registers 70H and 71H).
• The B1 byte is calculated internally and inserted. The
microprocessor can invert the values of B1 for system
testing purposes.
Pointer processing re-timing is performed by the Multi-
plexer Section Adaptation (MSA) section. Positive and
negative pointer movement events are stored in counters
that can be accessed via the microprocessor interface. The
resulting parallel data stream is supplied to the Multiplexer
Section Termination (MST) and to the Multiplexer Section
Protection (MSP) port if it is configured as a protection
master. The data MMSPPDATA <7:0>, along with timing
information, is sent to the redundant (slave) SXT6051.
• E1 is sourced from the TROW input or, in ADM
mode, received E1 byte. A 64 KHz reference clock is
supplied at TROWC and an 8 KHz sync pulse at
TROWBYC.
19
l
SXT6051 STM-1/0 SDH Overhead Terminator
• F1 is sourced from the TMOW input or, in ADM
mode, received F1 byte. A 64 KHz reference clock is
supplied at TROWC and an 8 KHz sync pulse at
TROWBYC.
MHPOSD, or output as B3ZS encoded data on MHPOSD
and MHNEGD. The output selection is configurable via
the microprocessor.
Receive Data Flow
• D1-D3 are sourced from the TRD input or, in ADM
mode, received D1-D3 bytes. A 192 KHz reference
clock is supplied at TRDC.
STM-1 data is input on the parallel DHBDATA<7:0> bus
(see Figure 2). The parallel clock input is DHBCLK.
STM-0 data and clock signals can be entered as parallel
data like STM-1, or as serial NRZ data on DHPOSD, or as
B3ZS encoded data on DHPOSD and DHNEGD. The
B3ZS inputs are decoded and the resulting NRZ data con-
verted to parallel format. The serial clock input is
DHICLK.
Finally, the data is scrambled with a configured scrambler
type and framing bytes A1/A2 are added. The scrambler
has a selectable length of seven to comply with ITU speci-
fications, or 11 or 13 for radio applications. The polyno-
mial functions are 1+X6+X7 for the seven-bit scrambler, 1
+X9+X11
for
the
11-bit
scrambler
and
1+X8+X9+X12+X13 for the 13-bit scrambler. The 13-bit
scrambler is recommended for STM-1 radio applications.
The scrambler selection that can be programmed via the
microprocessor interface.
The parallel data is then fed to the framing and de-scram-
bling block. The framing block synchronizes the timing
generator to the incoming data and provides Out Of Frame
and Loss Of Frame alarm signals. These alarms are based
on frame counts that can be programmed via the micropro-
cessor interface, as the ITU specifications are unclear at
this time.
For STM-1, and optionally STM-0, the data is output on the
byte parallel bus MHBDATA<7:0> synchronous with the
MHBCLKO clock. In STM-0, the output can also be con-
verted from parallel to serial and emitted as NRZ data on
Figure 2:SXT6051 Block Diagram
HPOH
SERIAL
ACCESS SERIAL ACCESS
D4 D12
ACCESS ACCESS
D1 D3
F2 F3
ACCESS
E1 E2 F1
ACCESS
RSOH & M SOH
M SP interface
Com m unication O verhead
MSP Interface
DHPOSD/DHNRZ
DHNEGD
B3ZS
Decoder
RST
MST/MSP
Demultiplexer
Pointer
Interpretation
HOA Higher
order Path
Termination
Regenerator
M ultiplexer
Section
term ination
Retiming
Function
DHICLK
section
DHBDATA<7:0>
DHBCLK
A<7:0>
DATA<7:0>
M icrocontroller Interface
DE M U X Tim ing G enerator
M UX Tim ing G enerator
W R/RW
RD/E
CS
Intel/Motorola Selectable
RST
O verhead R AM
AS
M CUTYPE
M HBDATA<7:0>
M HBCLKO
MSA/MSP
MST
M ultiplexer
section
HCS Higher
order
Connection
Supervision
RST
Regenerator
Section
term ination
HOA Higher
order Path
Termination
M HPOSD/MHNRZ
M HNEGD
M ICLK
B3ZS
Encoder
M HBCLK
M HICLK
Com m unication O verhead
MSP Interface
D4 D12
ACCESS ACCESS
D1 D3
F2 F3
ACCESS
E1 E2 F1
ACCESS
HPOH
SERIAL
ACCESS
RSOH & M SOH
SERIAL ACCESS
M SP
Interface
20
Functional Description
After frame synchronization and de-scrambling, the
Regenerator Section Termination (RST) extracts the
RSOH:
“Master MST output data” or “Slave MSP output data” (see
figure 6 or section on page 31). The choice is completely
under the control of the microprocessor. The microproces-
sor has access to all the Master and Slave data (K1/K2
bytes, error statistics derived from counters and alarm sta-
tus from both chips) necessary for making this decision.
• The expected value of the J0 string is stored via the
microprocessor interface. The received J0 string is
compared with the stored version, and also used to
calculate a CRC-7 byte. Two alarms can be generated:
a J0 (Trace ID) Mismatch alarm and J0 CRC-7 mis-
match alarm.
The MSA block interprets the H1-H3 payload points bytes
to determine the location of the VC-3 or VC-4 payload
structure. Positive and negative pointer movement events
are stored in counters that can be accessed via the micro-
processor interface. The data from the MSA section is then
output to the HPT section in a byte parallel format.
• B1 byte is calculated internally and compared to the
incoming B1 value. The errors are stored into a set of
counters that can be read by the microprocessor inter-
face.
The HPT section extracts the HPOH:
• E1 is provided serially at the RROW output.
• The expected value of the 16 on 64 byte J1 string is
stored internally via the microprocessor interface. The
receive value of J1 is compared with the stored ver-
sion, and is also used to calculate a CRC-7 byte (in 16
byte string configuration). Two alarms are generated:
a J1 Mismatch alarm and J1 CRC-7 mismatch alarm.
• B3 byte is calculated internally and compared to the
incoming B3 value. The errors are stored into a set of
counters that can be read by the microprocessor inter-
face. These errors are also inserted in the transmitted
G1 REI bits (G1<7:4>) if enabled (see registers 70H
and 71H).
• F2 and F3 are provided serially at the ROW1 and
ROW2 outputs. The 64 KHz clock reference for this
output is provided at RPOWC and the 8 KHz sync
pulse at RPOWBYC.
• C2 is provided via both a microprocessor register and
serially at the RPOH output. The C2 value provided
via a microprocessor register is filtered over 3 or 5
frames. The number of filtering frames can be pro-
grammed by the microprocessor.
• G1 is provided serially at the RPOH and is used to
update HPTREI-CNT registers accessible by the
microprocessor.
• K3 is provided via both a microprocessor register and
serially at the RPOH output.
The last block is the re-timing block. This block allows the
alignment of the receive payload with the external signal
DRETFRMI, which supplies the J0 position and an exter-
nal clock DRETCLK. A new value of the pointer based on
the new alignment position is assigned to the payload. This
block typically is bypassed for a multiplexer application. It
is typically only required for external re-timing and align-
ment of multiple TUG-3 payload signals.
• F1 is provided serially at the RMOW output. E1 and
F1 are synchronous and can be accessed using the 64
KHz clock provided at RROWC and the 8 KHz syn-
chronization pulse provided at RROWBYC.
• D1-D3 are provided serially at the RRD output. The
192 KHz clock reference for this output is provided at
RRDC.
Next the Multiplexer Section Termination (MST) extracts
the MSOH:
• K1 and K2 bytes are provided via both a microproces-
sor register and serially at the RSOH output. A filter
based on 3 consecutive identical values of K1 and K2
gates the update of the microprocessor registers.
• D4-D12 bytes are provided serially at the RMD out-
put. The 576 KHz clock reference for this output is
provided at RMDC.
• S1 is provided via both a microprocessor register and
serially at the RSOH output. A filter based on 3 con-
secutive identical values of S1 gates the update of the
microprocessor register.
• M1 is provided serially at the RSOH output and
updates MST REI counters accessible by the micro-
processor.
• E2 is provided serially at the RMOW output. The
64 KHz clock reference for this output is provided at
RROWC and the 8 KHz sync pulse at RROWBYC.
• B2 byte is calculated internally and compared to the
incoming B2 value. The errors are stored into a set of
counters that can be read by the microprocessor inter-
face. These errors are also inserted in the transmitted
M1 byte if enabled (see register 60H).
The Multiplexer Section Protection (MSP) block allows
the selection of data presented to the Master Multiplexer
Section Adaptation (MSA) block to come from either the
21
l
SXT6051 STM-1/0 SDH Overhead Terminator
The output of this block is then sent to the Receive Telecom
Bus DTBDATA<7:0> with the DTBCLK clock and refer-
ence timing DTBJ0J1EN and DTBPAYEN.
• Terminal Mode Protection Slave
• Add And Drop Mode No Protection
• Add And Drop Mode Protection Main
• Add And Drop Mode Protection Slave
Reference Clocks
Note that the following are examples of configurations. For
more details, please refer to AN9801: SXT6051 &
SXT6251 SDH Chipset.
The transmit and the receive side of the SXT6051 operate
independently. In the STM-0 case, the input and output can
either be serial or parallel. In the STM-1 case, the input and
output are parallel only. The following table shows the
clock connections required for STM-1 and STM-0:
Repeater Mode Configuration
All MSOH, HPOH and VC data is passed through inter-
nally and no off chip connection is required between the
transmit and the receive sides. The transmit source of the
RSOH bytes is configurable (see register 60H).
Modes of Operation
Chip Configuration
The SXT6051 can be programmed in seven different con-
figurations in STM-0 or STM-1 mode (see register 50H.)
Figure 3 is an example of an STM-0 repeater using the
serial interface. The timing is recovered by the high-speed
line interface unit and passed to the transmit side via the
SXT6051. In the event of a receiver failure (i.e., a LOS of
Signal Alarm), the SXT6051 will switch to a Blue signal
reference if so configured (see register 40H).
• Repeater mode
• Terminal Mode No Protection
• Terminal Mode Protection Main
Figure 3: STM-0 Repeater Application
D1
B1
B2
E1
F1
to
D3
Error Error
J0
STM-0
B3Zs
Encoded
Serial clock
Serial Data
Los Alarm
STM-0
B3Zs
encoded
Serial clock
Serial Data
SSI 7200
Line
Interface
SSI 7200
Line
Interface
SXT 6051
Regenerator Configuration
51.84 Mbit/s
51.84Mbit/s
Pass Through Programmable
Microprocessor
for Configuration and
Network Management
Interface
51.84 MHz ±20 ppm
Local Reference for Blue
Signal Generation
22
Functional Description
Receive Side Telecom Bus Timing
Source
Table 4: Repeater Clocks
STM-0
MHICLK
In the Terminal mode, when receive re-timing is dis-
abled (see register 51H), the receive side telecom bus
timing is derived from the “recovered” clock.
STM-1
Multiplexer serial
clock input
Not used
Assuming an inactive LOS, the “recovered” clock is
derived from DHICLK in serial mode and DHBCLK
in parallel mode. During an active LOS condition, if
configured (see register 40H), the “recovered” clock is
derived from MHICLK in serial mode and MHBCLKI
in parallel mode (used as “blue” clocks).
(51.84 MHz)
Multiplexer paral-
lel clock input
MHBCLK
(6.48 MHz)
MHBCLK
(19.44 MHz)
Demultiplexer
DHICLK
Not used
serial clock input
(51.84 MHz)
When receive re-timing is enabled, the receive side
telecom bus timing is derived from the re-timing clock
(DRETCLK).
Demultiplexer par- DHBCLK
allel clock input (6.48 MHz)
DHBCLK
(19.44 MHz)
This arrangement of the SXT6051 providing both tim-
ing and data (at the receive telecom bus) is referred to
as co-directional timing.
1. DRETFRMI and DRETCLK are used when a re-timing func-
tion is implemented on the receive side.
Terminal Mode Configuration (No
Protection)
Transmit Side Telecom Bus Timing
Source
The transmit side telecom bus timing is provided by
the SXT6051. It is derived from the local clock refer-
ence (MHICLK in serial mode and MHBCLKI in par-
allel mode). This arrangement of the SXT6051
providing the timing and receiving the data (at the
transmit telecom bus) is referred to as
In Figure 4 the SXT6051 is used with the SXT6251 for the
implementation of an STM-1 terminal multiplexer. The
SXT6251 is a 21 E1 mapper designed to accommodate 21
E1 tributaries in a single chip. The SXT6051 and the
SXT6251 communicate via the Telecom Bus. In an STM-
0 configuration a single 21 E1 multiplexer is required. In an
STM-1 terminal multiplexer, three 21 E1 mappers are
required, sharing the telecom bus to implement a full
63xE1 MUX Telecom bus.
contra-directional timing.
23
l
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 4: STM-1 Terminal Multiplexer
SETS Local Reference 19.44 MHz
Transmit
Reference
21 E1 card TUG#3
SXT 6251
SXT 6051
OHT
TX
Data
Clock
Telecom Bus Timing
Mapper
TX
Transmit Data and Clock E1 <1:21>
Telecom Bus Data
MSOH:
E1 Line
Interface
units
STM-1
LIU
RAP
M1 REI,
K2 RDI
HPOH:
G1 REI,
G1 RDI
TX/RX STM-0
SXT 6251
Mapper
RX
REI, RDI
Alarm Status
Telecom Bus Data
Telecom Bus Timing
SXT 6051
OHT
Data
SAP
Clock
LOS
RX
Receive data and Clock E1 <1:21>
Transmit Data and Clock E1 <1:21>
SXT 6251
Mapper
TX
RAP
E1 Line
Interface
units
STANDARD Terminal
STM-1 configuration
without Receive retiming
SXT 6251
Mapper
RX
REI, RDI
Alarm Status
SAP
Receive data and Clock E1 <1:21>
21 E1 Card Tug#2
SXT 6251
Mapper
TX
Transmit Data and Clock E1 <1:21>
RAP
E1 Line
Interface
units
SXT 6251
Mapper
RX
REI, RDI
Alarm Status
SAP
Receive data and Clock E1 <1:21>
21 E1 Card Tug#1
24
Functional Description
Transmit Side Telecom Bus Timing
Source
Add and Drop Configuration
In Figure the SXT6051 is used with the SXT6251 for the
implementation of an STM-1 Add/Drop multiplexer with
42 E1 access (63 is possible with the addition of another
SXT6251).
In an ADM configuration, the transmit side telecom
bus timing is provided to the SXT6051. Therefore the
timing at the transmit telecom bus is co-directional,
since both timing and data are provided to the
SXT6051.STM-1 ADM Configuration With 42 E1
Access
Receive Side Telecom Bus Timing
Source
Receive side telecom bus timing in the ADM case is
identical to the terminal case.
Figure 5: STM-1 ADM Configuration With 42 E1 Access
Telecom Bus Clock
EAST
WEST
Telecom
Bus Timing
Process TUG3 #1 TU-12's
Passthrough TUG3 #3 Timing
&
Clock
TB Timing
Telecom Bus Data
SXT 6251
SXT 6251
21E1 RX
Telecom Bus Data
21E1 TX
DTBTUG1
DTBTUG3
DTbTugEn
PTTUGA
PTTUGB
PTSOH
GND
VCC
SAP
RAP
SXT 6051
OHT
SXT 6051
OHT
RX
TX
TX
RX
SXT 6251 21 E1 card
Process TUG3 #2 TU-12's
SXT 6251
21E1 RX
SXT 6251
21E1 TX
DTBTUG2
DTbTugEn
PTTUGA
PTTUGB
GND
SAP
RAP
RAP
SAP
PTSOH
Process TUG3 #2 TU-12's
Telecom Bus Data
SXT 6251
21E1 TX
SXT 6251
21E1 RX
Telecom Bus Data
DTbTugEn
DTBTUG2
PTTUGA
GND
SXT 6051
OHT
PTTUGB
SXT 6051
OHT
PTSOH
TX
RX
TX
RX
RAP
SAP
Process TUG3 #1 TU-12's
Passthrough TUG3 #3 Timing
TB Timing
&
Clock
SXT 6251
SXT 6251
21E1 TX
21E1 RX
DTbTugEn
PTTUGA
PTTUGB
PTSOH
DTBTUG1
DTBTUG3
GND
VCC
STM1-ADMCONFIG.VSD- PAGE-1 - 2/4/98
TB Clock
25
l
Functional Description
Updating the Transmit AU Pointer
Transmit Side Telecom Bus Timing
Justification Event Counters
Source
If the re-timing function on the receive side is disabled,
re-clocking by the local clock will occur on the trans-
mit side of the SXT6051. If the receive and local
(which generates the transmit clock) clocks are
slightly different, pointer movements on the transmit
side of the SXT6051 will be generated. These pointer
movements will be reflected in the transmit AU
pointer justification event counters.
On the transmit side, the master SXT6051 feeds the
data received from its transmit telecom bus to both its
MST block and MSP block (which feeds the slave)
using a contra-directional timing arrangement at the
transmit telecom bus interface.
Co-directional timing arrangement is used in both the
receive and transmit directions at the MSP interface.
Receiver Default Operation
If the re-timing function is enabled, re-clocking will
take place on the receive side. Similarly, if the receive
and the local (which generates DRETCLK and trans-
mit clock) clocks are slightly different, pointer move-
ments are again generated on the transmit side of the
SXT6051 and reflected in transmit AU pointer justifi-
cation event counters.
Figure 7 is a block diagram of the receive section of the
SXT6051. The detailed description follows the data flow
from left to right and describes the functionality and con-
figuration of each block. Note that all status change alarms,
counter overflow alarms and receive byte change alarms
mentioned, can cause the INT output pin to be activated if
they are unmasked. Please refer to the register definition
for location of alarms, masks & interrupts.
Terminal Protection Mode
Figure describes the dataflow for a 1-for-1 terminal protec-
tion configuration. The protection mode is an implementa-
tion of the ITU specifications in 1-for-1 configuration.
Serial Interface
The serial interface block accepts an STM-0 input as a
B3ZS encoded or NRZ signal. The B3ZS signal is
input at DHPOSD and DHNEGD and the NRZ signal
is input at DHPOSD. The 51.84 MHz clock is input at
DHICLK.
The SXT6051 can be used either in the main (master) or the
redundant (slave) signal path. The master & slave signal
paths are connected via the MSP bus.
In the master configuration the SXT6051 is connected to
the SXT6251 via the telecom bus in both the transmit and
the receive directions.
A bipolar violation detector has been implemented in
the B3ZS decoder. Detection of a BPV is indicated in
register A0H. Note that the selection (see register 50H)
of the serial interface and B3ZS encoder and decoder
is common to both the transmit and receive sides of the
chip.
In the slave configuration the SXT6051 is indirectly con-
nected to the SXT6251 via the MSP bus in both the trans-
mit and the receive directions.
A filter for the LOS input is provided by the line inter-
face circuit (register 40H). The filtering on the LOS
can be integrated over 128 or 4096 clock cycles. A
LOS status change is indicated in register A0H.
Receive Side Telecom Bus Timing
Source
On the receive side, the master SXT6051 selects the
data from either its receive MST block or its receive
MSP bus (fed by the slave) and presents this selection
using a co-directional timing arrangement at the
receive telecom bus interface. If the MSP (slave) data
is selected (i.e., the protection switch is active, see reg-
ister 21H) the clock provided at the receive telecom
bus will be derived from either DMSPPCKI (demulti-
plexer protection clock) or, if retiming is enabled,
DRETCLK (demultiplexer retiming clock, see register
51H).
Parallel Interface
The parallel interface block accepts a byte format input
at DHBDATA<7:0> in STM-0 or STM-1 mode. No
specific order on the byte is required for the SXT6051
to operate. The parallel clock is input at DHBCLK. As
in the serial case, the selection (see register 50H) of a
parallel interface is common between transmit and
receive sides.
A filter for the LOS input is provided by the line inter-
face circuit. The filtering on the LOS can be integrated
over 16 or 512 clock cycles. An LOS status change is
indicated in register A0H.
26
l
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 6:Terminal Protection Mode Data Flow
SXT 6051 Receive Section Slave channel
Receive
STM -0
Slave
MST/MSP
Multiplexer
section
RST
Regenerator
Section
B3ZS
Decoder
MSP Interface
MSP Interface
Receive
STM -0
Main
SXT 6251
21 E1 Mapper
RST
Regenerator
Section
MST
Multiplexer
section
MSP
Protection
switch
MSA
Pointer
Recovery
HPT
High Order
Path Section
B3ZS
Decoder
Re-
Tim ing
SXT 6051 Receive Section Main Channel
SXT 6051Transm it Section Slave Channel
RST
R egenerator
Section
M ST
M ultiplexer
Section
B3ZS
Encoder
Transmit STM-0 Slave
MSP Interface
MSP Interface
SXT 6251
21 E1 M apper
HPT
H igh O rder
M ST
M ultiplexer
Section
M SA
RST
R egenerator
Section
Transmit STM-0 Main
B3ZS
Encoder
Pointer
Path Section
Processing
SXT 6051 Transmit Section M ain Channel
27
Functional Description
Figure 7:SXT6051 Receiver Blocks
SERIAL
RSOH
&MSOH
RSOH
Interface
MSOH Interface
MSP INTERFACE
DHICLK
DHPOSD
Serial Interface
DHNEGD
LOS
MSP block
Multiplexer section
receiver
Regenerator
Section
receiver
Framer
DHBDATA[7..0]
DHBCLK
Parallel
Interface
Pointer
processing
MHICLK
Clock
AISRX
RPOW1
RPOW2
RPOWC
RPOWBYC
B3OUT
distribution and
references
MHBCLKI
Higher order
path Receiver
ROPHFR
RPOHEN
RPOHCK
RPOH
DTBH4EN
DTBPAYEN
DTBTUGEN
DTBJ0J1EN
DTBCK
1
TO 3
Retiming
Function
DTBPAR
DHBDATA[7..0]
DRETCLK
DRETFRMI
Receive side SXT 6051
_ . - - 2/12/98
REC DETAILS VSD PAGE-1
Figure 8:STM-0 Robust Frame State Machine
Clock Distribution and Reference
Two separate inputs are supplied for Blue clock refer-
ences.
Locked In
Frame
• MHICLK is used for a serial reference clock in
the case of an STM-0 system. The frequency of a
serial reference clock is 51.84 MHz ±20ppm
check
fram es with Valid NDF
3 m ore consecutive
8
consecutive fram es
with Invalid NDF
4
consecutive fram es
with Errored FAS
• MHBCLKI is used for a parallel reference clock
in the case of either an STM-0 or an STM-1 sys-
tem. The frequency of the parallel reference
clock for STM 0 is 6.48 MHz ±20ppm and for
STM-1 19.44MHz ±20ppm
In Frame
Received
Fram e with
Invalid NDF
2
consecutive fram es
with Correct FAS and Valid NDF
Out Of
Frame
An active LOS can have two consequent actions that
can be enabled or disabled (see register 40H):
ROBUST ALG ORITHM FOR STM -0 FRAM ING
• Clock switches from receive clock to reference
clock
• Insert AIS towards the PDH network from the
RST section
Desynchronisation:Transition from Locked In Frame to Out Of Frame
Acquisition
Transition
:Transition from Out Of frame to In Frame State.
:Transition from In Frame State to Locked In Frame.
Framer
OOF Alarm is disabled and receive demultiplexer is re-synchronized, according to the new
frame boundary, when entering in the In Frame State.
The framer operates on either a parallel byte or a serial
bit stream. Two settings are available for the frame
acquisition state machine. One follows ITU-T G.783;
the other is shown in Figure 8.
OOF Alarm is activated and receive demultiplexer keeps its former synchronization when
entering in the Out Of Frame State.
Correct FAS
Errored FAS
Valid NDF
:
:
STM -0 Fram e detected
Errored Fram e (errors on A1A2 bytes)
Valid New Data Flag can be either: descram bled HEX "6" "9" or "F" for NDF or AIS
Invalid receive New Data Flag State other than the valid ones)
: A1A2 bytes = Hex "F628"
:
Invalid NDF
=
(
3
28
l
SXT6051 STM-1/0 SDH Overhead Terminator
Frame Acquisition Algorithm
Loss of Frame (LOF) Detection
The frame acquisition algorithm is done on byte-wide
key word identification. The framer eliminates the
eight phases (bits) of ambiguity and memorizes the
position of the frame word. The framer also identifies
the position of the new data flag (NDF).
Upon detection of an Out Of Frame condition, no con-
secutive action is required by the ITU specifications.
The number of Out of Frame events are counted and
stored in a 13-bit counter accessible via registers 43H
and 44H.
Two consecutive frames with correct frame words and
identical NDF are required to change from an Out Of
Frame State (OOF) to an In Frame State (INF). To
declare an OOF condition, four consecutive frames
with incorrect frame words are required.
The Loss Of Frame state machine can be configured
via the registers 41H and 42H. Three parameters are
programmable (from 1 to 32 frames) in the state
machine:
M is the number of consecutive frames with no Out Of
Frame conditions required to re-enter a normal state. N
is the number of consecutive frames with no Out Of
Frame conditions required to re-enter a normal state
from a Loss Of Frame state. L is the number of non-
consecutive frames with Out Of Frame conditions
required to enter a Loss Of Frame state.
For certain values of the HPOH pointer, “R” bits in the
VC12 container in STM-0 will look like a framing
word after scrambling. This results in false frame syn-
chronization. To eliminate this problem, the acquisi-
tion machine is configurable (see register 40H).
The robust configuration requires five consecutive
frames with identical NDF and two consecutive
frames with the correct frame word for frame acquisi-
tion. This will minimize the probability of incorrect
synchronization. To ensure that an OOF condition is
activated when an incorrect synchronization occurs,
the state machine will desynchronize when eight con-
secutive frames not having identical NDF bits.
Status changes in the OOF & LOF detectors generate
OOF & LOF alarms. Also, output from these detectors
is provided at the OOF & LOF output pins.
Regenerator Section Receiver
This section provides access to all Regenerator Section
Overhead Bytes. All the overhead bytes (27 in STM-1
and 9 in STM-0) are accessible at the RSOH serial out-
put.
Upon frame acquisition, the framer de-scrambles the
signal. The standard scrambler defined by the ITU is
(27–1). Two additional scramblers (211-1) and (213-1)
can be programmed for STM-0 and STM-1 (see regis-
ter 50H). This flexibility allows the optimum choice of
scrambler for a radio application where an equal distri-
bution of 1s and 0s is required.
Figure 10:Overhead Bytes for the STM-1
A1
B1
D1
A1
A1
A2
E1
D2
A2
A2
J0
F1
D3
RSOH
Figure 9:LOF State Machine
AU Pointers
K1
OofSt
= 0
B2
D4
B2
B2
K2
D6
D5
D8
N O R M
D7
D9
MSOH
N
OofSt
=
1
consecutive
frames with
OofSt = 0
D10
S1
D11
D12
E2
M
M1
consecutive
frames with
OofSt = 0
Reserved for National Use
L
Media dependant Byte
Undefined Bytes
non-consecutive
frames with
OofSt = 1
LOF
S T W
OofSt
= 1
29
Functional Description
The Regenerator Section Trace J0
Receive Regenerator Section AIS (RstAIS)
The AIS generated after the Regenerator Section is
labeled RstAis. It can be inserted on the following con-
ditions:
This byte is used to repetitively transmit a Section
Access Identifier so that a section receiver can verify
its continued connection to the intended transmitter.
This byte has been defined in the latest specification of
ITU. To avoid compatibility problems with in-service
equipment, the chip can ignore J0 processing via reg-
ister 51H.
• Loss Of Signal (LOS)
• Loss Of Frame (LOF)
• Trace Identification Mismatch (J0MsMtch)
These conditions can be individually enabled or dis-
abled (see register 40H). A test register that can force
an RstAis for test purposes is also available. RstAis
insertion is indicated in register D0H.
The expected J0 string is configurable (see registers
0EH and 0FH). This J0 string value needs to have the
correct CRC7 bits per G707 specifications. The
receiver calculates the CRC7 of the received J0 string.
In the case of a mismatch between the expected &
received J0 string, a J0 mismatch (J0MsMtch) is indi-
cated in register A1H. In the case of a transmission
error in the J0 string, a J0 string CRC7 error
(J0Crc7Err) is indicated in register A1H and will mask
the J0MsMtch alarm.
National Used Bytes
The four RSOH “National Use” bytes are only acces-
sible in the STM-1 case. These bytes can be read via
registers 03H, 04H, 05H, and 06H or serially at the
RSOH output.
Media Dependent and Undefined Bytes
Bip-8 B1 Byte
The six “Media Dependent” and four “Undefined”
bytes are only accessible in the STM-1 case. These
bytes can only be read via the serial RSOH output.
This byte is used for Regenerator Section error moni-
toring. The error events are counted in a 16 bit counter
accessible via registers 45H and 46H.
Multiplexer Section Receiver
The Multiplexer Section receiver handles the MSOH
overhead bytes. All the overhead bytes (45 in STM-1
and 15 bytes in STM-0) are accessible at the RSOH
serial output.
The B1 counter can be configured as either a bit or a
block counter (see register 47H). Also, the B1OUT
output provides pulse for each calculated B1 bit that is
different from the one received.
E1 Orderwire Byte
This 64 Kbit/s channel is used to provide orderwire
channel for voice communication. The data is serially
accessible via RROW. The 64 KHz clock and the 8
KHz byte synchronization signals are used to receive
both the E2 and F1 bytes and are provided at pins
ROWC and ROWBYC.
B2 Error Byte
This byte is used for Multiplexer Section error moni-
toring. The B2 errors are counted either as block error
in register 10H and 11H (13 bit) or as bit errors in reg-
ister 12H, 13H and 14H (18-bit counter).
An Excessive Error Defect (EED) indication (see reg-
ister A1H) is generated by integrating the B2 errors in
a sliding window. Integration is also used when clear-
ing the EED indication. Six registers allow the config-
uration of EED indication thresholds. They are 18H,
15H, 16H, 17H, 1EH, 1BH, 1CH and 1DH.
F1 Byte
This 64 Kbit/s channel is reserved for the user’s pur-
pose. It can be used as an extra maintenance orderwire
access. The data is serially accessible via RDOW. The
64 KHz clock and the 8 KHz byte synchronization sig-
nals are used to receive both the E1 and E2 bytes and
are provided at pins ROWC and ROWBYC.
These six registers allow configuring the EED thresh-
old from a bit error rate of 10-3 to a bit error rate of 10-
9, even in the case of a non-Gaussian statistical distri-
bution of errors. An active EED indication can be con-
figured to insert an AIS signal (see register 20H).
D1 to D3 Data Channels
This 192 Kbit/s channel is used by the network man-
agement as a data channel. The data is accessible via
pin RRD and the clock is provided by RRDC. Note
that ROWBYC can be used as an 8KHz synchroniza-
tion if required.
30
l
SXT6051 STM-1/0 SDH Overhead Terminator
K1 and K2 Bytes: Automatic Protection
Channel
both the E1 and F1 bytes and are provided at pins
ROWC and ROWBYC.
These bits are assigned for the APS signaling. A
change in K1 byte for three consecutive frames is indi-
cated in register A1H and allows the updating of reg-
ister 00H. A change in K2 byte for three consecutive
frames is indicated in register A1H and allows the
updating of register 01H.
D4 to D12 Bytes: Data Channel
This 576 Kbit/s channel is used as a data channel by
the network management. The data is accessible via
pin RMD and the clock is provided by RMDC.
Receive Multiplexer Section AIS (MS-AIS)
The AIS generated after the multiplexer section is
labeled MstAis. It can be inserted on the following
conditions:
MS-RDI via K2 Byte
The Multiplex Section Remote Defect Indication (MS-
RDI) is used to tell the transmit end that the received
end has detected an incoming section defect or is
receiving MS-AIS. An MS-RDI is detected when the
three received K2<2:0> bits have a value of “110” for
three consecutive frames. MS-RDI detector status
changes are indicated in register A1H.
• MS-AIS detection in K2
• EED detection
The AIS insertion can disabled or forced via register
20H. The EED dependency can be disabled via regis-
ter 20H (ITU specification). MstAis insertion is indi-
cated in register D0H.
MS-AIS via K2 Byte
The Multiplex Section AIS is detected when the three
received K2<2:0> bits have a value of “111” for three
consecutive frames. MS-AIS detector status changes
are indicated in register A1H.
Multiplexer Section Protection (MSP)
Block
Master 1-for-1 Protection Configuration
The MSP block receives the data coming from the
MST block and from the slave receiver via the DMSP-
PDATA<7:0> inputs (MSP bus). K1 and K2 from the
MSP bus are de-multiplexed and accessible in regis-
ters 22H and 23H. The Signal Degrade (SD) and the
Signal Fail (SF) indications from the slave are input to
the Master at DMSPPSD & DMSPPSF respectively
and are accessible in register C3H.
MS-REI via M1 Byte
This byte is allocated for the Remote Error Indication.
Remote BIP errors are accumulated in a 13-bit
counter, accessible via registers 0AH and 09H.
Remote block errors are accumulated in an 18-bit
counter, accessible via registers 0DH, 0CH and 0BH.
S1 Byte: Synchronization Status
S1<3:0> bits are allocated for Synchronization Status
Messages. A change in S1 byte for three consecutive
frames is indicated in register A2H and allows the
updating of register 02H.
Changes in register 22H, 23H, DMSPPSD or
DMSPPSF are indicated in register A3H.
Having access to the K1 and K2, SD and SF informa-
tion for both the master and the slave SXT6051, the
microprocessor can select the appropriate working
channel. The selection is done by setting the protection
switch via register 21H. The effective switch position
is accessible on register D0H.
National Used Bytes
The “National Use” bytes are only accessible in the
STM-1 case. There are two MSOH “National Use”
bytes. These bytes can be read via registers 07H and
08H.
Undefined Bytes
K1/K2 filtering and SF detection are done on chip. The
SD detection is done by the microprocessor using a
user defined criteria.
The “Undefined Bytes” are only accessible in the
STM-1 case. There are 26 bytes only accessible via the
RSOH serial output.
Slave 1-for-1 Protection Configuration
This block is just an interface between the data
received from the MST block and the MSP interface
with the Master. All switching is done in the master-
configured SXT6051.
E2 Byte: Orderwire Channel
This 64 Kbit/s channel is used to provide orderwire
channel for voice communication. The data is accessi-
ble serially via RMOW. The 64 KHz clock and the 8
KHz byte synchronization signals are used to receive
31
SXT6051 STM-1/0 SDH Overhead Terminator
In the case of a mismatch between the expected and
received J1 string, a J1MsMtch is indicated in register
A5H. In the case of a transmission error in the J1
string, a J1Crc7Err is indicated (16 byte case only) in
register A5H and will mask the J1MsMtch indication.
Pointer Recovery
Pointer Recovery Block
The pointer recovery block interprets the value of the
incoming pointer associated with either a VC-3 (STM-
0) or a VC-4 (STM-1) payload. The AU pointers
include two SS undefined bits. These bits can be either
ignored or recovered in the receive pointer processor
(see register 90H). The monitoring function of the
receive pointer processor includes the following
counters:
B3 Byte
This byte is used for Higher Order Path error monitor-
ing. The error events are counted in a 16 bit counter
accessible via registers 86H and 87H.
The B3 counter can be used either as a bit or a block
counter configurable via register 80H. Also, the
B3OUT output provides a pulse for each calculated B3
bit that is different from the received one.
• An 11-bit Positive Justification Counter accessi-
ble via register 91H and 92H
• An 11-bit Negative Justification Counter accessi-
ble via register 93H and 94H
C2 Byte
This block indicates the following conditions via reg-
ister A4H: an AU-AIS (all ones in the pointer), Loss of
Pointer (LOP) or New Data Flag (NDF).
This byte indicates the composition of the VC-3 or the
VC-4 payload. A change in the C2 byte for three or
five (configurable via register 80H) consecutive
frames is indicated in register A4H and allows the
updating of register 83H.
The LOP detection follows the ITU G 783 recommen-
dation using eight consecutive frames.
An “expected” value of C2 can be programmed in reg-
ister 82H. If the received C2 value is not equal to the
expected value and is not zero or one, this is indicated
in register A5H via the HptSlm (HPT Signal Label
Mismatch).
Receive Adaptation Section AIS (DmsaAIS)
The AIS generated after the Pointer recovery section is
labeled DmsaAis. It can be inserted on the following
conditions:
• AU-AIS detection (all ones pointer for three con-
secutive frames)
VC-AIS is defined as all ones in C2 (new G783 spec-
ifications). Five consecutive frames are required for
the VC-AIS detection which is indicated in register
A4H.
• LOP detection
The AIS can be disabled or forced via register 90H.
DmsaAis insertion is indicated in register D0H.
Unequipped Detection
To generate an “unequipped” indication, a set of four
simultaneous events need to be detected (see register
81H):
Higher Order Path Receiver
The Higher Order Path Receiver processes the over-
head bytes associated with the Higher Order Path
Overhead. All the Path Overhead bytes are accessible
at the RPOH output.
• C2 equal to all zero
• J1 equal to zero
• N1 equal to all zero
• No B3 errors
J1 Byte Path Trace
This byte is used to repetitively transmit a Path Access
Identifier so that a path receiver can verify its contin-
ued connection to the intended transmitter. The length
of the “expected” J1 string can be programmed to
either 64 bytes (non-specified) or 16 bytes with CRC7
(see register 80H). The 16 byte “expected” J1 string
value needs to have the correct CRC7 bits per G707
specifications. The receiver calculates the CRC7 of the
received J0 string.
The unequipped detector requires 5 frames before it is
indicated in register A5H.
G1 Byte
This byte conveys the path status and performance
back to a VC-3 or VC-4 trail termination source as
detected by a trail termination sink.
G1<7:4> bits act as a Remote Error Indication (REI).
They report the number of B3 errors detected at the
32
SXT6051 STM-1/0 SDH Overhead Terminator
remote end. These REI errors are accumulated in the
REI counter registers 88H and 89H. The REI counter
can be selected as a bit counter or as a block counter
via register 80H.
Receive Higher Order path AIS (HptAIS)
The AIS generated after the HPOH receiver is labeled
HptAis. It can be inserted on the following conditions:
• SLM (C2 byte mismatches)
• TIM (J1 string mismatches)
G1<3:1> bits act as a Remote Detection Indication
(RDI). They, along with G1<0> (“spare” bit), are
accessible via register 85H. The contents of this regis-
ter is filtered over 3 or 5 frames configurable via reg-
ister 80H. An update to register 80H is indicated in
register A5H.
• Unequipped detection
The AIS can be disabled or forced via register 80H.
Re-Timing Function
The re-timing function block is used when the system
needs to synchronize the DTBDATA<7:0> output
with a local clock input. Re-timing can be disabled via
register 51H.
An RDI is reported to the far-end upon detection of an
SLM (C2 Mismatch) or an “unequipped” alarm. The
dependency of RDI on either of these conditions is
configurable via 81H. This will ensure compatibility
of the new equipment with an installed equipment
base. (See Table 5).
Two external signals are required to align the payload:
• DRETFRI, an 8 KHz input signal indicating the
position of the J0 byte. This input is always
needed.
K3 Byte
This byte is allocated for the VC-3 and VC-4 Auto-
matic Protection Switching (APS). A change in K3
byte for three consecutive frames is indicated in regis-
ter A4H and allows the updating of register 84H.
• DRETCLK, a 19.44 MHz input signal for a
STM-1 or a 6.48 MHz input signal for STM-0.
This is the “local” clock.
The DRETFRMI is generated externally by DRET-
CLK. The re-timing function recalculates the new
pointer and inserts the new value to the payload VC-3
and VC-4.
N1 Byte
There is no internal processing for the tandem connec-
tion byte. This is because in an ADM, the virtual con-
tainer VC-3 or VC-4 is de-multiplexed to VC12 to
extract and insert the VC-12 traffic. A new B3 needs
to be generated and the tandem connection is broken.
After the re-timing block, the signal is sent to the Tele-
com Bus. The Telecom Bus is described in the Timing
Specification part of this document.
N1 is accessible at the RPOH output and can be used
in the detection of an “unequipped” VC (see register
81H).
Note that when the receive re-timing function is
enabled, the AU pointer and the A1/A2 frame word are
still present on the Telecom Bus.
F2 and F3 Bytes
These two 64 Kbit/s channels are reserved for the user.
They can be used as an extra maintenance orderwire
access. The data is serially accessible via the RPOW1
pin for F2 and RPOW2 for F3. The 64 KHz clock and
8KHz synchronization are provided on pins RPOWC
and RPOWBYC. In an ADM configuration with no
receive timing, these bytes can be passed through to
the transmit side.
Transmitter Default Operation
Higher Order Path Transmitter
The HPT transmitter receives its input signal from the
MTBDATA<7:0> Telecom Bus Interface input. It
inserts the Higher Order Path Overhead and synchro-
nizes the VC-3 or the VC-4. The Telecom Bus inter-
face is configured via registers 50H and 71H.
H4 Processing and Multi-Frame Recovery
The multi-frame recovery state machine requires two
consecutive frames with the correct H4 adjacent pat-
tern to synchronize. The Loss of Multiframe (LOM),
indicated in register A5H, is declared after two multi-
frames. The LOM indication forces the DTBH4EN
output on the Telecom Bus Low.
All HPOH bytes can be sourced from the serial TPOH
input, received bytes (ADM mode only), microproces-
sor registers or internal processing. An AIS signal can
be forced on the incoming payload data via register
71H. The parity on the Telecom bus is checked (three
parity errors per frame) and indicated in register E0H.
33
Functional Description
J1 byte: Path Trace Identifier
• The incoming byte from the Telecom bus input
(ADM mode only)
This byte is used to transmit a repetitive Path Trace
Identifier so that a path receiver can verify its contin-
ued connection to the intended transmitter. The length
of the “transmit” J1 string can be programmed to either
64 bytes (non-specified) or 16 bytes with CRC7 via
register 71H. The 16 byte “expected” J1 string value
needs to have the correct CRC7 bits per G707 specifi-
cations. If the higher order VC is configured
unequipped (see register 71H), then J1 byte can be
automatically set to all 0s (see register 70H). If the VC
is not configured as unequipped, J1 can be provided by
one of three sources configured in register 70H:
• The serial TPOH interface (TPOH input pin)
• An internal RAM (up to 64 bytes)
The RAM is accessed via registers 75H and 76H. Dur-
ing a RAM access the default J1 value transmitted
“01H.” Note that a complete 16-byte string with CRC7
is required by the ITU for proper operation.
Figure 11:Transmit Detail Block Diagram
MSP
Interface
MSOH
Interface
SERIAL
TPOH
TPOH
Interface
SERIAL
RSOH
&MSOH
RSOH
Interface
M HNEGD
M HPOSD
M ICLK
Serial
Interface
M TBH4EN
M TBPAYEN
M TBJ0J1EN
M TBTUGEN
1 TO 3
Telecom
Bus
Interface
Higher order
Path
Transmitter
Pointer
Processing
Multiplexer
section
Transmitter
Regenerator
Section
Transmitter
M TBCKI
M TBCKO
M TBPAR
M FRMO
M FRMI
MSP Block
M TBDATA<7:0>
Parallel
M HBDATA<7:0>
M HBCLKO
Interface
M HBCLKI
M HICLK
Clock
Distribution and
References
B3 Byte
• Transmit Telecom bus (In ADM mode)
• The serial POH interface (TPOH input pin)
The B3 byte source is specified by register 70H and
can come from:
• An internal register (register 72H) programmed
by the microprocessor
• Transmit Telecom bus (In ADM mode)
• By calculation on the previous frame
G1 byte: Remote defects HP-REI & HP-RDI
For testing purposes, it is possible to invert the B3
value (see register 71H). The B3 value can be inverted
for a single frame (8 errors) or for an indefinite dura-
tion.
The G1 source is specified by the register 70H:
• Transmit Telecom bus (In ADM mode)
• The serial POH interface (TPOH input pin)
• Internal Processing (see register 71H)
C2 Byte: Path Label
If the higher order VC is configured unequipped (see
register 71H), then the C2 byte is automatically set to
0.
In the case of Internal Processing the REI bits can be
either provided by the B3 error value on the receiver or
be disabled (set to “0000”).
Also, the RDI bits can be supplied either by the
receiver (See Table 5), or the contents of register 74H
If not, the C2 source is specified by the register 70H
and can come from:
34
l
SXT6051 STM-1/0 SDH Overhead Terminator
(in which case the G1 spare bit is also sourced from
74H).
K3 Byte: APS
The K3 source is specified by the register 70H:
• The incoming byte from the Telecom bus input
(only in ADM mode).
Table 5: G1x RDI Bit Coding
• The serial POH interface (TPOH input pin)
• An internal register (address 73H)
G1<3:1>
RDI bits
coding
Triggered
Meaning
Priority
by
N1 Byte: for Tandem Connection Support
The N1 source is specified by the register 70H and can
come from:
000
101
100
110
No Remote
Defect
No Remote
Defect
0
1
2
3
• The incoming byte from the Telecom bus input
(only in ADM mode).
Remote
Defect
AU-AIS,
LOP
• The serial POH interface (TPOH input pin)
Remote
Defect
PLM
There is no internal processing for N1 and tandem con-
nection monitoring. But the monitoring can be done by
configuring the SXT6051 in ADM mode (the POH
bytes are present on the Telecom bus input and can be
passed-through), and by using an external FPGA to
read and write N1 and B3 bytes on the transmit Tele-
com bus.
Remote
Defect
TIM, UNEQ
F2 Byte: Order Wire Channel
The F2 source is specified by the register 70H and can
come from:
Transmit Pointer Processing Function
• The incoming byte from the Telecom bus input
(only in ADM mode).
Terminal Mode
• The 64 kbit/s serial TPOW1 input.
In this configuration, the reference frequency is sup-
plied by the SXT6051 to the Telecom bus. The
inserted pointer value is fixed 6800H.
F3 Byte: Order Wire Channel
The F3 source is specified by the register 70H and can
come from:
ADM Mode
The transmit frequency of the SXT6051 and the Tele-
com bus frequency can be different. This configura-
tion allows the pointer processing block to calculate
the value of the pointer while the data is fed through a
FIFO. An overflow of this FIFO is indicated in register
E0H.
• The incoming byte from the Telecom bus input
(only in ADM mode).
• The 64 kbit/s serial TPOW2 input.
H4 Byte: Multiframe Indicator
The H4 source is specified by the register 70H and can
come from:
The pointer processor is able to handle up to 150 ppm
of total offset between the transmit clock and the Tele-
com Bus clock exceeding the ITU specifications. No
NDF is generated on the transmit side.
• The incoming byte from the Telecom bus input
(only in ADM mode).
• Internal hardware processing. In this case, an
internal counter that can be either free running or
synchronized by the MMFRMI input in terminal
mode, is used to update H4<1:0> with values 0
through 3. In the ADM mode, MTBH4EN and
MTBJ0J1EN on the Telecom Bus synchronizes
H4. In either case, H4<7:2> are set to 1.
Pointer justification events are recorded by two 11-bit
counters (one for positive, the other one for negative)
in registers E2H, E3H, E4H and E5H. Overflows are
indicated in register E0H.
Note: The transmit frame can still be aligned by an
8KHz reference on MFRMI.
35
Functional Description
AU-AIS Insertion
Note that in case of a regenerator, all the received
MSOH bytes are passed through unchanged.
For both Terminal and ADM modes, it is possible to
force AU-AIS (“all one” into AU-3 or AU-4) via reg-
ister 30H.
B2 Error Byte(s):
The B2 (BIP-8 in STM-0 mode, BIP-24 in STM-1)
byte source is specified by register 70H and can come
from:
Test Points
Two output pins test points are available:
• MMSAJ1EN: This pulse (active High: pulse
duration is 51 ns (STM-1) or 154 ns (STM-0)
indicates J1 byte presence on the TB.
• Transmit Telecom bus (In ADM mode)
• By calculation on the previous frame
For testing purposes, it is possible to invert B2 value
(via register 71H). The B2 value can be inverted for a
single frame (8 errors) or for an indefinite duration.
• MMSAPAYEN: A High indicates the position of
VC-3 (STM-0) or VC-4 (STM-1) bytes. A Low
indicates the SOH + AU Pointer bytes presence
on the TB.
K1 and K2 Automatic Protection Channel
Bytes & MS-RDI:
These bytes are assigned for APS signaling and the
transmission of a Multiplex Section Remote Defect
Indication.
Transmit Multiplex Section Protection
(MSP Block)
This block is used in a 1-for-1 configuration (ADM or
Terminal). Two SXT6051 chips in parallel can trans-
mit the same AU data. In a non-protected configura-
tion, the data is simply passed to the transmit MST.
The K1 source is specified by the register 61H and can
come from:
• The serial RSOH and MSOH interface (TSOH
input pin)
In a 1-for-1 protection, one SXT6051 will be config-
ured as Master (Main) and the other one as Slave
(Redundant).
• An internal register (address 37H) programmed
by the microprocessor
The Master transmitter data flow follows the unpro-
tected mode flow and the SOH overhead will be added
in the Multiplexer Section Block.
The K2 source is specified by the register 61H:
• The serial RSOH and MSOH interface (TSOH
input pin)
In the Slave transmitter, the Higher Order Path Trans-
mitter and Pointer Processing block are not used. The
data and timing reference are input from the Master
transmitter to the Slave via the MSP bus. The Slave
Multiplexer and Regenerator Section Transmitter
blocks process these incoming AU data, clock and tim-
ing references.
• Internal hardware process. In this case the RDI
bits can be provided by RDI output from the
receiver (see Table 6) or an internal register
(address 38H) programmed by the microproces-
sor (in which case the other K2 bits are also
updated from register 38H). This choice is con-
figurable via register 30H
Note
The transmitted data at the Slave Regenerator
Section output (MHBDATA<7:0> or MHPOSD/
MHNEGD) is synchronized by the MSP bus
signal MMSPPJ0EN received from the Master.
This results in the A1 framing bytes of both
Master and Slave transmit frames being aligned.
Multiplexer Section Transmitter
The multiplexer section inserts the MSOH overhead
bytes into the transmit frame.
36
l
SXT6051 STM-1/0 SDH Overhead Terminator
.
• The serial RSOH & MSOH interface (TSOH
input pin)
Table 6: K2 RDI Bit Coding
K2<2:0> RDI
• The Internal Processing configured by 30H. The
M1<4:0> REI bits can be either provided by the
detected B2 errors from the receiver or disabled
(set to “00000”). The three MSB (M1<7:5>)
undefined bits are always set to “000” value.
Meaning
Triggered by
bits coding
000
NoRemote No Remote Defect
Defect
E2 Byte: Orderwire
MS-AIS, EED1
Remote
110
This byte is used to provide orderwire channel for
voice communication. The E2 byte source is specified
by the register 60H and can come from:
Defect
Microprocessor2
1. The Excessive Error Defect trigger can be disabled
via register 1AH
• Transmit Telecom bus (In ADM mode)
2. It is possible to force insertion of RDI by configuring
register 1AH
• A dedicated 64 kbit/s serial interface (TMOW
input pin)
See note above
D4 to D12 Bytes: Data Communication
Channel:
NU Bytes: Bytes Reserved for a National Use
In the STM-1 mode, two bytes are reserved for a
National Used. They are located in row number 9, col-
umn number 8 (NU9-8) and column number 9 (NU9-
9) of the MSOH (see Figure 10).
The D4-D12 byte source is specified by the register
60H and can come from:
• Transmit Telecom bus (In ADM mode)
• A dedicated 576 kbit/s serial interface (TMD
input pin)
The NU9-8 byte source is specified by the register 61H
and can come from:
Note
• The serial RSOH and MSOH interface (TSOH
input pin)
The D4-D12 bytes can be passed-through
unchanged from an SXT6051 receiver (when
receive re-timing is disabled) to a SXT6051
transmitter by using the Telecom bus support. If
the two clock frequencies (receive and transmit)
are different, some data will be periodically lost or
added depending on the frequency variation. For
example, for a difference of 5ppm between the
clocks, one frame will be lost or added every 25s.
• An internal register (address 35H) programmed
by the microprocessor
The NU9-9 byte source is specified by the register 61H
and can come from:
• The serial RSOH and MSOH interface (TSOH
input pin)
• An internal register (address 36H) programmed
by the microprocessor
S1 Byte: Synchronization Status
The S1<3:0> bits are allocated for Synchronization
Status Messages. The S1 byte source is specified by
the register 61H and can come from:
Undefined Bytes
The 25 undefined bytes of the STM-1 frame’s MSOH
(see Figure 10) can be provided to the transmit frame
by the serial RSOH and MSOH interface (TSOH input
pin)
• The serial RSOH & MSOH interface (TSOH
input pin)
• An internal register (address 39H) programmed
by the microprocessor
Regenerator Section Transmitter
The Regenerator section inserts the RSOH overhead
bytes. In a repeater configuration, each received
RSOH byte (except A1, A2 and B1) can be individu-
ally passed through unchanged.
M1 Byte: MS-REI
This byte is allocated for the Multiplex Section
Remote Error Indication. The M1 byte source is spec-
ified by the register 60H and can come from:
37
Functional Description
A1 & A2 Framing Bytes
F1 byte: Orderwire Channel
The frame keyword bytes are always regenerated in
the SXT6051 Transmitter regardless of the configura-
tion.
This byte is reserved for user purposes and can be used
as extra maintenance orderwire channel. Register 60H
specifies the F1 source to be either:
• The received byte (Regenerator mode) from the
Regenerator Section receiver. The received byte
from the transmit telecom bus (ADM mode)
The Regenerator Section Trace J0
This byte is inserted to repetitively transmit a Section
Access Identifier so that a section receiver can verify
its continued connection to the intended transmitter.
The 16 byte “expected” J0 string value needs to have
the correct CRC7 bits per G707 specifications. Regis-
ter 60H specifies the J0 source to be either:
• The dedicated 64 kbit/s serial interface (TDOW
input pin)
• Transmit Telecom bus (In ADM mode)
See note above.
• The received byte (Regenerator mode) from the
Regenerator Section receiver. The received byte
from the transmit telecom bus (ADM mode)
D1 to D3 Bytes: Data Communication Channel
This channel is used as a data channel by the network
management. Register 60H specifies the D1-D3
source to be either:
• The serial RSOH and MSOH interface (TSOH
input pin)
• The internal RAM (16 byte) programmed by the
microprocessor
• The received byte (Regenerator mode) from the
Regenerator Section receiver. The received byte
from the transmit telecom bus (ADM mode)
The RAM is accessed via registers 75H and 76H. Dur-
ing J0 RAM configuration the transmitted J0 byte
value is “01H.” Note that a complete 16-byte string
with CRC7 is required by the ITU for proper opera-
tion.
• A dedicated 192 kbit/s serial interface (TRD
input pin)
See note above
NU Bytes: Bytes Reserved for a National Use
In the STM-1 mode, four bytes are reserved for
National Use. They are located in row number 1, col-
umn numbers 8 (NU1-8) and 9 (NU1-9) and in row
number 2, column numbers 8 (NU2-8) and 9 (NU2-9)
of the MSOH (see Figure 10). Registers 61H and 30H
specify the source of these bytes. The possibilities are:
Compatibility of J0 with in-service equipment can be
provided by either writing a value into the transmit J0
RAM, or by setting register 3AH, to value ‘1’ (see reg-
ister 3AH).
B1 Bip-8 Byte
B1 byte is always regenerated in the SXT6051 trans-
mitter. This byte is used for the Regenerator Section
error monitoring function. It is the result of a BIP-8
calculation done on the previous scrambled frame, and
it is inserted into transmit RSOH before scrambling.
For testing purpose, it is possible to invert the B1
value, (register 30H). The B1 value can either be
inverted for a single frame (8 errors), or forever.
• The received byte (Regenerator mode) from the
Regenerator Section receiver.
• The serial RSOH and MSOH interface (TSOH
input pin)
• Internal registers (address 31H, 32H, 33H, 34H)
• Default value AAH (only for NU1-8 and NU1-9)
E1 Byte: Orderwire Channel
MD bytes: Media Dependent Bytes
This byte is used to provide an orderwire channel for
voice communication. Register 60H specifies the E1
source to be either:
In the STM-1 mode, the six media-dependent bytes are
located in raw number 2, column numbers 2 (MD2-2),
3 (MD2-3), and 5 (MD2-5) and in raw number 3, col-
umn numbers 2 (MD3-2), 3 (MD3-3), and 5 (MD3-5)
of the MSOH. Register 63H specifies the source of
these bytes. The possibilities are:
• The received byte (Regenerator mode) from the
Regenerator Section receiver. The received byte
from the transmit telecom bus (ADM mode)
• The received byte (Regenerator mode) from the
Regenerator Section receiver
• The dedicated 64 kbit/s serial interface (TROW
input pin)
See note above.
38
l
Functional Description
• The serial RSOH and MSOH interface (TSOH
input pin)
MFRMO of chip #2 connected to input pin MFRMI of
chip #3, etc.).
If the MFRMI is not used it must be tied to GND.
UN Bytes: Undefined Bytes
In the STM-1 mode, four “Undefined” bytes are
located in row number 2, column number 6 (UN2-6),
and in row number 3, column numbers 6 (UN3-6), 8
(UN3-8), and 9 (UN3-9) of the MSOH (see Figure 10).
Register 63H specifies the source of these bytes. The
possibilities are:
Parallel Interface
The parallel interface output is a byte wide bus MHB-
DATA. The parallel clock is output synchronous with
MHBCLKO (6.48 MHz/STM-0 or
19.44 MHz/STM-1).
• The received byte (Regenerator mode) from the
Regenerator Section receiver
The parallel interface is selected via register 50H. The
selection of a parallel interface is common between the
transmit and receive sides.
• The serial RSOH and MSOH interface (TSOH
input pin)
In case of a repeater application, the order on the par-
allel byte will be the same between the input and the
output and the delay is constant. The repeater delay is
approximately 700ns in STM-0 mode and 233ns in
STM-1 mode.
Scrambler
After inserting the RSOH bytes, the data is scrambled.
The ITU Standard scrambler is 27 -1. Two additional
scramblers 211 - 1 and 213 -1 can be programmed for
STM-0 and STM-1 via register 50H. This flexibility
allows the optimum choice of scrambler for a radio
application.
Serial Interface
The serial interface output at STM-0 is a B3ZS signal
output on MHPOSD and MHNEGD. The output clock
is MICLK (51.84 MHz).
The data scrambling can be disabled via register 50H
or via the external input pin SCRAMSEL.
Note that the selection of serial interface and B3ZS
decoder (see register 50H) is common to the transmit-
ter and the receive side of the chip.
External Frame Synchronization
The SXT6051 provides an external frame pulse refer-
ence (output pin MFRMO). It is an 8 KHz reference
signal with a pulse duration of 154ns (STM-0) or 51ns
(STM-1). This pulse is used to identify the position of
the frame start. This signal is synchronous with the
output transmit frame clock.
If the B3ZS decoder is not used, MHPOSD is used as
a NRZ output pin.
Transmit Frame Alignment
The transmit frame can be synchronized (in Terminal
or ADM mode, no protection or protection Master) by
using an external 8 KHz reference connected to the
MFRMI input pin. This input signal is active High and
can be either a square wave or a pulse.
If the SXT6051 is configured in parallel mode the
MFRMI input must be synchronous with the MHB-
CLKI parallel Transmit Frame clock reference input;
if the SXT6051 is configured in serial mode, the
MFRMI input must be synchronous with MHICLK
serial Transmit Frame clock reference input (51.84
MHz).
This feature can be used by an Upper Level Multi-
plexer to align several SXT6051s. The alignment can
done by cascading the reference signals (output pin
39
l
SXT6051 STM-1/0 SDH Overhead Terminator
Clock Distribution and Reference
Depending on the chip configuration, the source of the Transmit Clock references
Table 7: Operating Mode Vs. Input Clock Source Reference
Transmit
Frame
Parallel Clock
Reference
output
Transmit
Frame
Serial Clock
Reference
output
MSP & TSOH
Bus
Parallel Clock
Reference
output
Telecom Bus
Parallel Clock
Reference
output
VC3/4 &
TPOH Bus
Clock
Reference
output
MHBCLKO
MICLK
MMSPPCKO
MTBCKO
TPOHCK
OPERATING
MODE
CLOCK SOURCE (INPUT PIN)
Repeater
Not used
(tri-state)
DHICLK (1)
DHICLK / 8 (1)
Not used
(tri-state)
Not used
(tri-state)
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20ppm)
Repeater
DHBCLK (2)
Not used
(tri-state)
DHBCLK (2)
Not used
(tri-state)
Not used
(tri-state)
Parallel interface (6.48/19.44 MHz
± 20ppm)
(6.48/19.44 MHz
±20ppm)
Terminal
Not used
(tri-state)
MHICLK
MHICLK / 8
MHICLK / 8
MHICLK / 8
No Protection
Serial interface
Terminal
(51.84 MHz
±20ppm)
(6.48 MHz
±20ppm)
(6.48 MHz
±20ppm)
(6.48 MHz
±20 ppm)
MHBCLKI
Not used
(tri-state)
MHBCLKI
MHBCLKI
MHBCLKI
(6.48/
19.44MHz
± 20ppm)
No Protection
Parallel interface
(6.48/19.44 MHz
± 20ppm)
(6.48/19.44 MHz
±20ppm)
(6.48/19.44 MHz
±20ppm)
ADM
Not used
(tri-state)
MHICLK
MHICLK / 8
Not used
(tri-state)
MTBCLKI
No Protection
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20 ppm)
(6.48 MHz
±20 ppm)
40
SXT6051 Functional Description
Table 8: Operating Mode Vs Output Clock Source Reference
Transmit
Frame
Parallel
Clock
Reference
output
Transmit
Frame
Serial
Clock
Reference
output
MSP & TSOH
Bus
Parallel
Clock
Reference
output
Telecom
Bus
Parallel
Clock
Reference
output
VC3/4 &
TPOH Bus
Clock
Reference
output
MHBCLKO
MICLK
MMSPPCKO
MTBCKO
TPOHCK
ADM
MHBCLKI
Not used
(tri-state)
MHBCLKI
Not used
(tri-state)
MTBCLKI
No Protection ➝ Parallel
interface
(6.48/
19.44 MHz
± 20ppm)
(6.48/
19.44 MHz
±20ppm)
(6.48 MHz
±20 ppm)
Terminal ➝ Protection Main Not used
MHICLK
MHICLK / 8
MHICLK / 8
MHICLK / 8
(tri-state)
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20 ppm)
(6.48 MHz
±20 ppm)
(6.48 MHz
±20 ppm)
Terminal
MHBCLKI
Not used
(tri-state)
MHBCLKI
MHBCLKI
MHBCLKI
Protection Main
Parallel interface
(6.48/
19.44 MHz
± 20ppm)
(6.48/
19.44 MHz
±20ppm)
(6.48/
19.44 MHz
± 20ppm)
(6.48 /
19.44 MHz
±20ppm)
Terminal ➝ Protection Slave Not used
MHICLK
MMSPPCKI
Not used
(tri-state)
Not used
(tri-state)
(tri-state)
Serial interface
(51.84 MHz
±20ppm)
(6.48/
19.44 MHz
±20ppm)
Terminal
MMSPPCKI
Not used
(tri-state)
MMSPPCKI
Not used
(tri-state)
Not used
(tri-state)
Protection Slave
Parallel interface
(6.48/
19.44 MHz
± 20ppm)
(6.48/
19.44 MHz
±20ppm)
ADM ➝ Protection Main
Not used
(tri-state)
MHICLK
MHICLK / 8
Not used
(tri-state)
MTBCLKI
Serial interface
(51.84 MHz
±20ppm)
(6.48 MHz
±20 ppm)
(6.48 MHz
±20 ppm)
1. In case of LOS, MHICLK can be used as a Blue Clock (see register 40H)
2. In case of LOS, MHBCLKI can be used as a Blue Clock (see register 40H)
41
SXT6051 STM-1/0 SDH Overhead Terminator
Table 8: Operating Mode Vs Output Clock Source Reference
Transmit
Frame
Parallel
Clock
Reference
output
Transmit
Frame
Serial
Clock
Reference
output
MSP & TSOH
Bus
Parallel
Clock
Reference
output
Telecom
Bus
Parallel
Clock
Reference
output
VC3/4 &
TPOH Bus
Clock
Reference
output
MHBCLKO
MICLK
MMSPPCKO
MTBCKO
TPOHCK
ADM
MHBCLKI
Not used
(tri-state)
MHBCLKI
Not used
(tri-state)
MTBCLKI
Protection Main
Parallel interface
(6.48/
19.44 MHz
± 20ppm)
(6.48/
19.44 MHz
±20ppm)
(6.48 MHz
±20 ppm)
ADM ➝ Protection Slave
Not used
(tri-state)
MHICLK
MMSPPCKI
Not used
(tri-state)
Not used
(tri-state)
Serial interface
(51.84 MHz
±20ppm)
(6.48/
19.44 MHz
±20ppm)
ADM
MHBCLKI
Not used
(tri-state)
MMSPPCKI
Not used
(tri-state)
Not used
(tri-state)
Protection Slave
Parallel interface
(6.48/
19.44 MHz
± 20ppm)
(6.48/
19.44 MHz
±20ppm)
1. In case of LOS, MHICLK can be used as a Blue Clock (see register 40H)
2. In case of LOS, MHBCLKI can be used as a Blue Clock (see register 40H)
42
SXT6051 Functional Timing
FUNCTIONAL TIMING
Transmit Frame Parallel Timing
Figure 12:Transmit Frame Reference Timing Parallel Interface
MHBC LKI
Input parallel clock
for transmit frame
(6.48 MHz
19.44 M Hz
/
STM-0 or
STM-1
Every fram e
/
)
MFRM I
External input frame reference
for transmit frame (8 KHz)
MHBC LKO
Output Parallel Clock
(Transmit Frame)
MHBD ATA (STM -0)
Output parallel data
(Transmit Frame)
A1
A2
J0
Data
Data
Data
Data
Data
Data
Data
Data
Data
MFRM O (STM -0)
Output Frame Reference
(Transmit Frame)
Every fram e
MHBD ATA (STM -1)
A1
A2
A2
A2
J0
NU1_8 NU1-9
Data
Data
Data
Data
Data
Data
Data
Output data
(
Transmit Frame)
MFRM O (STM -1)
Every fram e
Output Frame Reference
(
Transmit Frame)
Note :
a. MFRM I input cannot be used in repeater m ode or in 1+1 protection "slave" configuration.
(has to be tied to ground or VCC)
b. MFRM I input can be tied to ground if there is no need to synchronize the transm it fram e with an
external reference. The transm it fram e reference is then dependent to the chip reset.
43
SXT6051 Functional Timing
Transmit Frame Serial Timing
Figure 13:Transmit Frame Reference Timing Serial Interface (STM-0)
MHICLK
Input serial clock
for transmit frame
(
51.84 MHz / STM -0 )
Every fram e
MFRMI
External input frame reference
for transmit frame (8 KHz)
MICLK
Output Serial Clock
(
Transmit Frame)
MHPOSD (B3ZS)
A1
A1
A1
A1
A1
A1
A1
A1
A2
A2
A2
A2
A2
A2
A2
bit1
MHNEGD (B3ZS)
D ata
D ata D ata D ata
D ata D ata D ata D ata D ata D ata D ata D ata
MS B bit6 bit5 bit4 bit3 bit2 bit1 LSB MS B bit6 bit5 bit4 bit3 bit2
Output Serial data (Transmit Frame)
MFRMO (STM-0)
Output Frame Reference
Every fram e
(
Transmit Frame)
MM SPPCKO
Output Byte Clock Reference
(
Transmit Frame : 6.48 M Hz)
MHPOSD (NRZ)
A1
MS B bit6
A1
A1
bit2
A2
bit2
A1
A1
A1
A1
A1
A2
A2
A2
A2
bit4 bit3
A2
A2
bit1 LSB
A2
D ata D ata D ata D ata D ata D ata D ata D ata D ata D ata D ata
Output Serial data( Transmit Frame)
(M HNEG D output is tied to high)
bit5 bit4 bit3
bit1 LSB MS B bit6 bit5
Notes :
a. M FRM I input cannot be used in repeater m ode or in 1+1 protection "slave" configuration.
(has to be tied to ground or VCC)
b. M FRM I input can be tied to ground if there is no need to synchronize the transm it fram e with an
external reference. The transm it fram e reference is then dependent to the chip reset.
c. MFRMO output tim ing is different from the one above in repeater m ode. This output is not usable in
case of a repeater (pulse position relatively to A1 MSB depends on the receiver sync. )
44
SXT6051 STM-1/0 SDH Overhead Terminator
Receive Re-timing Functional Timing
Figure 14:Receive Re-Timing Function Timing
DRETCLK
Input clock
for retim ing
(
6.48 M H z
/
/
STM -0 or
Every
fram e
19.44 M H z
STM -1
)
DRETFRMI
Input fram e clock
for retim ing
( 8 KH z
)
DTBCK
O utput C lock
(
D em ultiplexer telecom bus)
DTBDATA (STM -0)
J0
position
O utput data
Data
A1
A2
Data
Data
Data
Data
Data
Data
Data
Data
Data
(
D em ultiplexer telecom bus)
DTBPAYEN (STM -0)
O utput Payload EN able
(
D em ultiplexer telecom bus)
DTBDATA (STM -1)
J0
NU1_8
NU1-9
O utput data
A1
A2
A2
A2
Data
Data
Data
Data
Data
Data
Data
position position position
(
D em ultiplexer telecom bus)
DTBPAYEN (STM -1)
O utput Payload EN able
(
D em ultiplexer telecom bus)
45
Functional Timing
byte locations can be filled by a 0 or
1 but not tri-stated.
Telecom Bus Interface
The SXT6051 follows the industry standard Telecom Bus
to interface with other SDH products, including the
SXT6251. The standard is based on the original work of the
IEEE P1396 project, which never made it to final approval.
SFT has enhanced the bus to be compatible with other stan-
dard SDH products on the market.
MTBPAR
MTBCKO
MTBDATA<7:0> parity check. An odd
parity calculation accompanies each data
byte input (including the bytes filling the
SOH, AUP and HPOH locations).
Telecom Bus byte clock output (6.48
MHz in STM-0 and 19.44 MHz in STM-
1 mode). This clock is the same as the
Multiplexer transmit frame clock output
(MHBCLKO).
Multiplexer Telecom Bus Terminal
Mode
In this mode, the Telecom Bus is a contra-directional inter-
face. This means the SXT6051 generates the timing refer-
ences (clock and signals) and receives the synchronized
data.
MTBCKI
Not used in terminal mode (should be
tied to ground).
MTBPAYEN A High on this output indicates the loca-
tion of the VC-4 (STM-1 mode) or the
VC-3 with two stuffed columns (STM-0
mode) on the Multiplexer Telecom Bus.
A Low indicates the location of the SOH
bytes and the AU Pointers bytes.
Note on Telecom Bus
Timing Reference
All transitions of the Telecom bus Timing
references (MTBH4EN, MTBPAYEN,
MTBJ0EN and MTBTUGEN) are in phase with
the rising edge of MTBCKO, and the incoming
data (MTBPAR & MTBDATA<7:0>) are
clocked by the falling edge of this clock.
MTBH4EN
An output that indicates the multi-frame
start position. This signal is High during
one complete frame every four frames
and Low for the remaining three frames
The Low to High or High to Low transi-
tion occurs at the H4 location, and the
MTBH4EN output is High on the J1 byte
position following the “00” value of H4.
Note on Multi-Frame
Synchronization
The transmit multi-frame can be synchronized by
using an external 2 KHz reference signal
connected to the MMFRMI input pin. This
synchronization input signal can only be active
High for a single frame and must be synchronous
with MTBCLKO or MHBCKO outputs.
MTBJ0J1EN
An output that indicates J0 and J1 bytes
locations relative to the SXT6051 Trans-
mit Frame synchronization as there is no
AU pointer movements and no re-timing
functions in Terminal mode (AU pointer
equal to value 0). MTBJ0J1EN can be
configured via register 71H in two ways:
It is possible to synchronize several transmitters
by cascading the synchronization: Connect the
output MTBH4EN of one chip (chip #1) to the
input MMFRMI of a second chip (chip #2), etc. If
no synchronization is required, MMFRMI must
be grounded.
•A single pulse at J0 position and a sin-
gle pulse at J1 position.
•A single pulse at J0 position, a single
pulse at J1 position and a double pulse
on J1 every four frames to indicate the
V1 position.
This Telecom Bus is comprised of the following signals:
MTBDATA<7:0> Byte wide input data with either
STM-1 or STM-0 frame structure
MTBTUGEN1 A High indicates the location of TUG3
#1, plus the position of the VC-4 POH
depending on STMMODE selec-
tion. Only the C-4 (in STM-1) or C-
bytes. In STM-0 this output is tied High.
MTBTUGEN2 A High indicates the location of TUG3
3 (in STM-0) bytes are relevant. The
#2, plus the position of the VC-4 POH
SOH Byte, AU Pointers and HPOH
46
l
SXT6051 STM-1/0 SDH Overhead Terminator
bytes (But not the stuffed column). In
STM-0 this output is tied High
long and cover the J1 time slot. (See
timing for further details)
MTBTUGEN3 A High indicates the location of TUG3
#3, plus the position of the VC-4 POH
bytes (But not the stuffed column). In
STM-0 this output is tied High.
Note that MMFRMI input pin is not
used and is tied to ground.
MTBJ0J1EN
This input indicates J0 and J1 bytes’
locations
on
MTBDATA<7:0>.
MTBJ0J1EN can be configured via
register 71H in two ways:
Multiplexer Telecom Bus ADM
Mode
In this mode, the Telecom Bus is a co-directional interface.
This means the SXT6051 receives the timing references
(clock and signals) and the associated data.
•A single pulse at J0 position and a
single pulse at J1 position indi-
cates when the frame and the
payload starts.
The signals for this mode are:
•A single pulse at J0 position, a sin-
gle pulse at J1 position and a dou-
ble pulse on J1 every four frames
indicating a multiframe.
MTBDATA<7:0> Identical to the Terminal mode.
MTBPAR
MTBCKO
MTBCKI
Identical to the Terminal mode.
Output is tri-stated (not used).
MTBTUGEN1
MTBTUGEN2
MTBTUGEN3
Outputs are tri-stated (not used).
Outputs are tri-stated (not used).
Outputs are tri-stated (not used).
This input is the Telecom Bus byte
clock (6.48 MHz in STM0 and 19.44
MHz in STM1 mode). It can be asyn-
chronous to the transmit reference
clock input.
Demultiplexer Telecom Bus
(Terminal or ADM) Mode
Note that the incoming data (MTB-
PAR and MTBDATA<7:0>) and
Telecom bus Timing references
(MTBH4EN, MTBPAYEN, and
MTBJ0J1EN) are internally clocked
by the falling edge of MTBCKI (see
Telecom bus timings).
Note on Telecom Bus
Timing Reference
All transitions of the Telecom bus Timing
references (DTBH4EN, DTBPAYEN, DTBJ0EN
and DTBTUGEN) and the outgoing data
(DTBPAR and DTBDATA<7:0>) are clocked by
the rising edge of DTBCK (see Telecom bus
timings).
MTBPAYEN
MTBH4EN
A High on this input indicates the
location of the VC-4 (STM-1 mode) or
the VC-3 with two stuffed columns
(STM-0 mode). A Low indicates the
location of the SOH bytes and the AU
Pointers bytes.
The signals for this mode are:
DTBDATA<7:0>Byte wide data output with either STM-
1 or STM-0 frame structure depending
on STMMODE selection.
This input indicates the multiframe
start position. This input is not used if
MTBJ0J1EN is configured to support
the “framing-multiframing indication”
(see register 71H<7>). When used,
this signal must be High one frame
every fourth frame. It is possible to use
a pulse as an indicator. As a minimum,
this pulse has to be one clock cycle
DTBPAR
DTBDATA<7:0> parity check. An odd
parity bit calculation accompanies each
data byte input (including the bytes fill-
ing the SOH, AUP and HPOH loca-
tions).
47
SXT6051 STM-1/0 SDH Overhead Terminator
DTBCK
Telecom Bus byte clock output 6.48
MHz (STM-0) and 19.44 MHz (STM-1)
mode.
DTBPAYEN
A High on this output indicates the pres-
ence of the VC-4 (STM1 mode) or the
VC-3 with two stuffed columns (STM0
mode). A Low indicates the presence of
the SOH bytes and the AU Pointers’
bytes.
DTBH4EN
Output indicates the multi-frame start
position. This signal is High during one
complete frame every four frames and
Low for the remaining three frames The
Low to High or High to Low transition
occurs at the H4 location, and the
MTBH4EN output is High on the J1 byte
position following the “00” value of H4.
DTBJ0J1EN
Output indicates J0 and J1 byte locations
relative to the receive signal.
MTBJ0J1EN can be configured via reg-
ister 81H in two ways:
•A single pulse at J0 position and a sin-
gle pulse at J1 position indicates when
the frame and the payload starts.
•A single pulse at J0 position, a single
pulse at J1 position and a double pulse
on J1 every four frames indicating a
multiframe.
DTBTUGEN1 A High on this output indicates the loca-
tion of TUG3 #1, plus the presence of the
VC-4 POH bytes. In STM-0 this output
is tied High.
DTBTUGEN2 A High on this output indicates the loca-
tion of TUG3 #2, plus the presence of the
VC-4 POH bytes (but not the stuffed col-
umn) In STM-0 this output is tied High.
DTBTUGEN3 A High on this output indicates the loca-
tion of TUG3 #3, plus the presence of the
VC-4 POH bytes (but not the stuffed col-
umn) In STM-0 this output is tied High.
Figures 15 and 16 show the relation of timing reference and
data signals on the Telecom bus.
48
SXT6051 Functional Timing
Figure 15:STM-0 Telecom Bus Timing
STM -0 R eceive Telecom Bus T im ing (Term inal & Add/Drop)
D TBC K
O utput
Every 4th Fram e
if enabled
J0
J1
M F-IND
D TBJ0J1EN
O utput
D TBPAYEN
O utput
J0
Position
D TBD ATA
O utput
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
A2
J1
D TBH 4EN
O utput
G oes H I one clock cycle after H 4 = 00, Low one clock cycle after H 4 = 01
STM -0 T ransm it Telecom Bus T im ing (Term inal)
M TB CK O
O utput
Every 4th Fram e
if enabled
J0
J1
M F-IND
M TB J0J1EN
O utput
M TB PAYEN
O utput
J1
Position
H1
Position
H2
H3
J0
Position
C -3
C-3
C -3
C -3
C -3
C-3
C-3
C-3
M TB DA TA
Input
Position Position
M TB H4EN
G oes H I one clock cycle after H 4 = 00, Low one clock cycle after H 4 = 01
O utput
STM -0 T ransm it Telecom Bus T im ing (Add/Drop)
M TB CK I
Input
Every 4th Fram e
if enabled
J0
J1
M TB J0J1EN
Input
M F-IND
M TB PAYEN
Input
A2
J0
J1
Position
M TB DA TA
Input
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
C-3
Position Position
M TB H4EN
Input
G oes H I one clock cycle after H 4 = 00, Low one clock cycle after H 4 = 01
49
SXT6051 Functional Timing
Figure 16:STM-1 Telecom Bus Timing
STM-1 Receive Telecom Bus Timing (Terminal, Add/Drop)
DTBCK
Output
Enabled
Every 4 th Frame
J0
J1
V1
DTBJ0J1EN
Output
Every POH
byte
DTBPAYEN
Output
DTBTUGEN1
Output
DTBTUGEN2
Output
DTBTUGEN3
Output
Fixed
Stuff
Fixed
Stuff
NU1_8
Positon
NU1_9
Position
TUG3 #2
TUG3 #3
TUG3 #1
TUG3 #2
TUG3 #3
TUG3 #1
TUG3 #2
J0 Position
DTBDATA
J1
A2
Output
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
DTBH4
Output
STM -1 Transm it Telecom Bus Tim ing (Term inal)
M TBCKO
Output
Every 4th Frame
if enabled
J0
J1
V1
M TBJ0J1EN
Output
Every POH
byte
M TBPAYEN
Output
M TBTUGEN1
Output
M TBTUGEN2
Output
M TBTUGEN3
Output
M TBH4
Goes HI one clock cycle after H4 = 00,
Low one clock cycle after H4 = 01
Output
NU1_8
A2 Position J0 Position
Position
H3 #1
Position
H3 #2
Position
H3 #3
Position
Fixed
Stuff
Fixed
Stuff
M TBDATA
J1 Position
TU G3 #1
TU G3 #2
TU G3 #3
TU G3 #1
TU G3 #2
Input
S TM -1 Transm it Telecom B us T im ing (A dd/D rop)
M TBCKI
Input
Enabled
Every 4th Frame
J0
J1
V1
M TBJ0J1EN
Input
M TBPAYEN
Input
A2
Position
J0
Position
NU1_8
Position
NU1_9
Position
Fixed
Stuff
Fixed
Stuff
TUG3 #1
TUG3 #3
J1 Position
TUG3 #1
TUG3 #2
TUG3 #3
TUG3 #1
TUG3 #2
M TBDATA
Input
TIME_STM1_XMT_ADM_TB.VSD - PAGE-1 - 2/11/98
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
M TBH4
Input
50
SXT6051 STM-1/0 SDH Overhead Terminator
Transmitter “Slave” in 1+1
Protection Configuration
The signals for this configuration are:
Protection Bus Interface
Timing
This is the interface between the SXT6051 “Master” and
the SXT6051 “Slave” in a one for one protection mode.
The signals for the configurations are listed in this section.
MMSPPDATA<7:0> Data byte input with a STM-1 or
STM-0 frame structure depending
on STMMODE. Only the AU-4
Transmitter “Master” in 1+1
Protection Configuration
The signals for this configuration are:
(STM-1) or AU-3 (STM-0) data
bytes are valid (pointers included).
MMSPPCKI
Transmit Protection Bus byte clock
input (6.48 MHz in STM-0 and
19.44 MHz in STM-1 mode). This
clock has the same exact frequency
as the transmit frame clock refer-
ence. Data and timing reference are
internally re-sampled by the falling
edge of this clock.
MMSPPDATA<7:0>:Data byte output with a STM-1 or
STM-0 frame structure depending
on STMMODE. Only the AU-4
(STM-1) or AU-3 (STM-0) data
bytes are valid (pointers included).
MMSPPCKO
Transmit Protection Bus byte clock
output (6.48 MHz in STM-0 &
19.44 MHz in STM-1 mode). This
clock has the same exact frequency
as the transmit clock reference.
MMSPPCKO
This output is not part of the Protec-
tion bus, but can be used as the
transmit RSOH and MSOH serial
bus (TSOH bus) clock reference on
the Slave SXT6051.
Note that all transitions of the Trans-
mit Protection Bus Data (MMSPP-
MMSPPJ0JEN
This input indicates J0 byte loca-
tion. It is a single pulse (active High)
when the J0 byte is present on the
MMSPPDATA<7:0> data bus. It is
used to synchronize the transmit
frame, to ensure frame alignment of
the Master and Slave SXT6051.
DATA<7:0>)
and
Timing
references (MMSPPJ0EN and
MMSPPAUEN) are in phase with
the rising edge of this clock. This
clock is also used as the RSOH &
MSOH serial bus (TSOH bus) clock
reference.
MMSPPAUEN
Output is not used (tri-stated)
MMSPPCKI
Input is not used (can be tied to
ground).
MMSPPJ0JEN
Output indicates J0 byte location. It
is a single pulse (active High) when
the J0 byte is present on the MMSP-
PDATA<7:0> data bus.
MMSPPAUEN
A High output indicates the pres-
ence of the VC-4 (STM-1) or the
VC-3 + 2 stuffed columns (STM-0)
bytes on the MMSPPDATA<7:0>
data bus. A Low indicates the pres-
ence of the SOH + AU Pointers
bytes. This pin is used as a test point
or in the Ring Protection for a Fiber
ADM application (see Application
Note SDH Chip Set on the fiber).
51
SXT6051 STM-1/0 SDH Overhead Terminator
Receive”Master” in 1+1 Protection
Receive “Slave” Configuration
Configuration
The signals for this configuration are:
(1+1 Protection)
The signals for this configuration are:
DMSPPDATA Data byte input with an STM-1 or
STM-0 frame structure depending on
STMMODE. This bus includes also the
SOH bytes to be processed for protection
switching.
DMSPPDATA Data byte output with a STM-1 or
STM-0 frame structure depending on
STMMODE. This bus also includes the
SOH byte to be processed for protection
switching.
DMSPPCKI
Receive Protection Bus byte clock input
(6.48 MHz in STM-0 and 19.44 MHz in
STM-1 mode).
DMSPPCKI
This input is not used.
DMSPPCKO Receive Protection Bus byte clock out-
put (6.48 MHz in STM-0 and 19.44 MHz
in STM-1 mode).
Note that all transitions of the Receive
Protection
Bus
Data
(DMSPP-
Note that the transitions of the Receive
Protection bus Data (DMSPPDATA)
and Timing references (DMSPPJ0EN &
DMSPPAUEN) are in phase with the ris-
ing edge of this clock. This clock is also
used as the receive RSOH and MSOH
serial bus (RSOH bus) clock reference.
DATA<7:0>) and Timing references
(DMSPPJ0EN and DMSPPAUEN) are
in phase with the rising edge of this
clock.
DMSPPCKO This output is not used for the MSP bus.
It is used as the Serial RSOH and MSOH
bus (RSOH bus) clock reference
DMSPPJ0JEN This output indicates the J0 byte loca-
tion. It is a single pulse (active High)
indicating the presence of the J0 position
on the DMSPPDATA<7:0> data bus.
(Used for protection bus K1/K2 byte
recovery by the Master).
DMSPPJ0JEN This input indicates J0 byte location. It is
a single pulse (active High) indicating
the presence of the J0 byte on the DMSP-
PDATA<7:0> transmit data bus. (Used
for protection bus K1/K2 byte recovery).
DMSPPAUEN A High on this input indicates the pres-
ence of the VC-4 (STM-1) or the
DMSPPAUEN A High on this output indicates the pres-
ence of the VC-4 (STM-1) or the VC-3 +
2 stuffed columns (STM-0) bytes on the
DMSPPDATA<7:0> data bus. A Low
indicates the position of the SOH + AU
Pointers bytes.
VC-3 + 2 stuffed columns (STM-0)
bytes on DMSPPDATA<7:0>. A Low
indicates SOH + AU Pointer bytes.
DMSPPSF
DMSPPSD
Signal Fail input indicator from the
SXT6051 slave. Active High.
DMSPPSF
Signal Fail output indicator. Active
High.
Signal Degrade input indicator from the
SXT6051 slave. Active High.
DMSPPSD
Signal Degrade output indicator. Active
High.
52
SXT6051 Functional Timing
Figure 17: Master MSP Interface Timing
Multiplexer Protection Interface
M HBCLKI
STM-0/6.48MHz
STM-1/19.44MHz
M M SPPCKO
M M SPPJ0EN
J0 Enable Output
A1
A2
M M SPPDATA
A2
J0
J0
B1
B1
E1
F1
STM-0 Output Data
RSOH
1
RSOH
2
M M SPPAUEN
STM-0 Output Enable
NU1_8
NU1_9
M D2_2
M D2_3
M D2_5
M M SPPDATA
A2
E1
STM-1 Output Data
RSOH
1
RSOH 2
M M SPPAUEN
STM-1 Output Enable
Demultiplexer Protection Interface
DM SPPC KI
STM-0/6.48MHz
STM-1/19.44MHz
DM SPPJ0EN
J0 Enable Input
DM SPPD ATA
A2
J0
B1
E1
F1
STM-0 Input Data
RSOH
1
RSOH 2
DM SPPAU EN
STM-0 Input Enable
DM SPPD ATA
NU1_8
NU1_9
M D2_5
M D2_2
M D2_3
A2
A2
J0
B1
E1
STM-1 Input Data
RSOH
2
RSOH
1
DM SPPAU EN
STM-1 Input Enable
53
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 18:Slave MSP Interface Timing
M ultiplexer Protection Interface
M M SPPC KI
STM -0/6.48MHz
STM -1/19.44MHz
M M SPPC KO
J0
M M SPPJ0EN
J0 Enable Input
M M SPPD ATA
A1
A2
J0
B1
B1
E1
F1
STM -0 Input Data
RSO H
1
RSO H 2
M M SPPAU EN
NO T USED
NU1_8
NU1_9
M D2_5
M M SPPD ATA
M D2_2
RSO H
M D2_3
E1
A2
A2
J0
STM -1 Input Data
RSO H
1
2
Dem ultiplexer Protection Interface
D M SPPCKO
STM -0/6.48MHz
STM -1/19.44MHz
D M SPPJ0EN
J0 Enable Output
D M SPPDATA
STM -0 Output Data
A2
J0
B1
E1
F1
RSO H
1
RSO H 2
D M SPPAU EN
STM -0 Output Enable
NU1_8
NU1_9
M D2_2
RSO H
M D2_3
M D2_5
A2
A2
J0
B1
E1
D M SPPDATA
STM -1 Output Data
RSO H
1
2
D M SPPAU EN
STM -1 Input Enable
54
SXT6051 Functional Timing
OverHead Byte Access Timing
F2 and F3 Digital Channel Functional Timing
Transmit side access
• Data input are TPOW1 and TPOW2 input.
• Clock reference is TPOWC. This 64 KHz signal is a square wave.
• Byte reference is TPOWBYC.
• Both the clock reference and the byte reference are synchronous with the transmit VC.
Figure 19:Transmit F2 and F3 Orderwire Timing
1 fram e : 125 us
TPOW C
Output clock
(
64 KHz )
TPOW BYC
Output frame byte clock
(
8 KHz )
TPOW 1
F2 LSB F2 MSB F2 bit 6 F2 bit 5 F2 bit 4 F2 bit 3 F2 bit 2 F2 bit 1 F2 LSB F2 MSB F2 bit 6 F2 bit 5 F2 bit 4
Input F2 data channel
TPOW 2
F3 LSB F3 MSB F3 bit 6 F3 bit 5 F3 bit 4 F3 bit 3 F3 bit 2 F3 bit 1 F3 LSB F3 MSB F3 bit 6 F3 bit 5 F3 bit 4
Input F3 data channel
Receive side access
• Data output are RPOW1 and RPOW2 input.
• Clock reference is RPOWC. This 64 KHz signal is a square wave.
• Byte reference is RPOWBYC.
• Both the clock reference and the byte reference are synchronous with the receive VC.
Figure 20:Receive F2 and F3 orderwire timing
R eceive P ath O verH ead S erial O rderwire Tim ing (F2 F3)
1 fram e : 125 us
RPO W C
Output clock
(
64 KHz )
RPO W BYC
Output frame byte clock
(
8 KHz )
RPO W 1
F2 LSB F2 MSB F2 bit 6 F2 bit 5 F2 bit 4 F2 bit 3 F2 bit 2
F2 bit 1 F2 LSB F2 MSB F2 bit 6 F2 bit 5 F2 bit 4
F3 bit 1 F3 LSB F3 MSB F3 bit 6 F3 bit 5 F3 bit 4
F2 bit 5
F3 bit 5
Output F2 data channel
RPO W 2
F3 LSB F3 MSB F3 bit 6 F3 bit 5 F3 bit 4 F3 bit 3 F3 bit 2
Output F3 data channel
55
SXT6051 STM-1/0 SDH Overhead Terminator
E1, E2 and F1 Orderwire Channel Functional Timing
Transmit Timing
• Data input are TROW TMOW and TDOW
• Clock reference is TOWC. This 64 KHz signal is a square wave.
• Byte reference is TOWBYC.
• Both the clock reference and the byte reference are synchronous with the transmit clock
Figure 21:Transmit orderwire E1, E2 and F1 timing
Transm it m ultiplex & regenenerator Section O verH ead Serial O rderwire Tim ing (E1 F1 E2)
1 fram e : 125 us
TOW C
Output clock
(
64 KHz )
TOW BYC
Output frame byte clock
(
8 KHz )
TROW
E1 LSB
E1 MSB
E1 bit 6
E1 bit 5
E1 bit 4
E1 bit 3
E1 bit 2
E1 bit 1
E1 LSB
E1 MSB
E1 bit 6
E1 bit 5
E1 bit 4
Input E1 data channel
TDOW
F1 LSB
E2 LSB
F1 MSB
E2 MSB
F1 bit
6
F1 bit
5
F1 bit
4
F1 bit
3
F1 bit
2
F1 bit
1
F1 LSB
E2 LSB
F1 MSB
E2 MSB
F1 bit
6
F1 bit
5
F1 bit 4
Input F1 data channel
TMOW
E2 bit 6
E2 bit 5
E2 bit 4
E2 bit 3
E2 bit 2
E2 bit 1
E2 bit 6
E2 bit 5
E2 bit 4
Input E2 data channel
Receive timing
• Data outputs are RROW, RMOW and RDOW.
• Clock reference is ROWC. This 64 KHz signal is a square wave.
• Byte reference is ROWBYC.
• Both the clock reference and the byte reference are synchronous with the receive clock.
Figure 22:Receive Orderwire E1, F1 and E2 Timing
R eceive m ultiplex & regenenerator Section O verH ead Serial O rderwires Tim ing (E1 F1 E2)
1 fram e : 125 us
ROW C
Output clock
(
64 KHz )
ROW BYC
Output frame byte clock
(
8 KHz )
RROW
Output E1 data channel
E1 LSB E1 MSB E1 bit 6 E1 bit 5 E1 bit 4 E1 bit 3 E1 bit 2
E1 bit 1 E1 LSB E1 MSB E1 bit 6 E1 bit 5 E1 bit 4
RDOW
Output F1 data channel
F1 LSB F1 MSB F1 bit 6 F1 bit 5 F1 bit 4 F1 bit 3 F1 bit 2
E2 LSB E2 MSB E2 bit 6 E2 bit 5 E2 bit 4 E2 bit 3 E2 bit 2
F1 bit 1 F1 LSB F1 MSB F1 bit 6 F1 bit 5 F1 bit 4
E2 bit 1 E2 LSB E2 MSB E2 bit 6 E2 bit 5 E2 bit 4
RMOW
Output E2 data channel
56
Functional Timing
The clock reference output is TPOHCK at 19.44 MHz
(STM-1) or 6.48 MHz (STM-0). This clock is synchro-
nous with the VC-3 /VC-4 (STM-0/STM-1) or trans-
mit frequency.
HPOH Bytes Serial Access
Functional Timing
Transmit serial HPOH Timing
The TPOH data bits positions are indicated by the
clock enable (output pin TPOHEN). In the STM-0
mode this enable signal is HIGH during 8 consecutive
clock cycles (POH byte), then LOW during 90 - 8 = 82
clock cycles in STM-0. In STM-1 mode the TPOHEN
is HIGH for 8 clock cycles and LOW for 270 -8 = 262
clock cycles.
• Data Input TPOH
• Reference clock TPOHCK synchronous with the
transmit clock
• Frame reference TPOHFR indicates the expected
presence of J1 MSB at TPOH input
• Output enable TPOHEN indicates the expected
presence of HPOH data at TPOH input
TPOHFR indicates the position of J1 MSB.
The TPOH is used to insert all POH byte except the
B3, F2, H4 and F3 bytes. This serial interface uses a
contra-directional gapped bus.
Figure 23:Transmit HPOH Serial Bus Timing
Transm it P ath O verHead S erial B us Tim ing (Term inal & A dd/Drop)
1 fram e: 125 us <=> 810 x TPOHCK clock cycles (STM-0) or 2430 x TPOHCKclock cycles (STM-1)
82 clock cycles (STM-0)
262 clock cycles (STM-1)
8 clock cycles
TPOHFR
Output frame pulse
TPOHEN
Output data enable
TPOH
(1)
(1)
(1)
(1)
(1)
Input data
J1
C2
G1
K3
N1
J1
(1) Unused Time slots
TPOHCK
Output clock
(6.48 MHz (STM-0)
or 19.44 MHz (STM-1)
Every Fram e
TPOHFR
Output frame pulse
TPOHEN
Output data enable
TPOH
J1 bit 1
J1 LSB
J1 MSB J1 bit 6
J1 bit 5
J1 bit 4
J1 bit 3
J1 bit 2
Input data
57
SXT6051 STM-1/0 SDH Overhead Terminator
Receive Serial HPOH Timing
• Data Input RPOH
• Reference clock RPOHCK synchronous with the receive clock
• Frame reference RPOHFR indicates presence of J1 MSB at RPOH output
• Output enable RPOHEN indicates presence of RPOH clock at RPOH output
Figure 24:Receive HPOH Serial Bus Timing
Receive Path OverHead Serial Bus Timing (Terminal & Add/Drop)
1
frame: 125 us <=> 810 x RPOHCK clock cycles (STM-0) or 2430 x RPOHCKclock cycles (STM-1)
82 clock cycles (STM-0)
262 clock cycles (STM-1)
8
clock cycles
RPOHFR
Output frame pulse
RPOHEN
Output data enable
RPOH
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Output data
J1
B3
C2
G1
F2
H4
F3
K3
N1
J1
(1) Unused Time slots
RPOHCK
Output clock
(6.48 MHz (STM-0)
or 19.44 MHz (STM-1)
Every Frame
RPOHFR
Output frame pulse
RPOHEN
Output data enable
RPOH
J1 MSB J1 bit 6
J1 bit 5
J1 bit 4
J1 bit 3
J1 bit 2
J1 bit 1
J1 LSB
Output data
58
Functional Timing
• The reference clock is supplied by MMSPPCKO
at 19.44MHz (STM-1) or at 6.48 MHz (STM-0).
It is at the same frequency as the transmit clock.
Frame pulse TSOHFR indicates the start of the
frame (A1 MSB position).
SOH Overhead Access Functional
Timing
Transmit Side SOH Serial Timing
• The transmit side of SOH interface allows inser-
tion of each SOH byte (except A1, A2, B1 and
B2 bytes), into the MSOH and RSOH via a serial
contra-directional gapped interface.
• Enable signal TSOHEN is high (enabled) for all
bytes of the SOH (see Figure 10). The TSOHEN
signal is not enabled during AU pointer bytes.
• The SXT6051 will latch the data on the TSOH
pin, synchronized with the timing signals. All
data input will be output from the SXT6051 one
SDH row after it is latched.
Figure 25:Transmit TSOH Serial Bus Timing
Transmit multiplex & regenenerator Section OverHead Serial Bus Timing
1 frame: 125 us <=> 810 x MMSPPCKO clock cycles (STM-0) or 2430 x MMSPPCKO clock cycles (STM-1)
66 clock cycles (STM-0)
198 clock cycles (STM-1)
24 clock cycles (STM-0)
72 clock cycles (STM-1)
TSOHFR
Output frame pulse
TSOHEN
Output data enable
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
TSOH
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Input data
# 1
# 2
# 5
# 6
# 1
# 3
# 7
# 8
# 9
(1) Unused Time slots
MMSPPCKO
Output clock
(6.48 MHz (STM-0)
or 19.44 MHz (STM-1)
Every Frame
TSOHFR
Output frame pulse
TSOHEN
Output data enable
A2 MSB(*) or
A1 MSB
J0 Bit 1 or
NU1_9 bit 1 NU1_9 LSB
J0 LSB or
A1
MSB(*)
A1 bit
6(*)
A1 bit
5(*)
A1 bit
4(*)
A1 bit
3(*)
A1 bit
2(*)
A1 bit
1(*)
A1
LSB(*)
TSOH
Input data
( STM-0 or
( STM-0 or ( STM-0 or
(*) unused time slots (A1 & A2 bytes cannot be inserted via the
TSOH bus into the Transmit frame )
STM-1
)
STM-1
)
STM-1 )
24 clock cycles (STM-0) or 72 clock cycles (STM-1)
Note concerning the used and unused time slots :
SOH Row #1 : only J0, and the National Use ( STM1) bytes are relevent
SOH Row #2 : only Media dependent, National Use & Undefined (STM-1) bytes are relevent
SOH Row #3 : only D1 to D3, Media dependant & Undefined (STM-1) bytes are relevent
SOH Row #5 : only K1, K2 and Undefined bytes(STM1) are relevent
SOH Row #6, #7 & #8 : only the Undefined bytes (STM-1) are relevent
SOH Row #9 : only S1, M1, Undefined & National Use (STM-1) are relevent
"Relevent" means these bytes can be inserted into the transmit frame via the TSOH serial bus
TIME XMT SOH VSD PAGE-1
_ _ . - - 2/9/98
59
SXT6051 STM-1/0 SDH Overhead Terminator
Receive Side SOH Serial Timing
The receive side SOH interface provides all the signals necessary to collect the RSOH and MSOH bytes via a serial
co-directional gapped interface described below:
• Frame pulse RSOHFR indicates the start of the frame (A1 MSB position)
• The DMSPPCKO clock (MSP bus clock) is used for clocking the RSOH output.
• Enable signal RSOHEN is high (active) for all bytes of the SOH (see Figure 10).
• On the receive side, the data is immediately output on the RSOH pin when it is received; there is not a row delay
as on the transmit side.
Figure 26:Receive RSOH Timing
Receive multiplex & regenenerator Section OverHead Serial Bus Timing
1
frame: 125 us <=> 810
x
DMSPPCKO clock cycles (STM-0) or 2430
x
DMSPPCKO clock cycles (STM-1)
66 clock cycles (STM-0)
198 clock cycles (STM-1)
24 clock cycles (STM-0)
72 clock cycles (STM-1)
R S O H F R
Output frame pulse
FGVVVVFDC
R S O H E N
Output data enable
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
Soh
Row
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
R S O H
Output data
#
1
#
2
# 5
#
6
# 1
# 3
#
7
#
8
# 9
(1) Unused Time slots
D M S P P C K O
Output clock
(6.48 MHz (STM-0)
or 19.44 MHz (STM-1)
Every Frame
R S O H F R
Output frame pulse
R S O H E N
Output data enable
J0 Bit 1 or
NU1_9 bit
J0 LSB or
NU1_9 LSB
A2 MSB
or A1 MSB
1
R S O H
Output data
A1 MSB A1 bit 6 A1 bit 5 A1 bit 4 A1 bit 3 `A1 bit 2 `A1 bit 1 A1 LSB
(
STM-0 or
STM-1
(
STM-0
(
STM-0 or
STM-1
)
or STM-1
)
)
24 clock cycles (STM-0) or 72 clock cycles (STM-1)
60
SXT6051 Functional Timing
D1 to D3 Data Communication Channel Functional Timing
Transmit Side Access
• Data input is TRD
• Clock reference is TRDC. This 192 KHz signal is a square wave, synchronous with the transmit clock
• TOWBYC can be used to identify the byte position relative to the transmit frame
Figure 27:Transmit D1 to D3 Timing
Transm it Regenerator Section O verHead Serial D CC Tim ing
TRDC
Output clock
(
192 KHz )
TRD
Input
D1 to D3
Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit
Data Communication channel
Receive Side Access
• Data Output is RRD
• Clock reference is RRDC. This 192 KHz signal is a square wave synchronous with the receive clock
• ROWBYC can be used to identify the byte position relative to the receive frame
Figure 28:Receive D1 to D3 Timing
Receive Regenerator Section O verHead Serial D CC Tim ing
RRDC
Output clock
(
192 KHz )
RRD
Input
Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit
Data bit
D1 to D3
Data Communication channel
61
SXT6051 STM-1/0 SDH Overhead Terminator
D4 to D12 Data Communication Channel
Transmit Side Access
• Data Input is TMD
• Clock Reference is TMDC. This 576 KHz signal is a square wave synchronous with the transmit clock
• TOWBYC can be used to identify the byte position relative to the transmit frame
Figure 29:Transmit D4 to D12 Timing
Transm it m ultiplex Section O verHead Serial D CC Tim ing
TMDC
Output clock
(
576 KHz )
TMD
Input
D4 to D12
Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit
Data Communication channel
Receive Side Access
• Data Output is RMD
• Clock reference is RMDC. This 576 KHz signal is a square wave synchronous with the receive clock
• ROWBYC can be used to identify the byte position relative to the receive frame
Figure 30:Receive D4 to D12 Timing
R eceive M ultiplex S ection O verH ead S erial D CC Tim ing
RMDC
Output clock
(
576 KHz )
RMD
Input
Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit
Data bit
D1 to D3
Data Communication channel
62
SXT6051 Functional Timing
BIP Receive Functional Timing
Figure 31:BIP Functional Timing
Receive BIP E rrors Tim ing
DM SPPCKO
Output clock
(
6.48 MHz
19.44 MHz
/
STM-0 or
STM-1
/
)
B1OUT
1
3
1
Output
B1 RS-BIP8 errors
5 errors detected with B1 RS-BIP8
B2OUT
Output
1
B2 MS-BIP
errors
8 or 24
1 error detected
with B2 MS-BIP
RPOHCK
Output clock
(
6.48 MHz
19.44 MHz
/
STM-0 or
STM-1
/
)
B3OUT
4
1
Output
B3 HP-BIP8 errors
5 errors detected with B3 HP-BIP8
63
SXT6051 STM-1/0 SDH Overhead Terminator
TEST SPECIFICATIONS
Notes
Minimum and maximum values in tables 9 though 11 represent the performance specifications of the SXT6051 and are
guaranteed by test, unless otherwise noted. Minimum and maximum values in tables 12 though 27 and figures 32 through
45 represent the performance specifications of the SXT6051 and are guaranteed by design and are not subject to production
testing.
All timing parameters assume that the outputs have a 50 pF load unless otherwise noted.
Table 9: Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
CC
Supply Voltage
V
6.0
V
V
DC Voltage on any pin1
IN
V
-2.0
+7.0
OP
Ambient operating temperature
Storage temperature range
T
-40
-65
+85
C
C
ST
T
+150
1. Minimum voltage is -0.6V D.C. which may undershoot to -2.0 V for pulses of less than 20 ns
CAUTION
Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied
Exposure to maximum rating conditions for extended periods may affect device reliability
.
1
Table 10: Operating Conditions
Parameter
Typ2
Symbol
Min
Max
Unit
Recommended Operating Temperature
Supply Voltage - I/O Ring
TOP
VCC5
VCC3
IDD5
-40
4.75
3.15
-
-
+85
5.25
3.45
90
C
V
5
Supply Voltage - Core
3.3
75
V
Supply Current - I/O Ring 1
Supply Current - Core 1
mA
IDD3
-
100
120
mA
1. The operating condition parameters are for a STM-1 master 1+1 terminal protection configuration with receive re-timing enabled and during
microprocessor access (worst case configuration)
2. Typical values are at 25C and nominal voltage and are provided for design aid only; not guaranteed nor subject to production testing
3. Voltages with respect to ground unless otherwise specifie
64
SXT6051 Test Specifications
Table 11: 5 V Digital I/O Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
TTL Input Low Voltage
TTL Input High Voltage
TTL Switching Threshold
Input Leakage High
VIL
VIH
VT
0.8
V
V
2.0
1.4
V
VCC-5.0V, 25C
VIN-VCC=5.5V
VCC=4.5V
IIH
10
uA
V
Output Low Voltage
VOL
VOH
IOZ
0.2
4.2
0.4
Output High Voltage
0.7xVCC
-10
VCC=4.5V
Output Leakage (no pull up)
10
uA
VIN=VDD=5.5V
1. All values applicable over recommended Voltage and Temperature operating range unless otherwise noted
65
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 32:Serial Interface Timing
MHICLK
MICLK
t1pd
DHICLK
tS U
t2pd
tH
DHPOSD
MHPOSD
MHNEGD
DHNEGD
Transmit Serial Timing
Receive Serial Timing
Table 12: Serial Interface Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
ns
ns
15.5 ns
DHPOSD & DHNEGD setup time to DHICLK falling edge.
DHPOSD & DHNEGD hold time from DHICLK falling edge.
MHICLK rising edge to MICLK rising edge
tsu
th
1.5
1.5
5
t1pd
t2pd
MICLK rising edge to MHPOSD and MHNEGD
0.5
3
ns
Figure 33:Parallel Interface Timing
DHBCLK
MHBCLKI
t1pd
tSU
tH
DHBNRZ<7:0>
MHBCLKO
t2pd
MHBDATA<7:0>
Receive Parallel Timing
Transmit Parallel timing
Table 13: Parallel Interface Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
DHBDATA<7:0> setup time to DHBCLK rising edge.
DHBDATA<7:0> hold time from DHBCLK rising edge.
MHBCLKI rising edge to MHBCLKO rising edge
MHBCLKO rising edge to MHBDATA<7:0>
tsu
th
3
2
7
2
ns
ns
ns
ns
t1pd
t2pd
18
7
66
SXT6051 Test Specifications
Figure 34:Receive Re-Timing Function Timing
DRETCLK
tR ET1pd
tR ET2pd
tR ETh
DTBCK
DTBDATA
DTBPAYEN
DTBJ0J1EN
tR ETsu
DRETFRM I
Table 14: Receive Re-Timing Function Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
DRETFRMI setup time to DRETCLK falling edge.
DRETFRMI hold time from DRETCLK falling edge.
DRETCLK falling edge to DTBCK rising edge
tRETsu
tRETh
tRET1pd
tRET2pd
0.5
4
ns
ns
ns
ns
5
14
20
Delay from DRETCLK falling edge any telecom bus output.
7
67
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 35:Transmit Frame Parallel Timing
M HBCLKI
tTPF1pd
M HBCLKO
tTPF2pd
M HBDATA<7:0>
tTPF3pd
M FRM O
tTPFsu
tTPFh
M FRM I
Table 15: Transmit Frame Parallel Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MFRMI setup time to MHBCLKI rising edge.
MFRMI hold time from MHBCLKI rising edge.
MHBCLKI rising edge to MHBCLKO rising edge
MHBCLKI rising edge to MHBDATA<7:0>
MHBCLKI falling edge to MFRMO rising edge
tTPFsu
tTPFh
0
ns
ns
ns
6.5
7
tTPF1pd
tTPF2pd
tTPF3pd
18
25
23
9
8.5
ns
68
SXT6051 Test Specifications
Figure 36:Transmit Frame Serial Timing
M HICLK
tTSF1pd
tTSF2pd
tTSF3pd
tTSF4pd
tTSFh
M ICLK
M M SPPCKO
M FRM O
M HPOSD
M HNEGD
tTSFsu
M FRM I
Table 16: Transmit Frame Serial Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MFRMI setup time to MHICLK rising edge.
MFRMI hold time from MHICLK rising edge.
MHICLK rising edge to MICLK rising edge
MHICLK rising edge to MHPOSD and MHNEGD
MHICLK rising edge to MFRMO rising edge
tTSFsu
tTSFh
2
ns
ns
ns
ns
ns
1.5
5
tTSF1pd
tTSF4pd
tTSF3pd
15.5
18.5
5.5
7 1
6 2
18 1
15 2
MHICLK rising edge to MMSPPCKO rising edge
tTSF2d
9
22.5
ns
1. 50 pF load on output
2. 20 pF load on output
69
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 37:Receive Telecom Bus Timing
DHBCLK
tDCK1pd
DTBCLK
tDTBpd
DTBDATA<7:0>
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DTBTUGEN
Table 17: Receive Telecom Bus Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
DHBCLK falling edge to DTBCLK rising edge
tDCK1pd
tDTBdp
8
2
22
6
ns
ns
Delay from DTBCLK rising edge to any Telecom
bus output
Figure 38:ADM Mode Transmit Telecom Bus Timing
MTBCKI
MTBDATA<7:0>
tMTB2su
tMTB2h
MTBJ0J1EN
MTBPAYEN
MTBH4EN
MTBPAR
Table 18: ADM Mode Transmit Telecom Bus Timing Parameters
Parameter
Symbol
Min
Typ
Max Unit
Setup time for any telecom bus input to MTBCKI
falling edge
tMTB2su
0.5
ns
Hold time for any telecom bus input from MTBCKI
falling edge
tMTB2h
5
ns
70
SXT6051 Test Specifications
Figure 39:Terminal Mode Transmit Telecom Bus Timing
M HBCLKI
tM C K1pd
M TBCKO
tM TBpd
M TBJ0J1EN
M TBPAYEN
M TBH4EN
M TBTUGEN
tM TB1h
tM TB1su
M TBDATA<7:0>
M TBPAR
tM TBh
tM TB2su
M M FRM I
Table 19: Terminal Mode Transmit Telecom Bus Timing Parameters:
Parameter
Symbol
Min
Typ
Max
Unit
MHBCLKI rising edge to MTBCKO rising edge.
tMCK1pd
tMTBpd
3
8.5
15
ns
ns
Delay from MTBCKO rising edge to any telecom
bus output.
5.5
Setup time for any telecom bus input to MTBCKO
falling edge.
tMTB1su
tMTB1h
tMTB2su
tMTB2h
5
ns
ns
ns
ns
Hold time for any telecom bus input from MTB-
CKO falling edge.
-1
Setup time for MMFRMI to MTBCKO falling
edge.
5.5
-1.5
Hold time for MMFRMI from MTBCKO falling
edge.
71
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 40:Master Mode MSP Bus Timing
M HBCLKI
tC Kpd
M M SPPCKO
tM M SPpd
M M SPPJ0J1
M M SPPAUEN
M M SPPDATA<7:0>
DM SPPCKI
tD M SPsu
tD M SPh
DM SPPDATA<7:0>
DM SPPJ0J1
DM SPPAUEN
DM SPPSF
DM SPPSD
Table 20: Master Mode MSP Bus Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
ns
MHBCLKI edge to MMSPPCKO edge delay
tCKpd
5
3
15
7
MMSPPCKO rising edge to MMSPPDATA<7:0>,
MMSPPAYEN and MMSPPJ0EN
tMMSPpd
ns
ns
ns
DMSPPDATA<7:0>, DMSPPJ0EN and DMSPPAYEN setup
time to DMSPPCKI falling edge
tDMSPsu
tDMSPh
1.5
7
DMSPPDATA<7:0>, DMSPPJ0EN and DMSPPAYEN hold
time from DMSPPCKI falling edge
72
SXT6051 Test Specifications
Figure 41:Slave Mode MSP Bus Timing
DHBCLK
tD C Kpd
DM SPPCKO
tD M SPpd
DM SPPDATA<7:0>
DM SPPJ0J1
DM SPPAUEN
DM SPPSD
DM SPPDF
M M SPPCKI
M M SPPCKO
tM C Kpd
tM M SPsu
tM M SPh
M M SPPDATA<7:0>
M M SPPJ0J1
Table 21: Slave Mode MSP Bus Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
DHBCLK falling to DMSPPCKO rising
tDCKpd
DMSPPCKO rising edge to DMSPPDATA<7:0>, DMSP-
PAUEN, DMSPPJ0EN, DMSPPSD, DMSPPSF
tDMSPpd
3.5
9
ns
MMSPPCKI falling to MMSPPCKO falling
tMCKpd
6
16
ns
ns
MMSPPDATA<7:0> and MMSPPJ0EN setup time to
MMSPPCKI falling edge
tMMSPsu
0.5
MMSPPDATA<7:0> and MMSPPJ0EN hold time from
MMSPPCKI falling edge
tMMSPh
5.5
ns
73
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 42:Microprocessor Read Timing
MicroProcessor Read Timing (Intel Mode)
MicroProcessor Read Timing (Motorola Mode)
tSAR
tSAR
A<7:0>
A<7:0>
tHAR
tHAR
tSALR
tSALR
tHALR
tHALR
tVL
tVL
AS
AS
tSCR
tHCR
tSLR
CS
RW
tSRW B
tHRW B
tSLR
tVRD
RD
CS
tINTH
tSCR
tHCR
INT
E
tDDR
tZDR
tVRD
tINTH
INT
D<7:0>
tDDR
tZDR
tADR
tAAC
tAAC
tHDR
D<7:0>
tADR
tHDR
tAAC
tAAC
74
SXT6051 Test Specifications
Table 22: Microprocessor Data Read Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
A<7:0> setup time to active read
tSAR
12
1
-
-
-
-
ns
ns
1
A<7:0> hold time from inactive read
tHAR
2
A<7:0> setup time to latch
A<7:0> hold time from latch
Valid latch pulse width
1
2
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tSALR
2
tHALR
2
1.5
13
tVL
2
AS rising edge to active read setup
tSLR
RWB setup to active read
RWB hold from inactive read
CS setup to active read
tSRWB
tHRWB
tSCR
-1
2
2
2
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
CS hold from inactive read
tHCR
-
D<7:0> access time from valid address
(or AS whichever comes last for muxed AD bus)
D<7:0> bus driven from active read
tAAC
40
tDDR
tADR
tHDR
tZDR
6.5
-
-
-
-
-
-
19
-
ns
ns
ns
ns
ns
D<7:0> access time from active read
D<7:0> hold from inactive read
D<7:0> HIgh impedance from inactive read
Valid read pulse width
-
7
-
17.5
-
3
T+2
tVRD
3
Inactive read to inactive INT (due to reset on read
feature)
3*T + 12
-
4*T + 36
ns
tINTH
1. For non multiplexed Address and Data bus (AS tied high)
2. For multiplexed Address and Data bus (AS used as address latch enable)
3. T is the minimum cycle time of either MTBYCK or DTBYCK (typically 51.44 ns for STM1, 154.32 ns for STM0)
4. Consecutive reads from the on-chip RAM (“expected and “transmitted” J0 & J1 strings) must be separated by more than 4*T
75
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 43:Microprocessor Write Timing
M icroProcessor Write Timing (Intel M ode)
M icroProcessor Write Timing (M otorola Mode)
tSAW
tSAW
A<7:0>
A<7:0>
tHAW
tHAW
tSALW
tSALW
tHALW
tHALW
tVL
tVL
AS
AS
tSCW
tHCW
tSLW
tHRW B
C S
R W
tSLW
tSRW B
tHCW
tSCW
W R
IN T
C S
E
tINTH
tVW R
tVW R
tSDW
tINTH
tHDW
IN T
D <7:0>
tSDW
tHDW
D <7:0>
76
SXT6051 Test Specifications
Table 23: Microprocessor Data Write Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
A<8:0> setup time to active write
tSAW
6
4
-
-
-
-
ns
ns
1
A<8:0> hold time from inactive write
tHAW
2
A<8:0> setup time to latch
A<8:0> hold time from latch
Valid latch pulse width
1
2
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tSALW
2
tHALW
2
1.5
7
tVL
2
AS rising edge to active write setup
tSLW
RWB setup to active write
RWB hold from inactive write
CS setup to active write
tSRWB
tHRWB
tSCW
2
0.2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
CS hold from inactive write
D<7:0> setup to inactive write
D<7:0> hold from inactive write
Valid write pulse width
tHCW
tSDW
2
2.5
7
tHDW
3
T+2
tVWR
Inactive write to inactive INT (due to interrupt
masking)
tVWR
12
-
37
ns
1. For non multiplexed Address and Data bus (AS tied high)
2. For multiplexed Address and Data bus (AS used as address latch enable)
3. T is the minimum cycle time of either MTBYCK or DTBYCK (typically 51.44 ns for STM1, 154.32 ns for STM0)
4. There must be more than 4*T between the rising edge of a write to a BIP or REI error counter and the falling edge of the read to a BIP or REI
error counter
5. Consecutive writes to the on-chip RAM (“expected and “transmitted” J0 & J1 strings) must be separated by more than 4*T
77
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 44:Orderwire E1, F1 & E2, F2 & F3 Timing
xOW C
tO W pd
xOW BYC
RxOW
TPOW C
TOW C
tO W su
tO W h
TxOW
Table 24: Orderwire E1, F1 & E2, F2 & F3 Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
TOWC falling edge to TOWBYC
tOWpd
tOWsu
0.0
0.5
0.0
ns
ns
TROW, TDOW or TMOW setup time to falling
edge of TOWC
-124 (STM0)
-22 (STM1)
145 (STM0)
42 (STM1)
-0.5
TROW, TDOW or TMOW hold time from falling
edge of TOWC
tOWh
ns
ROWC falling edge to ROWBYC
tOWpd
tOWpd
ns
ns
ROWC falling edge to RROW, RDOW or RMOW
153 (STM0)
50 (STM1)
-0.5
155 (STM0)
52 (STM1)
0.5
TPOWC falling edge to TPOWBYC
tOWpd
tOWsu
ns
ns
TPOW1 or TPOW2 setup time to falling edge of
TPOWC
-126 (STM0)
-23 (STM1)
145 (STM0)
42 (STM1)
-0.2
TPOW1 or TPOW2 hold time from falling edge of
TPOWC
tOWh
ns
RPOWC falling edge to RPOWBYC
tOWpd
tOWpd
0.2
ns
ns
RPOWC falling edge to RPOW1 or RPOW2
153 (STM0)
51 (STM1)
154 (STM0)
52 (STM1)
78
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 45:Data Communication Channel Timing
RRDC
RM DC
tD C C pd
RRD
RM D
TRDC
TM DC
tD C C su
tD C C h
TRD
TM D
Table 25: Data Communication Channel Timing Parameters
Parameter
Symbol
Min
Typ
Max Unit
TRD setup time to falling edge of TRDC
tDCCSU
-127 (STM0)
-24 (STM1)
ns
TRD hold time from falling edge of TRDC
TMD setup time to falling edge of TMDC
TMD hold time from falling edge of TMDC
RRDC falling edge to RRD
tDCCH
tDCCSU
tDCCh
145 (STM0)
42 (STM1)
ns
ns
ns
-125 (STM0)
-23 (STM1)
145 (STM0)
42 (STM1)
tDCCPD
tDCCPD
154 (STM0)
51 (STM1)
155 (STM0) ns
52 (STM1)
RMDC falling edge to RMD
154 (STM0)
51 (STM1)
155 (STM0) ns
52 (STM1)
79
Test Specifications
Figure 46:Serial Overhead Interface Timing
Receive PO H & SO H Serial Interface
Transm it PO H Serial Interface
xOHCK
txO H pd
xOHEN
xOHFR
RxOH
tTPO H su
tTPO H h
TPOH
Transm it SO H Serial Interface
M M SPPCKO
tTSO H pd
TSOHEN
TSOHFR
tTSO H su
tTSO H h
TSOH
Table 26: Serial Overhead Interface Timing Parameters
Parameter
Symbol
Min
0.7
Typ
Max
Unit
TPOHCK rising edge to TPOHEN and TPOHFR
RSOHCK rising edge to RSOHEN, RSOHFR and RSOH
RPOHCK rising edge to RPOHEN, RPOHFR and RPOH
TPOH setup time to TPOHCK rising edge
txOHpd
txOHpd
txOHpd
tTPOHsu
tTPOHh
tTSOHpd
tTSOHsu
tTSOHh
4
9
3
ns
ns
ns
ns
ns
ns
ns
ns
3
0.5
17
TPOH hold time from TPOHCK rising edge
-6
MMSPPCKO falling edge to TSOHEN and TSOHFR
TSOH setup time to MMSPPCKO falling edge
TSOH setup time from MMSPPCKO falling edge
2.5
11.5
-4
8.5
80
l
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 47:BIP Alarm output Timing
DM SPPCKO
tB12pd
B1OUT
B2OUT
RPOHCK
tB3pd
B3OUT
Table 27: BIP Alarm output Timing Parameters
Parameter
Symbol
tB12pd
tB3pd
Min
Typ
Max
Unit
DMSPPCKO rising edge to B1OUT and B2OUT
RPOHCK rising edge to B3OUT
5.5
3
15
11
ns
ns
81
Microprocessor Interface & Register Description
MICROPROCESSOR INTERFACE & REGISTER DESCRIPTION
A Low on the E input initiates both cycles. The E input is
Microcontroller Interface
connected to the E output from the Motorola microproces-
This section contains a description of the asynchronous
sor and is typically a 50% duty cycle waveform with a fre-
microprocessor interface. A microprocessor should be con-
quency derived from the microprocessor clock.
nected to the SXT6051 for reading and writing data via the
microprocessor interface pins.
Both cycles require the CS pin to be Low and the micropro-
cessor to drive the A<7:0> address pins. In the case of the
write cycle, the microprocessor is also required to drive the
DATA <7:0> data pins. In the case of the read cycle, the
SXT6051 drives the DATA<7:0> data pins.
The microprocessor interface is a generic asynchronous
interface, including an address bus (A<7:0>), data bus
(DATA<7:0>) and handshaking pins (WR/RW, RD/E, CS,
and AS). The MCUTYPE input pin indicates the type of
microprocessor interface used – Intel or Motorola. There is
also an INT output pin that indicates unmasked active inter-
rupts microprocessor to the microprocessor.
When a multiplexed data/address bus is used, the falling
edge of the AS input latches the address provided on the
muxed bus (the muxed bus will be connected to both the
A<7:0> and DATA<7:0>). If the address and data are not
multiplexed the AS pin should be tied High.
Intel interface
The Intel interface is indicated by driving the MCUTYPE
input pin High. It uses the WR/RW input pin as WR and the
RD/E input pin as RD.
Interrupt Handling
A read cycle is indicated to the SXT6051 by the micropro-
cessor forcing a Low on the RD pin with the WR pin held
High.
Interrupt Sources
There are three types of interrupt sources:
A write cycle is indicated to the SXT6051 by the micropro-
cessor forcing a Low on the WR pin with the RD pin held
High.
1. Status change of a monitoring process: For example,
the SXT6051 monitors the incoming STM frame for
the correct framing pattern and updates the OofSt and
LofSt status bits to indicate presence or absence of Out
Of Frame and Loss Of Frame conditions. When the
value of these status bits change an interrupt can be
generated.
Both cycles require the CS pin to be Low and the micropro-
cessor to drive the A<7:0> address pins. In the case of the
write cycle, the microprocessor is also required to drive the
DATA<7:0> data pins. In the case of the read cycle, the
SXT6051 drives the DATA<7:0> data pins.
2. Change in the contents of an overhead byte register:
For example, the SXT6051 stores the incoming K1 (as
well as others) Section Overhead byte in register 00H.
When the value of the contents in this register changes
an interrupt can be generated.
When a multiplexed data/address bus is used, the falling
edge of the AS input latches the address provided on the
muxed bus (the muxed bus will be connected to both the
A<7:0> and DATA<7:0>). If the address and data are not
multiplexed the AS pin should be tied High.
3. Counter overflows: For example, the SXT6051
monitors the B1 overhead byte for bit interleaved
parity calculation errors. These errors are recorded in
the B1 error counter (registers 46H and 45H). If this
register pair overflows, an interrupt can be generated.
Motorola interface
The Motorola interface is indicated by driving the MCU-
TYPE input pin Low. It uses the WR/RW input pin as RW
and the RD/E input pin as E.
Interrupt Enables
In order for an interrupt source to affect the state of the
INT output pin its associated interrupt enable bit must
be SET. The setting (whether 0 or 1) of the interrupt
enables does not affect the updating of the status reg-
isters, the overhead byte registers, interrupt registers or
the counters.
A read cycle is indicated to the SXT6051 by the micropro-
cessor forcing a High on the RW pin. A write cycle is indi-
cated to the SXT6051 by the microprocessor forcing a Low
on the RWR pin.
82
l
Microprocessor Interface & Register Description
Assuming the interrupt enable for a particular interrupt
source is SET and the interrupt source is active, the
input pin will be active.
For this reason we encourage programmers to SET the
AlmUpdDsbl bit before accessing the status registers
during alarm processing. This effectively locks out
internal processes that wish to access the status and
interrupt bits during the time that the microprocessor is
accessing these bits. After the microprocessor is done
accessing the status registers it should CLEAR the
AlmUpdDsbl bit so that internal processes may again
update the status and interrupt bits.
Interrupt Clearing
The primary difference between each of interrupt
types is the way its interrupt bits are cleared. In the dis-
cussion below it is assumed that the example interrupt
sources have their interrupt enable bits SET.
1. Status change interrupt sources have their interrupt
bits cleared when their status is read. For example, say
the OofSt bit changes from zero to one (in frame to out
of frame). Its interrupt bit (Oof, A0H<bit 0>) is SET
by this event. When the microprocessor reads the
register (C0H) containing the OofSt bit its interrupt bit
will be CLEARED. If the OofSt bit subsequently
changes from one to zero (out of frame to in frame)
again its interrupt bit is SET by this event and then
CLEARED when the status is read.
C2, K3, K2, K1 and S1 Receive Byte
Registers Access
The BytChgUpdDsbl is SET to disable updates to
overhead byte registers when a particular overhead
byte register’s interrupt is active. For example, if both
RcvK1Chg interrupt (see register A1H) and BytCh-
gUpdDsbl (see register 50H) are SET, updates to
RcvK1 (see register 00H) will be disabled until RcvK1
is read by the microprocessor. This allows a rapidly
fluctuating incoming K1 byte value to be captured dur-
ing system debug.
It should be noted that updates to status bits are not
affected by the interrupt bit state. For example, the
OofSt bit could change from a one to zero (generating
an interrupt) and then before the microprocessor reads
OofSt it could change back to one (this would have no
affect on its interrupt bit since it would already be
SET). When the microprocessor reads the OofSt bit it
would read a one.
Note that this is also true for the K1 and K2 bytes
received in the protection bus in a 1+1 Master config-
uration.
Counter Reading
Counters are read by first buffering their contents and then
reading the buffer. They can be individually buffered or
globally buffered. They are globally buffered by writing to
register BfrAllCntrs (54H). They are individually buffered
by writing to the most significant byte of a particular
buffer. After buffering the counter the contents of the
buffer is read at the address specified in the register defini-
tion.
2. Interrupt sources associated with the contents of
overhead byte registers, have their interrupt bits
cleared when the particular overhead byte register is
read. For example, the incoming K1 overhead byte is
stored (after filtering) in the RcvK1 register (register
00H). If the value of this register changes the
RcvK1Chg bit is SET. It will clear when the RcvK1
register is read.
See the following section for discussion concerning
updates to an overhead byte register when its associ-
ated interrupt is active.
For example, to read the contents of the B1 counter a write
to register 46H (or 54H) is required (this write will clear the
B1 overflow interrupt bit B1OvrFlw, A0H<bit 7> if it is
SET). The contents of the buffer can now be read by read-
ing registers 45H & 46H (in no particular order).
3. Interrupt sources associated with counter overflows,
have their interrupt bits cleared when the particular
overflowing counter is buffered. See the following
section for description of counter reading.
Status Registers Access
Due to the asynchronous nature of the microprocessor
interface and timing differences during interrupt bit
updates, it is possible that a status bit change can fail
to SET its associated interrupt bit if the AlmUpdDsbl
bit is not SET during a read of the status registers by
the microprocessor. This situation is very difficult to
achieve however, it can happen.
83
l
SXT6051 STM-1/0 SDH Overhead Terminator
Register Address Map
The following notations and definitions are used in the register descriptions.
RO
Read Only. Unless otherwise stated in the register description, writes have no affect. Note that
for some counter registers, a write to the MSByte resets the counter.
WO
Write Only. Reads return undefined values.
R/W
Read/Write. A register (or bit) with this attribute can be read and written.
Reserved Bits
Some of the registers contain reserved bits. Software must deal correctly with reserved fields.
For reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. In some cases, software must program reserved bit
positions to a particular value. This value is defined in the individual bit descriptions.
Default
When the SXT6051 is reset, it sets its registers to predetermined default states. The default
state represents the minimum functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system configuration. It is the responsibility
of software to properly determine the operating parameters, and optional system features that
are applicable, and to program the SXT6051 registers accordingly.
Default = X
AIS
Undefined
Alarm Signal Indication
High Order Path OverHead
Multiplexer Section OverHead
OverHead Terminator
HPOH
MSOH
OHT
RSOH
RST
Regenerator Section OverHead
Regenerator Section Termination
84
SXT6051 Microprocessor Interface & Register Description
Table 28: Register Address Map (Sheet 1 of 4)
Address Mnemonic Register Name
Global Registers
Type
Page #
50H
OCR1
Operational Configuration 1
Operational Configuration 2
Chip ID Number
R/W
R/W
RO
89
90
91
91
51H
52H
54H
OCR2
CHIP_ID
BUF_ACNTS
Buffer All Counters
WO
Receive Regenerator Section Termination Registers
40H
R_RSTC1
R_RSTC2
LOF_LMN
OOF_ECNT
Receive RST Configuration 1
Receive RST Configuration 2
Loss of Frame L, M, and N Configuration
Out Of Frame Event Counter
R/W
R/W
R/W
RO
92
93
93
94
94
47H
41–42H
44–43H
46–45H
B1_ERRCNT
B1 Error Counter
RO
Receive Regenerator and Multiplexer Section Termination Registers
0EH
J0_RSTR_C
J0 Expected String Control
R/W
95
95
96
96
96
96
97
97
0FH
J0_RSTR_D
WINSZ_SB2
CWIN_SB2
E#_EXCWIN
WINSZ_C2
CWIN_CB2
E#_NEXCWIN
J0 Expected String Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1C–1BH
1DH
Window Size for Setting ExcB2ErrSt
Consecutive Windows for Setting ExcB2ErrSt
Number of Errs/Win for Excessively Errored Window
Window Size for Clearing ExcB2ErrSt
Consecutive Windows for Clearing ExcB2ErrSt
1EH
16–15H
17H
18H
Number of Errs/Win for Non-Excessively Errored Win-
dow
11–10H
14–12H
0A–09H
0D–0BH
00H
B2_BLKCNT
B2_BIPCNT
MR_BLKCNT
MR_BIPCNT
R_K1
B2 Block Error Counter
B2 BIP Error Counter
MST REI Block Error Counter
MST REI BIP Error Counter
Received K1 byte
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
97
97
98
98
98
98
98
99
99
99
01H
R_K2
Received K2 Byte
02H
R_S1
Received S1 byte
03H
R_NU1_8
R_NU1_9
R_NU2_8
Received Nu1_8 byte
Received Nu1_9 byte
Received Nu2_8 byte
04H
05H
85
SXT6051 STM-1/0 SDH Overhead Terminator
Table 28: Register Address Map (Sheet 2 of 4)
Address
06H
Mnemonic
Register Name
Received Nu2_9 byte
Type
Page #
R_NU2_9
R_NU9_8
R_NU9_9
RO
RO
RO
99
99
99
07H
08H
Received Nu9_8 byte
Received Nu9_9 byte
Receive Multiplexer Section Protection Registers
20H
21H
22H
23H
R_MSP_C
Receive MSP Configuration
R/W
R/W
RO
100
100
101
101
R_MSP_OP
R_PROTK1
R_PROTK2
Receive MSP Operational
Received K1 byte on Protection Bus from Slave
Received K2 byte on Protection Bus from Slave
RO
Receive Multiplexer Section Adaptation Registers
90H
R_MSA_C
Receive MSA Configuration
R/W
RO
101
102
102
92–91H
94–93H
R_AU_NCNT
R_AU_PCNT
Receive Negative AU Pointer Justification Event Counter
Receive Positive AU Pointer Justification Event Counter
RO
Receive HighOrder Path Termination Registers
80H
R_HPT_C1
R_HPT_C2
J1_RSTR_C
J1_RSTR_D
EXP_C2
Receive HPT Configuration 1
Receive HPT Configuration 2
J1 Expected String Control
J1 Expected String Data
Expected C2 byte
R/W
R/W
WO
R/W
R/W
RO
103
104
105
105
105
105
105
106
106
106
81H
8AH
8BH
82H
83H
R_C2
Received C2 byte
84H
R_K3
Received K3 byte
RO
85H
R_HPT_RDI
B3_ECNT
Received HPT RDI Bits
B3 Error Event Counter
RO
87–86H
89–88H
RO
HPTREI_CNT
HPT REI Counter
RO
Transmit Regenerator and Multiplexer Section Termination Registers
30H
1AH
60H
61H
62H
63H
3AH
3BH
T_RMST_OP1
T_RMST_OP2
T_SC1_SOH
T_SC2_SOH
T_SC3_SOH
T_SC4_SOH
J0_TSTR_C
JO_TSTR_D
Transmit RMST Operational 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
107
108
109
110
111
112
113
114
Transmit RMST Operational 2
Transmit Source Configuration 1 for SOH bytes
Transmit Source Configuration 2 for SOH bytes
Transmit Source Configuration 3 for SOH bytes
Transmit Source Configuration 4 for SOH bytes
J0 Transmit String Control
J0 Transmit String Data
86
SXT6051 Microprocessor Interface & Register Description
Table 28: Register Address Map (Sheet 3 of 4)
Address
31H
Mnemonic
Register Name
Type
Page #
MP_TNU1_8
MP_TNU1_9
MP_TNU2_8
MP_TNU2_9
MP_TNU9_8
MP_TNU9_9
MP_TK1
Microprocessor Provided Transmit Nu1_8 Byte
Microprocessor Provided Transmit Nu1_9 Byte
Microprocessor Provided Transmit Nu2_8 Byte
Microprocessor Provided Transmit Nu2_9 Byte
Microprocessor Provided Transmit Nu9_8 Byte
Microprocessor Provided Transmit Nu9_9 Byte
Microprocessor Provided Transmit K1 Byte
Microprocessor Provided Transmit K2 Byte
Microprocessor Provided Transmit S1 Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
114
114
114
114
115
115
115
115
115
32H
33H
34H
35H
36H
37H
38H
39H
MP_TK2
MP_TS1
Transmit Multiplexer Section Adaptation Registers
E3–E2H
E5–E4H
T_AU_NCNT
Transmit Negative AU Pointer Justification Event
Counter
RO
RO
116
116
T_AU_PCNT
Transmit Positive AU Pointer Justification Event Counter
Transmit High Order Path Termination Registers
70H
71H
72H
73H
75H
76H
T_SC_HPOH
T_HPT_C
Transmit Source Configuration for HPOH bytes
Transmit HPT Configuration
R/W
R/W
R/W
R/W
R/W
R/W
117
118
119
119
120
120
MP_TC2
Microprocessor Provided Transmit C2 Byte
Microprocessor Provided Transmit K3 Byte
J1 Transmit String Control
MP_TK3
J1_TSTR_C
J1_TSTR_D
J1 Transmit String Data
Interrupt Source Registers
A0H
A1H
IS_RG
Receive Regenerator Section Interrupt Source
RO
RO
121
121
IS_RGMUX
Receive Regenerator and Multiplexer Section Interrupt
Source
A2H
A3H
A4H
A5H
A6H
E0H
D1H
IS_MUX
IS_PROT
IS_A_HPT
IS_HPT
Receive Multiplexer Section Interrupt Source
Receive Protection Section Interrupt Source
Receive Adaptation and HPT Interrupt Source
Receive HPT Interrupt Source
RO
RO
RO
RO
RO
RO
RO
122
122
123
123
124
124
125
IS_RETIME
IS_XMT
Receive Retiming Interrupt Source
Transmit Interrupt Source
IS_GLOB
Global Interrupt Source
87
SXT6051 STM-1/0 SDH Overhead Terminator
Table 28: Register Address Map (Sheet 4 of 4)
Address
Mnemonic
Register Name
Type
Page #
Interrupt Enable Registers
B0H
IE_RG
Receive Regenerator Section Interrupt Enable
R/W
R/W
126
126
B1H
IE_RGMUX
Receive Regenerator and Multiplexer Section Interrupt
Enable
B2H
B3H
B4H
B5H
B6H
E1H
IE_MUX
IE_PROT
IE_A_HPT
IE_HPT
Receive Multiplexer Section Interrupt Enable
Receive Protection Section Interrupt Enable
Receive Adaptation and HPT Interrupt Enable
Receive HPT Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
126
126
126
126
126
126
IE_RETIME
IE_XMT
Receive Retiming Interrupt Enable
Transmit Interrupt Enable
Status Registers
C0H
C1H
C3H
C4H
C5H
D0H
S_RG
Receive Regenerator Section Status
Receive Regenerator and Multiplexer Section Status
Receive Protection Section Status
Receive Adaptation and HPT Status
Receive HPT Status
RO
RO
RO
RO
RO
RO
127
127
128
128
129
130
S_RGMUX
S_PROT
S_A_HPT
S_HPT
S_AIS_PROT
Receive AIS and Protection Switch Status
88
SXT6051 Microprocessor Interface & Register Description
Global Registers
OCR1—Operational Configuration 1 (50H)
Configures global configuration parameters for chip operation.
Bit
Name
Formless
Description
Type
Default
7
Select I/O frame data stream interface. Must be set to 0 in
R/W
0
STM-1 mode.
0 = Serial
1 = Parallel
6
5
LnCodeSel
StmMode
Line interface coding (serial interface only).
R/W
RO
0
X
0 = B3ZS
1 = NRZ
STMMODE pin input setting.
0 = STM-0
1 = STM-1
4:2
OpCnfg<2:0>
The OHT chip can be configured to have the following
operational modes:
R/W
100
000 = Repeater
001 = Add/Drop Multiplexor (ADM) - No Protection
010 = 1+1 ADM Protection Main/Master
011 = 1+1 ADM Protection Slave
100 = Terminal - No Protection
101 = 1+1 Terminal Protection Main/Master
110 = 1+1 Terminal Protection Slave
1:0
ScrmblCnfg<1:0>
If input pin SCRAMSEL is 0 these indicate the scrambler
length. When SCRAMSEL is 1 the scrambler is disabled.
R/W
10
00 = Disable scrambler
01 = 2e13
10 = 2e7
11 = 2e11
89
SXT6051 STM-1/0 SDH Overhead Terminator
OCR2—Operational Configuration 2 (51H)
Bit
Name
MasIntEn
Description
Type
Default
7
This bit enables/disables the chip interrupt pin
0 = Disable interrupt pin
R/W
0
1 = Activate interrupt pin when there are unmasked active
interrupts
6
AlmUpdDsbl
This bit enables/disables updates to status registers when a
status alarm in the same register has an active interrupt. This
pin is used during interrupt servicing. In the interrupt service
routine the software should 1) set this bit, 2) access status bits
and 3) clear this bit. This guarantees that interrupts due to sta-
tus changes will not be missed.
R/W
0
0 = Enable status updates when alarm interrupt is active
1 = Disable status updates when alarm interrupt is active
5
BytChgUpdDsbl This bit enables/disables received byte register updates when a
register’s byte change interrupt is active. This bit is generally
used for diagnostics. For example, if the received K2 byte
were rapidly toggling the values that it is toggling between
could be captured by setting this bit.
R/W
0
0 = Enable received byte register updates when byte change
interrupt is active
1 = Disable received byte register updates when byte change
interrupt is active
4
CntrTest
This bit should always be set to 0 during normal operation. It
allows faster testing of the overflow interrupt functionality
during simulation.
R/W
0
0 = Normal operation
1 = Set overflow count: B1 counter 7; B2 bit counter 31; B2
block counter 3; M1 REI bit counter 31; M1 REI block
counter 3; B3 bit/ block counters 7; G1 REI bit/block
counters 7
3
RcvRetimDsbl
Allows re-timing to be done on the receive side (re-timing is
always done on the transmit side). If re-timing is done on the
receive side (i.e., RcvRetimDsbl = 0) the MSOH & RSOH
bytes will not be passed through. They are regenerated on the
transmit side. This is used when system requirements dictate
that the receive side telecom bus timing be synchronous with a
local clock.
R/W
1
0 = Enable receive side re-timing.
1 = Disable receive side re-timing.
90
SXT6051 Microprocessor Interface & Register Description
Bit
Name
IgnoreJ0
Description
Type
Default
2
Ignore J0 bytes. The receive J0 string cannot result in TIM
(Trace Identifier Mismatches) or J1 CRC alarms.
R/W
0
0 = Ignore J0 byte
1 = Monitor J0 bytes.
Reserved
1
0
Reserved
IOBusEn
This bit allows the enabling/disabling of the all chip I/O bus-
ses except the microprocessor interface. This is useful when
changing the configuration bits OpCnfg<2:0> in register 50H.
If the I/O busses are not disabled during configuration
changes, the chip could be damaged.
R/W
0
0 = Disable I/O busses
1 = Enable I/O busses
CHIP_ID—Chip ID Number (52H)
This register can only be read. It is used to identify the version of the chip.
Bit
Name
Description
Type
Default
7:0
ChipID<7:0>
Chip Identification: This field contains the Chip Identifica-
RO
01H
tion value.
BUF_ACNTS—Buffer All Counters (54H)
A write to this location causes all of the counters to be loaded into buffers and then cleared. The contents of an individual
counter buffer can then be read at the addresses specified for the counters in this document. Counters can be individually
buffered by writing to the specified MSByte of the counter of interest.
Bit
Name
Description
Type
Default
7:0
BfrAllCntrs<7:0>
WO
XXH
91
SXT6051 STM-1/0 SDH Overhead Terminator
Receive Regenerator Section Termination Registers
R_RSTC1—Receive RST Configuration 1 (40H)
Configures Regenerator Section Termination parameters of the chip
Bit
Name
Description
Type
Default
7
RstClkLosEn
Enable/Disable automatic switching to blue clock during Loss of
Signal condition.
R/W
1
0 = Disable automatic clock switch because of LOS
1 = Enable automatic clock switch because of LOS
6
5
RstAisLofEn
RstAisLosEn
RstAisFrc
Enable/Disable automatic AIS generation from the RST section
to the MST section because of a Loss of Frame condition.
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0 = Disable AIS generation during LOF
1 = Enable AIS generation during LOF
Enable/Disable automatic AIS generation from the RST section
to the MST section because of a Loss of Signal condition.
0 = Disable AIS generation during LOS
1 = Enable AIS generation during LOS
4
Force AIS generation from the RST section to the MST section
via software.
0 = Disable
1 = Enable
3
RstAisTimEn
LosItg<1:0>
Enable/Disable automatic AIS generation from the RST section
to the MST section because of an active J0MsMtchSt.
0 = Disable AIS generation during active J0MsMtchSt
1 = Enable AIS generation during active J0MsMtchSt
This field configures LOS alarm filtering.
0X =No filtering
2:1
10 = Weak LOS filtering. When IOFrmSel selects Serial, the
LOS condition must be maintained for a total of 128 clocks;
when set to Parallel LOS must be present for 16 clocks.
11 = Strong LOS filtering. When IOFrmSel selects Serial the
LOS condition must be maintained for a total of 4096
clocks; when set to Parallel LOS must be present for 512
clocks.
92
SXT6051 Microprocessor Interface & Register Description
Bit
Name
Description
Type
Default
0
CnfgFrmAcq
Modifies the frame acquisition algorithm as it relates to the NDF
bits. Only relevant in STM-0. STM-1 mode always uses Normal
Acquisition.
R/W
0
0 = Normal Acquisition: During acquisition check 2 consecu-
tive frames for identical NDF and correct frame word. De-
synchronization caused by 4 consecutive incorrect frame
words.
1 = Robust Acquisition: During acquisition check 5 consecu-
tive frames for identical NDF while also checking for 2 con-
secutive correct frame words. De-synchronization caused
by 4 consecutive incorrect frame words OR 8 consecutive
frames not having identical NDF bits.
R_RSTC2—Receive RST Configuration 2 (47H)
Configures Regenerator Section Termination parameters of the chip
Bit
Name
Description
Type
Default
7:1
0
Reserved
X
0
CnfgB1Cntr
Configure B1 error counter to be updated using bit errors or
block errors
R/W
0 = Bit error
1 = Block errors
LOF_LMN—Loss of Frame L, M, & N Configuration (41–42H)
41H=Bits<15:8>, 42H=Bits<7:0> (Byte access only)
This register sets the Loss Of Frame detection parameters. Address 41H is the upper byte and 42H the lower byte.
Bit
Name
Description
Type
Default
15
Reserved
L<4:0>
14:10
After an OOF event is observed (indicated by OofSt = C0H<0> = 1),
this represents the L parameter. L+1 is the number of frames having
OofSt = 1 status that result in entering the LOF state (indicated by an
LofSt = C0H<1> = 1).
R/W
00000
9:5
4:0
M<4:0>
N<4:0>
After an OOF event is observed (indicated by OofSt = C0H<0> = 1),
this represents the M parameter. M+1 is the number of frames having
OofSt = 0 that result in re-entering the NORM state before entering
the LOF state.
R/W
R/W
00000
00000
After an LOF event is observed (indicated by an LofSt = C0H<1> =
1), this represents the N parameter. N+1 is the number of frames hav-
ing OofSt = 0 that result in re-entering the NORM state from the LOF
state (indicated by an LofSt = C0H<1> = 0).
93
SXT6051 STM-1/0 SDH Overhead Terminator
OOF_ECNT—Out Of Frame Event Counter (44–43H)
44H=Bits<15:8>, 43H=Bits<7:0> (Byte access only)
This counter increments each time an OOF error event is detected. A write to the MSB of the counter (44H) causes the
entire counter to be loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Reserved
OofCnt<12:0>
Description
Type
Default
15:13
12:0
RO
RO
This field indicates the OOF error count value.
00H
B1_ERRCNT—B1 Error Counter (46–45H)
46H=Bits<15:8>, 45H=Bits<7:0> (Byte access only)
This counter increments each time a B1 error event is detected. A write to the MSB of the counter (46H) causes the entire
counter to be loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Description
Type
Default
15:0
B1Cnt<15:0>
This field indicates the B1 error count value.
RO
00H
94
Microprocessor Interface & Register Description
1. Set ExpcJ0Acc bit to 1. This allows the microprocessor
Receive Regenerator and
Multiplexer Section
Termination Registers
to be in control of incrementing the J0 string pointer.
2. Reset the string pointer. A 0 to 1 transition in the
RstExpcJ0StrgPntr bit does this. This pointer
identifies which byte in the J0 string will be accessed.
Resetting it means that the first byte of the string will
be accessed. It is automatically incremented when a
read or write accesses the string data register.
J0_RSTR_C—J0 Expected String
Control (0EH)
These registers allow the configuring of the expected J0
string received in the incoming SOH. This is outlined
below:
3. Configure (write) the J0 string that is to be transmitted
into the J0 expected string data register 0FH.
4. Reset the string pointer and read back the configured
string value and verify.
5. Reset the string pointer and set ExpcJ0Acc to 0.
Bit
Name
Reserved
ExpcJ0Acc
Description
Type
Default
7:2
1
This bit allows microprocessor read/write operations to
be in control of incrementing the string pointer. This
functionality is normally used only during initializa-
tion, to program/verify the string value configured by
the microprocessor.
WO
0
0 = Normal operation. Internal hardware process that
is comparing the configured J1 string with the
incoming J1 string increments the string pointer.
1 = The microprocessor read/write operations incre-
ment the string pointer.
Bit
Name
RstExpcJ0StrgPntr
Description
Type
Default
0
A transition from 0 to 1 in this bit resets the J1 expected
string pointer.
WO
0
J0_RSTR_D—J0 Expected String Data (0FH)
Bit
Name
Description
Type
Default
7:0
ExpcJ0StrgData<7:0>
Bits <7:0> represents the data value.
R/W
00H
95
SXT6051 STM-1/0 SDH Overhead Terminator
WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH)
1CH=Bits<15:8>, 1BH=Bits<7:0> (Byte access only)
Bit
Name
Description
Type
Default
15:11
10:0
Reserved
ExcB2SetWinSz<10:0>
R/W
R/W
Number of frames per window =
8*(ExcB2OnWinSz<10:0>+1)
00H
CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH)
Bit
Name
Description
Type
Default
7
Reserved
ExcB2SetWinNum<6:0>
6:0
Number of consecutive windows that must be
excessively errored in order to set the ExcB2ErrSt
bit (register C1H). Note: If ExcB2ErrSt is clear and
this register is set to zero, ExcB2ErrSt will never
be set.
R/W
00 0011
E#_EXCWIN—Number of Errs/Win for Excessively Errored Window (1EH)
This register configures the minimum number of errors that a window must contain to be considered an excessively errored
window. Note: Setting this register to zero will cause every window to be considered an excessively errored window.
Bit
Name
Description
Type
Default
7:0
ExcB2Min<7:0>
R/W
2BH
WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H)
16H=Bits<15:8>, 15H=Bits<7:0> (Byte access only)
Bit
Name
Description
Type
Default
15:11
10:0
Reserved
ExcB2ClrWinSz<10:0>
R/W
R/W
Number of frames per window =
8*(ExcB2OnWinSz<10:0>+1).
00H
96
SXT6051 Microprocessor Interface & Register Description
CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H)
Bit
Name
Label
Type
Default
7
Reserved
ExcB2ClrWinNum<6:0>
6:0
Number of consecutive non-excessively errored
windows needed for the excessive error condi-
tion to be cleared. Note: If the ExcB2ErrSt bit
(register C1H) is set and this register is set to
zero, bit ExcB2ErrSt will never be cleared.
R/W
07H
E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored Window
(18H)
This register configures the maximum number of errors that a window can contain and be considered a NonExcessively
Errored window. Note: Setting this register to zero will cause every window to be considered a non-excessively errored
window.
Bit
Name
Description
Type
R/W
Default
7:0
ExcB2Max<7:0>
08H
B2_BLKCNT—B2 Block Error Counter (11–10H)
11H=Bits<15:8>, 10H=Bits<7:0> (Byte access only)
This counter increments each time a B2 block error event is detected. A write to the MSByte of the counter (register 11H)
causes the entire counter to be loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Reserved
B2BlkCnt<12:0>
Description
Type
Default
15:13
12:0
B2 Block Error Count Value.
RO
00H
B2_BIPCNT—B2 BIP Error Counter (14–12H)
14H=Bits<23:16>, 13H=Bits<15:8>, 12H=Bits<7:0> (Byte access only)
This counter increments each time a B2 BIP error event is detected. A write to the MSByte of the counter (register 14H)
causes the entire counter to be loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Reserved
B2BipCnt<17:0>
Description
Type
Default
23:18
17:0
B2 BIP Error Count Value.
RO
00H
97
SXT6051 STM-1/0 SDH Overhead Terminator
MR_BLKCNT—MST REI Block Error Counter (0A–09H)
0AH=Bits<15:8>, 09H=Bits<7:0> (Byte reads only)
Every frame for which the value of MST REI bits (M1<7:0>) is non-zero, this counter is incremented. A write to the
MSByte of the counter (register 0AH) causes the entire counter to be loaded into a buffer and then cleared. The contents
of the buffer can then be read.
Bit
Name
Reserved
MstReiBlkCnt<12:0>
Description
Type
Default
15:13
12:0
RO
00H
MR_BIPCNT—MST REI BIP Error Counter (0D–0BH)
0DH=Bits<23:16>, 0CH=Bits<15:8>, 0BH=Bits<7:0> (Byte access only)
Every frame that is the value of MST REI bits (M1<7:0>) is added to this counter. A write to the MSByte of the counter
(register 0DH) causes the entire counter to be loaded into a buffer and then cleared. The contents of the buffer can then be
read.
Bit
Name
Reserved
MstReiBipCnt<17:0>
Description
Type
Default
23:18
12:0
RO
00H
R_K1—Received K1 byte (00H)
Value of the last 3 consecutively received K1 bytes having the same setting.
Bit
Name
Description
Type
Default
7:0
RcvK1<7:0>
RO
00H
R_K2—Received K2 Byte (01H)
Value of the last 3 consecutively received K2 bytes having the same setting.
Bit
Name
Description
Type
Default
7:0
RcvK2<7:0>
RO
00H
R_S1—Received S1 byte (02H)
Value of the last 3 consecutively received S1 bytes having the same setting.
Bit
Name
Description
Type
Default
7:0
RcvS1<7:0>
RO
00H
98
SXT6051 Microprocessor Interface & Register Description
R_NU1_8—Received Nu1_8 byte (03H)
National Use byte (see Figure 10) located in row 1 column 8 in the RSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu1_8<7:0>
RO
XXH
R_NU1_9—Received Nu1_9 byte (04H)
National Use byte (see Figure 10) located in row 1 column 9 in the RSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu1_9<7:0>
RO
XXH
R_NU2_8—Received Nu2_8 byte (05H)
National Use byte (see Figure 10) located in row 2 column 8 in the RSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu2_8<7:0>
RO
XXH
R_NU2__9—Received Nu2_9 byte (06H)
National Use byte (see Figure 10) located in row 2 column 9 in the RSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu2_9<7:0>
RO
XXH
R_NU9_8—Received Nu9_8 byte (07H)
National Use byte (see Figure 10) located in row 9 column 8 in the MSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu9_8<7:0>
RO
XXH
R_NU9_9—Received Nu9_9 byte (08H)
National Use byte (see Figure 10) located in row 9 column 9 in the MSOH (STM-1 only).
Bit
Name
Description
Type
Default
7:0
Nu9_9<7:0>
RO
XXH
99
SXT6051 STM-1/0 SDH Overhead Terminator
Receive Multiplexer Section Protection Registers
R_MSP_C—Receive MSP Configuration (20H)
Bit
Name
Reserved
Description
Type
Default
7:3
2
AisOnExcB2En
Enable the insertion of AIS from MST section towards MSA
section and generation of SF when ExcB2ErrSt bit (C1H<3>)
is set.
R/W
1
0 = Active ExcB2ErrSt will not cause AIS to be transmitted.
1 = Active ExcB2ErrSt will cause AIS to be transmitted.
1
0
MstAisEn
Enable/Disable automatic AIS generation from the MST sec-
tion to the MSA section (see GenMstAisSt bit (D0H register
<bit 6>) for AIS generation logic).
R/W
R/W
1
0
0 = Disable
1 = Enable
MstAisFrc
Force AIS generation from the MST section to the MSA sec-
tion via software.
0 = Disable
1 = Enable
R_MSP_OP—Receive MSP Operational (21H)
Bit
Name
Description
Type
Default
7:2
1
Reserved
SigDegrade
For both MASTER and SLAVE configurations this value is
reflected at the SD output pin. When configured as a SLAVE the
value is also reflected at the DMSPPSD output pin. It is updated
by the microprocessor.
R/W
0
0 = No defect
1 = Defect
0
ProtSw
Protection switch setting. When configured as a MASTER the
value of this bit is reflected in ProtSwSt (see D0H<0>). When
configured as a SLAVE this bit has no action.
R/W
1
0 = Protect
1 = No Protect
100
SXT6051 Microprocessor Interface & Register Description
R_PROTK1—Received K1 byte on Protection Bus from Slave (22H)
.
Bit
Description
Type
Default
7:0
ProtK1<7:0>
Bits <7:0> represents the K1 byte received on the protection bus.
RO
00H
R_PROTK2—Received K2 byte on Protection Bus from Slave (23H)
.
Bit
Description
Type
Default
7:0
ProtK2<7:0>
Bits <7:0> represents the K2 byte received on the protection bus.
RO
00H
Receive Multiplexer Section Adaptation Registers
R_MSA_C—Receive MSA Configuration (90H)
Bit
Description
Type
Default
7:3
2
Reserved
RcvMsaAisEn
Enable/Disable automatic AIS generation from the MSA sec-
tion to the HPT section. (see GenMsaAisSt bit (D0H<bit 5>)
for AIS generation logic).
R/W
0
0 = Disable
1 =Enable
1
0
RcvMsaAisFrc
AuPntrSSEn
Force AIS generation from the MSA section to the HPT sec-
tion via software.
R/W
R/W
0
0
0 = Normal operation
1 = Force
Enable consideration of AU pointer SS bits during pointer
processing. If enabled the SS bits must be set to “10” (binary)
or a LOP (C4H<7>) alarm will be generated.
0 = Disable
1 = Enable
101
SXT6051 STM-1/0 SDH Overhead Terminator
R_AU_NCNT—Receive Negative AU Pointer Justification Event Counter
(92–91H)
This counter increments each time a negative pointer justification on the receive side is detected in the H1: H2 bytes of the
administrative unit payload. A write to the MSByte of the counter (register 92H) causes the entire counter to be loaded into
a buffer and then cleared. The contents of the buffer can then be read.
Note
If receive re-timing is enabled (RcvRetimDsbl = 51<3> = 0) and a pointer decrement is generated by the re-timing
function, this counter will not be incremented.
.
Bit
Name
Description
Type
Default
15:11
10:0
Reserved
RcvAUNegCnt<10:0>
Bits <10:0> represent the count value.
RO
00H
R_AU_PCNT—Receive Positive AU Pointer Justification Event Counter
(94–93H)
This counter increments each time a negative pointer justification on the receive side is detected in the H1:H2 bytes of the
administrative unit payload. A write to the MSByte of the counter (register 94H) causes the entire counter to be loaded into
a buffer and then cleared. The contents of the buffer can then be read.
Note
If re-timing is enabled (RcvRetimDsbl = 51H<3> = 0) and a pointer increment is generated by the re-timing
function, this counter will not be incremented.
.
Bit
Name
Reserved
RcvAUPosCnt<10:0>
Description
Type
Default
15:11
10:0
Bits <10:0> represent the count value.
RO
00H
102
SXT6051 Microprocessor Interface & Register Description
Receive HighOrder Path Termination Registers
R_HPT_C1—Receive HPT Configuration 1 Register (80H)
.
Bit
Name
Description
Type
Default
7
HptRdiDetCnt
This bit configures the number of received G1 bytes that
must have the same value in the RDI bits for the HptRdiSt
bit (C5H<bit 3>) to be updated. The received G1 RDI bits
can be retrieved via register 85H.
R/W
0
0 = 3
1 = 5
6
C2MsMtchCnt
Configures the number of mismatches, between the RcvC2
byte (83H) and the ExpcC2 byte (82H), needed for the
HptSlmSt bit (C5H<bit 4>) to be updated.
R/W
0
0 = 3 mismatches
1 = 5 mismatches
Set the J1 string length
0 = 16 bytes
5
4
RcvJ1StrgLen
RcvHptAisFrc
R/W
R/W
0
0
1 = 64 bytes
Force AIS generation from the HPT section to the HPA sec-
tion via software
0 = Normal Operation
1 = Force
3
RcvHptAisEnbl
Enable/Disable automatic AIS generation from the HPT
section to the HPA section. (See GenHptAisSt bit (D0H<bit
4>) for AIS generation logic).
R/W
0
0 = Disable
1 = Enable
2
1
0
B3CntrCnfg
HptReiCntrCnfg
Reserved
Configure B3 error counter to be updated using bit errors or
block errors.
R/W
R/W
0
0
0 = Bit error
1 = Block errors
Configure HPT REI error counter (88H and 89H) to be
updated using bit errors or block errors.
0 = Bit error
1 = Block errors
103
SXT6051 STM-1/0 SDH Overhead Terminator
R_HPT_C2—Receive HPT Configuration 2 Register (81H)
.
Bit
Name
Reserved
Description
Type
Default
7
6
HptRdiOnSlmEn
Enable the insertion of HPT RDI on active HptSlmSt
R/W
0
(C5H<bit 4>) alarm.
0 = Active HptSlmSt alarm will not cause insertion of
RDI bits in the transmitted G1 byte.
1 = Active HptSlmSt alarm will cause insertion of RDI
bits in the transmitted G1 byte.
5
4
RcvTbJ0J1Cnfg
Configures DTBJ0J1EN output.
R/W
R/W
0
0
0 = Single pulse on J1 every frame.
1 = Double pulse on J1 every 4 frames, indicating mul-
tiframe beginning (H4<1:0> = “00”). Other 3
frames only a single pulse.
HptRdiOnUnEqpEn
Enable the insertion of HPT RDI on active HptUnEqpSt
(C5H<bit 5>) alarm.
0 = Active HptUnEqpSt alarm will not cause update of
transmitted G1 RDI bits
1 = Active HptUnEqpSt alarm will cause update of
transmitted G1 RDI bits.
3
2
B3UnEqpCnfg
Configures behavior of HptUnEqpSt alarm
(C5H<bit 5>) generation based on the B3 byte.
R/W
R/W
R/W
0
0
0 = Ignore B3 when generating HptUnEqpSt alarm
1= No error detected in received B3 for 5 consecutive
frames is necessary for HptUnEqpSt alarm gener-
ation.
N1UnEqpCnfg
Configures behavior of HptUnEqpSt alarm
(C5H<bit 5>) alarm generation based on the N1 byte.
0 = Ignore N1 when generating HptUnEqpSt alarm.
1 = Received N1 with value zero for 5 consecutive
frames is necessary for HptUnEqpSt alarm gener-
ation.
1:0
J1UnEqpCnfg<1:0>
These bits configure the behavior of HptUnEqpSt
00
(C5H<bit 5>) alarm generation based on the J1 byte.
00 = Ignore J1 when generating HptUnEqpSt alarm.
10 = Receive J1 with value zero for 5 consecutive
frames is necessary for HptUnEqpSt alarm gener-
ation.
104
SXT6051 Microprocessor Interface & Register Description
J1_RSTR_C—J1 Expected String Control Register (8AH)
These registers allow the configuring of the expected J1string (trace identifier) received in incoming HPOH. See the
J0_RSTR_C (0EH) Register description for the configuration procedure.
Bit
Name
Reserved
Description
Type
Default
7:2
1
ExpcJ1Acc
This bit allows microprocessor read/write operations to
be in control of incrementing the string pointer. This func-
tionality is normally used only during initialization, to
verify the string value configured by the microprocessor.
WO
1
0 = Normal operation. Internal hardware process that
compares the configured J1 string with the incoming
J1 string and increments the string pointer.
1 = The microprocessor read/write operations increment
the string pointer.
0
RstExpcJ1StrgPntr
A transition from 0 to 1 in this bit resets the J1 expected
string pointer.
WO
0
J1_RSTR_D—J1 Expected String Data Register (8BH)
.
Bit
Name
Description
Type
Default
7:0
ExpcJ1StrgData<7:0>
Bits <7:0> correspond to Data<7:0>, respectively.
R/W
00H
EXP_C2—Expected C2 byte Register (82H)
The contents of this register are the expected value of the received signal label (C2) byte.
Bit
Name
Description
Type
Default
7:0
ExpcC2<7:0>
Bits <7:0> correspond to ExpcC2<7:0>, respectively.
R/W
00H
R_C2—Received C2 byte Register (83H)
The contents of this register are the received signal label (C2) byte.
Bit
Name
Description
Type
Default
7:0
RcvC2<7:0>
Bits <7:0> correspond to RcvC2<7:0>, respectively.
RO
XXH
R_K3—Received K3 byte Register (84H)
Setting of the last 3 consecutively received K3 bytes having the same value.
Bit
Name
Description
Type
Default
7:0
RcvK2<7:0>
Bits <7:0> correspond to RcvK2<7:0>, respectively.
RO
XXH
105
SXT6051 STM-1/0 SDH Overhead Terminator
R_HPT_RDI—Received HPT RDI Bits Register (85H)
The contents of this register are the received RDI (G1<3:1>) and spare bits (G1<bit 0>) from the received G1 byte.
Bit
Name
Reserved
Description
Type
Default
7:4
3:1
0
HptRcvRdi<2:0>
HptRcvSpBit
Bits <3:1> correspond to G1<3:1>, respectively.
G1 <bit 0>
RO
RO
X
X
B3_ECNT—B3 Error Event Counter (87–86H)
87H=Bits<15:8>, 86H=Bits<7:0> (Byte access only)
This counter is configured via B3CntrCnfg (registers 0x80) to count B3 error events. A write to the MSByte of the counter
(register 87H) causes the entire counter to be loaded into a buffer and then cleared. The contents of the buffer can then be
read.
Bit
Name
Description
Type
Default
15:0
B3Cnt<15:0>
Bits <15:0> correspond to B3CNT<15:0>, respectively.
RO
0000H
HPTREI_CNT—HPT REI Counter (89–88H)
89H=Bits<15:8>, 88H=Bits<7:0> (Byte access only)
If counting HPT REI bit errors (HptReiCntrCnfg = 80H<bit 1> = 0), each frame’s HPT REI bits (G1<7:4>) are added to
this counter. If counting HPT REI block errors (HptReiCntrCnfg = 80H<bit 1> = 1), for each frame in which the value of
the REI bits is non-zero, this counter is incremented. A write to the MSByte of the counter (register 89H) causes the entire
counter to be loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Description
Type
Default
15:0
HptReiCnt<15:0>
Bits <15:0> correspond to HptReiCnt<15:0>, respectively.
RO
0000H
106
SXT6051 Microprocessor Interface & Register Description
Transmit Regenerator and Multiplexer Section Termination
Registers
T_RMST_OP1—Transmit RMST Operational 1 Register (30H)
.
Bit
Name
Description
Type
Default
7
XmtMsaAisFrc
Force AIS at the pointer processing block level (MSA)
towards the SDH network
R/W
0
0 = No force
1 = Force AIS
6
5
4
MstReiSrc
Nu1DefEn
MstRdiSrc
When XmtM1Src = 60H<0> = 0 the source of the M1 REI bits
is defined by this bit.
R/W
R/W
R/W
0
0
0
0 = Hardware supplied REI (Feedback of received B2 errors)
1 = REI bits set to zero
Value for NU1_8 & NU1_9 when transmit source is not serial
bus (see XmtNu1_9Src & XmtNu1_8Src in register 62H)
0 = Default value (AAH)
1 = Microprocessor supplied value
When XmtK2Src = 61H<bit 1> = 0 the source of the MST RDI
bits (K2<2:0>) are defined by this bit.
0 = Hardware supplied MST RDI bits (other K2 bits set to reg-
ister 38H value)
1 = Microprocessor supplied RDI (all K2 bits set to register
38H value)
3:2
1:0
InvB2<1:0>
InvB1<1:0>
Invert B2 byte (used for testing).
0X = No inversion
R/W
R/W
00
00
10 = Invert forever
11 = Invert for a frame
Invert B1 byte (used for testing).
0X = No inversion
10 = Invert forever
11 = Invert for a frame
107
SXT6051 STM-1/0 SDH Overhead Terminator
T_RMST_OP2—Transmit RMST Operational 2 Register (1AH)
To activate the configuration bits specified in this register the K2 byte must come from hardware
(XmtK2Src = 61H<bit 1>= 0) and K2 RDI bits must be hardware supplied (MstRdiSrc = 30H<bit 4> = 0).
Bit
Name
Reserved
Description
Type
Default
7:3
2
MstRdiOnExcB2En
Enable the insertion of MST RDI (K2<2:0> = “110”) dur-
R/W
0
ing active ExcB2ErrSt (C1H<bit 3>).
0 = Active ExcB2ErrSt will not cause insertion
1 = Active ExcB2ErrSt will cause insertion
Force insertion of MST RDI (K2<2:0> = “110”).
0 = Disable force
1
0
MstRdiFrc
Reserved
R/W
0
1 = Enable force
108
SXT6051 Microprocessor Interface & Register Description
T_SC1_SOH—Transmit Source Configuration 1 for SOH bytes Register
(60H)
Bit
Name
XmtJ0Src
Description
Type
Default
7:6
These bits specify the source of the transmitted J0 byte.
XmtJ0Src<1> should be set to 0 in terminal and ADM con-
figurations.
R/W
0
00 = Microprocessor
01 = TSOH input
1X = Source is received byte
5
4
3
2
XmtE1Src
This bit specifies the source of the transmitted E1 byte. Should
be set to 0 in terminal configuration.
R/W
R/W
R/W
R/W
0
0
0
0
0 = TROW input
1 = Source is received byte
XmtF1Src
This bit specifies the source of the transmitted F1 byte. Should
be set to 0 in terminal configuration.
0 = TDOW input
1 = Source is received byte
XmtD1D3Src
XmtD4D12Src
This bit specifies the source of the transmitted D1-D3 bytes.
Should be set to 0 in terminal configuration.
0 = TRD input
1 = Source is received byte
This bit specifies the source of the transmitted D4-D12 bytes.
Should be set to 0 in terminal configuration. Should be set to
1 in regenerator configuration.
0 = TMD input
1 = Source is received byte
1
0
XmtE2Src
XmtM1Src
This bit specifies the source of the transmitted E2 byte. Should
be set to 0 in terminal configuration. Should be set to 1 in
regenerator configuration.
R/W
R/W
0
0
0 = TMOW input
1 = Source is received byte
This bit specifies the source of the transmitted M1 byte. It is
ignored in regenerator configuration - the received M1 byte
is passed through.
0 = Internal hardware process (see MstReiSrc, 30H<bit 6>)
1 = TSOH input
109
SXT6051 STM-1/0 SDH Overhead Terminator
T_SC2_SOH—Transmit Source Configuration 2 for SOH bytes Register
(61H)
Bit
Name
Description
Type
Default
7
XmtNu9_9Src
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the National Use byte in row 9 column 9 of the
SOH. It is ignored in regenerator configuration - the
received byte is passed through.
R/W
0
0 = Microprocessor
1 = TSOH input
6
5
4
3
2
XmtNu9_8Src
XmtUn3_9Src
XmtUn3_8Src
XmtUn3_6Src
XmtS1Src
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the National Use byte in row 9 column 8 of the
SOH. It is ignored in regenerator configuration - the
received byte is passed through.
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0 = Microprocessor
1 = TSOH input
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the “Unused” byte in row 3 column 9 of the
SOH. Should be set to 0 in terminal and ADM configura-
tions.
0 = TSOH input
1 = Source is received byte
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the “Unused” byte in row 3 column 8 of the
SOH. Should be set to 0 in terminal and ADM configura-
tions.
0 = TSOH input
1 = Source is received byte
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the “Unused” byte in row 3 column 6 of the
SOH. Should be set to 0 in terminal and ADM configura-
tions.
0 = TSOH input
1 = Source is received byte
This bit specifies the source of the transmitted S1 byte. It is
ignored in regenerator configuration - the received S1 byte
is passed through.
0 = Microprocessor
1 = TSOH input
110
SXT6051 Microprocessor Interface & Register Description
Bit
Name
Description
Type
Default
1
XmtK2Src
This bit specifies the source of the transmitted K2 byte. It is
ignored in regenerator configuration - the received K2 byte
is passed through.
R/W
0
0 = Internal hardware process (see MstRdiSrc, 30H<4>)
1 = TSOH input
0
XmtK1Src
This bit specifies the source of the transmitted K1 byte. It is
ignored in regenerator configuration - the received K1 byte
is passed through.
R/W
0
0 = Microprocessor
1 = TSOH input
T_SC3_SOH—Transmit Source Configuration 3 for SOH Bytes Register
(62H)
Bit
Name
Description
Type
Default
7:6
XmtNu2_9Src<1:0>
These bits are only valid in STM-1 mode. They specify
transmit source for the National Use byte in row 2 column
9 of the SOH. XmtNu2_9Src<1> should be set to Ø in
terminal and ADM configurations.
R/W
00
00 = Microprocessor provided value
01 = TSOH input
1X = Received byte
5:4
XmtNu2_8Src<1:0>
These bits are only valid in STM-1 mode. They specify
the transmit source for the National Use byte in row 2 col-
umn 8 of the SOH. XmtNu2_8Src<1> should be set to Ø
in terminal and ADM configurations.
R/W
00
00 = Microprocessor provided value
01 = TSOH input
1X = Received byte
3:2
XmtNu1_9Src<1:0>
These bits are only valid in STM-1 mode. They specify
the transmit source for the National Use byte in row 1 col-
umn 9 of the SOH. XmtNu1_9Src<1> should be set to Ø
in terminal and ADM configurations.
R/W
00
00 = Nu1DefEn (30H<5>)
01 = TSOH input
1X = Received byte
111
SXT6051 STM-1/0 SDH Overhead Terminator
Bit
Name
Description
Type
Default
1:0
XmtNu1_8Src<1:0>
These bits are only valid in STM-1 mode. They specify
the transmit source for the National Use byte in row 1 col-
umn 8 of the SOH. XmtNu1_8Src<1> should be set to Ø
in terminal and ADM configurations.
R/W
00
00 = Nu1DefEn (30H<5>)
01 = TSOH input
1X = Received byte
T_SC4_SOH—Transmit Source Configuration 4 for SOH Bytes Register
(63H)
Bit
Name
Reserved
Description
Type
Default
7
6
XmtMd3_5Src
XmtMd3_3Src
XmtMd3_2Src
XmtUn2_6Src
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 3 column 5
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
R/W
0
0 = TSOH input
1 = Source is received byte
5
4
3
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 3 column 3
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
R/W
R/W
R/W
0
0
0
0 = TSOH input
1 = Source is received byte
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 3 column 2
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
0 = TSOH input
1 = Source is received byte
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the “Unused” byte in row 2 column 6 of the
SOH. Should be set to 0 in terminal and ADM configura-
tions.
0 = TSOH input
1 = Source is received byte
112
SXT6051 Microprocessor Interface & Register Description
Bit
Name
Description
Type
Default
2
XmtMd2_5Src
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 2 column 5
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
R/W
0
0 = TSOH input
1 = Source is received byte.
1
0
XmtMd2_3Src
XmtMd2_2Src
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 2 column 3
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
R/W
R/W
0
0
0 = TSOH input
1 = Source is received byte
This bit is only valid in STM-1 mode. It specifies the trans-
mit source for the Media-Dependent byte in row 2 column 2
of the SOH. Should be set to 0 in terminal and ADM config-
urations.
0 = TSOH input
1 = Source is received byte
J0_TSTR_C—J0 Transmit String Control Register (3AH)
These registers allow the configuration of the J0 string to be transmitted in the outgoing SOH. See the J0_RSTR_C (0EH)
Register description for the configuration procedure.
Bit
Name
Reserved
Description
Type
Default
7:2
1
XmtJ0Acc
This bit allows microprocessor read/write operations to be
in control of incrementing the string pointer. This function-
ality is normally used only during initialization, to verify the
string value configured by the microprocessor.
R/W
0
0 = Normal operation. Internal hardware process that
inserts this string into the outgoing STM frame incre-
ments the string pointer.
1 = The microprocessor read/write operations increment
the string pointer. During this operation a value of 01H
is transmitted in the outgoing J0 byte.
0
RstXmtJ0StrgPntr
A transition from 0 to 1 in this bit resets the J0 transmit
string pointer.
R/W
0
113
SXT6051 STM-1/0 SDH Overhead Terminator
JO_TSTR_D—J0 Transmit String Data Register (3BH)
Bit
Name
Description
Type
Default
7:0
XmtJ0StrgData<7:0> Bits <7:0> correspond to Data bits <7:0>, respectively.
R/W
00H
MP_TNU1_8—Microprocessor Provided Transmit Nu1_8 Byte (31H)
When XmtNu1_8Src<1:0> = 62H<1:0> = 00 and Nu1DefEn = 30H<5> = 0 this value will be transmitted in National Use
byte located in row 1 column 8 of an STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu1_8<7:0>
Bits <7:0> correspond to XmtNu1_8<7:0>, respectively.
R/W
00H
MP_TNU1_9—Microprocessor Provided Transmit Nu1_9 Byte Register
(32H)
When XmtNu1_9Src<1:0> = 62H<3:2> = 00 and Nu1DefEn = 30H<5> = 0 this value will be transmitted in National Use
byte located in row 1 column 9 of an STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu1_9<7:0>
Bits <7:0> correspond to XmtNu1_9<7:0>, respectively.
R/W
00H
MP_TNU2_8—Microprocessor Provided Transmit Nu2_8 Byte (33H)
When XmtNu2_8Src<1:0> = 62H<5:4> = 00 this value will be transmitted in National Use byte located in row 2 column 8
of an STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu2_8<7:0>
Bits <7:0> correspond to XmtNu2_8<7:0>, respectively.
R/W
00H
MP_TNU2_9—Microprocessor Provided Transmit Nu2_9 Byte Register
(34H)
When XmtNu2_9Src<1:0> = 62H<7:6> = 00 this value will be transmitted in National Use byte located in row 2 column 9
of an STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu2_9<7:0>
Bits <7:0> correspond to XmtNu2_9<7:0>, respectively.
R/W
00H
114
SXT6051 Microprocessor Interface & Register Description
MP_TNU9_8—Microprocessor Provided Transmit Nu9_8 Byte (35H)
When XmtNu9_8Src = 61H<bit 6> = 0 this value will be transmitted in National Use byte located in row 9 column 8 of an
STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu9_8<7:0>
Bits <7:0> correspond to XmtNu9_8<7:0>, respectively.
R/W
00H
MP_TNU9_9—Microprocessor Provided Transmit Nu9_9 Byte (36H)
When XmtNu9_9Src = 61H<bit 7> = 0 this value will be transmitted in National Use byte located in row 9 column 9 of an
STM-1 frame.
Bit
Name
Description
Type
Default
7:0
XmtNu9_9<7:0>
Bits <7:0> correspond to XmtNu9_9<7:0>, respectively.
R/W
00H
MP_TK1—Microprocessor Provided Transmit K1 Byte Register (37H)
When XmtK1Src = 61H<bit 0> = 0 this byte is transmitted in the K1 byte.
Bit
Name
Description
Type
Default
7:0
XmtK1<7:0>
Bits <7:0> correspond to XmtK1<7:0>, respectively.
R/W
00H
MP_TK2—Microprocessor Provided Transmit K2 Byte Register (38H)
When XmtK2Src = 61H<bit 1> = 0 and K2RdiSrc = 30H<bit 4> = 1 this byte is transmitted in the K2 byte.
Bit
Name
Description
Type
Default
7:0
XmtK2<7:0>
Bits <7:0> correspond to XmtK2<7:0>, respectively.
R/W
00H
MP_TS1—Microprocessor Provided Transmit S1 Byte Register (39H)
When XmtS1Src = 61H<bit 2> = 0 this byte is transmitted in the S1 byte.
Bit
Name
Description
Type
Default
7:0
XmtS1<7:0>
Bits <7:0> correspond to XmtS1<7:0>, respectively.
R/W
00H
115
SXT6051 STM-1/0 SDH Overhead Terminator
Transmit Multiplexer Section Adaptation Registers
The AU pointer justification event counters discussed below are only updated in ADM mode.
T_AU_NCNT—Transmit Negative AU Pointer Justification Event Counter
(E3–E2H)
This counter increments each time a negative pointer justification is generated by the transmit re-timing function (this re-
timing function cannot be disabled). A write to the MSByte of the counter (register 92H) causes the entire counter to be
loaded into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Reserved
XmtAUNegCnt<10:0>
Description
Type
Default
15:11
10:0
Bits <10:0> correspond to counter bits <10:0>, respec-
tively.
RO
00H
T_AU_PCNT—Transmit Positive AU Pointer Justification Event Counter
(E5–E4H)
This counter increments each time a positive pointer justification is generated by the transmit retiming function (this retim-
ing function cannot be disabled). A write to the MSByte of the counter (register 94H) causes the entire counter to be loaded
into a buffer and then cleared. The contents of the buffer can then be read.
Bit
Name
Reserved
XmtAUPosCnt<10:0>
Description
Type
Default
15:11
10:0
Bits <10:0> correspond to counter bits <10:0>, respec-
tively.
RO
00H
116
SXT6051 Microprocessor Interface & Register Description
Transmit HighOrder Path Termination Registers
T_SC_HPOH—Transmit Source Configuration for HPOH bytes (70H)
Note that the H4 POH byte is generated internally. The source of N1 POH byte is serially sourced if XmtPOHSrc = 0 and
passed through if XmtPOHSrc = 1.
Bit
Name
Description
Type
Default
7
XmtUnEqpJ1Cnfg
Enable insertion of all zeros in the J1 bytes during active
R/W
1
HptUnEqpSt (C5H<5>) alarm.
0 = During active HptUnEqpSt send J1 value defined by
XmtJ1Src bit
1 = During active HptUnEqpSt send all zeros in the J1 byte
6
5
XmtK3Src
XmtG1Src
This bit specifies the source of the transmitted K3 byte. It
is ignored in regenerator configuration - the received
K3 byte is passed through.
R/W
R/W
0
0
0 = Microprocessor (73H)
1 = TPOH input
This bit specifies the source of the transmitted G1 byte.
When set to 0, updates to the RDI and REI bits are
defined by G1ReiSrc and G1RdiSrc (see register 71H). It
is ignored in regenerator configuration - the received
G1 byte is passed through.
0 = Internal hardware
1 = TPOH input
4
3
2
XmtC2Src
XmtJ1Src
This bit specifies the source of the transmitted C2 byte. It
is ignored in regenerator configuration - the received
C2 byte is passed through.
R/W
R/W
R/W
0
0
0
0 = Microprocessor (72H)
1 = TPOH input
This bit specifies the source of the transmitted J1 byte. It
is ignored in regenerator configuration - the received J1
byte is passed through.
0 = Microprocessor
1 = TPOH input
XmtPOHSrc
This bit forces all POH bytes to be passed through. Must
be set to 0 in terminal configuration.
0 = Source of all POH bytes independently specified by
other bits in this register
1 = All POH bytes passed through
117
SXT6051 STM-1/0 SDH Overhead Terminator
Bit
Name
XmtF3Src
Description
Type
Default
1
This bit specifies the source of the transmitted F3 byte.
Must be set to 0 in terminal configuration. It is ignored
in regenerator configuration - the received F3 byte is
passed through.
R/W
0
0 = TPOW2 input
1 = Source is received byte
0
XmtF2Src
This bit specifies the source of the transmitted F2 byte.
Must be set to 0 in terminal configuration. It is ignored
in regenerator configuration - the received F2 byte is
passed through.
R/W
0
0 = TPOW1 input
1 = Source is received byte
T_HPT_C—Transmit HPT Configuration (71H)
Bit
Name
Description
Configures MTBJ0J1EN output.
Type
Default
7
XmtTbJ0J1Cnfg
R/W
1
0 = Single pulse on J1 every frame
1 = Double pulse on J1 every 4 frames, indicating multi-
frame beginning (H4<1:0> = “00”). Other 3 frames
only a single pulse
6
XmtUnEqp
Transmit unequipped VC-3 (STM-0) or VC-4 (STM-1) sig-
nal.
R/W
0
0 = Normal
1 = Unequipped – C2, N1 = 00H, Valid B3, J1 see
XmtUnEqpJ1Cnfg bit (70H<7>)
5
4
XmtJ1StrgLen
XmtHptAisFrc
Set the transmitted J1 string length
0 = 16 bytes
R/W
R/W
0
0
1 = 64 bytes
Force AIS at the HPT level towards the SDH network when
XmtPOHSrc = 70H<2> = 1.
0 = Normal operation
1 = Force AIS
3
HptReiSrc
When the XmtG1Src = 70H<5> = 0, the source of the G1
R/W
0
REI bits (G1<7:4>) is defined by this bit setting.
0 = Hardware supplied REI – (feedback B3 errors)
1 = REI bits to zero
118
SXT6051 Microprocessor Interface & Register Description
Bit
Name
HptRdiSrc
Description
Type
Default
2
When the XmtG1Src = 70H<5> = 0, the source of the G1
R/W
0
RDI bits (G1<3:1>) are defined by this bit setting.
0 = Hardware supplied RDI = >
If (AuAisSt OR LopSt)
G1<3:1> = 101
elsif (RdiOnSlmEn AND HptSlmSt)
G1<3:1> = 100
elsif ((RdiOnUnEqpEn AND HptUnEqpSt) OR
J1MsMtchSt)
G1<3:1> = 110
else
G1<3:1> = 000
1 = Microprocessor supplied RDI (74H)
Invert B3 byte (used for testing).
0X = No inversion
1:0
InvB3<1:0>
R/W
00
10 = Invert forever
11 = Invert for a frame
MP_TC2—Microprocessor Provided Transmit C2 Byte (72H)
When XmtC2Src = 70H<4> = 0 and XmtPOHSrc = 70H<2> = 0 this byte is transmitted in the C2 timeslot.
Bit
Name
Description
Type
Default
7:0
XmtC2<7:0>
Bits <7:0> correspond to XmtC2<7:0>, respectively.
R/W
01H
MP_TK3—Microprocessor Provided Transmit K3 Byte (73H)
When XmtK3Src = 70H<6> = 0 and XmtPOHSrc = 70H<2> = 0 this byte is transmitted in the K3 timeslot.
Bit
Name
Description
Type
Default
7:0
XmtK3<7:0>
Bits <7:0> correspond to XmtK3<7:0>, respectively.
R/W
00H
MP_THPTRDI—Microprocessor Provided Transmit HPT RDI bits (74H)
Bit
Name
Reserved
Description
Type
Default
7:4
3:1
XmtHptRdi<2:0>
Microprocessor provided HPT RDI value. This value is
transmitted in G1<3:0> when XmtG1Src = 70H<5> = 0 and
HptRdiSrc = 71H<2> = 1.
R/W
0
0
XmtG1SpBit
Microprocessor provided HPT RDI value. This value is
transmitted in G1<3:0> when XmtG1Src = 70H<5> = 0 and
HptRdiSrc = 71H<2> = 1.
R/W
0
119
SXT6051 STM-1/0 SDH Overhead Terminator
J1_TSTR_C—J1 Transmit String Control (75H)
These registers allow the configuration of the J1 string to be transmitted in outgoing HPOH. See the J0_RSTR_C (0EH)
Register description for the configuration procedure.
Bit
Name
Reserved
Description
Type
Default
7:2
1
XmtJ1Acc
This bit allows microprocessor read/write operations to be
in control of incrementing the string pointer. This function-
ality is normally used only during initialization, to verify the
string value configured by the microprocessor.
W
1
0 = Normal operation. The internal hardware process that
is inserting this string into the outgoing STM frame has
exclusive access to it.
1 = The microprocessor read/write operations increment
the string pointer. During this operation a value of 01H
is transmitted in the outgoing J1 byte.
0
ResetXmtJ1StrgPntr
A transition from 0 to 1 in this bit resets the J1 transmit
string pointer.
W
0
J1_TSTR_D—J1 Transmit String Data (76H)
Bit
Name
Description
Type
R/W
Default
00H
7:0
XmtJ1StrgData<7:0>
Bits <7:0> correspond to data bits 7:0, respectively.
120
SXT6051 Microprocessor Interface & Register Description
Interrupt Source Registers
IS_RG—Receive Regenerator Section Interrupt Source (A0H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 1.
Bit
Name
Description
Type
Default
7
OofOvrFlw
This bit is set when the OOF_ECNT error counter rollover occurs.
RO
0
It is cleared when the counter is read.
6
B1OvrFlw
This bit is set when the B1_ERRCNT error counter rollover occurs.
It is cleared when the counter is read.
RO
RO
0
0
5:4
3
Reserved
Bpv
Only updated for STM-0 serial interface B3ZS encoding. This
bit is set when a bipolar violation occurs on either the DHPOSD or
DHNEGD pins. It is cleared when this register is read.
2
1
0
Los
Lof
Oof
This bit is set when there is a change in the LosSt bit (C0H<2>). It
is cleared when status register (C0H) is read.
RO
RO
RO
0
0
0
This bit is set when there is a change in the LofSt bit (C0H<1>). It
is cleared when status register (C0H) is read.
This bit is set when there is a change in the OofSt bit (C0H<0>). It
is cleared when status register (C0H) is read.
IS_RGMUX—Receive Regenerator and Multiplexor Section Interrupt
Source (A1H)
Each of this bit can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 2.
Bit
Name
Description
Type
Default
7
RcvK1Chg
This bit is set when there is a change in the R_K1 register (00H)
RO
0
register. It is cleared when that register is read.
6
5
4
3
2
1
0
RcvK2Chg
MspSF
This bit is set when there is a change in the R_K2 (01H) register.
It is cleared when that register is read.
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
This bit is set when there is a change in the MspSFSt bit
(C1H<5>). It is cleared when status register (C1H) is read.
MstRdi
This bit is set when there is a change in the MstRdiSt bit
(C1H<4>). It is cleared when status register (C1H) is read.
ExcB2Err
MstAis
This bit is set when there is a change in the ExcB2ErrSt bit
(C1H<3>). It is cleared when status register (C1H) is read.
This bit is set when there is a change in the MstAisSt bit
(C1H<2>). It is cleared when status register (C1H) is read.
J0MsMtch
J0Crc7Err
This bit is set when there is a change in the J0MsMtchSt bit
(C1H<1>). It is cleared when status register (C1H) is read.
This bit is set when there is a change in the J0Crc7ErrSt bit
(C1H<0>). It is cleared when status register (C1H) is read.
121
SXT6051 STM-1/0 SDH Overhead Terminator
IS_MUX—Receive Multiplexor Section Interrupt Source (A2H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 3.
Bit
Name
Reserved
Description
Type
Default
7:5
4
RcvS1Chg
This bit is set when there is a change in the R_S1 register
(02H). It is cleared when that register is read.
RO
RO
RO
RO
RO
0
0
0
0
0
3
2
1
0
B2BitOvrFlw
This bit is set when a B2_BIPCNT error counter rollover
occurs. It is cleared when the counter is read.
B2BlkOvrFlw
MstReiBitOvrFlw
MstReiBlkOvrFlw
This bit is set when a B2_BLKCNT error counter rollover
occurs. It is cleared when the counter is read.
This bit is set when a MR_BIPCNT error counter rollover
occurs. It is cleared when the counter is read.
This bit is set when a MR_BLKCNT error counter rollover
occurs. It is cleared when the counter is read.
IS_PROT—Receive Protection Section Interrupt Source (A3H)
The interrupts in this byte should ONLY be enabled when the chip is configured as an ADM Protection Main or a Terminal
Protection Main. Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the Receive
Interrupt Enable Register 4.
Bit
Name
Description
Type
Default
7:4
3
Reserved
ProtSF
This bit is set when the DMSPPSF input changes state. It is cleared
when status register (C3H) is read.
RO
RO
RO
RO
0
0
0
0
2
1
0
ProtSD
This bit is set when the DMSPPSD input changes state. It is
cleared when status register (C3H) is read.
ProtK1Chg
ProtK2Chg
This bit is set when there is a change in the R_ProtK1 (22H) regis-
ter. It is cleared when that register is read.
This bit is set when there is a change in the R_ProtK2 (23H) regis-
ter. It is cleared when that register is read.
122
SXT6051 Microprocessor Interface & Register Description
IS_A_HPT—Receive Adaptation and HPT Interrupt Source (A4H)
Each of this bit can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 5.
Bit
Name
Description
Type
Default
7
Lop
This bit is set when there is a change in the LopSt bit
RO
0
(C4H<7>). It is cleared when status register (C4H) is read.
6
5
4
3
2
1
0
NewDataFlg
AuAis
This bit is set when there is a change in the NewDataFlgSt bit
(C4H<6>). It is cleared when status register (C4H) is read.
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
This bit is set when there is a change in the AuAisSt bit
(C4H<5>). It is cleared when status register (C4H) is read.
RcvAuNegOvrFlw This bit is set when a R_AU_NgNt error counter rollover
occurs. It is cleared when the counter is read.
RcvAuPosOvrFlw
VcAis
This bit is set when a R_AU_PcNt error counter rollover
occurs. It is cleared when the counter is read.
This bit is set when there is a change in the VcAisSt bit
(C4H<2>). It is cleared when status register (C4H) is read.
RcvC2Chg
RcvK3Chg
This bit is set when there is a change in the R_C2 register
(83H). It is cleared when that register is read.
This bit is set when there is a change in the R_K3 register
(84H). It is cleared when that register is read.
IS_HPT—Receive HPT Interrupt Source (A5H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 6.
Bit
Name
Description
Type
Default
7
J1MsMtch
This bit is set when there is a change in the J1MsMtchSt bit
RO
0
(C5H<7>). It is cleared when the status register (C5H) is read.
6
5
4
3
J1Crc7Err
HptUnEqp
HptSlm
This bit is set when there is a change in the J1Crc7St bit
(C5H<6>). It is cleared when the status register (C5H) is read.
RO
RO
RO
RO
0
0
0
0
This bit is set when there is a change in the HptUneqSt bit
(C5H<5>). It is cleared when the status register (C5H) is read.
This bit is set when there is a change in the HptSlmSt bit
(C5H<4>). It is cleared when the status register (C5H) is read.
HptRdi
This bit is set when the register 85H<3:1> bits (filtered received
G1 RDI bits) change (see G1RdiDetCnt = 80H<7>. It is cleared
when register 85H is read.
2
1
0
HpaLom
This bit is set when there is a change in the HpaLomSt bit
(C5H<2>). It is cleared when the status register (C5H) is read.
RO
RO
RO
0
0
0
HptReiOvrFlw This bit is set when the value in the HPTREI_CNT counter roll-
over. It is cleared when the counter is read.
B3OvrFlw
This bit is set when the value in the B3_ECNT counter rollover.
It is cleared when the counter is read.
123
SXT6051 STM-1/0 SDH Overhead Terminator
IS_RETIME—Receive Retiming Interrupt Source (A6H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable
Register 7.
Bit
Name
Reserved
RcvFifoOvrFlw
Description
Type
Default
7:1
0
Indicates that the receive FIFO has overflowed. It is cleared
when the register is read. It is only valid when receive re-tim-
ing is enabled (RcvRetimDsbl = 51H<3> = 0).
RO
0
0 = No overflow
1 = Overflow
IS_XMT—Transmit Interrupt Source (E0H)
Each of these bits can cause the chip interrupt pin to become active if enabled via the bits the Transmit Interrupt Enable
Register.
Bit
Name
Reserved
Description
Type
Default
7:4
3
XmtAuNegOvrFlw This bit is set when an T_AU_NCNTerror counter rollover
RO
RO
RO
0
0
0
occurs. It is cleared when the counter is read.
2
1
XmtAuPosOvrFlw This bit is set when an T_AU_PCNT error counter rollover
occurs. It is cleared when the counter is read.
XmtFifoOvrFlw
Indicates that the transmit FIFO has overflowed It is cleared
when this register is read.
0 =No overflow
1 = Overflow
0
XmtTbParOvrFlw
Transmit telecom bus (MTBDATA) parity overflow indica-
tion. A parity error on the 8 bit telecom bus value incre-
ments a counter which overflows at 3 setting this bit. The
counter and this bit are cleared when this register is read.
RO
0
0 = No overflow
1 = Overflow
124
SXT6051 Microprocessor Interface & Register Description
IS_GLOB—Global Interrupt Source (D1H)
This register indicates that an interrupt register contains an active interrupt.
Bit
Name
XmtRegInt
Description
Type
Default
7
Indicates that an interrupt in the IS_XMT register (E0H)
RO
X
is active.
0 = No active interrupts
1 = active interrupts
6
5
4
3
2
1
0
RcvRetimRegInt
RcvHptRegInt
Indicates that an interrupt in the IS_RETIME register
(A6H) is active.
RO
RO
RO
RO
RO
RO
RO
X
X
X
X
X
X
X
0 = No active interrupts
1 = active interrupts
Indicates that an interrupt in the IS_HPT register (A5H)
is active.
0 = No active interrupts
1 = active interrupts
RcvAdapRegInt
RcvProtRegInt
Indicates that an interrupt in the IS_A_HPT register
(A4H) is active.
0 = No active interrupts
1 = active interrupts
Indicates that an interrupt in the IS_PROT register
(A3H) is active.
0 = No active interrupts
1 = active interrupts
RcvMuxRegInt
RcvRegenMuxRegInt
RcvRegenRegInt
Indicates that an interrupt in the IS_MUX register
(A2H) is active.
0 = No active interrupts
1 = active interrupts
Indicates that an interrupt in the IS_RGMUX register
(A1H) is active.
0 = No active interrupts
1 = active interrupts
Indicates that an interrupt in the IS_RG register (A0H)
is active.
0 = No active interrupts
1 = active interrupts
125
SXT6051 STM-1/0 SDH Overhead Terminator
Interrupt Enable Registers
All of the interrupt registers in the above section are capa-
ble of activating the chip interrupt pin if their correspond-
ing interrupt enable bits are set to 1. Default value is 0
(disabled). The Interrupt Enable Register bit assignments
mirror the assignments in the corresponding Interrupt
Source Registers. For example, the status bits in the IS_RG
Register (A0H) are enabled by setting the corresponding
bit location in the IE_RG Register (B0H).
IE_RG—Receive Regenerator
Section Interrupt Enable (B0H)
Interrupt enable register for IS_RG.
IE_RGMUX—Receive Regenerator
and Multiplexer Section Interrupt
Enable (B1H)
Interrupt enable register for IS_RGMUX.
IE_MUX—Receive Multiplexor
Section Interrupt Enable (B2H)
Interrupt enable register for IS_MUX.
IE_PROT—Receive Protection
Section Interrupt Enable (B3H)
Interrupt enable register for IS_PROT.
IE_A_HPT—Receive Adaptation
and HPT Interrupt Enable (B4H)
Interrupt enable register for IS_A_HPT.
IE_HPT—Receive HPT Interrupt
Enable (B5H)
Interrupt enable register for IS_HPT.
IE_RETIME—Receive Retiming
Interrupt Enable (B6H)
Interrupt enable register for IS_RETIME.
IE_XMT—Transmit Interrupt Enable
(E1H)
Interrupt enable register IS_XMT.
126
SXT6051 Microprocessor Interface & Register Description
Status Registers
These registers are closely associated with the interrupt source registers. Almost all of the interrupt source bits have an asso-
ciated status bit. Generally, when an interrupt is being acknowledged, the status bit will be checked to see the present status
of the interrupt-generating source. Overflow interrupt sources do not have status bits associated with them since the counter
acts as “status.” Byte change interrupt sources do not have status bits associated with them since the received byte acts as
“status.”
S_RG—Receive Regenerator Section Status (C0H).
Bit
Name
Description
Type
Default
7:3
2
Reserved
LosSt
Present status of Loss of Signal detect
RO
X
0 = No LOS
1 = LOS
1
0
LofSt
OofSt
Present status of Loss of Frame detect
RO
RO
X
X
0 = No LOF
1 = LOF
Present status of Out of Frame detect
0 = No OOF
1 = OOF
S_RGMUX—Receive Regenerator and Multiplexer Section Status (C1H)
.
Bit
Name
Description
Type
Default
7:6
5
Reserved
MspSfSt
This bit indicates the present status of the Signal Fail detection. For
both MASTER and SLAVE configurations the value is reflected at
the SF output pin. When configured as a SLAVE the value is also
reflected at the DMSPPSF output pin.
RO
X
0 = No Signal Fail
1 = Signal Fail = MstAisSt OR (AisOnExcB2En AND ExcB2ErrSt).
Detection of “110” in RcvK2<2:0> bits (01H).
0 = No “110” detect
4
3
2
MstRdiSt
ExcB2ErrSt
MstAisSt
RO
RO
RO
X
X
X
1 = “110” detect
Present status of excessive BER detects
0 = No excessive BER
1 = Excessive BER
Detection of “111” in RcvK2<2:0> bits (01H)
0 = No “111” detect
1 = “111” detect
127
SXT6051 STM-1/0 SDH Overhead Terminator
Bit
Name
Description
Type
Default
1
J0MsMtchSt Present status of comparison between received and expected J0
string
RO
X
0 = OK comparison
1 = Bad comparison
0
J0Crc7ErrSt
Present status of comparison between received and expected J0
string CRC-7 value
RO
X
0 = OK comparison
1 = Bad comparison
S_PROT—Receive Protection Section Status (C3H)
These status bits are only relevant when the chip is configured as an ADM Protection Main or a Terminal Protection Main.
They reflect the protection bus DMSPPSF and DMSPPSD inputvalues (a slave’s DMSPPSD output is updated by a micro-
processor write to SigDegrade = 21H<1>. A slave’s DMSPPSF output is updated whenever MspSFSt is updated).
Bit
Name
Description
Type
Default
7:4
3
Reserved
ProtSfSt
ProtSdSt
Reserved
Present status of DMSPPSF input
Present status of DMSPPSD input
RO
RO
X
X
2
1:0
S_A_HPT—Receive Adaptation and HPT Status (C4H)
.
Bit
Name
LopSt
Description
Type
Default
7
Present status of Loss of Pointer detects
0 = No LOP
RO
X
1 = LOP – Invalid pointer value OR (SS bits!= “10” AND AuP-
ntrSSEn)
6
5
NewDataFlgSt Present status of New Data Flag.
RO
RO
X
X
0 = NDF = 0
1 = NDF = 1
AuAisSt
Present status of Pointer processing AIS detects
0 = No AIS
1= AIS – H1:H2 bytes (AU pointer) = “11111111 11111111”
4:3
2
Reserved
VcAisSt
Present status of VC AIS detect
0 = No AIS
RO
X
1 – AIS – C2 (signal label) = “11111111”
1:0
Reserved
128
SXT6051 Microprocessor Interface & Register Description
S_HPT—Receive HPT Status (C5H)
.
Bit
Name
Description
Type
Default
7
J1MsMtchSt
Present status of comparison between received and expected J1
string.
RO
X
0 = OK comparison
1 = Bad comparison
6
J1Crc7ErrSt
Present status of comparison between received and expected J1
string CRC-7 value.
RO
X
0 = OK comparison
1 = Bad comparison
5
4
HptUnEqpSt:
HptSlmSt
Present status of unequipped status detects
0 = Equipped
RO
RO
X
X
1 = Unequipped – C2 = “00000000” AND (see register 81H)
Present status of Signal Label Mismatch detection
0 = No mismatch
1 = Mismatch – (RcvC2!= ExpcC2) AND (RcvC2 != 00H) AND
(RcvC2 != 01H)
3
2
Reserved
HpaLomSt
Present status of Loss of Multiframe detects
RO
X
0 = No LOM
1 = LOM
1:0
Reserved
129
SXT6051 STM-1/0 SDH Overhead Terminator
S_AIS_PROT—Receive AIS & Protection Switch Status (D0H)
This register is used primarily for testing purposes. It indicates the status of internal chip logic for AIS generation processes
and protection switch status.
Bit
Name
Description
Type
Default
7
GenRstAisSt
Present status of receive side RST AIS generator.
0 = No AIS
RO
X
1 = AIS – (see register 40H)
6
5
GenMstAisSt
GenMsaAisSt
Present status of receive side MST AIS generator.
0 = No AIS
RO
RO
X
X
1 = AIS – (RcvMstAisEn AND MspSFSt) OR RcvMstAisFrc
Present status of receive side MSA AIS generator.
0 = No AIS
1 = AIS = (RcvMsaAisEn AND (AuAisSt OR LopSt)) OR RcvM-
saAisFrc
4
GenHptAisSt
Present status of receive side HPT AIS generator. The value of
this bit is reflected at the AISRX output pin.
RO
RO
X
X
0 = No AIS
1 = AIS – (RcvHptAisEn AND (HptSlmSt OR HptUneqSt OR
J1MsMtchSt)) OR RcvHptAisFrc
3:1
0
Reserved
ProtSwSt
Protection switch status (this bit value is identical to ProtSw bit
value).
0 = Protecting
1 = Not protecting
130
SXT6051 STM-1/0 SDH Overhead Terminator
TESTABILITY
The SXT6051 provides a method for enhancing testability;
IEEE1149.1 Boundary Scan (JTAG) is used for testing of
the interconnect.
An asynchronous reset pin (JTRS) allows resetting of the
boundary scan circuitry.
Table 29: Boundary Scan Port
Pin #
Name
I/O
Function
IEEE 1149.1 Boundary Scan
The boundary scan circuitry allows the user to test the
interconnection between the SXT6051 and the circuit
board.
109
JTMS
I
Test Mode Select:
Determines state of
TAP Controller. Pull up
48k
The boundary scan port consists of 5 pins as shown in the
table below. The heart of the scan circuitry is the Test
Access Port controller (TAP). The TAP controller is a state
machine that controls the function of the boundary scan cir-
cuitry. Inputs to the TAP controller are the Test Mode
Select (JTMS) and the Test Clock (JTCK) signals.
110
108
JTCK
JTRS
I
I
Test Clock: Clock for
all boundary scan cir-
cuitry
Test Reset: Active Low
asynchronous signal
that causes the TAP
controller to reset. Pull
down 35k
Data and instructions are shifted into the SXT6051 through
the Test Data In input pin (JTDI). Data and instructions are
shifted out through the Test Data Out output pin (JTDO).
107
106
JTDI
I
Test Data In: input for
instructions and data.
Pull up 48k
JTDO
O
Test data Out: Output of
instructions and data.
Figure 48:Test Access Port
Boundary Scan
Bypass Register
JTDI
TDO
Device ID register
Instruction Register
JTMS
JTCK
JTRS
Test Access
Port Controller
131
Testability
BYPASS (‘b11): This instruction allows a device to be
removed from the scan chain by inserting a one-bit shift
register stage between TDI and TDO during data shifts.
When the instruction is active, the test logic has no impact
upon the system logic performing its function. When
selected, the shift-register is set to a logic zero on the rising
edge of the JTCK during the CAPTURE-DR state.
Instruction Register and
Definitions
The SXT6051 supports the following instructions identi-
fied by IEEE1149.1: EXTEST, SAMPLE/PRELOAD,
BYPASS and IDCODE. Instructions are shifted into the
instruction register during the SHIFT-IR state, and become
active upon exiting the UPDATE-IR state. The instruction
register definition is shown in the following figure.
IDCODE (‘b10): This instruction allows the reading of
component types via the scan chain. During this instruc-
tion, the 32-bit Device Identification Register (ID-Regis-
ter) is placed between TDI and TDO. The ID Register
captures a fixed value of (117A30FDH) on the rising edge
of JTCK during the CAPTURE-DR state. The Device
Identification Register contains the following information:
Manufacturer ID: ‘d126; Design Part Number: ‘d 6051;
Design Version Number: ‘d1.
Figure 49:Instruction Register
TDI
MSB
LSB
Boundary Scan Register
The Boundary Scan Register is a 209-bit shift register,
made of two types of 4 types of shift-register cells. Accord-
ing to the Boundary Scan Description Language (BSDL),
EXTEST (‘b00): This instruction allows the testing of cir-
cuitry external to the package (typically the board intercon-
nect) to be tested. While the instruction is active, the
boundary scan register is connected between TDI and
TDO, for any data shifts. Boundary scan cells at the output
pins are used to apply test stimuli, while those at input pins
capture test results. Signals present on input pins are loaded
into the BSR inputs cells on the rising edge of JTCK during
CAPTURE-DR state. BSR input cell contents are shifted
one bit location on each rising edge of JTCK during the
SHIFT-DR state. BSR output cell contents appear at output
pins on the falling edge of JTCK during the UPDATE-IR
state.
JTAG_BSRINBOTH,
JTAG_BSRCTL
JTAG_BSROUTBOTH
designated
and
TYPE2,
are
JTAG_BSRINCLKOBS are designated TYPE1.
Summary Information
Length
JTCK
209 BSR cells
JTAG Test Clock
JTAG Test Data Input
JTDI
One test cycle is:
JTDO_C
JTAG Test Data Output Control
enable (internal signal)
1. A test stimuli pattern is shifted into the BSR during
SHIFT-DR state
JTDO
JTMS
JTRS
JTAG Test Data Output
JTAG Test Mode Select
JTAG Test Reset
2. This pattern is applied to output pins during the
UPDATE-DR state
3. The response is loaded in to input BSR cells during the
CAPTURE-DR state
4. The results are shifted out and next test stimuli shifted
into the BSR
SAMPLE/PRELOAD (‘b01): This instruction allows a
snapshot of the normal operation of the SXT6051. The
boundary scan register is connected between the TDI and
TDO for any data shifts while this instruction is active. All
BSR cells capture data present at their inputs on the rising
edge of JTCK during the CAPTURE-DR state. No action
is taken during the UPDATE-DR state.
132
l
SXT6051 STM-1/0 SDH Overhead Terminator
Figure 50:Boundary Scan Cell
Data in
Data out
Scan out
Scan in
Type 1
Shift dr
Clock dr
Scan out
Data out
Data in
Scan in
Shift dr
Type 2
Clock dr
Update dr
M ode
133
Testability
Table 30: Boundary Scan Order (Sheet 1 of 6)
Numbering in
Scan chain
Associated
Control enable
Pin Name
Type
Type of BSR Cell
SCANEN
Data
1
2
3
4
5
6
7
8
9
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
DRETCLK
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
DRETFRMI
B3OUT
OEN_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
OEN_C
DMSPP_C
RPOWBYC
RPOWC
RPOW2
RPOW1
RPOHEN
RPOHFR
RPOHCK
RPOH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
B2OUT
RMDC
RMD
RRDC
RRD
RDOW
RMOW
ROWBYC
ROWC
RROW
RSOHFR
RSOHEN
RSOH
DMSPPSD /O
DMSPPSD /I
DMSPPSF /O
DMSPPSF /I
DMSPPAUEN /O
DMSPPAUEN /I
DMSPPJ0EN /O
DMSPPJ0EN /I
DMSPPCKI
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
134
l
SXT6051 STM-1/0 SDH Overhead Terminator
Table 30: Boundary Scan Order (Sheet 2 of 6)
Numbering in
Associated
Control enable
Pin Name
Type
Type of BSR Cell
Scan chain
DMSPPCKO
Data
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
JTAG_BSROUTBOTH
JTAG_BSRCTL
OEN_C
DMSPP_C (internal)
DMSPPDATA /O<7>
DMSPPDATA /I<7>
DMSPPDATA /O<6>
DMSPPDATA /I<6>
DMSPPDATA /O<5>
DMSPPDATA /I<5>
DMSPPDATA /O<4>
DMSPPDATA /I<4>
DMSPPDATA /O<3>
DMSPPDATA /I<3>
DMSPPDATA /O<2>
DMSPPDATA /I<2>
DMSPPDATA /O<1>
DMSPPDATA /I<1>
DMSPPDATA /O<0>
DMSPPDATA /I<0>
OEN
Enbl
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
Data
Data
Data
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
DMSPP_C
SCANTEST
DHPOSD
DHNEGD
DHICLK
LOS
DHBDATA <0>
DHBDATA <1>
DHBDATA <2>
DHBDATA <3>
DHBDATA <4>
DHBDATA <5>
DHBDATA <6>
DHBDATA <7>
DHBCLK
STMMODE
B1OUT
OEN_C
OEN_C
AISRX
135
Testability
Table 30: Boundary Scan Order (Sheet 3 of 6)
Numbering in
Scan chain
Associated
Control enable
Pin Name
Type
Type of BSR Cell
LOF
OOF
Data
71
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
OEN_C
OEN_C
Data
Enbl
Data
Data
Data
Data
Data
Clock
Clock
Data
Data
Enbl
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enbl
Data
Enbl
Data
Data
Data
Data
Data
Data
Data
Data
Data
72
73
OEN_C (internal)
SD
74
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINCLKOBS
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
OEN_C
OEN_C
SF
75
SCRAMSEL
76
MFRMO
77
OEN_C
MFRMI
78
MHICLK
79
80
81
MHBCLKI
MMSAPAYEN
MMSAJ1EN
TB3Z_C
TB3Z_C
82
83
84
PARSEL_C (internal)
MHBCLKO
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
PARSEL_C
SERSEL_C
SERSEL_C
MHBDATA <0>
MHBDATA <1>
MHBDATA <2>
MHBDATA <3>
MHBDATA <4>
MHBDATA <5>
MHBDATA <6>
MHBDATA <7>
MICLK
85
86
87
88
89
90
91
92
93
MHNEGD
94
SERSEL_C (internal)
MHPOSD
95
96
97
98
99
100
101
102
103
104
105
106
JTAG_BSROUTBOTH
JTAG_BSRCTL
SERSEL_C
MMSPP_C
MMSPP_C
MMSPP_C
MMSPP_C
MMSPP_C
MMSPP_C (internal)
MMSPPDATA /O<0>
MMSPPDATA /I<0>
MMSPPDATA /O<1>
MMSPPDATA /I<1>
MMSPPDATA /O<2>
MMSPPDATA /I<2>
MMSPPDATA /O<3>
MMSPPDATA /I<3>
MMSPPDATA /O<4>
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
136
l
SXT6051 STM-1/0 SDH Overhead Terminator
Table 30: Boundary Scan Order (Sheet 4 of 6)
Numbering in
Associated
Control enable
Pin Name
Type
Type of BSR Cell
Scan chain
MMSPPDATA /I<4>
MMSPPDATA /O<5>
MMSPPDATA /I<5>
MMSPPDATA /O<6>
MMSPPDATA /I<6>
MMSPPDATA /O<7>
MMSPPDATA /I<7>
MMSPPCKI
MMSPPCKO
MMSPPAUEN
MMSPPJ0EN /O
MMSPPJ0EN /I
TSOH
Data
107
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
Data
Data
Data
Data
Data
Data
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enbl
Data
Data
Data
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
MMSPP_C
MMSPP_C
MMSPP_C
OEN_C
MMSPP_C
MMSPP_C
TSOHEN
OEN_C
OEN_C
TSOHFR
TROW
TOWC
OEN_C
TMOW
TDOW
TOWBYC
OEN_C
OEN_C
OEN_C
TRD
TRDC
TMD
TMDC
TPOH
TPOHCK
TB3Z_C
TB3Z_C
TB3Z_C
TPOHFR
TPOHEN
TPOW1
TPOW2
TPOWC
TB3Z_C
TB3Z_C
TPOWBYC
RDB_C (internal)
DATA /I<7>
DATA /O<7>
DATA /I<6>
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
RDB_C
137
Testability
Table 30: Boundary Scan Order (Sheet 5 of 6)
Numbering in
Scan chain
Associated
Control enable
Pin Name
Type
Type of BSR Cell
DATA /O<6>
Data
143
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
RDB_C
DATA /I<5>
DATA /O<5>
DATA /I<4>
DATA /O<4>
DATA /I<3>
DATA /O<3>
DATA /I<2>
DATA /O<2>
DATA /I<1>
DATA /O<1>
DATA /I<0>
DATA /O<0>
AD <7>
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
RDB_C
RDB_C
RDB_C
RDB_C
RDB_C
RDB_C
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CS
AS
WR/RW
RD/E
MRESET
INT
OEN_C
MCUTYPE
MTBDATA [7]
MTBDATA [6]
MTBDATA [5]
MTBDATA [4]
MTBDATA [3]
MTBDATA [2]
MTBDATA [1]
MTBDATA [0]
138
l
SXT6051 STM-1/0 SDH Overhead Terminator
Table 30: Boundary Scan Order (Sheet 6 of 6)
Numbering in
Associated
Control enable
Pin Name
Type
Type of BSR Cell
Scan chain
MTBPAR
MTBCKI
Data
179
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRCTL
Clock
Enbl
Data
Enbl
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
TB3Z_C (internal)
MTBCKO
JTAG_BSROUTBOTH
JTAG_BSRCTL
TB3Z_C
TB_C
TB_C (internal)
MTBJ0J1EN /O
MTBJ0J1EN /I
MTBTUGEN1
MTBTUGEN2
MTBTUGEN3
MTBPAYEN /O
MTBPAYEN /I
MTBH4EN /O
MTBH4EN /I
MMFRMI
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
TB3Z_C
TB3Z_C
TB3Z_C
TB_C
TB_C
DTBH4EN
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
TB3Z_C
DTBPAYEN
DTBTUGEN3
DTBTUGEN2
DTBTUGEN1
DTBJ0J1EN
DTBCK
DTBPAR
DTBDATA [0]
DTBDATA [1]
DTBDATA [2]
DTBDATA [3]
DTBDATA [4]
DTBDATA [5]
DTBDATA [6]
DTBDATA [7]
139
Package Information
PACKAGE INFORMATION
The SXT6051 Overhead Terminator is packaged in a 208-
pin QFP package. The package measures 28mm per side,
plus 1.3mm pin lead length.
• Part Number SXT6051
• 208-pin Plastic Quad Flat Pack
• Extended Temperature Range
D
D 1
Millimeters
e
E 1
E
Dim
Min
Max
A
A1
A2
b
-
4.10
-
e
/
2
0.25
3.20
0.17
3.60
0.27
D
30.60 BSC.
θ2
D1
E
28.00 BSC.
30.60 BSC.
28.00 BSC.
.50 BSC.
L1
A2
A
E1
e
θ
A1
L
0.50
0.75
θ3
b
L
L1
θ
1.30 REF
0°
5°
5°
7°
θ2
θ3
16°
16°
140
l
SXT6051 STM-1/0 SDH Overhead Terminator
GLOSSARY OF TERMS
AIS
Alarm Indication Signal
APS
Automatic Protection Switching
Administrative Unit Group
Excessive Error Defect
AUG
EED
FIFO
HPT
First in/First Out Memory
High Order Path Termination
High Order Path OverHead
Loss of Frame
HPOH
LOF
LOP
Loss of Pointer
MSA
MSOH
MST
NDF
NRZ
OOF
POH
RDI
Multiplexer Section Adaptation
Multiplexer Section Overhead
Multiplexer Section Termination
New Data Flag
Non-Return to Zero
Out of Frame
Path Overhead
Remote Defect Indication
Remote Error Indication
Regenerator Section Overhead
Synchronous Digital Hierarchy
Synchronous Optical Network
Synchronous Payload Envelope
Synchronous Transport Module
Synchronous Transport Module for Radio Relay
Synchronous Transport Signal
Tributary Unit Group
REI
RSOH
SDH
SONET
SPE
STM
STM-RR
STS
TUG
VC
Virtual Container
141
SXT6051 STM-1/0 SDH Overhead Terminator
Table 31: Changes from previous version (Rev. 1.0) to current (Rev. 1.1)
Section
Page #
Change
Description
Pin
Description
15
Modify
Move descriptions of pins 112 and 113 from Multiplexer/demultiplexer Pro-
tection Interface Section to External References section.
Functional
Description
29
27
Delete
Sentence: “The 00 for each calculated B2 bit is different from the one
received.”
Functional
Description
Modify
Modified Figure 8, STM-O Framing Acquisition
142
SXT6051 Glossary of terms
Notes
143
Corporate Headquarters
9750 Goethe Road
Sacramento, California 95827
Telephone (916) 855-5000
Fax: (916) 854-1101
Web: www.level1.com
The Americas
International
EAST
WEST
ASIA/PACIFIC
EUROPE
European Area
Eastern Area Headquarters & Western Area
Northeastern Regional Office Headquarters
Asia / Pacific Area
Headquarters
Headquarters
234 Littleton Road, Unit 1A
Westford, MA 01886
Tel: (508) 692-1193
3375 Scott Blvd., #338
101 Thomson Road
United Square #08-01
Singapore 307591
Tel: +65 353-6722
Fax: +65 353-6711
Parc Technopolis - Bat. Zeta
3, avenue du Canada -
Z.A. de Courtaboeuf
91974 Les Ulis Cedex
France
Santa Clara, CA 95054
Tel: (408) 496-1950
Fax: (408) 496-1955
Fax: (508) 692-1244
Tel: +33 1 64 86 2828
Fax: +33 1 60 92 0608
North Central
Regional Office
South Central
Regional Office
Central Asia/Pacific
Regional Office
Northern Europe
Regional Office
One Pierce Place
Suite 500E
Itasca, IL 60143
Tel: (630) 250-6044
Fax: (630) 250-6045
2340 E. Trinity Mills Road Suite 305, 4F-3
Suite 306
75 Hsin Tai Wu Road,
Torshamnsgatan 35
164/40 Kista/Stockholm,
Sweden
Tel: +46 8 750 39 80
Fax: +46 8 750 39 82
Carrollton, TX 75006
Tel: (972) 418-2956
Fax: (972) 418-2985
Sec. 1, Hsi-Chih,
Taipei County, Taiwan
R.O.C.
Tel: +886 22 698 2525
Fax: +886 22 698 3017
Southeastern
Regional Office
Southwestern
Regional Office
Northern Asia/Pacific
Regional Office
Central and Southern
Europe Regional Office
4020 West Chase Blvd.
Raleigh, NC 27615
Tel: (305) 444-2966
Fax: (305) 444-4650
28203 Cabot Road
Suite 300
Laguna Niguel, CA 92677
Tel: (714) 365-5655
Fax: (714) 365-5653
Nishi-Shinjuku, Mizuma "Regus"
Building 8F
Feringastrasse 6
3-3-13, Nishi-Shinjuku, D-85774 Muenchen-
Shinjuku-Ku
Unterfoerhring, Germany
Tel: +49 89 99 216 375
Fax: +49 89 99 216 377
Tokyo, 160 Japan
Tel: +81 33 347-8630
Fax: +81 48 855-0470
Latin/South
America
9750 Goethe Road
Sacramento, CA 95827
USA
Tel: (916) 855-5000
Fax: (916) 854-1102
Revision
Date
Status
1.0
1.1
02/98
05/98
Product Release
Corrected errors, see Table 31 for details
This product is covered by one or more of the following patents. Additional patents pending.
2002382-1; 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746;
5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341
Copyright © 1998 Level One Communications, Inc. Specifications subject to change without notice.
All rights reserved. Printed in the United States of America.
PDS-T
相关型号：
©2020 ICPDF网 联系我们和版权申明