1400I_技术文档

LTC1400

Complete SO-8, 12-Bit,

400ksps ADC with

Shutdown

U

DESCRIPTIO

FEATURES

TheLTC^®1400isacomplete400ksps,12-bitA/Dconverter

which draws only 75mW from 5V or ±5V supplies. This

easy-to-use device comes complete with a 200ns sample-

and-hold and a precision reference. Unipolar and bipolar

conversion modes add to the ﬂexibility of the ADC. The

LTC1400 has two power saving modes: Nap and Sleep.

In Nap mode, it consumes only 6mW of power and can

wake up and convert immediately. In the Sleep mode, it

consumes 30μW of power typically. Upon power-up from

Sleepmode,areferenceready(REFRDY)signalisavailable

in the serial data word to indicate that the reference has

settled and the chip is ready to convert.

■

Complete 12-Bit ADC in SO-8

■

Single Supply 5V or ±5V Operation

■

Sample Rate: 400ksps

Power Dissipation: 75mW (Typ)

■

72dB S/(N + D) and –80dB THD at Nyquist

■

No Missing Codes over Temperature

■

Nap Mode with Instant Wake-Up: 6mW

■

Sleep Mode: 30μW

High Impedance Analog Input

■

Input Range (1mV/LSB): 0V to 4.096V or ±2.048V

■

Internal Reference Can Be Overdriven Externally

■

3-Wire Interface to DSPs and Processors (SPI and

MICROWIRE^TMCompatible)

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The LTC1400 converts 0V to 4.096V unipolar inputs from

a single 5V supply and ±2.048V bipolar inputs from ±5V

supplies. Maximum DC specs include ±1LSB INL, ±1LSB

DNLand45ppm/°Cdriftovertemperature.GuaranteedAC

performance includes 70dB S/(N + D) and –76dB THD at

an input frequency of 100kHz, over temperature.

APPLICATIO S

■

High Speed Data Acquisition

Digital Signal Processing

Multiplexed Data Acquisition Systems

Audio and Telecom Processing

Digital Radio

Spectrum Analysis

Low Power and Battery-Operated Systems

■

The 3-wire serial port allows compact and efﬁcient data

transfer to a wide range of microprocessors, microcon-

trollers and DSPs.

■

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

■

Handheld or Portable Instruments

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TYPICAL APPLICATIO

Single 5V Supply, 400kHz, 12-Bit Sampling A/D Converter

Power Consumption vs Sample Rate

100

NORMAL CONVERSION

10

5V

NAP MODE

BETWEEN CONVERSION

1

V

SS

CC

+

10µF

0.1µF

MPU

P1.4

LTC1400

SLEEP AND NAP MODE

ANALOG INPUT

(0V TO 4.096V)

A

V

CONV

CLK

IN

0.1

0.01

BETWEEN CONVERSION

SLEEP MODE BETWEEN

CONVERSION

2.42V REF

P1.3

P1.2

REF

OUT

+

GND

D

10µF

0.1µF

OUT

SERIAL

DATA LINK

6.4MHz CLOCK

0.001

1400 TA01

100

SAMPLE RATE (Hz)

0.01 0.1

1

10

1k 10k 100k 1M

1400 TA02

1400fa

1

LTC1400

W W W U

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1, 2)

TOP VIEW

Supply Voltage (V ) ..................................................7V

CC

V

SS

1

2

3

4

8

7

6

5

CC

Negative Supply Voltage (V )..................... –6V to GND

SS

A

CONV

CLK

IN

Total Supply Voltage (V to V )

CC

SS

V

REF

Bipolar Operation Only..........................................12V

Analog Input Voltage (Note 3)

GND

D

OUT

S8 PACKAGE

8-LEAD PLASTIC SO

Unipolar Operation....................–0.3V to (V + 0.3V)

CC

Bipolar Operation........... (V – 0.3V) to (V + 0.3V)

SS

CC

T

= 150°C, θ = 130°C/W

JA

JMAX

Digital Input Voltage (Note 4)

ORDER PART NUMBER

S8 PART MARKING

Unipolar Operation................................. –0.3V to 12V

Bipolar Operation.........................(V – 0.3V) to 12V

SS

LTC1400CS8

LTC1400IS8

1400

1400I

Digital Output Voltage

Unipolar Operation....................–0.3V to (V + 0.3V)

CC

Order Options Tape and Reel: Add #TR

Bipolar Operation........... (V – 0.3V) to (V + 0.3V)

SS

CC

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Power Dissipation.............................................. 500mW

Operation Temperature Range

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

LTC1400C ................................................ 0°C to 70°C

LTC1400I ............................................. –40°C to 85°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

W U

POWER REQUIRE E TS ^The

●

denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Positive Supply Voltage (Note 6)

Unipolar

Bipolar

4.75

5.25

V

CC

V

Negative Supply Voltage (Note 6)

Positive Supply Current

Bipolar Only

–2.45

–5.25

V

SS

●

I

f

= 400ksps

SAMPLE

15

1.0

5.0

30

3.0

20.0

mA

μA

CC

Nap Mode

Sleep Mode

●

Negative Supply Current

Power Dissipation

f

= 400ksps, V = –5V

0.3

0.2

1

0.6

0.5

5

mA

μA

SS

SAMPLE

SS

Nap Mode

Sleep Mode

●

P

f

= 400ksps

SAMPLE

75

6

30

160

20

125

mW

μW

D

Nap Mode

Sleep Mode

U

A ALOG I PUT ^The

●

denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

SYMBOL

PARAMETER

CONDITIONS

4.75V ≤ V ≤ 5.25V (Unipolar)

MIN

TYP

MAX

UNITS

●

V

Analog Input Range (Note 7)

0 to 4.096

±2.048

V

IN

CC

4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –2.45V (Bipolar)

CC

SS

●

I

Analog Input Leakage Current

Analog Input Capacitance

During Conversions (Hold Mode)

±1

μA

IN

C

Between Conversions (Sample Mode)

During Conversions (Hold Mode)

45

5

pF

IN

1400fa

2

LTC1400

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CO VERTER CHARACTERISTICS

The

●

denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. With internal reference (Notes 5, 8)

A

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

●

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

12

(Note 9)

±1

LSB

(Note 10)

±6

±8

LSB

●

Full-Scale Error

Full-Scale Tempco

U W

±15

±45

LSB

I

= 0

±10

ppm/°C

OUT(REF)

DY A IC ACCURACY

The

●

denotes the speciﬁcations which apply over the full operating temperature range,

= 400kHz unless otherwise noted. (Note 5)

otherwise speciﬁcations are at T = 25°C. V = 5V, V = –5V, f

SAMPLE

A

CC

SS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

S/(N + D)

Signal-to-Noise

Plus Distortion Ratio

100kHz Input Signal

Commercial

Industrial

70

69

72

dB

200kHz Input Signal

72

dB

●

THD

Total Harmonic Distortion

Up to 5th Harmonic

100kHz Input Signal

200kHz Input Signal

–82

–80

–76

dB

Peak Harmonic or

Spurious Noise

100kHz Input Signal

200kHz Input Signal

–84

–82

dB

IMD

Intermodulation Distortion

f

= 99.51kHz, f = 102.44kHz

–82

–70

dB

IN1

IN2

= 199.12kHz, f = 202.05kHz

IN2

Full Power Bandwidth

4

MHz

kHz

U U ^{Full Linear Bandwidt}U^{h (S/(N + D) ≥ 68dB)}

I TER AL REFERE CE CHARACTERISTICS

900

The

●

denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

PARAMETER

CONDITIONS

MIN

TYP

2.420

±10

MAX

2.440

±45

UNITS

V

Output Voltage

Output Tempco

Load Regulation

I

= 0

2.400

REF

OUT

●

ppm/°C

4.75V ≤ V ≤ 5.25V

0.01

LSB/V

CC

–5.25V ≤ V ≤ 0V

SS

V

Load Regulation

0 ≤ |I | ≤ 1mA

2

4

LSB/mA

ms

REF

OUT

Wake-Up Time from Sleep Mode (Note 7)

C

= 10μF

VREF

U

DIGITAL I PUTS A D DIGITAL OUTPUTS

The

●

denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

CC

V

CC

V

IN

= 5.25V

= 4.75V

= 0V to V

2.0

IH

IL

0.8

V

I

IN

±10

μA

pF

CC

C

V

5

IN

V

CC

V

CC

= 4.75V, I = –10μA

= 4.75V, I = –200μA

4.7

V

OH

O

●

4.0

1400fa

3

LTC1400

U

DIGITAL I PUTS A D DIGITAL OUTPUTS

The

●

denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Low Level Output Voltage

V

= 4.75V, I = 160μA

0.05

0.10

V

OL

CC

O

●

= 4.75V, I = 1.6mA

0.4

O

I

OZ

Hi-Z Output Leakage D

V

OUT

= 0V to V

±10

μA

pF

OUT

CC

C

Hi-Z Output Capacitance D

Output Source Current

Output Sink Current

(Note 7)

15

–10

10

OZ

OUT

I

V

= 0V

mA

SOURCE

OUT

= V

^SINW^KU

OUT

CC

TI I G CHARACTERISTICS

The

●

denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T = 25°C unless otherwise noted. (Note 5)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

kHz

●

f

t

Maximum Sampling Frequency

Conversion Time

(Note 6)

400

SAMPLE(MAX)

CONV

f

= 6.4MHz

2.1

μs

CLK

●

Acquisition Time

(Unipolar Mode)

(Bipolar Mode V = –5V)

(Note 7)

230

200

300

270

ns

ACQ

SS

●

f

t

CLK Frequency

0.1

50

6.4

MHz

ns

CLK

CLK Pulse Width

(Notes 7, 12)

(Note 7)

CLK

Time to Wake Up from Nap Mode

CLK Pulse Width to Return to Active Mode

CONV↑ to CLK↑ Setup Time

350

WK(NAP)

●

50

80

0

1

2

3

4

5

6

7

CONV↑ After Leading CLK↑

CONV Pulse Width

(Note 11)

50

Time from CLK↑ to Sample Mode

Aperture Delay of Sample-and-Hold

Minimum Delay Between Conversion (Unipolar Mode)

(Note 7)

80

45

●

Jitter < 50ps (Note 7)

65

●

265

235

385

355

ns

(Bipolar Mode V = –5V)

SS

●

t

Delay Time, CLK↑ to D

Valid

Hi-Z

C

= 20pF

40

25

80

ns

8

OUT

LOAD

9

OUT

Time from Previous Data Remains Valid After CLK↑

Minimum Time between Nap/Sleep Request to Wake Up Request

14

50

10

11

(Notes 7, 12)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Guaranteed by design, not subject to test.

Note 8: Linearity, offset and full-scale speciﬁcations apply for unipolar and

bipolar modes.

Note 9: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 10: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code ﬂickers between 0000 0000 0000 and 1111 1111 1111.

Note 11: The rising edge of CONV starts a conversion. If CONV returns

low at a bit decision point during the conversion, it can create small errors.

For best performance ensure that CONV returns low either within 120ns

after conversion starts (i.e., before the ﬁrst bit decision) or after the 14

clock cycle. (Figure 13 Timing Diagram).

Note 2: All voltage values are with respect to GND.

Note 3: When these pin voltages are taken below V (ground for unipolar

SS

mode) or above V , they will be clamped by internal diodes. This product

CC

can handle input currents greater than 40mA below V (ground for

SS

unipolar mode) or above V without latch-up.

CC

Note 4: When these pin voltages are taken below V (ground for unipolar

SS

mode), they will be clamped by internal diodes. This product can handle

input currents greater than 40mA below V (ground for unipolar mode)

SS

without latch-up. These pins are not clamped to V

.

CC

Note 5: V = 5V, f

= 400kHz, t = t = 5ns unless otherwise

r f

CC

SAMPLE

Note 12: If this timing speciﬁcation is not met, the device may not respond

speciﬁed.

to a request for a conversion. To recover from this condition a NAP

Note 6: Recommended operating conditions.

request is required.

1400fa

4

LTC1400

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TYPICAL PERFOR A CE CHARACTERISTICS

Differential Nonlinearity vs

Output Code

Integral Nonlinearity vs

Output Code

S/(N + D) vs Input Frequency

and Amplitude

80

70

60

50

40

30

20

10

0

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

V

= 0dB

IN

f

= 400kHz

f

= 400kHz

SAMPLE

V

= –20dB

IN

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

–1.00

V

= –60dB

IN

f

= 400kHz

SAMPLE

10

100

INPUT FREQUENCY (kHz)

1000

2048 2560

3072 3584 4096

0

512 1024 1536

3072 3584 4096

0

512 1024 1536

OUTPUT CODE

1400 TPC06

1400 TPC01

1400 TPC02

Signal-to-Noise Ratio (Without

Harmonics) vs Input Frequency

Peak Harmonic or Spurious Noise

vs Input Frequency

Acquisition Time vs

Source Impedance

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

4500

4000

3500

3000

2500

2000

1500

1000

500

80

70

60

50

40

30

20

10

0

T

= 25°C

f

= 400kHz

A

SAMPLE

f

= 400kHz

SAMPLE

0

10

100

INPUT FREQUENCY (kHz)

1000

10

100

1000

(Ω)

10000

10

100

INPUT FREQUENCY (kHz)

1000

R

SOURCE

1400 TPC05

1400 TPC08

1400 TPC07

Reference Voltage vs

Load Current

Power Supply Feedthrough vs

Ripple Frequency

Supply Current vs Temperature

0

2.435

2,430

2.425

2.420

2.415

2.410

2.405

2.400

2.395

2.390

20

15

10

5

f

= 400kHz

SAMPLE

f

= 400kHz

SAMPLE

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

(V

= 10mV)

RIPPLE

SS

V

(V

= 1mV)

RIPPLE

CC

0

1

10

100

1000

–50 –25

0

25

50

75 100 125

–8

–1

0

1

2

–7 –6 –5 –4 –3 –2

RIPPLE FREQUENCY (kHz)

TEMPERATURE (°C)

LOAD CURRENT (mA)

1400 TPC07.5

1400 TPC04

1400 TPC03

1400fa

5

LTC1400

U U

U

PI FU CTIO S

V

(Pin 1): Positive Supply, 5V. Bypass to GND (10μF

CLK (Pin 6): Clock. This clock synchronizes the serial data

transfer. A minimum CLK pulse of 50ns will cause the ADC

to wake up from Nap or Sleep mode.

CC

tantalum in parallel with 0.1μF ceramic).

A (Pin2):AnalogInput.0Vto4.096V(Unipolar),±2.048V

IN

(Bipolar).

CONV (Pin 7): Conversion Start Signal. This active high

signal starts a conversion on its rising edge. Keeping CLK

low and pulsing CONV two/four times will put the ADC

into Nap/Sleep mode.

V

(Pin 3): 2.42V Reference Output. Bypass to GND

REF

(10μF tantalum in parallel with 0.1μF ceramic).

GND (Pin 4): Ground. GND should be tied directly to an

analog ground plane.

V

(Pin 8): Negative Supply. –5V for bipolar operation.

SS

Bypass to GND with 0.1μF ceramic. V should be tied to

SS

D

(Pin 5): The A/D conversion result is shifted out

GND for unipolar operation.

OUT

from this pin.

U

W

FU CTIO AL BLOCK DIAGRA

C

ZEROING SWITCH

SAMPLE

V

A

CC

IN

GND

V

SS

V

REF

2.42V REF

12-BIT CAPACITIVE DAC

COMP

CLK

12

CONTROL

LOGIC

CONV

SUCCESSIVE APPROXIMATION

REGISTER/PARALLEL TO

SERIAL CONVERTER

D

OUT

1400 BD01

TEST CIRCUITS

5V

3k

D

OUT

D

OUT

3k

C

LOAD

C

LOAD

Hi-Z TO V

OH

Hi-Z TO V

OL

V

OL

OH

TO V

OH

V

OH

OL

TO V

OL

V

TO Hi-Z

V

TO Hi-Z

1400 TC01

1400fa

6

LTC1400

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APPLICATIO S I FOR ATIO

Conversion Details

Dynamic Performance

TheLTC1400hasexcellenthighspeedsamplingcapability.

FFT (Fast Fourier Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined for

frequencies outside the fundamental. Figure 2a shows a

typical LTC1400 FFT plot.

The LTC1400 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit serial output based on a preci-

sion internal reference. The control logic provides easy

interface to microprocessors and DSPs through 3-wire

connections.

A rising edge on the CONV input starts a conversion. At

the start of a conversion the successive approximation

register(SAR)isreset. Onceaconversioncyclehasbegun

it cannot be restarted.

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

to frequencies from DC to half the sampling frequency.

Figure 2a shows a typical spectral content with a 400kHz

sampling rate and a 100kHz input. The dynamic perfor-

mance is excellent for input frequencies up to the Nyquist

limit of 200kHz as shown in Figure 2b.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most signiﬁcant

bit (MSB) to the least signiﬁcant bit (LSB). Referring to

Figure 1, the A input connects to the sample-and-hold

IN

capacitor during the acquired phase and the comparator

offset is nulled by the feedback switch. In this acquire

phase, it typically takes 200ns for the sample-and-hold

capacitor to acquire the analog signal. During the convert

phase, the comparator feedback switch opens, putting the

comparator into the compare mode. The input switches

0

f

= 400kHz

SAMPLE

IN

–10

–20

= 94.824kHz

connect C

to ground, injecting the analog input

SINAD = 72.5dB

THD = –82dB

SAMPLE

–30

charge onto the summing junction. This input charge is

successively compared with the binary-weighted charges

supplied by the capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion,

–40

–50

–60

–70

–80

the DAC output balances the A input charge. The SAR

IN

–90

contents (a 12-bit data word) which represent the input

–100

–110

–120

voltage, are output through the serial pin D

.

OUT

0

20 40 60 80 100 120 140 160 180 200

FREQUENCY (kHz)

SAMPLE

S1

1400 F02a

C

SAMPLE

DAC

Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT

Plot with 100kHz Input Frequency in Bipolar Mode

SAMPLE

HOLD

–

+

A

IN

COMP

Effective Number of Bits

C

V

DAC

The effective number of bits (ENOBs) is a measurement

of the effective resolution of an ADC and is directly related

to the S/(N + D) by the equation:

S

A

R

DAC

D

OUT

S / N+D –1.76

(

)

1400 F01

N=

6.02

Figure 1. A Input

IN

1400fa

7

LTC1400

U U

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APPLICATIO S I FOR ATIO

0

f

= 400kHz

= 199.121kHz

SAMPLE

IN

V2²+ V3²+ V4²+…Vn²

–10

–20

THD= 20log

SINAD = 72.1dB

THD = –80dB

V1

–30

–40

where V1 is the RMS amplitude of the fundamental fre-

quencyandV2throughVnaretheamplitudesofthesecond

through nth harmonics. THD vs input frequency is shown

inFigure4.TheLTC1400hasgooddistortionperformance

up to the Nyquist frequency and beyond.

–50

–60

–70

–80

–90

–100

–110

–120

0

20 40 60 80 100 120 140 160 180 200

FREQUENCY (kHz)

f

= 400kHz

SAMPLE

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1400 F02b

Figure 2b. LTC1400 Nonaveraged, 4096 Point FFT

Plot with 200kHz Input Frequency in Bipolar Mode

where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling

rate of 400kHz, the LTC1400 maintains very good ENOBs

up to the Nyquist input frequency of 200kHz (refer to

Figure 3).

3RD HARMONIC

THD

2ND HARMONIC

10k

100k

1M

INPUT FREQUENCY (Hz)

1400 F04

12

11

10

9

74

68

62

56

50

Figure 4. Distortion vs Input Frequency in Bipolar Mode

NYQUIST

FREQUENCY

8

Intermodulation Distortion

7

6

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

5

4

3

2

1

f

= 400kHz

SAMPLE

0

10k

100k

INPUT FREQUENCY (Hz)

1M

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at sum and difference

frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 2nd order IMD terms include (fa + fb)

and (fa – fb) while the 3rd order IMD terms includes (2fa

+ fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input

sine waves are equal in magnitude, the value (in decibels)

of the 2nd order IMD products can be expressed by the

following formula.

1400 F03

Figure 3. Effective Bits and Signal-to-Noise +

Distortion vs Input Frequency in Bipolar Mode

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half of the sampling frequency. THD

is expressed as:

Amplitude at (fa ± fb)

IMD fa ± fb = 20log

(

)

Amplitude at fa

1400fa

8

LTC1400

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APPLICATIO S I FOR ATIO

0

settles in 200ns to small load current transient will allow

maximum speed operation. If a slower op amp is used,

more settling time can be provided by increasing the time

between conversions. Suitable devices capable of driving

f

= 400kHz

SAMPLE

–10

–20

fa = 99.512kHz

fb = 102.441kHz

fa fb

–30

–40

–50

3fa

2fb – fa

the ADC’s A input include the LT^®1360 and the LT1363

2fa

IN

–60

–70

2fa + fb

op amps.

2fa – fb

fa + fb

2fb

2fb + fa

–80

fb – fa

3fb

LTC1400 comes with a built-in unipolar/bipolar detection

–90

–100

–110

–120

circuit. If V potential is forced below GND, the internal

SS

circuitry will automatically switch to bipolar mode.

0

20 40 60 80 100 120 140 160 180 200

FREQUENCY (kHz)

The following list is a summary of the op amps that are

suitable for driving the LTC1400, more detailed informa-

tion is available in the Linear Technology databooks or the

Linear Technology Website.

1400 F05

Figure 5. Intermodulation Distortion Plot in Bipolar Mode

Figure 5 shows the IMD performance at a 100kHz input.

Peak Harmonic or Spurious Noise

LT1215/LT1216: Dual and quad 23MHz, 50V/μs single

supply op amps. Single 5V to ±15V supplies, 6.6mA

speciﬁcations, 90ns settling to 0.5LSB.

Thepeakharmonicorspuriousnoiseisthelargestspectral

component excluding the input signal and DC. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

LT1223: 100MHz video current feedback ampliﬁer. ±5V

to ±15V supplies, 6mA supply current. Low distortion up

to and above 400kHz. Low noise. Good for AC applica-

tions.

LT1227: 140MHz video current feedback ampliﬁer. ±5V to

±15V supplies, 10mA supply current. Lowest distortion

at frequencies above 400kHz. Low noise. Best for AC

applications.

Full Power and Full Linear Bandwidth

The full power bandwidth is the input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full-scale input signal.

LT1229/LT1230: Dual and quad 100MHz current feedback

ampliﬁers.±2Vto±15Vsupplies,6mAsupplycurrenteach

ampliﬁer. Low noise. Good AC specs.

The full linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 68dB (11 effective bits). The

LTC1400 has been designed to optimize input bandwidth,

allowing the ADC to undersample input signals with fre-

quencies above the converter’s Nyquist Frequency. The

noise ﬂoor stays very low at high frequencies; S/(N +

D) becomes dominated by distortion at frequencies far

beyond Nyquist.

LT1360: 37MHz voltage feedback ampliﬁer. ±5V to ±15V

supplies. 3.8mA supply current. Good AC and DC specs.

70ns settling to 0.5LSB.

LT1363:50MHz, 450V/μsopamps. ±5Vto±15Vsupplies.

6.3mA supply current. Good AC and DC specs. 60ns

settling to 0.5LSB.

Driving the Analog Input

LT1364/LT1365:Dualandquad50MHz,450V/μsopamps.

±5V to ±15V supplies, 6.3mA supply current per ampliﬁer.

60ns settling to 0.5LSB.

The analog input of the LTC1400 is easy to drive. It draws

only one small current spike while charging the sample-

and-hold capacitor at the end of a conversion. During

conversion, the analog input draws only a small leakage

current. The only requirement is that the ampliﬁer driv-

ing the analog input must settle after the small current

spike before the next conversion starts. Any op amp that

Internal Reference

The LTC1400 has an on-chip, temperature compensated,

curvature corrected, bandgap reference, which is factory

1400fa

9

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APPLICATIO S I FOR ATIO

trimmed to 2.42V. It is internally connected to the DAC

and is available at Pin 3 to provide up to 1mA of current to

an external load. For minimum code transition noise, the

reference output should be decoupled with a capacitor to

ﬁlterwidebandnoisefromthereference(10μFtantalumin

Unipolar/Bipolar Operation and Adjustment

Figure 8 shows the ideal input/output characteristics for

the LTC1400. The code transitions occur midway between

successive integer LSB values (i.e., 0.5LSB, 1.5LSB,

2.5LSB, … FS – 1.5LSB). The output code is straight

binary with 1LSB = 4.096V/4096 = 1mV. Figure 9 shows

the input/output transfer characteristics for the bipolar

mode in two’s complement format.

parallel with a 0.1μF ceramic). The V pin can be driven

REF

with a DAC or other means to provide input span adjust-

ment in bipolar mode. The V

pin must be driven to at

REF

least 2.45V to prevent conﬂict with the internal reference.

The reference should not be driven to more than 5V.

FS

4096

1LSB =

111...111

111...110

111...101

111...100

Figure 6 shows an LT1360 op amp driving the reference

pin. Figure 7 shows a typical reference, the LT1019A-5

connected to the LTC1400. This will provide an improved

drift (equal to the maximum 5ppm/°C of the LT1019A-

5) and a ±4.231V full scale. If V

is forced lower than

REF

UNIPOLAR

ZERO

2.42V, the REFRDY bit in the serial data output will be

000...011

000...010

000...001

000...000

forced to low.

5V

INPUT RANGE

0V

1

LSB

V

FS – 1LSB

CC

A

V

IN

±0.846 • V

REF(OUT)

INPUT VOLTAGE (V)

1400 F08

+

LTC1400

V

≥ 2.45V

3Ω

REF(OUT)

LT1360

Figure 8. LTC1400 Unipolar Transfer Characteristics

REF

–

10µF

011...111

GND

V

SS

BIPOLAR

ZERO

011...110

–5V

1400 F06

000...001

000...000

111...111

111...110

Figure 6. Driving the V

with the LT1360 Op Amp

REF

5V

100...001

100...000

INPUT RANGE ±4.231V

(= ±0.846 • V

V

CC

A

V

IN

)

REF

10V

LTC1400

–1 0V

1

–FS/2

FS/2 – 1LSB

V

LSB

IN

V

REF

OUT

INPUT VOLTAGE (V)

11400 F09

3Ω

10µF

LT1019A-5

GND

Figure 9. LTC1400 Bipolar Transfer Characteristics

GND

V

SS

Unipolar Offset and Full-Scale Error Adjustments

–5V

1400 F07

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Figure

10a shows the extra components required for full-scale

Figure 7. Supplying a 5V Reference Voltage

to the LTC1400 with the LT1019A-5

1400fa

10

LTC1400

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APPLICATIO S I FOR ATIO

R1

error adjustment. Figure 10b shows offset and full-scale

adjustment. Offset error must be adjusted before full-

scale error. Zero offset is achieved by applying 0.5mV

(i.e., 0.5LSB) at the input and adjusting the offset trim

until the LTC1400 output code ﬂickers between 0000

0000 0000 and 0000 0000 0001. For zero full-scale er-

ror, apply an analog input of 4.0945V (FS – 1.5LSB or

last code transition) at the input and adjust R5 until the

LTC1400 output code ﬂickers between 1111 1111 1110

and 1111 1111 1111.

50Ω

V

+

IN

A1

A

IN

–

R4

R2

10k

100Ω

LTC1400

GND

R3

10k

FULL-SCALE

ADJUST

ADDITIONAL PINS OMITTED FOR CLARITY

±20LSB TRIM RANGE

1400 F10a

Bipolar Offset and Full-Scale Error Adjustments

Figure 10a. LTC1400 Full-Scale Adjust Circuit

Bipolaroffsetandfull-scaleerrorsareadjustedinasimilar

fashion to the unipolar case. Bipolar offset error adjust-

ment is achieved by applying an input voltage of –0.5mV

(–0.5LSB) to the input in Figure 10c and adjusting the

op amp until the ADC output code ﬂickers between 0000

00000000and111111111111.Forfull-scaleadjustment,

an input voltage of 2.0465V (FS – 1.5LSBs) is applied to

the input and R5 is adjusted until the output code ﬂickers

between 0111 1111 1110 and 0111 1111 1111.

R1

10k

ANALOG

INPUT

+

–

0V TO 4.096V

A

A1

IN

R2

10k

R4

5V

100k

LTC1400

R9

20Ω

R5

4.3k

FULL-SCALE

ADJUST

R3

100k

5V

R7

R8

10k

100k

Board Layout and Bypassing

OFFSET

ADJUST

R6

400Ω

To obtain the best performance from the LTC1400, a

printed circuit board is required. Layout for the printed

circuit board should ensure that digital and analog signal

linesareseparatedasmuchaspossible.Inparticular,care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC. The analog

input should be screened by GND.

1400 F10b

Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit

R1

10k

ANALOG

INPUT

±2.048V

+

–

A1

R2

10k

A

IN

High quality tantalum and ceramic bypass capacitors

R4

100k

should be used at the V and V pins as shown in the

CC

REF

LTC1400

R5

4.3k

Typical Application on the ﬁrst page of this data sheet.

For the bipolar mode, a 0.1μF ceramic provides adequate

FULL-SCALE

ADJUST

bypassing for the V pin. For optimum performance, a

SS

R3

10μF surface mount AVX capacitor with a 0.1μF ceramic

100k

5V

R8

R7

isrecommendedfortheV andV pins.Thecapacitors

100k

CC

REF

20k

OFFSET

mustbelocatedasclosetothepinsaspossible.Thetraces

connecting the pins and the bypass capacitors must be

kept short and should be made as wide as possible. In

ADJUST

R6

–5V

200Ω

1400 F10c

unipolar mode operation, V should be isolated from

SS

any noise source before shorting to the GND pin.

Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit

1400fa

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APPLICATIO S I FOR ATIO

Input signal leads to A and signal return leads from GND

theLTC1400GNDpin.ThegroundreturnfromtheLTC1400

Pin 4 to the power supply should be low impedance for

noise free operation. Digital circuitry grounds must be

connected to the digital supply common.

IN

(Pin 4) should be kept as short as possible to minimize

noisecoupling.Inapplicationswherethisisnotpossible,a

shielded cable between source and ADC is recommended.

Also,sinceanypotentialdifferenceingroundsbetweenthe

signalsourceandADCappearsasanerrorvoltageinseries

with the input signal, attention should be paid to reducing

the ground circuit impedance as much as possible.

InapplicationswheretheADCdataoutputsandcontrolsig-

nalsareconnectedtoacontinuouslyactivemicroprocessor

bus, it is possible to get errors in the conversion results.

These errors are due to feedthrough from the micropro-

cessor to the successive approximation comparator. The

problem can be eliminated by forcing the microprocessor

into a Wait state during conversion or by using three-state

buffers to isolate the ADC data bus.

ANALOG SUPPLY

GND

DIGITAL SUPPLY

–5V

5V

GND

5V

Power-Down Mode

+

Upon power-up, the LTC1400 is initialized to the active

state and is ready for conversion. However, the chip can

be easily placed into the Nap or Sleep mode by exercising

the right combination of CLK and CONV signal. In the Nap

modeallpowerisoffexcepttheinternalreference,whichis

still active and provides 2.42V output voltage to the other

circuitry. In this mode, the ADC draws only 6mW of power

instead of 75mW (for minimum power, the logic inputs

must be within 500mV of the supply rails). The wake-up

time from the Nap mode to the active mode is 350ns.

V

GND

V

GND

V

CC

SS

CC

LTC1400

DIGITAL CIRCUITRY

1400 F11

Figure 11. Power Supply Connection

Figure11showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated at

t

11

CLK

t

1

CONV

NAP

SLEEP

V

REF

REFRDY

1400 F12

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE D

WORD.

OUT

Figure 12. Nap Mode and Sleep Mode Waveforms

1400fa

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APPLICATIO S I FOR ATIO

In the Sleep mode, power consumption is reduced to a

minimum by cutting off the supply to all internal circuitry

includingthereference.Figure12showsthewaystopower

down the LTC1400. The chip can enter the Nap mode by

keeping the CLK signal low and pulsing the CONV signal

twice. For Sleep mode operation, CONV signal should be

pulsed four times while CLK is kept low.

Digital Interface

The digital interface requires only three digital lines. CLK

and CONV are both inputs, and the D

the conversion result in serial form.

output provides

OUT

Figure13showsthedigitaltimingdiagramoftheLTC1400

during the A/D conversion. The CONV rising edge starts

the conversion. Once initiated, it can not be restarted until

the conversion is completed. If the time from CONV signal

The LTC1400 can be returned to active mode easily. The

rising edge of CLK will wake-up the LTC1400. During the

to CLK rising edge is less than t , the digital output will

2

transition from Sleep mode to active mode, the V volt-

REF

be delayed by one clock cycle.

age ramp-up time is a function of the loading conditions.

With a 10μF bypass capacitor, the wake-up time from

Sleep mode is typically 4ms. A REFRDY signal will be

activated once the reference has settled and is ready for

The digital output data is updated on the rising edge of the

CLK line. D

data should be captured by the receiving

OUT

system on the rising CLK edge. Data remains valid for a

minimum time of t after the rising CLK edge to allow

capture to occur.

an A/D conversion. This REFRDY bit is output to the D

10

OUT

pin before the rest of the A/D converted code.

t

2

t

7

t

3

1

2

3

4

5

6

7

8

9

10

11

12

13

15

1

2

14

CLK

t

5

4

CONV

t

6

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

8

Hi-Z

D

OUT

REFRDY D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

REFRDY

t

CONV

t

1400 F13

SAMPLE

Figure 13. ADC Digital Timing Diagram

CLK

V

IH

t

8

t

9

t

10

V

90%

10%

OH

OL

D

OUT

1400 F14

Figure 14. CLK to D

Delay

OUT

1400fa

13

LTC1400

U

TYPICAL APPLICATIO S

Hardware Interface to TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX)

TMS320C50

5V

TCLKX

TCLKR

TFSX

1

2

6

7

V

A

CLK

CC

IN

UNIPOLAR

INPUT

+

CONV

LTC1400

TFSR

0.1µF

10µF

5

3

TDR

V

D

REF

OUT

+

GND

4

SS

8

0.1µF

10µF

1400 TA04a

Logic Analyzer Waveforms Show 3.2μs Throughput Rate (Input Voltage = 3.046V, Output Code = 1011 1110 0110 = 3046 )

10

Data from LTC1400 Loaded into TMS320C50’s TRCV Register

X

D10 D9

D7 D6 D5 D4 D3

D2

D1 D0

X

RDY D11

D8

1400 TA05c

Data Stored in TMS320C50’s Memory (in Right Justiﬁed Format)

0

RDY D11

D10

D9 D8 D7 D6 D5

D4

D3 D2 D1

D0

0

1400 TA05d

1400fa

14

LTC1400

U

TYPICAL APPLICATIO S

TMS320C50 Code for Circuit

THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO TMS320C50

FRAME SYNC PULSE IS GENERATED FROM TFSX

*Start Serial Communication*

SACL TDXR

SPLK #040h, IMR

CLRC INTM

; Generate frame sync pulse

; Turn on TRNT receiver interrupt

; Enable interrupt

*Initialization*

.mmregs

; Deﬁnes global symbolic names

CLRC SXM

; For Unipolar input, set for right shift

;- - Initialized data memory to zero

; with no sign extension

; Load the auxiliary register pointer with seven

.ds

0F00h

; Initialize data to zero

MAR *AR7

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

.word

0

; Begin sample data location

; .

; Location of data

; .

LAR AR7, #0F00h

; Load the auxiliary register seven with #0F00h

; as the begin address for data storage

WAIT: NOP

NOP

; Wait for a receive interrupt

;

; .

NOP

; End sample data location

SACL TDXR

; !! regenerate the frame sync pulse

;

;- - Set up the ISR vector

B

WAIT

.ps

B

080Ah

; Serial ports interrupts

; - - - - - - - end of main program - - - - - - - - - - ;

rint :

xint :

trnt :

txnt :

RECEIVE

TRANSMIT

TREC

; 0A;

; 0C;

; 0E;

; 10;

B

*Receiver Interrupt Service Routine*

TREC:

B

TTRANX

LAMM TRCV

SFR

; Load the data received from LTC1400

; Shift right two times

;

;- - Setup the reset vector

.ps 0A00h

.entry

START:

AND #1FFFh, 0

; ANDed with #1FFFh

; For converting the data to right

; justiﬁed format

*TMS32C050 Initialization*

SETC INTM

; Temporarily disable all interrupts

; Set data page pointer to zero

;

LDP #0

SACL *+, 0

; Write to data memory pointed by AR7 and

; increase the memory address by one

;

OPL #0834h, PMST ; Set up the PMST status and control register

LACC #0

LACC AR7

SUB #0F05h,0

SAMMCWSR

SAMMPDWSR

; Set software wait state to 0

;

; Compare to end sample address #0F05h

BCND END_TRCV, GEQ ; If the end sample address has exceeded jump

to END_TRCV

;

; Else Re-enable the TRNT receive interrupt

; Return to main program and enable interrupt

*Conﬁgure Serial Port*

SPLK #0038h, TSPC ; Set TDM Serial Port

SPLK #040h, IMR

RETE

; TDM = 0 Stand Alone mode

; DLB = 0 Not loop back

; FO = 0 16 Bits

*After Obtained the Data from LTC1400, Program Jump to END_TRCV*

END_TRCV:

; FSM = 1 Burst Mode

; MCM = 1 CLKX is generated internally

; TXM = 1 FSX as output pin

; Put serial port into reset

; (XRST = RRST =0)

SPLK #002h, IMR

CLRC INTM

; Enable INT2 for program to halt

SUCCESS:

SUCCESS

B

SPLK #00F8h, TSPC ; Take Serial Port out of reset

; (XRST = RRST = 1)

SPLK #0FFFFh, IFR ; Clear all the pending interrupts

*Fill the Unused Interrupt with RETE, to avoid program get “lost”*

TTRANX:

RETE

RECEIVE:

RETE

TRANSMIT:

RETE

INT2:

B halt

; Halts the running CPU

1400fa

15

LTC1400

U

TYPICAL APPLICATIO S

LTC1400 Interface to ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0)

ADSP2181

SCLKO

5V

1

2

6

7

CLK

V

A

CC

IN

UNIPOLAR

INPUT

+

CONV

LTC1400

RFSO

DR0

10µF

0.1µF

3

5

V

D

REF

OUT

+

GND

SS

8

0.1µF

10µF

4

1400 TA05a

Logic Analyzer Waveforms Show 2.88μs Throughput Rate (Input Voltage = 2.240V, Output Code = 1000 1100 0000 = 2240 )

10

Data from LTC1400 (Normal Mode)

X

D10 D9

D7 D6 D5 D4 D3

D2

D1 D0

X

RDY D11

D8

1400 TA05c

Data Stored in ADSP2181’s Memory (Normal Mode, SLEN = D)

0

RDY D11

D10

D9 D8 D7 D6 D5

D4

D3 D2 D1

D0

0

1400 TA05d

1400fa

16

LTC1400

U

TYPICAL APPLICATIO S

ADSP2181 Code for Circuit

THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181

FRAME SYNC PULSE IS GENERATED FROM RFS0

/*Section 3: conﬁgure CLKDIV and RFSDIV, setup interrupts*/

/*to conﬁgure CLKDIV reg*/

ax0 = 2;

/*Section 1: Initialization*/

dm(0x3FF5) = ax0; /*set the serial clock divide modulus reg

.module/ram/abs = 0 adspltc; /*deﬁne the program module*/

SCLKDIV*/

jump start;

/*jump over interrupt vectors*/

/*the input clock frequency = 16.67MHz*/

/*CLKOUT frequency = 2x = 33MHz*/

/*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/

/*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/

/*to Conﬁgure RFSDIV*/

nop; nop; nop;

rti; rti; rti; rti;

ax0 = rx0;

/*code vectors here upon IRQ2 int*/

/*code vectors here upon IRQL1 int*/

/*code vectors here upon IRQL0 int*/

/*code vectors here upon SPORT0 TX int*/

/*Section 5*/

ax0 = 15;

/*set the RFSDIV reg = 15*/

/*= > the frame sync pulse for every 16 SCLK*/

/*if frame sync pulse in every 15 SCLK, ax0 = 14*/

dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/

rti;

/* */

dm(0x3FF4) = ax0;

/*to setup interrupt*/

ifc = 0x0066;

/*end of SPORT0 receive interrupt*/

/*code vectors here upon /IRQE int*/

/*code vectors here upon BDMA interrupt*/

/*code vectors here upon SPORT1 TX (IRQ1) int*/

/*code vectors here upon SPORT1 RX (IRQ0) int*/

/*code vectors here upon TIMER int*/

/*code vectors here upon POWER DOWN int*/

/*clear any extraneous SPORT interrupts*/

/*IRQXB = level sensitivity*/

rti; rti; rti; rti;

icntl = 0;

/*disable nesting interrupt*/

/*bit 0 = timer int = 0*/

imask= 0x0020;

/*bit 1 = SPORT1 or IRQ0B int = 0*/

/*bit 2 = SPORT1 or IRQ1B int = 0*/

/*bit 3 = BDMA int = 0*/

/*Section 2: Conﬁgure SPORT0*/

start:

/*to conﬁgure SPORT0 control reg*/

/*bit 4 = IRQEB int = 0*/

/*bit 5 = SPORT0 receive int = 1*/

/*bit 6 = SPORT0 transmit int = 0*/

/*bit 7 = IRQ2B int = 0*/

/*SPORT0 address = 0X3FF6*/

/*RFS is used for frame sync generation*/

/*RFS0 is internal, TFS is not use*/

/*bit 0-3 = Slen*/

/*F = 15 = 1111*/

/*E = 14 = 1110*/

/*D = 13 = 1101*/

/*bit 4,5 data type right justiﬁed zero ﬁlled MSB*/

/*bit 6 INVRFS = 0*/

/*enable SPORT0 receive interrupt*/

/*Section 4: Conﬁgure System Control Register and Start Communication*/

/*to conﬁgure system control reg*/

ax0 = dm(0x3FFF);

ay0 = 0xFFF0;

ar = ax0 AND ay0;

ay0 = 0x1000;

/*read the system control reg*/

/*set wait state to zero*/

ar = ar OR ay0;

dm(0x3FFF) = ar;

/*bit12 = 1, enable SPORT0*/

/*bit 7 INVTFS = 0*/

/*bit 8 IRFS = 1 receive internal frame sync*/

/*bit 9,10,11 are for TFS (don’t care)*/

/*bit 12 TFSW = 1 receive is Normal mode*/

/*bit 13 RTFS = 1 receive is framed mode*/

/*bit 14 ISCLK internal = 1*/

/*frame sync pulse regenerated automatically*/

cntr = 5000;

do waitloop until ce;

nop;

/*bit 15 multichannel mode = 0*/

/*normal mode, bit12 = 0*/

ax0 = 0x6B0D;

/*if alternate mode bit12 = 1, ax0 = 0x7F0E*/

dm (0x3FF6) =ax0;

nop;

waitloop: nop;

rts;

.endmod;

1400fa

17

LTC1400

U

TYPICAL APPLICATIO S

Quick Look Circuit for Converting Data to Parallel Format

5V

1

8

V

SS

5V

CC

+

CONV

10µF

0.1µF

10

SRCLR

LTC1400

7

6

5

12

11

14

13

15

1

2

3

4

5

6

7

9

CONV

CLK

RCK

QA

QB

QC

QD

QE

D0

D1

D2

D3

D4

D5

D6

D7

ANALOG INPUT

(0V TO 4.096V)

2

3

A

V

IN

2.42V

REFERENCE

OUTPUT

SRCK

74HC595

REF

+

4

GND

D

SER

10µF

0.1µF

OUT

QF

G

QG

QH

QH'

3-WIRE SERIAL

INTERFACE LINK

10

SRCLR

12

11

14

13

15

1

2

3

4

5

6

7

9

RCK

QA

QB

QC

QD

QE

D8

D9

D10

D11

REFRDY

SRCK

74HC595

CLK

SER

QF

G

QG

QH

QH'

1400 TA03

1400fa

18

W

BLOCK DIAGRA

LTC1400

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

7

5

8

6

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

1

3

4

2

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.016 – 0.050

0.406 – 1.270

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

SO8 0695

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1400fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC1400

U

TYPICAL APPLICATIO S

LTC1400 Interface to TMS320C50

TMS320C50

5V

TCLKX

TCLKR

TFSX

1

2

6

7

V

A

CLK

CC

IN

UNIPOLAR

INPUT

+

CONV

LTC1400

TFSR

0.1µF

10µF

5

3

TDR

V

D

REF

OUT

+

GND

4

SS

8

0.1µF

10µF

1400 TA04a

LTC1400 Interface to ADSP2181

ADSP2181

5V

1

2

6

7

SCLKO

RFSO

DR0

CLK

V

A

CC

IN

UNIPOLAR

INPUT

+

CONV

LTC1400

10µF

0.1µF

3

5

V

D

REF

OUT

+

GND

SS

8

0.1µF

10µF

4

1400 TA05a

RELATED PARTS

PART NUMBER

LTC1285/LTC1288

LTC1286/LTC1298

LTC1290

DESCRIPTION

COMMENTS

12-Bit, 3V, 7.5/6.6ksps, Micropower Serial ADCs

0.48mW, 1 or 2 Channel Input, SO-8

12-Bit, 5V 12.5/11.16ksps, Micropower Serial ADCs

12-Bit, 50ksps 8-Channel Serial ADC

1.25mW, 1 or 2 Channel Input, SO-8

5V or ± 5V Input Range, 30mW, Full-duplex

5V or ± 5V Input Range, 30mW, Half-duplex

3V, 15mW, MSOP Package

LTC1296

12-Bit, 46.5ksps 8-Channel Serial ADC

LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADCs

LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADCs

3V, 14mW, 2-Channel Differential Inputs, MSOP Package

5V or ± 5V, 20mW, Internal Reference, SSOP-16

5V, Conﬁgurable Bipolar or Unipolar Inputs to ±10V

1.22mW, 1-/2-Channel Inputs, MSOP and SO-8

4.25mW, 1-/2-Channel Inputs, MSOP and SO-8

1.22mW, 1-/2-Channel Inputs, MSOP and SO-8

4.25mW, 1-/2-Channel Inputs, MSOP and SO-8

LTC1417

LTC1609

14-Bit, 400ksps Serial ADC

16-Bit, 200ksps Serial ADC

LTC1860L/LTC1861L 12-Bit, 3V, 150ksps Serial ADCs

LTC1860/LTC1861 12-Bit, 5V, 250ksps Serial ADCs

LTC1864L/LTC1864L 16-Bit, 3V, 150KSPS Serial ADCs

LTC1864/LTC1864 16-Bit, 5V, 250ksps Serial ADCs

1400fa

LT 0606 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

 LINEAR TECHNOLOGY CORPORATION 2006

(408)432-1900 FAX: (408) 434-0507 www.linear.com


型号：	1400I
厂家：	Linear
描述：	Complete SO-8, 12-Bit, 400ksps ADC with Shutdown 完整的SO - 8 ， 12位， 400ksps与关断ADC
文件：	总20页 (文件大小：487K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1400I [Linear]

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