LDNC [Linear]
High Voltage Monolithic Inverter and Dual Boost; 高压变频器单片和双升压
| 型号： | LDNC |
| 厂家： | 
Linear |
| 描述： | High Voltage Monolithic Inverter and Dual Boost |
| 文件： | 总24页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3587
High Voltage Monolithic
Inverter and Dual Boost
FEATURES
DESCRIPTION
The LT®3587 provides a one chip solution for applications
requiring two positive and one negative high voltage sup-
plies. The LT3587 input voltage range of 2.5V to 6V makes
it ideal for various battery-powered systems.
n
Ideal for CCD, LCD, LED Backlight and OLED
Applications
n
Easy Generation of 15V (50mA), –8V (100mA) and
20V (20mA) from a Li-Ion Cell
n
V
Range: 2.5V to 6V
VIN
Asingleresistorprogramseachofthethreeoutputvoltage
levelsandtheoutputcurrentofBoost3.Theintelligentsoft-
start allows for sequential soft-start of the Boost1 output
followed by the negative output with a single capacitor.
Internalsequencingcircuitryalsodisablestheinverteruntil
the Boost1 output has reached 87% of its final value.
n
Wide Output Ranges: Up to 32V for the Boosts and
Up to –32V for the Inverter
n
n
Output Disconnect for the Boost Channels
Boost3 Allows Voltage Programming and/or Current
Programming for a ‘One Wire Current Source’
Overload Fault Protection with Fault I/O Pin Indicator
Combined Soft-Start and Enable Pins
n
n
n
The LT3587 integrates all the power switches, soft-start,
and output-disconnect circuits into a small 3mm × 3mm
QFN package. This high level of integration combined
with small external components makes the LT3587 ideal
for space constrained applications.
Small 20-Pin 3mm × 3mm QFN Package
APPLICATIONS
n
Digital Still and Video Cameras
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Scanner and Display Systems
n
PDA, Cellular Phones and Handheld Computers
LED Backlight and OLED Display Drivers
CCD Imager Bias
General High Voltage Supply Bias
n
n
n
TYPICAL APPLICATION
Li-Ion Powered Supply for CCD Imager and Six White Backlight LEDs
V
VIN
2.5V TO 6V
10μH
Efficiency Curve
15μH
1μF
90
85
80
75
70
65
60
55
50
800
700
600
500
400
300
200
100
0
+
–
CDD = 50mA
+
CDD
2.2μF
10μF
1M
SW3
CAP3
V
SW1
CAP1
CDD = 100mA
IN
LED = 20mA
CCD POSITIVE
15V, 50mA
I
V
OUT1
FB3
8.06k
ALL CHANNELS
ENABLED
FB1
GND
2.7pF
LT3587
2.2μF
–
CDD
LED DRIVER
20mA, UP TO 6 LEDS
V
EN/SS1
EN/SS3
FLT
OUT3
LED
POWER DISSIPATION
ALL CHANNELS
ENABLED
V
FB3
1M
FB2
SW2
6.8pF
15μH
15μH
0
0.5
1
1.5
V
VIN
2.5V TO 6V
NORMALIZED CURRENT
CCD NEGATIVE
–8V, 100mA
3587 TA01b
22μF
3587 TA01a
3587fc
1
LT3587
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V ..............................................................................6V
IN
Soft-Start Input Pins
20 19 18 17 16
EN/SS1, EN/SS3 .....................................................6V
Feedback Pins
FB1
V
15
14
13
12
11
V
1
2
3
4
5
OUT3
CAP3
SW3
GND
FLT
OUT1
FB1, FB2, I , V ................................. –0.2V to 6V
FB3 FB3
CAP1
GND
SW1
21
8
High Voltage Switch Pins
SW1, SW2, SW3...................................................40V
High Voltage Output Pins
6
7
9 10
CAP1, CAP3, V
, V
...................................32V
OUT1 OUT3
Bidirectional I/O Pin
UD PACKAGE
20-LEAD (3mm s 3mm) PLASTIC QFN
= 68°C/W, θ = 4.2°C/W
FLT..........................................................................6V
FLT Current ........................................................10mA
Operating Junction Temperature Range.. –40°C to 125°C
Storage Temperature Range...................–65°C to 125°C
θ
JA
JC
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
20-Lead (3mm × 3mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
LT3587EUD#PBF
LT3587EUD#TRPBF
LDNC
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN = 3.6V, VEN/SS1 = VEN/SS3 = VVIN unless otherwise noted (Note 2, 3).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Input Voltage Range
Quiescent Current
2.5
6
4
V
V
V
= 0V, V
= V OR
2.4
mA
EN/SS1
EN/SS1
EN/SS1
EN/SS3
VIN
= V , V
= 0V OR
VIN EN/SS3
= V
= V
VIN
EN/SS3
Not Switching
V
= V
= 0V, In Shutdown
5.5
1
9
μA
MHz
%
EN/SS1
EN/SS3
l
l
Switching Frequency
0.8
87
1.2
Maximum Duty Cycle
93
50
16
1.0
Minimum On Time
70
ns
Power Fault Delay from Any Output to FLT
FLT Input Threshold Low
FLT Leakage Current
ms
V
l
l
l
0.4
1.6
1
V
FLT
= 5V
μA
V
FLT Voltage Output Low
I
FLT
= 1mA
0.4
3587fc
2
LT3587
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN = 3.6V, VEN/SS1 = VEN/SS3 = VVIN unless otherwise noted (Note 2, 3).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Boost1
CAP1 Bias Current
FB1 Reference Voltage
V
= 15V, V
= Open
OUT1
60
1.22
15
150
1.25
μA
V
CAP1
l
l
1.19
14.25
800
V
Output Voltage
R
= 1MΩ
15.75
V
OUT1
FB1
SW1 Current Limit
SW1 V
990
200
0.1
mA
mV
μA
V
I
= 400mA
= 15V
CESAT
SW1
SW1 Leakage Current
V
V
5
SW1
EN/SS1 for Full Inductor Current
EN/SS1 Shutdown Voltage Threshold
EN/SS1 Pin Bias Current
= 1.1V, V = 0.1V
2.5
FB1
FB2
l
0.2
–0.5
100
V
V
V
V
= 0V
–1
155
5
–1.5
μA
mA
Ω
EN/SS1
V
OUT1
Current Limit
= 15V
CAP1
CAP1
CAP1 to V
On-Resistance (R
)
= 15V, I = 50mA
VOUT1
8
1
OUT1
DISC1
V
Disconnect Leakage
V
VIN
= V
= 6V, V = 0V
VOUT1
0.1
μA
OUT1
CAP1
Inverter
l
l
FB2 Reference Voltage
Output Voltage
SW2 Current Limit
–10
–7.5
900
5
–8
20
mV
V
R
= 1Mꢀ
–8.5
FB2
1090
250
0.1
87
mA
mV
μA
%
SW2 V
I
= 600mA
= 15V
CESAT
SW2
SW2 Leakage Current
V
SW2
5
FB1 Threshold to Start Negative Channel
Boost3
Percent of Final Regulation Value
90
CAP3 Bias Current
V
= 15V, V
= Open
OUT3
70
20
150
22
μA
mA
V
CAP3
l
l
l
Boost3 Programmed Current
R
= 8.06kꢀ
= 1Mꢀ, I
= 1Mꢀ, I
18
0.77
14
IFB3
V
V
Reference Voltage
R
= 20mA
0.8
15
0.83
16
FB3
VFB3
VOUT3
VOUT3
Output Voltage
R
= 20mA
V
OUT3
VFB3
SW3 Current Limit
SW3 V
400
480
250
0.1
mA
mV
μA
V
I
= 200mA
SW3
CESAT
SW3 Leakage Current
V
= 15V
5
2
SW3
EN/SS3 for Full Inductor Current
EN/SS3 Shutdown Voltage Threshold
EN/SS3 Pin Bias Current
V
= V
= 0.6V
VFB3
IFB3
l
0.2
–0.5
70
V
V
= 0V
–1
110
10
–1.5
μA
mA
ꢀ
EN/SS3
V
OUT3
Current Limit
V
= 15V, V
= 0V
CAP3
CAP3
IFB3
CAP3 to V
On Resistance (R
)
V
= 15V, I
= 20mA
15
1
OUT3
DISC3
VOUT3
V
OUT3
Disconnect Leakage
V
= V
= 6V, V = 0V
VOUT3
0.1
29
μA
V
VIN
CAP3
CAP3 Pin Overvoltage Clamp
27
31
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: The LT3587 is guaranteed to meet specified performance from
0°C to 125°C. Specifications over the –40°C to 125°C operating range are
assured by design, characterization and correlation with statistical process
controls.
3587fc
3
LT3587
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at T = 25°C unless otherwise noted.
A
Quiescent Current
When On But Not Switching
vs Input Supply Voltage
Shutdown Quiescent Current
vs Input Supply Voltage
VIN UVLO Voltage vs Temperature
3.5
3.0
2.5
2.0
1.5
2.20
2.15
2.10
2.05
2.00
10
8
V
= EN/SS1 = EN/SS3 = 3.6V
V
= 3.6V
VIN
VIN
125°C
90°C
FB1 = V
= 1.5V
FB3
= 0V
FB3
EN/SS1 = EN/SS3 = 0V
125°C
FB2 = I
90°C
25°C
25°C
6
–40°C
–40°C
4
2
2.5
3
3.5
4
4.5
5
5.5
6
–50 –25
0
25
50
75 100 125
2.5
3
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3587 G02
3587 G03
3587 G01
FB2 Regulation Voltage
vs Temperature
FB1, VFB3 and IFB3 Regulation
Voltage vs Temperature
15
10
5
1.240
1.230
1.220
1.210
1.200
0.825
V
= 3.6V
= 1MΩ
= 100mA
V
R
R
= 3.6V
= R
VIN
FB2
VIN
FB1
R
I
= 1MΩ
VFB3
= 8.06kΩ
VNEG
IFB3
I
I
= 50mA
= 20mA
VOUT1
VOUT3
0.813
0.800
0.788
0.775
V
FB3
V
IFB3
0
FB1
–5
–10
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3587 G05
3587 G04
FB2 Bias Current in Regulation
vs Temperature
FB1, VFB3, IFB3 Bias Current in
Regulation vs Temperature
14.50
14.25
14.00
13.75
13.50
13.25
13.00
106
104
102
100
98
–7.75
–7.85
–7.95
–8.05
–8.15
–8.25
V
= 3.6V
VIN
FB2
R
I
=1MΩ
I
= 100mA
VFB3
VNEG
I
FB1
I
IFB3
V
R
R
= 3.6V
VIN
FB1
= R
=1MΩ
VFB3
=8.06kΩ
= 50mA
= 20mA
96
IFB3
I
I
VOUT1
VOUT3
94
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3587 G06
3587 G07
3587fc
4
LT3587
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
Switches Current Limit
Switching Frequency
vs Temperature
vs Temperature
Switches VCESAT vs Current
0.5
0.4
0.3
0.2
0.1
0
1.2
1.20
1.10
1.00
0.90
0.80
V
= 3.6V
SW3
V
= 3.6V
V
= 3.6V
VIN
VIN
VIN
DUTY CYCLE = 60%
1.0
0.8
0.6
0.4
0.2
0
SW2
SW1
SW1
SW2
SW3
0
0.2
0.4
0.6
0.8
1
1.2
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
SW CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3587 G09
3587 G10
3587 G08
SW1 and SW2 Current Limit
vs EN/SS1 Voltage
SW3 Current Limit
vs EN/SS3 Voltage
Switches Current Limit
vs Duty Cycle
1.6
1.2
0.8
0.4
0
0.5
0.4
0.3
0.2
0.1
0
2.5
2.0
1.5
1.0
0.5
0
V
= 3.6V
V
= 3.6V
VIN
V
= 3.6V
VIN
VIN
SW2
DUTY CYCLE = 60%
SW3
SW2
SW1
SW1
SW3
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
0
10 20 30 40 50 60 70 80 90 100
EN/SS1 VOLTAGE (V)
EN/SS3 VOLTAGE (V)
DUTY CYCLE (%)
3587 G12
3587 G13
3587 G11
EN/SS1, EN/SS3 Pull-Up Current
In Shutdown vs Temperature
Output Disconnects On Resistance
Output Disconnects Current Limit
vs Temperature
vs Temperature (RDISC1, RDISC3
)
14
12
10
8
200.0
167.5
135.0
102.5
70
1.50
1.25
1.00
0.75
0.50
V
I
= 3.6V
V
V
= 3.6V
= V = 15V
VOUT3
V
= 3.6V
VIN
VIN
VOUT1
VIN
= 50mA
= 20mA
EN/SS1 = EN/SS3 = 0V
VOUT1
VOUT3
I
I
R
DISC3
VOUT1
R
DISC1
6
I
VOUT3
4
2
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3587 G14
3587 G15
3587 G16
3587fc
5
LT3587
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at T = 25°C unless otherwise noted.
A
EN/SS1, EN/SS3 Shutdown
Threshold vs Temperature
CAP3 Overvoltage Clamp
vs Temperature
0.45
0.40
0.35
0.30
0.25
0.20
31
30
29
28
27
V
= 3.6V
V
VIN
= 3.6V
VIN
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3587 G17
3587 G18
PIN FUNCTIONS
V
(Pin 1): Boost3 Output Pin. This pin is the drain of
FB2 (Pin 6): Inverter Output Voltage Feedback Pin. Con-
nect a resistor R from this pin to the Inverter Output
OUT3
an output disconnect PMOS transistor.
FB2
(V ) such that:
NEG
CAP3 (Pin 2): Boost3 Output Capacitor Pin. This pin is the
sourceofanoutputPMOSdisconnect.Connectacapacitor
from this pin to ground.
R
= |V |/8μA
NEG
FB2
Note that FB2 pin voltage is about 0V when in regulation.
There is an internal 153k resistor from the FB2 pin to the
internal reference.
SW3 (Pin 3): Boost3 Switch Pin. Connect an inductor
from this pin to V . Minimize trace area at this pin to
IN
minimize EMI.
SW2 (Pin 9): Inverter Switch Pin. Connect an inductor
GND (Pin 4, 7, 8, 12): Ground Pins.
between this pin and V , as well as the flying capacitor
IN
from this pin to the anode of the lnverter ground return
FLT (Pin 5): Fault Pin. This pin is a bidirectional open-
drain pull-down pin. This pin pulls low when any of the
enabled outputs fall out of regulation for more than 16ms.
Each output is ignored during start-up until its respective
enable/soft-start pin allows for full inductor current. This
pin can also be externally forced low to disable all the
supply outputs. Once this pin goes low (either due to an
out of regulation condition or externally forced low), the
pin latches low until the inputs to EN/SS1 and EN/SS3 are
set low or the input supply pin is recycled. Pull up this pin
diode. Minimize trace area at this pin to minimize EMI.
NC (Pin 10): No Connect Pin. Leave open or connect to
ground.
SW1 (Pin 11): Boost1 Switch Pin. Connect an inductor
from this pin to V . Minimize trace area at this pin to
IN
minimize EMI.
CAP1 (Pin 13): Boost1 Output Capacitor Pin. This pin
is the source of an output PMOS disconnect. Connect a
capacitor from this pin to ground.
to V with a 200k resistor when not used.
IN
3587fc
6
LT3587
PIN FUNCTIONS
V
(Pin 14): Boost1 Output Pin. This pin is the drain
V
(Pin 20): Boost3 Output Voltage Feedback Pin. Con-
OUT1
FB3
of an output disconnect PMOS transistor.
nect a resistor R
such that:
from this pin to V
(or CAP3)
VFB3
OUT3
FB1 (Pin 15): Boost1 Output Voltage Feedback Pin. Con-
nect a resistor R
such that:
from this pin to V
(or CAP1)
R
= ((V /0.8V) – 1) • 56.3k
VOUT3
FB1
OUT1
VFB3
There is an internal 56.3k resistor from the V
pin to
VFB3
FB3
R
= ((V /1.22V) – 1) • 88.5k
VOUT1
ground. In the current regulator configuration, R
can
FB1
be optionally used to limit the maximum output voltage
There is an internal 88.5k resistor from the FB1 pin to
ground.
to V
, such that:
CLAMP
R
= ((V
/0.8V) – 1) • 56.3k
CLAMP
VFB3
EN/SS1(Pin16):Boost1/InverterShutdownandSoft-Start
Pin. Boost1 and Inverter are enabled when the voltage
on this pin is greater than 2.5V. They are disabled when
the voltage is below 0.2V. An internal 1μA current source
in conjunction with an external capacitor can be used to
ramp this pin and provide soft-start.
Note: When no voltage clamp is desired in the current
regulator configuration, tie V to GND.
FB3
ExposedPad(Pin21):GroundPin.ConnecttoPCBground
plane.Groundplaneconnectionthroughmultipleviasunder
the package is recommended for optimum electrical and
thermal performance.
V (Pin 17): Input Supply Pin. Must be locally bypassed
IN
with an X5R or X7R type ceramic capacitor.
EN/SS3 (Pin 18): Boost3 Shutdown and Soft-Start Pin.
Boost3 is enabled when the voltage on this pin is greater
than 2V. It is disabled when the voltage is below 0.2V. An
internal 1μA current source in conjunction with an exter-
nal capacitor can be used to ramp this pin and provide
soft-start.
I
(Pin 19): Boost3 Output Current Programming Pin.
FB3
Connect a resistor R
from this pin to ground such
IFB3
that:
R
= 200 • (0.8V/I
)
IFB3
VOUT3
If Boost3 output is configured as a voltage regulator,
can be optionally used to limit the maximum output
R
IFB3
current to I
:
LIMIT
R
IFB3
= 200 • (0.8V/I
)
LIMIT
Note: Tie I to GND when no current limit is desired.
FB3
3587fc
7
LT3587
BLOCK DIAGRAM
V
IN
V
IN
1μA
EN/SS3
L4
SW3
C5
SOFT-
+
OVERVOLTAGE
PROTECTION
+
–
V
REF
0.8V
START
D
A8
S3
–
200mV
V
C3
CAP3
A5
–
+
X3
S
C4
FLT
A6
Q3
Q
R
M2
M3
V
OUT3
V
OUT3
R
VFB3
V
MAX
Σ
V
FB3
DISCONNECT
CONTROL
56.3k
RAMP
GENERATOR
SHDN3
I
V
IN
FB3
V
IN
R
100k
FLT
IFB3
EN/SS3
C6
EN/SS1
EN/SS3
FLT
PTAT BIAS
V
IN
R
FILTER
AND
S
Q
V
C1
V
C2
V
C3
BANDGAP
AND LDO
OSCILLATOR
16ms
DELAY
L1
V
SW1
OUT1
R
D
FB1
S1
–
EN/SS1
A3
CAP1
V
C1
X1
S
FB1
–
+
A1
C1
88.5k
FLT
M1
+
Q
Q1
R
V
OUT1
DISCONNECT
CONTROL
Σ
–
200mV
V
REF
1.22V
A7
+
RAMP
GENERATOR
SHDN1
V
IN
1μA
EN/SS1
SOFT-
START
C3
V
IN
SEQUENCING
153k
L2
FB2
–
+
SW2
V
C2
X2
S
A2
–
R
FB2
A4
Q
Q2
R
V
NEG
GND
+
C2
Σ
D
S2
RAMP
GENERATOR
L3
V
NEG
C7
3587 F01
Figure 1. Block Diagram
3587fc
8
LT3587
OPERATION
All three channels of the LT3587 use a constant frequency,
current mode control scheme to provide voltage and/or
current regulation at the output. Operation can be best un-
derstood by referring to the Block Diagram in Figure 1.
200mV, the bandgap reference, the start-up bias and the
oscillators are also turned on. The SR latch X3 is set at
the start of each oscillator cycle which turns on the power
switch Q3. Q3 turns off based on its own feedback loop,
whichconsistsoferroramplifierA5andPWMcomparator
A6. The level at the negative input of A6 is set by the error
amplifier A5, and is an amplified version of the difference
between the reference voltage of 0.8V and the maximum
If EN/SS1 is pulled higher than 200mV, the bandgap refer-
ence, the start-up bias and the oscillator are turned on. At
the start of each oscillator cycle, the SR latch X1 is set,
whichturnsonthepowerswitchQ1.Avoltageproportional
to the switch current is added to a stabilizing ramp and
the resulting sum is fed into the positive terminal of the
PWM comparator A3. When this voltage exceeds the level
atthenegativeinputofA3, theSRlatchX1isreset, turning
off the power switch Q1. The level at the negative input
of A3 is set by the error amplifier A1, which is simply an
amplified version of the difference between the reference
voltage of 1.22V and the feedback voltage. In this manner,
the error amplifier sets the correct peak switch current
level to keep the output voltage in regulation. If the error
amplifier output increases, more current is delivered to
the output; if it decreases, less current is delivered.
of the two feedback voltages at V and I . A separate
FB3
FB3
comparator (not shown) sets the maximum current limit
on Q3.
The I
pin is pulled up internally with a current that
FB3
is (1/200) times the load current out of the V
pin.
OUT3
Therefore, an external resistor connected from this pin
to ground generates a feedback voltage proportional to
the V
output load current at the I
FB3
pin. When the
FB3
OUT3
FB3
voltage at V is higher than the voltage at I , the third
channelregulatestothefeedbackvoltageatV , whichin
normal application is a divided down voltage from V
FB3
.
OUT3
In this state, the third channel behaves as a boost voltage
regulator. On the other hand if the voltage at I is higher,
FB3
Thesecondchannelisaninvertingconverter. Thischannel
is also enabled through the EN/SS1 pin. The basic opera-
tion of this second channel is the same as the positive
channel. The SR latch X2 is also set at the start of each
oscillator cycle. The power switch Q2 is turned on at the
same time as Q1. Q2 turns off based on its own feedback
loop, which consists of error amplifier A2 and PWM
comparator A4. The reference voltage of this negative
channel is ground.
the third channel regulates to the feedback voltage at I
,
FB3
which therefore regulates the V
output load current to
OUT3
a particular value. In this state, the third channel behaves
as a boost current regulator.
PMOS M1 is used as an output disconnect pass transistor
forthefirstchannel.M1disconnectstheload(V
)from
OUT1
the input as long as the voltage between CAP1 and V
IN
is less than 2.5V (typical) and the voltage between CAP1
and V is less than 10V (typ). Similarly, PMOS M3 is
OUT1
Voltage clamps (not shown) on the output of the error
amplifiers A1 and A2 enforce current limit on Q1 and Q2
respectively.
used as an output disconnect pass transistor for the third
channel. M3 disconnects the load (V ) from the input
OUT3
when the third channel is in shutdown (EN/SS3 voltage
Similar to the first channel, the third channel is also a
positive boost regulator. If EN/SS3 is pulled higher than
is lower than 200mV) and the voltage between CAP3 and
V
OUT3
is less than 10V (typical).
3587fc
9
LT3587
APPLICATIONS INFORMATION
Inductor Selection
Fortheinvertingchannel,theinrushcurrentflowsfromthe
input through inductor L2, charging the flying capacitor
A 15μH inductor and a 10μH inductor are recommended
for the LT3587 Boost1 channel and Boost3 channel re-
spectively. The inverting channel can use 15μH or 22μH
inductors. Although small size is the major concern for
mostapplications, forhighefficiencytheinductorsshould
have low core losses at 1MHz and low DCR (copper wire
resistance). The inductor DCR should be on the order of
half of the switch on resistance for its channel: 0.5ꢀ for
Boost1,0.4ꢀfortheinverterand1ꢀforBoost3.Forrobust
applications, the inductors should have current ratings
corresponding to their respective peak current during
regulation. Furthermore, with no soft-start, the inductor
should also be able to withstand temporary high start-up
currents of 1A, 1.1A and 480mA for the Boost1, inverter
and Boost3 channels respectively (typ, refer to the Typical
Performance Characteristics curves).
C2 and returning through the Schottky diode D .
S2
The selection of inductor and capacitor values should
ensure that the peak inrush current is below the rated
momentary maximum current of the Schottky diodes. The
peak inrush current can be estimated as follows:
−1
tan−1(ϕ)
(VVIN − 0.6)•e ϕ
IP =
L
C
4L
R2C
ϕ =
−1
where L is the inductance, C is the capacitance and R is
thetotalseriesresistanceintheinrushcurrentpath, which
includes the resistance of the inductor and the Schottky
diode. Note that in this equation, we model the Schottky
as having a fixed 0.6V drop.
Capacitor Selection
The small size of ceramic capacitors makes them suitable
for LT3587 applications. X5R and X7R types of ceramic
capacitors are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 1μF input ca-
pacitor is sufficient for most LT3587 applications. The
output capacitors required for stability depend on the
application. For most applications, the output capacitor
values required are: 10μF for the Boost1 channel, 22μF
for the inverter channel and 2.2μF for the Boost3 chan-
nel. The inverter requires a 2.2μF flying capacitor. Note
that this flying capacitor needs a voltage rating of at least
Table 1 gives inrush peak currents for some component
selections. Note that inrush current is not a concern if the
input voltage rises slowly.
Table 1. Inrush Peak Current
V
(V)
R (Ω)
0.68
L (μH)
15
C (μF)
10
I (A)
VIN
P
5
5
5
2.48
1.19
1.64
1.64
0.80
1.10
0.68
22
2.2
2.2
10
0.68
10
3.6
3.6
3.6
0.745
0.745
0.745
15
22
2.2
2.2
V + |V |.
IN
NEG
10
Inrush Current
Schottky Diode Selection
For any of the external diode (D , D and D ) selec-
tions, besides having sufficiently high reverse breakdown
voltagetowithstandtheoutputvoltage, bothforwardvolt-
age drop and diode capacitance need to be considered.
Schottkydiodesratedforhighercurrentusuallyhavelower
forward voltage drops and larger capacitance. Although
lower forward voltage drop is good for efficiency, a large
When a supply voltage is abruptly applied to the V pin,
IN
S1 S2
S3
the voltage difference between the V pin and the CAP
IN
pins generates inrush current. For the case of the Boost1
channel, the inrush current flows from the input through
the inductor L1 and the Schottky D to charge the Boost1
S1
output capacitor C1. Similarly for the Boost3 channel, the
inrush current flows from the input through the inductor
L4andtheSchottkyD tochargetheoutputcapacitorC4.
S3
3587fc
10
LT3587
APPLICATIONS INFORMATION
capacitancewillslowdowntheswitchingwaveform,which
can cause significant switching losses at 1MHz switch-
ing frequency. Some recommended Schottky diodes are
listed in Table 2.
The same constraints as the other Schottky diodes ap-
ply for selecting D3. Therefore, the same recommended
Schottky diodes in Table 2 can be used for D3.
Boost3 Overcurrent and Overvoltage Protection
Table 2. Recommended Schottky Diodes
As briefly discussed in the Operation section, the regula-
tion loop of Boost3 uses the maximum of the two voltages
at V and I as feedback information to set the peak
current of its power switch Q3. This allows for the Boost3
loop to be configured as either a boost voltage regulator
or a boost current regulator (Figure 3). Furthermore, this
architecturealsoallowsforaprogrammablecurrentlimiton
voltage regulation or voltage limit on current regulation.
DIODE
FORWARD FORWARD CAPACI-
PART
NUMBER
CURRENT VOLTAGE
TANCE
FB3
FB3
(mA)
DROP (V) (pF at 10V) MANUFACTURER
RSX051VA-30
1000
0.35
30
ROHM
www.rohm.com
PMEG401OCEJ
PMEG2005EB
IR05H40CSPTR
500
500
500
0.49
0.43
0.48
25
8
NXP/Phillips
www.nxp.com
39
Vishay
www.vishay.com
V
V
VIN
VIN
B0540WS
ZLLS400
500
520
0.48
0.53
20
17
Diodes Inc.
www.diodes.com
V
SW3
CAP3
V
SW3
CAP3
IN
IN
Zetex
www.zetex.com
LT3587
BOOST3
VOLTAGE
LT3587
BOOST3
V
V
OUT3
OUT3
CURRENT
REGULATOR
R
R
VFB3
VFB3
REGULATOR
Smaller Footprint Inverter Topology
V
V
FB3
FB3
OPTIONAL
VOLTAGE
I
I
FB3
FB3
EN/SS3
EN/SS3
PROGRAMMABLE
VOLTAGE LIMIT
RESISTOR
Incertainapplicationswithhighertoleranceofcurrentripple
attheoutputoftheinverter,theinductorL3canbereplaced
with a Schottky diode. Since the Schottky diode footprint
isusuallysmallerthantheinductorfootprint,thisalternate
topology is recommended if a smaller overall solution is a
must. Note that this topology is only viable if the absolute
REGULATION
FEEDBACK
RESISTOR
R
IFB3
R
IFB3
CURRENT REGULATION
FEEDBACK RESISTOR
3587 F03
OPTIONALPROGRAMMABLE
CURRENT LIMIT RESISTOR
Figure 3. Boost3 Configured as a Voltage
Regulator and as a Current Regulator
value of the inverter output is greater than V .
IN
When configured as a boost voltage regulator, a feedback
resistor from the output pin V to the V pin sets the
ThisSchottkydiodeisconfiguredwiththeanodeconnected
to the output of the inverter and the cathode to the output
end of the flying capacitor C2 as shown in Figure 2.
OUT3
FB3
voltage level at V
at a fixed level. In this case, the I
OUT3
FB3
pin can either be grounded if no current limiting is desired
or connected to ground with a resistor such that:
R
FB1
I
= 200 • (0.8V/R
)
LIMIT
IFB3
1M
LT3587
SW2
FB2
whereI
isthedesiredoutputcurrentlimitvalue.Recall
LIMIT
3587 F02
that the pull-up current on the I pin is controlled to be
FB3
INVERTER
OUTPUT
C2
2.2μF
L2
15μH
typically 1/200 of the output load current at the V
D3
OUT3
–8V, 100mA
V
VIN
pin. In this case, when the load current is less than I
,
2.5V TO 4.5V
LIMIT
the Boost3 loop regulates the voltage at the V
pin to
C7
22μF
FB3
DS2
0.8V. When there is an increase in load current beyond
, the voltage at V starts to drop and the voltage
I
LIMIT
FB3
at I rises above 0.8V. The Boost3 loop then regulates
FB3
Figure 2. Inverter Configured with a Schottky
Diode in Place of the Output Inductor
the voltage at the I
pin to 0.8V, limiting the output
FB3
3587fc
11
LT3587
APPLICATIONS INFORMATION
current at V
to I . Figure 4 compares the transient
LIMIT
lower than 29V is obtained by connecting a resistor from
the V pin to the V pin such that:
OUT3
responses with and without current limit when a current
overload occurs.
OUT3
FB3
R
FB3
= ((V
/0.8V) – 1) • 56.3k
CLAMP
where V
is the desired output voltage clamp level. In
CLAMP
15V
V
VOUT3
5V/DIV
this case, when the voltage level is less than V
, the
CLAMP
Boost3 loop regulates the voltage at the I pin to 0.8V.
FB3
I
20mA
VOUT3
Whentheoutputloadfailsopen-circuitorisdisconnected,
13mA/DIV
LOAD STEP
the voltage at I drops to reflect the lower output current
FB3
I
L4
and the voltage at V
starts to rise. When the voltage
, the Boost3 loop then regulates
FB3
CLAMP
200mA/DIV
at V
rises to V
OUT3
the voltage at the V
pin to 0.8V, limiting the voltage
. Figure 5 contrasts the transient
FB3
CLAMP
3587 F04a
level at V
to V
200μs/DIV
OUT3
V
= 3.6V
VIN
WITHOUT CURRENT LIMIT: I
CONNECTED TO GND
FB3
responses with and without programmed V
the output load is disconnected.
when
CLAMP
V
STAYS AT 15V, OUTPUT CURRENT
OUT3
INCREASES FROM 20mA TO 40mA
15V
V
VOUT3
20V
V
VOUT3
5V/DIV
10V/DIV
OUTPUT LOAD
DISCONNECTED
I
20mA
VOUT3
13mA/DIV
LOAD STEP
I
L4
200mA/DIV
I
L4
200mA/DIV
3587 F05a
200μs/DIV
WITHOUT PROGRAMMED OUTPUT VOLTAGE
CLAMP: V CONNECTED TO GND
V
= 3.6V
VIN
3587 F04b
200μs/DIV
V
= 3.6V
VIN
FB3
WITH 20mA CURRENT LIMIT: R
OUTPUT CURRENT STAYS AT 20mA,
DROPS FROM 15V TO 7.5V
= 8.06k
IFB3
V
OUT3
Figure 4. Boost3 Waveform in an Output Current
Overload Event with and Without Output Current Limit
20V
V
VOUT3
10V/DIV
OUTPUT LOAD
DISCONNECTED
The LT3587 CAP3 pin has an internal overvoltage protec-
tion. When the voltage at the CAP3 pin is driven above
29V (typ), the Boost3 loop is disabled and the SW3 pin
stops switching.
I
L4
200mA/DIV
3587 F05b
When configured as a boost current regulator, a feedback
200μs/DIV
V
= 3.6V
VIN
WITH PROGRAMMED OUTPUT
VOLTAGE CLAMP AT 24V
resistor from the I pin to ground sets the output cur-
FB3
rent at V
at a fixed level. In this case, if the V pin is
grounded then the overvoltage protection defaults to the
OUT3
FB3
Figure 5. Boost3 Output Open-Circuit Waveform with
and Without Programmed Output Voltage Clamp
open-circuit clamp voltage level of 29V. A voltage clamp
3587fc
12
LT3587
APPLICATIONS INFORMATION
Setting The Output Voltages and The Boost3 Output
Current
Connecting a capacitor from the EN/SS3 pin to ground
sets up a soft-start ramp for the Boost3 channel. As the
1μA current charges up the capacitor, the Boost3 regula-
tion loop is enabled when the EN/SS3 pin voltage goes
The LT3587 has a trimmed internal feedback resistor. A 1M
feedbackresistorfromeachoutputpintoitscorresponding
feedbackpinsetstheoutputsto15VforBoost1,–8Vforthe
inverter and 15V for Boost3. Note that only one resistor is
needed to set the output voltage for each channel. Set the
output voltages according to the following formulas:
above 200mV. The V node voltage follows the EN/SS3
C3
voltage as it ramps up ensuring slow start-up on the
Boost3 channel. When the voltage at the EN/SS3 pin is
above 2V, the Boost3 regulation loop is free running with
full inductor current.
R
R
= ((V
/1.22V) – 1) • 88.5k
FB1
FB2
VOUT1
Start Sequencing
= |V |/8μA
NEG
The LT3587 also has internal sequencing circuitry that
inhibits the inverter channel from operating until the feed-
backvoltageoftheBoost1voltage(attheFB1pin)reaches
about 1.1V (87% of the final voltage). This ensures that
the Boost1 output voltage is near regulation before any
negative voltage is generated at the inverter output.
R
= ((V
/0.8V) – 1) • 56.3k
VFB3
VOUT3
Asdescribedinprevioussections,Boost3canbeconfigured
as a boost current regulator. When configured as such, set
the output current according to the following formula:
R
= 200 • (0.8V/I
)
IFB3
VOUT3
Figure 6 contrasts the start-up sequencing without any
soft-start capacitor, and with a 10nF soft-start capacitor.
Inordertomaintainaccuracy, usehighprecisionresistors
when setting any of the channels output voltage and/or
the Boost3 output current (1% is recommended).
Soft-Start
V
EN/SS1
0V
2V/DIV
The LT3587 has two soft-start control pins: EN/SS1 and
EN/SS3. The EN/SS1 pin controls the soft-start for both
the Boost1 and the inverter, while the EN/SS3 pin controls
the soft-start for the Boost3. Each of these soft-start pins
is pulled up internally with a 1μA current source.
I
VIN
0mA
500mA/DIV
V
VOUT1
10V/DIV
0V
0V
V
NEG
10V/DIV
Connecting a capacitor from the EN/SS1 pin to ground
programs a soft-start ramp for the Boost1 and the inverter
channels. Use an open-drain transistor to pull this pin low
to shut down both the Boost1 and the inverter. Turning off
this transistor allows the 1μA pull-up current to charge the
soft-start capacitor. When the voltage at the EN/SS1 pins
goes above 200mV, the regulation loops for Boost1 and
3587 F06a
400μs/DIV
V
EN/SS1
2V/DIV
I
VIN
0mA
500mA/DIV
the inverter are enabled. The V node voltage follows the
C1
V
VOUT1
0V
0V
10V/DIV
EN/SS1 voltage as it continues to ramp up to ensure slow
V
NEG
start-up on the Boost1 channel. The V node follows the
C2
10V/DIV
ramp voltage minus 0.7V. This ensures that the inverter
starts up after the Boost1, but still has a slow ramping
output to avoid large start-up currents. The Boost1 and
the inverter regulation loops are free running with full
inductor current when the voltage at the EN/SS1 pin is
above 2.5V.
3587 F06b
4ms/DIV
Figure 6. VEN/SS1, VOUT1, VNEG, IVIN with No Soft-Start
Capacitor, and with a 10nF Soft-Start Capacitor
3587fc
13
LT3587
APPLICATIONS INFORMATION
Output Disconnect
The output disconnect feature on Boost3 is implemented
similarlyusingM3. However, inthiscaseM3isonlyturned
off when the EN/SS3 pin voltage is less than 200mV and
the Boost3 regulation loop is disabled.
Both the Boost1 and the Boost3 channels have an output
disconnect between their respective CAP pin and V
OUT
IN
pin. This disconnect feature prevents a DC path from V
to V
.
The disconnect transistor M3 is also current limited, pro-
OUT
vidingamaximumoutputcurrentatV
of110mA(typ).
OUT3
ForBoost1, thisoutputdisconnectfeatureisimplemented
using a PMOS (M1) as shown in the Block Diagram in
Figure 1. When turned on, M1 is driven hard in the linear
region to reduce power dissipation when delivering cur-
M3 also has a similar protection circuit as M1 that limits
the voltage drop across CAP3 and V to about 10V.
OUT3
Figure 8 shows the output voltage and current during an
overload event with V initially at 24V.
CAP3
rent between the CAP1 pin and the V
pin. M1 stays
OUT1
on as long as the voltage difference between CAP1 and
V is greater than 2.5V. This allows for the positive bias
IN
I
VOUT3
to stay high for as long as possible as the negative bias
500mA/DIV
0mA
24V
discharges during turn off.
I
L4
500mA/DIV
ThedisconnecttransistorM1iscurrentlimitedtoprovidea
maximumoutputcurrentof155mA(typ).However,thereis
also a protection circuit for M1 that limits the voltage drop
V
CAP3
10V/DIV
V
VOUT3
10V/DIV
across CAP1 and V
to about 10V. When the voltage at
OUT1
CAP1 is greater than 10V, in an overload or a short-circuit
3587 F08a
40μs/DIV
event, M1 current is limited to 155mA until the voltage
across CAP1 to V
grows to about 10V. Then M1 is
OUT1
I
VOUT3
turned on hard without any current limit to allow for the
voltage on CAP1 to discharge as fast as possible. When
500mA/DIV
0mA
I
L4
the voltage across CAP1 and V
reduces to less than
500mA/DIV
OUT1
10V, the output current is then again limited to 155mA.
Figure 7 shows the output voltage and current during an
V
CAP3
24V
10V/DIV
V
VOUT3
overload event with V
initially at 15V.
CAP1
10V/DIV
3587 F08b
40μs/DIV
V
= 3.6V
VIN
C4 = 1μF
I
VOUT1
Figure 8. VCAP3, VVOUT3, IVOUT3 and IL4 During a Short-Circuit
Condition with and Without Programmed 20mA Current Limit
500mA/DIV
0mA
I
L1
500mA/DIV
Choosing A Feedback Node
V
CAP1
15V
15V
10V/DIV
Boost1 feedback resistor, R , may be connected to the
FB1
V
VOUT1
V
pin or the CAP1 pin (see Figure 9). Similarly for
OUT1
10V/DIV
Boost3 in a boost voltage regulator configuration, the
3587 F07
40μs/DIV
V
VIN
= 3.6V
C1 = 4.7μF
feedback resistor, R
, may be connected to the V
VFB3
OUT3
pins
pin or the CAP3 pin. Regulating the V
and V
OUT1
OUT3
Figure 7. VCAP1,VVOUT1, IVOUT1 and IL1 During a Short-Circuit Event
eliminatestheoutputoffsetresultingfromthevoltagedrop
across the output disconnect PMOS transistors.
3587fc
14
LT3587
APPLICATIONS INFORMATION
VVOUT1 +IVOUT1 •RDISC1 −1.22V
13.8μA
VVOUT3 +IVOUT3 •RDISC3 − 0.8V
14.3μA
FLT
B1
B3 SW3
V
IN
SW1
GND
RFB1
RFB3
=
=
EN/SSEN/SS
CAP3
V
CAP1
FB1
FB3
LT3587
R
VFB3
V
I
OUT3
R
FB1
V
FB3
OUT1
DN
SW2
FB2
Fault Detection and Indicator
The LT3587 features fault detection on all its outputs and
a fault indicator pin (FLT). The fault detection circuitry is
enabled only when at least one of the channels has com-
pleted the soft-start process and is free running with full
inductor current. Once the fault detection is enabled, the
FLT
B1
B3 SW3
V
IN
SW1
EN/SSEN/SS
CAP3
GND
CAP1
R
VFB3
LT3587
V
FB3
R
FB1
FB1
V
I
OUT3
Faultpinpullslowwhenanyofthefeedbackvoltages(V
,
FB1
V
FB3
OUT1
DN
SW2
FB2
V
or Max(V
,V )) fall below their regulation value
FB2
VFB3 IFB3
for more than 16ms.
3587 F09
Figure 9. Feedback Connection Using the VOUT and CAP Pins
One particularly important case is an overload or short-
circuitconditiononanyofthechanneloutputs.Inthiscase,
if the corresponding loop is unable to bring the output
back into regulation within 16ms, a fault is detected and
the Fault pin is pulled low.
However, in the case of a short-circuit fault at the V
OUT
pins, the LT3587 will switch continuously because the FB1
or the V pin is low. While operating in this open-loop
FB3
condition, the rising voltage at the CAP pins is limited
only by the protection circuit of their respective output
disconnects. At the worst case, the CAP pin rises to 10V
Note that the fault condition is latched. Once the Fault pin
is pulled low, all the three channels are disabled. In order
to enable any of the channels again, reset the part by shut-
ting it down and then turning it on again. This is done by
first forcing both the EN/SS1 and EN/SS3 pins low below
200mV and then either letting them go high again in a
soft-start process or forcing them high immediately if no
soft-startisdesired.Figure10showsthewaveformswhen
a short-circuit condition occurs at Boost1 for more than
16ms as well as the subsequent resetting of the part.
abovethecorrespondingV
pin. Sointhecaseofshort-
OUT
circuit fault to ground, the voltage on the CAP pins may
reach 10V. When the short-circuit condition is removed,
the V
pins rise up to the voltage on the CAP pins,
OUT
potentiallyexceedingtheprogrammedoutputvoltageuntil
the capacitor voltages fall back into regulation. While this
is harmless to the LT3587, this should be considered in
the context of the external circuitry if short-circuit events
are expected.
V
FLT
Regulating the CAP pins ensures that the voltage on the
OUT
5V/DIV
PART RESET
V
pins never exceeds the set output voltage after a
ENSS1/ENSS3
5V/DIV
short-circuit event. However, this setup does not com-
pensateforthevoltagedropacrosstheoutputdisconnect,
resulting in an output voltage that is slightly lower than
the voltage set by the feedback resistor. This voltage drop
is equal to the product of the output current and the on
resistance of the PMOS disconnect transistor. This drop
can be accounted for when using the CAP pin as the
feedback node by setting the output voltage according to
the following formula:
V
VOUT1
10V/DIV
SHORT
V
AT V
OUT1
NEG
10V/DIV
V
VOUT3
20V/DIV
3587 F10
100ms/DIV
Figure 10. Waveforms During Fault
Detection of a Short-Circuit Event
3587fc
15
LT3587
APPLICATIONS INFORMATION
Besides acting as a fault output indicator, the Fault pin
is also an input pin. If this pin is externally forced low
below 400mV, the LT3587 behaves as if a fault event has
been detected and all the channels turn off. In order to
turn the part back on, remove the external voltage that
forces the pin low and reset the part. Figure 11 shows the
waveforms when the Fault pin is externally forced low and
the subsequent resetting of the part.
Since the programmed V
current is proportional to
OUT3
thecurrentthroughR , theLEDcurrentcanbeadjusted
IFB3
according to the following formula:
I
= (0.8V – V
) • 200/R
DAC-OUT IFB3
VOUT3
A higher DAC output voltage level results in lower LED
current and hence lower overall brightness. Conversely,
a lower DAC output voltage results in higher LED current
andhigherbrightness.NotethattheDACoutputimpedance
should be low enough to be able to sink approximately
1/200 of the desired maximum LED current without any
appreciable error for accurate dimming control.
V
FLT FORCED LOW
PART RESET
FLT
5V/DIV
ENSS1/ENSS3
5V/DIV
Note also that the maximum output current is limited by
the output disconnect current limit to 110mA (typ).
V
VOUT1
10V/DIV
V
NEG
10V/DIV
PWM Dimming
V
VOUT3
20V/DIV
Changing the forward current flowing in the LEDs not
only changes the brightness intensity of the LEDs, it also
changes the color. The chromaticity of the LEDs changes
with the change in forward current. Many applications
cannot tolerate any shift in the color of the LEDs. Control-
ling the intensity of the LEDs with a direct PWM signal
allows dimming of the LEDs without changing the color.
In addition, direct PWM dimming offers a wider dimming
range to the user.
3587 F11
100ms/DIV
Figure 11. Waveforms When the
Fault Pin is Externally Forced Low
Dimming Control For Boost3 Current Regulator as an
LED Driver
As shown on the front page application and the Block Dia-
gram,oneofthemostcommonapplicationsfortheBoost3
channel when configured as a boost current regulator is
a backlight LED driver. In an LED driver application, there
are two different ways to implement a dimming control of
the LED string. The LED current can be adjusted either by
using a digital to analog converter (DAC) with a resistor
V
VIN
2.5V TO 5V
10μH
1μF
V
SW3
IN
CAP3
LT3587
R
IFB3
or by using a PWM signal.
V
LED DRIVER
OUT3
I
EN/SS3
FB3
Using a DAC and a Resistor
R
IFB3
Forsomeapplications,thepreferredmethodofbrightness
controlisusingaDACandaresistor.TheBoost3configura-
tion for using this method is shown in Figure 12.
8.06k
V
DAC
LTC2630
DAC-OUT
3587 F12
Figure 12. Dimming Using a DAC and a Resistor
3587fc
16
LT3587
APPLICATIONS INFORMATION
Dimming the LEDs via a PWM signal essentially involves
turning the LEDs on and off at the PWM frequency. The
typical human eye has a sensitivity limit of ~60Hz. By
increasing the PWM frequency to ~80Hz or higher, the eye
will interpret that the pulsed light source is continuously
on. Additionally, by modulating the duty cycle (amount of
“on-time”), intensity of the LEDs is controlled. The color
of the LEDs remains unchanged in this scheme since the
LED current is either zero or a constant value.
V
VIN
2.5V TO 5V
10μH
V
IN
SW3
1μF
CAP3
LT3587
LED DRIVER
20mA
V
OUT3
I
EN/SS3
FB3
Figure 13 shows a partial application showing an LED
driver for six white LEDs. If the voltage at the CAP3 pin is
higher than 10V when the LEDs are on, direct PWM dim-
ming method requires an external NMOS. This external
NMOS is tied between the cathode of the lowest LED in
the string and ground as shown in Figure 13.
R
IFB3
8.06k
PWM
FREQ
MN1
Si1304BDL
2.5V
0V
A Si1304 logic-level MOSFET can be used since its source
is connected to ground, and it is able to withstand the
3587 F13
open-circuit voltage at the V
pin across its drain and
Figure 13. Six White LEDs Driver With PWM Dimming
OUT3
source. The PWM signal must be applied to the EN/SS3
pin of the LT3587 and the gate of the NMOS. The PWM
signal should traverse between 0V to 2.5V, to ensure
proper turn on and off of the Boost3 regulation loop and
the NMOS transistor MN1. When the PWM signal goes
high, the LEDs are connected to ground and a current of
I
VOUT3
0mA
13mA/DIV
I
L4
0mA
0V
I
= 160V/R
flows through the LEDs. When the
VOUT3
IFB3
200mA/DIV
PWM signal goes low, the LEDs are disconnected and
turned off.
ENSS3
5V/DIV
The output disconnect feature and the external NMOS
ensure that the LEDs quickly turn off without discharging
theoutputcapacitor. ThisallowstheLEDstoturnonfaster.
Figure 14 shows the PWM dimming waveforms for the
circuit in Figure 13.
3587 F14
2ms/DIV
V
= 3.6V
VIN
6 LEDs
Figure 14. PWM Dimming Waveforms
3587fc
17
LT3587
APPLICATIONS INFORMATION
100
1kHz
10
IDEAL
300Hz
1
0.1
MEASURED
100Hz
0.01
1
10
PWM DIMMING RANGE
100
1
10
DUTY CYCLE (%)
100
3587 F16
3587 F15
Figure 15. Average LED Current Variation with
PWM Duty Cycle at 100Hz PWM Frequency
Figure 16. Dimming Range Comparison
of Three PWM Frequencies
The time it takes for the LED current to reach its pro-
grammed value sets the achievable dimming range for a
givenPWMfrequency.Figure15showstheaveragecurrent
variation over duty cycle for a 100Hz PWM frequency with
the circuit in Figure 13.
Example:
f = 100Hz → t
= 1/f = 0.01s, t
= 320μs
PERIOD
MIN-ON
Dim Range = t
/t
= 0.01s/320μs ≈ 30:1
PERIOD MIN-ON
Min Duty Cycle = (t
/t
) • 100 = 3.2%
MIN-ON PERIOD
Notice that at lower end of the duty cycle, the linear rela-
tion between the average LED current and the PWM duty
cycle is no longer preserved. This indicates that the loop
requires a fixed amount of time to reach its final current.
When the duty cycle is reduced such that the amount of
on time is in the order of or less than this settling time, the
loop no longer has the time to regulate to its final current
before it is turned off again and the initial current before
settling is a larger proportion of the average current.
Duty Cycle Range = 100% → 3.2% at 100Hz
Thecalculationsshowthatfora100Hzsignalthedimming
rangeis30to1. Inaddition, theminimumPWMdutycycle
of 3.2% ensures that the LED current varies linearly with
duty cycle to within 10%. Figure 16 shows the dimming
range achievable for three different frequencies with a
minimum on time of 320μs.
The dimming range can be further extended by combin-
ing this PWM method with the DAC and resistor method
discussedpreviously.Inthismannerbothanalogdimming
and PWM dimming extend the dimming range for a given
application. The color of the LEDs no longer remains
constant because the forward current of the LED changes
with the output voltage of the DAC. For the six LED ap-
plication described above, the LEDs can be dimmed first
by modulating the duty cycle of the PWM signal with the
DACoutputat0V.Oncetheminimumdutycycleisreached,
the value of the DAC output voltage can be increased to
further dim the LEDs. The use of both techniques together
allows the average LED current for the six LED application
to be varied from 20mA down to less than 1μA.
Depending on how much linearity on the average LED
current is required, the minimum LED on time is chosen
based on the graphs in Figure 15. For example, for ap-
proximately 10% deviation from linearity at the lower
duty cycle, the minimum on time of the LED current is
approximately 320μs for a 3.6V input voltage.
The achievable dimming range for this application with
a 100Hz PWM frequency can be determined using the
following method.
3587fc
18
LT3587
APPLICATIONS INFORMATION
Lower Input Voltage Applications
the LT3587. The outputs can be driven straight from the
battery, resulting in higher efficiency.
The LT3587 can be used in lower input voltage applica-
tions. The V supply voltage to the LT3587 must be
Figure 17 shows a typical digital still camera application
with CCD positive and negative supply as well as an LED
driver powered by two AA cells. The battery is connected
to the input inductors and the chip is powered with a 3.3V
logic supply voltage.
IN
2.5V to 6V. However, the inductors can be run off a lower
voltage. This allows the outputs to be powered off two
alkaline cells. Most portable devices and systems have
a 3.3V logic supply voltage which can be used to power
LED DRIVER
20mA UP TO 12V
C4
2AA CELLS
2V TO 3.2V
1μF
L4
10μH
L1
15μH
R
VFB3
D
S3
787k
(OPTIONAL)
D
S1
C1
4.7μF
V
V
CAP3
SW3
SW1
FB3 OUT3
R
IFB3
8.06k
I
CAP1
FB3
C
FB1
3.3pF
FLT
LT3587
EN/SS1
EN/SS3
R
FB1
787k
FB1
V
V
OUT1
SW2
GND
FB2
IN
CCD POSITIVE
12V, 10mA
3.3V
C6
1μF
L2
15μH
C
FB2
R
1M
FB2
C2
2.2μF
6.8pF
L3
15μH
CCD NEGATIVE
–8V, 20mA
2AA CELLS
2V TO 3.2V
D
C7
10μF
S2
3587 F17
C1: MURATA GRM21BR61E475KA12L
C2: MURATA GRM188R61C225KE15D
C4: MURATA GRM188R61E105KA12B
C6: MURATA GRM155R61A105KE15D
C7: MURATA GRM21BR71A106KE51L
C
C
: MURATA GRM1555C1H3R3BZ01D
: MURATA GRM1555C1H6R3BZ01D
FB1
FB2
L1, L2, L3: SUMIDA CDRH2D18/HP-150N
L4: TOKO 1071AS-100M
D
, D , D : NXP PMEG2005EB
S1 S2 S3
Figure 17. 2 AA Cells Providing CCD Positive and Negative Supply
and a Three White Backlight LED Driver
3587fc
19
LT3587
APPLICATIONS INFORMATION
Board Layout Consideration
The voltage signals of the SW1, SW2 and SW3 pins have
riseandfalltimesofafewns. Minimizethelengthandarea
of all traces connected to the SW1, SW2 and SW3 pins
to reduce capacitive coupling between these fast nodes
and other circuitry. In particular, keep all the traces of the
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential.
feedback voltage pins (FB1, FB2, V and I ) away from
FB3
FB3
the switching node. Always use a ground plane under the
switching regulator to minimize interplane coupling.
In order to minimize magnetic field radiation, reduce the
parasiticinductancebykeepingthetracesthatconducthigh
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. Figure 18 outlines the critical paths.
Finally, place as much of the output capacitors of each
channelclosetotheirrespectiveCAPpins.Recommended
component placement is shown in Figure 19.
C2
L2
L3
D
D
S3
S1
V
L1
L4
VIN
V
NEG
V
V
VIN
VIN
SW2
SW1
SW3
D
S2
CAP1
LT3587
GND
CAP3
LT3587
GND
C6
C7
LT3587
GND
Q2
C1
C4
C6
C6
Q1
Q3
3587 F18
Figure 18. High Current Paths
V
IN
CAP3
V
NEG
C6
(OPT)
C7
L4
C4
R
C
FB2
R
IFB3
V
OUT3
DS3
L3
FB2
C5
V
U1
C6
C3
IN
C2
R
FB1
DS2
DS1
C
FB1
L2
V
OUT1
L1
C1
C6
(OPT)
C6
(OPT)
3587 F19
V
CAP1
IN
Figure 19. Recommended Component Placement
3587fc
20
LT3587
TYPICAL APPLICATIONS
Li-Ion Powered Supply for CCD Imager and Five White Backlight LEDs
LED DRIVER
20mA UP TO 24V
R
VFB3
C4
V
VIN
1.65M
2.2μF
2.5V TO 6V
L4
10μH
L1
15μH
(OPTIONAL)
C6
1μF
D
S3
V
V
CAP3
SW3
V
SW1
FB3 OUT3
IN
D
C1
10μF
S1
R
IFB3
8.06k
I
CAP1
FB3
C
FB1
2.7pF
LT3587
FLT
R
FB1
EN/SS1
EN/SS3
1M
FB1
V
OUT1
SW2
GND FB2
C3
100nF
CCD POSITIVE
15V, 50mA
C5
100nF
C2
2.2μF
R
C
FB2
6.8pF
FB2
L2
15μH
L3
1M
15μH
V
CCD NEGATIVE
–8V, 100mA
VIN
2.5V TO 6V
D
C7
22μF
S2
3587 TA02
C1: MURATA GRM21BR61C106KE15L
C2: MURATA GRM188R61C225KE15D
C3, C5: MURATA GRM033R60J104KE19D
C4: MURATA GRM21BR71E225KA73L
C6: MURATA GRM155R61A105KE15D
C7: TAIYO YUDEN LMK212BJ226MG-T
C
C
: MURATA GRM1555C1H2R7BZ01D
: MURATA GRM1555C1H6R8BZ01D
FB1
FB2
L1, L2, L3: SUMIDA CDRH2D18/HP-150N
L4: TOKO 1071AS-100M
D
, D , D : IR IR05H40CSPTR
S1 S2 S3
3587fc
21
LT3587
TYPICAL APPLICATIONS
Driver For a CCD Imager and an OLED Display Panel with Soft-Start
OLED DRIVER
16V, 20mA
V
VIN
C4
1μF
2.5V TO 6V
L4
10μH
L1
15μH
C6
1μF
D
S3
R
VFB3
1.07M
R
IFB3
7.15k
C1
CAP3
SW3
V
IN
SW1
CAP1
V
V
FB3
OUT3
D
S1
4.7μF
(OPTIONAL)
I
FB3
C
FB1
LT3587
GND
2.7pF
FLT
R
FB1
1M
EN/SS1
FB1
EN/SS3
V
SW2
FB2
OUT1
CCD POSITIVE
15V, 50mA
C3
100nF
C5
100nF
C
FB2
6.8pF
C2
2.2μF
R
FB2
1M
L2
15μH
D3
V
CCD NEGATIVE
–8V, 100mA
VIN
2.5V TO 6V
3587 TA03
C7
22μF
D
S2
C1: TAIYO YUDEN TMK212BJ475KG-T
C2: TAIYO YUDEN EMK107BJ225KA-T
C3, C5: TAIYO YUDEN JMK063BJ104KP-F
C4: TAIYO YUDEN GMK107BJ105KA-T
C6: TAIYO YUDEN LMK105BJ105KV-F
C7: TAIYO YUDEN LMK212BJ226MG-T
C
C
: TAIYO YUDEN EMK105SK2R7JW-F
: TAIYO YUDEN EMK105SH6R8JW-F
FB1
FB2
L1, L2: SUMIDA CDRH2D18/HP-150N
L4: TOKO 1071AS-100M
D
, D , D , D3: NXP PMEG2005EB
S1 S2 S3
Extending the High Voltage Range and the Number of Independently Controlled Regulated Outputs
D8
24V
C10
1μF
R5
GND
100k
SHDN ADJ
C11
C8
R6
LT1964
SUPPLY 5:
40V, 5mA
2.2μF
2.2μF
D5
D7
1.21M
IN
OUT
OUT
LT3014
IN
SUPPLY 4:
–40V, 5mA
C12
C9
2.2μF
R6
2.2μF
3.24M
D6
SUPPLY 1
D4
C13
1μF
ADJ SHDN
R7
100k
GND
SUPPLY 2
D10
SUPPLY 3:
C4
2.2μF
V
VIN
25V, 1mA TO 10mA
3V TO 6V
L4
15μH
L1
15μH
C6
1μF
D
S3
R
VFB3
1.74M
D
S1
C1
10μF
V
FB3
V
CAP3
SW3
V
IN
SW1
OUT3
R
IFB3
10.7k
CAP1
I
FB3
C
FB1
2.2pF
FLT
LT3587
EN/SS1
R
FB1
1.21M
EN/SS3
FB1
V
OUT1
SW2
GND
FB2
SUPPLY 1:
18V, 50mA
C3
100nF
C5
C
FB2
2.7pF
C2
2.2μF
100nF
R
FB2
SUPPLY 2:
–18V, 50mA
L2
22μH
D3
2.26M
V
VIN
3V TO 6V
3587 TA04
C7
22μF
D9
D
S2
C1: MURATA GRM31CR71E106KA12L
C
C
: MURATA GRM1555C1H2R2BZ01D
: MURATA GRM1555C1H2R7BZ01D
FB1
FB2
C2, C8, C11: MURATA GCM21BR71E225KA73L
C3, C5: MURATA GRM033R60J104KE19D
C4: MURATA GRM21BR71E225KA73L
C6: MURATA GRM155R61A105KE15D
C7: MURATA GRM32ER61E226KE15L
L1, L4: COILCRAFT LPS4018-153
L2, L3: COILCRAFT LPS4018-223
D
, D , D , D3, D4, D5, D6, D7, D9, D10: IR IR05H40CSPTR
S1 S2 S3
D8: DIODES INC DDZ9709T
C9, C12: MURATA GRM31CR71H225KA55L
C10, C13: MURATA GRM21BR71H105KA12L
3587fc
22
LT3587
PACKAGE DESCRIPTION
UD Package
20-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1720 Rev A)
0.70 0.05
3.50 0.05
(4 SIDES)
1.65 0.05
2.10 0.05
PACKAGE
OUTLINE
0.20 0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 TYP
OR 0.25 × 45°
CHAMFER
R = 0.115
TYP
0.75 0.05
3.00 0.10
(4 SIDES)
R = 0.05
TYP
19 20
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
1.65 0.10
(4-SIDES)
(UD20) QFN 0306 REV A
0.200 REF
0.20 0.05
0.40 BSC
0.00 – 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3587fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3587
TYPICAL APPLICATION
General Purpose High Voltage Supplies Generator
SUPPLY 3: 25V SUPPLY
WITH SAFETY
CURRENT LIMIT AT 25mA
C4
2.2μF
V
VIN
2.5V TO 6V
L4
10μH
L1
15μH
C6
1μF
D
S3
R
VFB3
1.74M
C1
10μF
D
V
V
CAP3
SW3
V
IN
SW1
CAP1
S1
R
IFB3
6.34k
FB3 OUT3
I
FB3
C
FB1
2.7pF
LT3587
GND
R
FB1
C1: MURATA GRM31CR71E106KA12L
FLT
1M
C2: MURATA GRM21BR71E225KA73L
C3, C5: MURATA GRM033R60J104KE19D
C4: MURATA GRM21BR71E225KA73L
C6: MURATA GRM155R61A105KE15D
C7: MURATA GRM32ER61E226KE15L
FB1
EN/SS1
EN/SS3
V
SW2
FB2
OUT1
SUPPLY 1:
15V, 50mA
C5
100nF
C3
100nF
R
C
C
: MURATA GRM1555C1H2R7BZ01D
: MURATA GRM1555C1H2R2BZ01D
C
FB2
2M
FB1
FB2
C2
2.2μF
FB2
2.2pF
SUPPLY 2:
–16V, 50mA
L2
22μH
L3
22μH
L1: COILCRAFT LPS4018-153
L2, L3: COILCRAFT LPS4018-223
L4: TOKO 1071AS-100M
V
VIN
2.5V TO 6V
C7
22μF
3587 TA05
D
D
S2
S4
D
, D , D , D : IR IR05H40CSPTR
S1 S2 S3 S4
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
= 1.2V, V
LT1944
Dual Output, Boost/Inverter, 350mA I , High Efficiency
Boost-Inverting DC/DC Converter
V
= 15V, V
= 15V, V
= 15V, V
=
=
34V, I = 20, I < 1μA,
Q SD
SW
IN(MIN)
IN(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
MSOP-10 Package
LT1945
Dual Output, Boost/Inverter, 350mA I , High Efficiency
V
= 1.2V, V
34V, I = 20, I < 1μA,
Q SD
SW
IN(MIN)
IN(MAX)
Boost-Inverting DC/DC Converter
MSOP-10 Package
LT3463/LT3463A
Dual Output, Boost/Inverter, 250mA I , Constant Off-
V
= 2.3V, V
= 40V, I = 40μA, I < 1μA,
Q SD
SW
IN(MIN)
IN(MAX)
Time, High Efficiency Step-Up DC/DC Converter with
Integrated Schottkys
3 × 3 DFN-10 Package
LT3466/LT3466-1
LT3471
Dual Constant Current, 2MHz, High Efficiency White LED
Boost Regulator with Integrated Schottky Diode
V
= 2.7V, V
= 24V, V
= 16V, V
= 16V, V
= 16V, V
= 16V, V
= 10V, V
= 40V, I = 5mA, I < 16μA,
Q SD
IN(MIN)
IN(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
3 × 3 DFN-10 Package
Dual Output, Boost/Inverter, 1.3A I , 1.2MHz, High
V
= 2.4V, V
= 40V, I = 2.5mA, I < 1μA,
Q SD
SW
IN(MIN)
IN(MAX)
Efficiency Boost-Inverting DC/DC Converter
3 × 3 DFN-10 Package
LT3472/LT3472A
LT3473/LT3473A
LT3494/LT3494A
LT3497
Dual Output, Boost/Inverter, 400mA I , 1.2MHz, High
V
= 2.2V, V
= 34V I = 2.8mA, I < 1μA,
Q SD
SW
IN(MIN)
IN(MAX)
Efficiency Boost-Inverting DC/DC Converter
3 × 3 DFN-10 Package
40V, 1A, 1.2MHz Micropower Low Noise Boost Converter
with Output Disconnect
V
= 2.2V, V
= 36V, I = 150μA, I < 1μA,
Q SD
IN(MIN)
IN(MAX)
3 × 3 DFN-12 Package
40V, 180mA/350mA Micropower Low Noise Boost
Converter with Output Disconnect
V
= 2.3V, V
= 40V, I = 65μA, I < 1μA,
Q SD
IN(MIN)
IN(MAX)
3 × 2 DFN-8 Package
Dual 2.3MHz, Full Function LED Driver with Integrated
Schottkys and 250:1 True Color PWM Dimming
V
= 2.5V, V
= 32V, I = 6mA, I < 12μA,
Q SD
IN(MIN)
IN(MAX)
2 × 3 DFN-10 Package
LT3580
40V, 2A, 2.5MHz Boost/Inverter DC/DC Converter
V : 2.5V to 32V, V
= 40V, I = 1mA, I < 1μA, MSOP-8E,
OUT(MAX) Q SD
IN
3mm × 3mm DFN-8 Packages
3587fc
LT 0109 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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