LLTC1142HV_技术文档

LTC1142/LTC1142L/LTC1142HV

Dual High Efficiency

Synchronous Step-Down

Switching Regulators

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DESCRIPTIO

FEATURES

The LTC^®1142/LTC1142L/LTC1142HV are dual synchro-

nous step-down switching regulator controllers featuring

automatic Burst Mode^TMoperation to maintain high efficien-

cies at low output currents. The devices are composed of two

separate regulator blocks, each driving a pair of external

complementary power MOSFETs, at switching frequencies

up to 250kHz, using a constant off-time current mode archi-

tecture providing constant ripple current in the inductor.

■

Dual Outputs: 3.3V and 5V or User Programmable

■

Ultrahigh Efficiency: Over 95% Possible

■

Current Mode Operation for Excellent Line and Load

Transient Response

■

High Efficiency Maintained over 3 Decades of

Output Current

■

Low Standby Current at Light Loads: 160µA/Output

■

Independent Micropower Shutdown: I_Q< 40µA

■

Wide V_INRange: 3.5V to 20V

The operating current level for both regulators is user pro-

grammableviaanexternalcurrentsenseresistor. Wideinput

supply range allows operation from 3.5V* to 18V (20V

maximum).Constantoff-timearchitectureprovideslowdrop-

out regulation limited only by the R_DS(ON)of the external

MOSFET and resistance of the inductor and current sense

resistor.

■

Very Low Dropout Operation: 100% Duty Cycle

■

Synchronous FET Switching for High Efficiency

■

Available in Standard 28-Pin SSOP

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APPLICATIO S

■

Notebook and Palmtop Computers

The LTC1142 series is ideal for applications requiring dual

output voltages with high conversion efficiencies over a wide

load current range in a small amount of board space.

■

Battery-Operated Digital Devices

■

Portable Instruments

DC Power Distribution Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

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TYPICAL APPLICATIO

V

IN

5.2V TO 18V

C

IN5

C

+

IN3

22µF

25V

× 2

22µF

25V

× 2

0.22µF

0V = NORMAL

>1.5V = SHDN

2

24

16

10

P-CH

Si9430DY

V

SHDN3

V

IN5

SHDN5

IN3

23

1

9

L2

L1

50µH

R

SENSE5

0.05Ω

SENSE3

PDRIVE 3

PDRIVE 5

50µH

V

0.05Ω

OUT3

3.3V/2A

V

OUT5

5V/2A

15

+

SENSE

3

SENSE

5

LTC1142HV

1000pF

–

3

14

20

28

6

D1

MBRS130L

D2

NDRIVE 3

NDRIVE 5

MBRS130L

N-CH

Si9410DY

N-CH

Si9410DY

C

PGND3 SGND3

C

I

SGND5

17

PGND5

18

T5

T3

TH3

27

TH5

13

R

C5

1k

C

OUT5

C

+

OUT3

220µF

4

3

25

11

220µF

10V

× 2

10V

× 2

R

C3

1k

R

: DALE WSL-2010-.05

SENSE3, SENSE5

L1, L2: COILTRONICS CTX50-2-MP

PINS 5, 7, 8, 19, 21, 22: NC

C

T5

T3

C3

C5

560pF 3300pF 3300pF 390pF

1142 F01

NOTE: COMPONENTS OPTIMIZED FOR HIGHEST EFFICIENCY, NOT MINIMUM BOARD SPACE.

Figure 1. High Efficiency Dual 3.3V, 5V Supply

1

LTC1142/LTC1142L/LTC1142HV

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ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (Pins 10, 24)

Operating Ambient Temperature Range...... 0°C to 70°C

Extended Commercial

Temperature Range ........................... –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Storage Temperature Range ................ – 65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

LTC1142, LTC1142L-ADJ..................... 16V to –0.3V

LTC1142HV, LTC1142HV-ADJ ............. 20V to –0.3V

Continuous Output Current (Pins 6, 9, 20, 23) .... 50mA

Sense Voltages (Pins 1, 14, 15, 28)

V_IN> 13V.............................................. 13V to –0.3V

V_IN< 13V.................................. (V_IN+ 0.3V) to –0.3V

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W

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PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

ORDER PART

–

+

1

2

28 SENSE

27

26 INTV

1

2

28 SENSE

27

26 INTV

3

SENSE

V

1

SENSE

3

NUMBER

I

SHDN3

SGND3

PGND3

NC

TH1

TH3

FB1

3

SHDN1

CC1

CC3

4

25

24

C

V

4

25

24

C

V

SGND1

PGND1

NDRIVE 1

NC

T1

T3

LTC1142CG

LTC1142HVCG

LTC1142HVCG-ADJ

LTC1142LCG-ADJ

5

IN1

IN3

6

23 PDRIVE 1

22 NC

6

23 PDRIVE 3

22 NC

NDRIVE 3

NC

7

8

21 NC

8

21 NC

NC

9

20 NDRIVE 2

9

20 NDRIVE 5

19 NC

PDRIVE 2

PDRIVE 5

10

11

12

13

14

PGND2

SGND2

SHDN2

10

11

12

13

14

19

18

17

16

15

V

IN2

V

IN5

18 PGND5

17 SGND5

C

T2

C

T5

INTV

CC2

INTV

CC5

V

16 SHDN5

+

I

FB2

TH2

TH5

+

–

SENSE

2

15 SENSE

5

SENSE

2

SENSE

5

G PACKAGE

28-LEAD PLASTIC SSOP

G PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V₁₀= V₂₄= 10V, V_SHDN= 0V unless otherwise noted.

SYMBOL

V , V

PARAMETER

CONDITIONS

MIN

TYP

1.25

0.2

MAX

1.29

1

UNITS

V

Feedback Voltage

Feedback Current

LTC1142HV-ADJ, LTC1142L-ADJ : V , V = 9V

●

1.21

2

16

10 24

I , I

LTC1142HV-ADJ, LTC1142L-ADJ

µA

2

16

V

Regulated Output Voltage

3.3V Output

LTC1142, LTC1142HV

OUT

I

= 700mA, V = 9V

●

3.23

4.90

3.33

5.05

3.43

5.20

V

LOAD

24

5V Output

= 700mA, V = 9V

10

∆V

OUT

Output Voltage Line Regulation

V

= 7V to 12V, I = 50mA

LOAD

–40

0

40

mV

10, 24

Output Voltage Load Regulation

3.3V Output

Figure 1 Circuit

5mA < I

< 2A

●

40

60

65

100

mV

LOAD

5V Output

Output Ripple (Burst Mode)

I

= 0A

50

mV

P-P

LOAD

I

, I

10 24

Input DC Supply Current (Note 3)

Normal Mode

LTC1142

4V < V , V < 12V

1.6

160

10

2.1

230

20

mA

µA

10 24

Sleep Mode

4V < V < 12V, 6V < V < 12V

24

10

Shutdown

V

= V

= 2.1V, 4V < V , V < 12V

SD1

SD2 10 24

2

LTC1142/LTC1142L/LTC1142HV

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V₁₀= V₂₄= 10V, V_SHDN= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

2.3

250

22

UNITS

Input DC Supply Current (Note 3)

Normal Mode

LTC1142HV, LTC1142HV-ADJ

4V < V , V < 18V

1.6

160

10

mA

µA

10 24

Sleep Mode

Shutdown

4V < V < 18V, 6V < V < 18V

24

= V

10

V

= 2.1V, 4V < V , V < 18V

SD1

SD2 10 24

Input DC Supply Current (Note 3)

Normal Mode

LTC1142L-ADJ (Note 6)

3.5V < V , V < 12V

1.6

160

10

2.1

230

20

mA

µA

10 24

Sleep Mode

Shutdown

3.5V < V , V < 12V

10 24

V

= V = 2.1V, 3.5V < V , V < 12V

SD2 10 24

SD1

V – V

15

Current Sense Threshold Voltage

LTC1142HV-ADJ, LTC1142L-ADJ

1

28

V

– V

V

= V = V

+ 100mV, V = V = V

+ 25mV

– 25mV

25

mV

14

28

OUT

2

16

REF

= V = V

– 100mV, V = V = V

●

130

150

170

28

2

16

LTC1142, LTC1142HV

V

= V

+ 100mV (Forced)

– 100mV (Forced)

25

150

mV

28

OUT

LTC1142, LTC1142HV

V

= V

+ 100mV (Forced)

– 100mV (Forced)

25

150

mV

14

OUT

130

0.5

170

2

V

Shutdown Pin Threshold

0.8

1.2

V

SHDN

I

Shutdown Pin Input Current

0V < V

< 8V, V , V = 16V

5

µA

SHDN

10 24

–

, I

11 24

C Pin Discharge Current

T

V

in Regulation, V

= 0V

= V

OUT

50

4

70

2

90

10

µA

OUT

SENSE

t

Off-Time (Note 4)

C = 390pF, I

T

= 700mA

LOAD

5

6

µs

OFF

t , t

r

Driver Output Transition Times

C = 3000pF (Pins 6, 9, 20, 23), V , V = 6V

100

200

ns

f

L

10 24

–40°C ≤ T_A≤ 85°C (Note 5), V₁₀= V₂₄= 10V, unless otherwise noted.

SYMBOL

V , V

PARAMETER

CONDITIONS

MIN

TYP

1.25

0.2

MAX

1.29

1

UNITS

V

Feedback Voltage

Feedback Current

LTC1142HV-ADJ Only: V , V = 9V

1.21

2

16

10 24

I , I

LTC1142HV-ADJ Only

µA

2

16

V

Regulated Output Voltage

3.3V Output

LTC1142, LTC1142HV

OUT

I

= 700mA, V = 9V

3.17

4.85

3.33

5.05

3.43

5.20

V

LOAD

24

5V Output

= 700mA, V = 9V

10

I

, I

10 24

Input DC Supply Current (Note 3)

Normal Mode

LTC1142

4V < V , V < 12V

1.6

160

10

2.4

260

22

mA

µA

10 24

Sleep Mode

4V < V < 12V, 6V < V < 12V

24 10

Shutdown

V

= 2.1V, 4V < V , V < 12V

SHDN 10 24

Input DC Supply Current (Note 3)

Normal Mode

LTC1142HV-ADJ, LTC1142HV

4V < V , V < 18V

1.6

160

10

2.6

280

24

mA

µA

10 24

Sleep Mode

4V < V < 18V, 6V < V < 18V

24 10

Shutdown

V

= 2.1V, 4V < V , V < 12V

SHDN 10 24

Input DC Supply Current (Note 3)

Normal Mode

LTC1142L-ADJ (Note 6)

3.5V < V , V < 12V

1.6

160

10

2.4

260

22

mA

µA

10 24

Sleep Mode

Shutdown

3.5V < V , V < 12V

10 24

V

= V = 2.1V, 3.5V < V , V < 12V

SD2 10 24

SD1

V – V

15

Current Sense Threshold Voltage

LTC1142HV-ADJ, LTC1142L-ADJ

1

28

V

– V

V

= V = V

+ 100mV, V = V = V

+ 25mV

– 25mV

25

mV

14

28

OUT

2

16

REF

= V = V

– 100mV, V = V = V

125

150

175

28

2

16

LTC1142, LTC1142HV

V

= V

+ 100mV (Forced)

– 100mV (Forced)

25

150

mV

28

OUT

3

LTC1142/LTC1142L/LTC1142HV

ELECTRICAL CHARACTERISTICS

–40°C ≤ T_A≤ 85°C (Note 5), V₁₀= V₂₄= 10V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LTC1142, LTC1142HV

V

= V

+ 100mV (Forced)

– 100mV (Forced)

25

mV

14

OUT

125

0.55

3.8

150

175

2

V

Shutdown Pin Threshold

Off-Time (Note 4)

0.8

5

V

SHDN

t

C = 390pF, I

T

= 700mA

LOAD

6

µs

OFF

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: In applications where R

time increases approximately 40%.

is placed at ground potential, the off-

SENSE

Note 2: T is calculated from the ambient temperature T and power

Note 5: The LTC1142/LTC1142L/LTC1142HV are guaranteed to meet

specified performance from 0°C to 70°C and are designed, characterized

and expected to meet these extended temperature limits, but are not tested

at –40°C and 85°C. Guaranteed I-grade parts are available, consult the

factory.

J

A

dissipation P according to the following formula:

D

LTC1142CG: T = T + (P × 95°C/W)

J

A

D

Note 3: This current is for one regulator block. Total supply current is the

sum of Pins 10 and 24 currents. Dynamic supply current is higher due to

the gate charge being delivered at the switching frequency. See the

Applications Information section.

Note 6: The LTC1142L-ADJ allows operation down to V = 3.5V.

IN

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TYPICAL PERFOR A CE CHARACTERISTICS

5V Output Efficiency

3.3V Output Efficiency

5V Efficiency vs Input Voltage

100

98

96

94

92

90

88

86

84

82

80

100

FIGURE 1 CIRCUIT

OUT

V

= 6V

IN

V

= 5V

V

= 5V

IN

I

= 1A

LOAD

95

V

= 10V

IN

I

= 100mA

LOAD

V

= 10V

IN

90

85

0

4

8

12

16

20

0.01

0.1

LOAD CURRENT (A)

1

2

0.01

0.1

LOAD CURRENT (A)

1

2

INPUT VOLTAGE (V)

1142 G01

1142 G02

1142 G03

3.3V Efficiency vs Input Voltage

Line Regulation

Load Regulation

40

30

100

98

96

94

92

90

88

86

84

82

80

20

0

FIGURE 1 CIRCUIT

= 0.05Ω

FIGURE 1 CIRCUIT

OUT

FIGURE 1 CIRCUIT

= 1A

R

SENSE

V

= 3.3V

I

LOAD

20

V

= 6V

IN

–20

–40

–60

–80

–100

I

= 1A

V

IN

= 12V

LOAD

10

0

I

= 100mA

LOAD

–10

–20

–30

–40

V

IN

= 6V

V

IN

= 12V

2.0

V

= 5V

= 3.3V

OUT

0

4

8

12

16

20

0

4

8

12

16

20

0

0.5

1.0

1.5

2.5

INPUT VOLTAGE (V)

LOAD CURRENT (A)

1142 G04

1142 G05

1142 G06

4

LTC1142/LTC1142L/LTC1142HV

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Operating Frequency vs

V_IN– V_OUT

Supply Current in Shutdown

DC Supply Current

20

18

16

14

12

10

8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

V

OUT

= 5V

PER REGULATOR BLOCK

PINS 10, 24

SHUTDOWN

V

= 2V

0°C

ACTIVE MODE

70°C

PER REGULATOR BLOCK

NOT INCLUDING

GATE CHARGE CURRENT

PINS 10, 24

25°C

6

4

SLEEP MODE

2

0

4

6

8

0

2

10

12

0

6

10 12 14 16 18

0

6

10 12 14 16 18

2

4

8

2

4

8

V

IN

– V

OUT

VOLTAGE (V)

INPUT VOLTAGE (V)

1142 G09

1142 G07

1142 G08

Off-Time vs Output Voltage

Gate Charge Supply Current

Current Sense Threshold Voltage

80

70

60

50

40

30

20

10

0

175

150

125

100

75

28

24

20

16

12

8

V

= V

MAXIMUM

SENSE

OUT

THRESHOLD

Q

+ Q = 100nC

P

N

50

Q

+ Q = 50nC

MINIMUM

THRESHOLD

N

P

25

V

= 5V

4

OUT

V

= 3.3V

2

OUT

0

1

3

4

5

0

20

40

60

80

100

20

80

200

260

140

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

OPERATING FREQUENCY (kHz)

1142 G11

1142 G12

1142 G10

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PI FU CTIO S

LTC1142/LTC1142HV

SGND3 (Pin 3): The 3.3V section small-signal ground

must be routed separately from other grounds to the (–)

terminal of the 3.3V section output capacitor.

SENSE⁺3 (Pin 1): The (+) Input to the 3.3V Section

Current Comparator. A built-in offset between Pins 1 and

28 in conjunction with R_SENSE3sets the current trip

threshold for the 3.3V section.

PGND3 (Pin 4): The 3.3V section driver power ground

connects to source of N-channel MOSFET and the (–)

terminal of the 3.3V section input capacitor.

SHDN3 (Pin 2): When grounded, the 3.3V section oper-

ates normally. Pulling Pin 2 high holds both MOSFETs off

and puts the 3.3V section in micropower shutdown mode.

Requires CMOS logic-level signal with t_r, t_f< 1µs. Do not

“float” Pin 2.

NC (Pin 5): No Connection.

NDRIVE3(Pin6):HighCurrentDriveforBottomN-Channel

MOSFET, 3.3V Section. Voltage swing at Pin 6 is from

ground to V_IN3

.

5

LTC1142/LTC1142L/LTC1142HV

U

PI FU CTIO S

NC (Pins 7, 8): No Connection.

NC (Pins 21, 22): No Connection.

PDRIVE 5 (Pin 9): High Current Drive for Top P-Channel

MOSFET,5VSection.VoltageswingatthispinisfromV_IN5

to ground.

PDRIVE 3 (Pin 23): High Current Drive for Top P-Channel

MOSFET, 3.3V Section. Voltage swing at this pin is from

V_IN3to ground.

V_IN5(Pin 10): Supply pin, 5V section, must be closely

decoupled to 5V power ground Pin 18.

V_IN3(Pin 24): Supply pin, 3.3V section, must be closely

decoupled to 3.3V power ground, Pin 4.

C_T5(Pin 11): External capacitor C_T5from Pin 11 to ground

setstheoperatingfrequencyforthe5Vsection.(Theactual

frequency is also dependent upon the input voltage.)

C_T3(Pin 25): External capacitor C_T3from Pin 25 to ground

sets the operating frequency for the 3.3V section. (The

actualfrequencyisalsodependentupontheinputvoltage.)

INTV_CC5(Pin 12) : Internal supply voltage for the 5V

section,nominally3.3V,canbedecoupledtosignalground,

Pin 17. Do not externally load this pin.

INTV_CC3(Pin 26): Internal supply voltage for the 3.3V

section,nominally3.3V,canbedecoupledtosignalground,

Pin 3. Do not externally load this pin.

I_TH5(Pin 13): Gain Amplifier Decoupling Point, 5V Sec-

tion. The 5V section current comparator threshold in-

creases with the Pin 13 voltage.

I_TH3(Pin 27): Gain Amplifier Decoupling Point, 3.3V

Section. The 3.3V section current comparator threshold

increases with the Pin 27 voltage.

SENSE^–5 (Pin 14): Connects to internal resistive divider

which sets the output voltage for the 5V section. Pin 14 is

also the (–) input for the current comparator on the

5V section.

SENSE^–3 (Pin 28): Connects to internal resistive divider

which sets the output voltage for the 3.3V section. Pin 28

is also the (–) input for the current comparator on the

3.3V section.

SENSE⁺5(Pin15):The(+)Inputtothe5VSectionCurrent

Comparator. A built-in offset between Pins 15 and 14 in

conjunction with R_SENSE5sets the current trip threshold

for the 5V section.

LTC1142HV-ADJ/LTC1142L-ADJ

SENSE⁺1 (Pin 1): The (+) Input to the Section 1 Current

Comparator. A built-in offset between Pins 1 and 28 in

conjunction with R_SENSE1sets the current trip threshold

for this section.

SHDN5(Pin16):Whengrounded, the5Vsectionoperates

normally. Pulling Pin 16 high holds both MOSFETs off and

puts the 5V section in micropower shutdown mode.

Requires CMOS logic signal with t_r, t_f< 1µs. Do not “float”

Pin 16.

V_FB1(Pin 2): This pin serves as the feedback pin from an

external resistive divider used to set the output voltage for

section 1.

SGND5(Pin17):The5Vsectionsmall-signalgroundmust

be routed separately from other grounds to the (–) termi-

nal of the 5V section output capacitor.

SHDN1 (Pin 3): When grounded, the section 1 regulator

operatesnormally.PullingPin3highholdsbothMOSFETs

off and puts this section in micropower shutdown mode.

Requires CMOS logic signal with t_r, t_f< 1µs. Do not “float”

Pin 3.

PGND5 (Pin 18): The 5V section driver power ground

connects to source of N-channel MOSFET and the (–)

terminal of the 5V section input capacitor.

SGND1 (Pin 4): The section 1 small-signal ground must

be routed separately from other grounds to the (–) termi-

nal of the section 1 output capacitor.

NC (Pin 19): No Connection.

NDRIVE 5 (Pin 20): High Current Drive for Bottom

PGND1 (Pin 5): The section 1 driver power ground con-

nectstosourceofN-channelMOSFETandthe(–)terminal

of the section 1 input capacitor.

N-Channel MOSFET, 5V Section. Voltage swing at Pin 20

is from ground to V_IN5

.

6

LTC1142/LTC1142L/LTC1142HV

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PI FU CTIO S

NDRIVE1(Pin6):HighCurrentDriveforBottomN-Channel

SGND2 (Pin 18): The section 2 small-signal ground must

be routed separately from other grounds to the (–) termi-

nal of the section 2 output capacitor.

MOSFET, Section 1. Voltage swing at Pin 6 is from ground

to V_IN1

.

NC (Pins 7, 8): No Connection.

PGND2 (Pin 19): The section 2 driver power ground

connects to source of the N-channel MOSFET and the (–

)

PDRIVE 2 (Pin 9): High Current Drive for Top P-Channel

MOSFET, Section 2. Voltage swing at this pin is from V_IN2

to ground.

terminal of the section 2 input capacitor.

NDRIVE 2 (Pin 20): High Current Drive for Bottom

N-Channel MOSFET, Section 2. Voltage swing at Pin 20 is

V_IN2(Pin 10): Supply pin, section 2, must be closely

decoupled to section 2 power ground, Pin 19.

from ground to V_IN2

.

NC (Pins 21, 22): No Connection.

C_T2(Pin 11): External capacitor C_T2from Pin 11 to ground

sets the operating frequency for the section 2. (The actual

frequency is also dependent upon the input voltage.)

PDRIVE 1 (Pin 23): High Current Drive for Top P-Channel

MOSFET, Section 1. Voltage swing at this pin is from V_IN1

to ground.

INTV_CC2(Pin 12) : Internal supply voltage for section 2,

nominally 3.3V, can be decoupled to signal ground, Pin

18. Do not externally load this pin.

V_IN1(Pin 24): Supply Pin, Section 1. Must be closely

decoupled to section 1 power ground Pin 5.

I_TH2(Pin 13): Gain Amplifier Decoupling Point, Section 2.

The section 2 current comparator threshold increases

with the Pin 13 voltage.

C_T1(Pin 25): External capacitor C_T1from Pin 25 to ground

sets the operating frequency for section 1. (The actual

frequency is also dependent upon the input voltage.)

SENSE^–2 (Pin 14): Connects (–) input for the current

INTV_CC1(Pin 26): Internal supply voltage for section 1,

nominally 3.3V, can be decoupled to signal ground, Pin 4.

Do not externally load this pin.

comparator on section 2.

SENSE⁺2 (Pin 15): The (+) Input to the Section 2 Current

Comparator. A built-in offset between Pins 15 and 14 in

conjunction with R_SENSE2sets the current trip threshold

for this section.

I_TH1(Pin 27): Gain Amplifier Decoupling Point, Section 1.

The section 1 current comparator threshold increases

with the Pin 27 voltage.

V_FB2(Pin 16): This pin serves as the feedback pin from an

external resistive divider used to set the output voltage for

section 2.

SENSE^–1 (Pin 28): Connects to the (–) input for the

current comparator on section 1.

SHDN2 (Pin 17): When grounded, the section 2 regulator

operatesnormally.PullingPin17highholdsbothMOSFETs

off and puts section 2 in micropower shutdown mode.

Requires CMOS logic signal with t_r, t_f< 1µs. Do not “float”

Pin 17.

7

LTC1142/LTC1142L/LTC1142HV

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Only one regulator block shown. Pin numbers are for 3.3V (5V) sections for LTC1142/LTC1142HV,

and V_OUT1(V_OUT2) for LTC1142L-ADJ/LTC1142HV-ADJ.

PIN NUMBERS FOR

2(16)

LTC1142, LTC1142HV

SGND

3(17)

LTC1142L-ADJ

LTC1142HV-ADJ

4(18)

24(10)

23(9)

V

IN

LTC1142-ADJ PIN NUMBERS

3(17)

FOR LTC1142L-ADJ

LTC1142HV-ADJ

+

–

PDRIVE

SENSE

28(14)

1(15)

LTC1142L-ADJ

LTC1142HV-ADJ

2(16)

NDRIVE

PGND

6(20)

4(18)

NC/ADJ

–

+

LTC1142L-ADJ, LTC1142HV-ADJ: 5(19)

V

SLEEP

–

25mV TO 150mV

C

R

S

Q

+

–

5pF

+

V

OS

S

I

TH

V

–

TH1

–

+

–

+

TH2

13k

27(13)

T

G

1.25V

100k

INTV

SHDN

2(16)

CC

V

IN

OFF-TIME

CONTROL

25(11)

26(12)

REFERENCE

–

SENSE

C

T

LTC1142L-ADJ

LTC1142HV-ADJ

3(17)

1142 BD

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OPERATIO

Refer to Functional Diagram

During the switch “ON” cycle in continuous mode, current

comparator C monitors the voltage between Pins 1 (15)

and 28 (14) connected across an external shunt in series

with the inductor. When the voltage across the shunt

reaches its threshold value, the PDrive output is switched

to V_IN, turning off the P-channel MOSFET. The timing

capacitor connected to Pin 25 (11) is now allowed to

discharge at a rate determined by the off-time controller.

The discharge current is made proportional to the output

voltage [measured by Pin 28 (14)] to model the inductor

current, which decays at a rate that is also proportional to

the output voltage. While the timing capacitor is discharg-

ing,theNDriveoutputgoestoV_IN,turningontheN-channel

MOSFET.

The LTC1142 series consists of two individual regulator

blocks, each using current mode, constant off-time archi-

tectures to synchronously switch an external pair of

complementary power MOSFETs. The two regulators are

internally set to provide output voltages of 3.3V and 5V for

the LTC1142. The LTC1142HV-ADJ/LTC1142L-ADJ are

configuredtoprovidetwouserselectableoutputvoltages,

each set by external resistor dividers. Operating fre-

quency is individually set on each section by the external

capacitors at C_T, Pins 11 and 25.

The output voltage is sensed by an internal voltage divider

connected to Sense^–, Pin 28 (14) (LTC1142) or external

divider returned to V_FB, Pin 2 (16) (LTC1142-ADJ). A

voltage comparator V and a gain block G compare the

divided output voltage with a reference voltage of 1.25V.

To optimize efficiency, the LTC1142 series automatically

switches between two modes of operation, Burst Mode

and continuous mode. The voltage comparator is the

primary control element when the device is in Burst Mode

operation, while the gain block controls the output voltage

in continuous mode.

When the voltage on the timing capacitor has discharged

past V_TH1, comparator T trips, setting the flip-flop. This

causes the NDrive output to go low (turning off the

N-channel MOSFET) and the PDrive output to also go low

(turning the P-channel MOSFET back on). The cycle then

repeats.

8

LTC1142/LTC1142L/LTC1142HV

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OPERATIO

Refer to Functional Diagram

As the load current increases, the output voltage de-

creases slightly. This causes the output of the gain stage

[Pin 27(13)] to increase the current comparator thresh-

old, thus tracking the load current.

hysteresis in comparator V, the P-channel MOSFET is

again turned on and this process repeats.

To avoid the operation of the current loop interfering with

Burst Modeoperation, a built-in offset V_OSis incorporated

in the gain stage. This prevents the current comparator

threshold from increasing until the output voltage has

dropped below a minimum threshold.

The sequence of events for Burst Modeoperation is very

similar to continuous operation with the cycle interrupted

by the voltage comparator. When the output voltage is at

or above the desired regulated value, the P-channel

MOSFET is held off by comparator V and the timing

capacitor continues to discharge below V_TH1. When the

timing capacitor discharges past V_TH2, voltage compara-

tor S trips, causing the internal sleep line to go low and the

N-channel MOSFET to turn off.

To prevent both the external MOSFETs from ever being

turned on at the same time, feedback is incorporated to

sense the state of the driver output pins. Before the NDrive

output can go high, the PDrive output must also be high.

Likewise, the PDrive output is prevented from going low

while the NDrive output is high.

The circuit now enters sleep mode with both power

MOSFETs turned off. In sleep mode a majority of the

circuitry is turned off, dropping the quiescent current

from 1.6mA to 160µA (for one regulator block). The load

current is now being supplied from the output capacitor.

When the output voltage has dropped by the amount of

Using constant off-time architecture, the operating fre-

quency is a function of the input voltage. To minimize the

frequency variation as dropout is approached, the off-time

controller increases the discharge current as V_INdrops

below V_OUT+ 1.5V. In dropout the P-channel MOSFET is

turned on continuously (100% duty cycle) providing low

dropout operation with V_OUT~ V_IN.

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APPLICATIO S I FOR ATIO

T

he basic LTC1142 application circuit is shown in

Figure 1. External component selection is driven by the

load requirement and begins with the selection of R_SENSE

yielding a maximum output current I_MAXequal to the peak

value less half the peak-to-peak ripple current. For proper

Burst Mode operation, I_RIPPLE(P-P)must be less than or

equal to the minimum current comparator threshold.

.

Once R_SENSEis known, C_Tand L can be chosen. Next, the

power MOSFETs and D1 are selected. Finally, C_INand

C_OUTare selected and the loop is compensated. Since the

3.3V and 5V sections in the LTC1142 are identical and

similarly section 1 and section 2 in the LTC1142HV-ADJ/

LTC1142L-ADJ are identical, the process of component

selection is the same for both sections. The circuit shown

in Figure 1 can be configured for operation up to an input

voltage of 20V.

Since efficiency generally increases with ripple current,

the maximum allowable ripple current is assumed, i.e.,

I_RIPPLE(P-P)= 25mV/R_SENSE(see C_Tand L Selection for

Operating Frequency section). Solving for R_SENSEand

allowing a margin for variations in the LTC1142 and

external component values yields:

100mV

I_MAX

R_SENSE

=

R

_SENSESelection for Output Current

A graph for Selecting R_SENSEvs Maximum Output Current

is given in Figure 2.

R_SENSEis chosen based on the required output current.

The LTC1142 current comparators have a threshold range

which extends from a minimum of 25mV/R_SENSEto a

maximum of 150mV/R_SENSE. The current comparator

threshold sets the peak of the inductor ripple current,

The load current below which Burst Modeoperation com-

mences, I_BURST, andthepeakshort-circuitcurrentI_SC(PK)

,

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A graph for selecting C_Tversus frequency including the

effects of input voltage is given in Figure 3.

bothtrackI_MAX.OnceR_SENSEhasbeenchosen,I_BURSTand

_SC(PK)can be predicted from the following:

I

As the operating frequency is increased the gate charge

losses will be higher, reducing efficiency (see Efficiency

Considerations section). The complete expression for

operating frequency of the circuit in Figure 1 is given by:

15mV

R_SENSE

I_BURST

≈

150mV

R_SENSE

I_SC(PK)

=

1

t_OFF

V_OUT

V

IN

f =

1−

The LTC1142 automatically extends t_OFFduring a short

circuit to allow sufficient time for the inductor current to

decay between switch cycles. The resulting ripple current

causes the average short-circuit current I_SC(AVG)to be

where:

V_REG

V_OUT

t_OFF= 1.3• 10⁴• C_T•

reduced to approximately I_MAX

.

0.20

V_REGis the desired output voltage (i.e., 5V, 3.3V). V_OUT

is the measured output voltage. Thus V_REG/V_OUT= 1 in

regulation.

0.15

0.10

0.05

0

Note that as V_INdecreases, the frequency decreases.

When the input-to-output voltage differential drops below

1.5V for a particular section, the LTC1142 reduces t_OFFin

thatsectionbyincreasingthedischargecurrentinC_T. This

prevents audible operation prior to dropout.

0

1

2

3

4

5

1000

V

= V

= 5V

OUT

SENSE

MAXIMUM OUTPUT CURRENT (A)

1142 F02

800

600

400

200

0

Figure 2. Selecting R_SENSE

L and C_TSelection for Operating Frequency

EachregulatorsectionoftheLTC1142usesaconstantoff-

time architecture with t_OFFdetermined by an external

timing capacitor C_T. Each time the P-channel MOSFET

switchturnson,thevoltageonC_Tisresettoapproximately

3.3V. During the off-time, C_Tis discharged by a current

which is proportional to V_OUT. The voltage on C_Tis

analogous to the current in inductor L, which likewise

decays at a rate proportional to V_OUT. Thus the inductor

value must track the timing capacitor value.

V

= 12V

IN

V

= 7V

50

IN

V

= 10V

IN

0

150

200

250

300

100

FREQUENCY (kHz)

1142 F03

Figure 3. Timing Capacitor Value

OncethefrequencyhasbeensetbyC_T,theinductorLmust

be chosen to provide no more than 25mV/R_SENSEof peak-

to-peak inductor ripple current. This results in a minimum

required inductor value of:

The value of C_Tis calculated from the desired continuous

mode operating frequency:

1

C_T=

L_MIN= 5.1 • 10⁵• R_SENSE• C_T• V_REG

2.6• 10⁴• f

As the inductor value is increased from the minimum

value, the ESR requirements for the output capacitor are

Assumes V_IN= 2V_OUT, Figure 1 circuit.

10

LTC1142/LTC1142L/LTC1142HV

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APPLICATIO S I FOR ATIO

eased at the expense of efficiency. If too small an inductor

is used, the inductor current will decrease past zero and

changepolarity.AconsequenceofthisisthattheLTC1142

may not enter Burst Modeoperation and efficiency will be

severely degraded at low currents.

Theminimuminputvoltagedetermineswhetherstandard

threshold or logic-level threshold MOSFETs must be

used. For V_IN> 8V, standard threshold MOSFETs

(

V

< 4V) may be used. If V is expected to drop

GS(TH) IN

below 8V, logic-level threshold MOSFETs (V

<

GS(TH)

2.5V) are strongly recommended. When logic-level

MOSFETs are used, the LTC1142 supply voltage must

Inductor Core Selection

be less than the absolute maximum V ratings for the

GS

Once the minimum value for L is known, the type of

inductor must be selected. The highest efficiency will be

obtained using ferrite, molypermalloy (MPP), or Kool Mµ^®

cores. Lower cost powdered iron cores provide suitable

performance, but cut efficiency by 3% to 7%. Actual core

loss is independent of core size for a fixed inductor value,

but it is very dependent on inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

MOSFETs.

ThemaximumoutputcurrentI_MAXdeterminestheR_DS(ON)

requirement for the two MOSFETs. When the LTC1142 is

operating in continuous mode, the simplifying assump-

tion can be made that one of the two MOSFETs is always

conducting the average load current. The duty cycles for

the two MOSFETs are given by:

V_OUT

V

IN

P-Ch Duty Cycle =

Ferrite designs have very low core loss, so design goals

canconcentrateoncopperlossandpreventingsaturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design cur-

rent is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage

ripple which can cause Burst Modeoperation to be falsely

triggered. Do not allow the core to saturate!

V − V_OUT

IN

N-Ch Duty Cycle =

V

IN

From the duty cycles the required R_DS(ON)for each

MOSFET can be derived:

V • P_P

IN

P-Ch R_DS(ON)

N-Ch R_DS(ON)

=

2

Kool Mµ (from Magnetics, Inc.) is a very good, low loss

core material for toroids with a “soft” saturation charac-

teristic. Molypermalloy is slightly more efficient at high

(>200kHz)switchingfrequencies, butitisquiteabitmore

expensive. Toroids are very space efficient, especially

when you can use several layers of wire. Because they

generally lack a bobbin, mounting is more difficult. How-

ever, new designs for surface mount are available from

Coiltronics and Beckman Industrial Corporation which do

not increase the height significantly.

V_OUT• I_MAX• 1+ δ_P

(

)

V • P_N

IN

2

V − V_OUT• I_MAX• 1+ δ_N

(

IN

)

(

)

where P_Pand P_Nare the allowable power dissipations and

δ_Pand δ_Nare the temperature dependencies of R_DS(ON)

.

P_Pand P_Nwill be determined by efficiency and/or thermal

requirements (see Efficiency Considerations). (1 + δ) is

generally given for a MOSFET in the form of a normalized

R_DS(ON)vs Temperature curve, but δ = 0.007/°C can be

used as an approximation for low voltage MOSFETs.

Power MOSFET and D1, D2 Selection

Two external power MOSFETs must be selected for use with

each section of the LTC1142: a P-channel MOSFET for the

mainswitch, andanN-channelMOSFETforthesynchronous

switch. The main selection criteria for the power MOSFETs

The Schottky diodes D1 and D2 shown in Figure 1 only

conduct during the dead-time between the conduction of

the respective power MOSFETs. The sole purpose of D1

and D2 is to prevent the body diode of the N-channel

MOSFET from turning on and storing charge during the

arethethresholdvoltageV_GS(TH)andon-resistanceR_DS(ON)

.

Kool Mµ is a registered trademark of Magnetics, Inc.

11

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dead-time, which could cost as much as 1% in efficiency

(although there are no other harmful effects if D1 and D2

are omitted). Therefore, D1 and D2 should be selected for

fromSanyohasthelowestESR/sizeratioofanyaluminum

electrolytic at a somewhat higher price. Once the ESR

requirement for C_OUThas been met, the RMS current

rating generally far exceeds the I_RIPPLE(P-P)requirement.

a forward voltage of less than 0.6V when conducting I_MAX

.

In surface mount applications multiple capacitors may

have to be parallel to meet the capacitance, ESR or RMS

current handling requirements of the application. Alumi-

num electrolytic and dry tantalum capacitors are both

available in surface mount configurations. In the case of

tantalum, it is critical that the capacitors are surge tested

for use in switching power supplies. An excellent choice

is the AVX TPS series of surface mount tantalums, avail-

able in case heights ranging from 2mm to 4mm. For

example, if 200µF/10V is called for in an application

requiring 3mm height, two AVX 100µF/10V (P/N TPSD

107K010) could be used. Consult the manufacturer for

other specific recommendations.

C_INand C_OUTSelection

In continuous mode, the source current of the P-channel

MOSFET is a square wave of duty cycle V_OUT/V_IN. To

prevent large voltage transients, a low ESR input capaci-

torsizedforthemaximumRMScurrentmustbeused.The

maximum RMS capacitor current is given by:

1/2

]

V_OUTV − V_OUT

(

IN

)

[

C_INRequired I_RMS≈I_MAX

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst case conditon is com-

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the

capacitor, or to choose a capacitor rated at a higher

temperaturethanrequired.Severalcapacitorsmayalsobe

paralleled to meet size or height requirements in the

design. Always consult the manufacturer if there is any

question. An additional 0.1µF to 1µF ceramic capacitor is

also required on each V_INline (Pins 10 and 24) for high

frequency decoupling.

At low supply voltages, a minimum capacitance at C_OUTis

needed to prevent an abnormal low frequency operating

mode (see Figure 4). When C_OUTis made too small, the

outputrippleatlowfrequencieswillbelargeenoughtotrip

the voltage comparator. This causes Burst Mode opera-

tion to be activated when the LTC1142 would normally be

in continuous operation. The output remains in regulation

at all times.

1000

L = 50µH

R

= 0.02Ω

SENSE

800

600

400

200

0

The selection of C_OUTis driven by the required Effective

Series Resistance (ESR). The ESR of C_OUTmust be less

than twice the value of R_SENSEfor proper operation of the

LTC1142:

L = 25µH

SENSE

R

= 0.02Ω

L = 50µH

= 0.05Ω

C_OUTRequired ESR < 2R_SENSE

R

SENSE

Optimum efficiency is obtained by making the ESR equal

to R_SENSE. As the ESR is increased up to 2R_SENSE, the

efficiency degrades by less than 1%. If the ESR is greater

than 2R_SENSE, the voltage ripple on the output capacitor

willprematurelytriggerBurstModeoperation, resultingin

disruption of continuous mode and an efficiency hit which

can be several percent.

0

1

2

3

4

5

V

IN

– V

OUT

VOLTAGE (V)

1142 F04

Figure 4. Minimum Value of C_OUT

Checking Transient Response

The regulator loop response can be checked by looking

attheloadtransientresponse. Switchingregulatorstake

several cycles to respond to a step in DC (resistive) load

Manufacturers such as Nichicon and United Chemicon

should be considered for high performance capacitors.

The OS-CON semiconductor dielectric capacitor available

12

LTC1142/LTC1142L/LTC1142HV

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APPLICATIO S I FOR ATIO

section) less the gate charge current. For V_IN= 10V the

LTC1142 DC supply current for each section is 160µA

with no load, and increases proportionally with load up

to a constant 1.6mA after the LTC1142 has entered

continuous mode. Because the DC bias current is

drawn from V_IN, the resulting loss increases with input

voltage. For V_IN= 10V the DC bias losses are generally

less than 1% for load currents over 30mA. However, at

very low load currents the DC bias current accounts for

nearly all of the loss.

current. When a load step occurs, V_OUTshifts by an

amountequalto∆I_LOAD•ESR,whereESRistheeffective

series resistance of C_OUT. ∆I_LOADalso begins to charge

or discharge C_OUTuntil the regulator loop adapts to the

current change and returns V_OUTto its steady- state

value. During this recovery time V_OUTcan be monitored

for overshoot or ringing which would indicate a stability

problem. ThePin27(13)externalcomponentsshownin

theFigure1circuitwillproveadequatecompensationfor

most applications.

2. MOSFET gate charge current results from switching

the gate capacitance of the power MOSFETs. Each time

a MOSFET gate is switched from low to high to low

again, a packet of charge dQ moves from V_INto ground.

The resulting dQ/dt is a current out of V_INwhich is

typically much larger than the DC supply current. In

continuous mode, I_GATE(CHG)= f (Q_N+ Q_P). The typical

gate charge for a 0.1Ω N-channel power MOSFET is

25nC, and for a P-channel about twice that value. This

results in I_GATE(CHG)= 7.5mA in 100kHz continuous

operation, for a 2% to 3% typical mid-current loss with

V_IN= 10V.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately 25 • C_LOAD.

Thus a 10µF capacitor would require a 250µs rise time,

limiting the charging current to about 200mA.

Efficiency Considerations

Note that the gate charge loss increases directly with

both input voltage and operating frequency. This is the

principal reason why the highest efficiency circuits

operate at moderate frequencies. Furthermore, it ar-

gues against using larger MOSFETs than necessary to

control I²R losses, since overkill can cost efficiency as

well as money!

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

3. I²R losses are easily predicted from the DC resistances

oftheMOSFET,inductor,andcurrentshunt.Incontinu-

ous mode the average output current flows through L

and R_SENSE, but is “chopped” between the P-channel

and N-channel MOSFETs. If the two MOSFETs have

approximately the same R_DS(ON), then the resistance of

one MOSFET can simply be summed with the resis-

tances of L and R_SENSEto obtain I²R losses. For

example, if each R_DS(ON)= 0.1Ω, R_L= 0.15Ω, and

R_SENSE= 0.05Ω, then the total resistance is 0.3Ω. This

results in losses ranging from 3% to 12% as the output

current increases from 0.5A to 2A. I²R losses cause the

efficiency to roll off at high output currents.

where L1, L2, etc., are the individual losses as a percent-

age of input power. (For high efficiency circuits only small

errors are incurred by expressing losses as a percentage

of output power.)

Although all dissipative elements in the circuit produce

losses, threemainsourcesusuallyaccountformostofthe

losses in LTC1142 circuits:

1. LTC1142 DC bias current

2. MOSFET gate charge current

3. I²R losses

1. The DC supply current is the current which flows into

V_IN(pin 24 for the 3.3V section, Pin 10 for the 5V

13

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Figure 5 shows how the efficiency losses in one section of

a typical LTC1142 regulator end up being apportioned.

The gate charge loss is responsible for the majority of the

efficiency lost in the mid-current region. If Burst Mode

operation was not employed at low currents, the gate

charge loss alone would cause efficiency to drop to

unacceptable levels. With Burst Mode operation, the DC

supply current represents the lone (and unavoidable) loss

component which continues to become a higher percent-

age as output current is reduced. As expected, the I²R

losses dominate at high load currents.

and δ_P= δ_N= 0.007(63 – 25) = 0.27. The required R_DS(ON)

for each MOSFET can now be calculated:

12(0.25)

5(2)²(1.27)

P -Ch R_DS(ON)

N-Ch R_DS(ON)

=

= 0.12Ω

12(0.25)

5(2)²(1.27)

= 0.085Ω

The P-channel requirement can be met by a Si9430DY,

while the N-channel requirement is exceeded by a

Si9410DY. Note that the most stringent requirement for

theN-channelMOSFETiswithV_OUT=0(i.e., shortcircuit).

During a continuous short circuit, the worst case

N-channel dissipation rises to:

Other losses including C_INand C_OUTESR dissipative

losses, MOSFET switching losses, Schottky conduction

losses during dead-time and inductor core losses, gener-

ally account for less than 2% total additional loss.

P_N= I_SC(AVG)²• R_DS(ON)• (1 + δ_N)

100

With the 0.05Ω sense resistor, I_SC(AVG)= 2A will result,

increasingthe0.085ΩN-channeldissipationto450mWat

a die temperature of 73°C.

2

I R

GATE CHARGE

95

1/2 LTC1142 I

Q

C_INwill require an RMS current rating of at least 1A at

temperature, and C_OUTwill require an ESR of 0.05Ω for

optimum efficiency.

90

85

80

NowallowV_INtodroptoitsminimumvalue. Atlowerinput

voltages the operating frequency will decrease and the

P-channel will be conducting most of the time, causing its

power dissipation to increase. At V_IN(MIN)= 7V:

0.01

0.03

0.1

0.3

1

3

OUTPUT CURRENT (A)

1142 F05

f_MIN= (1/2.92µs)[1 – (5V/7V)] = 98kHz

5V(0.12Ω)(2A)²(1.27)

Figure 5. Efficiency Loss

Design Example

P_P=

= 435mV

7V

As a design example, assume V_IN= 12V (nominal), 5V

section, I_MAX= 2A and f = 200kHz; R_SENSE, C_Tand L can

immediately be calculated:

A similar calculation for the 3.3V section results in the

component values shown in Figure 14.

R_SENSE= 100mV/2 = 0.05Ω

LTC1142HV-ADJ/LTC1142L-ADJ

Adjustable Applications

t_OFF= (1/200kHz) • [1 – (5/12)] = 2.92µs

C_T5= 2.92µs/(1.3 • 10⁴) = 220pF

L2_MIN= 5.1 • 10⁵• 0.05Ω • 220pF • 5V = 28µH

When an output voltage other than 3.3V or 5V is required,

the LTC1142 adjustable version is used with an external

resistive divider from V_OUTto V_FB, Pin 2 (16). The regu-

lated output voltage is determined by:

Assume that the MOSFET dissipations are to be limited to

P_N= P_P= 250mW.

R2

R1

If T_A= 50°C and the thermal resistance of each MOSFET

is 50°C/W, then the junction temperatures will be 63°C

V_OUT= 1.25 1+

14

LTC1142/LTC1142L/LTC1142HV

U

W U U

APPLICATIO S I FOR ATIO

To prevent stray pickup a 100pF capacitor is suggested

across R1 located close to the LTC1142HV-ADJ/LTC1142L-

ADJ as in Figure 6. The external divider network must be

placed across C_OUTwith the negative plate of C_OUTreturned

to signal ground. Refer to the Board Layout Checklist.

the layout diagram of Figure 7. In general each block

should be self-contained with little cross coupling for best

performance. Check the following in your layout:

1. Are the signal and power grounds segregated? The

LTC1142signalground[Pin3(17) fortheLTC1142, Pin

4 (18) for LTC1142-ADJ] must return tothe(–) plate of

R

SENSE

V

C

. The power ground returns to the source of the

R2

OUT

V

FB

OUT

[PIN 2(16)]

N-channel MOSFET, anode of the Schottky diode,

+

R1

100pF

C

OUT

and (–) plate of C , which should have as short lead

lengths as possible.

IN

SGND

[PIN 4(18)]

1142 F06

2. Does the LTC1142 Sense^–, Pin 28 (14) connect to a

Figure 6. LTC1142-ADJ External Feedback Network

point close to R_SENSEand the (+) plate of C_OUT

?

3. Are the Sense^–and Sense⁺leads routed together with

minimum PC trace spacing? The 1000pF capacitor

between Pins 1 (15) and 28 (14) should be as close as

possibletotheLTC1142.Ensureaccuratecurrentsens-

Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1142. These items are also illustrated graphically in

SENSE RESISTOR PCB PATTERN

1000pF

+

R

SENSE3

+

C

1

2

OUT3

28

27

26

25

24

23

+

–

+

–

V

1k

OUT3

SENSE SENSE

SENSE 3

3300pF

SHDN (3.3V OUTPUT)

SHDN3

SGND3

I

C

TH3

T3

+

3

–

INTV

CC3

L1

4

PGND3

NC

C

T3

C

IN5

5

+

V

IN3

V

P-CH

IN5

+

6

PDRIVE 3

NDRIVE 3

NC

1µF

D2

N-CH

7

NC 22

–

LTC1142

D1

NC

21

8

NC

–

N-CH

P-CH

9

PDRIVE 5

20

1µF

NDRIVE 5

+

C

IN3

V

IN3

+

10

11

12

13

14

19

18

17

16

15

NC

V

IN5

V

C

IN5

PGND5

SGND5

SHDN5

T5

L2

INTV

CC5

–

3300pF

–

+

C

T5

I

SHDN (5V OUTPUT)

TH5

V

OUT5

+

1k

SENSE 5

C

OUT5

+

R

SENSE5

+

1000pF

BOLD LINES INDICATE HIGH CURRENT PATHS

1142 F07

Figure 7. LTC1142 Layout Diagram (see Board Layout Checklist)

15

LTC1142/LTC1142L/LTC1142HV

U U

U

W

APPLICATIO S I FOR ATIO

PIN 26(12)

ing with Kelvin connections. Be sure to use a PCB

pattern similar to that shown in Figure 7 for the current

sense resistors.

INT V

CC

FROM CROWBAR

DETECT CIRCUIT

VN2222LL

PIN 25(11)

LTC1142

(ACTIVE WHEN V

= V

IN

GATE

OFF WHEN V

= GND)

GATE

C

T

4. Does the (+) plate of C_INconnect to the source of the

P-channelMOSFETascloselyaspossible?Thiscapaci-

tor provides the AC current to the P-channel MOSFET.

1142 F08

Figure 8. Output Crowbar Interface

Troubleshooting Hints

5. Is the input decoupling capacitor (1µF/0.22µF) con-

nected closely between Pin 24 (10) and power ground

[Pin4(18)fortheLTC1142,Pin5(19)fortheLTC1142-

ADJ]? This capacitor carries the MOSFET driver peak

currents.

Since efficiency is critical to LTC1142 applications, it is

very important to verify that the circuit is functioning

correctly in both continuous and Burst Mode operation.

The waveform to monitor is the voltage on the C_T, Pins 25

and 11.

6. Are the shutdown Pins 2 and 16 for the LTC1142 (Pins

3 and 17 for the LTC1142-ADJ) actively pulled to

ground during normal operation? Both Shutdown pins

are high impedance and must not be allowed to float.

Both pins can be driven by the same external signal if

needed.

In continuous mode (I_LOAD> I_BURST) the voltage on the C_T

pin should be a sawtooth with a 0.9V_P-Pswing. This

voltage should never dip below 2V as shown in Figure 9a.

When load currents are low (I_LOAD< I_BURST) Burst Mode

operation occurs. The voltage on the C_Tpin now falls to

ground for periods of time as shown in Figure 9b.

7. For the LTC1142-ADJ adjustable applications, the re-

sistive divider R1, R2 must be connected between the

(+) plate of C_OUTand signal ground.

3.3V

0V

Output Crowbar

(a) CONTINUOUS MODE OPERATION

An added feature to using an N-channel MOSFET as the

synchronous switch is the ability to crowbar the output

with the same MOSFET. Pulling the C_T, Pin 25 (11) above

1.5V when the output voltage is greater than the desired

regulated value will turn “on” the N-channel MOSFET for

that regulator section.

3.3V

0V

1142 F09

(b) Burst Mode OPERATION

Figure 9. C_TWaveforms

A fault condition which causes the output voltage to go

above a maximum allowable value can be detected by

external circuitry. Turning on the N-channel MOSFET

when this fault is detected will cause large currents to flow

and blow the system fuse.

Inductor current should also be monitored. Look to verify

that the peak-to-peak ripple current in continuous mode

operation is approximately the same as in Burst Mode

operation.

If Pin 25 or Pin 11 is observed falling to ground at high

output currents, it indicates poor decoupling or improper

grounding. Refer to the Board Layout Checklist.

The N-channel MOSFET needs to be sized so it will safely

handle this overcurrent condition. The typical delay from

pullingtheC_TpinhighandtheNDrivePin6(20)goinghigh

is 250ns. Note: Under shutdown conditions, the N-chan-

nel is held OFF and pulling the C_Tpin high will not cause

the N-channel MOSFET to crowbar the output.

Auxiliary Windings––Suppressing Burst Mode

Operation

The LTC1142 synchronous switch removes the normal

limitation that power must be drawn from the inductor

primary winding in order to extract power from auxiliary

windings. With synchronous switching, auxiliary outputs

A simple N-channel FET can be used as an interface

between the overvoltage detect circuitry and the LTC1142

as shown in Figure 8.

16

LTC1142/LTC1142L/LTC1142HV

U

W U U

APPLICATIO S I FOR ATIO

may be loaded without regard to the primary output load,

providing that the loop remains in continuous mode

operation.

With the addition of R3 a current is generated through R1

causing an offset of:

R1

R1+R3

Burst Mode operation can be suppressed at low output

currents with a simple external network which cancels the

25mV minimum current comparator threshold. This tech-

nique is also useful for eliminating audible noise from

certain types of inductors in high current (I_OUT> 5A)

applications when they are lightly loaded.

An external offset is put in series with the Sense^–pin to

subtract from the built-in 25mV offset. An example of this

technique is shown in Figure 10. Two 100Ω resistors are

inserted in series with the sense leads from the sense

resistor.

V

_OFFSET= V_OUT•

If V_OFFSET> 25mV, the built-in offset will be cancelled and

Burst Modeoperation is prevented from occurring. Since

V_OFFSETis constant, the maximum load current is also

decreased by the same offset. Thus, to get back to the

same I_MAX, the value of the sense resistor must be lower:

75mV

R_SENSE

≈

I_MAX

R2

To prevent noise spikes from erroneously tripping the

current comparator, a 1000pF capacitor is needed across

Pins 1 (15) and Pins 28 (14).

100Ω

+

SENSE

[PIN 1(15)]

R1

100Ω

R

SENSE

1000pF

–

SENSE

V

OUT

[PIN 28(14)]

+

R3

C

OUT

1142 F10

Figure 10. Suppression of Burst Mode Operation

U

TYPICAL APPLICATIO S

(For additional high efficiency circuits, see Application Note 54)

V

IN

5.2V TO 18V

C

IN2

C

+

IN1

22µF

35V

× 2

22µF

35V

× 2

0.22µF

0V = NORMAL

>1.5V = SHDN

P-CH

3

24

17

10

Si9430DY

V

SHDN1

V

IN2

PDRIVE 2

SHDN2

IN1

L1

27µH

23

1

L2

33µH

9

R

SENSE2

0.05Ω

SENSE1

0.05Ω

PDRIVE 1

V

OUT1

V

OUT2

5V/2A

3.6V/2A

15

+

SENSE 2

SENSE 1

1000pF

LTC1142HV-ADJ

–

SENSE

1

SENSE

2

28

2

14

16

V

FB2

FB1

C

OUT2

C

+

OUT1

+

NDRIVE 1

NDRIVE 2

220µF

10V

20

6

10V

× 2

D1

D2

N-CH

Si9410DY

N-CH

Si9410DY

C

PGND1 SGND1

C

I

SGND2

18

PGND2

19

R2

100k

1%

T2

T1

TH1

27

TH2

13

R

C2

1k

× 2

MBRS130T3

R4

150k

1%

5

4

25

11

R

C1

1k

R1

52.3k

1%

R3

49.9k

1%

100pF

C

C2

C

T1

C1

T2

270pF 3300pF 3300pF 270pF

R

: DALE WSL-2010-.05

SENSE1, SENSE2

1142 F11

L1: SUMIDA CDRH125-270

L2: SUMIDA CDRH125-330

Figure 11. LTC1142HV-ADJ Dual Regulator with 3.6V/2A and 5V/2A Outputs

17

LTC1142/LTC1142L/LTC1142HV

U

TYPICAL APPLICATIO S

V

IN

4.5V TO 18V

C

IN2

C

+

+ ^IN1

22µF

35V

× 2

22µF

35V

× 2

0.22µF

0V = NORMAL

>1.5V = SHDN

P-CH

3

24

17

10

Si9430DY

V

SHDN1

V

IN2

PDRIVE 2

SHDN2

IN1

L1

23

1

L2

25µH

9

R

SENSE2

0.05Ω

SENSE1

PDRIVE 1

33µH

0.075Ω

V

OUT1

V

OUT2

3.3V/2A

2.5V/1.5A

15

+

SENSE

2

SENSE 1

1000pF

LTC1142HV-ADJ

–

SENSE

1

14

16

28

2

V

FB2

FB1

C

OUT2

C

OUT1

+

NDRIVE 1

NDRIVE 2

220µF

10V

20

6

10V

× 2

D2

D1

N-CH

C

PGND1 SGND1

C

I

SGND2

18

PGND2

19

R2

49.9k

1%

× 2

T2

T1

TH1

27

TH2

13

MBRS130T3

R4

84.5k

1%

Si9410DY

5

4

25

11

R

C2

1k

R

C1

1k

R1

49.9k

1%

R3

51k

1%

100pF

C

C2

C

T1

C1

T2

330pF 3300pF 3300pF 330pF

R

: IRC L1206-01-R075-J

SENSE1

: IRC L1206-01-R050-J

SENSE2

L1: COILTRONICS CTX33-4

L2: COILTRONICS CTX25-4

1142 F12

Figure 12. LTC1142HV-ADJ High Efficiency Regulator with 3.3V/2A and 2.5V/1.5A Outputs

V

IN

5.2V TO 18V

C

IN3

+

C

IN5

22µF

25V

× 2

0.22µF

0V = NORMAL

>1.5V = SHDN

22µF

25V

× 2

2

24

16

10

P-CH

V

SHDN3

V

IN5

SHDN5

IN3

Si9433DY

Si9430DY

23

1

9

L1

L2

R

PDRIVE 5

SENSE3

PDRIVE 3

SENSE5

0.05Ω

10µH

22µH

V

0.033Ω

OUT3

3.3V/3A

V

OUT5

5V/2A

15

+

SENSE 3

SENSE 5

LTC1142HV

1000pF

–

SENSE

3

SENSE

5

14

20

28

6

D1

MBRS130T3

D2

NDRIVE 3

NDRIVE 5

MBRS130T3

N-CH

Si9410DY

N-CH

Si9410DY

C

PGND3 SGND3

C

I

SGND5

17

PGND5

18

T5

T3

TH3

27

TH5

13

R

C5

1k

C

+

+ ^OUT3

OUT5

4

3

25

11

100µF

220µF

10V

× 3

R

C3

510Ω

× 2

C

T5

T3

C3

C5

200pF 3300pF 3300pF 150pF

R : IRC L1206-01-R033-J

SENSE3

R : IRC L1206-01-R050-J

SENSE5

L1: COILCRAFT D03316P-103

L2: COILCRAFT D03316P-223

1142 F13

Figure 13. LTC1142HV High Efficiency Regulator with 3.3V/3A and 5V/2A Outputs

18

LTC1142/LTC1142L/LTC1142HV

U

TYPICAL APPLICATIO S

V

IN

22µF

25V

× 2

+

22µF

25V

× 2

+

0V = NORMAL

>1.5V = SHDN

6.5V TO

14V

1µF

2

24

16

10

P-CH

T1

Si9430DY

V

SHDN3

V

IN5

SHDN5

IN3

23

1

9

L1

33µH

R

SENSE5

0.04Ω

SENSE3

0.05Ω

PDRIVE 3

PDRIVE 5

V

30µH

OUT3

3.3V/2A

V

OUT5

5V/2A

15

+

SENSE

3

SENSE 5

LTC1142

100Ω

1000pF

0.01µF

R1,100Ω

–

3

SENSE 5

14

20

28

6

R5

18k

D1

MBRS140T3

NDRIVE 3

NDRIVE 5

D2

MBRS140T3

N-CH

C

PGND3 SGND3

C

I

SGND5

17

PGND5

18

T5

T3

TH3

27

TH5

13

+

220µF

10V

× 2

+

100µF

Si9410DY

4

3

25

11

10V

R

C5

510Ω

R

C3

510Ω

× 2

VN2222LL

C

T5

T3

C3

C5

390pF 3300pF 3300pF 200pF

12V ENABLE

0V = 12V OFF

>3V = 12V ON

(6V MAX)

12V/150mA

1

C9

+

22Ω

R3

649k

1%

V

OUT

22µF

25V

D3

22µF

20pF

+

5

MBRS140T3

35V

SHUTDOWN

2

1000pF

ADJ

LT1121

8

1142 F14

R4

294k

1%

V

IN

R

: KRL SL-C1-1/2-0R050J

: KRL SL-C1-1/2-0R040J

L1: COILTRONICS CTX33-4

T1: DALE LPE-6562-A026

PRIMARY: SECONDARY = 1:1.8

SENSE3

SENSE5

GND

3

Figure 14. LTC1142 Triple Output Regulator with Switched 12V Output

V

IN

8V TO 18V

0V = CHARGE ON

>1.5V = CHARGE OFF

0V = OUTPUT ON

>1.5V = 3.3V OUTPUT OFF

FROM WALL ADAPTER

C

+

IN2

V

BATT

22µF

25V

× 2

C

+

IN1

22µF

4 CELLS

NiCAD

0.22µF

D3

35V

× 2

MBRS340T3

P-CH

24

17

10

3

Si9433DY

Si9430DY

V

SHDN1

V

IN2

PDRIVE 2

SHDN2

IN1

L1

23

1

L2

25µH

9

R

SENSE2

0.05Ω

SENSE1

0.1Ω

PDRIVE 1

50µH

V

OUT2

3.3V/2A

+

15

SENSE 1

+

SENSE 2

1000pF

LTC1142HV-ADJ

–

SENSE 1

SENSE 2

28

2

14

16

V

FB2

FB1

C

OUT1

OUT2

+

NDRIVE 1

NDRIVE 2

PGND2

220µF

6

20

10V

× 2

D1

D2

N-CH

C

SGND1

PGND1

5

C

I

R2

274k

1%

T2

T1

TH1

TH2

13

SGND2

18

MBRS140T3

R4

Si9410DY

4

25 27

11

19

84.5k

1%

R

C1

1k

C2

1k

R1

49.9k

1%

R3

51k

1%

100pF

C

T2

T1

C1

C2

3300pF 330pF

200pF 3300pF

VN2222LL

“1” FOR TRICKLE CHARGE

FAST CHARGE = 130mV/R

= 1.3A

SENSE1

TRICKLE CHARGE = 130mV/R

= 100mA

1142 F15

R

: KRL SL-C1-1/2-1R100J

: KRL SL-C1-1/2-1R050J

R

X

51Ω

SENSE1

SENSE2

L1: COILTRONICS CTX50-4

L2: COILTRONICS CTX25-4

Figure 15. LTC1142HV-ADJ High Efficiency Power Supply Providing 3.3V/2A with Built-In Battery Charger

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1142/LTC1142L/LTC1142HV

U

TYPICAL APPLICATIO S

1400

1200

1000

800

600

400

200

0

1

2

4

0

3

SET RESISTANCE (kΩ)

1142 F16

Figure 16. LTC1142HV-ADJ Output Current vs Trickle Charge Set Resistance

(R_X) for the Circuit in Figure 15 Using a 0.1Ω Current Sense Resistor R_SENSE1

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

10.07 – 10.33*

(0.397 – 0.407)

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

0° – 8°

7.65 – 7.90

(0.301 – 0.311)

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

5

7

8

1

2

3

4

6

9 10 11 12 13 14

G28 SSOP 1098

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

SO-8 with Current Limit. No R

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High Power Synchronous Step-Down Controller

No R

^TMCurrent Mode Synchronous Step-Down Controller

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SENSE

Above 95% Efficiency, Needs No R

, 16-Lead SSOP Package

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Fits SO-8 Footprint

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Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ V ≤ 36V

LTC1702 w/ 5-Bit Mobile VID for Mobile Pentium^®Processor Systems

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OUT

No R

is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

1142fd LT/TP 0600 2K REV D • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1995

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LLTC1142HV
厂家：	Linear
描述：	Dual High Efficiency Synchronous Step-Down Switching Regulators 双通道高效率同步降压型开关稳压器稳压器开关
文件：	总20页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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