LT1054CSW-PBF_技术文档

LT1054/LT1054L

Switched-Capacitor Voltage

Converter with Regulator

FEATURES

DESCRIPTION

The LT^®1054 is a monolithic, bipolar, switched-capacitor

voltage converter and regulator. The LT1054 provides

higher output current than previously available converters

with significantly lower voltage losses. An adaptive switch

driver scheme optimizes efficiency over a wide range of

output currents. Total voltage loss at 100mA output current

is typically 1.1V. This holds true over the full supply voltage

range of 3.5V to 15V. Quiescent current is typically 2.5mA.

■ꢀ

Output Current: 100mA (LT1054)

125mA (LT1054L)

■

Reference and Error Ampliﬁer for Regulation

■

Low Loss: 1.1V at 100mA

■

Operating Range:3.5V to 15V (LT1054)

3.5V to 7V (LT1054L)

■

External Shutdown

■

External Oscillator Synchronization

■

Can Be Paralleled

The LT1054 also provides regulation, a feature not previ-

ouslyavailableinswitched-capacitorvoltageconverters.By

adding an external resistive divider a regulated output can

be obtained. This output will be regulated against changes

in both input voltage and output current. The LT1054 can

also be shut down by grounding the feedback pin. Supply

current in shutdown is less than 100µA.

Pin Compatible with the LTC^®1044/ICL7660

■

Available in SW16 and SO-8 Packages

APPLICATIONS

■

Voltage Inverter

■

Voltage Regulator

The internal oscillator of the LT1054 runs at a nominal

frequency of 25kHz. The oscillator pin can be used to ad-

just the switching frequency or to externally synchronize

the LT1054.

■

Negative Voltage Doubler

Positive Voltage Doubler

■

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

The LT1054 is pin compatible with previous converters

such the LTC1044/ICL7660.

BLOCK DIAGRAM

V

REF

6

V

IN

LT1054/LT1054 Voltage Loss

8

2

2.5V

3.5V ≤ V ≤ 15V (LT1054)

IN

REFERENCE

LT1054L

3.5V ≤ V ≤ 7V (LT1054L)

IN

R

DRIVE

CAP

C

= C

= 100µF

OUT

IN

INDICATES GUARANTEED

TEST POINT

+

–

+

–

2

4

+

C

*

LT1054

IN

Q

1

FEEDBACK/

SHUTDOWN

1

0

OSC

Q

CAP

7

R

T

= 125°C

= 25°C

= –55°C

J

OSC

DRIVE

3

5

GND

+

*EXTERNAL CAPACITORS

C

*

0

25

50

75

100

125

OUT

OUTPUT CURRENT (mA)

–V

OUT

1054 TA01•

LT1054 • BD

1954lfg

1

LT1054/LT1054L

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Supply Voltage (Note 2)

Maximum Junction Temperature (Note 3)

LT1054 .................................................................16V

LT1054L .................................................................7V

LT1054C/LT1054LC ......................................... 125°C

LT1054I............................................................. 125°C

LT1054M........................................................... 150°C

Storage Temperature Range

J8, N8 and S8 Packages.................... –55°C to 150°C

S Package......................................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

Input Voltage

+

Pin 1 ................................................. 0V ≤ V

Pin 3 (S Package) ............................. 0V ≤ V

Pin 7 .............................................. 0V ≤ V

≤ V

PIN1

PIN3

≤ V

PIN7

REF

Pin 13 (S Package) ...................... 0V ≤ V

≤ V

PIN13

REF

Operating Junction Temperature Range

LT1054C/LT1054LC .............................. 0°C to 100°C

LT1054I............................................. –40°C to 100°C

LT1054M............................................ –55°C to 125°C

PIN CONFIGURATION

TOP VIEW

NC

1

2

3

4

5

6

7

8

16 NC

TOP VIEW

+

FB/SHDN

1

2

3

4

8

7

6

5

V

15 NC

+

FB/SHDN

1

2

3

4

V

8

7

6

5

CAP

OSC

FB/SHDN

14

V

+

CAP

OSC

CAP

13 OSC

GND

V

REF

–

GND

12

11

10

9

GND

V

CAP

V

REF

OUT

–

CAP

V

OUT

S8 PACKAGE

8-LEAD PLASTIC SO

= 125°C, θ = 120°C/W

NC

N8 PACKAGE

8-LEAD PLASTIC DIP 8-LEAD CERAMIC DIP

= 125°C, θ = 130°C/W

J8 PACKAGE

T

JMAX

JA

SEE REGULATION AND CAPACITOR SELECTION SECTIONS

IN THE APPLICATIONS INFORMATION FOR IMPORTANT

INFORMATION ON THE S8 DEVICE

T

JMAX

JA

SW PACKAGE

16-LEAD PLASTIC SO

T

JMAX

= 125°C, θ = 150°C/W

JA

ORDER INFORMATION

LEAD FREE FINISH

LT1054CN8#PBF

LT1054IN8#PBF

LT1054MJ8#PBF

LT1054CS8#PBF

LT1054LCS8#PBF

LT1054IS8#PBF

LT1054CSW#PBF

LT1054ISW#PBF

TAPE AND REEL

PART MARKING

LT1054CN8

LT1054IN8

LT1054MJ8

1054

PACKAGE DESCRIPTION

8-Lead Plastic DIP

8-Lead Ceramic DIP

8-Lead Plastic SO

16-Lead Plastic SO

8-Lead Ceramic DIP

TEMPERATURE RANGE

0°C to 100°C

LT1054CN8#TRPBF

LT1054IN8#TRPBF

LT1054MJ8#TRPBF

LT1054CS8#TRPBF

LT1054LCS8#TRPBF

LT1054IS8#TRPBF

LT1054CSW#TRPBF

LT1054ISW#TRPBF

–40°C to 100°C

–55°C to 125°C

0°C to 100°C

1054L

0°C to 100°C

1054I

–40°C to 100°C

0°C to 100°C

LT1054CSW

LT1054ISW

LT1054CJ8

–40°C to 100°C

0°C to 100°C

LT1054CJ8#PBF OBSOLETE PART LT1054CJ8#TRPBF

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

1054lfg

2

LT1054/LT1054L

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 7)

PARAMETER

CONDITIONS

= 0mA

MIN

TYP

MAX

UNITS

l

Supply Current

I

LT1054:

V

IN

V

IN

= 3.5V

= 15V

2.5

3.0

4.0

5.0

mA

LOAD

l

LT1054L: V = 3.5V

2.5

3.0

4.0

5.0

mA

IN

V

= 7V

IN

l

Supply Voltage Range

LT1054

LT1054L

3.5

15

7

V

Voltage Loss (V – |V |)

C

= C

= 100µF Tantalum (Note 4)

OUT

IN

OUT

IN

l

I

= 10mA

0.35

1.10

1.35

0.55

1.60

1.75

V

OUT

= 100mA

= 125mA (LT1054L)

l

Output Resistance

10

15

Ω

∆I

OUT

= 10mA to 100mA (Note 5)

l

Oscillator Frequency

LT1054: 3.5V ≤ V ≤ 15V

15

25

40

35

kHz

IN

LT1054L: 3.5V ≤ V ≤ 7V

IN

Reference Voltage

I

= 60µA, T = 25°C

2.35

2.25

2.50

2.65

2.75

V

REF

J

l

Regulated Voltage

Line Regulation

Load Regulation

V

= 7V, T = 25°C, R = 500Ω (Note 6)

–4.70

–5.00

5

–5.20

25

V

mV

mA

µA

IN

J

L

l

LT1054: 7V ≤ V ≤ 12V, R = 500Ω (Note 6)

IN

L

V

IN

= 7V, 100Ω ≤ 500Ω (Note 6)

10

50

Maximum Switch Current

300

100

l

Supply Current in Shutdown

V

= 0V

200

PIN1

Note 5: Output resistance is defined as the slope of the curve, (∆V

OUT

portion of the curve. The incremental slope of the curve will be higher at

currents <10mA due to the characteristics of the switch transistors.

vs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

OUT

∆I ), for output currents of 10mA to 100mA. This represents the linear

Note 6: All regulation specifications are for a device connected as a

positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k,

Note 2: The absolute maximum supply voltage rating of 16V is for

unregulated circuits using LT1054. For regulation mode circuits using

C1 = 0.002µF, (C1 = 0.05µF S package) C = 10µF tantalum, C

= 100µF

LT1054 with V

≤ 15V at Pin 5 (Pin 11 on S package), this rating may be

IN

OUT

tantalum.

increased to 20V. The absolute maximum supply voltage for LT1054L is 7V.

Note 7: The S8 package uses a different die than the H, J8, N8 and S

packages. The S8 device will meet all the existing data sheet parameters.

See Regulation and Capacitor Selection in the Applications Information

section for differences in application requirements.

Note 3: The devices are guaranteed by design to be functional up to the

absolute maximum junction temperature.

Note 4: For voltage loss tests, the device is connected as a voltage inverter,

with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected. The voltage

losses may be higher in other configurations.

1954lfg

3

LT1054/LT1054L

TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Threshold

Supply Current

Oscillator Frequency

0.6

0.5

0.4

0.3

5

4

3

2

35

25

15

I

L

= 0

V

PIN1

V

= 15V

IN

V

= 3.5V

IN

0.2

0.1

0

1

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

0

10

5

INPUT VOLTAGE (V)

15

–70 –50

50

TEMPERATURE (°C)

100 125

–25

0

25

75

LT1054 • TPC01

LT1054 • TPC02

LT1054 • TPC03

Supply Current in Shutdown

Average Input Current

Output Voltage Loss

120

100

80

60

40

20

0

140

120

1.4

1.2

I

= 100mA

OUT

V

= 0V

PIN1

100

1.0

80

60

40

20

0.8

0.6

0.4

0.2

I

= 50mA

= 10mA

OUT

INVERTER CONFIGURATION

C

= 100µF TANTALUM

= 25kHz

OUT

OSC

f

0

60

OUTPUT CURRENT (mA)

80

100

0

10

5

INPUT VOLTAGE (V)

15

20

40

100

50 60 70 80 90

0

30

10 20

40

INPUT CAPACITANCE (µF)

LT1054 • TPC04

LT1050 • TPC05

LT1054 • TPC06

Output Voltage Loss

INVERTER CONFIGURATION

C

= 10µF TANTALUM

IN

= 100µF TANTALUM

OUT

C

= 100µF TANTALUM

IN

= 100µF TANTALUM

OUT

2

1

0

2

1

0

I

= 100mA

OUT

I

= 100mA

= 50mA

OUT

I

= 50mA

= 10mA

OUT

I

OUT

= 10mA

1

10

OSCILLATOR FREQUENCY (kHz)

100

1

10

100

OSCILLATOR FREQUENCY (kHz)

LT1054 • TPC07

LT1054 • TPC08

1054lfg

4

LT1054/LT1054L

TYPICAL PERFORMANCE CHARACTERISTICS

Reference Voltage Temperature

Coefficient

Regulated Output Voltage

–4.7

–4.8

100

80

V

AT 0 = 2.500V

REF

–4.9

60

–5.0

40

–5.1

20

–11.6

–11.8

–12.0

–12.2

–12.4

–12.6

0

–20

–40

–60

–80

–100

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

LT1054 • TPC09

LT1054 • TPC10

PIN FUNCTIONS

FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has

twofunctions.PullingPin1belowtheshutdownthreshold

(≈0.45V) puts the device into shutdown. In shutdown the

reference/regulator is turned off and switching stops. The

switchesaresetsuchthatbothC andC aredischarged

Pin 1 is also the inverting input of the LT1054’s error

amplifier and as such can be used to obtain a regulated

output voltage.

+

–

CAP /CAP (Pin 2/Pin 4): Pin 2, the positive side of the

+

IN

OUT

input capacitor (C ), is alternately driven between V

IN

through the output load. Quiescent current in shutdown

drops to approximately 100µA (see Typical Performance

Characteristics). Any open-collector gate can be used to

put the LT1054 into shutdown. For normal (unregulated)

operation the device will start back up when the external

gate is shut off. In LT1054 circuits that use the regulation

feature, the external resistor divider can provide enough

pull-down to keep the device in shutdown until the output

+

and ground. When driven to V , Pin 2 sources current

+

from V . When driven to ground Pin 2 sinks current to

ground. Pin 4, the negative side of the input capacitor, is

driven alternately between ground and V . When driven

OUT

to ground, Pin 4 sinks current to ground. When driven to

V

Pin 4 sources current from C . In all cases current

OUT

flowintheswitchesisunidirectionalasshouldbeexpected

using bipolar switches.

capacitor (C ) has fully discharged. For most applica-

OUT

V

OUT

(Pin 5): In addition to being the output pin this pin

tions where the LT1054 would be run intermittently, this

does not present a problem because the discharge time

of the output capacitor will be short compared to the off-

time of the device. In applications where the device has

is also tied to the substrate of the device. Special care

must be taken in LT1054 circuits to avoid pulling this

pin positive with respect to any of the other pins. Pulling

Pin 5 positive with respect to Pin 3 (GND) will forward

biasthesubstratediodewhichwillpreventthedevicefrom

starting. This condition can occur when the output load

driven by the LT1054 is referred to its positive supply (or

to some other positive voltage). Note that most op amps

present just such a load since their supply currents flow

to start up before the output capacitor (C ) has fully

OUT

discharged, a restart pulse must be applied to Pin 1 of

the LT1054. Using the circuit of Figure 5, the restart signal

can be either a pulse (t > 100µs) or a logic high. Diode

p

coupling the restart signal into Pin 1 will allow the output

voltage to come up and regulate without overshoot. The

resistor divider R3/R4 in Figure 5 should be chosen to

provide a signal level at pin 1 of 0.7V to 1.1V.

+

–

from their V terminals to their V terminals. To prevent

start-up problems with this type of load an external

1954lfg

5

LT1054/LT1054L

PIN FUNCTIONS

transistor must be added as shown in Figure 1. This will

OSC (Pin 7): Oscillator Pin. This pin can be used to raise

or lower the oscillator frequency or to synchronize the

device to an external clock. Internally Pin 7 is connected

prevent V

(Pin 5) from being pulled above the ground

OUT

pin (Pin 3) during start-up. Any small, general purpose

to the oscillator timing capacitor (C ≈ 150pF) which is

transistor such as 2N2222 or 2N2219 can be used. R

t

X

alternately charged and discharged by current sources of

7µAsothatthedutycycleis≈50ꢀ. TheLT1054oscillator

is designed to run in the frequency band where switch-

ing losses are minimized. However the frequency can be

raised, lowered, or synchronized to an external system

clock if necessary.

should be chosen to provide enough base drive to the

external transistor so that it is saturated under nominal

output voltage and maximum output current conditions.

In some cases an N-channel enhancement mode MOSFET

can be used in place of the transistor.

V

β

(

)

OUT

R_X≤

The frequency can be lowered by adding an external

capacitor (C1, Figure 2) from Pin 7 to ground. This will

increase the charge and discharge times which lowers the

oscillator frequency. The frequency can be increased by

adding an external capacitor (C2, Figure 2, in the range

of 5pF to 20pF) from Pin 2 to Pin 7. This capacitor will

I_OUT

+

V

I

Q

L

+

–

LOAD

couple charge into C at the switch transitions, which will

T

I

OUT

+

shorten the charge and discharge time, raising the oscil-

lator frequency. Synchronization can be accomplished

by adding an external resistive pull-up from Pin 7 to the

reference pin (Pin 6). A 20k pull-up is recommended. An

open collector gate or an NPN transistor can then be used

to drive the oscillator pin at the external clock frequency

as shown in Figure 2. Pulling up Pin 7 to an external volt-

age is not recommended. For circuits that require both

frequency synchronization and regulation, an external

reference can be used as the reference point for the top

of the R1/R2 divider allowing Pin 6 to be used as a pull-

up point for Pin 7.

FB/SHDN

V

+

CAP

OSC

LT1054 • F01

+

R

LT1054

GND

X

C

IN

V

REF

–

CAP

V

OUT

C

OUT

+

Figure 1

V

(Pin 6): Reference Output. This pin provides a 2.5V

REF

referencepointforuseinLT1054-basedregulatorcircuits.

The temperature coefficient of the reference voltage has

been adjusted so that the temperature coefficient of the

regulated output voltage is close to zero. This requires the

referenceoutputtohaveapositivetemperaturecoefficient

as can be seen in the typical performance curves. This

nonzero drift is necessary to offset a drift term inherent

in the internal reference divider and comparator network

tied to the feedback pin. The overall result of these drift

terms is a regulated output which has a slight positive

temperature coefficient at output voltages below 5V and a

slight negative TC at output voltages above 5V. Reference

output current should be limited, for regulator feedback

networks, to approximately 60µA. The reference pin will

draw ≈100µA when shorted to ground and will not af-

fect the internal reference/regulator, so that this pin can

also be used as a pull-up for LT1054 circuits that require

synchronization.

+

V

FB/SHDN

V

C2

C1

IN

+

CAP

OSC

+

LT1054

GND

C

V

REF

IN

LT1054 • F02

–

CAP

V

OUT

C

OUT

+

Figure 2

+

V (Pin 8): Input Supply. The LT1054 alternately charges

to the input voltage when C is switched in parallel

C

IN

with the input supply and then transfers charge to C

OUT

when C is switched in parallel with C . Switching oc-

curs at the oscillator frequency. During the time that C

IN

OUT

IN

1054lfg

6

LT1054/LT1054L

PIN FUNCTIONS

is charging, the peak supply current will be approximately

capacitorof2µF,preferablytantalumorsomeotherlowESR

type is recommended. A larger capacitor may be desirable

in some cases, for example, when the actual input supply

is connected to the LT1054 through long leads, or when

the pulse current drawn by the LT1054 might affect other

circuitry through supply coupling.

equal to 2.2 times the output current. During the time that

C is delivering charge to C

the supply current drops

IN

OUT

to approximately 0.2 times the output current. An input

supply bypass capacitor will supply part of the peak input

current drawn by the LT1054 and average out the current

drawn from the supply. A minimum input supply bypass

APPLICATIONS INFORMATION

Theory of Operation

V1

V2

f

R

To understand the theory of operation of the LT1054, a re-

viewofabasicswitched-capacitorbuildingblockishelpful.

L

C1

C2

LT1054 • F03

In Figure 3 when the switch is in the left position, capaci-

tor C1 will charge to voltage V1. The total charge on C1

will be q1 = C1V1. The switch then moves to the right,

discharging C1 to voltage V2. After this discharge time

the charge on C1 is q2 = C1V2. Note that charge has been

transferred from the source V1 to the output V2. The

amount of charge transferred is:

Figure 3. Switched-Capacitor Building Block

R

EQUIV

V1

V2

1

fC1

R

L

C2

R

EQUIV

=

LT1054 • F04

Figure 3. Switched-Capacitor Equivalent Circuit

∆q = q1 – q2 = C1(V1 – V2)

eventually be dominated by the 1/fC1 term and voltage

losses will rise.

If the switch is cycled f times per second, the charge

transfer per unit time (i.e., current) is:

Note that losses also rise as frequency increases. This is

caused by internal switching losses which occur due to

somefinitechargebeinglostoneachswitchingcycle.This

chargelossper-unit-cycle,whenmultipliedbytheswitching

frequency, becomes a current loss. At high frequency this

loss becomes significant and voltage losses again rise.

I = (f)(∆q) = (f)[C1(V1 – V2)]

To obtain an equivalent resistance for the switched-

capacitor network we can rewrite this equation in terms

of voltage and impedance equivalence:

V1– V2 V1– V2

1/ fC1 R_EQUIV

I=

=

The oscillator of the LT1054 is designed to run in the

frequency band where voltage losses are at a minimum.

A new variable R is defined such that R

= 1/fC1.

EQUIV

Thus the equivalent circuit for the switched-capacitor

network is as shown in Figure 4. The LT1054 has the same

switching action as the basic switched-capacitor building

block.Eventhoughthissimplificationdoesn’tincludefinite

switchon-resistanceandoutputvoltageripple, itprovides

anintuitivefeelforhowthedeviceworks.

Regulation

T

he error amplifier of the LT1054 servos the drive to the

PNPswitchtocontrolthevoltageacrosstheinputcapaci-

tor (C ) which in turn will determine the output voltage.

IN

Using the reference and error amplifier of the LT1054,

an external resistive divider is all that is needed to set

the regulated output voltage. Figure 5 shows the basic

regulator configuration and the formula for calculating

the appropriate resistor values. R1 should be chosen to

1954lfg

These simplified circuits explain voltage loss as a function

of frequency (see Typical Performance Characteristics).

As frequency is decreased, the output impedance will

7

LT1054/LT1054L

APPLICATIONS INFORMATION

ground pin of the LT1054 must be less than the total of the

supply voltage minus the voltage loss due to the switches.

Thevoltagelossversusoutputcurrentduetotheswitches

canbefoundinTypicalPerformanceCharacteristics.Other

configurations such as the negative doubler can provide

higher output voltages at reduced output currents (see

Typical Applications).

2.2µF

R3

V

IN

+

FB/SHDN

V

+

CAP

OSC

C

10µF

TANTALUM

+

IN

R4

LT1054

GND

R1

R2

V

REF

–

CAP

V

OUT

C1

RESTART SHUTDOWN

V

OUT

|V

REF

|

|V

|

OUT

R2

R1

OUT

=

+ 1 ≈

+ 1

Capacitor Selection

V

1.21V

C

OUT

– 40mV

)

100µF

TANTALUM

2

+

ForunregulatedcircuitsthenominalvaluesofC andC

WHERE V

= 2.5V NOMINAL

IN

OUT

REF

LT1054 • F05

should be equal. For regulated circuits see the section on

FOR EXAMPLE: TO GET V

PIN OF THE LT1054, CHOOSE R1 = 20k, THEN

= –5V REFERRED TO THE GROUND

OUT

Regulation. While the exact values of C and C

are

IN

OUT

|–5V|

noncritical, goodquality, lowESRcapacitorssuchassolid

R2 = 20k

+ 1 = 102.6k*

2.5V

)

– 40mV

tantalum are necessary to minimize voltage losses at high

currents. For C the effect of the ESR of the capacitor will

2

*CHOOSE THE CLOSEST 1% VALUE

IN

be multiplied by four due to the fact that switch currents

areapproximatelytwotimeshigherthanoutputcurrentand

losses will occur on both the charge and discharge cycle.

Figure 5

be 20k or greater because the reference output current

is limited to ≈100µA. R2 should be chosen to be in the

range of 100k to 300k. For optimum results the ratio of

This means that using a capacitor with 1Ω of ESR for C

IN

will have the same effect as increasing the output imped-

C /C

is recommended to be 1/10. C1, required for

IN OUT

ance of the LT1054 by 4Ω. This represents a significant

good load regulation at light load currents, should be

increaseinthevoltagelosses. ForC

theaffectofESRis

OUT

0.002µF for all output voltages.

less dramatic. C

is alternately charged and discharged

OUT

at a current approximately equal to the output current and

the ESR of the capacitor will cause a step function to oc-

cur in the output ripple at the switch transitions. This step

function will degrade the output regulation for changes

in output load current and should be avoided. Realizing

that large value tantalum capacitors can be expensive, a

technique that can be used is to parallela smaller tantalum

capacitor with a large aluminum electrolytic capacitor to

gain both low ESR and reasonable cost. Where physical

size is a concern some of the newer chip type surface

mount tantalum capacitors can be used. These capacitors

are normally rated at working voltages in the 10V to 20V

range and exhibit very low ESR (in the range of 0.1Ω).

A new die layout was required to fit into the physical

dimensions of the S8 package. Although the new die

of the LT1054CS8 will meet all the specifications of the

existing LT1054 data sheet, subtle differences in the

layout of the new die require consideration in some ap-

plication circuits. In regulating mode circuits using the

1054CS8 the nominal values of the capacitors, C and

IN

C

OUT

, must be approximately equal for proper operation

at elevated junction temperatures. This is different from

the earlier part. Mismatches within normal production

tolerances for the capacitors are acceptable. Making the

nominal capacitor values equal will ensure proper opera-

tion at elevated junction temperatures at the cost of a

small degradation in the transient response of regulator

Output Ripple

circuits. For unregulated circuits the values of C and

IN

C

OUT

are normally equal for all packages. For S8 applica-

The peak-to-peak output ripple is determined by the value

of the output capacitor and the output current. Peak-to-

peak output ripple may be approximated by the formula:

tions assistance in unusual applications circuits, please

consult the factory.

It can be seen from the circuit block diagram that the

maximumregulatedoutputvoltageislimitedbythesupply

voltage. For the basic configuration, |V_OUT|referred to the

I_OUT

dV =

2fC_OUT

1054lfg

8

LT1054/LT1054L

APPLICATIONS INFORMATION

wheredV=peak-to-peakrippleandf=oscillatorfrequency.

where:

For output capacitors with significant ESR a second term

mustbeaddedtoaccountforthevoltagestepattheswitch

transitions. This step is approximately equal to:

V ≈ V – [(LT1054 Voltage Loss)(1.3) + |V_OUT|]

X

IN

and I

= maximum required output current. The factor

OUT

of 1.3 will allow some operating margin for the LT1054.

(2I )(ESR of C

)

OUT

For example: assume a 12V to –5V converter at 100mA

outputcurrent.Firstcalculatethepowerdissipationwithout

an external resistor:

Power Dissipation

The power dissipation of any LT1054 circuit must be

limited such that the junction temperature of the device

does not exceed the maximum junction temperature rat-

ings. The total power dissipation must be calculated from

two components, the power loss due to voltage drops

in the switches and the power loss due to drive current

losses. The total power dissipated by the LT1054 can be

calculated from:

P = (12V – |–5V|)(100mA) + (12V)(100mA)(0.2)

P = 700mW + 240mW = 940mW

At θ of 130°C/W for a commercial plastic device this

JA

would cause a junction temperature rise of 122°C so that

the device would exceed the maximum junction tempera-

ture at an ambient temperature of 25°C. Now calculate the

power dissipation with an external resistor (R ). First find

X

how much voltage can be dropped across R . The maxi-

X

P ≈ (V – |V_OUT|)(I ) + (V )(I )(0.2)

IN

OUT

IN OUT

mum voltage loss of the LT1054 in the standard regulator

where both V and V

are referred to the ground pin

configuration at 100mA output current is 1.6V, so:

IN

OUT

(Pin 3) of the LT1054. For LT1054 regulator circuits, the

power dissipation will be equivalent to that of a linear

regulator. Due to the limited power handling capability of

the LT1054 packages, the user will have to limit output

currentrequirementsortakestepstodissipatesomepower

external to the LT1054 for large input/output differentials.

This can be accomplished by placing a resistor in series

V = 12V – [(1.6V)(1.3) + |–5V|] = 4.9V and

X

R = 4.9V/(4.4)(100mA) = 11Ω

X

This resistor will reduce the power dissipated by the

LT1054 by (4.9V)(100mA) = 490mW. The total power dis-

sipated by the LT1054 would then be (940mW – 490mW)

= 450mW. The junction temperature rise would now be

only 58°C. Although commercial devices are guaranteed

to be functional up to a junction temperature of 125°C, the

specifications are only guaranteed up to a junction tem-

perature of 100°C, so ideally you should limit the junction

temperature to 100°C. For the above example this would

mean limiting the ambient temperature to 42°C. Other

steps can be taken to allow higher ambient temperatures.

The thermal resistance numbers for the LT1054 packages

represent worst-case numbers with no heat sinking and

still air. Small clip-on type heat sinks can be used to lower

the thermal resistance of the LT1054 package. In some

systems there may be some available airflow which will

helptolowerthethermalresistance. WidePCboardtraces

from the LT1054 leads can also help to remove heat from

the device. This is especially true for plastic packages.

with C as shown in Figure 6. A portion of the input

IN

voltage will then be dropped across this resistor without

affecting the output regulation. Because switch current is

approximately2.2timestheoutputcurrentandtheresistor

will cause a voltage drop when C is both charging and

IN

discharging, the resistor should be chosen as:

R = V /(4.4 I

)

X

OUT

V

IN

+

FB/SHDN

V

R

X

+

CAP

OSC

+

LT1054

R1

R2

C1

C

IN

GND

V

REF

–

CAP

V

OUT

V

OUT

C

OUT

+

LT1054 • F06

Figure 6

1954lfg

9

LT1054/LT1054L

TYPICAL APPLICATIONS

Basic Voltage Inverter

Basic Voltage Inverter/Regulator

+

2µF

V

IN

V

FB/SHDN

V

IN

+

FB/SHDN

V

2µF

+

CAP

OSC

+

LT1054

GND

+

CAP

OSC

100µF

V

REF

+

LT1054

GND

R1

R2

10µF

V

REF

–

–V

100µF

CAP

V

OUT

–

+

CAP

V

OUT

0.002µF

LT1054 • TAO2

V

OUT

|V

REF

|

|V

|

R2

R1

OUT

1.21V

=

+ 1 =

+ 1 ,

100µF

V

+

)

– 40mV

2

LT1054 • TA03

REFER TO FIGURE 5

Negative Voltage Doubler

Positive Doubler

V

IN

+

FB/SHDN

V

+

–

3.5V TO 15V

1N4001

100µF

1N4001

V

OUT

+

CAP

OSC

+

LT1054

GND

V

OUT

+

2µF

10µF

FB/SHDN

V

50mA

V

REF

IN

Q *

X

100µF

–

+

–

V

CAP

V

OUT

R *

X

100µF

2µF

+

CAP

LT1054

GND

OSC

+

V

REF

V

= 3.5V TO 15V

IN

OUT

V

IN

≈ 2V – (V + 2V )

V

= –3.5V TO –15V

–

IN

L

DIODE

IN

CAP

V

OUT

= LT1054 VOLTAGE LOSS

L

= 2V + (LT1054 VOLTAGE LOSS) + (Q SATURATION VOLTAGE)

OUT

IN

X

LT1054 • TAO5

*SEE FIGURE 3

LT1054 • TAO4

100mA Regulating Negative Doubler

V

IN

3.5 TO 15V

+

2.2µF

+

FB/SHDN

V

FB/SHDN

V

HP5082-2810

PIN 2

LT1054 #1

+

CAP

OSC

CAP

OSC

V

OUT

+

LT1054 #1

GND

LT1054 #2

GND

20k

SET

10µF

V

REF

R1

40k

–

CAP

V

CAP

V

OUT

1N4002

10µF

+

0.002µF

+

R2

500k

1N4002

–V

OUT

I

≅ 100mA MAX

1N4002

V

= 3.5 TO 15V

100µF

IN

+

LT1054 • TAO6

MAX ≈ –2V + [1054 VOLTAGE LOSS + 2(V )]

OUT

IN

DIODE

|V

REF

|

|V

|

OUT

R2

R1

OUT

=

+ 1 =

+ 1

, REFER TO FIGURE 5

V

1.21V

– 40mV

)

2

1054lfg

10

LT1054/LT1054L

TYPICAL APPLICATIONS

Bipolar Supply Doubler

V

IN

3.5V TO 15V

+

–

+

10µF

100µF

+

+V

OUT

FB/SHDN

V

+

CAP

OSC

+

LT1054

GND

10µF

V

REF

100µF

+

–

CAP

V

OUT

–

+

100µF

V

+V

–V

= 3.5V TO 15V

IN

+

–V

OUT

≈ 2V – (V + 2V

)

OUT

IN

L

DIODE

≈ –2V + (V + 2V

)

OUT

IN

L

DIODE

V

= LT1054 VOLTAGE LOSS

L

LT1054 • TAO7

= 1N4001

5V to 12V Converter

V

IN

= 5V

+

5µF

1N914

≈ 12V

1N914

V

OUT

+

I

= 25mA

FB/SHDN

V

+

100µF

10µF

TO PIN 4

+

FB/SHDN

V

CAP

OSC

LT1054 #1

+

LT1054 #1

GND

+

10µF

CAP

OSC

V

REF

LT1054 #2

GND

20k

2N2219

1k

–

V

REF

CAP

V

OUT

100µF

5µF

V

OUT

≈ –12V

= 25mA

–

OUT

+

CAP

V

OUT

I

100µF

+

LT1054 • TAO8

Strain Gauge Bridge Signal Conditioner

5V

10k

+

INPUT TTL

OR CMOS

LOW FOR ON

10k

ZERO

TRIM

10µF

40Ω

2N2907

5k

GAIN

TRIM

8

100k

5k

0.022µF

1

–

6

5

2

1M

301k

A1

A2

7

^{1/2 LT1013}+ ³

1/2 LT1013

+

10k

350Ω

4

200k

1µF

LT1054 • TAO9

+

FB/SHDN

V

5V

3k

+

A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE

BRIDGE OUTPUT OF 24mV

CAP

OSC

2N2222

+

LT1054

GND

+

10µF

V

100µF

TANTALUM

REF

–

CAP

V

OUT

1954lfg

11

LT1054/LT1054L

TYPICAL APPLICATIONS

3.5V to 5V Regulator

V

IN

3.5V TO 5.5V

20k

1

2

3

4

8

7

6

5

1N914

+

LTC1044

1N914

+

1µF

FB/SHDN

V

+

5µF

+

CAP

OSC

R1

20k

R2

125k

+

LT1054

GND

10µF

V

REF

+

–

1µF

+

–

+

0.002µF

CAP

V

OUT

R2

125k

3k

V

OUT

= 5V

100µF

V

I

= 3.5V TO 5.5V

OUT

IN

= 5V

2N2219

= 50mA

OUT(MAX)

1N914

LT1054 • TA10

1N5817

Regulating 200mA, 12V to –5V Converter

5µF

12V

+

HP5082-2810

+

FB/SHDN

V

FB/SHDN

V

+

CAP

LT1054 #2

GND

OSC

CAP

LT1054 #1

GND

OSC

R1

39.2k

+

10Ω

1/2W

20k

10Ω

1/2W

10µF

V

REF

10µF

R2

200k

–

0.002µF

CAP

V

OUT

CAP

V

OUT

+

LT1054 • TA11

200µF

|V

REF

|

|V

|

R2

=

OUT

1.21V

+

+ 1 =

+ 1 ,

R1

V

I

= –5V

= 0mA to 200mA

OUT

– 40mV

)

2

REFER TO FIGURE 5

Digitally Programmable Negative Supply

15V

+

11

5µF

20k

16

DIGITAL

INPUT

AD558

LT1004-2.5

2.5V

+

FB/SHDN

V

+

14

13

12

20k

CAP

OSC

+

LT1054

GND

10µF

V

REF

LT1054 • TA12

–

CAP

V

OUT

V

OUT

= –V (PROGRAMMED)

IN

100µF

+

1054lfg

12

LT1054/LT1054L

PACKAGE DESCRIPTION

J8 Package

8-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)

.405

(10.287)

MAX

CORNER LEADS OPTION

(4 PLCS)

.005

(0.127)

MIN

6

5

4

8

7

.023 – .045

(0.584 – 1.143)

HALF LEAD

OPTION

.025

.220 – .310

(5.588 – 7.874)

.045 – .068

(0.635)

RAD TYP

(1.143 – 1.650)

FULL LEAD

OPTION

1

2

3

.200

(5.080)

MAX

.300 BSC

(7.62 BSC)

.015 – .060

(0.381 – 1.524)

.008 – .018

(0.203 – 0.457)

0 – 15

.045 – .065

(1.143 – 1.651)

.125

3.175

MIN

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE

OR TIN PLATE LEADS

.014 – .026

(0.360 – 0.660)

.100

(2.54)

BSC

J8 0801

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

.400*

(10.160)

MAX

.130 .005

.300 – .325

.045 – .065

(3.302 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

8

7

6

5

4

.065

(1.651)

TYP

.255 .015*

(6.477 0.381)

.008 – .015

(0.203 – 0.381)

.120

.020

(0.508)

MIN

(3.048)

MIN

+.035

–.015

1

2

3

.325

.018 .003

(0.457 0.076)

.100

(2.54)

BSC

+0.889

8.255

NOTE:

1. DIMENSIONS ARE

(

)

N8 1002

–0.381

INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

1954lfg

13

LT1054/LT1054L

PACKAGE DESCRIPTION

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.189 – .197

(4.801 – 5.004)

NOTE 3

.045 ±.005

.050 BSC

7

5

8

6

.245

MIN

.160 ±.005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

.030 ±.005

TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

.010 – .020

× 45°

.053 – .069

(0.254 – 0.508)

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0°– 8° TYP

.016 – .050

(0.406 – 1.270)

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

SO8 0303

NOTE:

INCHES

1. DIMENSIONS IN

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

SW Package

16-Lead Plastic Small Outline (Wide .300 Inch)

(Reference LTC DWG # 05-08-1620)

.050 BSC .045 .005

.398 – .413

.030 .005

TYP

(10.109 – 10.490)

NOTE 4

15 14

12

10

11

9

N

16

N

13

.325 .005

.420

MIN

.394 – .419

(10.007 – 10.643)

NOTE 3

N/2

8

1

2

3

N/2

RECOMMENDED SOLDER PAD LAYOUT

2

3

5

7

1

4

6

.291 – .299

(7.391 – 7.595)

NOTE 4

.037 – .045

(0.940 – 1.143)

.093 – .104

(2.362 – 2.642)

.010 – .029

¥ 45∞

(0.254 – 0.737)

.005

(0.127)

RAD MIN

0 – 8 TYP

.050

(1.270)

BSC

.004 – .012

.009 – .013

(0.102 – 0.305)

NOTE 3

(0.229 – 0.330)

.014 – .019

.016 – .050

(0.356 – 0.482)

TYP

(0.406 – 1.270)

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

S16 (WIDE) 0502

2. DRAWING NOT TO SCALE

3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

1054lfg

14

LT1054/LT1054L

REVISION HISTORY ^{(Revision history begins at Rev F)}

REV

DATE

12/10 The LTC1054MJ8 is now available. Changes reflected throughout the data sheet

6/11 Correct error to part number from LTC7660 to ICL7660

DESCRIPTION

PAGE NUMBER

F

1 to 16

G

1

1954lfg

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT1054/LT1054L

TYPICAL APPLICATIONS

Negative Doubler with Regulator

Positive Doubler with Regulation

V

= 5V

IN

V

IN

3.5V TO 15V

+

50k

+

FB/SHDN

V

+

2µF

1N5817

FB/SHDN

V

+

10µF

V

2µF

+

OUT

8V

CAP

OSC

+

CAP

OSC

+

LT1054

GND

LT1054

GND

50mA

0.03µF

10µF

V

REF

1N5817

5.5k

V

REF

10k

+

R1, 20k

–

100µF

CAP

V

OUT

–

CAP

V

OUT

R2

1M

5V

100µF

0.002µF

+

10k

–

10k

1N4001

–V

LT1006

OUT

2.5k

+

100µF

V

= 3.5V TO 15V

IN

+

≈ –2V + (V + 2V

)

DIODE

OUT(MAX)

IN

L

= LT1054 VOLTAGE LOSS

L

LT1054 • TA13

|V

REF

|

|V

|

OUT

R2

R1

0.1µF

OUT

=

+ 1 =

+ 1

, REFER TO FIGURE 5

V

1.21V

– 40mV

)

LT1054 • TA14

2

THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS

ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Wide Input Voltage Range: 2V to 18V, I < 8µA, SO8

LTC^®1144

Switched-Capacitor Wide Input Range Voltage Converter with

Shutdown

SD

LTC1514/LTC1515

LT1611

Step-Up/Step-Down Switched-Capacitor DC/DC Converters

V : 2V to 10V, V : 3.3V to 5V, I = 60µA, SO8

IN

OUT

Q

150mA Output, 1.4mHz Micropower Inverting Switching Regulator V : 0.9V to 10V, V

:

34V ThinSOTꢁ

IN

OUT

LT1614

250mA Output, 600kHz Micropower Inverting Switching Regulator V : 0.9V to 6V, V

: 30V, I = 1mA, MS8, SO8

OUT Q

IN

LTC1911

250mA, 1.5MHz Inductorless Step-Down DC/DC Converter

V : 2.7V to 5.5V, V : 1.5V/1.8V, I = 180µA, MS8

IN OUT Q

LTC3250/LTC3250-1.2/ Inductorless Step-Down DC/DC Converter

LTC3250-1.5

V : 3.1V to 5.5V, V : 1.2V, 1.5V, I = 35µA, ThinSOT

IN OUT Q

LTC3251

500mA Spread Spectrum Inductorless Step-Down DC/DC Converter V : 2.7V to 5.5V, V : 0.9V to 1.6V, 1.2V, 1.5V, I = 9µA,

IN

MS10E

OUT

Q

LTC3252

Dual 250mA, Spread Spectrum Inductorless Step-Down

DC/DC Converter

V : 2.7V to 5.5V, V : 0.9V to 1.6V, I = 50µA, DFN12

IN OUT Q

1054lfg

LT 0611 REV G • PRINTED IN USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1054CSW-PBF
厂家：	Linear
描述：	Switched-Capacitor Voltage Converter with Regulator 开关电容电压转换器与调节器转换器调节器开关
文件：	总16页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1054CSW-PBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E