LT1054_技术文档

LT1054/LT1054L

Switched-Capacitor Voltage

Converter with Regulator

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DESCRIPTIO

EATURE

Available in Space Saving SO-8 Package

Output Current: 100mA (LT1054)

125mA (LT1054L)

Low Loss: 1.1V at 100mA

Operating Range:3.5V to 15V (LT1054)

3.5V to 7V (LT1054L)

Reference and Error Amplifier for Regulation

External Shutdown

S

F

The LT^®1054 is a monolithic, bipolar, switched-capacitor

voltage converter and regulator. The LT1054 provides

higher output current than previously available converters

with significantly lower voltage losses. An adaptive switch

driver scheme optimizes efficiency over a wide range of

outputcurrents. Total voltagelossat100mAoutputcurrent

is typically 1.1V. This holds true over the full supply voltage

range of 3.5V to 15V. Quiescent current is typically 2.5mA.

■

External Oscillator Synchronization

Can Be Paralleled

The LT1054 also provides regulation, a feature not previ-

ously available in switched-capacitor voltage converters.

By adding an external resistive divider a regulated output

can be obtained. This output will be regulated against

changes in both input voltage and output current. The

LT1054 can also be shut down by grounding the feedback

pin. Supply current in shutdown is less than 100µA.

Pin Compatible with the LTC^®1044/LTC7660

O U

PPLICATI

A

S

■

Voltage Inverter

Voltage Regulator

Negative Voltage Doubler

Positive Voltage Doubler

The internal oscillator of the LT1054 runs at a nominal

frequencyof25kHz.Theoscillatorpincanbeusedtoadjust

the switching frequency or to externally synchronize the

LT1054.

The LT1054 is pin compatible with previous converters

such the LTC1044/LTC7660.

, LTC and LT are registered trademarks of Linear Technology Corporation.

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BLOCK DIAGRAM

V

REF

6

V

IN

LT1054/LT1054L Voltage Loss

8

2

2.5V

3.5V ≤ V ≤ 15V (LT1054)

IN

REFERENCE

LT1054L

3.5V ≤ V ≤ 7V (LT1054L)

IN

C

IN

= C

= 100µF

OUT

R

DRIVE

CAP

INDICATES GUARANTEED

TEST POINT

+

–

+

–

2

4

+

LT1054

C

*

IN

Q

1

FEEDBACK/

SHUTDOWN

1

0

OSC

CAP

7

T

= 125°C

= 25°C

= –55°C

R

J

OSC

DRIVE

3

5

GND

*EXTERNAL CAPACITORS

+

0

25

50

75

100

125

C

*

OUT

OUTPUT CURRENT (mA)

–V

OUT

1054 TA01•

LT1054 • BD

1

LT1054/LT1054L

W W W

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(Note 1)

ABSOLUTE AXI U RATI GS

Supply Voltage (Note 2)

Maximum Junction Temperature (Note 3)

LT1054 ................................................................ 16V

LT1054L ................................................................ 7V

Input Voltage

LT1054C/LT1054LC ........................................ 125°C

LT1054I ............................................................ 125°C

LT1054M ......................................................... 150°C

Storage Temperature Range

Pin 1 ................................................. 0V ≤ V_PIN1≤ V⁺

Pin 3 (S Package) ............................. 0V ≤ V_PIN3≤ V⁺

Pin 7 ............................................. 0V ≤ V_PIN7≤ V_REF

Pin 13 (S Package) ...................... 0V ≤ V_PIN13≤ V_REF

Operating Junction Temperature Range

H, J8, N8 and S8 Packages................–55°C to 150°C

S Package........................................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

LT1054C/LT1054LC ............................. 0°C to 100°C

LT1054I ........................................... –40°C to 100°C

LT1054M ......................................... –55°C to 125°C

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/O

(Note 6)

PACKAGE RDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

ORDER PART

NUMBER

TOP VIEW

+

V

+

FB/SHDN

1

2

3

4

8

7

6

5

V

8

FB/SHDN

+

1

3

OSC

7

5

+

CAP

OSC

LT1054CS8

LT1054LCS8

LT1054CH

LT1054MH

GND

V

CAP

2

6

V

REF

–

CAP

V

OUT

GND

V

OUT

4

CASE

IS

S8 PACKAGE

S8 PART

MARKING

–

CAP

8-LEAD PLASTIC SO

V

OUT

H PACKAGE

8-LEAD TO-5 METAL CAN

T_JMAX= 125°C, θ_JA= 120°C/W

SEE REGULATION AND CAPACITOR SELECTION SECTIONS

IN THE APPLICATIONS INFORMATION FOR IMPORTANT

INFORMATION ON THE S8 DEVICE

T_JMAX= 150°C, θ_JA= 150°C, θ_JC= 45°C/W

1054

1054L

ORDER PART

NUMBER

ORDER PART

NUMBER

TOP VIEW

NC

1

2

3

4

5

6

7

8

16 NC

TOP VIEW

+

15 NC

+

LT1054CSW

LT1054ISW

LT1054CJ8

LT1054CN8

LT1054IN8

LT1054MJ8

FB/SHDN

1

2

3

4

V

8

7

6

5

FB/SHDN

14

13

12

11

10

9

V

+

CAP

OSC

+

CAP

OSC

GND

V

REF

GND

V

REF

–

CAP

V

OUT

–

CAP

OUT

NC

J8 PACKAGE

N8 PACKAGE

8-LEAD CERAMIC DIP 8-LEAD PLASTIC DIP

NC

T_JMAX= 150°C, θ_JA= 100°C/ W (J8)

T_JMAX= 125°C, θ_JA= 130°C/ W (N8)

SW PACKAGE

16-LEAD PLASTIC SO

T_JMAX= 125°C, θ_JA= 150°C/W

2

LT1054/LT1054L

(Note 7)

ELECTRICAL CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current

I

= 0mA LT1054:

V

= 3.5V

= 15V

●

2.5

3.0

4.0

5.0

mA

LOAD

IN

LT1054L:

V

= 3.5V

= 7V

●

2.5

3.0

4.0

5.0

mA

IN

Supply Voltage Range

LT1054

LT1054L

●

3.5

15

7

V

Voltage Loss (V

–

V

)

C

= C

= 100µF Tantalum (Note 4)

IN

OUT

IN

OUT

I

= 10mA

●

0.35

1.10

1.35

0.55

1.60

1.75

V

OUT

= 100mA

= 125mA (LT1054L)

Output Resistance

∆I

OUT

= 10mA to 100mA (Note 5)

●

10

15

Ω

Oscillator Frequency

LT1054: 3.5V ≤ V ≤ 15V

●

15

25

35

kHz

IN

LT1054L: 3.5V ≤ V ≤ 7V

IN

Reference Voltage

I

= 60µA, T = 25°C

2.35

2.25

2.50

2.65

2.75

V

REF

J

●

Regulated Voltage

Line Regulation

Load Regulation

V

= 7V, T = 25°C, R = 500Ω (Note 6)

–4.70

–5.00

5

–5.20

25

V

mV

mA

µA

IN

J

L

LT1054: 7V ≤ V ≤ 12V, R = 500Ω (Note 6)

●

IN

L

V

= 7V, 100Ω ≤ R ≤ 500Ω (Note 6)

10

50

IN

L

Maximum Switch Current

300

100

Supply Current in Shutdown

V

= 0V

●

200

PIN1

The

●

denotes specifications which apply over the full operating

Note 5: Output resistance is defined as the slope of the curve, (∆V

∆I ), for output currents of 10mA to 100mA. This represents the linear

OUT

vs

OUT

temperature range.

portion of the curve. The incremental slope of the curve will be higher at

currents <10mA due to the characteristics of the switch transistors.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 6: All regulation specifications are for a device connected as a

positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k,

Note 2: The absolute maximum supply voltage rating of 16V is for

unregulated circuits using LT1054. For regulation mode circuits using

C1 = 0.002µF, (C1 = 0.05µF S package) C = 10µF tantalum,

IN

LT1054 with V

≤ 15V at Pin 5 (Pin 11 on S package), this rating may

OUT

C

= 100µF tantalum.

OUT

be increased to 20V. The absolute maximum supply voltage for LT1054L

is 7V.

Note 7: The S8 package uses a different die than the H, J8, N8 and S

packages. The S8 device will meet all the existing data sheet parameters.

See Regulation and Capacitor Selection in the Applications Information

section for differences in application requirements.

Note 3: The devices are guaranteed by design to be functional up to the

absolute maximum junction temperature.

Note 4: For voltage loss tests, the device is connected as a voltage

inverter, with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected.

The voltage losses may be higher in other configurations.

3

LT1054/LT1054L

TYPICAL PERFOR A CE CHARACTERISTICS

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Shutdown Threshold

Supply Current

Oscillator Frequency

35

25

15

5

4

3

2

0.6

0.5

0.4

0.3

I

L

= 0

V

PIN1

V

IN

= 15V

V

IN

= 3.5V

0.2

0.1

0

1

0

50

TEMPERATURE (˚C)

100 125

0

10

5

INPUT VOLTAGE (V)

15

–70 –50

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–25

0

25

75

LT1054 • TPC02

LT1054 • TPC03

LT1054 • TPC01

Supply Current in Shutdown

Average Input Current

Output Voltage Loss

120

100

80

60

40

20

0

140

120

1.4

1.2

I

= 100mA

OUT

V

= 0V

PIN1

100

1.0

80

60

40

20

0.8

0.6

0.4

0.2

I

= 50mA

= 10mA

OUT

INVERTER CONFIGURATION

C

= 100µF TANTALUM

= 25kHz

OUT

OSC

f

0

10

5

INPUT VOLTAGE (V)

15

0

60

OUTPUT CURRENT (mA)

100

0

30

20

40

80

10 20

40

50 60 70 80 90 100

INPUT CAPACITANCE (µF)

LT1054 • TPC04

LT1050 • TPC05

LT1054 • TPC06

Output Voltage Loss

INVERTER CONFIGURATION

C

= 10µF TANTALUM

C

= 100µF TANTALUM

IN

OUT

IN

OUT

= 100µF TANTALUM

2

1

0

2

1

0

I

= 100mA

OUT

I

= 100mA

= 50mA

OUT

I

= 50mA

= 10mA

OUT

I

OUT

= 10mA

1

10

100

1

10

100

OSCILLATOR FREQUENCY (kHz)

LT1054 • TPC07

LT1054 • TPC08

4

LT1054/LT1054L

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TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage Temperature

Coefficient

Regulated Output Voltage

–4.7

–4.8

100

V

AT 0 = 2.500V

REF

80

60

–4.9

–5.0

40

–5.1

20

–11.6

–11.8

–12.0

–12.2

–12.4

–12.6

0

–20

–40

–60

–80

–100

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

LT1054 • TPC09

LT1054 • TPC10

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PIN FUNCTIONS

Pin 1 is also the inverting input of the LT1054’s error

amplifier and as such can be used to obtain a regulated

output voltage.

FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has

two functions. Pulling Pin 1 below the shutdown threshold

(≈0.45V) puts the device into shutdown. In shutdown the

reference/regulator is turned off and switching stops. The

switches are set such that both C_INand C_OUTare dis-

charged through the output load. Quiescent current in

shutdown drops to approximately 100µA (see Typical

PerformanceCharacteristics).Anyopen-collectorgatecan

be used to put the LT1054 into shutdown. For normal

(unregulated) operation the device will start back up when

the external gate is shut off. In LT1054 circuits that use the

regulation feature, the external resistor divider can provide

enough pull-down to keep the device in shutdown until the

output capacitor (C_OUT) has fully discharged. For most

applicationswheretheLT1054wouldberunintermittently,

thisdoesnotpresentaproblembecausethedischargetime

of the output capacitor will be short compared to the off-

time of the device. In applications where the device has to

start up before the output capacitor (C_OUT) has fully dis-

charged, a restart pulse must be applied to Pin 1 of the

LT1054. Using the circuit of Figure 5, the restart signal can

beeitherapulse(t_p>100µs)oralogichigh.Diodecoupling

the restart signal into Pin 1 will allow the output voltage to

come up and regulate without overshoot. The resistor

divider R3/R4 in Figure 5 should be chosen to provide a

signal level at pin 1 of 0.7V to 1.1V.

CAP⁺/CAP^–(Pin 2/Pin 4): Pin 2, the positive side of the

input capacitor (C_IN), is alternately driven between V⁺and

ground. WhendriventoV⁺, Pin2sourcescurrent from V⁺.

When driven to ground Pin 2 sinks current to ground. Pin

4, the negative side of the input capacitor, is driven alter-

nately between ground the V_OUT. When driven to ground,

Pin 4 sinks current to ground. When driven to V_OUTPin 4

sources current from C_OUT. In all cases current flow in the

switches is unidirectional as should be expected using

bipolar switches.

V_OUT(Pin 5): In addition to being the output pin this pin is

also tied to the substrate of the device. Special care must

be taken in LT1054 circuits to avoid pulling this pin

positive with respect to any of the other pins. Pulling Pin

5 positive with respect to Pin 3 (GND) will forward bias the

substratediodewhichwillpreventthedevicefromstarting.

Thisconditioncanoccurwhentheoutputloaddrivenbythe

LT1054 is referred to its positive supply (or to some other

positivevoltage).Notethatmostopampspresentjustsuch

a load since their supply currents flow from their V⁺

terminals to their V^–terminals. To prevent start-up prob-

lems with this type of load an external transistor must be

added as shown in Figure 1. This will prevent V_OUT(Pin 5)

5

LT1054/LT1054L

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PIN FUNCTIONS

from being pulled above the ground pin (Pin 3) during OSC (Pin 7): Oscillator Pin. This pin can be used to raise or

start-up. Any small, general purpose transistor such as lower the oscillator frequency or to synchronize the device

2N2222 or 2N2219 can be used. R_Xshould be chosen to to an external clock. Internally Pin 7 is connected to the

provide enough base drive to the external transistor so that oscillatortimingcapacitor(C_t≈150pF)whichisalternately

it is saturated under nominal output voltage and maximum chargedanddischargedbycurrentsourcesof±7µAsothat

output current conditions. In some cases an N-channel the duty cycle is ≈50%. The LT1054 oscillator is designed

enhancement mode MOSFET can be used in place of the to run in the frequency band where switching losses are

transistor.

minimized. However the frequency can be raised, lowered,

or synchronized to an external system clock if necessary.

(

|

V

I

|

)β

OUT

The frequency can be lowered by adding an external

capacitor (C1, Figure 2) from Pin 7 to ground. This will

increase the charge and discharge times which lowers the

oscillator frequency. The frequency can be increased by

adding an external capacitor (C2, Figure 2, in the range of

5pF to 20pF) from Pin 2 to Pin 7. This capacitor will couple

charge into C_Tat the switch transitions, which will shorten

the charge and discharge time, raising the oscillator fre-

quency. Synchronization can be accomplished by adding

an external resistive pull-up from Pin 7 to the reference pin

(Pin 6). A 20k pull-up is recommended. An open collector

gate or an NPN transistor can then be used to drive the

oscillator pin at the external clock frequency as shown in

Figure 2. Pulling up Pin 7 to an external voltage is

not recommended. For circuits that require both fre-

quency synchronization and regulation, an external refer-

ence can be used as the reference point for the top of the

R1/R2 divider allowing Pin 6 to be used as a pull-up point

for Pin 7.

R ≤

X

OUT

+

V

I

Q

L

+

–

LOAD

I

OUT

+

FB/SHDN

V

+

CAP

OSC

+

R

LT1054

X

C

IN

GND

V

REF

–

CAP

V

OUT

LT1054 • F01

C

OUT

+

Figure 1

V_REF(Pin 6): Reference Output. This pin provides a 2.5V

reference point for use in LT1054-based regulator circuits.

The temperature coefficient of the reference voltage has

been adjusted so that the temperature coefficient of the

regulated output voltage is close to zero. This requires the

reference output to have a positive temperature coefficient

as can be seen in the typical performance curves. This

nonzero drift is necessary to offset a drift term inherent in

the internal reference divider and comparator network tied

to the feedback pin. The overall result of these drift terms

is a regulated output which has a slight positive tempera-

ture coefficient at output voltages below 5V and a slight

negative TC at output voltages above 5V. Reference output

currentshouldbelimited, forregulatorfeedbacknetworks,

to approximately 60µA. The reference pin will draw

+

V

FB/SHDN

V

C2

C1

IN

+

CAP

OSC

+

LT1054

GND

C

V

REF

IN

–

CAP

V

OUT

LT1054 • F02

C

OUT

+

Figure 2

≈100µA when shorted to ground and will not affect the V⁺(Pin 8): Input Supply. The LT1054 alternately charges

internal reference/regulator, so that this pin can also be C_INtotheinputvoltagewhenC_INisswitchedinparallelwith

used as a pull-up for LT1054 circuits that require synchro- the input supply and then transfers charge to C_OUTwhen

nization.

C_INis switched in parallel with C_OUT. Switching occurs at

6

LT1054/LT1054L

U

PIN FUNCTIONS

drawn from the supply. A minimum input supply bypass

capacitor of 2µF, preferably tantalum or some other low

ESR type is recommended. A larger capacitor may be

desirableinsomecases,forexample,whentheactualinput

supply is connected to the LT1054 through long leads, or

when the pulse current drawn by the LT1054 might affect

other circuitry through supply coupling.

the oscillator frequency. During the time that C_INis charg-

ing, the peak supply current will be approximately equal to

2.2 times the output current. During the time that C_INis

delivering charge to C_OUTthe supply current drops to

approximately 0.2 times the output current. An input

supply bypass capacitor will supply part of the peak input

current drawn by the LT1054 and average out the current

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APPLICATIONS INFORMATION

V1

V2

Theory of Operation

f

R

L

To understand the theory of operation of the LT1054, a

review of a basic switched-capacitor building block is

helpful.

C1

C2

LT1054 • F03

Figure 3. Switched-Capacitor Building Block

In Figure 3 when the switch is in the left position, capacitor

C1 will charge to voltage V1. The total charge on C1 will be

q1=C1V1. Theswitchthenmovestotheright, discharging

C1tovoltageV2. AfterthisdischargetimethechargeonC1

is q2 = C1V2. Note that charge has been transferred from

the source V1 to the output V2. The amount of charge

transferred is:

R

EQUIV

V1

V2

1

fC1

R

L

C2

R

=

EQUIV

LT1054 • F04

Figure 4. Switched-Capacitor Equivalent Circuit

∆q = q1 – q2 = C1(V1 – V2)

ally be dominated by the 1/fC1 term and voltage losses will

rise.

If the switch is cycled f times per second, the charge

transfer per unit time (i.e., current) is:

Note that losses also rise as frequency increases. This is

caused by internal switching losses which occur due to

some finite charge being lost on each switching cycle. This

charge loss per-unit-cycle, when multiplied by the switch-

ing frequency, becomes a current loss. At high frequency

thislossbecomessignificantandvoltagelossesagainrise.

I = (f)(∆q) = (f)[C1(V1 – V2)]

Toobtainanequivalentresistancefortheswitched-capaci-

tornetworkwecanrewritethisequationintermsofvoltage

and impedance equivalence:

V1 – V2 V1 – V2

The oscillator of the LT1054 is designed to run in the

frequency band where voltage losses are at a minimum.

I =

=

(1/fC1)

R

EQUIV

A new variable R_EQUIVis defined such that R_EQUIV= 1/fC1.

Thus the equivalent circuit for the switched-capacitor

network is as shown in Figure 4. The LT1054 has the same

switching action as the basic switched-capacitor building

block. Eventhoughthissimplificationdoesn’tincludefinite

switch on-resistance and output voltage ripple, it provides

an intuitive feel for how the device works.

Regulation

The error amplifier of the LT1054 servos the drive to the

PNPswitch to controlthevoltageacrosstheinput capaci-

tor (C_IN) which in turn will determine the output voltage.

Using the reference and error amplifier of the LT1054, an

external resistive divider is all that is needed to set the

regulated output voltage. Figure 5 shows the basic regu-

lator configuration and the formula for calculating the

appropriate resistor values. R1 should be chosen to be

These simplified circuits explain voltage loss as a function

offrequency(seeTypicalPerformanceCharacteristics).As

frequency is decreased, the output impedance will eventu-

7

LT1054/LT1054L

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APPLICATIONS INFORMATION

voltage. For the basic configuration, |V_OUT| referred to the

ground pin of the LT1054 must be less than the total of the

supply voltage minus the voltage loss due to the switches.

The voltage loss versus output current due to the switches

canbefoundinTypicalPerformanceCharacteristics.Other

configurations such as the negative doubler can provide

higher output voltages at reduced output currents (see

Typical Applications).

R3

2.2µF

V

IN

+

FB/SHDN

V

+

CAP

OSC

C

10µF

TANTALUM

+

IN

R4

LT1054

GND

R1

R2

V

REF

–

CAP

V

OUT

C1

RESTART SHUTDOWN

V

OUT

|V

REF

2

|

|V

|

R2

R1

OUT

1.21V

=

+ 1 ≈

+ 1

C

OUT

100µF

TANTALUM

V

Capacitor Selection

– 40mV

)

+

WHERE V

= 2.5V NOMINAL

REF

ForunregulatedcircuitsthenominalvaluesofC_INandC_OUT

should be equal. For regulated circuits see the section on

Regulation. While the exact values of C_INand C_OUTare

noncritical, good quality, low ESR capacitors such as solid

tantalum are necessary to minimize voltage losses at high

currents. For C_INthe effect of the ESR of the capacitor will

bemultipliedbyfourduetothefactthatswitchcurrentsare

approximately two times higher than output current and

losses will occur on both the charge and discharge cycle.

This means that using a capacitor with 1Ω of ESR for C_IN

will have the same effect as increasing the output imped-

ance of the LT1054 by 4Ω. This represents a significant

increase in the voltage losses. For C_OUTthe affect of ESR is

less dramatic. C_OUTis alternately charged and discharged

at a current approximately equal to the output current and

the ESR of the capacitor will cause a step function to occur

in the output ripple at the switch transitions. This step

function will degrade the output regulation for changes in

output load current and should be avoided. Realizing that

large value tantalum capacitors can be expensive, a tech-

nique that can be used is to parallel a smaller tantalum

capacitor with a large aluminum electrolytic capacitor to

gain both low ESR and reasonable cost. Where physical

size is a concern some of the newer chip type surface

mount tantalum capacitors can be used. These capacitors

are normally rated at working voltages in the 10V to 20V

range and exhibit very low ESR (in the range of 0.1Ω).

LT1054 • F05

FOR EXAMPLE: TO GET V

PIN OF THE LT1054, CHOOSE R1 = 20k, THEN

= –5V REFERRED TO THE GROUND

OUT

|–5V|

R2 = 20k

+ 1 = 102.6k*

2.5V

)

– 40mV

2

*CHOOSE THE CLOSEST 1% VALUE

Figure 5

20k or greater because the reference output current is

limitedto≈100µA. R2shouldbechosentobeintherange

of100kto300k. ForoptimumresultstheratioofC_IN/C_OUT

is recommended to be 1/10. C1, required for good load

regulation at light load currents, should be 0.002µF for all

output voltages.

A new die layout was required to fit into the physical

dimensionsoftheS8package.Althoughthenewdieofthe

LT1054CS8 will meet all the specifications of the existing

LT1054 data sheet, subtle differences in the layout of the

new die require consideration in some application cir-

cuits. In regulating mode circuits using the 1054CS8 the

nominal values of the capacitors, C_INand C_OUT, must be

approximately equal for proper operation at elevated

junction temperatures. This is different from the earlier

part. Mismatches within normal production tolerances

for the capacitors are acceptable. Making the nominal

capacitor values equal will ensure proper operation at

elevated junction temperatures at the cost of a small

degradation in the transient response of regulator cir-

cuits. For unregulated circuits the values of C_INand C_OUT

are normally equal for all packages. For S8 applications

assistanceinunusualapplicationscircuits,pleaseconsult

the factory.

Output Ripple

The peak-to-peak output ripple is determined by the value

of the output capacitor and the output current. Peak-to-

peak output ripple may be approximated by the formula:

I

OUT

It can be seen from the circuit block diagram that the

maximum regulated output voltage is limited by the supply

dV =

2fC

OUT

8

LT1054/LT1054L

U

W U U

APPLICATIONS INFORMATION

wheredV=peak-to-peakrippleandf=oscillatorfrequency.

R_X= V_X/(4.4 I_OUT

where

)

For output capacitors with significant ESR a second term

must be added to account for the voltage step at the switch

transitions. This step is approximately equal to:

V_X≈ V_IN– [(LT1054 Voltage Loss)(1.3) + |V_OUT|]

and I_OUT= maximum required output current. The factor of

1.3 will allow some operating margin for the LT1054.

(2I_OUT)(ESR of C_OUT

)

Power Dissipation

For example: assume a 12V to –5V converter at 100mA

output current. First calculate the power dissipation with-

out an external resistor:

The power dissipation of any LT1054 circuit must be

limited such that the junction temperature of the device

does not exceed the maximum junction temperature rat-

ings. The total power dissipation must be calculated from

twocomponents,thepowerlossduetovoltagedropsinthe

switches and the power loss due to drive current losses.

ThetotalpowerdissipatedbytheLT1054canbecalculated

from:

P = (12V – |–5V|)(100mA) + (12V)(100mA)(0.2)

P = 700mW + 240mW = 940mW

At θ_JAof 130°C/W for a commercial plastic device this

would cause a junction temperature rise of 122°C so that

the device would exceed the maximum junction tempera-

ture at an ambient temperature of 25°C. Now calculate the

power dissipation with an external resistor (R_X). First find

how much voltage can be dropped across R_X. The maxi-

mum voltage loss of the LT1054 in the standard regulator

configuration at 100mA output current is 1.6V, so

P ≈ (V_IN– |V_OUT|)(I_OUT) + (V_IN)(I_OUT)(0.2)

wherebothV_INandV_OUTarereferredtothegroundpin(Pin

3) of the LT1054. For LT1054 regulator circuits, the power

dissipation will be equivalent to that of a linear regulator.

Due to the limited power handling capability of the LT1054

packages, the user willhavetolimitoutputcurrent require-

mentsortakestepstodissipatesomepowerexternaltothe

LT1054 for large input/output differentials. This can be

accomplished by placing a resistor in series with C_INas

shown in Figure 6. A portion of the input voltage will then

bedroppedacrossthisresistorwithoutaffectingtheoutput

regulation. Because switch current is approximately 2.2

times the output current and the resistor will cause a

voltage drop when C_INis both charging and discharging,

the resistor should be chosen as:

V_X= 12V – [(1.6V)(1.3) + |–5V|] = 4.9V and

R_X= 4.9V/(4.4)(100mA) = 11Ω

This resistor will reduce the power dissipated by the

LT1054 by (4.9V)(100mA) = 490mW. The total power

dissipated by the LT1054 would then be (940mW –

490mW) = 450mW. The junction temperature rise would

now be only 58°C. Although commercial devices are

guaranteed to be functional up to a junction temperature

of 125°C, the specifications are only guaranteed up to a

junction temperature of 100°C, so ideally you should limit

the junction temperature to 100°C. For the above example

thiswouldmeanlimitingtheambienttemperatureto42°C.

Otherstepscanbetakentoallowhigherambienttempera-

tures. The thermal resistance numbers for the LT1054

packages represent worst case numbers with no heat

sinking and still air. Small clip-on type heat sinks can be

used to lower the thermal resistance of the LT1054 pack-

age. In some systems there may be some available airflow

which will help to lower the thermal resistance. Wide PC

board traces from the LT1054 leads can also help to

remove heat from the device. This is especially true for

plastic packages.

V

IN

+

FB/SHDN

V

RX

+

CAP

OSC

+

LT1054

GND

R1

R2

C1

C

IN

V

REF

–

CAP

V

OUT

V

OUT

C

OUT

+

LT1054 • F06

Figure 6

9

LT1054/LT1054L

U

TYPICAL APPLICATIONS N

Basic Voltage Inverter

Basic Voltage Inverter/Regulator

+

2µF

V

FB/SHDN

V

IN

+

FB/SHDN

V

2µF

+

CAP

OSC

+

LT1054

GND

+

CAP

OSC

100µF

V

REF

+

LT1054

GND

R1

R2

10µF

V

REF

–

–V

OUT

100µF

CAP

V

OUT

–

+

CAP

V

OUT

0.002µF

LT1054 • TAO2

V

OUT

|

V

|

V

|

R2

R1

OUT

=

+ 1 =

+ 1 ,

100µF

V

1.21V

+

REF

2

)

– 40mV

LT1054 • TA03

REFER TO FIGURE 5

Negative Voltage Doubler

Positive Doubler

+

FB/SHDN

V

+

–

V

IN

3.5V TO 15V

V

OUT

1N4001

+

CAP

OSC

LT1054

GND

+

V

REF

V

OUT

IN

2µF

Q *

X

100µF

10µF

100µF

50mA

–

CAP

V

OUT

+

FB/SHDN

V

R *

X

100µF

2µF

+

CAP

LT1054

GND

OSC

+

V

IN

REF

V

= 3.5V TO 15V

IN

V

= –3.5V TO –15V

= 2V + (LT1054 VOLTAGE LOSS) + (Q SATURATION VOLTAGE)

IN

≈ 2V – (V + 2V )

–

OUT

IN

L

DIODE

CAP

V

OUT

IN

X

= LT1054 VOLTAGE LOSS

L

*SEE FIGURE 3

LT1054 • TAO4

LT1054 • TAO5

100mA Regulating Negative Doubler

V

IN

3.5 TO 15V

+

2.2µF

+

FB/SHDN

V

FB/SHDN V

HP5082-2810

PIN 2

LT1054 #1

+

CAP

OSC

CAP

OSC

V

OUT

+

LT1054 #1

GND

LT1054 #2

GND

20k

SET

10µF

V

REF

R1

40k

–

CAP

V

CAP

V

OUT

1N4002

10µF

+

0.002µF

+

R2

500k

1N4002

–V

OUT

I

100mA MAX

1N4002

V

= 3.5 TO 15V

100µF

IN

+

LT1054 • TAO6

MAX ≈ –2V + [1054 VOLTAGE LOSS + 2(V

)]

DIODE

OUT

IN

|

V

|

V

|

OUT

R2

R1

OUT

=

+ 1 =

+ 1

, REFER TO FIGURE 5

V

1.21V

REF

2

– 40mV

)

10

LT1054/LT1054L

U

TYPICAL APPLICATIONS N

Bipolar Supply Doubler

V

IN

3.5V TO 15V

+

–

+

10µF

100µF

+

+V

OUT

FB/SHDN

V

+

CAP

OSC

+

LT1054

GND

10µF

V

REF

100µF

–

CAP

V

OUT

+

10µF

–

+

100µF

V

+V

–V

= 3.5V TO 15V

IN

+

–V

OUT

≈ 2V – (V + 2V

)

OUT

IN

L

DIODE

≈ –2V + (V + 2V

)

OUT

IN

L

DIODE

V

= LT1054 VOLTAGE LOSS

L

LT1054 • TAO7

= 1N4001

5V to ±12V Converter

V

IN

= 5V

+

5µF

1N914

V

OUT

≈ 12V

OUT

+

I

= 25mA

FB/SHDN

V

+

100µF

10µF

TO PIN 4

LT1054 #1

+

FB/SHDN

V

CAP

OSC

+

LT1054 #1

GND

+

10µF

CAP

OSC

V

REF

10µF

LT1054 #2

20k

2N2219

1k

–

GND

V

REF

CAP

V

OUT

100µF

5µF

V

OUT

≈ –12V

= 25mA

–

OUT

+

CAP

V

OUT

I

100µF

+

LT1054 • TAO8

Strain Gauge Bridge Signal Conditioner

5V

10k

+

INPUT TTL

OR CMOS

LOW FOR ON

10µF

10k

ZERO

TRIM

40Ω

2N2907

5k

GAIN

TRIM

8

100k

5k

0.022µF

–

+

–

6

5

2

3

1M

301k

A1

A2

1

7

1/2 LT1013

+

10k

350Ω

4

200k

1µF

LT1054 • TAO9

+

FB/SHDN

V

5V

3k

+

A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE

BRIDGE OUTPUT OF 24mV

CAP

LT1054

GND

OSC

2N2222

+

10µF

V

100µF

TANTALUM

REF

–

CAP

V

OUT

11

LT1054/LT1054L

TYPICAL APPLICATIONS N

U

3.5V to 5V Regulator

V

IN

3.5V TO 5.5V

20k

1

2

3

4

8

7

6

5

1N914

+

LTC1044

1N914

+

1µF

FB/SHDN

V

+

5µF

+

CAP

OSC

R1

20k

R2

125k

+

LT1054

GND

10µF

V

REF

+

–

1µF

+

–

+

0.002µF

CAP

V

OUT

R2

125k

3k

V

OUT

= 5V

100µF

V

I

= 3.5V TO 5.5V

OUT

IN

= 5V

2N2219

= 50mA

OUT(MAX)

1N914

LT1054 • TA10

1N5817

Regulating 200mA, 12V to –5V Converter

5µF

12V

+

HP5082-2810

+

FB/SHDN

V

FB/SHDN

V

+

CAP

OSC

CAP

OSC

R1

39.2k

+

10Ω

1/2W

LT1054 #2

GND

LT1054 #1

GND

20k

10Ω

1/2W

10µF

V

REF

V

REF

10µF

+

R2

200k

–

0.002µF

CAP

V

OUT

CAP

V

OUT

LT1054 • TA11

200µF

|

V

|

V

|

R2

=

OUT

+

+ 1 =

+ 1 ,

R1

V

1.21V

REF

2

V

I

= –5V

= 0mA to 200mA

OUT

– 40mV

)

REFER TO FIGURE 5

Digitally Programmable Negative Supply

15V

+

11

5µF

20k

16

DIGITAL

INPUT

AD558

LT1004-2.5

2.5V

+

FB/SHDN

V

+

14

13

12

20k

CAP

OSC

+

LT1054

GND

10µF

V

REF

LT1054 • TA12

–

CAP

V

OUT

V

OUT

= –V (PROGRAMMED)

IN

100µF

+

12

LT1054/LT1054L

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

H Package

8-Lead TO-5 Metal Can (0.200 PCD)

(LTC DWG # 05-08-1320)

0.335 – 0.370

(8.509 – 9.398)

DIA

0.305 – 0.335

(7.747 – 8.509)

0.040

0.050

(1.016)

MAX

0.165 – 0.185

(1.270)

MAX

(4.191 – 4.699)

REFERENCE

PLANE

SEATING

PLANE

GAUGE

PLANE

0.500 – 0.750

(12.700 – 19.050)

0.010 – 0.045*

(0.254 – 1.143)

0.016 – 0.021**

(0.406 – 0.533)

0.027 – 0.045

(0.686 – 1.143)

45°TYP

PIN 1

0.028 – 0.034

(0.711 – 0.864)

0.200

(5.080)

TYP

0.110 – 0.160

*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE

AND 0.045" BELOW THE REFERENCE PLANE

0.016 – 0.024

**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS

(0.406 – 0.610)

(2.794 – 4.064)

INSULATING

STANDOFF

H8(TO-5) 0.200 PCD 1197

J8 Package

8-Lead CERDIP (Narrow 0.300, Hermetic)

(LTC DWG # 05-08-1110)

0.405

(10.287)

MAX

CORNER LEADS OPTION

(4 PLCS)

0.005

(0.127)

MIN

6

5

4

8

7

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

0.025

(0.635)

RAD TYP

0.220 – 0.310

(5.588 – 7.874)

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

1

2

3

0.200

(5.080)

MAX

0.300 BSC

(0.762 BSC)

0.015 – 0.060

(0.381 – 1.524)

0.008 – 0.018

(0.203 – 0.457)

0° – 15°

0.045 – 0.068

(1.143 – 1.727)

0.125

3.175

MIN

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE

OR TIN PLATE LEADS

0.100 ± 0.010

0.014 – 0.026

(2.540 ± 0.254)

(0.360 – 0.660)

J8 1197

13

LT1054/LT1054L

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.400*

(10.160)

MAX

8

7

6

5

4

0.255 ± 0.015*

(6.477 ± 0.381)

1

2

3

0.130 ± 0.005

0.300 – 0.325

0.045 – 0.065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

0.065

(1.651)

TYP

0.009 – 0.015

(0.229 – 0.381)

0.125

0.020

(0.508)

MIN

(3.175)

MIN

+0.035

0.325

–0.015

0.100 ± 0.010

(2.540 ± 0.254)

0.018 ± 0.003

(0.457 ± 0.076)

+0.889

8.255

(

)

N8 1197

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

7

5

8

6

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

1

0.053 – 0.069

(1.346 – 1.752)

3

4

2

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.016 – 0.050

0.406 – 1.270

0.050

(1.270)

TYP

0.014 – 0.019

(0.355 – 0.483)

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

SO8 0996

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

14

LT1054/LT1054L

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

SW Package

16-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

0.398 – 0.413*

(10.109 – 10.490)

15 14 12

10

11

9

16

13

0.394 – 0.419

(10.007 – 10.643)

NOTE 1

2

3

5

7

8

1

4

6

0.291 – 0.299**

(7.391 – 7.595)

0.037 – 0.045

(0.940 – 1.143)

0.093 – 0.104

(2.362 – 2.642)

0.010 – 0.029

(0.254 – 0.737)

× 45°

0° – 8° TYP

0.050

(1.270)

TYP

0.004 – 0.012

(0.102 – 0.305)

0.009 – 0.013

(0.229 – 0.330)

NOTE 1

0.014 – 0.019

(0.356 – 0.482)

TYP

0.016 – 0.050

(0.406 – 1.270)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

S16 (WIDE) 0396

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LT1054/LT1054L

U

TYPICAL APPLICATIONS N

Negative Doubler with Regulator

Positive Doubler with Regulation

V

IN

V

IN

= 5V

3.5V TO 15V

+

FB/SHDN

V

+

50k

2µF

+

1N5817

FB/SHDN

V

2µF

10µF

+

CAP

OSC

V

OUT

8V

+

LT1054

GND

CAP

OSC

10µF

V

REF

LT1054

GND

50mA

0.03µF

R1, 20k

1N5817

5.5k

V

REF

10k

–

+

CAP

V

OUT

R2

1M

100µF

–

0.002µF

+

CAP

V

OUT

5V

10k

1N4001

–

1N4001

10k

–V

OUT

LT1006

100µF

V

= 3.5V TO 15V

IN

+

2.5k

+

≈ –2V + (V + 2V )

OUT(MAX)

IN

L

DIODE

= LT1054 VOLTAGE LOSS

L

|

V

|

V

|

OUT

R2

R1

OUT

LT1054 • TA13

=

+ 1 =

+ 1

, REFER TO FIGURE 5

0.1µF

V

1.21V

REF

2

– 40mV

)

LT1054 • TA14

THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS

ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1144

Switched-Capacitor Voltage Converter

Wide Input Voltage Range, 2V to 18V

Regulated 5V Doublers

150mA Output

LTC1514/LTC1515

LT1611

Step-Up/Step-Down Switched Capacitor DC/DC Converters

Micropower Inverting DC/DC Converter

LT1614

Micropower Inverting DC/DC Converter

250mA Output

1054ld LT/TP 1298 2K REV D • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1987

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LT1054
厂家：	Linear
描述：	Switched-Capacitor Voltage Converter with Regulator 开关电容电压转换器与调节器转换器调节器开关
文件：	总16页 (文件大小：337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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