首页 |元器件品牌

LT1103_15 [Linear]

Offline Switching Regulator;
LT1103_15
型号： LT1103_15
厂家： Linear    Linear
描述：

Offline Switching Regulator
文件： 总32页 (文件大小：381K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
LT1103/LT1105  
Offline Switching Regulator  
OBSOLETE:  
Contact Linear Technology for Potential Replacement  
FOR INFORMATION PURPOSES ONLY  
U
DESCRIPTION  
FEATURES  
The LT®1103 Offline Switching Regulator is designed for  
high input voltage applications using an external FET  
switchwhosesourceisdrivenbytheopencollectoroutput  
of the LT1103. The LT1103 is optimized for 15W to 100W  
applications. For higher power applications or additional  
switch current flexibility, the LT1105 is available and its  
totem pole output drives the gate of an external FET.  
Unique design of the LT1103/LT1105 eliminates the need  
for an optocoupler while still providing ±1% load and line  
regulation in a magnetic flux-sensed converter. This sig-  
nificantly simplifies the design of offline power supplies  
andreducesthenumberofcomponentswhichmustcross  
the isolation barrier to one, the transformer.  
I
±1% Line and Load Regulation with No Optocoupler  
I
Switch Frequency Up to 200kHz  
I
Internal 2A Switch and Current Sense (LT1103)  
I
Internal 1A Totem-Pole Driver (LT1105)  
I
Start-Up Mode Draws Only 200µA  
I
Fully Protected Against Overloads  
I
Overvoltage Lockout of Main Supply  
I
Protected Against Underdrive or Overdrive to FET  
I
Operates in Continuous or Discontinuous Mode  
I
Ideal for Flyback and Forward Topologies  
I
Isolated Flyback Mode Has Fully Floating Outputs  
U
APPLICATIONS  
The LT1103/LT1105 current mode switching techniques  
arewellsuitedtotransformerisolatedflybackandforward  
topologies while providing ease of frequency compensa-  
tion with a minimum of external components. Low exter-  
nal part count for a typical application combines with a  
I
Up to 250W Isolated Mains Converter  
I
Up to 50W Isolated Telecom Converter  
I
Fully Isolated Multiple Outputs  
Distributed Power Conversion Networks  
I
, LTC and LT are registered trademarks of Linear Technology Corporation.  
U
TYPICAL APPLICATION  
Fully Isolated Flyback 100kHz 50W Converter with Load Regulation Compensation  
OPTIONAL OUTPUT FILTER  
MBR2045  
85V TO 270V  
AC  
10µH  
AC  
5V  
10A  
1.5KE300A  
5W  
!
!
T
+
+
R
L
E
O
50V  
470µF  
220k  
1W  
+
G
V
!
!
N
E
*50V  
3600µF  
A
G
A
D
G
+
MUR150  
220µF  
385V  
H
I
H
499Ω  
*OUTPUT CAPACITOR IS THREE 1200µF,  
50V CAPACITORS IN PARALLEL TO  
ACHIEVE REQUIRED RIPPLE CURRENT  
RATING AND LOW ESR.  
–
1N4148  
1000pF  
100Ω  
Load Regulation  
BRIDGE  
RECTIFIER  
+
LINE  
FILTER  
5.25  
5.20  
5.15  
5.10  
5.05  
5.00  
4.95  
4.90  
4.85  
4.80  
4.75  
BAV21  
WINDINGS FOR  
OPTIONAL  
±12V OUTPUTS  
BUK426-800A  
BAV21  
1N4148  
V
V
IN  
SW  
DC  
+
39µF  
35V  
LT1103  
13k  
1%  
10Ω  
TRANSFORMER DATA:  
COILTRONICS CTX110228-3  
= 1.6mH  
220V  
AC  
18.7k  
15V  
FB  
GND  
L
(PRI)  
+
V
C
OSC  
1µF  
25V  
N
N
:N  
= 1:0.05  
= 1:0.27  
PRI SEC  
4.75k  
1%  
85V  
AC  
:N  
110V  
AC  
BIAS SEC  
270V  
AC  
0.047µF  
390pF  
330Ω  
0.1µF  
0.047µF  
LT1103 TA13  
0
1
2
3
4
5
6
7
8
9
10  
I
(A)  
OUT  
LT1103 TA02  
Danger!! Lethal Voltages Present – See Text  
1
LT1103/LT1105  
U
U U  
DESCRIPTION  
WAR I G!  
200kHz maximum switching frequency to achieve high  
power density. Performance at switching frequencies  
above 100kHz may be degraded due to internal timing  
constraints associated with fully isolated flyback mode.  
DANGEROUS AND LETHAL POTENTIALS ARE  
PRESENT IN OFFLINE CIRCUITS!  
BEFORE PROCEEDING ANY FURTHER, THE  
READER IS WARNED THAT CAUTION MUST  
BE USED IN THE CONSTRUCTION, TESTING  
AND USE OF OFFLINE CIRCUITS. HIGH  
VOLTAGE,ACLINE-CONNECTEDPOTENTIALS  
AREPRESENTINTHESECIRCUITS. EXTREME  
CAUTION MUST BE USED IN WORKING WITH  
AND MAKING CONNECTIONS TO THESE  
CIRCUITS. REPEAT: OFFLINE CIRCUITS  
CONTAINDANGEROUS,ACLINE-CONNECTED  
HIGH VOLTAGE POTENTIALS. USE CAUTION.  
Included are the oscillator, control, and protection cir-  
cuitry such as current limit and overvoltage lockout.  
Switchfrequencyandmaximumdutycycleareadjustable.  
Bootstrap circuitry draws 200µA for start-up of isolated  
topologies. A 5V reference as well as a 15V gate bias are  
available to power external primary-side circuitry. No  
external current sense resistor is necessary with LT1103  
because it is integrated with the high current switch. The  
LT1105 brings out the input to the current limit amplifier  
and requires the use of an external sense resistor.  
ALL TESTING PERFORMED ON AN OFFLINE  
CIRCUIT MUST BE DONE WITH AN ISOLATION  
TRANSFORMER CONNECTED BETWEEN THE  
OFFLINE CIRCUIT'S INPUT AND THE AC LINE.  
USERS AND CONSTRUCTORS OF OFFLINE  
CIRCUITSMUSTOBSERVETHISPRECAUTION  
WHEN CONNECTING TEST EQUIPMENT TO  
THE CIRCUIT TO AVOID ELECTRIC SHOCK.  
REPEAT: AN ISOLATION TRANSFORMER  
MUSTBECONNECTEDBETWEENTHECIRCUIT  
INPUT AND THE AC LINE IF ANY TEST  
EQUIPMENT IS TO BE CONNECTED.  
The LT1103/LT1105 have unique features not found on  
other offline switching regulators. Adaptive antisat switch  
drive allows wide ranging load currents while maintaining  
high efficiency. The external FET is protected from insuf-  
ficient or excessive gate drive voltage with a drive detec-  
tion circuit. An externally activated shutdown mode  
reducestotalsupplycurrenttolessthan200µA, typicalfor  
standby operation. Fully isolated and regulated outputs  
can be generated in the optional isolated flyback mode  
without the need for optocouplers or other isolated feed-  
back paths.  
W W  
U W  
ABSOLUTE MAXIMUM RATINGS (Note 1)  
VIN .......................................................................... 30V  
VSW Output Voltage (LT1103)................................. 50V  
VSW Output Current (200ns)(LT1105) ................. ±1.5A  
VC, FB, OSC, SS ........................................................ 6V  
ILIM (LT1105) ........................................................... 3V  
0VLO Input Current ............................................... 1mA  
Lead Temperature (Soldering, 10 sec.)................ 300°C  
Maximum Operating Ambient Temperature Range  
LT1103C .............................................. 0°C to 70°C  
LT1105C .............................................. 0°C to 70°C  
Maximum Operating Junction Temperature Range  
LT1103C ............................................. 0°C to 100°C  
LT1105C ............................................ 0°C to 100°C  
LT1105I ......................................... –40°C to 125°C  
Storage Temperature Range ................. –65°C to 150°C  
2
LT1103/LT1105  
U
W U  
PACKAGE/ORDER INFORMATION  
TOP VIEW  
ORDER PART  
NUMBER  
ORDER PART  
NUMBER  
GND  
1
2
3
4
8
7
6
5
V
SW  
I
15V  
LIM  
TOP VIEW  
LT1105CN  
LT1105IN  
V
IN  
LT1105CN8  
LT1105IN8  
FB  
1
2
3
4
5
6
7
V
SW  
14  
13  
12  
11  
10  
9
PWRGND  
OVLO  
FB  
OSC  
V
C
NC  
N8 PACKAGE  
8-LEAD PDIP  
NC  
15V  
V
C
TJMAX = 100°C, θJA = 130°C/W  
V
5V  
SS  
IN  
FRONT VIEW  
OSC  
ORDER PART  
7
6
5
4
3
2
1
15V  
IN  
OSC  
GND  
I
8
GND  
LIM  
NUMBER  
V
N PACKAGE  
14-LEAD PDIP  
LT1103CT7  
V
C
PINS 1 AND 7 MUST BE TIED TOGETHER  
FB  
V
TJMAX = 100°C, θJA = 100°C/W  
SW  
T7 PACKAGE  
7-LEAD TO-220  
CASE IS CONNECTED TO GROUND. LEADS ARE FORMED  
TJMAX = 100°C, θJA = 50°C/W  
Consult factory for Military grade parts.  
ELECTRICAL CHARACTERISTICS  
VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, TA = 25°C, unless otherwise noted.  
SYMBOL PARAMETER CONDITIONS  
8V < V < 30V, After Device Has Started  
MIN  
TYP  
20  
MAX  
UNITS  
I
I
Supply Current  
●
10  
30  
mA  
Q
IN  
Start-Up Current  
V
< V Start Threshold  
●
●
200  
400  
450  
µA  
µA  
START  
IN  
IN  
Industrial Grade  
V
V
Start Threshold  
●
●
14.5  
5.0  
16.0  
7.0  
17.5  
8.0  
V
V
IN  
IN  
Shutdown Threshold  
Note: Switching Stops When V < 10V (LT1103)  
SW  
Note: Switching Stops When V  
< 10V (LT1105)  
GATE  
V
5V Reference Voltage  
●
●
●
4.80  
4.95  
0.025  
0.025  
60  
5.20  
0.1  
V
%/ V  
REF  
V
V
V
Line Regulation  
10V < V < 30V  
IN  
REF  
REF  
REF  
Load Regulation  
Short-Circuit Current  
0mA < I < 20mA  
0.05  
%/mA  
L
Commercial Grade  
Industrial Grade  
●
●
25  
20  
110  
120  
mA  
mA  
15V Short-Circuit Current  
Commercial Grade  
Industrial Grade  
●
●
30  
25  
130  
140  
mA  
mA  
V
15V Gate Bias Reference  
15V Dropout Voltage  
17 < V < 30V, 0mA < I < 30mA  
●
●
●
13.8  
15.0  
2.0  
70  
16.2  
2.5  
V
V
GATE  
IN  
L
V
= 15V, I = 30mA  
L
IN  
15V Short-Circuit Current  
Oscillator Scaling Factor  
30  
130  
mA  
SF  
FB = 4V, V = Open, Measured at V , I = 25mA,  
36  
32  
40  
40  
44  
48  
Hz • µF  
Hz • µF  
C
SW SW  
OVLO = 5V, f  
= SF/C  
40kHz < f < 200kHz  
●
OSC  
OSC,  
OSC  
Oscillator Valley Voltage  
Oscillator Peak Voltage  
2.0  
4.5  
V
V
3
LT1103/LT1105  
ELECTRICAL CHARACTERISTICS  
VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, TA = 25°C, unless otherwise noted.  
SYMBOL PARAMETER  
DC Preset Max Switch Duty Cycle  
CONDITONS  
FB = 4V, V = Open, f  
Note: Maximum Duty Cycle Can Be Altered at OSC Pin  
MIN  
TYP MAX  
UNIT  
= 40kHz, I = 25mA,  
●
58  
65  
72  
%
C
OSC  
SW  
(LT1103)  
Preset Max Switch Duty Cycle  
(LT1105)  
FB = 4V, V = Open, f = 40kHz, I = 25mA,  
Note: Maximum Duty Cycle Can Be Altered at OSC Pin  
Industrial Grade  
●
●
56  
55  
63  
70  
75  
%
%
C
OSC  
SW  
OVLO Threshold  
Overvoltage Lockout Threshold at Which Switching is Inhibited  
Industrial Grade  
●
●
2.3  
2.2  
2.5  
1.0  
2.7  
2.8  
V
V
OVLO Input Bias Current  
FB Threshold Voltage  
OVLO = 2V, Measured Out of Pin (Note 2)  
●
3.0  
µA  
V
I(V ) = 0mA  
C
4.425 4.50 4.575  
4.400 4.50 4.600  
V
V
FB  
●
FB Input Bias Current  
Change in FB Input  
FB = V (Note 3)  
Industrial Grade  
●
●
5
4
10  
20  
22  
µA  
µA  
FB  
FB = V , V = 1V to 4V (Note 3)  
8
7
6
11  
11  
13  
14  
15  
µA/V  
µA/V  
µA/V  
FB  
C
Bias Current with Change in V  
●
●
C
Industrial Grade  
10V < V < 30V  
FB Threshold Line Regulation  
Error Amp Transconductance  
●
0.025 0.10  
%/V  
IN  
gm  
∆I(V ) = ±50µA  
9000 12000 17500  
6000 12000 20000  
5000  
µmho  
µmho  
µmho  
C
●
●
Industrial Grade  
24000  
A
Error Amp Voltage Gain  
1V < V < 3V  
Industrial Grade  
●
●
500 1250  
450  
V/V  
V/V  
V
C
V Switching Threshold  
C
Switch Duty Cycle = 0%  
●
0.85 1.25  
1.4  
V
Shutdown Threshold Voltage  
●
●
50  
50  
150  
250  
300  
mV  
mV  
Industrial Grade  
Error Amp Source Current  
Error Amp Sink Current  
●
150  
275  
3
µA  
●
●
1.5  
0.7  
4.5  
4.5  
mA  
mA  
Industrial Grade  
Error Amp Clamp Voltage  
Soft-Start Charging Current  
Soft-Start Reset Current  
FB = 4.75V  
FB = 4.0V  
●
●
0.3  
4.2  
0.7  
4.4  
0.9  
4.6  
V
V
SS = 0V  
Industrial Grade  
●
●
25  
20  
40  
60  
75  
µA  
µA  
V
= 6V, SS = 0.3V  
●
1
2
mA  
IN  
Output Switch Leakage  
(LT1103)  
V
V
= 45V  
= 15V  
●
●
500  
200  
µA  
µA  
SW  
SW  
BV  
Switch Breakdown Voltage  
(LT1103)  
I
= 5mA  
●
50  
70  
V
SW  
V
Current Limit (LT1103)  
Duty Cycle = 25% (Note 4)  
●
●
2.0  
2.5  
0.4  
3.0  
A
SW  
Output Switch On Resistance  
(LT1103)  
0.75  
Ω
∆I  
I Increase During Switch On Time  
(LT1103)  
I
= 0.5A to 1.5A  
●
30  
50  
mA/A  
IN  
Q
SW  
∆I  
SW  
Switch Output High Level  
(LT1105)  
Switch Output High Level  
Industrial Grade  
I
I
I
I
= 200mA, V  
= 750mA, V  
= 200mA, V  
= 750mA, V  
= 15V  
= 15V  
= 15V  
= 15V  
●
●
●
●
13.00 13.5  
12.50 13.2  
12.75  
V
V
V
V
SW  
SW  
SW  
SW  
GATE  
GATE  
GATE  
GATE  
12.25  
4
LT1103/LT1105  
ELECTRICAL CHARACTERISTICS  
VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, TA = 25°C, unless otherwise noted.  
SYMBOL PARAMETER CONDITONS  
Switch Output Low Level  
MIN  
TYP MAX  
UNIT  
I
I
= 200mA  
= 750mA  
●
●
0.25 0.50  
0.75 1.50  
V
V
SW  
SW  
(LT1105)  
Rise Time (LT1105)  
Fall Time (LT1105)  
C = 1000pF  
50  
20  
ns  
ns  
L
C = 1000pF  
L
I
Threshold Voltage (LT1105)  
Duty Cycle = 25% (Note 5)  
●
●
300  
9.0  
375  
9.5  
450  
mV  
V
LIM  
Low Switch Drive Lockout  
Threshold  
Measured at V (LT1103)  
10.5  
SW  
Measured at 15V Gate Bias Reference (LT1105)  
High Switch Drive Lockout  
Threshold  
Measured at V (LT1103)  
Measured at 15V Gate Bias Reference (LT1105)  
●
17.0 18.5 20.0  
V
SW  
The  
●
denotes specifications which apply over the full operating  
Note 4: Current limit on V is constant for DC < 35% and decreases for  
SW  
temperature range.  
DC > 35% due to internal slope compensation circuity. The LT1103 switch  
current limit is given by I = 1.76 (1.536 – DC) above 35% duty cycle.  
Note 1: Absolute Maximum Ratings are those values beyond which the life  
of a device may be impaired.  
Note 2: The OVLO pin is clamped with a 5.5V Zener and can sink a  
maximum input current of 1mA.  
LIM  
Note 5: The current limit threshold voltage is constant for DC < 35% and  
decreases for DC > 35% due to internal slope compensation circuitry. The  
LT1105 switch current limit threshold voltage is given by V = 0.225  
LIM  
(1.7 – DC) above 35% duty cycle.  
Note 3: FB input bias current changes as a function of the V pin voltage.  
C
Rate of change of FB input bias current is 11µA/V of change on V . By  
C
including a resistor in series with the FB pin, load regulation can be set  
to zero.  
W
U
TYPICAL PERFORMANCE CHARACTERISTICS  
Start-Up Supply Current vs  
Input Voltage  
Quiescent Supply Current vs  
Input Voltage  
Supply Current vs Input Voltage  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
25  
20  
15  
10  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
25°C  
125°C  
25°C  
25°C  
125°C  
–55°C  
–55°C  
5
0
I
SHUT  
I
START  
0
0
20  
INPUT VOLTAGE (V)  
30 35  
5
10 15  
25  
40  
0
10  
15  
20  
25  
30  
5
0
3
6
9
12  
15  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
LT1103 G03  
LT1103 G01  
LT1103 G02  
5
LT1103/LT1105  
TYPICAL PERFORMANCE CHARACTERISTICS  
W
U
Quiescent Supply Current vs  
Temperature  
Shutdown Supply Current vs  
Input Voltage  
Shutdown Supply Current vs  
VC Voltage  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
30V  
125°C  
V
C
= 75mV  
25°C  
120  
8V  
V
C
= 0  
–55°C  
0
0
0
10  
15  
20  
25  
30  
35  
5
100  
140  
180  
160  
200  
0
20 40 60 80  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
INPUT VOLTAGE (V)  
V
(mV)  
TEMPERATURE (°C)  
C
LT1103 G05  
LT1103 G06  
LT1103 G04  
VIN Start-Up Threshold vs  
Temperature  
VIN Shutdown Threshold vs  
Temperature  
Output Switch Frequency vs  
Temperature  
17.5  
8.0  
7.7  
7.4  
45  
43  
C
= 1000pF  
OSC  
17.0  
16.5  
16.0  
41  
7.1  
6.8  
6.5  
39  
37  
35  
15.5  
15.0  
14.5  
–25  
0
25 50 75 100 125 150 175  
–25  
75  
–75 –50 –25  
0
50  
100 125 150  
75  
–75 –50  
–75 –50  
0
25  
125 150 175  
100  
25  
50  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G07  
LT1103 G09  
LT1103 G08  
Switch Oscillator Frequency vs  
Capacitance  
Overvoltage Lockout Threshold vs  
Temperature  
Preset Switch Maximum Duty  
Cycle vs Temperature  
1000  
100  
10  
75  
72  
69  
3.0  
2.8  
2.6  
C
= 1000pF  
OSC  
66  
63  
60  
2.4  
2.2  
2.0  
100  
1000  
10000  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
–75  
–25  
175  
150  
25 50 75 100 125  
–50  
0
CAPACITANCE (pF)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G11  
LT1103 G10  
LT1103 G12  
6
LT1103/LT1105  
W
U
TYPICAL PERFORMANCE CHARACTERISTICS  
Soft-Start Reset Current vs  
Temperature  
OVLO Input Bias Current vs  
Temperature  
Soft-Start Charging Current vs  
Temperature  
0
60  
50  
5
4
3
OVLO = 2V  
–0.5  
–1.0  
–1.5  
40  
30  
2
1
0
–2.0  
–2.5  
–3.0  
20  
10  
0
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G13  
LT1103 G14  
LT1103 G15  
5V Reference Voltage vs  
Temperature  
5V Load Regulation vs  
Temperature  
5V Line Regulation vs  
Temperature  
5.20  
5.15  
5.10  
5.05  
5.00  
4.95  
4.90  
4.85  
4.80  
0.05  
0.025  
0.020  
0.015  
0.04  
0.03  
0.02  
0.01  
0
0.010  
0.005  
0
100  
–25  
75  
100 125  
–75  
25 50  
175  
150  
–25 0 25 50 75  
125 150 175  
–50  
0
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G18  
LT1103 G16  
LT1103 G17  
15V Gate Bias Reference vs  
Temperature  
15V Gate Bias Dropout Voltage vs  
Temperature  
5V Reference Short-Circuit  
Current vs Temperature  
16.2  
15.8  
110  
100  
90  
2.5  
2.0  
1.5  
15.4  
15.0  
80  
70  
1.0  
0.5  
0
60  
14.6  
14.2  
13.8  
50  
40  
30  
–25  
–75 –50  
0
25 50 75 100 125 150 175  
100  
–25 0 25 50 75  
125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
TEMPERATURE (°C)  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G20  
LT1103 G19  
LT1103 G21  
7
LT1103/LT1105  
TYPICAL PERFORMANCE CHARACTERISTICS  
W
U
15V Gate Bias Short-Circuit  
Current vs Temperature  
Low Switch Drive Lockout  
Threshold vs Temperature  
High Switch Drive Lockout  
Threshold vs Temperature  
20.0  
19.5  
130  
110  
90  
10.5  
10.2  
9.9  
19.0  
18.5  
70  
50  
30  
9.6  
9.3  
9.0  
18.0  
17.5  
17.0  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G24  
LT1103 G22  
LT1103 G23  
Change in FB Input Bias Current  
with Change in VC vs Temperature  
(VC = 1V to 4V)  
Feedback Threshold vs  
Temperature  
FB Input Bias Current vs  
Temperature (VC = 1V)  
4.60  
4.56  
4.52  
20  
16  
12  
14  
13  
12  
11  
10  
9
4.48  
4.44  
4.40  
8
4
0
8
7
175  
150  
–25  
25 50 75 100 125  
–25  
25 50 75 100  
125 150  
175  
–75  
–50 –25  
0
25  
50  
75  
100  
125  
–75  
175  
–75 –50  
0
–50  
0
150  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G25  
LT1103 G26  
LT1103 G27  
Error Amplifier Transconductance  
vs Temperature  
Error Amplifier Transconductance  
and Phase vs Frequency  
Error Amplifier Voltage Gain vs  
Temperature  
25000  
20000  
15000  
10000  
5000  
0.020  
0.018  
200  
180  
2500  
2000  
1500  
1000  
500  
PHASE  
gm  
0.016  
160  
0.014  
0.012  
0.010  
0.008  
0.006  
0.004  
0.002  
0
140  
120  
100  
80  
60  
40  
gm  
20  
PHASE  
0
100  
–25  
25 50 75  
125 150 175  
0.1  
1
10  
100  
1000  
–75 –50  
0
100  
–25  
0
25 50 75  
125 150 175  
–75 –50  
FREQUENCY (kHz)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G29  
LT1103 G28  
LT1103 G30  
8
LT1103/LT1105  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Error Amplifier High Clamp  
Voltage vs Temperature  
(FB = 4V)  
Error Amplifier Source Current vs  
Temperature  
Error Amplifier Sink Current vs  
Temperature  
4.5  
4.0  
350  
325  
300  
275  
250  
225  
200  
175  
150  
4.5  
4.4  
4.3  
3.5  
3.0  
4.2  
4.1  
4.0  
2.5  
2.0  
1.5  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
100  
–25  
25 50 75  
125 150 175  
–75 –50  
0
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G32  
LT1103 G31  
LT1103 G33  
Error Amplifier Low Clamp  
Voltage vs Temperature  
(FB = 4.75V)  
VC Switching Threshold Voltage  
vs Temperature  
LT1103 Output Switch Leakage  
Current vs Temperature  
0.9  
0.8  
200  
160  
120  
1.5  
1.3  
1.1  
V
= 45V  
SW  
0.7  
0.6  
80  
40  
0
0.9  
0.7  
0.5  
V
= 15V  
SW  
0.5  
0.4  
0.3  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G34  
LT1103 G36  
LT1103 G35  
LT1103 Switch Saturation Voltage  
vs Temperature  
LT1103 VSW Current Limit vs  
Duty Cycle  
LT1103 VSW Current Limit vs  
Temperature  
1.2  
1.0  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
3.0  
2.9  
2.8  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2.0  
–55°C  
25°C  
DC = 25%  
125°C  
0.8  
0.6  
I
= 1.5A  
= 0.5A  
SW  
0.4  
0.2  
0
I
SW  
–25  
0
25 50 75 100 125 150 175  
60  
–75 –50  
0
20 30 40 50  
DUTY CYCLE (%)  
70 80  
10  
0
25  
50  
75  
100  
150  
125  
175  
–75 –50 –25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G38  
LT1103 G39  
LT1103 G40  
9
LT1103/LT1105  
TYPICAL PERFOR A CE CHARACTERISTICS  
U W  
LT1103 Driver Current vs  
Temperature  
LT1105 VSW Low Saturation  
Voltage vs Temperature  
LT1105 VSW High Saturation  
Voltage vs Temperature  
3.0  
2.5  
3.0  
2.5  
50  
40  
30  
I
= 750mA  
= 200mA  
SW  
2.0  
1.5  
2.0  
1.5  
I
SW  
20  
10  
0
I
= 750mA  
= 200mA  
SW  
1.0  
0.5  
0
1.0  
0.5  
0
I
SW  
–25  
–75 –50  
0
25 50 75 100 125 150 175  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
150  
–50  
0
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G43  
LT1103 G42  
LT1103 G41  
LT1105 Current Limit Threshold  
Voltage vs Temperature  
LT1105 VSW Rise Time vs  
Temperature  
LT1105 VSW Fall Time vs  
Temperature  
450  
425  
100  
80  
100  
80  
DC = 25°C  
400  
375  
C
= 4700pF  
= 1000pF  
LOAD  
60  
60  
C
= 4700pF  
LOAD  
40  
20  
0
40  
20  
0
C
LOAD  
350  
325  
300  
C
= 1000pF  
LOAD  
–25  
0
25 50 75 100 125 150 175  
–75 –50  
–75  
–25  
25 50 75 100 125  
175  
–75  
–25  
50 75 100 125  
175  
150  
–50  
0
150  
–50  
0
25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
LT1103 G46  
LT1103 G44  
LT1103 G45  
10  
LT1103/LT1105  
U
U
U
PIN FUNCTIONS  
LT1103  
V
SW: The Switch Output pin is the collector of the internal  
NPN power switch. This pin has a typical ON resistance of  
0.4Ωand a minimum breakdown voltage of 50V. This pin  
also ties to the FET gate drive detection circuit.  
FB: The Feedback pin is the inverting input to the sampling  
error amplifier. The noninverting input is tied to a 4.5V  
reference. The FB pin is used for output voltage sensing.  
The input bias current is a function of the control pin VC  
voltage and can be used for load regulation compensation  
by including a resistor in series with the FB pin. The  
sampling error amplifier has a typical gm of 0.012 mhos  
and the output of the sampling error amplifier has asym-  
metrical slew rate to reduce overshoot during start-up  
conditions or following the release of an output overload.  
LT1105  
All functions on the LT1105 are equivalent to the LT1103  
with the exception of the VSW pin and the ILIM pin and the  
availability of the OVLO, 5V, and SS functions.  
OVLO: The Overvoltage Lockout pin inhibits switching  
when the pin is pulled above its threshold voltage of 2.5V.  
OVLO is implemented with a resistor divider network from  
the rectified DC line and is used to protect the external FET  
from an overvoltage condition in the off state. This func-  
tion is only available on the 14-lead PDIP.  
VC: The VC control pin is used for frequency compensa-  
tion, current limiting and shutdown. It is the high imped-  
ance output of the sampling error amplifier and the input  
of the current limit comparator.  
GND: The Ground pin acts as both the negative sense  
point for the internal sampling error amplifier feedback  
signal and as the high current path for the 2A switch.  
Also, the case of the 7-lead TO-220 is connected to  
ground. Proper connections to ground for signal paths  
and high current paths must be made in order to insure  
good load regulation.  
5V: A 5V reference is available to power primary-side  
circuitry. The temperature coefficient is typically  
50ppm/°C and the output can source 25mA. This func-  
tion is only available on the 14-lead PDIP.  
SS: The Soft-Start pin is used to either program start-up  
time with a capacitor to ground or to set external current  
limit with a resistor divider. The SS pin has a 40µA pull-up  
current and is reset to 0V by a 1mA pull-down current  
during start-up and shutdown. This function is only avail-  
able on the 14-lead PDIP.  
OSC:TheOscillatorpinsetstheoperatingfrequencyofthe  
regulatorwithoneexternalcapacitortoground.Maximum  
duty cycle can also be adjusted by using an external  
resistor to alter the charge/discharge ratio.  
VSW: The Switch Output pin is the output of a 1A NPN  
totem-polestage.TheVSW pinturnstheexternalFETonby  
pulling its gate high. Break-Before-Make action of 200ns  
on each switch edge is built in to eliminate cross conduc-  
tion currents.  
VIN: The Input Supply pin is designed to operate with  
voltages of 12V to 30V. The supply current is typically  
200µA up to the start-up threshold of 16V. Normal oper-  
ating supply current is fairly flat at 18mA down to the  
shutdown threshold of 7V. Switching is inhibited for VIN  
less than 12V due to the gate drive detection circuit.  
ILIM: The ILIM pin is the input to the current limit amplifier  
and requires the use of a noninductive, power sense  
resistorfromILIM togroundtosetcurrentlimit.Thetypical  
current limit threshold voltage is 350mV. The typical input  
bias current is 100µA out of the pin.  
15V: A15Vreferenceisusedtobiasthegateofanexternal  
powerFET. Thevoltagetemperaturecoefficientistypically  
3mV/°C and the output can source 30mA. Typical dropout  
voltage is 1.5V for VIN less than 17V and 30mA of load  
current.  
11  
LT1103/LT1105  
W
BLOCK DIAGRA S  
LT1103  
V
SW  
OSC  
GATE  
BIAS  
DETECT  
15V  
GATE  
BIAS  
15V  
OSCILLATOR  
START-UP  
16V  
7V  
V
LOGIC  
COMP  
DRIVER  
IN  
SPIKE  
BLANK  
ANTISAT  
4.5V  
5V  
REF  
+
5V  
FB  
V
CURRENT  
LIMIT  
+
–
–
AMP  
0.15Ω  
A
= 10  
V
SAMPLING  
ERROR AMP  
g
= 0.012  
6V  
m
40µA  
0VLO  
SHUT  
DOWN  
RESET  
OVERVOLTAGE  
LOCKOUT  
2.5V  
0.15V  
LT1103 BD  
V
SS  
GND  
C
12  
LT1103/LT1105  
W
BLOCK DIAGRA S  
LT1105  
OSC  
GATE  
15V  
GATE  
BIAS  
BIAS  
15V  
DETECT  
OSCILLATOR  
START-UP  
DRIVER  
16V  
7V  
V
LOGIC  
COMP  
IN  
V
SW  
DRIVER  
SPIKE  
BLANK  
ANTISAT  
4.5V  
+
5V  
REF  
5V  
FB  
V
CURRENT  
LIMIT  
+
–
–
I
LIM  
AMP  
A
= 10  
V
SAMPLING  
ERROR AMP  
g
m
= 0.012  
6V  
40µA  
0VLO  
SHUT  
DOWN  
RESET  
OVERVOLTAGE  
LOCKOUT  
2.5V  
0.15V  
LT1105 BD  
V
C
SS  
GND  
13  
LT1103/LT1105  
U
OPERATIO  
LT1103  
turning on if the gate voltage is less than 10V or greater  
than 20V, the industry standards for power MOSFET  
operation.  
The LT1103 is a current mode switcher. Switch duty cycle  
is controlled by switch current rather than directly by the  
output voltage. Referring to the block diagram, the switch  
is turned on at the start of each oscillator cycle. It is turned  
off when switch current reaches a predetermined level.  
Control of output voltage is obtained by using the output  
ofavoltagesensingerroramplifiertosetcurrenttriplevel.  
This technique has several advantages. First, it has imme-  
diate response to input voltage variations, unlike ordinary  
switchers which have notoriously poor line transient  
response. Second, it reduces the 90° phase shift at mid  
frequencies in the transformer. This greatly simplifies  
closed-loop frequency compensation under widely vary-  
ing input voltage or output load conditions. Finally, it  
allows simple pulse-by-pulse current limiting to provide  
maximum switch protection under output overload or  
short-circuit conditions.  
The switch current is sensed internally and amplified to  
trip the comparator and turn off the switch according to  
the VC pin control voltage. A blanking circuit suppresses  
the output of the current limit comparator for 500ns at the  
beginning of each switch cycle. This prevents false trip-  
ping of the comparator due to current spikes caused by  
external parasitic capacitance and diode stored charge.  
The 4.5V Zener-based reference biases the positive input  
of the sampling error amplifier. The negative input (FB) is  
used for output voltage sensing. The sampling error  
amplifier allows the LT1103 to operate in fully isolated  
flyback mode by regulating from the flyback voltage of the  
bootstrap winding. The leakage inductance spike at the  
leading edge of the flyback waveform is ignored with a  
blanking circuit. The flyback waveform is directly propor-  
tional to the output voltage in a transformer-coupled  
flyback topology. Output voltages are fully floating up to  
the breakdown voltage of the transformer windings. Mul-  
tiple floating outputs are easily obtained with additional  
windings.  
A start-up loop with hysteresis allows the IC supply  
voltage to be bootstrapped from an extra primary side  
windingonthepowertransformer. From0Vto16VonVIN,  
the LT1103 is in a prestart mode and total input current is  
typically 200µA. Above 16V, up to 30V, the 6V regulator  
that biases the internal circuitry and the externally avail-  
able 15V regulator is turned on. The internal circuitry  
remains biased on until VIN drops below 7V and the part  
returnstotheprestartmode.Outputswitchingstopswhen  
the VSW drive is less than 10V corresponding to VIN of  
about 12V.  
The error signal developed at the comparator input is  
brought out externally. This VC pin has three functions  
including frequency compensation, current limit adjust-  
ment and total regulator shutdown. During normal opera-  
tion, this pin sits at a voltage between 1.2V (low output  
current) and 4.4V (high output current). The error ampli-  
fier is a current output (gm) type, so this voltage can be  
externally clamped for adjusting current limit. Switch duty  
cycle goes to zero if the VC pin is pulled to ground through  
a diode, placing the LT1103 in an idle mode. Pulling the VC  
pin below 0.15V causes total regulator shutdown and  
places the LT1103 in a prestart mode.  
The oscillator provides the basic clock for all internal  
timing. Frequency is adjustable to 200kHz with one exter-  
nal capacitor from OSC to ground. The oscillator turns on  
the output switch via the logic and driver circuitry. Adap-  
tive antisat circuitry detects the onset of saturation in the  
power switch and adjusts driver current instantaneously  
to limit switch saturation. This minimizes driver dissipa-  
tion and provides very rapid turn-off of the switch.  
LT1105  
The LT1103 is designed to drive the source of an external  
power FET in common gate configuration. The 15V regu-  
lator biases the gate to guarantee the FET is on when the  
switch is on. Special drive detection circuitry senses the  
gate bias voltage and prevents the output switch from  
The LT1105 is a current mode switcher. Switch duty cycle  
is controlled by switch current rather than directly by  
output voltage. Referring to the block diagram, the switch  
is turned on at the start of each oscillator cycle. It is turned  
off when switch current reaches a predetermined level.  
14  
LT1103/LT1105  
U
OPERATIO  
Control of output voltage is obtained by using the output  
ofavoltagesensingerroramplifiertosetcurrenttriplevel.  
This technique has several advantages. First, it has imme-  
diate response to input voltage variations, unlike ordinary  
switchers which have notoriously poor line transient re-  
sponse. Second, it reduces the 90° phase shift at  
midfrequencies in the transformer. This greatly simplifies  
closed-loop frequency compensation under widely vary-  
ing input voltage or output load conditions. Finally, it  
allows simple pulse-by-pulse current limiting to provide  
maximum switch protection under output overload or  
short-circuit conditions.  
suppresses the output of the current limit comparator for  
500ns at the beginning of each switch cycle. This prevents  
false tripping of the comparator due to current spikes  
caused by external parasitic capacitance and diode stored  
charge.  
A 4.5V Zener-based reference biases the positive input of  
the sampling error amplifier. The negative input (FB) is  
used for output voltage sensing. The sampling error  
amplifier allows the LT1105 to operate in fully isolated  
flyback mode by regulating the flyback voltage of the  
bootstrap winding. The leakage inductance spike at the  
leading edge of the flyback waveform is ignored with a  
blanking circuit. The flyback waveform is directly propor-  
tional to the output voltage in the transformer coupled  
flyback topology. Output voltages are fully floating up to  
the breakdown voltage of the transformer windings. Mul-  
tiple floating outputs are easily obtained with additional  
windings.  
A start-up loop with hysteresis allows the IC supply  
voltage to be bootstrapped from an extra primary side  
windingonthepowertransformer. From0Vto16VonVIN,  
the LT1105 is in prestart mode and total input current is  
typically 200µA. Above 16V, up to 30V, the 6V regulator  
that biases the internal circuitry and the externally avail-  
able 5V and 15V regulators are turned on. The internal  
circuitry remains biased on until VIN drops below 7V and  
the part returns to prestart mode. Output switching stops  
when the 15V gate bias reference is less than 10V corre-  
sponding to VIN of about 12V.  
The error signal developed at the comparator input is  
brought out externally. The VC pin has three functions  
including frequency compensation, current limit adjust-  
ment and total regulator shutdown. During normal opera-  
tion, this pin sits at a voltage between 1.2V (low output  
current) and 4.4V (high output current). The error ampli-  
fier is a current output (gm) type, so this voltage can be  
externally clamped for adjusting current limit. Switch duty  
cycle goes to zero if the VC pin is pulled to ground through  
a diode, placing the LT1105 in an idle mode. Pulling the VC  
pin below 0.15V causes total regulator shutdown and  
places the LT1105 in prestart mode.  
The oscillator provides the basic clock for all internal  
timing. Frequency is adjustable to 200kHz with one exter-  
nal capacitor from OSC to ground. The oscillator turns on  
the output switch via the logic and driver circuitry.  
The LT1105 is designed to drive the gate of an external  
power FET in common source configuration. The drivers  
and the 1A maximum totem-pole output stage are biased  
from the 15V gate bias reference. Special drive detection  
circuity senses the gate bias reference voltage and pre-  
vents the output switch from turning on if this voltage is  
less than 10V or greater than 20V. Break-Before-Make  
action of 200ns is built into each switch edge to eliminate  
cross conduction currents.  
TheSSpinimplementssoft-startwithoneexternalcapaci-  
tor to ground. The internal pull-up current and clamp  
transistor limit the voltage at VC to one diode drop above  
thevoltageattheSSpin,therebycontrollingtherateofrise  
of switch current in the regulator. The SS pin is reset to 0V  
when the LT1105 is in prestart mode.  
Switch current is sensed externally through a precision,  
power resistor. This allows for greater flexibility in switch  
currentandoutputpowerthanallowedbytheLT1103. The  
voltageacrossthesenseresistorisfedintotheILIM pinand  
amplified to trip the comparator and turn off the switch  
according to the VC pin control voltage. A blanking circuit  
A final protection feature includes overvoltage lockout  
monitoring of the main supply voltage on the OVLO pin. If  
the OVLO pin is greater than 2.5V, the output switch is  
prevented from turning on. This function can be disabled  
by grounding the OVLO pin.  
15  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
start-up resistor is to insure that the maximum voltage  
rating of the resistor is not exceeded. Typical carbon film  
resistors have a voltage rating of 250V. The most reliable  
andeconomicalsolutionforthestart-upresistorisgenerally  
provided by placing several 0.25W resistors in series.  
Bootstrap Start  
It is inefficient as well as impractical to power a switching  
regulator control IC from the rectified DC input as this  
voltage is several hundred volts. Self-biased switching  
regulator topologies take advantage of a lower voltage  
auxiliary winding on the power transformer or inductor to  
power the regulator, but require a start-up cycle to begin  
regulation.  
The LT1103/LT1105 is designed to operate with supply  
pinvoltagesupto30V.However,theauxiliarybiaswinding  
should be designed for a typical output voltage of 17V to  
minimize IC power dissipation and efficiency loss.  
Allowances must also be made for cross regulation of the  
bias voltage due to variations in the rectified DC line  
voltage and output load current.  
Start-up circuitry with hysteresis built into the LT1103/  
LT1105 allows the input voltage to increase from 0V to  
16V before the regulator tries to start. During this time the  
start-up current of the switching regulator is typically  
200µA and all internal voltage regulators are off. The low  
quiescentcurrentallowstheinputvoltagetobetrickledup  
with only 500µA of current from the rectified DC line  
voltage, therebyminimizingpowerdissipationinthestart-  
up resistor. At 16V, the internal voltage regulators are  
turned on and switching begins. If enough power feeds  
back through the auxiliary winding to keep the input  
voltagetotheswitchingregulatorabove12V,thenswitching  
continues and a bootstrap start is accomplished. If the  
inputvoltagedropsbelow12V,thentheFETdrivedetection  
circuit locks out switching. The input voltage continues to  
fall as the VIN bypass capacitor is discharged by the  
normalquiescentcurrentoftheLT1103/LT1105. Oncethe  
inputvoltagefallsbelow7V,theinternalvoltageregulators  
are turned off and the switching regulator returns to the  
lowstart-upcurrentstate.Acontinuous“burpstart”mode  
indicates a fault condition or an incomplete power loop.  
Soft-Start  
Soft-start refers to the controlled increase of switch  
currentfromastart-uporshutdownstate.Thisallowsthe  
power supply to come up to voltage in a controlled  
mannerandchargetheoutputcapacitorwithoutactivating  
current limit. In general, soft-start is not required on the  
LT1105 due to the design of the sampling error amplifier  
gm stage which generates asymmetrical slew capability  
on the VC pin.  
This feature exhibits itself as a typical 3mA sink current  
capability on the VC pin whereas source current is only  
275µA. The low gm of the error amplifier allows small-  
valued compensation capacitors to be used on VC. This  
allowsthesinkcurrenttoslewthecompensationcapacitor  
quickly. Therefore, overshoot of the output voltage on  
start-up sequences and recovery from overload or short-  
circuit conditions is prevented. However, if a longer start-  
up period is required, the soft-start function can be used.  
The trickle current required to bootstrap the regulator  
inputvoltageistypicallygeneratedwitharesistorfromthe  
rectified DC input voltage. When combined with the  
regulator input bypass capacitor, the start-up resistor  
creates a ramp whose slope governs the turn-on time of  
theregulatoraswellastheperiodofthe“burpstart”mode.  
The design trade-offs are power dissipated in the trickle  
resistor, the turn-on time of the regulator, and the hold-up  
time of the regulator input bypass capacitor. The value of  
the start-up resistor is set by the minimum rectified DC  
input voltage to guarantee sufficient start-up current. The  
recommended minimum trickle current is 500µA. The  
powerratingofthestart-upresistorissetbythemaximum  
rectified DC input voltage. A final consideration for the  
Soft-start is implemented with an internal 40µA pull-up  
and a transistor clamp on the VC pin so that a single  
external capacitor from SS ground can define the linear  
ramp function. The voltage at VC is limited to one VBE  
abovethesoft-startpin(SS). Thetimetomaximumswitch  
current is defined as the capacitance on SS multiplied by  
the active range in volts of the VC pin divided by the pull-  
up current:  
C •(3.2V)  
T =  
40µA  
16  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
Ground (LT1103)  
SS is reset to 0V whenever VIN is less than 7V (prestart  
mode) or when shutdown is activated by pulling VC below  
0.15V. The SS pin has a guaranteed reset sink current of  
1mA when either the regulator supply voltage VIN falls  
below 7V or the regulator is placed in shutdown.  
The ground pin of the LT1103 is important because it acts  
as the negative sense point for the internal error amplifier  
feedback signal, the negative sense point for the current  
limit amplifier, and as the high current path for the 2A  
switch.Thetabofthe7-leadTO-220isinternallyconnected  
to GND (Pin 4).  
Shutdown  
The LT1103/LT1105 can be put in a low quiescent current  
shutdown mode by pulling VC below 150mV. In the  
shutdown mode the internal voltage regulators are turned  
off, SS is reset to 0V and the part draws less than 200µA.  
To initiate shutdown, about 400µA must be pulled out of  
VC until the internal voltage regulators turn off. Then, less  
than 50µA pull-down current is required to maintain  
shutdown. The shutdown function has about 60mV of  
hysteresis on the VC pin before the part returns to normal  
operation. Soft-start, if used, controls the recovery from  
shutdown.  
To avoid degradation of load regulation, the feedback  
resistor divider string and the reference side of the bias  
winding should be directly connected to the ground pin on  
the package. These ground connections should not be  
mixed with high currentcarryinggroundreturn paths. The  
length of the switch current ground path should be as  
short as possible to the input supply bypass capacitor and  
low resistance for best performance. The case of the  
LT1103 package is desirable to use as the high current  
groundreturnpathasthisisalowerresistiveandinductive  
path than that of the actual package pin and will help  
minimize voltage spikes associated with the high dI/dt  
switch current.  
5V Reference  
A5Vreferenceoutputisavailablefortheuser’sconvenience  
to power primary-side circuitry or to generate a clamp  
voltage for switch current limiting. The output will source  
25mA and the voltage temperature coefficient is typically  
50ppm/°C. If bypassing of the 5V reference is required, a  
0.1µF is recommended. Values of capacitance greater  
than 1µF may be susceptible to ringing due to decreased  
phase margin. In such cases, the capacitive load can be  
isolated from the reference output with a small series  
resistor at the expense of load regulation performance.  
Avoiding long wire runs to the ground pin minimizes load  
regulation effects and inductive voltages created by the  
highdI/dtswitchcurrent.Groundplanetechniquesshould  
also be used and will help keep EMI to a minimum.  
Grounding techniques are illustrated in the Typical  
Applications section.  
Ground (LT1105)  
ThegroundpinoftheLT1105isimportantbecauseitacts  
asthenegativesensepointfortheinternalerroramplifier  
feedback signal and as the negative sense point for the  
current limit amplifier. The LT1105 8-pin PDIP has Pin 1  
as its ground. The LT1105 14-pin PDIP has Pin 1 and  
Pin 7 as grounds and must be tied together for proper  
operation.  
Overvoltage Lockout  
The switching supply and primarily the external power  
MOSFET can be protected from an extreme surge of the  
input line voltage with the overvoltage lockout feature  
implementedontheOVLOpin.IfthevoltageonOVLOrises  
aboveitstypicalthresholdvoltageof2.5V,outputswitching  
is inhibited. This feature can be implemented with a  
resistive divider off of the rectified DC input voltage. This  
feature is only available on the LT1105 in the 14-lead PDIP  
and must be tied to ground if left unused.  
To avoid degradation of load regulation, the feedback  
resistordividershouldbedirectlyconnectedtothepackage  
ground pin. These ground connections should not be  
mixed with high currentcarryinggroundreturn paths. The  
length of the switch current ground path should be as  
short as possible to the input supply bypass capacitor and  
17  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
Note that the capacitor value must change to maintain the  
same frequency. For example, a 24k resistor from 5V to  
OSC and a 440pF capacitor from OSC to ground will yield  
100kHzwith50%maximumdutycycle. A56kresistorand  
a 280pF capacitor from OSC to ground will yield 100 kHz  
with 80% maximum duty cycle.  
lowresistanceforbestperformance.Thiswillhelpminimize  
voltagespikesassociatedwiththehighdI/dtswitchcurrent.  
Avoiding long wire runs to the ground pin minimizes load  
regulation effects and inductive voltages created by the  
highdI/dtswitchcurrent.Groundplanetechniquesshould  
also be used and will help keep EMI to a minimum.  
Grounding techniques are illustrated in the Typical  
Applications section.  
The oscillator can be synchronized to an external clock by  
coupling a sync pulse into the OSC pin. The width of this  
pulse should be a minimum of 500ns. The oscillator can  
onlybesynchronizedupinfrequencyandthesynchronizing  
frequency must be greater than the maximum possible  
unsynchronized frequency (for the chosen oscillator  
capacitor value). The amplitude of the sync pulse must be  
chosen so that the sum of the oscillator voltage amplitude  
plus the sync pulse amplitude does not exceed the 6V bias  
reference. Otherwise, theoscillatorpull-upcurrentsource  
will saturate and erroneous operation will result. If the  
LT1103/LT1105 is positioned on the primary side of the  
transformerandtheexternalclockontheisolatedsecondary  
output side, the sync signal must be coupled into the OSC  
pinusingapulsetransformer.Thepulsetransformermust  
meet all safety/isolation requirements as it also crosses  
the isolation boundary. An example of externally  
synchronizing the oscillator is shown in the Typical  
Applications section.  
Oscillator  
The oscillator of the LT1103/LT1105 is a linear ramp type  
powered from the internal 6V bias line. The charging  
currents and voltage thresholds are generated internally  
so that only one external capacitor is required to set the  
frequency. The 150µA pull-up current, which is on all the  
time, sets the preset maximum on-time of the switch and  
the 450µA pull-down current which is turned on and off,  
sets the dead time. The threshold voltages are typically 2V  
and 4.5V, so for a 400pF capacitor the ramp-up time of the  
voltage on the OSC pin is 6.67µs and the ramp-down time  
is 3.3µs, resulting in an operating frequency of 100kHz.  
Although the oscillator, as well as the rest of the switching  
regulator, will function at higher frequencies, 200kHz is  
the practical upper limit that will allow control range for  
lineandloadregulation. Thelowestoperatingfrequencyis  
limited by the sampling error amplifier to about 10kHz.  
Gate Biasing (LT1103)  
Thefrequencytemperaturecoefficientistypically–80ppm/  
°C with a good low T.C. capacitor. This means that with a  
low temperature coefficient capacitor, the temperature  
coefficient of the currents and the temperature coefficient  
of the thresholds sum to –80ppm/°C over the commercial  
temperature range. Bowing in the temperature coefficient  
of the currents affects the frequency about ±3% at the  
extremes of the military temperature range. The capacitor  
type chosen will have a direct effect on the frequency  
tempco.  
TheLT1103isdesignedtodriveanexternalpowerMOSFET  
in the common gate or cascode connection with the VSW  
pin.Theadvantageisthattheswitchcurrentcanbesensed  
internally, eliminating a low value, power sense resistor.  
The gate needs to be biased at a voltage high enough to  
guaranteethattheFETissaturatedwhentheopen-collector  
sourcedriveison. Thismeans10VasspecifiedinFETdata  
sheets, plus 1V for the typical switch saturation voltage,  
plus a couple of volts for temperature variations and  
processing tolerances. This leads to 15V for a practical  
gate bias voltage.  
Maximum duty cycle is set internally by the pull-up and  
pull-down currents, independent of frequency. It can be  
adjusted externally by modifying the fixed pull-up current  
with an additional resistor. In practice, one resistor from  
the OSC pin to the 5V reference or to ground does the job.  
PowerMOSFETsarewellsuitedtoswitchingpowersupplies  
becausetheirhighspeedswitchingcharacteristicspromote  
highswitchingefficiency.Toachievehighswitchingspeed,  
18  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
keep the switch just at the edge of saturation. Very low  
switch current results in nearly zero driver current and  
high switch currents automatically increase driver current  
as necessary. The ratio of switch current to driver current  
is approximately 30:1. This ratio is determined by the  
sizing of the extra emitter and the value of the current  
source feeding the driver circuitry. The quasisaturation  
state of the switch permits rapid turn-off without the need  
for reverse base emitter voltage drive.  
A special circuit in the LT1103 senses the voltage at VSW  
prior to turning on the switch. VSW is tied to the source of  
the FET and should represent the bias voltage on the gate  
when the switch is off. When the switch first turns off, the  
drain flies back until it is clamped by a snubber network.  
The source also flies high due to parasitic capacitive  
coupling on the FET and parasitic inductance of the leads.  
An extra diode from the source to the gate or VIN will  
provide insurance against fault conditions that might  
otherwise damage the FET. The diode clamps the source  
to one diode drop above the gate or VIN, thereby limiting  
the gate source reverse bias. Once the energy in the  
leakage inductance spike is dissipated and the primary is  
being regulated to its flyback voltage, the diode shuts off.  
The source is then floating and its voltage will be close to  
the gate voltage. If the sensed voltage on VSW is less than  
10V or greater than 20V, the circuit prevents the switch  
from turning on. This protects the FET from dissipating  
highpowerinanonsaturatedstateorfromexcessivegate-  
source voltage. The oscillator continues to run and the net  
effect is to skip switching cycles until the gate bias voltage  
is corrected. One consequence of the gate bias detection  
circuitisthatthestart-upwindowis 6Vifthegateisbiased  
from VIN and to 4V if the gate is biased from the 15V  
output. This influences the size of the bypass capacitor on  
VIN.  
Gate Biasing (LT1105)  
TheLT1105isdesignedtodriveanexternalpowerMOSFET  
in the common source configuration with the totem-pole  
output VSW pin. The advantage is added switch current  
flexibility (limited only by the choice of external power  
FET)andhigheroutputpowerapplicationsthanallowedby  
LT1103. An external, noninductive, power sense resistor  
must be used in series with the source of the FET to detect  
switch current and must be tied to the input of the current  
limit amplifier. The gate needs to be biased at a voltage  
high enough to guarantee that the FET is saturated when  
the totem-pole gate drive is on. This means 10V as  
specified in FET data sheets, plus the totem-pole high side  
saturation voltage plus a couple of volts for temperature  
variationsandprocessingtolerances.Thisleadsto15Vfor  
a practical gate bias voltage.  
PowerMOSFETsarewellsuitedtoswitchingpowersupplies  
becausetheirhighspeedswitchingcharacteristicspromote  
highswitchingefficiency.Toachievehighswitchingspeed,  
the gate capacitance must be charged and discharged  
quickly with high peak currents. In particular, the turn-off  
current can be as high as the peak switch current. The  
switching speed is controlled by the impedance seen by  
thegatecapacitance.Practicallyspeaking,zeroimpedance  
isnotdesirablebecauseofthehighfrequencynoisespikes  
introduced to the system. The gate bias supply which  
drives the totem-pole output stage should be bypassed  
with a 1µF low ESR capacitor to ground. This capacitor  
supplies the energy to charge the gate capacitance during  
gate drive turn-on. The power MOSFET should have a 5Ω  
resistor or larger in series with its gate from the VSW pin  
to define the source impedance.  
VSW Output (LT1103)  
The VSW pin of the LT1103 is the collector of an internal  
NPNpowerswitch. ThisNPNhasatypicalonresistanceof  
0.4Ωandatypicalbreakdownvoltage(BVCBO)of75V.Fast  
switching times and high efficiency are obtained by using  
aspecialdriverloopwhichautomaticallyadaptsbasedrive  
current to the minimum required to keep the switch in a  
quasisaturated state. The key element in the loop is an  
extra emitter on the output power transistor as seen in the  
block diagram. This emitter carries no current when the  
NPN output transistor collector is high (unsaturated). In  
this condition, the driver circuit can deliver very high base  
drive to the switch for fast turn-on. When the switch  
saturates, the extra emitter acts as a collector of an NPN  
operating in inverted mode and pulls base current away  
from the driver. This linear feedback loop serves itself to  
19  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
The LT1105 provides a 15V regulated output intended for  
driving the totem-pole output stage. It will source 30mA  
into a capacitive load with no stability problems. The  
output voltage temperature coefficient is 3mV/°C. If VIN  
dropsbelow17V,the15Voutputfollowsabout2.0Vbelow  
VIN until the part shuts down. If the 15V output is pulled  
above 17.5V, it will sink 5mA.  
the edge of saturation. This results in nearly zero driver  
current. The quasisaturation state of the low side switch  
permits rapid turn-on of the external FET when VSW pulls  
high.  
Fully Isolated Flyback Mode  
A unique sampling error amplifier included in the control  
loop of the LT1103/LT1105 eliminates the need for an  
optoisolator while providing ±1% line and load regulation  
in a magnetic flux-sensed flyback converter. In this mode,  
theflybackvoltageontheprimaryduring“switchoff”time  
is sensed and regulated. It is difficult to derive a feedback  
signal directly from the primary flyback voltage as this  
voltage is typically several hundred volts. A dedicated  
winding is not required because the bias winding for the  
regulator lends itself to flux-sensing. Flux-sensing made  
practicalsimplifiesthedesignofofflinepowersuppliesby  
minimizing the total number of external components and  
reduces the components which must cross the isolation  
barrier to one, the transformer. This inherently implies  
greater safety and reliability. The transformer must be  
optimized for coupling between the bias winding and the  
secondaryoutputwinding(s)whilemaintainingtherequired  
isolationandminimizingtheparasiticleakageinductances.  
A special circuit in the LT1105 senses the voltage at the  
15V regulated output prior to turning on the switch. The  
15V regulator drives the totem-pole output stage and the  
V
SW pin will pull the gate of the FET very close to the value  
of the 15V output when VSW turns on. Therefore, the 15V  
output represents what the gate bias voltage on the FET  
will be when the FET is turned on. If the sensed voltage on  
the 15V output is less than 10V or greater than 20V, the  
circuit prevents the switch from turning on. This protects  
the FET from dissipating high power in a nonsaturated  
stateorfromexcessivegate-sourcevoltage.Theoscillator  
continues to run and the net effect is to skip switching  
cycles until the gate bias voltage is corrected. One  
consequence of the gate bias detection circuit is that the  
start-up window is 4V. This influences the size of the  
bypass capacitor on VIN.  
VSW Output (LT1105)  
Althoughmagneticflux-sensinghasbeenusedinthepast,  
thetechniquehasexhibitedpooroutputvoltageregulation  
due to the parasitics present in a transformer coupled  
design.Transformerswhichprovidethesafetyandisolation  
as required by various international safety/regulatory  
agenciesalsoprovidethepoorestoutputvoltageregulation.  
Solutions to these parasitic elements have been achieved  
with the novel sampling error amplifier of the LT1103/  
LT1105. A brief review of flyback converter operation and  
the problems which create a poorly regulated output will  
provide insight on how the sampling error amplifier of the  
LT1103/LT1105addressestheregulationissueofmagnetic  
flux sensed converters.  
TheVSW pinoftheLT1105istheoutputofa1Atotem-pole  
driver stage. This output stage turns an external power  
MOSFET on by pulling its gate high. Break-Before-Make  
action of 200ns is built into each switch edge to eliminate  
cross-conduction currents. Fast switching times and high  
efficiency are obtained by using a low loss output stage  
and a special driver loop which automatically adapts base  
drive current to the totem-pole low side drive. The key  
element in the loop is an extra emitter on the output pull-  
down transistor as seen in the block diagram. This emitter  
carries no current when the low side transistor collector  
is high (unsaturated). In this condition, the driver can  
deliververyhighbasedrivetotheoutputtransistor forfast  
turn-off. When the low side transistor saturates, the extra  
emitter acts as a collector of an NPN operating in inverted  
mode and pulls base current away from the driver. This  
linear feedback loop serves itself to keep the switch just at  
The following figure shows a simplified diagram of a  
flyback converter using magnetic flux sensing. The major  
parasitic elements present in the transformer coupled  
designareindicated.Therelationshipsbetweentheprimary  
20  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
voltage, the secondary voltage, the bias voltage and the  
winding currents are indicated in the figures found on the  
following page for both continuous and discontinuous  
modes of operation.  
to zero or changing polarity. Therefore, the voltage on the  
bias winding is only valid as a representation of the output  
voltage while the secondary is delivering current.  
Although the bias winding flyback voltage is a representa-  
tion of the output voltage, its voltage is not constant. For  
a brief period following the leakage inductance spike, the  
biaswindingflybackvoltagedecreasesduetononlinearities  
and parasitics present in the transformer. Following this  
nonlinear behavior is a period where the bias winding  
flyback voltage decreases linearly. This behavior is easily  
explained. Current flow in the secondary decreases lin-  
early at a rate determined by the voltage across the  
secondary and the inductance of the secondary. The  
parasitic secondary leakage inductance appears as an  
impedance in series with the secondary winding. In addi-  
tion, parasitic resistances exist in the secondary winding,  
the output diode and the output capacitor. These imped-  
ances can be combined to form a lumped sum equivalent  
and which cause a voltage drop as secondary current  
flows. This voltage drop is coupled from the secondary to  
the bias winding flyback voltage and becomes more sig-  
nificant as the output is loaded more heavily. This voltage  
drop is largest at the beginning of “switch off” time and  
smallest just prior to either all transformer energy being  
depleted or the switch turning on again.  
Simplified Flyback Converter  
V
IN  
L(Ik  
)
PRI  
D1  
R
L(lk  
)
SEC  
1:N  
V
OUT  
C1  
COMMON  
S1  
N = TURNS RATIO FROM SECONDARY TO PRIMARY.  
N1 = TURNS RATIO FROM SECONDARY TO BIAS.  
N2 = N/N1  
V
BIAS  
L(lk ) = PRIMARY LEAKAGE INDUCTANCE.  
PRI  
L(lk ) = SECONDARY LEAKAGE INDUCTANCE.  
SEC  
R = PARASITIC WINDING, DIODE AND OUTPUT  
1:N1  
CAPACITOR RESISTANCE.  
LT1103 AI01  
When the switch “turns on,” the primary winding sees the  
input voltage and the secondary and bias windings go to  
negative voltages as a function of the turns ratio. Current  
builds in the primary winding as the transformer stores  
energy. When the switch “turns off,” the voltage across  
the switch flies back to a clamp level as defined by a  
snubber network until the energy in the leakage induc-  
tanceoftheprimarydissipates. Leakageinductanceisone  
of the main parasitic elements in a flux-sensed converter  
and is modeled as an inductor in series with the primary  
and secondary of the transformer. These parasitic induc-  
tances contribute to changes in the bias winding voltage  
and thus the output voltage with increasing load current.  
The best representation of the output voltage is just prior  
to either all transformer energy being used up and the bias  
winding voltage collapsing to zero or just prior to the  
switch turning on again and the bias winding going  
negative. This point in time also represents the smallest  
forward voltage for the output diode. It is possible to  
redefine the relationship between the secondary winding  
voltage and the bias winding voltage as:  
Theenergystoredinthetransformertransfersthroughthe  
secondary and bias windings during “switch off” time.  
Ideally, thevoltageacrossthebiaswindingissetbytheDC  
output voltage, the forward voltage of the output diode,  
and the turns ratio of the transformer after the energy in  
the leakage inductance spike of the primary is dissipated.  
V
+ Vf +I• R  
P
(
=
)
OUT  
V
BIAS  
N1  
where Vf is the forward voltage of the output diode, I is the  
current flowing in the secondary, RP is the lumped sum  
equivalent secondary parasitic impedance and N1 is the  
transformer turns ratio from the secondary to the bias  
winding. It is apparent that even though the above point in  
This relationship holds until the energy in the transformer  
dropstozero(discontinuousmode)ortheswitchturnson  
again (continuous mode). Either case results in the volt-  
age across the secondary and bias windings decreasing  
21  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
Flyback Waveform for Discontinuous Mode Operation  
Flyback Waveform for Continuous Mode Operation  
V
ZENER  
V
ZENER  
PRIMARY SWITCH VOLTAGE  
PRIMARY SWITCH VOLTAGE  
[V + Vf + (I • R )]/N  
[V  
+ Vf + (I • R )]/N  
SEC P  
OUT  
OUT  
SEC  
P
a
a
V
IN  
V
IN  
AREA “a” = AREA “b” TO MAINTAIN  
ZERO VOLTS ACROSS PRIMARY  
AREA “a” = AREA “b” TO MAINTAIN  
ZERO VOLTS ACROSS PRIMARY  
b
d
b
0V  
0V  
SECONDARY WINDING VOLTAGE  
SECONDARY WINDING VOLTAGE  
[V  
OUT  
+ Vf + (I  
• R )]  
SEC P  
[V  
OUT  
+ Vf + (I  
• R )]  
SEC P  
c
c
0V  
0V  
AREA “c” = AREA “d” TO MAINTAIN  
ZERO VOLTS ACROSS SECONDARY  
AREA “c” = AREA “d” TO MAINTAIN  
d
ZERO VOLTS ACROSS SECONDARY  
N • V  
N • V  
IN  
IN  
BIAS WINDING VOLTAGE  
[V + Vf + (I • R )]/N1  
BIAS WINDING VOLTAGE  
[V + Vf + (I • R )]/N1  
OUT  
SEC  
P
OUT  
SEC  
P
e
e
0V  
0V  
AREA “e” = AREA “f” TO MAINTAIN  
ZERO VOLTS ACROSS BIAS WINDING  
N2 • V  
IN  
AREA “e” = AREA “f” TO MAINTAIN  
ZERO VOLTS ACROSS BIAS WINDING  
f
f
N2 • V  
IN  
I
I
PRI  
PRI  
∆I  
∆I  
PRIMARY CURRENT  
PRIMARY CURRENT  
0A  
0A  
I
I
/N  
I
I
/N  
SEC = PRI  
SEC = PRI  
SECONDARY CURRENT  
SECONDARY CURRENT  
0A  
0A  
I
I
PRI  
PRI  
∆I  
∆I  
SWITCH CURRENT  
SWITCH CURRENT  
0A  
0A  
I
PRI  
I
PRI  
SNUBBER DIODE CURRENT  
SNUBBER DIODE CURRENT  
0A  
0A  
∆t = (I )[L(lk )]/V  
SNUB  
∆t = (I )[L(lk )]/V  
SNUB  
PRI  
PRI  
PRI  
PRI  
LT1103 WF01  
22  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
time is the most accurate representation of the output  
voltage, the answer given by the bias winding voltage is  
still off from the “true” answer by the amount I•RP/N1.  
follows the flyback waveform as it changes with time and  
amplifiesthedifferencebetweentheflybacksignalandthe  
internal 4.5V reference. Tracking is maintained until the  
point in time where the bias winding voltage collapses as  
a result of all transformer energy being depleted (discon-  
tinuous mode) or the switch turning on again (continuous  
mode). The level detector circuit senses the fact that the  
bias winding flyback voltage is no longer a representation  
of the output voltage and activates an internal peak detec-  
tor. This effectively saves the most accurate representa-  
tion of the output voltage which is then buffered to the  
second stage of the error amplifier.  
The sampling error amplifier of the LT1103/LT1105 pro-  
vides solutions to the errors associated with the bias  
winding flyback voltage. The error amplifier is comprised  
of a leakage inductance spike blanking circuit, a slew rate  
limited tracking amplifier, a level detector, a sample-and-  
hold, an output gm stage and load regulation compensa-  
tion circuitry. This all seems complicated at first glance,  
but its operation is straightforward and transparent to the  
user of the IC. When viewed from a system or block level,  
thesamplingerroramplifierbehaveslikeasimpletranscon-  
ductance amplifier. Here’s how it works.  
The second stage of the error amplifier consists of a  
sample-and-hold. When the switch turns on, the sample-  
and-hold samples the buffered error voltage for 1µs and  
then holds for the remainder of the switch cycle. This held  
voltage is then processed by the output gm stage and  
converted into a control signal at the output of the error  
amplifier, the VC pin.  
The sampling error amplifier takes advantage of the fact  
that the voltage across the bias winding during at least a  
portion of switch off time is proportional to the DC output  
voltage of the secondary winding. The feedback network  
used to sense the bias winding voltage is no longer  
comprised of a traditional peak detector in conjunction  
with a resistor divider network. The feedback network  
consists of a diode in series with the bias winding feeding  
the resistor divider network directly. The resultant error  
signal is then fed into the input of the error amplifier. The  
purpose of the diode in series with the bias winding is now  
not to peak detect, but to prevent the FB pin (input of the  
error amplifier) from being pulled negative and forward  
biasing the substrate of the IC when the bias winding  
changes polarity with “switch turn-on.”  
The final adjustment in regulation is provided by the load  
regulation compensation circuitry. As stated earlier, out-  
put regulation degrades with increasing load current (out-  
put power). The effect is traced to secondary leakage  
inductance and parasitic secondary winding, diode and  
output capacitor resistances. Even though the tracking  
amplifierhasobtainedthemostaccuraterepresentationof  
the output voltage, its answer is still flawed by the amount  
of the voltage drop across the secondary parasitic lumped  
sum equivalent impedance which is coupled to the bias  
winding voltage. This error increases with increasing load  
current. Therefore, a technique for sensing load current  
conditions has been added to the LT1103/LT1105. The  
switch current is proportional to the load current by the  
turnsratioofthetransformer.Asmallcurrentproportional  
to switch current is generated in the LT1103/LT1105 and  
fed back to the FB pin. This allows the input bias current of  
the sampling error amplifier to be a function of load  
current. A resistor in series with the FB pin generates a  
linear increase in the effective reference voltage with  
increasingloadcurrent. Thistranslatestoalinearincrease  
in output voltage with increasing load current. By adjust-  
ing the value of the series resistor, the slope of the load  
The primary winding leakage inductance spike effects are  
first eliminated with an internal blanking circuit in the  
LT1103/LT1105 which suppresses the input of the FB pin  
for1.5µsatthestartof“switchoff”time. Thispreventsthe  
primary leakage inductance spike from being propagated  
through the error amplifier and affecting the regulated  
output voltage.  
With the effects of the leakage inductance spike elimi-  
nated, the effects of decreasing bias winding flyback  
voltage can be addressed. With the traditional diode/  
capacitor peak detector circuitry eliminated from the feed-  
backnetwork,thetrackingamplifieroftheLT1103/LT1105  
23  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
compensation can be set to cancel the effects of these  
parasitic voltage drops. The feature can be ignored by  
eliminating the series resistor and lowering the equivalent  
divider impedance to swamp out the effects of the input  
bias current.  
drops back to 0° (actually 180° since FB is an inverting  
input) when the reactance of CC is small compared to RC.  
Thus, this RC series network forms a pole-zero pair. The  
pole is set by the high impedance output of the error  
amplifier and the value of CC on the VC pin. The zero is  
formed by the value of CC and the value of RC in series with  
CC ontheVC pin. TheRCseriesnetworkwillhavecapacitor  
values in the range of 0.1µF to 1.0µF and series resistor  
values in the range of 100Ω to 1000Ω.  
Frequency Compensation  
In order to prevent a regulator loop using the LT1103/  
LT1105 from oscillating, frequency compensation is  
required. AlthoughthearchitectureoftheLT1103/LT1105  
is simple enough to lend itself to a mathematical approach  
to frequency compensation, the added complication of  
input/or output filters, unknown capacitor ESR, and gross  
operatingpointchangeswithinputvoltageandloadcurrent  
variationsallsuggestamorepracticalempiricalapproach.  
Many hours spent on breadboards have shown that the  
simplest way to optimize the frequency compensation of  
theLT1103/LT1105istousetransientresponsetechniques  
and an “RC” box to quickly iterate toward the final  
compensation network. Additional information on this  
technique of frequency compensation can be found in  
Linear Technology’s Application Note 19.  
ItisnotedthattheRCnetworkontheVC pinformsthemain  
compensation network for the regulator loop. However, if  
the load regulation compensation feature is used as ex-  
plained in the section on fully-isolated flyback mode,  
additional frequency compensation components are re-  
quired.Theloadregulationcompensationfeatureinvolves  
the use of local positive feedback from the VC pin to the FB  
pin. Thus, it is possible to add enough load regulation  
compensation to make the loop oscillate. In order to  
prevent oscillation, it is necessary to roll off this local  
positive feedback at high frequencies. This is accom-  
plished by placing a capacitor in parallel with the compen-  
sation resistor which is in series with the FB pin. A value  
for this capacitor in the range of 0.01µF to 0.1µF is  
recommended. The time constant associated with this RC  
combination will be longer than that associated with the  
loop bandwidth. Thus, transient response will be affected  
in that settling time will be increased. However, this is  
typically not as important as controlling the absolute  
underorovershootamplitudeofthesysteminresponseto  
load current changes which could cause deleterious sys-  
tem operation.  
In general, frequency compensation is accomplished with  
anRCseriesnetworkontheVC pin. Theerroramplifierhas  
a gm (voltage “in” to current “out”) of ≈ 12000 µmhos.  
Voltage gain is determined by multiplying gm times the  
total equivalent error amplifier output loading, consisting  
of the error amplifier output impedance in parallel with the  
series RC external frequency compensation network. At  
DC, theexternalRCcanbeignored. Theoutputimpedance  
of the error amplifier is typically 100kΩ resulting in a  
voltage gain of ≈ 1200V/V. At frequencies just above DC,  
the voltage gain is determined by the external  
compensation, RC and CC. The gain at mid frequencies is  
given by:  
Switching Regulator Topologies  
Two basic switching regulator topologies are pertinent to  
the LT1103/LT1105, the flyback and forward converter.  
The flyback converter employs a transformer to convert  
onevoltagetoeitherahigherorloweroutputvoltage.VOUT  
in continuous mode is defined as:  
gm  
2π • f •CC  
AV =  
The gain at high frequencies is given by:  
AV = gm • RC  
DC  
(1– DC)  
V
= V •N •  
IN  
OUT  
Phase shift from the FB pin to the VC pin is 90° at mid  
frequencies where the external CC is controlling gain, then  
24  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
where N is the transformer turns ratio of secondary to  
primary and DC is the duty cycle. This formula can be  
rewritten in terms of duty cycle as:  
the end of “switch on” time. If maximum output power is  
needed, a reasonable starting value is found by assigning  
∆I a value of 20% of the peak switch current (2A for the  
LT1103 and set by the external FET rating used with the  
LT1105). With this design approach, LPRI is defined as:  
V
OUT  
DC =  
V
+ N • V  
IN  
(
)
OUT  
V
IN  
L
=
PRI  
V
It is important to define the full range of input voltage, the  
range of output loading conditions and the regulation  
requirementsforadesign.Dutycycleshouldbecalculated  
for both minimum and maximum input voltage.  
IN  
(∆I)(f) 1+  
V
PRI  
If maximum output power is not required, then ∆I can be  
increased which results in lower primary inductance and  
smallermagnetics.Maximumoutputpowerwithanisolated  
flyback converter is defined by the primary flyback voltage  
and the peak allowed switch current and is limited to:  
Inmanyapplications,Ncanvaryoverawiderangewithout  
degrading performance. If maximum output power is  
desired, N can be optimized:  
V
+ Vf  
OUT  
V
N
=
(
)
2
∆I  
2
PRI  
OPT  
(
)
P
=
V I –  
– Ip R E  
( )  
OUT(MAX)  
IN P  
V – V  
– V  
SNUB  
M
IN MAX  
(
)
(
)
V
+ V  
IN  
(
)
PRI  
where  
where  
Vf = Forward voltage of the output diode  
VM = Maximum switch voltage  
VSNUB = Snubber clamp level – primary flyback  
voltage.  
R = Total “switch” on resistance  
IP = Maximum switch current  
E = Overall efficiency ≈ 75%  
Peak primary current is used to determine core size for the  
transformer and is found from:  
In the isolated flyback mode, the LT1103/LT1105 sense  
and regulate the transformer primary voltage VPRI during  
“switch off” time. The secondary output voltage will be  
regulated if VPRI is regulated. VPRI is related to VOUT by:  
V
I
V
+ V  
(
)(  
)(  
)
+
∆I  
2
OUT OUT PRI IN  
I
=
PRI  
E V  
(
V
)(  
)
PRI IN  
V
+ Vf  
(
=
)
OUT  
V
A second consideration on primary inductance is the  
transition point from continuous mode to discontinuous  
mode. At light loads, the flyback pulse across the primary  
will drop to zero before the end of “switch off” time. The  
load current at which this starts to occur can be calculated  
from:  
PRI  
N
This allows duty cycle for an isolated flyback converter to  
be rewritten as:  
V
PRI  
+ V  
IN  
DC = Duty Cycle =  
V
(
)
PRI  
2
V
• V  
(
)
An important transformer parameter to be determined is  
the primary inductance LPRI. The value of this inductance  
is a trade-off between core size, regulation requirements,  
leakage inductance effects and magnetizing current ∆I.  
Magnetizing current is the difference between the primary  
current at the start of “switch on” time and the current at  
PRI IN  
2
I
=
OUT(TRANSITION)  
V
+ V  
2V  
f L  
)( )(  
(
) (  
)
PRI  
IN  
OUT  
PRI  
The forward converter as shown below is another  
transformer-based topology that converts one voltage to  
either a higher or a lower voltage.  
25  
LT1103/LT1105  
U
W U U  
APPLICATIONS INFORMATION  
V
OUT in continuous mode is defined as:  
VOUT = VIN • N • DC  
forward converter to define the switch voltage when S1 is  
off. This “reset” winding limits the maximum duty cycle  
allowed for the switch. This topology trades off reduced  
transformersizeforincreasedcomplexityandpartscount.  
A separate isolated feedback path is required for full  
isolation from input to output because voltages on the  
primary are no longer related to the DC output voltage  
during switch off time.  
ThesecondaryvoltagechargesupL1throughD1whenS1  
is on. When S1 is off, energy in L1 is transferred through  
free-wheeling diode D2 to C1. The extra transformer  
winding and diode D3 are needed in a single switch  
Simplified Forward Converter  
The isolated feedback path can take several forms. A  
second transformer in a modulator/demodulator scheme  
provides the isolation, but with significant complexity. An  
optoisolator can be substituted for the transformer with a  
savings in volume to be traded off with component  
variations and possible aging problems with the  
optoisolator transfer function. Finally, an extra winding  
closely coupled to the output inductor L1 can sense the  
flux in this element and give a representation of the output  
voltage when S1 is off.  
L1  
V
IN  
V
OUT  
1:N  
D1  
C1  
COMMON  
D2  
D3  
S1  
LT1103 AI02  
U
TYPICAL APPLICATIONS  
LT1103 FET Connection  
15V  
LT1103  
V
SW  
LT1103 TA03  
LT1105 FET Connection  
15V  
V
LT1105  
SW  
I
LIM  
LT1103 TA04  
26  
LT1103/LT1105  
U
TYPICAL APPLICATIONS  
Setting Oscillator Frequency  
Setting Overvoltage Lockout  
OVLO  
TH  
R2  
R1  
LT1105  
LT1103/LT1105  
OSC  
OVLO  
LT1103 TA09  
C
OSC  
LT1103 TA05  
CHOOSE OVLO  
LET R1 = 5k  
TH  
CHOOSE 20kHz ≤ f  
≤ 200kHz  
OSC  
100µA  
2.5V  
I
SF  
OVLO  
2.5V  
TH  
C
=
=
=
R2 =  
–1 R1  
OSC  
(
)
f
∆V  
f
f
OSC  
OSC  
(
)
OSC  
)
(
)
(
(
)
DC 0.66 66%  
Increasing Oscillator  
Maximum Duty Cycle  
Decreasing Oscillator  
Maximum Duty Cycle  
Synchronizing Oscillator Frequency  
to an External Clock  
5V  
LT1103/LT1105  
500ns  
LT1105  
LT1103/LT1105  
OSC  
5V  
OSC  
OSC  
1µF  
C
1:0.5  
OSC  
0V  
R
I1  
C
OSC  
C
R
OSC  
I1  
LT1103 TA07  
LT1103 TA08  
LT1103 TA06  
CHOOSE 0 ≤ DC ≤ 0.66  
CHOOSE 0.66 ≤ DC ≤ 1.0  
(6 – 9DC)  
(9DC – 6)  
SOLVE FOR X X =  
SOLVE FOR X X =  
2
ISOLATION  
BOUNDARY  
2
0 ≤ X ≤ 3  
0 ≤ X ≤ 1.5  
I1 = X • I = X • 100µA  
I1 = X • I = X • 100µA  
1.75V  
R =  
3.25V  
R =  
I1  
I1  
3X – 2X2  
9
3X + 2X2  
(
• 1 +  
)
100µA  
(
)
100µA  
C
=
OSC  
C =  
OSC  
• 1 –  
2.5V  
f
(
)
OSC  
)
(
9
2.5V  
f
OSC  
(
)
)
(
27  
LT1103/LT1105  
U
TYPICAL APPLICATIONS  
LT1103 Ground Connections  
15V  
IN  
SWITCH CURRENT PATH  
KEEP RESISTANCE LOW  
V
OSC  
GND  
V
C
FB  
SW  
V
LT1103 TA11a  
TO BIAS  
WINDING OUTPUT  
GND  
SEPARATE  
GROUND PATH  
SWITCH CURRENT PATH  
KEEP RESISTANCE LOW  
15V  
V
IN  
OSC  
GND  
V
C
FB  
SW  
V
LT1103 TA11b  
TO BIAS  
WINDING OUTPUT  
GND  
LT1105 Ground Connections  
HIGH CURRENT  
GROUND PATH  
V
GND  
SW  
I
LIM  
V
IN  
FB  
V
C
TO BIAS  
WINDING  
OUTPUT  
LT1103 TA12a  
28  
LT1103/LT1105  
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.  
N8 Package  
8-Lead PDIP (Narrow 0.300)  
(LTC DWG # 05-08-1510)  
0.400*  
(10.160)  
MAX  
8
7
6
5
4
0.255 ± 0.015*  
(6.477 ± 0.381)  
1
2
3
0.130 ± 0.005  
0.300 – 0.325  
0.045 – 0.065  
(3.302 ± 0.127)  
(1.143 – 1.651)  
(7.620 – 8.255)  
0.065  
(1.651)  
TYP  
0.009 – 0.015  
(0.229 – 0.381)  
0.125  
0.020  
(0.508)  
MIN  
(3.175)  
MIN  
+0.035  
0.325  
–0.015  
0.100 ± 0.010  
(2.540 ± 0.254)  
0.018 ± 0.003  
(0.457 ± 0.076)  
+0.889  
8.255  
(
)
N8 1197  
–0.381  
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)  
29  
LT1103/LT1105  
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.  
N Package  
14-Lead PDIP (Narrow 0.300)  
(LTC DWG # 05-08-1510)  
0.770*  
(19.558)  
MAX  
14  
13  
12  
11  
10  
9
8
7
0.255 ± 0.015*  
(6.477 ± 0.381)  
1
2
3
5
6
4
0.300 – 0.325  
(7.620 – 8.255)  
0.045 – 0.065  
(1.143 – 1.651)  
0.130 ± 0.005  
(3.302 ± 0.127)  
0.020  
(0.508)  
MIN  
0.065  
(1.651)  
TYP  
0.009 – 0.015  
(0.229 – 0.381)  
+0.035  
0.325  
0.005  
(0.125)  
MIN  
0.100 ± 0.010  
(2.540 ± 0.254)  
–0.015  
0.125  
(3.175)  
MIN  
0.018 ± 0.003  
(0.457 ± 0.076)  
+0.889  
8.255  
(
)
–0.381  
N14 1197  
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)  
30  
LT1103/LT1105  
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.  
T7 Package  
7-Lead Plastic TO-220 (Standard)  
(LTC DWG # 05-08-1422)  
0.165 – 0.180  
(4.191 – 4.572)  
0.147 – 0.155  
(3.734 – 3.937)  
DIA  
0.390 – 0.415  
(9.906 – 10.541)  
0.045 – 0.055  
(1.143 – 1.397)  
0.230 – 0.270  
(5.842 – 6.858)  
0.570 – 0.620  
(14.478 – 15.748)  
0.620  
(15.75)  
TYP  
0.460 – 0.500  
(11.684 – 12.700)  
0.330 – 0.370  
(8.382 – 9.398)  
0.700 – 0.728  
(17.780 – 18.491)  
0.095 – 0.115  
(2.413 – 2.921)  
0.152 – 0.202  
(3.860 – 5.130)  
0.260 – 0.320  
(6.604 – 8.128)  
0.013 – 0.023  
(0.330 – 0.584)  
0.040 – 0.060  
(1.016 – 1.524)  
0.026 – 0.036  
(0.660 – 0.914)  
0.135 – 0.165  
(3.429 – 4.191)  
0.155 – 0.195  
(3.937 – 4.953)  
T7 (TO-220) (FORMED) 1197  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
31  
LT1103/LT1105  
TYPICAL APPLICATION  
U
Minimum Parts Count Fully-Isolated Flyback 100kHz 50W Converter  
OPTIONAL OUTPUT FILTER  
MBR2045  
85V TO 270V  
AC  
10µH  
AC  
5V  
10A  
1.5KE300A  
5W  
+
+
+
50V  
470µF  
35V  
3600µF  
220k  
1W  
+
MUR150  
220µF  
385V  
499Ω  
*OUTPUT CAPACITOR IS THREE 1200µF,  
50V CAPACITORS IN PARALLEL TO  
ACHIEVE REQUIRED RIPPLE CURRENT  
RATING AND LOW ESR.  
–
1N4148  
1000pF  
100Ω  
BRIDGE  
RECTIFIER  
+
LINE  
FILTER  
WINDINGS FOR  
OPTIONAL  
±12V OUTPUTS  
BAV21  
BUK426-800A  
V
V
SW  
IN  
DC  
BAV21  
+
39µF  
25V  
LT1103  
16.2k  
1%  
10Ω  
TRANSFORMER DATA:  
COILTRONICS - CTX110228-3  
= 1.6mH  
15V  
FB  
L
(PRI)  
+
GND  
OSC  
V
C
1µF  
25V  
5.36k  
1%  
N
:N  
= 1:0.05  
= 1:0.27  
PRI SEC  
N
:N  
BIAS SEC  
390pF  
330Ω  
0.1µF  
0.047µF  
LT1103 TA01  
Danger!! Lethal Voltages Present – See Text  
Load Regulation  
5.25  
5.20  
5.15  
5.10  
270V  
AC  
5.05  
5.00  
4.95  
4.90  
4.85  
4.80  
4.75  
220V  
AC  
110V  
AC  
85V  
AC  
0
1
2
3
4
5
6
7
8
9
10  
I
(A)  
OUT  
LT1103 TA14  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LT1241  
High Speed Current Mode Pulse Width Modulators  
Off-Line Current Mode PWM  
Up to 500kHz Operation  
1MHz Operation  
LT1246  
LT1248  
Power Factor Controller  
Programmable Frequency, 16-Pin SO  
100kHz, SO-8  
LT1249  
Power Factor Controller  
LT1508  
Power Factor and PWM Controller  
Power Factor and PWM Controller  
Voltage Mode  
LT1509  
Current Mode  
11035fd LT/TP 0998 REV D 2K • PRINTED IN USA  
LINEAR TECHNOLOGY CORPORATION 1992  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
32  
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明