LT1175CN8-5-TR_技术文档

LT1175

500mA Negative

Low Dropout Micropower

Regulator

FeaTures

DescripTion

The LT^®1175 is a negative micropower low dropout

regulator. It features 45µA quiescent current, dropping

to 10µA in shutdown. A new reference ampliﬁer topology

gives precision DC characteristics along with the ability to

maintain good loop stability with an extremely wide range

of output capacitors. Very low dropout voltage and high

efﬁciency are obtained with a unique power transistor

anti-saturation design. Adjustable and ﬁxed 5V versions

are available.

n

Operating Current: 45µA

n

Adjustable Current Limit

n

Low Voltage Linear Dropout Characteristics

n

Stable with Wide Range of Output Capacitors

n

Shutdown Current: 10µA

n

Positive or Negative Shutdown Logic

n

Fixed 5V and Adjustable Versions

n

Tolerates Reverse Output Voltage

n

Available in 8-pin PDIP and SO Packages, 3-lead

SOT-223, 5-Pin Surface Mount DD and Through-Hole

TO-220 Packages

Several new features make the LT1175 very user-friendly.

The SHDN pin can interface directly to either positive or

negative logic levels. Current limit is user-selectable at

200mA, 400mA, 600mA and 800mA. The output can be

forced to reverse voltage without damage or latchup. Un-

likesomeearlierdesigns,theincreaseinquiescentcurrent

during a dropout condition is actively limited.

applicaTions

n

Analog Systems

n

Modems

n

Instrumentation

n

A/D and D/A Converters

The LT1175 has complete blowout protection with current

limiting, power limiting and thermal shutdown. Special

attention was given to the problem of high temperature

operation with micropower operating currents, preventing

output voltage rise under no-load conditions. The LT1175

is available in 8-pin PDIP and SO packages, 3-lead SOT-

223 as well as 5-pin surface mount DD and through-hole

TO-220 packages. The 8-pin SO package is specially

constructed for low thermal resistance.

n

Interface Drivers

n

Battery-Powered Systems

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

Minimum Input-to-Output Voltage

1.0

T

= 25°C

Typical LT1175 Connection

J

I

, I

TIED TO V

LIM2 LIM4 IN

0.8

0.6

0.4

0.2

0

+

C

OUT

C

*

IN

≥ 0.1µF

SHDN

GND

SENSE

–5V

UP TO 500mA

V

–V

IN

I

LT1175-5

OUTPUT

LIM2

I

LIM4

*C IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM

IN

INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION

0

0.2 0.3 0.4

0.5 0.6 0.7

0.1

1175 TA01

SECTION FOR DETAILS

OUTPUT CURRENT (A)

1175 TA02

1175fe

ꢀ

LT1175

absoluTe MaxiMuM raTings

(Note 1)

Input Voltage (Transient 1 sec, Note 11) ...................25V

Input Voltage (Continuous) .......................................20V

Input-to-Output Differential Voltage (Note 12)..........20V

5V SENSE Pin (with Respect to GND Pin).........2V, –10V

ADJ SENSE Pin

(with Respect to OUTPUT Pin)...................20V, –0.5V

5V SENSE Pin

(with Respect to OUTPUT Pin)......................20V, –7V

Output Reverse Voltage ..............................................2V

SHDN Pin to GND Pin Voltage (Note 2)........13.5V, –20V

SHDN Pin to V Pin Voltage.............................30V, –5V

IN

Operating Junction Temperature Range

LT1175C................................................. 0°C to 125°C

LT1175I.............................................. –40°C to 125°C

Ambient Operating Temperature Range

LT1175C................................................... 0°C to 70°C

LT1175I................................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

pin conFiguraTion

FRONT VIEW

TOP VIEW

FRONT VIEW

3

2

1

GND

V

1

2

3

4

V

I

8

7

6

5

4

3

2

1

SHDN

GND

IN

TAB

IS

IN

TAB IS

I

LIM2

LIM4

V

IN

V

IN

V

SENSE

OUTPUT

SENSE

SHDN

OUTPUT

GND

Q PACKAGE

ST PACKAGE

3-LEAD PLASTIC SOT-223

= 50°C/W

WITH BACKPLANE AND 10cm

TOPSIDE LAND SOLDERED TO TAB

N8 PACKAGE

8-LEAD PDIP

= 80°C/W TO 120°C/W

5-LEAD PLASTIC DD

θ

= 27°C/W TO 60°C/W

DEPENDING ON PC MOUNTING.

SEE DATA SHEET FOR DETAILS

JA

θ

JA

θ

JA

2

DEPENDING ON PC BOARD LAYOUT

TOP VIEW

V

1

2

3

4

8

7

6

5

V

I

IN

FRONT VIEW

I

LIM2

LIM4

5

4

3

2

1

SHDN

GND

OUTPUT

SENSE

SHDN

GND

V

IN

SENSE

OUTPUT

S8 PACKAGE

8-LEAD PLASTIC SO

TAB IS

IN

θ

= 60°C/W TO 100°C/W

JA

V

DEPENDING ON PC BOARD LAYOUT

T PACKAGE

5-LEAD PLASTIC TO-220

PINS 1, 8 ARE INTERNALLY CONNECTED TO DIE ATTACH PADDLE FOR HEAT SINKING.

ELECTRICAL CONTACT CAN BE MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE,

PINS 1, 8 SHOULD BE CONNECTED TO AN EXPANDED LAND THAT IS OVER AN INTERNAL

OR BACKSIDE PLANE.

θ

= 50°C/W, θ = 5°C/W

JC

JA

SEE APPLICATIONS INFORMATION

1175fe

ꢁ

LT1175

orDer inForMaTion

LEAD FREE FINISH

LT1175CN8#PBF

LT1175CN8-5#PBF

LT1175CS8#PBF

LT1175CS8-5#PBF

LT1175CST-5#PBF

LT1175CQ#PBF

LT1175CQ-5#PBF

LT1175CT#PBF

LT1175CT-5#PBF

LT1175IN8#PBF

LT1175IN8-5#PBF

LT1175IS8#PBF

LT1175IS8-5#PBF

LT1175IST-5#PBF

LT1175IQ#PBF

LT1175IQ-5#PBF

LT1175IT#PBF

LT1175IT-5#PBF

LEAD BASED FINISH

LT1175CN8

TAPE AND REEL

LT1175CN8#TRPBF

LT1175CN8-5#TRPBF

LT1175CS8#TRPBF

LT1175CS8-5#TRPBF

LT1175CST-5#TRPBF

LT1175CQ#TRPBF

LT1175CQ-5#TRPBF

LT1175CT#TRPBF

LT1175CT-5#TRPBF

LT1175IN8#TRPBF

LT1175IN8-5#TRPBF

LT1175IS8#TRPBF

LT1175IS8-5#TRPBF

LT1175IST-5#TRPBF

LT1175IQ#TRPBF

LT1175IQ-5#TRPBF

LT1175IT#TRPBF

LT1175IT-5#TRPBF

TAPE AND REEL

LT1175CN8#TR

PART MARKING*

LT1175CN8

LT1175CN8-5

1175

PACKAGE DESCRIPTION

8-Lead Plastic Dip

TEMPERATURE RANGE

0°C to 125°C

8-Lead Plastic Dip

0°C to 125°C

8-Lead Plastic SO

0°C to 125°C

11755

8-Lead Plastic SO

0°C to 125°C

11755

3-Lead Plastic SOT-223

5-Lead Plastic DD-Pak

5-Lead Plastic TO-220

8-Lead Plastic Dip

0°C to 125°C

LT1175CQ

LT1175CQ-5

LT1175CT

LT1175CT-5

LT1175IN8

LT1175IN8-5

1175I

0°C to 125°C

–40°C to 125°C

TEMPERATURE RANGE

0°C to 125°C

8-Lead Plastic Dip

8-Lead Plastic SO

1175I5

8-Lead Plastic SO

1175I5

3-Lead Plastic SOT-223

5-Lead Plastic DD-Pak

5-Lead Plastic TO-220

PACKAGE DESCRIPTION

8-Lead Plastic Dip

LT1175IQ

LT1175IQ-5

LT1175IT

LT1175IT-5

PART MARKING*

LT1175CN8

LT1175CN8-5

1175

LT1175CN8-5

LT1175CS8

LT1175CN8-5#TR

LT1175CS8#TR

8-Lead Plastic Dip

0°C to 125°C

8-Lead Plastic SO

0°C to 125°C

LT1175CS8-5

LT1175CST-5

LT1175CQ

LT1175CS8-5#TR

LT1175CST-5#TR

LT1175CQ#TR

11755

8-Lead Plastic SO

0°C to 125°C

11755

3-Lead Plastic SOT-223

5-Lead Plastic DD-Pak

5-Lead Plastic TO-220

8-Lead Plastic Dip

0°C to 125°C

LT1175CQ

LT1175CQ-5

LT1175CT

LT1175CT-5

LT1175IN8

LT1175IN8-5

1175I

0°C to 125°C

LT1175CQ-5

LT1175CQ-5#TR

LT1175CT#TR

0°C to 125°C

LT1175CT

0°C to 125°C

LT1175CT-5

LT1175CT-5#TR

0°C to 125°C

LT1175IN8

LT1175IN8#TR

–40°C to 125°C

LT1175IN8-5

LT1175IN8-5#TR

LT1175IS8#TR

8-Lead Plastic Dip

LT1175IS8

8-Lead Plastic SO

LT1175IS8-5

LT1175IS8-5#TR

LT1175IST-5#TR

LT1175IQ#TR

1175I5

8-Lead Plastic SO

LT1175IST-5

1175I5

3-Lead Plastic SOT-223

5-Lead Plastic DD-Pak

5-Lead Plastic TO-220

LT1175IQ

LT1175IQ-5

LT1175IT

LT1175IT-5

LT1175IQ-5

LT1175IQ-5#TR

LT1175IT

LT1175IT#TR

LT1175IT-5

LT1175IT-5#TR

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

1175fe

ꢂ

LT1175

elecTrical characTerisTics ^Thel denotes speciﬁcations which apply over the operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. V_OUT= 5V, V_IN= 7V, I_OUT= 0, V_SHDN= 3V, I_LIM2and I_LIM4tied to V_IN, T_J= 25°C, unless

otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values

except where polarity is not obvious.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Feedback Sense Voltage

Adjustable Part

Fixed 5V Part

3.743

4.93

3.8

5.0

3.857

5.075

V

Output Voltage Initial Accuracy

Adjustable, Measured at 3.8V Sense

Fixed 5V

0.5

1.5

%

l

Output Voltage Accuracy (All Conditions)

Quiescent Input Supply Current

V

– V

= 1V to V = 20V, I = 0A to 500mA

OUT

1.5

2.5

%

IN

OUT

IN

P = 0 to P

, T = T

to T

(Note 3)

MAX

J

MIN

MAX

V

IN

– V

≤ 12V

OUT

45

65

80

µA

l

GND Pin Current Increase with Load (Note 4)

Input Supply Current in Shutdown

10

20

µA/mA

V

SHDN

= 0V

20

25

µA

l

Shutdown Thresholds (Note 9)

Either Polarity On SHDN Pin

0.8

2.5

V

SHDN Pin Current (Note 2)

V

SHDN

V

SHDN

= 0V to 10V (Flows Into Pin)

= –15V to 0V (Flows Into Pin)

4

1

8

4

µA

Output Bleed Current in Shutdown (Note 6)

SENSE Pin Input Current

V

= 0V, V = 15V

0.1

1

5

µA

OUT

IN

l

(Adjustable Part Only, Current Flows Out of Pin)

(Fixed Voltage Only, Current Flows Out of Pin)

75

12

150

20

nA

µA

l

Dropout Voltage (Note 7)

I

= 25mA

0.1

0.18

0.5

0.2

0.26

0.7

V

OUT

LIM2

LIM4

= 100mA

= 500mA

Open, I

= 300mA

= 200mA

OUT

0.33

0.3

0.5

OUT

0.45

, I

Open, I

= 100mA

0.26

LIM2 LIM4

l

Current Limit (Note 11)

V

– V

= 1V to 12V

520

390

260

130

800

600

400

200

1300

975

650

325

mA

IN

OUT

Open

I

LIM2

LIM4

LIM2 LIM4

, I

Open

l

Line Regulation (Note 10)

Load Regulation (Note 5, 10)

Thermal Regulation

V

– V

= 1V to V = 20V

0.003

0.1

0.015

0.35

%/V

%

IN

OUT

IN

I

= 0mA to 500mA

OUT

P = 0 to P

(Notes 3, 8)

5-Pin Packages

8-Pin Packages

0.04

0.1

0.2

%/W

MAX

Output Voltage Temperature Drift

T = 25°C to T

, or 25°C to T

JMIN JMAX

0.25

1.25

%

J

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

is in saturation, GND pin current will be slightly higher. See Typical

Performance Characteristics.

Note 5: With I

= 0, at T > 125°C, power transistor leakage could

LOAD

J

increase higher than the 10µA to 25µA drawn by the output divider or ﬁxed

voltage SENSE pin, causing the output to rise above the regulated value.

To prevent this condition, an internal active pull-up will automatically turn

on, but supply current will increase.

Note 2: SHDN pin maximum positive voltage is 30V with respect to

–V and 13.5V with respect to GND. Maximum negative voltage is –20V

IN

with respect to GND and –5V with respect to –V .

IN

Note 3: P

= 1.5W for 8-pin packages, and 6W for 5-pin packages.

Note 6: This is the current required to pull the output voltage to within 1V

of ground during shutdown.

Note 7: Dropout voltage is measured by setting the input voltage equal to

the normal regulated output voltage and measuring the difference between

MAX

This power level holds only for input-to-output voltages up to 12V, beyond

which internal power limiting may reduce power. See Guaranteed Current

Limit curve in Typical Performance Characteristics section. Note that all

conditions must be met.

V

and V . For currents between 100mA and 500mA, with both I

IN

OUT LIM

Note 4: GND pin current increases because of power transistor base

drive. At low input-to-output voltages (<1V) where the power transistor

pins tied to V , maximum dropout can be calculated from

IN

V = 0.15 + 1.1Ω (I ).

DO OUT

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LT1175

elecTrical characTerisTics

Note 8: Thermal regulation is a change in the output voltage caused by

die temperature gradients, so it is proportional to chip power dissipation.

Temperature gradients reach ﬁnal value in less than 100ms. Output voltage

changes after 100ms are due to absolute die temperature changes and

reference voltage temperature coefﬁcient.

regulation will be affected by thermal regulation (Note 8) and chip

temperature changes. Load regulation speciﬁcation also holds for currents

up to the speciﬁed current limit when I or I are left open.

Note 11: Current limit is reduced for input-to-output voltage above 12V.

See the graph in Typical Performance Characteristics for guaranteed limits

above 12V.

Note 12: Operating at very large input-to-output differential voltages

(>15V) with load currents less than 5mA requires an output capacitor with

an ESR greater than 1Ω to prevent low level output oscillations.

LIM2

LIM4

Note 9: The lower limit of 0.8V is guaranteed to keep the regulator in

shutdown. The upper limit of 2.5V is guaranteed to keep the regulator

active. Either polarity may be used, referenced to GND pin.

Note 10: Load and line regulation are measured on a pulse basis with

pulse width of 20ms or less to keep chip temperature constant. DC

Typical perForMance characTerisTics

Typical Current Limit

Characteristics

Guaranteed Current Limit

Output Voltage Temperature Drift

1.0

0.8

0.6

0.4

0.2

0

0.6

0.5

0.4

0.3

0.2

0.1

0

5.05

5.00

4.95

3.84

3.80

3.76

CURRENT LIMIT CHANGES ONLY SLIGHTLY

WITH TEMPERATURE SO CURVES ARE

REPRESENTATIVE OF ALL TEMPERATURES

CURVES REPRE-

SENT MINIMUM

GUARANTEED

I

, I

TIED TO V

OUTPUT

LIM2 LIM4 IN

FIXED 5V PART

LIMITS AT ALL

TEMPERATURES

I

, I

TIED TO V

LIM2 LIM4 IN

I

TIED TO V

LIM4

IN

I

TIED TO V

LIM4

IN

I

TIED TO V

LIM2

IN

I

TIED TO V

LIM2

IN

FEEDBACK VOLTAGE

ADJUSTABLE PART

I

, I

OPEN

LIM2 LIM4

I

, I

OPEN

LIM2 LIM4

0

5

10

15

20

25

0

5

10

15

20

25

50

JUNCTION TEMPERATURE (°C)

125

–50

0

25

75 100

–25

INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)

1175 G03

1175 G01

1175 G02

SENSE Bias Current

(Adjustable Part)

Minimum Input-to-Output Voltage

1.0

0.8

0.6

0.4

0.2

0

1.0

0.8

0.6

0.4

0.2

0

100

80

60

40

20

0

T = 25°C

V

REDUCED UNTIL OUTPUT

IN

J

IN

V

REDUCED

VOLTAGE DROPS 1%.

I , I TIED TO V

LIM2 LIM4

UNTIL OUTPUT

VOLTAGE

IN

I

TIED

IN

LIM2

DROPS 1%

TO V

I

, I

LIM2 LIM4

T = 125°C

J

OPEN

I

TIED

IN

LIM4

TO V

T = 25°C

J

T = –55°C

J

I

, I

LIM2 LIM4

TIED TO V

IN

0

0.2 0.3 0.4

0.5 0.6 0.7

0

0.2 0.3 0.4

0.5 0.6 0.7

–50

0

25

50

75 100 125

0.1

–25

OUTPUT CURRENT (A)

TEMPERATURE (°C)

1175 G04

1175 G05

1175 G06

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LT1175

Typical perForMance characTerisTics

Shutdown Input Current

Shutdown Thresholds

SHDN Pin Characteristics

25

20

15

10

5

2.5

2.0

1.5

1.0

0.5

0

15

10

5

V

IN

= 25V

CHARACTERISTICS DO NOT

CHANGE SIGNIFICANTLY WITH

TEMPERATURE, SO A SINGLE

CURVE IS SHOWN. POSITIVE

CURRENT FLOWS INTO

SHDN PIN

POSITIVE THRESHOLD

NEGATIVE THRESHOLD

T = 25°C

J

T = 125°C

J

0

T = –55°C

J

IF SHDN PIN IS NEGATIVE WITH

RESPECT TO INPUT VOLTAGE AND

INPUT VOLTAGE IS LESS THAN 15V,

NEGATIVE BREAKOVER POINT WILL

–5

DEVICE IS OFF

BELOW THRESHOLD

BE ABOUT 8V BELOW –V

IN

0

–10

0

5

10

15

20

25

–25 –20 –15 –10 –5

0

5

10 15 20 25

–50

0

25

50

75 100 125

–25

INPUT VOLTAGE (V)

TEMPERATURE (°C)

SHUTDOWN TO GROUND VOLTAGE (V)

1175 G07

1175 G08

1175 G09

GND Pin Current

Ripple Rejection

20

16

12

8

100

V

= 12V

OUT

(ADJUSTABLE)

WITH 0.1µF ACROSS

DIVIDER RESISTOR

80

60

40

20

0

V

= 5V

OUT

V

– V

J

= 2V

OUT

(FIXED)

IN

POWER

TRANSISTOR

IN DROPOUT

T = 25°C

V

= 12V

OUT

(ADJUSTABLE)

T = –55°C

J

T = 25°C

J

4

I

V

C

= 100mA

OUT

IN

– V

= 2V

OUT

V

J

– V

≥ 3V

IN

OUT

= 1µF TANT

OUT

T = 25°C

0

10

100

1k

10k

100k

1M

0

0.2 0.3 0.4

0.5 0.6 0.7

0.1

FREQUENCY (Hz)

OUTPUT CURRENT (A)

1175 G10

RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF

INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN

25mA AND 500mA. LARGER OUTPUT CAPACITORS DO

NOT IMPROVE REJECTION FOR FREQUENCIES BELOW

50kHz. AT VERY LIGHT LOADS, REJECTION WILL

1175 G11

IMPROVE WITH LARGER OUTPUT CAPACITORS

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LT1175

pin FuncTions ^{(N8/Q/ST/S8/T)}

V (Pins 1, 8/Pin 3, Tab/Pin 2, Tab/Pins 1, 8/Pin 3, Tab):

The ﬁxed 5V version utilizes the SENSE pin to give true

Kelvin connections to the load or to drive an external pass

transistor for higher output currents. Bias current out

of the 5V SENSE pin is approximately 12µA. Separating

the SENSE and OUTPUT pins also allows for a new loop

compensation technique described in the Applications

Information section.

IN

Power is supplied to the device through this pin. A bypass

capacitor is required on this pin if the device is more than

six inches away from the main ﬁlter capacitor. In general,

the impedance of a battery rises with frequency, so it is

advisabletoincludeabypasscapacitorinbattery-powered

circuits. A 1µF or larger tantalum capacitor is suggested

for all applications, but if low ESR capacitors such as

ceramic or ﬁlm are used for the output and input capaci-

tors, the input capacitor should be three times the value

of the output capacitor.

GND (Pin 5/Pin 4/Pin 3/Pin 5/Pin 4): The GND pin has a

quiescent current of 45µA at zero load current, increas-

ing by approximately 10µA per mA of output current. At

500mA output current, GND pin current is about 5mA.

Current ﬂows into the GND pin.

I

, I

(Pins 2, 7/NA/NA/Pins 2, 7/NA): The two

LIM2 LIM4

currentlimitpinsareemittersectionsofthepowertransis-

tor. When left open, they ﬂoat several hundred millivolts

above the negative input voltage. When shorted to the

input voltage, they increase current limit by a minimum

SHDN (Pin 6/Pin 5/NA/Pin 6/Pin 5): The SHDN pin is

specially conﬁgured to allow it to be driven from either

positive voltage logic or with negative only logic. Forc-

ing the SHDN pin 2V either above or below the GND

pin will turn the regulator on. This makes it simple to

connect directly to positive logic signals for active low

shutdown. If no positive voltages are available, the

SHDN pin can be driven below the GND pin to turn the

regulator on. When left open, the SHDN pin will default

low to a regulator “on” condition. For all voltages below

absolute maximum ratings, the SHDN pin draws only a

few microamperes of current (see Typical Performance

Characteristics).MaximumvoltageontheSHDNpinis15V,

–20V with respect to the GND pin and 35V, –5V with

respect to the negative input pin.

of 200mA for I

and 400mA for I

. These pins must

LIM2

LIM4

be connected only to the input voltage, either directly or

through a resistor.

OUTPUT (Pin 3/Pin 1/Pin 1/Pin 3/Pin 1): The OUTPUT pin

isthecollectoroftheNPNpowertransistor.Itcanbeforced

to the input voltage, to ground or up to 2V positive with

respect to ground without damage or latchup (see Output

VoltageReversalinApplicationsInformationsection).The

LT1175 has foldback current limit, so maximum current at

the OUTPUT pin is a function of input-to-output voltage.

See Typical Performance Characteristics.

SENSE (Pin 4/Pin 2/NA/Pin 4/Pin 2): The SENSE pin is

used in the adjustable version to allow custom selection

of output voltage, with an external divider set to generate

3.8V at the SENSE pin. Input bias current is typically 75nA

ﬂowing out of the pin. Maximum forced voltage on the

SENSE pin is 2V and –10V with respect to GND pin.

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ꢆ

LT1175

applicaTions inForMaTion

The LT1175-5 is a ﬁxed 5V design with the SENSE pin

acting as a Kelvin connection to the output. Normally the

SENSE pin and the OUTPUT pin are connected directly

together, either close to the regulator or at the remote

load point.

Note to Reader: To avoid confusion when working with

negative voltages (is –6V more or less than –5V?), I have

decidedtotreattheLT1175asifitwereapositiveregulator

andexpressallvoltagesaspositivevalues,bothintextand

informulas. Ifyoudothesameandsimplyaddanegative

signtotheeventualanswer,confusionshouldbeavoided.

Please don’t give me a hard time about “preciseness” or

“correctness.” I have to ﬁeld phone calls from around

the world and this is my way of dealing with a multitude

of conventions. Thanks for your patience.

SHUTDOWN

LOGIC

> 2V OR < –2V TO

TURN REGULATOR ON

+

R1

C

IN

383k

1%

SHDN

GND

SENSE

C

OUT

V

IN

≥ 0.1µF

R2

825k

1%

LT1175

Setting Output Voltage

I

LIM2

V

OUT

I

OUTPUT

The LT1175 adjustable version has a feedback sense

voltage of 3.8V with a bias current of approximately 75nA

ﬂowing out of the SENSE pin. To avoid output voltage

errors caused by this current, the output divider string

(see Figure 1) should draw about 25µA. Table 1 shows

suggested resistor values for a range of output voltages.

The second part of the table shows resistor values which

draw only 10µA of current. Output voltage error caused

by bias current with the lower valued resistors is about

0.4% maximum and with the higher values, about 1%

maximum. A formula is also shown for calculating the

resistors for any output voltage.

LIM4

–12V

1175 F01

Figure 1. Typical LT1175 Adjustable Connection

Setting Current Limit

The LT1175 uses two I pins to set current limit (typical)

LIM

at 200mA, 400mA, 600mA or 800mA. The corresponding

minimumguaranteedcurrentsare130mA,260mA,390mA

and 520mA. This allows the user to select a current limit

tailored to his speciﬁc application and prevents the situa-

tion where short-circuit current is many times higher than

full-load current. Problems with input supply overload or

excessivepowerdissipationinafaultedloadareprevented.

Power limiting in the form of foldback current limit is built

inandreducescurrentlimitasafunctionofinput-to-output

voltage differential for differentials exceeding 14V. See the

graph in Typical Performance Characteristics. The LT1175

is guaranteed to be blowout-proof regardless of current

limit setting. The power limiting combined with thermal

shutdown protects the device from destructive junction

temperatures under all load conditions.

Table 1. Suggested Divider Resistors

OUTPUT

VOLTAGE

R1

R2

R1

R2

I

= 25µA NEAREST 1%

I

DIV

= 10µA NEAREST 1%

DIV

5V

6V

150k

47.5k

86.6k

165k

243k

324k

442k

383k

121k

221k

422k

619k

825k

1.13M

150k

383k

8V

10V

12V

15V

Shutdown

3.8V

I_DIV

R1=

In shutdown, the LT1175 draws only about 10µA. Special

circuitry is used to minimize increases in shutdown cur-

rent at high temperatures, but a slight increase is seen

above 125°C. One option not taken was to actively pull

down on the output during shutdown. This means that the

output will fall slowly after shutdown is initiated, at a rate

determined by load current plus the 12µA internal load,

and the size of the output capacitor. Active pull-down is

1175fe

R1 V − 3.8V

(

)

OUT

R2 =

Simple formula

(

)

3.8V

R1 V − 3.8V







(

)

OUT

Taking SENSE pin bias



current into account

3.8V +R1 I





( _FB)

I_DIV= Desired divider current

ꢇ

LT1175

applicaTions inForMaTion

normally a good thing when the regulator is used by itself,

but it prevents the user from shutting down the regulator

when a second power source is connected to the LT1175

output. If active output pull-down is needed in shutdown,

it can be added externally with a depletion mode PFET as

shown in Figure 2. Note that the maximum pinch-off volt-

age of the PFET must be less than the positive logic high

level to ensure that the device is completely off when the

regulator is active. The Motorola J177 device has 300Ω

on resistance for zero gate source voltage.

yet allows the power transistor to approach its theoretical

saturation limit.

Output Capacitor

Severalnewregulatordesigntechniquesareusedtomake

theLT1175extremelytolerantofoutputcapacitorselection.

Like most low dropout designs which use a collector or

drain of the power transistor to drive the output node, the

LT1175 uses the output capacitor as part of the overall

loop compensation. Older regulators generally required

the output capacitor to have a minimum value of 1µF to

100µF, a maximum ESR (Effective Series Resistance) of

0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to

0.3Ω. These restrictions usually could be met only with

good quality solid tantalum capacitors. Aluminum capaci-

tors have problems with high ESR unless much higher

values of capacitance are used (physically large). The ESR

of ceramic or ﬁlm capacitors was too low, which made

the capacitance/ESR zero frequency too high to maintain

phase margin in the regulator. Even with optimum capaci-

tors, loop phase margin was very low in previous designs

whenoutputcurrentwaslow. Theseproblemsledtoanew

designtechniquefortheLT1175errorampliﬁerandinternal

frequency compensation as shown in Figure 3.

3V TO 5V

s

Q1*

d

+

SHDN

GND

SENSE

C

OUT

≥ 0.1µF

V

–V

IN

LT1175-5

I

LIM2

I

OUTPUT

LIM4

* MOTOROLA J177

PINCH-OFF VOLTAGE MUST BE LESS THAN

POSITIVE LOGIC HIGH VOLTAGE

1175 F02

Figure 2. Active Output Pull-Down During Shutdown

A conventional regulator loop consists of error ampliﬁer

A1, driver transistor Q2 and power transistor Q1. Added

to this basic loop are secondary loops generated by Q3

Minimum Dropout Voltage

Dropoutvoltageistheminimumvoltagerequiredbetween

input and output to maintain proper output regulation.

For older 3-terminal regulator designs, dropout voltage

was typically 1.5V to 3V. The LT1175 uses a saturating

power transistor design which gives much lower dropout

voltage, typically 100mV at light loads and 450mV at full

load. Special precautions were taken to ensure that this

technique does not cause quiescent supply current to be

high under light load conditions. When the regulator input

voltage is too low to maintain a regulated output, the pass

transistor is driven hard by the error ampliﬁer as it tries

to maintain regulation. The current drawn by the driver

transistor could be tens of milliamperes even with little or

no load on the output. This indeed was the case for older

IC designs that did not actively limit driver current when

the power transistor saturated. The LT1175 uses a new

antisaturation technique that prevents high driver current,

and C . A DC negative feedback current fed into the error

F

ampliﬁer through Q3 and R causes overall loop current

N

gain to be very low at light load currents. This is not a

problem because very little gain is needed at light loads.

In addition to low gain, the parasitic pole frequency at Q2

base is extended by the DC feedback. The combination of

thesetwoeffectsdramaticallyimprovesloopphasemargin

at light loads and makes the loop tolerant of large ESR in

theoutputcapacitor.Withheavyloads,loopphaseandgain

are not nearly as troublesome and large negative feedback

could degrade regulation. The logarithmic behavior of the

base emitter voltage of Q1 reduces Q3 negative feedback

at heavy loads to prevent poor regulation.

Inaconventionaldesign,evenwiththenonlinearfeedback,

poor loop phase margin would occur at medium to heavy

loads if the ESR of the output capacitor fell below 0.3Ω.

1175fe

ꢈ

LT1175

applicaTions inForMaTion

GND

LT1175

+

3.8V

R1

R2

–

+

C

OUT

A1

LOAD

ESR

SENSE

Q2

AC

FEEDFORWARD

PATH

OUTPUT

C

F

20pF

OUTPUT

R

C

0.5Ω

NEGATIVE DC

FEEDBACK

AT LIGHT

LOADS

PARASITIC

COLLECTOR

RESISTANCE

Q3

Q1

POWER

TRANSISTOR

R

N

R

LIM

CURRENT LIMIT

SENSE RESISTOR

1175 F03

V

IN

Figure 3

This condition can occur with ceramic or ﬁlm capacitors

which often have an ESR under 0.1Ω. With previous de-

signs, the user was forced to add a real resistor in series

with the capacitor to guarantee loop stability. The LT1175

uses a unique AC feedforward technique to eliminate

The end result of all this attention to loop stability is that

the output capacitor used with the LT1175 can range in

value from 0.1µF to hundreds of microfarads, with an ESR

from 0Ω to 10Ω. This range allows the use of ceramic,

solid tantalum, aluminum and ﬁlm capacitors over a wide

range of values.

this problem. C is a conventional feedforward capacitor

F

often used in regulators to cancel the pole formed by the

output capacitor. It would normally be connected from the

regulated output node to the feedback node at the R1/R2

junction or to an internal node on the ampliﬁer as shown.

In this case, however, the capacitor is connected to the

The optimum output capacitor type for the LT1175 is

still solid tantalum, but there is considerable leeway in

selecting the exact unit. If large load current transients

are expected, larger capacitors with lower ESR may be

needed to control worst-case output variation during

transients. If transients are not an issue, the capacitor

can be chosen for small physical size, low price, etc.

Concerns about surge currents in tantalum capacitors are

not an issue for the output capacitor because the LT1175

limits inrush current to well below the level which can

cause capacitor damage. Surges caused by shorting the

regulator output are also not a problem because tantalum

internalstructureofthepowertransistor.R istheunavoid-

C

able parasitic collector resistance of the power transistor.

Access to the node at the bottom of R is available only

C

in monolithic structures where Kelvin connections can

be made to the NPN buried collector layer. The loop now

responds as if R were in series with the output capacitor

C

and good loop stability is achieved even with extremely

low ESR in the output capacitor.

1175fe

ꢀ0

LT1175

applicaTions inForMaTion

capacitors do not fail during a “shorting out” surge, only

voltage when the regulator output is being pulled high. If

a 4.8V output is pulled to 5V, for instance, the load on the

primary regulator would be (5V – 4.8V)/2kΩ = 100µA.

This also means that if the internal pass transistor leaks

50µA, the output voltage will be (50µA)(2kΩ) = 100mV

high. Thisconditionwillnotoccurundernormaloperating

conditions, but could occur immediately after an output

short circuit had overheated the chip.

during a “charge up” surge.

The output capacitor should be located within several

inchesoftheregulator.Ifremotesensingisused,theoutput

capacitor can be located at the remote sense node, but the

GND pin of the regulator should also be connected to the

remote site. The basic rule is to keep SENSE and GND pins

close to the output capacitor, regardless of where it is.

Operating at very large input-to-output differential volt-

ages (>15V) with load currents less than 5mA requires an

output capacitor with an ESR greater than 1Ω to prevent

low level output oscillations.

Thermal Considerations

The LT1175 is available in a special 8-pin surface mount

packagewhichhasPins1and8connectedtothedieattach

paddle.ThisreducesthermalresistancewhenPins1and8

are connected to expanded copper lands on the PC board.

Table2showsthermalresistanceforvariouscombinations

of copper lands and backside or internal planes. Table 2

also shows thermal resistance for the 5-pin DD surface

mount package and the 8-pin DIP and package.

Input Capacitor

The LT1175 requires a separate input bypass capacitor

only if the regulator is located more than six inches from

the raw supply output capacitor. A 1µF or larger tantalum

capacitor is suggested for all applications, but if low ESR

capacitors such as ceramic or ﬁlm are used for the out-

put and input capacitors, the input capacitor should be

at least three times the value of the output capacitor. If a

solid tantalum or aluminum electrolytic output capacitor

is used, the input capacitor is very noncritical.

Table 2. Package Thermal Resistance (°C/W)

LAND AREA

DIP

140

110

ST

90

70

SO

100

80

Q

Minimum

60

50

Minimum with

Backplane

2

1cm Top Plane with

100

80

64

50

75

60

35

27

Backplane

High Temperature Operation

2

10cm Top Plane

with Backplane

The LT1175 is a micropower design with only 45µA qui-

escent current. This could make it perform poorly at high

temperatures (>125°C), where power transistor leakage

might exceed the output node loading current (5µA to

15µA). To avoid a condition where the output voltage

driftsuncontrolledhighduringahightemperatureno-load

condition, the LT1175 has an active load which turns on

when the output is pulled above the nominal regulated

voltage. This load absorbs power transistor leakage and

maintains good regulation. There is one downside to this

feature,however.Iftheoutputispulledhighdeliberately,as

itmightbewhentheLT1175isusedasabackuptoaslightly

higher output from a primary regulator, the LT1175 will act

as an unwanted load on the primary regulator. Because of

this, the active pull-down is deliberately “weak.” It can be

modeled as a 2k resistor in series with an internal clamp

Tocalculatedietemperature, maximumpowerdissipation

or maximum input voltage, use the following formulas

with correct thermal resistance numbers from Table 2.

For through-hole TO-220 applications use θ = 50°C/W

JA

without a heat sink and θ = 5°C/W + heat sink thermal

JA

resistance when using a heat sink.

Die Temp = T_A+ θ_JAV − V

I

(

_OUT)( _LOAD

)

IN

T_MAX− T_A

θ_JA

T_MAX− T_A

Maximum Power Dissipation =

Maximum Input Voltage

for Thermal Considerations

=

+ V_OUT

θ_JA

I

(

)

LOAD

1175fe

ꢀꢀ

LT1175

applicaTions inForMaTion

T

= Maximum ambient temperature

between the input and output of the regulator. Reverse

voltages between input and output above 1V will damage

the regulator if large currents are allowed to ﬂow. Simply

disconnecting the input source with the output held up

will not cause damage even though the input-to-output

voltage will become slightly reversed.

A

T

= Maximum LT1175 die temperature (125°C for

commercial and industrial grades)

MAX

θ

= LT1175 thermal resistance, junction to ambient

JA

V

= Maximum continuous input voltage at maximum

load current

IN

High Frequency Ripple Rejection

I

= Maximum load current

LOAD

The LT1175 will sometimes be powered from switching

regulatorsthatgeneratetheunregulatedorquasi-regulated

inputvoltage.Thisvoltagewillcontainhighfrequencyripple

that must be rejected by the linear regulator. Special care

was taken with the LT1175 to maximize high frequency

ripple rejection, but as with any micropower design,

rejection is strongly affected by ripple frequency. The

graph in the Typical Performance Characteristics section

shows 60dB rejection at 1kHz, but only 15dB rejection at

100kHz for the 5V part. Photographs in Figures 4a and 4b

show actual output ripple waveforms with square wave

and triwave input ripple.

Example: LT1175S8 with I

= 200mA, V

= 5V,

LOAD

OUT

V

= 7V, T = 60°C. Maximum die temperature for the

IN

A

LT1175S8 is 125°C. Thermal resistance from Table 2 is

found to be 80°C/W.

Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C

125 – 60

Maximum Power Dissipation =

= 0.81W

+ 5 = 9V

80

Maximum Continuous

Input Voltage

(for Thermal Considerations)

125 – 60

=

80 0.2

(

)

Output Voltage Reversal

C

= 4.7µF TANT

= 1µF TANT

The LT1175 is designed to tolerate an output voltage

reversal of up to 2V. Reversal might occur, for instance,

if the output was shorted to a positive 5V supply. This

would almost surely destroy IC devices connected to the

negative output. Reversal could also occur during start-

up if the positive supply came up ﬁrst and loads were

connected between the positive and negative supplies.

For these reasons, it is always good design practice to

add a reverse biased diode from each regulator output to

ground to limit output voltage reversal. The diode should

be rated to handle full negative load current for start-up

situations,ortheshort-circuitcurrentofthepositivesupply

if supply-to-supply shorts must be tolerated.

OUT

OUTPUT

20mV/DIV

INPUT

RIPPLE

100mV/DIV

f = 50kHz

1175 F04a

5µs/DIV

Figure 4a.

C

= 4.7µF TANT

= 1µF TANT

OUT

OUTPUT

100mV/DIV

Input Voltage Lower Than Output

OUT

Linear Technology’s positive low dropout regulators

LT1121 and LT1129, will not draw large currents if the

input voltage is less than the output. These devices use a

lateralPNPpowertransistorstructurethathas40Vemitter

base breakdown voltage. The LT1175, however, uses an

NPN power transistor structure that has a parasitic diode

INPUT

RIPPLE

100mV/DIV

f = 100kHz

1175 F04b

2µs/DIV

Figure 4b.

1175fe

ꢀꢁ

LT1175

applicaTions inForMaTion

To estimate regulator output ripple under different

conditions, the following general comments should be

helpful:

loads, larger resistors and smaller capacitors can be used

to save space. At heavier loads an inductor may have to

be used in place of the resistor. The value of the inductor

can be calculated from:

1. Output ripple at high frequency is only weakly affected

by load current or output capacitor size for medium

to heavy loads. At very light loads (<10mA), higher

frequency ripple may be reduced by using larger output

capacitors.

ESR

L

=

FIL

rr / 20

10

2π f

( )

(

)

ESR = Effective series resistance of ﬁlter capacitor. This

assumesthatthecapacitivereactanceissmallcom-

pared to ESR, a reasonable assumption for solid

tantalum capacitors above 2.2µF and 50kHz.

2. Afeedforwardcapacitoracrosstheresistordividerused

with the adjustable part is effective in reducing ripple

only for output voltages greater than 5V and only for

frequencies less than 100kHz.

f

= Ripple frequency

3. Input-to-output voltage differential has little effect on

ripple rejection until the regulator actually enters a

dropout condition of 0.2V to 0.6V.

rr = Ripple rejection ratio of ﬁlter in dB

Example: ESR = 1.2Ω, f = 100kHz, rr = –25dB.

1.2

If ripple rejection needs to be improved, an input ﬁlter can

be added. This ﬁlter can be a simple RC ﬁlter using a 1Ω

to 10Ω resistor. A 3.3Ω resistor for instance, combined

with a 0.3Ω ESR solid tantalum capacitor, will give an ad-

ditional 20dB ripple rejection. The size of the resistor will

be dictated by maximum load current. If the maximum

L

=

= 34µH

FIL

5

−25/ 20



6.3 10





10







Solid tantalum capacitors are suggested for the ﬁlter to

keep ﬁlter Q fairly low. This prevents unwanted ringing at

theresonantfrequencyoftheﬁlterandoscillationproblems

with the ﬁlter/regulator combination.

voltage drop allowable across the resistor is “V ,” and

R

maximum load current is I

, R = V /I

. At light

LOAD

R LOAD

1175fe

ꢀꢂ

LT1175

package DescripTion

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

.400*

(10.160)

MAX

8

7

6

5

4

.255 ± .015*

(6.477 ± 0.381)

1

2

3

.130 ± .005

.300 – .325

.045 – .065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

.065

(1.651)

TYP

.008 – .015

(0.203 – 0.381)

.120

.020

(0.508)

MIN

(3.048)

MIN

+.035

.325

–.015

.018 ± .003

(0.457 ± 0.076)

.100

(2.54)

BSC

+0.889

8.255

(

)

N8 1002

–0.381

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

1175fe

ꢀꢃ

LT1175

package DescripTion

Q Package

5-Lead Plastic DD Pak

(Reference LTC DWG # 05-08-1461)

.060

(1.524)

TYP

.390 – .415

(9.906 – 10.541)

.060

(1.524)

.165 – .180

(4.191 – 4.572)

.256

(6.502)

.045 – .055

(1.143 – 1.397)

15° TYP

+.008

.004

–.004

.060

(1.524)

.059

(1.499)

TYP

.183

(4.648)

.330 – .370

(8.382 – 9.398)

+0.203

–0.102

0.102

(

)

.095 – .115

(2.413 – 2.921)

.075

(1.905)

.067

(1.702)

BSC

.050 ± .012

(1.270 ± 0.305)

.300

(7.620)

.013 – .023

(0.330 – 0.584)

+.012

.143

–.020

.028 – .038

+0.305

BOTTOM VIEW OF DD PAK

HATCHED AREA IS SOLDER PLATED

COPPER HEAT SINK

3.632

Q(DD5) 0502

(0.711 – 0.965)

(

)

–0.508

TYP

.420

.276

.080

.420

.350

.325

.205

.565

.320

.090

.042

.090

.042

.067

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

RECOMMENDED SOLDER PAD LAYOUT

FOR THICKER SOLDER PASTE APPLICATIONS

1. DIMENSIONS IN INCH/(MILLIMETER)

2. DRAWING NOT TO SCALE

1175fe

ꢀꢄ

LT1175

package DescripTion

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.189 – .197

(4.801 – 5.004)

NOTE 3

.045 ±.005

.050 BSC

7

5

8

6

.245

MIN

.160 ±.005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

.030 ±.005

TYP

1

2

3

4

RECOMMENDED SOLDER PAD LAYOUT

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0°– 8° TYP

.016 – .050

(0.406 – 1.270)

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

NOTE:

INCHES

1. DIMENSIONS IN

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

SO8 0303

ST Package

3-Lead Plastic SOT-223

(Reference LTC DWG # 05-08-1630)

.248 – .264

(6.30 – 6.71)

.129 MAX

.114 – .124

(2.90 – 3.15)

.059 MAX

.264 – .287

(6.70 – 7.30)

.248 BSC

.130 – .146

(3.30 – 3.71)

.039 MAX

.059 MAX

.090

BSC

.181 MAX

RECOMMENDED SOLDER PAD LAYOUT

.033 – .041

(0.84 – 1.04)

.0905

(2.30)

BSC

10° – 16°

.010 – .014

10°

MAX

.071

(1.80)

MAX

(0.25 – 0.36)

10° – 16°

.0008 – .0040

(0.0203 – 0.1016)

.024 – .033

(0.60 – 0.84)

.012

(0.31)

MIN

.181

(4.60)

BSC

ST3 (SOT-233) 0502

1175fe

ꢀꢅ

LT1175

package DescripTion

T Package

5-Lead Plastic TO-220 (Standard)

(Reference LTC DWG # 05-08-1421)

.165 – .180

(4.191 – 4.572)

.147 – .155

(3.734 – 3.937)

DIA

.390 – .415

(9.906 – 10.541)

.045 – .055

(1.143 – 1.397)

.230 – .270

(5.842 – 6.858)

.570 – .620

(14.478 – 15.748)

.620

(15.75)

TYP

.460 – .500

(11.684 – 12.700)

.330 – .370

(8.382 – 9.398)

.700 – .728

(17.78 – 18.491)

.095 – .115

(2.413 – 2.921)

SEATING PLANE

.152 – .202

(3.861 – 5.131)

.155 – .195*

(3.937 – 4.953)

.260 – .320

(6.60 – 8.13)

.013 – .023

(0.330 – 0.584)

.067

BSC

.135 – .165

(3.429 – 4.191)

.028 – .038

(0.711 – 0.965)

(1.70)

* MEASURED AT THE SEATING PLANE

T5 (TO-220) 0801

revision hisTory ^{(Revision history begins at Rev E)}

REV

DATE

11/09 Revise Typical Application

Revise Pin Conﬁguration Drawings and Layout

Update Order Information

Added and Pin Numbers Added to Pin Funcitons

DESCRIPTION

PAGE NUMBER

E

1

2

3

V

IN

7

Title Added to Table 1

8

8, 9, 10, 12

11

Revised Figures 1, 2, 3, 4a and 4b

Value Correction in Final Paragraph of Output Capacitor Section

1175fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ꢀꢆ

LT1175

relaTeD parTs

PART NUMBER

LT1121

DESCRIPTION

COMMENTS

150mA Positive Micropower Low Dropout Regulator with Shutdown

700mA Positive Micropower Low Dropout Regulator with Shutdown

3A Negative Low Dropout Regulator

LT1129

LT1185

LT1521

300mA Positive Micropower Low Dropout Regulator with Shutdown

3A Positive Micropower Low Dropout Regulator with Shutdown

LT1529

1175fe

LT 1109 REV E • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢀꢇ

●

 LINEAR TECHNOLOGY CORPORATION 1995

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1175CN8-5-TR
厂家：	Linear
描述：	500mA Negative Low Dropout Micropower Regulator 500毫安负低压差稳压器微稳压器
文件：	总18页 (文件大小：306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1175CN8-5-TR [Linear]

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