LT1175CQ [Linear]
500mA Negative Low Dropout Micropower Regulator; 500毫安负低压差稳压器微
| 型号： | LT1175CQ |
| 厂家： | 
Linear |
| 描述： | 500mA Negative Low Dropout Micropower Regulator |
| 文件： | 总12页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1175
500m A Ne g a tive
Lo w Dro p o ut Mic ro p o we r
Re g ula to r
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FEATURES
DESCRIPTIO
The LT®1175 is a negative micropower low dropout regu-
lator. It features 45µA quiescent current, dropping to
10µA in shutdown. A new reference amplifier topology
gives precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
efficiencyareobtainedwithauniquepowertransistoranti-
saturation design. Adjustable and fixed 5V versions are
available.
■
Stable with Wide Range of Output Capacitors
Operating Current: 45µA
■
■
■
■
■
■
■
Shutdown Current: 10µA
Adjustable Current Limit
Positive or Negative Shutdown Logic
Low Voltage Linear Dropout Characteristics
Fixed 5V and Adjustable Versions
Tolerates Reverse Output Voltage
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Several new features make the LT1175 very user-friendly.
The SHDN pin can interface directly to either positive or
negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latchup.
Unlike some earlier designs, the increase in quiescent
current during a dropout condition is actively limited.
APPLICATIO S
■
Analog Systems
Modems
Instrumentation
A/D and D/A Converters
Interface Drivers
Battery-Powered Systems
■
■
■
■
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The LT1175 has complete blowout protection with current
limiting, power limiting and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents,preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin PDIP and SO packages, 3-lead SOT-
223 as well as 5-pin surface mount DD and through-hole
TO-220 packages. The 8-pin SO package is specially
constructed for low thermal resistance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Minimum Input-to-Output Voltage
TYPICAL APPLICATIO
1.0
T = 25°C
J
Typical LT1175 Connection
I
, I TIED TO V
LIM2 LIM4 IN
0.8
0.6
0.4
0.2
0
+
+
C
OUT
C
*
IN
≥ 0.1µF
SHDN
GND
SENSE
LT1175-5 OUT
–5V
UP TO 500mA
INPUT
–V
IN
I
LIM2
I
LIM4
*C IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
IN
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
SECTION FOR DETAILS
0
0.2 0.3 0.4
0.5 0.6 0.7
0.1
OUTPUT CURRENT (A)
1175 TA01
1175 TA02
1
LT1175
W W
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ABSOLUTE MAXIMUM RATINGS (Note 1)
SHDN Pin to V Pin Voltage .......................... 30V, –5V
Operating Junction Temperature Range
LT1175C.............................................. 0°C to 125°C
LT1175I .......................................... –40°C to 125°C
Ambient Operating Temperature Range
Input Voltage (Transient 1 sec, Note 11) ................ 25V
Input Voltage (Continuous) .................................... 20V
Input-to-Output Differential Voltage (Note 12)........ 20V
5V SENSE Pin (with Respect to GND Pin) ...... 2V, –10V
ADJ SENSE Pin
IN
LT1175C................................................ 0°C to 70°C
LT1175I ............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(with Respect to OUTPUT Pin) ................ 20V, –0.5V
5V SENSE Pin
(with Respect to OUTPUT Pin) .................. 20V, – 7V
Output Reverse Voltage ............................................ 2V
SHDN Pin to GND Pin Voltage (Note 2) ..... 13.5V, –20V
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PACKAGE/ORDER INFORMATION
FRONT VIEW
TOP VIEW
FRONT VIEW
ORDER
PART NUMBER
ORDER
PART NUMBER
ORDER
PART NUMBER
1
2
3
GND
V
1
2
3
4
V
8
7
6
5
5
4
3
2
1
SHDN
GND
INPUT
SENSE
OUTPUT
IN
IN
TAB
IS
INPUT
TAB IS
INPUT
I
I
LIM4
LIM2
V
IN
OUTPUT
SHDN
GND
LT1175CQ
LT1175CQ-5
LT1175IQ
LT1175CST-5
LT1175IST-5
LT1175CN8
LT1175CN8-5
LT1175IN8
OUTPUT
SENSE
Q PACKAGE
5-LEAD PLASTIC DD
ST PACKAGE
3-LEAD PLASTIC SOT-223
N8 PACKAGE
8-LEAD PDIP
LT1175IQ-5
θJA = 27°C/ W TO 60°C/W DEPENDING
ON PC MOUNTING. SEE DATA SHEET
FOR DETAILS
LT1175IN8-5
θJA = 50°C/W WITH BACKPLANE
AND 10cm2 TOPSIDE LAND
SOLDERED TO TAB
θJA = 80°C/W TO 120°C/W DEPENDING
ON PC BOARD LAYOUT
ORDER
PART NUMBER
ORDER
PART NUMBER
PINS 1, 8 ARE INTERNALLY
CONNECTED TO DIE
FRONT VIEW
TOP VIEW
5
4
3
2
1
SHDN
GND
INPUT
SENSE
OUTPUT
ATTACH PADDLE FOR HEAT
SINKING. ELECTRICAL
CONTACT CAN BE MADE TO
EITHER PIN. FOR BEST
THERMAL RESISTANCE,
PINS 1, 8 SHOULD BE
CONNECTED TO AN
EXPANDED LAND THAT IS
OVER AN INTERNAL OR
BACKSIDE PLANE.
V
1
2
3
4
8
7
6
5
V
IN
IN
LT1175CT
LT1175CT-5
LT1175IT
LT1175CS8
LT1175CS8-5
LT1175IS8
I
I
LIM4
LIM2
OUTPUT
SHDN
GND
SENSE
TAB IS
INPUT
LT1175IT-5
LT1175IS8-5
S8 PACKAGE
8-LEAD PLASTIC SO
T PACKAGE
5-LEAD PLASTIC TO-220
S8 PART MARKING
θJA = 60°C/ W TO 100°C/W DEPENDING
ON PC BOARD LAYOUT
θJA = 50°C/ W, θJC = 5°C/ W
SEE APPLICATIONS
INFORMATION
1175
1175I
11755
1175I5
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VOUT = 5V, V = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to V , T = 25°C,
IN
IN
J
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Feedback Sense Voltage
Adjustable Part
Fixed 5V Part
3.743
4.93
3.8
5.0
3.857
5.075
V
V
Output Voltage Initial Accuracy
Adjustable, Measured at 3.8V Sense
Fixed 5V
0.5
0.5
1.5
1.5
%
%
Output Voltage Accuracy (All Conditions)
Quiescent Input Supply Current
V – V = 1V to V = 20V, I = 0A to 500mA
OUT
●
●
1.5
2.5
%
IN
OUT
IN
P = 0 to P , T = T to T (Note 3)
MAX
MAX
J
MIN
V – V ≤ 12V
45
65
80
µA
µA
IN
OUT
2
LT1175
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VOUT = 5V, V = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to V , T = 25°C,
IN
IN
J
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GND Pin Current Increase with Load (Note 4)
Input Supply Current in Shutdown
●
10
10
20
µA/mA
V
= 0V
20
25
µA
µA
SHDN
●
●
●
Shutdown Thresholds (Note 9)
SHDN Pin Current (Note 2)
Either Polarity On SHDN Pin
0.8
2.5
V
V
= 0V to 10V (Flows Into Pin)
= –15V to 0V (Flows Into Pin)
4
1
8
4
µA
µA
SHDN
V
SHDN
Output Bleed Current in Shutdown (Note 6)
SENSE Pin Input Current
V
= 0V, V = 15V
0.1
1
1
5
µA
µA
OUT
IN
●
(Adjustable Part Only, Current Flows Out of Pin)
(Fixed Voltage Only, Current Flows Out of Pin)
●
●
75
12
150
20
nA
µA
Dropout Voltage (Note 7)
I
= 25mA
= 100mA
= 500mA
●
●
●
●
●
●
0.1
0.18
0.5
0.33
0.3
0.2
0.26
0.7
0.5
0.45
0.45
V
V
V
V
V
V
OUT
I
OUT
I
OUT
I
Open, I
Open, I
= 300mA
= 200mA
LIM2
OUT
I
LIM4
OUT
I
, I
Open, I
= 100mA
0.26
LIM2 LIM4
OUT
Current Limit (Note 11)
V – V = 1V to 12V
●
●
●
●
520
390
260
130
800
600
400
200
1300
975
650
325
mA
mA
mA
mA
IN
OUT
I
Open
LIM2
I
Open
LIM4
I
, I
Open
LIM2 LIM4
Line Regulation (Note 10)
Load Regulation (Note 5, 10)
Thermal Regulation
V – V = 1V to V = 20V
●
●
0.003
0.1
0.015
0.35
%/V
%
IN
OUT
IN
I
= 0mA to 500mA
OUT
P = 0 to P
(Notes 3, 8)
5-Pin Packages
8-Pin Packages
0.04
0.1
0.1
0.2
%/W
%/W
MAX
Output Voltage Temperature Drift
T = 25°C to T
, or 25°C to T
JMAX
0.25
1.25
%
J
JMIN
Note 1: Absolute Maximum Ratings are those values beyond which the life
V
IN
and V . For currents between 100mA and 500mA, with both I
OUT LIM
of a device may be impaired.
pins tied to V , maximum dropout can be calculated from
IN
V
DO
= 0.15 + 1.1Ω (I ).
OUT
Note 2: SHDN pin maximum positive voltage is 30V with respect to
–V and 13.5V with respect to GND. Maximum negative voltage is –20V
Note 8: Thermal regulation is a change in the output voltage caused by die
temperature gradients, so it is proportional to chip power dissipation.
Temperature gradients reach final value in less than 100ms. Output
voltage changes after 100ms are due to absolute die temperature changes
and reference voltage temperature coefficient.
IN
with respect to GND and –5V with respect to –V .
IN
Note 3: P
= 1.5W for 8-pin packages, and 6W for 5-pin packages. This
MAX
power level holds only for input-to-output voltages up to 12V, beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 9: The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used, referenced to GND pin.
Note 4: GND pin current increases because of power transistor base drive.
At low input-to-output voltages (< 1V) where the power transistor is in
saturation, GND pin current will be slightly higher. See Typical
Performance Characteristics.
Note 10: Load and line regulation are measured on a pulse basis with
pulse width of 20ms or less to keep chip temperature constant. DC
regulation will be affected by thermal regulation (Note 8) and chip
temperature changes. Load regulation specification also holds for currents
Note 5: With I
= 0, at T > 125°C, power transistor leakage could
J
LOAD
up to the specified current limit when I
or I
are left open.
increase higher than the 10µA to 25µA drawn by the output divider or fixed
voltage SENSE pin, causing the output to rise above the regulated value.
To prevent this condition, an internal active pull-up will automatically turn
on, but supply current will increase.
LIM2
LIM4
Note 11: Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.
Note 6: This is the current required to pull the output voltage to within 1V
of ground during shutdown.
Note 12: Operating at very large input-to-output differential voltages
(>15V) with load currents less than 5mA requires an output capacitor with
an ESR greater than 1Ω to prevent low level output oscillations.
Note 7: Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
3
LT1175
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical Current Limit
Characteristics
Output Voltage Temperature Drift
Guaranteed Current Limit
5.05
5.00
4.95
3.84
3.80
3.76
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.8
0.6
0.4
0.2
0
CURRENT LIMIT CHANGES ONLY SLIGHTLY
WITH TEMPERATURE SO CURVES ARE
REPRESENTATIVE OF ALL TEMPERATURES
CURVES REPRE-
SENT MINIMUM
GUARANTEED
LIMITS AT ALL
TEMPERATURES
I
, I
TIED TO V
OUTPUT
FIXED 5V PART
LIM2 LIM
IN
I
, I
TIED TO V
IN
LIM2 LIM
I
TIED TO V
IN
LIM4
I
TIED TO V
IN
LIM4
I
TIED TO V
LIM2
IN
I
TIED TO V
IN
LIM2
FEEDBACK VOLTAGE
ADJUSTABLE PART
I
, I
OPEN
LIM2 LIM4
I
, I
OPEN
LIM2 LIM4
0
5
10
15
20
25
–50
0
25
50
75 100 125
–25
0
5
10
15
20
25
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
1175 G02
1175 G03
1175 G01
SENSE Bias Current
(Adjustable Part)
Minimum Input-to-Output Voltage
Minimum Input-to-Output Voltage
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
100
80
60
40
20
0
T = 25°C
V
IN
REDUCED UNTIL OUTPUT
J
V
IN
REDUCED
VOLTAGE DROPS 1%.
, I TIED TO V
UNTIL OUTPUT
VOLTAGE
DROPS 1%
I
LIM2 LIM4
IN
I
TIED
LIM2
TO V
IN
I
, I
LIM2 LIM4
OPEN
T = 125°C
J
I
TIED
LIM4
TO V
IN
T = 25°C
J
T = –55°C
J
I
, I
LIM2 LIM4
TIED TO V
IN
0
0.2 0.3 0.4
0.5 0.6 0.7
0.4
OUTPUT CURRENT (A)
0.7
50
TEMPERATURE (°C)
125
0.1
0
0.2 0.3
0.5 0.6
–50
0
25
75 100
0.1
–25
OUTPUT CURRENT (A)
1175 G04
1175 G05
1175 G06
SHDN Pin Characteristics
Shutdown Thresholds
Shutdown Input Current
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
15
10
5
V
IN
= 25V
CHARACTERISTICS DO NOT
CHANGE SIGNIFICANTLY WITH
TEMPERATURE, SO A SINGLE
CURVE IS SHOWN. POSITIVE
CURRENT FLOWS INTO
SHDN PIN
POSITIVE THRESHOLD
NEGATIVE THRESHOLD
T = 25°C
J
T = 125°C
J
0
T = –55°C
J
IF SHDN PIN IS NEGATIVE WITH
RESPECT TO INPUT VOLTAGE AND
INPUT VOLTAGE IS LESS THAN 15V,
NEGATIVE BREAKOVER POINT WILL
–5
DEVICE IS OFF
BELOW THRESHOLD
BE ABOUT 8V BELOW –V
IN
0
–10
0
5
10
15
20
25
–50
0
25 50
75
100
125
–25 –20 –15 –10 –5
0
5
10 15 20 25
–25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
SHUTDOWN TO GROUND VOLTAGE (V)
1175 G07
1175 G09
1175 G08
4
LT1175
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TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection
GND pin Current
20
16
12
8
100
80
60
40
20
0
V
= 12V
OUT
(ADJUSTABLE)
WITH 0.1µF ACROSS
DIVIDER RESISTOR
V
= 5V
OUT
(FIXED)
V
IN
– V
T = 25°C
J
= 2V
OUT
POWER
TRANSISTOR
IN DROPOUT
V
= 12V
OUT
(ADJUSTABLE)
T = –55°C
J
T = 25°C
J
4
I
= 100mA
OUT
V
IN
– V
OUT
= 2V
V
– V
OUT
≥ 3V
IN
C
OUT
= 1µF TANT
T = 25°C
J
0
10
100
1k
10k
100k
1M
0
0.2 0.3 0.4
0.5 0.6 0.7
0.1
FREQUENCY (Hz)
OUTPUT CURRENT (A)
1175 G10
RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF
INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN
25mA AND 500mA. LARGER OUTPUT CAPACITORS DO
NOT IMPROVE REJECTION FOR FREQUENCIES BELOW
50kHz. AT VERY LIGHT LOADS, REJECTION WILL
1175 G11
IMPROVE WITH LARGER OUTPUT CAPACITORS
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PIN FUNCTIONS
microamperes of current (see Typical Performance Char-
acteristics). Maximum voltage on the SHDN pin is 15V,
–20V with respect to the GND pin and 35V, –5V with
respect to the negative input pin.
SENSE Pin: The SENSE pin is used in the adjustable
version to allow custom selection of output voltage, with
an external divider set to generate 3.8V at the SENSE pin.
Input bias current is typically 75nA flowing out of the pin.
MaximumforcedvoltageontheSENSEpinis 2Vand–10V
with respect to GND pin.
ILIM Pins: The two current limit pins are emitter sections
of the power transistor. When left open, they float several
hundred millivolts above the negative input voltage. When
shorted to the input voltage, they increase current limit by
aminimumof200mAforILIM2 and400mAforILIM4.These
pins must be connected only to the input voltage, either
directly or through a resistor.
The fixed 5V version utilizes the SENSE pin to give true
Kelvin connections to the load or to drive an external pass
transistor for higher output currents. Bias current out of
the 5V SENSE pin is approximately 12µA. Separating the
SENSE and OUTPUT pins also allows for a new loop
compensation technique described in the Applications
Information section.
OUTPUT Pin: The OUTPUT pin is the collector of the NPN
power transistor. It can be forced to the input voltage, to
groundorupto2Vpositivewithrespecttogroundwithout
damage or latchup (see Output Voltage Reversal in Appli-
cations Information section). The LT1175 has foldback
current limit, so maximum current at the OUTPUT pin is a
function of input-to-output voltage. See Typical Perfor-
mance Characteristics.
SHDN Pin: The SHDN pin is specially configured to allow
it to be driven from either positive voltage logic or with
negative only logic. Forcing the SHDN pin 2V either above
orbelowtheGNDpinwillturntheregulatoron.This makes
it simple to connect directly to positive logic signals for
active low shutdown. If no positive voltages are available,
the SHDN pin can be driven below the GND pin to turn the
regulatoron.Whenleftopen, theSHDNpinwilldefaultlow
to a regulator “on” condition. For all voltages below
absolutemaximumratings,theSHDNpindraws onlyafew
GND Pin: The GND pin has a quiescent current of 45µA at
zero load current, increasing by approximately 10µA per
mA of output current. At 500mA output current, GND pin
current is about 5mA. Current flows into the GND pin.
5
LT1175
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APPLICATIONS INFORMATION
The LT1175-5 is a fixed 5V design with the SENSE pin
acting as a Kelvin connection to the output. Normally the
SENSE pin and the OUTPUT pin are connected directly
together, either close to the regulator or at the remote load
point.
Note to Reader: To avoid confusion when working with
negativevoltages (is –6Vmoreorless than–5V?), Ihave
decided to treat the LT1175 as if it were a positive
regulatorandexpress allvoltages as positivevalues,both
intextandinformulas. Ifyoudothesameandsimplyadd
a negative sign to the eventual answer, confusion should
be avoided. Please don’t give me a hard time about
“preciseness”or“correctness.”Ihavetofieldphonecalls
from around the world and this is my way of dealing with
a multitude of conventions. Thanks for your patience.
SHUTDOWN
LOGIC
> 2V OR < –2V TO
TURN REGULATOR ON
+
+
R1
383k
C
IN
1%
SHDN
INPUT
GND
SENSE
C
OUT
≥ 0.1µF
R2
825k
1%
LT1175-5
I
LIM2
Setting Output Voltage
V
–12V
OUT
I
OUT
LIM4
The LT1175 adjustable version has a feedback sense
voltage of 3.8V with a bias current of approximately 75nA
flowing out of the SENSE pin. To avoid output voltage
errors caused by this current, the output divider string
(see Figure 1) should draw about 25µA. Table 1 shows
suggested resistor values for a range of output voltages.
The second part of the table shows resistor values which
draw only 10µA of current. Output voltage error caused by
bias current with the lower valued resistors is about 0.4%
maximum and with the higher values, about 1% maxi-
mum. Aformulais alsoshownforcalculatingtheresistors
for any output voltage.
1175 F01
Figure 1. Typical LT1175 Adjustable Connection
Setting Current Limit
TheLT1175uses twoILIM pins tosetcurrentlimit(typical)
at 200mA, 400mA, 600mA or 800mA. The corresponding
minimumguaranteedcurrents are130mA,260mA,390mA
and 520mA. This allows the user to select a current limit
tailored to his specific application and prevents the situa-
tion where short-circuit current is many times higher than
full-load current. Problems with input supply overload or
excessive power dissipation in a faulted load are pre-
vented. Powerlimitingintheformoffoldbackcurrentlimit
is built in and reduces current limit as a function of input-
to-output voltage differential for differentials exceeding
14V. SeethegraphinTypicalPerformanceCharacteristics.
The LT1175 is guaranteed to be blowout-proof regardless
of current limit setting. The power limiting combined with
thermal shutdown protects the device from destructive
junction temperatures under all load conditions.
Table 1
OUTPUT
R1
R2
R1
R2
VOLTAGE
I
DIV
= 25µA
NEAREST 1%
I
DIV
= 10µA
NEAREST 1%
5V
6V
150k
150k
150k
150k
150k
150k
47.5k
86.6k
165k
243k
324k
442k
383k
383k
383k
383k
383k
383k
121k
221k
422k
619k
825k
1.13M
8V
10V
12V
15V
Shutdown
3.8V
IDIV
R1=
In shutdown, the LT1175 draws only about 10µA. Special
circuitry is used to minimize increases in shutdown cur-
rent at high temperatures, but a slight increase is seen
above 125°C. One option not taken was to actively pull
down on the output during shutdown. This means that the
output will fall slowly after shutdown is initiated, at a rate
determined by load current plus the 12µA internal load,
and the size of the output capacitor. Active pull-down is
R1 V − 3.8V
(
)
OUT
R2 =
R2 =
Simple formula
(
)
3.8V
R1 V − 3.8V
(
)
OUT
Taking SENSE pin bias
current into account
3.8V+R1 I
( FB)
IDIV = Desired divider current
6
LT1175
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APPLICATIONS INFORMATION
yet allows the power transistor to approach its theoretical
saturation limit.
normally a good thing when the regulator is used by itself,
but it prevents the user from shutting down the regulator
when a second power source is connected to the LT1175
output. If active output pull-down is needed in shutdown,
it can be added externally with a depletion mode PFET as
shown in Figure 2. Note that the maximum pinch-off
voltage of the PFET must be less than the positive logic
high level to ensure that the device is completely off when
the regulator is active. The Motorola J177 device has
300Ω on resistance for zero gate source voltage.
Output Capacitor
Severalnewregulatordesigntechniques areusedtomake
the LT1175 extremely tolerant of output capacitor selec-
tion. Like most low dropout designs which use a collector
or drain of the power transistor to drive the output node,
the LT1175 uses the output capacitor as part of the overall
loop compensation. Older regulators generally required
the output capacitor to have a minimum value of 1µF to
100µF, a maximum ESR (Effective Series Resistance) of
0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to
0.3Ω. These restrictions usually could be met only with
good quality solid tantalum capacitors. Aluminum capaci-
tors have problems with high ESR unless much higher
values of capacitance are used (physically large). The ESR
of ceramic or film capacitors was too low, which made the
capacitance/ESR zero frequency too high to maintain
phase margin in the regulator. Even with optimum capaci-
tors, loop phase margin was very low in previous designs
whenoutputcurrentwas low.Theseproblems ledtoanew
design technique for the LT1175 error amplifier and inter-
nal frequency compensation as shown in Figure 3.
3V TO 5V
s
+
Q1*
d
C
OUT
SHDN
INPUT
GND
SENSE
≥ 0.1µF
–V
IN
LT1175-5
OUT
I
LIM2
I
LIM4
* MOTOROLA J177
PINCH-OFF VOLTAGE MUST BE LESS THAN
POSITIVE LOGIC HIGH VOLTAGE
1175 F02
Figure 2. Active Output Pull-Down During Shutdown
A conventional regulator loop consists of error amplifier
A1, drivertransistorQ2andpowertransistorQ1. Addedto
this basic loop are secondary loops generated by Q3 and
CF. A DC negative feedback current fed into the error
amplifier through Q3 and RN causes overall loop current
gain to be very low at light load currents. This is not a
problem because very little gain is needed at light loads. In
addition to low gain, the parasitic pole frequency at Q2
base is extended by the DC feedback. The combination of
these two effects dramatically improves loop phase mar-
gin at light loads and makes the loop tolerant of large ESR
in the output capacitor. With heavy loads, loop phase and
gain are not nearly as troublesome and large negative
feedbackcoulddegraderegulation.Thelogarithmicbehav-
ior of the base emitter voltage of Q1 reduces Q3 negative
feedback at heavy loads to prevent poor regulation.
Minimum Dropout Voltage
Dropoutvoltageis theminimumvoltagerequiredbetween
input and output to maintain proper output regulation. For
older 3-terminal regulator designs, dropout voltage was
typically 1.5V to 3V. The LT1175 uses a saturating power
transistor design which gives much lower dropout volt-
age, typically 100mV at light loads and 450mV at full load.
Special precautions were taken to ensure that this tech-
nique does not cause quiescent supply current to be high
under light load conditions. When the regulator input
voltage is too low to maintain a regulated output, the pass
transistor is driven hard by the error amplifier as it tries to
maintain regulation. The current drawn by the driver
transistor could be tens of milliamperes even with little or
no load on the output. This indeed was the case for older
IC designs that did not actively limit driver current when
the power transistor saturated. The LT1175 uses a new
antisaturation technique that prevents high driver current,
In a conventional design, even with the nonlinear feed-
back, poor loop phase margin would occur at medium to
heavy loads if the ESR of the output capacitor fell below
7
LT1175
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APPLICATIONS INFORMATION
GND
LT1175
+
3.8V
R1
R2
–
C
OUT
A1
+
LOAD
ESR
SENSE
OUT
Q2
AC
FEEDFORWARD
C
F
PATH
20pF
OUTPUT
R
C
0.5Ω
NEGATIVE DC
FEEDBACK
AT LIGHT
LOADS
PARASITIC
COLLECTOR
RESISTANCE
Q3
Q1
POWER
TRANSISTOR
R
N
R
LIM
CURRENT LIMIT
SENSE RESISTOR
1175 F03
–V
IN
Figure 3
The end result of all this attention to loop stability is that
the output capacitor used with the LT1175 can range in
value from 0.1µF to hundreds of microfarads, with an ESR
from 0Ω to 10Ω. This range allows the use of ceramic,
solid tantalum, aluminum and film capacitors over a wide
range of values.
0.3Ω. This condition can occur with ceramic or film
capacitors which often have an ESR under 0.1Ω. With
previous designs,theuserwas forcedtoaddarealresistor
in series with the capacitor to guarantee loop stability. The
LT1175 uses a unique AC feedforward technique to elimi-
nate this problem. CF is a conventional feedforward ca-
pacitor often used in regulators to cancel the pole formed
by the output capacitor. It would normally be connected
fromtheregulatedoutputnodetothefeedbacknodeatthe
R1/R2 junction or to an internal node on the amplifier as
shown. In this case, however, the capacitor is connected
to the internal structure of the power transistor. RC is the
unavoidable parasitic collector resistance of the power
transistor. Access to the node at the bottom of RC is
available only in monolithic structures where Kelvin con-
nections can be made to the NPN buried collector layer.
The loop now responds as if RC were in series with the
output capacitor and good loop stability is achieved even
with extremely low ESR in the output capacitor.
The optimum output capacitor type for the LT1175 is still
solid tantalum, but there is considerable leeway in select-
ing the exact unit. If large load current transients are
expected,largercapacitors withlowerESRmaybeneeded
tocontrolworst-caseoutputvariationduringtransients. If
transients arenotanissue,thecapacitorcanbechosenfor
small physical size, low price, etc. Concerns about surge
currents in tantalum capacitors are not an issue for the
outputcapacitorbecausetheLT1175limits inrushcurrent
to well below the level which can cause capacitor damage.
Surges caused by shorting the regulator output are also
not a problem because tantalum capacitors do not fail
8
LT1175
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APPLICATIONS INFORMATION
high. If a 4.8V output is pulled to 5V, for instance, the load
on the primary regulator would be (5V – 4.8V)/2kΩ =
100µA. This also means that if the internal pass transistor
leaks 50µA, the output voltage will be (50µA)(2kΩ) =
100mV high. This condition will not occur under normal
operating conditions, but could occur immediately after
an output short circuit had overheated the chip.
during a “shorting out” surge, only during a “charge up”
surge.
The output capacitor should be located within several
inches of the regulator. If remote sensing is used, the
output capacitor can be located at the remote sense node,
but the GND pin of the regulator should also be connected
to the remote site. The basic rule is to keep SENSE and
GND pins close to the output capacitor, regardless of
where it is.
Thermal Considerations
The LT1175 is available in a special 8-pin surface mount
packagewhichhas Pins 1and8connectedtothedieattach
paddle. This reduces thermal resistance when Pins 1 and
8 are connected to expanded copper lands on the PC
board. Table 2 shows thermal resistance for various
combinations of copper lands and backside or internal
planes.Table2alsoshows thermalresistanceforthe5-pin
DDsurfacemountpackageandthe8-pinDIPandpackage.
Operating at very large input-to-output differential volt-
ages (>5V) with load currents less than 5mA requires an
output capacitor with an ESR greater than 1Ω to prevent
low level output oscillations.
Input Capacitor
The LT1175 requires a separate input bypass capacitor
only if the regulator is located more than six inches from
the raw supply output capacitor. A 1µF or larger tantalum
capacitor is suggested for all applications, but if low ESR
capacitors such as ceramic or film are used for the output
and inputcapacitors,theinputcapacitorshouldbeatleast
three times the value of the output capacitor. If a solid
tantalum or aluminum electrolytic output capacitor is
used, the input capacitor is very noncritical.
Table 2. Package Thermal Resistance (°C/W)
LAND AREA
DIP
140
110
ST
90
70
SO
100
80
Q
60
50
Minimum
Minimum with
Backplane
2
1cm Top Plane
100
80
64
50
75
60
35
27
with Backplane
2
10cm Top Plane
with Backplane
High Temperature Operation
The LT1175 is a micropower design with only 45µA
quiescent current. This could make it perform poorly at
hightemperatures (>125°C),wherepowertransistorleak-
age might exceed the output node loading current (5µA to
15µA).Toavoidaconditionwheretheoutputvoltagedrifts
uncontrolled high during a high temperature no-load
condition, the LT1175 has an active load which turns on
when the output is pulled above the nominal regulated
voltage. This load absorbs power transistor leakage and
maintains good regulation. There is one downside to this
feature, however. If the output is pulled high deliberately,
as it might be when the LT1175 is used as a backup to a
slightlyhigheroutputfromaprimaryregulator,theLT1175
will act as an unwanted load on the primary regulator.
Becauseofthis,theactivepull-downis deliberately“weak.”
It can be modeled as a 2k resistor in series with an internal
clamp voltage when the regulator output is being pulled
Tocalculatedietemperature,maximumpowerdissipation
or maximum input voltage, use the following formulas
withcorrectthermalresistancenumbers fromTable2. For
through-hole TO-220 applications use θJA = 50°C/W
without a heat sink and θJA = 5°C/W + heat sink thermal
resistance when using a heat sink.
Die Temp = T + θJA V − V
I
(
OUT)( LOAD
)
A
IN
TMAX − T
A
Maximum Power Dissipation =
θJA
MAX − T
Maximum Input Voltage
for Thermal Considerations
T
A
=
+ V
OUT
θJA LOAD
I
(
)
9
LT1175
U
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APPLICATIONS INFORMATION
TA = Maximum ambient temperature
NPN power transistor structure that has a parasitic diode
between the input and output of the regulator. Reverse
voltages between input and output above 1V will damage
the regulator if large currents are allowed to flow. Simply
disconnectingtheinputsourcewiththeoutputheldupwill
not cause damage even though the input-to-output volt-
age will become slightly reversed.
TMAX = Maximum LT1175 die temperature (125°C for
commercial and industrial grades)
θJA = LT1175 thermal resistance, junction to ambient
V
IN
= Maximum continuous input voltage at maximum
load current
ILOAD = Maximum load current
High Frequency Ripple Rejection
Example: LT1175S8 with ILOAD = 200mA, VOUT = 5V,
The LT1175 will sometimes be powered from switching
regulators that generate the unregulated or quasi-regu-
lated input voltage. This voltage will contain high fre-
quency ripple that must be rejected by the linear regulator.
Special care was taken with the LT1175 to maximize high
frequency ripple rejection, but as with any micropower
design, rejection is strongly affected by ripple frequency.
The graph in the Typical Performance Characteristics
section shows 60dB rejection at 1kHz, but only 15dB
rejectionat100kHzforthe5Vpart.Photographs inFigures
4a and 4b show actual output ripple waveforms with
square wave and triwave input ripple.
V = 7V, TA = 60°C. Maximum die temperature for the
IN
LT1175S8 is 125°C. Thermal resistance from Table 2 is
found to be 80°C/W.
Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C
125 – 60
Maximum Power Dissipation =
= 0.81W
+ 5 = 9V
80
125 – 60
Maximum Continuous
Input Voltage
=
80 0.2
(
)
(for Thermal Considerations)
Output Voltage Reversal
The LT1175 is designed to tolerate an output voltage
reversal of up to 2V. Reversal might occur, for instance, if
the output was shorted to a positive 5V supply. This would
almostsurelydestroyICdevices connectedtothenegative
output. Reversal could also occur during start-up if the
positive supply came up first and loads were connected
between the positive and negative supplies. For these
reasons, it is always good design practice to add a reverse
biased diode from each regulator output to ground to limit
output voltage reversal. The diode should be rated to
handle full negative load current for start-up situations, or
theshort-circuitcurrentofthepositivesupplyifsupply-to-
supply shorts must be tolerated.
COUT = 4.7µF TANT
OUTPUT
20mV/DIV
COUT = 1µF TANT
INPUT
RIPPLE
100mV/DIV
f = 50kHz
5µs/DIV
1175 F04
Figure 4a.
COUT = 4.7µF TANT
COUT = 1µF TANT
OUTPUT
100mV/DIV
Input Voltage Lower Than Output
Linear Technology’s positive low dropout regulators
LT1121 and LT1129, will not draw large currents if the
input voltage is less than the output. These devices use a
lateralPNPpowertransistorstructurethathas 40Vemitter
base breakdown voltage. The LT1175, however, uses an
INPUT
RIPPLE
100mV/DIV
f = 100kHz
2µs/DIV
1175 F04
Figure 4b.
10
LT1175
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APPLICATIONS INFORMATION
To estimate regulator output ripple under different condi-
tions, the following general comments should be helpful:
to save space. At heavier loads an inductor may have to be
used in place of the resistor. The value of the inductor can
be calculated from:
1. Output ripple at high frequency is only weakly affected
by load current or output capacitor size for medium to
heavy loads. At very light loads (<10mA), higher fre-
quency ripple may be reduced by using larger output
capacitors.
ESR
L
=
FIL
rr / 20
10
2π f
( )
ESR = Effective series resistance of filter capacitor. This
assumes that the capacitive reactance is small
compared to ESR, a reasonable assumption for
solid tantalum capacitors above 2.2µF and 50kHz.
2. A feedforward capacitor across the resistor divider
used with the adjustable part is effective in reducing
rippleonlyforoutputvoltages greaterthan5Vandonly
for frequencies less than 100kHz.
f
= Ripple frequency
3. Input-to-output voltage differential has little effect on
ripple rejection until the regulator actually enters a
dropout condition of 0.2V to 0.6V.
rr = Ripple rejection ratio of filter in dB
Example: ESR = 1.2Ω, f = 100kHz, rr = –25dB.
If ripple rejection needs to be improved, an input filter can
be added. This filter can be a simple RC filter using a 1Ω
to 10Ω resistor. A 3.3Ω resistor for instance, combined
with a 0.3Ω ESR solid tantalum capacitor, will give an
additional 20dB ripple rejection. The size of the resistor
will be dictated by maximum load current. If the maximum
voltage drop allowable across the resistor is “VR,” and
maximum load current is ILOAD, R = VR/ILOAD. At light
loads, larger resistors and smaller capacitors can be used
1.2
L
=
= 34µH
FIL
5
−25/ 20
10
6.3 10
Solid tantalum capacitors are suggested for the filter to
keep filter Q fairly low. This prevents unwanted ringing at
the resonant frequency of the filter and oscillation prob-
lems with the filter/regulator combination.
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
Q Package
5-Lead Plastic DD Pak
(LTC DWG # 05-08-1461)
0.060
0.390 – 0.415
(9.906 – 10.541)
(1.524)
TYP
0.060
(1.524)
0.165 – 0.180
(4.191 – 4.572)
0.256
(6.502)
0.045 – 0.055
(1.143 – 1.397)
15° TYP
+0.008
0.004
–0.004
0.060
(1.524)
0.183
(4.648)
0.059
(1.499)
TYP
0.330 – 0.370
(8.382 – 9.398)
+0.203
0.102
(
)
–0.102
0.095 – 0.115
(2.413 – 2.921)
0.075
(1.905)
0.057 – 0.077
(1.447 – 1.955)
0.050 ± 0.012
(1.270 ± 0.305)
0.300
(7.620)
0.013 – 0.023
(0.330 – 0.584)
+0.012
0.143
–0.020
0.028 – 0.038
(0.711 – 0.965)
+0.305
3.632
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
(
)
–0.508
Q(DD5) 0396
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
11
LT1175
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
S8 Package
8-Lead PDIP (Narrow 0.300)
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1510)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.400*
(10.160)
MAX
7
5
8
6
8
7
6
5
0.255 ± 0.015*
(6.477 ± 0.381)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
2
4
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(1.143 – 1.651)
1
0.053 – 0.069
(1.346 – 1.752)
2
3
4
(3.302 ± 0.127)
0.010 – 0.020
(0.254 – 0.508)
(7.620 – 8.255)
× 45°
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.065
(1.651)
TYP
0.009 – 0.015
0.016 – 0.050
0.406 – 1.270
0.125
(0.229 – 0.381)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.020
(3.175)
MIN
+0.035
–0.015
(0.508)
MIN
0.325
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.100 ± 0.010
0.018 ± 0.003
+0.889
–0.381
8.255
(
)
(2.540 ± 0.254)
(0.457 ± 0.076)
N8 1197
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.248 – 0.264
(6.30 – 6.71)
ST Package
3-Lead Plastic SOT-223
0.116 – 0.124
(2.95 – 3.15)
(LTC DWG # 05-08-1630)
10° – 16°
0.010 – 0.014
0.264 – 0.287
(6.71 – 7.29)
10°
MAX
0.071
(1.80)
MAX
(0.25 – 0.36)
0.130 – 0.146
(3.30 – 3.71)
10° – 16°
0.0008 – 0.0040
0.012
(0.31)
0.025 – 0.033
(0.64 – 0.84)
(0.0203 – 0.1016)
MIN
0.181
(4.60)
NOM
T Package
5-Lead Plastic TO-220 (Standard)
0.033 – 0.041
(0.84 – 1.04)
0.090
(2.29)
NOM
(LTC DWG # 05-08-1421)
ST3 (SOT-233) 0792
0.165 – 0.180
(4.191 – 4.572)
0.147 – 0.155
(3.734 – 3.937)
DIA
0.390 – 0.415
(9.906 – 10.541)
0.045 – 0.055
(1.143 – 1.397)
RELATED PARTS
LT1121 150mA Positive Micropower Low Dropout
0.230 – 0.270
(5.842 – 6.858)
0.570 – 0.620
(14.478 – 15.748)
0.620
(15.75)
TYP
0.460 – 0.500
(11.684 – 12.700)
Regulator with Shutdown
0.330 – 0.370
(8.382 – 9.398)
0.700 – 0.728
(17.78 – 18.491)
LT1129 700mA Positive Micropower Low Dropout
Regulator with Shutdown
LT1185 3A Negative Low Dropout Regulator
LT1521 300mA Positive Micropower Low Dropout
Regulator with Shutdown
0.095 – 0.115
(2.413 – 2.921)
0.152 – 0.202
(3.861 – 5.131)
0.260 – 0.320
(6.60 – 8.13)
LT1529 3A Positive Micropower Low Dropout
Regulator with Shutdown
0.013 – 0.023
(0.330 – 0.584)
0.057 – 0.077
(1.448 – 1.956)
0.135 – 0.165
(3.429 – 4.191)
0.155 – 0.195
0.028 – 0.038
(0.711 – 0.965)
(3.937 – 4.953)
T5 (TO-220) 0398
1175fc LT/TP 0399 2K REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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