LT1185CQ_技术文档

LT1185

Low Dropout Regulator

FEATURES

■

The LT1185 uses a saturation-limited NPN transistor as

the pass element. This device gives the linear dropout

characteristics of a FET pass element with significantly

lessdiearea.Highefficiencyismaintainedbyusingspecial

anti-saturation circuitry that adjusts base drive to track

load current. The “on resistance” is typically 0.25Ω.

Low Resistance Pass Transistor: 0.25

Ω

■

Dropout Voltage: 0.75V at 3A

■

±

1% Reference Voltage

Accurate Programmable Current Limit

Shutdown Capability

■

Internal Reference Available

Full Remote Sense

Accurate current limit is programmed with a single 1/8W

external resistor, with a range of zero to three amperes. A

second, fixed internal limit circuit prevents destructive

currents if the programming current is accidentally over-

ranged. Shutdown of the regulator output is guaranteed

when the program current is less than 1µA, allowing

external logic control of output voltage.

Low Quiescent Current: 2.5mA

Good High Frequency Ripple Rejection

Available in 5-Lead TO-220 and DD Packages

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DESCRIPTIO

TheLT^®1185isa3Alowdropoutregulatorwithadjustable

currentlimitandremotesensecapability. Itcanbeusedas

a positive output regulator with floating input or as a

standard negative regulator with grounded input. The

outputvoltagerangeis2.5Vto25V,with±1%accuracyon

the internal reference voltage.

The LT1185 has all the protection features of previous

LTC regulators, including power limiting and thermal

shutdown.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

Dropout Voltage

5V, 3A Regulator with 3.5A Current Limit

1.6

1.4

1.2

1.0

+

2µF

TANT

R

*

LIM

4.3k

2.37k

V

IN

6V TO 16V

REF

GND

+

V

OUT

5V AT 3A

2µF

TANT

FB

T

= 25°C

J

0.8

0.6

0.4

0.2

0

T

1

= 125°C

J

V

LT1185

2.67k

–

IN

V

–

OUT

LT1185 • TA01

T

= –55°C

J

*CURRENT LIMIT = 15k/R

LIM

= 3.5A

2

0

3

4

LOAD CURRENT (A)

LT1185 • TA02

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1

LT1185

ABSOLUTE AXI U RATI GS

Input Voltage .......................................................... 35V

Input-Output Differential ......................................... 30V

FB Voltage ................................................................ 7V

REF Voltage .............................................................. 7V

Output Voltage........................................................ 30V

Output Reverse Voltage ............................................ 2V

Operating Ambient Temperature Range

W W U W

(Note 1)

Operating Junction Temperature Range*

Control Section

LT1185C ............................................. 0°C to 125°C

LT1185I .......................................... –40°C to 125°C

LT1185M (OBSOLETE) ................... –55°C to 150°C

Power Transistor Section

LT1185C ............................................. 0°C to 150°C

LT1185I .......................................... –40°C to 150°C

LT1185M (OBSOLETE) ................... –55°C to 175°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

LT1185C ............................................... 0°C to 70°C

LT1185I ............................................. –40°C to 85°C

LT1185M (OBSOLETE) .................... –55°C to 125°C

*See Application Section for details on calculating Operation Junction Temperature

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PACKAGE/ORDER I FOR ATIO

BOTTOM VIEW

GND

FB

FRONT VIEW

5

4

3

2

1

REF

5

4

3

2

1

REF

1

4

2

V

OUT

V

IN

V

OUT

IN

TAB

IS

IN

V

IN

(CASE)

3

V

FB

GND

V

REF

OUT

Q PACKAGE

5-LEAD PLASTIC DD

TAB IS V

T PACKAGE

5-LEAD PLASTIC TO-220

IN

K PACKAGE

4-LEAD TO-3 METAL CAN

θ_{JC MAX}= 2.5°C/W, θ_JA= 35°C/W

T_JMAX= 150°C, θ_JA= 30°C/W

θ

_{JC MAX}= 2.5°C/W, θ_JA= 50°C/W

OBSOLETE PACKAGE

ORDER PART

NUMBER

ORDER PART

NUMBER

LT1185CQ

LT1185IQ

ORDER PART

NUMBER

LT1185CT

LT1185IT

LT1185MK

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at T_A= 25°C.

Adjustable version, V_IN= 7.4V, V_OUT= 5V, I_OUT= 1mA, R_LIM= 4.02k, unless otherwise noted.

PARAMETER

Reference Voltage (At FB Pin)

CONDITIONS

– V = 5V, V

MIN

TYP

2.37

0.3

1

MAX

UNITS

V

%

Reference Voltage Tolerance (At FB Pin) (Note 2)

V

= V

REF

±1

IN

OUT

1mA ≤ I

≤ 3A

●

±2.5

OUT

V

– V

= 1.2V to V = 30V

IN

OUT IN

P ≤ 25W (Note 6), V

= 5V

OUT

T

≤ T ≤ T

(Note 9)

MIN

J

MAX

Feedback Pin Bias Current

Droput Voltage (Note 3)

V

= V

0.7

2

µA

OUT

REF

I

= 0.5A, V

= 5V

0.20

0.67

0.37

1.00

V

OUT

= 3A, V

OUT

1185ff

2

LT1185

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at T_A= 25°C.

Adjustable version, V_IN= 7.4V, V_OUT= 5V, I_OUT= 1mA, R_LIM= 4.02k, unless otherwise noted.

PARAMETER

Load Regulation (Note 7)

CONDITIONS

= 5mA to 3A

MIN

TYP

0.05

MAX

0.3

UNITS

I

%

OUT

V

– V

= 1.5V to 10V, V

= 5V

OUT

IN

OUT

Line Regulation (Note 7)

Minimum Input Voltage

V

– V

= 1V to 20V, V

= 5V

0.002

0.01

%/V

IN

OUT

I

= 1A (Note 4), V

= 3A

= V

REF

4.0

4.3

V

OUT

Internal Current Limit (See Graph for

Guaranteed Curve) (Note 12)

1.5V ≤ V – V

≤ 10V

3.3

3.1

2.0

1.0

0.2

3.6

4.2

4.4

4.2

2.6

1.0

A

IN

OUT

●

V

IN

V

IN

V

IN

– V

= 15V

= 20V

= 30V

3.0

1.7

0.4

OUT

External Current Limit

Programming Constant

5k ≤ R ≤ 15k, V

= 1V

●

15k

A•Ω

LIM

(Note 11)

OUT

External Current Limit Error

Quiescent Supply Current

Supply Current Change with Load

REF Pin Shutoff Current

1A ≤ I ≤ 3A

LIM

0.02 I

0.06 I + 0.03

A

LIM

= 15k • A/I

LIM

R

●

0.04 I

0.09 I + 0.05

LIM

I

= 5mA, V

= V

REF

2.5

3.5

mA

OUT

4V ≤ V ≤ 25V (Note 5)

IN

V

IN

V

IN

– V

= V (Note 10)

SAT

≥ 2V

●

25

10

40

25

mA/A

OUT

●

0.4

2

7

µA

Thermal Regulation (See Applications

Information)

V

OUT

– V

= 10V

0.005

0.014

%/W

IN

OUT

= 5mA to 2A

I

Reference Voltage Temperature Coefficient

Thermal Resistance Junction to Case

(Note 8)

0.003

0.01

%/°C

TO-3 Control Area

Power Transistor

TO-220 Control Area

Power Transistor

1

3

1

3

°C/W

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: The 25W power level is guaranteed for an input-output voltage of

8.3V to 17V. At lower voltages the 3A limit applies, and at higher voltages

the internal power limiting may restrict regulator power below 25W. See

graphs.

Note 7: Line and load regulation are measured on a pulse basis with a

pulse width of ≈2ms, to minimize heating. DC regulation will be affected

by thermal regulation and temperature coefficient of the reference. See

Applications Information section for details.

Note 8: Guaranteed by design and correlation to other tests, but not

tested.

Note 2: Reference voltage is guaranteed both at nominal conditions (no

load, 25°C) and at worst-case conditions of load, line, power and

temperature. An intermediate value can be calculated by adding the effects

of these variables in the actual application. See the Applications

Information section of this data sheet.

Note 3: Dropout voltage is tested by reducing input voltage until the

output drops 1% below its nominal value. Tests are done at 0.5A and 3A.

The power transistor looks basically like a pure resistance in this range so

that minimum differential at any intermediate current can be calculated by

Note 9: T

= 0°C for the LT1185C, –40°C for LT1185I, and –55°C for

JMIN

the LT1185M. Power transistor area and control circuit area have different

maximum junction temperatures. Control area limits are T = 125°C for

JMAX

interpolation; V

0.5A, see graph.

= 0.25V + 0.25Ω • I . For load current less than

the LT1185C and LT1185I and 150°C for the LT1185M. Power area limits

are 150°C for LT1185C and LT1185I and 175°C for LT1185M.

DROPOUT

OUT

Note 4: “Minimum input voltage” is limited by base emitter voltage drive

of the power transistor section, not saturation as measured in Note 3. For

output voltages below 4V, “minimum input voltage” specification may limit

dropout voltage before transistor saturation limitation.

Note 10: V

0.25V + 0.25 • I

is the maximum specified dropout voltage;

SAT

.

OUT

Note 11: Current limit is programmed with a resistor from REF pin to GND

pin. The value is 15k/I

Note 12: For V – V

.

LIM

Note 5: Supply current is measured on the ground pin, and does not

= 1.5V; V = 5V, V

= 3.5V. V

= 1V for all

IN

OUT

IN

OUT

include load current, R , or output divider current.

other current limit tests.

LIM

1185ff

3

LT1185

TYPICAL PERFOR A CE CHARACTERISTICS

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Feedback Pin Voltage

Temperature Drift

Quiescent Ground Pin Current*

Internal Current Limit

12

10

8

5

2.41

2.40

2.39

2.38

2.37

2.36

2.35

2.34

2.33

I

= 0

LOAD

T_J= 25°C

4

3

GUARANTEED

LIMIT

*DOES NOT INCLUDE REF CURRENT

OR OUTPUT DIVIDER CURRENT

6

TYPICAL

2

4

2

0

V

= 5V

15

OUT

GUARANTEED

LIMIT

1

0

TEST POINTS

50 75

–50 –25

JUNCTION TEMPERATURE (°C)

0

25

100 125 150

20

30

35

0

5

10

25

0

5

15

20

25

30

10

INPUT VOLTAGE (V)

INPUT-OUTPUT DIFFERENTIAL (V)

LT1185 • TPC03

LT1185 • TPC02

LT1185 • TPC01

Ground Pin Current

Ripple Rejection vs Frequency

–100

–80

–60

–40

–20

0

160

140

120

100

80

T

= 25°C

J

ALL OUTPUT

VOLTAGES

WITH 0.05µF

ACROSS R2

REGULATOR JUST AT

DROPOUT POINT

60

V

OUT

= 5V

OUT

V

IN

– V

= 1.5V

40

V

– V

= 5V

IN

OUT

20

0

2

0

1

3

4

100

1k

10k

100k

1M

FREQUENCY (Hz)

LOAD CURRENT (A)

LT1185 • TPC05

LT1185 • TPC04

Load Transient Response

Output Impedance

10

1

OUTPUT IMPEDANCE IS

SET BY OUTPUT CAPACITOR

ESR IN THIS REGION

C

= 2.2µF, ESR = 1Ω

OUT

100mV

C

= 2.2µF, ESR = 2Ω

OUT

0.1

V

= 5V

= 1A

OUT

I

0.01

V

= 5V

OUT

∆I

0.1A t , ≤ 100ns

LOAD

r f

I

= 1A

C

OUT

= 2.2µF

0.001

0

8

12 14

2

4

6

10

16

1k

10k

100k

1M

TIME (µs)

FREQUENCY (Hz)

LT1183 • TPC07

LT1185 • TPC06

1185ff

4

LT1185

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APPLICATIO S I FOR ATIO

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Block Diagram

conditions, resulting in very high supply current when the

input voltage is low. To avoid this situation, the LT1185

uses an auxiliary emitter on Q3 to create a drive limiting

feedback loop which automatically adjusts the drive to Q1

so that the base drive to Q3 is just enough to saturate Q3,

but no more. Under saturation conditions, the auxiliary

emitter is acting like a collector to shunt away the output

current of A1. When the input voltage is high enough to

keep Q3 out of saturation, the auxiliary emitter current

dropstozeroevenwhenQ3isconductingfullloadcurrent.

A simplified block diagram of the LT1185 is shown in

Figure 1. A 2.37V bandgap reference is used to bias the

input of the error amplifier A1, and the reference amplifier

A2. A1 feeds a triple NPN pass transistor stage which has

the two driver collectors tied to ground so that the main

pass transistor can completely saturate. This topology

normally has a problem with unlimited current in Q1 and

Q2 when the input voltage is less than the minimum

required to create a regulated output. The standard “fix”

for this problem is to insert a resistor in series with Q1 and

Q2 collectors, but this resistor must be low enough in

value to supply full base current for Q3 under worst-case

GND

R

LIM

(EXTERNAL)

V

REF

2.37V

REF

FB

+

–

+

A1

A2

Q4

V

OUT

Q1

D2

D4

D3

Q2

Q3

A5

A4

R1

A3

+

–

D1

I1

2µA

R2

0.055Ω

300mV

200mV

350Ω

V

IN

LT1185 • BD

Figure 1. Block Diagram

1185ff

5

LT1185

W U U

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APPLICATIO S I FOR ATIO

AmplifierA2isusedtogenerateaninternalcurrentthrough

Q4 when an external resistor is connected from the REF

pin to ground. This current is equal to 2.37V divided by

Output Capacitor

The LT1185 has a collector output NPN pass transistor,

which makes the open-loop output impedance much

higher than an emitter follower. Open-loop gain is a direct

function of load impedance, and causes a main-loop

“pole” to be created by the output capacitor, in addition to

an internal pole in the error amplifier. To ensure loop

stability, theoutputcapacitormusthaveanESR(effective

series resistance) which has an upper limit of 2Ω, and a

lower limit of 0.2 divided by the capacitance in µF. A 2µF

output capacitor, for instance, should have a maximum

ESR of 2Ω, and a minimum of 0.2/2 = 0.1Ω. These values

are easily encompassed by standard solid tantalum

capacitors,butoccasionallyasolidtantalumunitwillhave

abnormally high ESR, especially at very low tempera-

tures. The suggested 2µF value shown in the circuit

applications should be increased to 4.7µF for –40°C and

–55°C designs if the 2µF units cannot be guaranteed to

stay below 2Ω at these temperatures.

R_LIM. It generates a current limit sense voltage across R1.

The regulator will current limit via A4 when the voltage

across R2 is equal to the voltage across R1. These two

resistors essentially form a current “amplifier” with a gain

of 350/0.055 = 6,360. Good temperature drift is inherent

because R1 and R2 are made from the same diffusions.

Their ratio, not absolute value, determines current limit.

Initial accuracy is enhanced by trimming R1 slightly at

wafer level. Current limit is equal to 15kΩ/R_LIM

.

D1 and I₁are used to guarantee regulator shutdown when

REF pin current drops below 2µA. A current less than 2µA

through Q4 causes the +input of A5 to go low and shut

down the regulator via D2.

A3 is an internal current limit amplifier which can override

the external current limit. It provides “goof proof” protec-

tion for the pass transistor. Although not shown, A3 has

a nonlinear foldback characteristic at input-output volt-

ages above 12V to guarantee safe area protection for Q3.

See the graph, Internal Current Limit in the Typical Perfor-

mance Characteristics of this data sheet.

Although solid tantalum capacitors are suggested, other

types can be used if they meet the ESR requirements.

Standard aluminum electrolytic capacitors need to be

upward of 25µF in general to hold 2Ω maximum ESR,

especially at low temperatures. Ceramic, plastic film, and

monolithic capacitors have a problem with ESR being too

low. These types should have a 1Ω carbon resistor in

series to guarantee loop stability.

Setting Output Voltage

The LT1185 output voltage is set by two external resistors

(see Figure 2). Internal reference voltage is trimmed to

2.37V so that a standard 1% 2.37k resistor (R1) can be

used to set divider current at 1mA. R2 is then selected

from:

The output capacitor should be located close to the regu-

lator (≤3") to avoid excessive impedance due to lead

inductance. A six inch lead length (2 • 3") will generate an

extra 0.8Ω inductive reactance at 1MHz, and unity-gain

frequency can be up to that value.

(V

– 2.37) R1

OUT

R2 =

V

REF

Forremotesenseapplications,thecapacitorshouldstillbe

located close to the regulator. Additional capacitance can

be added at the remote sense point, but the remote

capacitor must be at least 2µF solid tantalum. It cannot be

a low ESR type like ceramic or mylar unless a 0.5Ω to 1Ω

carbon resistor is added in series with the capacitor. Logic

boards with multiple low ESR bypass capacitors should

have a solid tantalum unit added in parallel whose value is

approximately five times the combined value of low ESR

capacitors.

for R1 = 2.37k and V_REF= 2.37V, this reduces to:

R2 = V_OUT– 2.37k

suggested values of 1% resistors are shown.

V_OUT

R2 WHEN R1 = 2.37k

5V

5.2V

6V

12V

15V

2.67k

2.87k

3.65k

9.76k

12.7k

1185ff

6

LT1185

W U U

APPLICATIO S I FOR ATIO

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Large output capacitors (electrolytic or solid tantalum)

will not cause the LT1185 to oscillate, but they will cause

a damped “ringing” at light load currents where the ESR

of the capacitor is several orders of magnitude lower than

the load resistance. This ringing only occurs as a result of

transient load or line conditions and normally causes no

problems because of its low amplitude (≤25mV).

Example: A commercial version of the LT1185 in the

TO-220 package is to be used with a maximum ambient

temperature of 60°C. Output voltage is 5V at 2A. Input

voltage can vary from 6V to 10V. Assume an interface

resistance of 1°C/W.

First solve for control area, where the maximum junction

temperature is 125°C for the TO-220 package, and

θ_JC= 1°C/W:

Heat Sinking

2A

40

P = (10V – 5V) (2A) +

125°C – 60°C

(10V) = 10.5W

TheLT1185willnormallybeusedwithaheatsink.Thesize

of the heat sink is determined by load current, input and

output voltage, ambient temperature, and the thermal

resistance of the regulator, junction-to-case (θ_JC). The

LT1185 has two separate values for θ_JC: one for the power

transistor section, and a second, lower value for the

control section. The reason for two values is that the

powertransistoriscapableofoperatingathighercontinu-

ous temperature than the control circuitry. At low power

levels, the two areas are at nearly the same temperature,

and maximum temperature is limited by the control area.

At high power levels, the power transistor will be at a

significantly higher temperature than the control area

and its maximum operating temperature will be the

limiting factor.

θ

=

– 1°C/W – 1°C/W = 4.2°C/W

HS

10.5W

Next, solve for power transistor limitation, with

T_JMAX= 150°C, θ_JC= 3°C/W:

150 – 60

θ

=

– 3 – 1 = 4.6°C/W

HS

10.5

The lowest number must be used, so heat sink resistance

must be less than 4.2°C/W.

Some heat sink data sheets show graphs of heat sink

temperature rise vs power dissipation instead of listing a

value for thermal resistance. The formula for θ_HScan be

rearranged to solve for maximum heat sink temperature

rise:

To calculate heat sink requirements, you must solve a

thermal resistance formula twice, one for the power

transistor and one for the control area. The lowest value

obtained for heat sink thermal resistance must be used. In

these equations, two values for maximum junction tem-

peratureandjunction-to-casethermalresistanceareused,

as given in Electrical Specifications.

∆T_HS= T_JMAX– T_AMAX– P(θ_JC+ θ_CHS

)

Using numbers from the previous example:

∆T_HS= 125°C – 60 – 10.5(1 + 1) = 44°C control

(T

– T

P

)

AMAX

JMAX

θ

=

– θ – θ

.

HS

JC

CHS

section

= Maximum heat sink thermal resistance

θ = LT1185 junction-to-case thermal resistance

∆T_HS= 150°C – 60 – 10.5(3 + 1) = 48°C power

transistor

HS

JC

θ

= Case-to-heat sink (interface) thermal

resistance, including any insulating washers

= LT1185 maximum operating junction

temperature

= Maximum ambient temperature in

customers application

CHS

The smallest rise must be used, so heat sink temperature

rise must be less than 44°C at a power level of 10.5W.

T

JMAX

For board level applications, where heat sink size may be

critical, one is often tempted to use a heat sink which

barely meets the requirements. This is permissible if

correct assumptions were made concerning maximum

ambient temperature and power levels. One complicating

1185ff

AMAX

P = Device dissipaton

= (V – V ) (I ) +

I

OUT

40

(V )

IN

OUT OUT

IN

7

LT1185

APPLICATIO S I FOR ATIO

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factor is that local ambient temperature may be somewhat Ground Pin Current

higher because of the point source of heat. The conse-

Ground pin current for the LT1185 is approximately 2mA

quences of excess junction temperature include poor

reliability, especially for plastic packages, and the possi-

bility of thermal shutdown or degraded electrical charac-

teristics. The final design should be checked in situ with a

thermocouple attached to the regulator case under worst-

case conditions of high ambient, high input voltage and

full load.

plus I_OUT/40. At I_OUT= 3A, ground pin current is typically

2mA + 3/40 = 77mA. Worst case guarantees on the ratio of

I_OUTto ground pin current are contained in the Electrical

Specifications.

Ground pin current can be important for two reasons. It

adds to power dissipation in the regulator and it can affect

load/line regulation if a long line is run from the ground pin

to load ground. The additional power dissipation is found

by multiplying ground pin current by input voltage. In a

typicalexample, withV_IN=8V, V_OUT=5VandI_OUT=2A, the

LT1185 will dissipate (8V – 5V)(2A) = 6W in the pass

transistor and (2A/40)(8V) = 0.4W in the internal drive

circuitry. This is only a 1.5% efficiency loss, and a 6.7%

increase in regulator power dissipation, but these values

will increase at higher output voltages.

What About Overloads?

IC regulators with thermal shutdown, like the LT1185,

allow heat sink designs which concentrate on worst-case

“normal” conditions and ignore “fault” conditions. An

outputoverloadorshortmayforcetheregulatortoexceed

its maximum junction temperature rating, but thermal

shutdown is designed to prevent regulator failure under

these conditions. A word of caution however; thermal

shutdown temperatures are typically 175°C in the control Ground pin current can affect regulation as shown in

portion of the die and 180°C to 225°C in the power Figure 2. Parasitic resistance in the ground pin lead will

transistor section. Extended operation at these tempera- create a voltage drop which increases output voltage as

tures can cause permanent degradation of plastic encap- load current is increased. Similarly, output voltage can

sulation. Designs which may be subjected to extended decrease as input voltage increases because the “I_OUT/40”

periods of overload should either use the hermetic TO-3 component of ground pin current drops significantly at

package or increase heat sink size. Foldback current higher input-output differentials. These effects are small

limiting can be implemented to minimize power levels enough to be ignored for local regulation applications, but

under fault conditions.

+

PARASITIC

LEAD RESISTANCES

External Current Limit

The LT1185 requires a resistor to set current limit. The

value of this resistor is 15k divided by the desired current

limit (in amps). The resistor for 2A current limit would be

15k/2A = 7.5k. Tolerance over temperature is ±10%, so

current limit is normally set 15% above maximum load

current. Foldback limiting can be employed if short-circuit

current must be lower than full load current (see Typical

Applications).

– r

+

r

b

a

I

GND

R

LIM

V

IN

R1*

LOAD

2.37k

R2

REF

GND

V

OUT

FB

V

LT1185

–

IN

V

–

OUT

LT1185 • F02

The LT1185 has internal current limiting which will over-

ride external current limit if power in the pass transistor

is excessive. The internal limit is ≈3.6A with a foldback

characteristic which is dependent on input-output volt-

age, not output voltage per se (see Typical Performace

*R1 SHOULD BE CONNECTED DIRECTLY TO GROUND LEAD, NOT TO THE LOAD,

SO THAT r ≈ 0Ω. THIS LIMITS THE OUTPUT VOLTAGE ERROR TO (I )(r ).

a

GND

b

ERRORS CREATED BY r ARE MULTIPLIED BY (1 + R2/R1). NOTE THAT V

a

OUT

INCREASES WITH INCREASING GROUND PIN CURRENT. R2 SHOULD BE CONNECTED

DIRECTLY TO LOAD FOR REMOTE SENSING

Figure 2. Proper Connection of Positive Sense Lead

Characteristics)

.

1185ff

8

LT1185

W U U

APPLICATIO S I FOR ATIO

U

for remote sense applications, they may need to be con-

sidered. Ground lead resistance of 0.4Ω would cause an

output voltage error of up to (3A/40)(0.4Ω) = 30mV, or

0.6% at V_OUT= 5V. Note that if the sense leads are

connected as shown in Figure 2, with r_a≈ 0Ω, this error is

a fixed number of millivolts, and does not increase as a

function of DC output voltage.

to 400Hz rectified AC inputs because parasitic resistance

and inductance will limit rate of rise even if the power

switch is closed at the peak of the AC line voltage. This

assumes that the switch is in the AC portion of the circuit.

If instead, a switch is placed directly in the regulator input

sothatalargefiltercapacitorisprecharged,fastinputslew

rates will occur on switch closure. The output of the

regulator will slew at a rate set by current limit and output

capacitorsize;dVdt=I_LIM/C_OUT. WithI_LIM=3.6AandC_OUT

= 2.2µF, the output will slew at 1.6V/µs and overshoot can

occur. This overshoot can be reduced to a few hundred

millivolts or less by increasing the output capacitor to

10µFand/orreducingcurrentlimitsothatoutputslewrate

is held below 0.5V/µs.

Shutdown Techniques

The LT1185 can be shut down by open-circuiting the REF

pin. The current flowing into this pin must be less than

0.4µA to guarantee shutdown. Figure 3 details several

ways to create the “open” condition, with various logic

levels. Forvariationsontheseschemes, simplyremember

that the voltage on the REF pin is 2.4V negative with

respect to the ground pin.

A second possibility for creating output overshoot is

recovery from an output short. Again, the output slews at

a rate set by current limit and output capacitance. To avoid

overshoot, the ratio I_LIM/C_OUTshould be less than

0.5 × 10⁶. Remember that load capacitance can be added

to C_OUTfor this calculation. Many loads will have multiple

Output Overshoot

Very high input voltage slew rate during start-up may

cause the LT1185 output to overshoot. Up to 20% over-

shootcouldoccurwithinputvoltageramp-uprateexceed-

ing 1V/µs. This condition cannot occur with normal 50Hz

supply bypass capacitors that total more than C_OUT

.

5V Logic, Negative Regulated Output

5V Logic, Positive Regulated Output

5V

+

V

OUT

†

R

R1

R2

LIM

*

4k

“HI” = OUTPUT “OFF”

3 EA 1N4148

REF

GND

+

Q1

2N3906

FB

Q1

2N3906

R5

300k

LT1185

V

IN

R4

33k

R

LIM

V

OUT

V

IN

REF

GND

FB

LT1185 • F3a

V

R7

R6

30k

V

LT1185

^IN–

IN

2.4k^†

*CMOS LOGIC

^†FOR HIGHER VALUES OF R , MAKE R7 = (R )(0.6)

LIM

–

V

OUT

LT1185 • F03b

Figure 3. Shutdown Techniques

1185ff

9

LT1185

W U U

U

APPLICATIO S I FOR ATIO

Thermal Regulation

This shift in output voltage could be in either direction

because K1 and K2 can be either positive or negative.

IC regulators have a regulation term not found in discrete

designsbecausethepowertransistoristhermallycoupled

to the reference. This creates a shift in the output voltage

whichisproportionaltopowerdissipationintheregulator.

Thermal regulation is already included in the worst case

reference specification.

Output Voltage Reversal

∆V_OUT= P(K1 + K2 θ_JA)

Some IC regulators suffer from a latch-up state when their

outputisforcedtoareversevoltageofaslittleasonediode

drop. The latch-up state can be triggered without a fault

condition when the load is connected to an opposite

polarity supply instead of to ground. If the second supply

is turned on first, it will pull the output of the first supply

to a reverse voltage through the load. The first supply may

then latch off when turned on. This problem is particularly

annoying because the diode clamps which should always

be used to protect against polarity reversal do not usually

stop the latch-up problem.

= (I_OUT)(V_IN– V_OUT)(K1 + K2 θ_JA)

K1 and K2 are constants. K1 is a fast time constant effect

caused by die temperature gradients which are estab-

lished within 50ms of a power change. K1 is specified on

the data sheet as thermal regulation, in percent per watt.

K2 is a long time constant term caused by the temperature

drift of the regulator reference voltage. It is also specified,

but in percent per degree centigrade. It must be multiplied

by overall thermal resistance, junction-to-ambient, θ_JA.

As an example, assume a 5V regulator with an input

voltage of 8V, load current of 2A, and a total thermal

resistance of 4°C/W, including junction-to-case, (use

control area specification), interface, and heat sink resis-

tance. K1 and K2, respectively, from the data sheet are

0.014%/W and 0.01%/°C.

The LT1185 is designed to allow output reverse polarity of

several volts without damage or latch-up, so that a simple

diode clamp can be used.

∆V_OUT= (2A)(8V – 5V)(0.014 + 0.01 • 4)

= 0.32%

1185ff

10

LT1185

U

TYPICAL APPLICATIO S

Foldback Current Limiting

+

1.6

1.4

1.2

1.0

R3

R4

5.36k

R1

2.37k

15k

15k 10.8k

I

=

+

FULL LOAD

Q1

2N3906

R3

R4

+

2µF

TANT

V

IN

+

2µF

TANT

V

OUT

0.8

0.6

GND

REF

FB

0.4

0.2

0

R2

2.61k

V

IN

LT1185

–

15k

R3

I

=

SHORT-CIRCUIT

V

OUT

–

I

OUT

LT1185 • TA03b

LT1185 • TA03a

Auxiliary + 12V Low Dropout Regulator for Switching Supply

12V

*

REGULATED

AUXILIARY

R1

2.37k

R

LIM

+

REF

GND

+

FB

R2

9.76k

V

LT1185

IN

V

OUT

PRIMARY

5V

*

MAIN

OUTPUT

+

5V

CONTROL

*DIODE CONNECTION INDICATES A FLYBACK

SWITCHING TOPOLOGY, BUT FORWARD

CONVERTERS MAY ALSO BE USED

LT1185 • TA04

1185ff

11

LT1185

TYPICAL APPLICATIO S

U

Low Input Voltage Monitor Tracks Dropout Characteristics

+

*3" #26 WIRE

**R4 DETERMINES TRIP POINT AT I

R1

R3

+

C2

2.2µF

TANT

= 0

4k

OUT

2.37k

360k

R6 DETERMINES INCREASE OF TRIP POINT AS I

R4 • R7

INCREASES

OUT

V

IN

R5 • R7

R6

REF

GND

TRIP POINT FOR V = V

1 +

+ I

OUT

+

C1

2.2µF

TANT

IN

OUT

(

)

R3 • R6

R4**

1k

V

FB

OUT

R5*

0.01Ω

FOR VALUES SHOWN, TRIP POINT FOR V IS:

IN

V

OUT

+ 0.37V AT I

= 0 AND V

= 1.18V AT I

= 3A

OUT

R2

2.6k

^†DO NOT SUBSTITUTE. OP AMP MUST HAVE COMMON MODE

RANGE EQUAL TO NEGATIVE SUPPLY

V

IN

LT1185

–

V

–

OUT

R6**

1k

R7

27k

OPTIONAL HYSTERESIS

≈2M

3

+

“LOW” FOR LOW INPUT

LT1006^†

+

–

V

OUTPUT SWINGS FROM V TO V

IN

2

–

7

V

–

4

LT1185 • TA05

Time Delayed Start-Up

Delay Time

+

4.0

3.5

3.0

2.5

R1

2.37k

R3**

15k

D3^†

R

***

LIM

D2

D1

V

IN

+

C1

2.2µF

TANT

V

OUT

Q1**

REF

GND

2.0

1.5

+

C2

2.2µF

FB

C3*

V

IN

LT1185

–

R2

1.0

0.5

0

V

–

OUT

LT1185 • TA06

5

10

20

0

25

30

15

ALL DIODES 1N4148

*SEE CHART FOR DELAY TIME VERSUS (C3)(R3//R ) PRODUCT

INPUT VOLTAGE (V)

LIM

LT1185 • TA07

**FOR LONG DELAY TIMES, REPLACE D2 WITH 2N3906 TRANSISTOR AND USE R3 ONLY FOR

CALCULATING DELAY TIME. R3 CAN INCREASE TO 100k

R3 • R

R3 + R

LIM

*t = (R3//R )(C3) =

(C3)

LIM

(

)

LIM

***I

IS ≈11k/R , INSTEAD OF 15k, BECAUSE OF VOLTAGE DROP IN D1. TEMPERATURE

LIM

COEFFICIENT OF I

WILL BE ≈0.11%/°C, SO ADEQUATE MARGIN MUST BE ALLOWED

LIM

FOR COLD OPERATION

^†D3 PROVIDES FAST RESET OF TIMING. INPUT MUST DROP TO A LOW VALUE TO RESET TIMING

1185ff

12

LT1185

W

SCHE ATIC DIAGRA

1185ff

13

LT1185

U

PACKAGE DESCRIPTIO

K Package

4-Lead TO-3 Metal Can

(Reference LTC DWG # 05-08-1311)

1.177 – 1.197

(29.90 – 30.40)

.760 – .775

(19.30 – 19.69)

.655 – .675

(16.64 – 19.05)

.320 – .350

(8.13 – 8.89)

.470 TP

P.C.D.

.060 – .135

(1.524 – 3.429)

.151 – .161

(3.84 – 4.09)

DIA 2 PLC

.420 – .480

(10.67 – 12.19)

.167 – .177

(4.24 – 4.49)

R

.038 – .043

(0.965 – 1.09)

.490 – .510

(12.45 – 12.95)

R

72°

18°

K4(TO-3) 0801

OBSOLETE PACKAGE

T Package

5-Lead Plastic TO-220 (Standard)

(Reference LTC DWG # 05-08-1421)

.165 – .180

(4.191 – 4.572)

.147 – .155

(3.734 – 3.937)

DIA

.390 – .415

(9.906 – 10.541)

.045 – .055

(1.143 – 1.397)

.230 – .270

(5.842 – 6.858)

.570 – .620

(14.478 – 15.748)

.620

(15.75)

TYP

.460 – .500

(11.684 – 12.700)

.330 – .370

(8.382 – 9.398)

.700 – .728

(17.78 – 18.491)

.095 – .115

(2.413 – 2.921)

SEATING PLANE

.152 – .202

(3.861 – 5.131)

.155 – .195*

(3.937 – 4.953)

.260 – .320

(6.60 – 8.13)

.013 – .023

(0.330 – 0.584)

.067

BSC

.135 – .165

(3.429 – 4.191)

.028 – .038

(0.711 – 0.965)

(1.70)

* MEASURED AT THE SEATING PLANE

T5 (TO-220) 0801

1185ff

14

LT1185

U

PACKAGE DESCRIPTIO

Q Package

5-Lead Plastic DD Pak

(Reference LTC DWG # 05-08-1461)

.060

(1.524)

TYP

.390 – .415

(9.906 – 10.541)

.060

(1.524)

.165 – .180

(4.191 – 4.572)

.256

(6.502)

.045 – .055

(1.143 – 1.397)

15° TYP

+.008

.004

–.004

.060

(1.524)

.059

(1.499)

TYP

.183

(4.648)

.330 – .370

(8.382 – 9.398)

+0.203

–0.102

0.102

(

)

.095 – .115

(2.413 – 2.921)

.075

(1.905)

.067

(1.702)

BSC

.050 ± .012

(1.270 ± 0.305)

.300

(7.620)

.013 – .023

(0.330 – 0.584)

+.012

.143

–.020

.028 – .038

(0.711 – 0.965)

TYP

+0.305

BOTTOM VIEW OF DD PAK

HATCHED AREA IS SOLDER PLATED

COPPER HEAT SINK

3.632

Q(DD5) 0502

(

)

–0.508

.420

.276

.080

.420

.350

.325

.205

.565

.320

.090

.042

.090

.042

.067

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

RECOMMENDED SOLDER PAD LAYOUT

FOR THICKER SOLDER PASTE APPLICATIONS

1. DIMENSIONS IN INCH/(MILLIMETER)

2. DRAWING NOT TO SCALE

1185ff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of circuits as described herein will not infringe on existing patent rights.

15

LT1185

TYPICAL APPLICATIO S

U

Logic Controlled 3A Low-Side Switch with Fault Protection

5V

R

LIM

4k

1N4001

REF

GND

V

LOAD

ADD FOR

INDUCTIVE LOADS

FB

LT1185

OUT

V

IN

LT1185 • TA08

Improved High Frequency Ripple Rejection

+

C2

2.2µF

TANT

R1

2.37k

R

LIM

V

IN

C1

REF

GND

4.7µF

V

OUT

FB

TANT

C3

0.05µF

R2

V

IN

LT1185

–

V

OUT

–

LT1185 • TA09

NOTE: C3 IMPOVES HIGH FREQUENCY RIPPLE REJECTION BY 6dB AT V

= 5V,

OUT

AND BY 14dB AT V

WHEN C3 IS USED

= 12V. C1 IS INCREASED TO 4.7µF TO ENSURE GOOD STABILTITY

OUT

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1085

7.5A Low Dropout Regulator

1V Dropout Voltage

LT1117

800mA Low Dropout Regulator with Shutdown

Micropower Regulator with Comparator and Shutdown

200mA Micropower Low Dropout Regulator

Reverse Voltage and Reverse Current Protection

20µA Supply Current, 2.5V Reference Output

400mV Dropout Voltage, 50µA Supply Current

45µA Supply Current, Adjustable Current Limit

For High Performance Microprocessors

LT1120A

LT1129

LT1175

500mA Negative Low Dropout Micropower Regulator

4.6A Low Dropout Fast Transient Response Regulator

200mA, Low Noise Micropower, Negative LDO

LT1585

LT1964

V : –0.9V to –20V, V

= –1.21V, V = 0.34V, I = 30µA,

IN

OUT(MIN) DO Q

I

= 3µA, ThinSOT Package

SD

1185ff

LT/LWI 0906 REV F • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1185CQ
厂家：	Linear
描述：	Low Dropout Regulator 低压差稳压器稳压器
文件：	总16页 (文件大小：179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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