LT1189CS8 [Linear]
Low Power Video Difference Amplifier; 低功耗视频差分放大器器
| 型号： | LT1189CS8 |
| 厂家： | 
Linear |
| 描述： | Low Power Video Difference Amplifier |
| 文件： | 总12页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1189
Low Power
Video Difference Amplifier
U
DESCRIPTIO
EATURE
S
F
■
■
■
■
■
■
■
■
■
■
■
Differential or Single-Ended Gain Block (Adjustable)
The LT1189 is a difference amplifier optimized for opera-
tion on ±5V, or a single 5V supply, and gain ≥10. This
versatile amplifier features uncommitted high input im-
pedance (+) and (–) inputs, and can be used in differential
or single-ended configurations. Additionally, a second set
of inputs give gain adjustment and DC control to the
difference amplifier.
–3dB Bandwidth, AV = ±10
Slew Rate
Low Supply Current
Output Current
CMRR at 10MHz
LT1193 Pin Out
35MHz
220V/µs
13mA
±20mA
48dB
Low Cost
The LT1189’s high slew rate, 220V/µs, wide bandwidth,
35MHz, and ±20mA output current require only 13mA of
supply current. The shutdown feature reduces the power
dissipation to a mere 15mW, and allows multiple amplifi-
ers to drive the same cable.
Single 5V Operation
Drives Cables Directly
Output Shutdown
O U
PPLICATI
Line Receivers
S
A
The LT1189 is a low power, gain of 10 stable version of the
popular LT1193, and is available in 8-pin miniDIPs and SO
packages. For lower gain applications see the LT1187
data sheet.
■
■
■
■
Video Signal Processing
Cable Drivers
Tape and Disc Drive Systems
U
O
TYPICAL APPLICATI
Cable Sense Amplifier for Loop Through Connections
with DC Adjust
Closed-Loop Gain vs Frequency
50
V
IN
V
= ±5V
= 1k
S
L
R
5V
40
30
20
10
0
3
2
+
–
7
CABLE
6
V
OUT
LT1189
1
8
V
DC
+
–
4
–5V
909Ω
100Ω
0.1
1
10
100
FREQUENCY (MHz)
LT1189 • TA01
LT1189 • TA02
1
LT1189
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
Total Supply Voltage (V + to V –) ............................. 18V
Differential Input Voltage ........................................ ±6V
Input Voltage .......................................................... ±VS
Output Short Circuit Duration (Note 1) ........ Continuous
Operating Temperature Range
LT1189M..................................... – 55°C to 150°C
LT1189C............................................. 0°C to 70°C
Junction Temperature (Note 2)
Plastic Package (CN8,CS8) ......................... 150°C
Ceramic Package (CJ8,MJ8) ....................... 175°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
TOP VIEW
ORDER PART
+/REF
–IN
1
2
3
4
8
7
6
5
–/FB
NUMBER
+
V
LT1189MJ8
LT1189CJ8
LT1189CN8
LT1189CS8
+IN
OUT
S/D
–
V
J8 PACKAGE
N8 PACKAGE
8-LEAD HERMETIC DIP 8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
LT1189 • POI01
S8 PART MARKING
1189
TJMAX = 175°C, θJA = 100°C/W (J8)
JMAX = 150°C, θJA = 100°C/W (N8)
JMAX = 150°C, θJA = 150°C/W (S8)
T
T
+
5V
TA = 25°C, (Note 3)
ELECTRICAL CHARACTERISTICS
–
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
LT1189M/C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
Either Input, (Note 4)
SOIC Package
1.0
1.0
3.0
4.0
mV
mV
OS
I
I
Input Offset Current
Input Bias Current
Either Input
Either Input
0.2
±0.5
30
1.0
µA
µA
OS
±2.0
B
e
Input Noise Voltage
Input Noise Current
Input Resistance
f = 10kHz
O
nV/√Hz
pA/√Hz
kΩ
n
i
f = 10kHz
O
1.25
30
n
R
Differential
Either Input
(Note 5)
IN
C
V
Input Capacitance
2.0
pF
IN
Input Voltage Limit
±170
mV
IN LIM
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing
–2.5
80
3.5
V
CMRR
PSRR
V
= –2.5V to 3.5V
105
90
dB
CM
V = ±2.375V to ±8V
75
dB
S
V
V = ±5V, R = 1k, A = 50
±3.8
±6.7
±6.4
±4.0
±7.0
±6.8
1.0
220
35
V
OUT
S
L
V
V = ±8V, R = 1k, A = 50
S
L
V
V = ±8V, R = 300Ω, A = 50, (Note 3)
S
L
V
G
E
Gain Error
V = ±1.0V, A = 10
3.5
75
%
V/µs
MHz
MHz
ns
O
V
SR
Slew Rate
(Note 6, 10)
150
35
FPBW
BW
Full Power Bandwidth
Small Signal Bandwidth
Rise Time, Fall Time
Propagation Delay
Overshoot
V = 2V , (Note 7)
O P-P
A = 10
35
V
t , t
r
A = 50, V = ±1.5V, 20% to 80% (Note 10)
50
f
V
O
t
R = 1k, V = ±125mV, 50% to 50%
12
ns
PD
L
O
V = ±50mV
10
%
O
t
Settling Time
3V Step, 0.1%, (Note 8)
1
µs
s
Diff A
Differential Gain
Differential Phase
Supply Current
R = 1k, A = 10, (Note 9)
0.6
0.75
13
%
V
L
V
Diff Ph
R = 1k, A = 10, (Note 9)
DEG
P-P
L
V
I
16
mA
mA
S
–
Shutdown Supply Current
Pin 5 at V
0.8
1.5
2
LT1189
+
5V
ELECTRICAL CHARACTERISTICS TA = 25°C, (Note 3)
–
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
LT1189M/C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µA
–
I
t
t
Shutdown Pin Current
Turn On Time
Pin 5 at V
5
25
S/D
on
–
Pin 5 from V to Ground, R = 1k
500
600
ns
L
–
Turn Off Time
Pin 5 from Ground to V , R = 1k
ns
off
L
5V
open.
TA = 25°C, (Note 3)
ELECTRICAL CHARACTERISTICS
VS+ = 5V, VS– = 0V, VREF = 2.5V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to VREF, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5
LT1189M/C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
Either Input, (Note 4)
SOIC Package
1.0
1.0
3.0
5.0
mV
mV
I
I
Input Offset Current
Either Input
Either Input
0.2
1.0
±2.0
3.5
µA
µA
V
OS
Input Bias Current
±0.5
B
Input Voltage Range
Common-Mode Rejection Ratio
Output Voltage Swing
2.0
80
CMRR
V
CM
= 2.0V to 3.5V
100
4.0
0.15
175
30
dB
V
V
R = 300Ω to Ground
V
V
High
Low
3.6
OUT
L
OUT
OUT
(Note 3)
0.4
SR
Slew Rate
V = 1.5V to 3.5V
O
V/µs
MHz
mA
BW
Small-Signal Bandwidth
Supply Current
A = 10
V
I
I
12
15
1.5
25
S
–
–
Shutdown Supply Current
Shutdown Pin Current
Pin 5 at V
Pin 5 at V
0.8
5
mA
µA
S/D
+
5V LECTR AL CHARACTERIST
E
IC
ICS –55°C ≤ TA ≤ 125°C, (Note 3)
–
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
LT1189M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
µV/°C
µA
V
OS
Input Offset Voltage
Either Input, (Note 4)
1.0
7.5
∆V /∆T
OS
Input V Drift
10
OS
I
I
Input Offset Current
Either Input
Either Input
0.2
1.5
±3.5
3.5
OS
B
Input Bias Current
±0.5
µA
Input Voltage Range
–2.5
80
V
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing
V
CM
= –2.5V to 3.5V
105
90
dB
V = ±2.375V to ±8V
S
65
dB
V
OUT
V = ±5V, R = 1k, A = 50
±3.7
±6.6
±6.4
±4.0
±7.0
±6.6
1.0
13
V
S
L
V
V = ±8V, R = 1k, A = 50
S
L
V
V = ±8V, R = 300Ω, A = 50, (Note 3)
S
L
V
G
E
Gain Error
V = ±1V, A = 10, R = 1k
6.0
17
%
mA
mA
µA
O
V
L
I
Supply Current
S
–
Shutdown Supply Current
Shutdown Pin Current
Pin 5 at V , (Note 11)
0.8
1.5
25
–
I
Pin 5 at V
5
S/D
3
LT1189
+
5V ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C, (Note 3)
–
VS = ±5V, VREF = 0V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to ground, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5 open.
LT1189C
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
V
OS
Input Offset Voltage
(Note 4)
Either Input
SOIC Package
1.0
1.0
3.0
6.0
mV
mV
∆V /∆T
Input V Drift
5.0
0.2
µV/°C
µA
µA
V
OS
OS
I
I
Input Offset Current
Either Input
Either Input
1.5
±3.5
3.5
OS
B
Input Bias Current
±0.5
Input Voltage Range
–2.5
80
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing
V
CM
= –2.5V to 3.5V
105
90
dB
dB
V
V = ±2.375V to ±8V
S
70
V
OUT
V = ±5V, R = 1k, A = 50
S
±3.7
±6.6
±6.4
±4.0
±7.0
±6.6
1.0
13
L
V
V = ±8V, R = 1k, A = 50
S
L
V
V = ±8V, R = 300Ω, A = 50, (Note 3)
S
L
V
G
E
Gain Error
V = ±1V, A = 10, R = 1k
O
3.5
17
%
mA
mA
µA
V
L
I
Supply Current
S
–
Shutdown Supply Current
Shutdown Pin Current
Pin 5 at V , (Note 11)
0.8
5
1.5
25
–
I
Pin 5 at V
S/D
5V ELECTRICAL CHARACTERISTICS
open.
0°C ≤ TA ≤ 70°C, (Note 3)
VS+ = +5V, VS– = 0V, VREF = 2.5V, RFB1 = 900Ω from pins 6 to 8, RFB2 = 100Ω from pin 8 to VREF, RL = RFB1 + RFB2 = 1k, CL ≤ 10pF, pin 5
LT1189C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
µV/°C
µA
V
OS
Input Offset Voltage, (Note 4)
Either Input
1.0
3.0
∆V /∆T
OS
Input V Drift
5.0
OS
I
I
Input Offset Current
Either Input
Either Input
0.2
1.5
±3.5
3.5
OS
B
Input Bias Current
±0.5
µA
Input Voltage Range
Common-Mode Rejection Ratio
Output Voltage Swing
2.0
80
V
CMRR
V
= 2.0V to 3.5V
100
4.0
0.15
12
dB
CM
V
OUT
R = 300Ω to Ground
V
V
High
Low
3.5
V
L
OUT
OUT
(Note 3)
0.4
16
I
I
Supply Current
mA
mA
µA
S
Shutdown Supply Current
Shutdown Pin Current
Pin 5 at V, (Note 11)
0.8
5
1.5
25
–
Pin 5 at V
S/D
Note 1: A heat sink may be required to keep the junction temperature below
absolute maximum when the output is shorted continuously.
Note 6: Slew rate is measured between ±1V on the output, with a V step of
IN
±0.5V, A = 10 and R = 1k.
V L
Note 2: T is calculated from the ambient temperature T and power dissipation
Note 7: Full power bandwidth is calculated from the slew rate measurement:
FPBW = SR/2πVp.
Note 8: Settling time measurement techniques are shown in “Take the
Guesswork Out of Settling Time Measurements,” EDN, September 19, 1985.
J
A
P according to the following formulas:
D
LT1189MJ8, LT1189CJ8: T = T + (P × 100°C/W)
J
A
D
LT1189CN8:
LT1189CS8:
T = T + (P × 100°C/W)
J A D
T = T + (P × 150°C/W)
J
A
D
Note 9: NTSC (3.58MHz).
Note 3: When R = 1k is specified, the load resistor is R + R , but when
L
FB1
FB2
Note 10: AC parameters are 100% tested on the ceramic and plastic DIP
packaged parts (J8 and N8 suffix) and are sample tested on every lot of the SO
packaged parts (S8 suffix).
R = 300Ω is specified, then an additional 430Ω is added to the output such
L
that (R + R ) in parallel with 430Ω is R = 300Ω.
FB1
FB2
L
Note 4: V measured at the output (pin 6) is the contribution from both input
OS
Note 11: See Application section for shutdown at elevated temperatures. Do
pair, and is input referred.
not operate shutdown above T > 125°C.
J
Note 5: V
is the maximum voltage between –V and +V (pin 2 and
IN LIM
IN IN
pin 3) for which the output can respond.
4
LT1189
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs
Common-Mode Voltage vs
Temperature
Common-Mode Voltage
Input Bias Current vs Temperature
+
V
100
0
3.0
2.5
V
= ±5V
S
V = ±5V
S
+
–0.5
–1.0
–1.5
–2.0
V
= 1.8V TO 9V
+I
B
2.0
1.5
1.0
0.5
–100
–200
–300
–400
–I
B
–55°C
I
OS
2.0
1.5
1.0
0.5
25°C
+
V
= –1.8V TO –9V
0
125°C
–
–0.5
V
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75 100 125
–5 –4 –3 –2 –1
0
1
2
3
4
5
TEMPERATURE (°C)
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
LT1189 • TPC02
LT1189 • TPC01
LT1189 • TPC03
Equivalent Input Noise Voltage vs
Frequency
Equivalent Input Noise Current vs
Frequency
Supply Current vs Supply Voltage
200
180
160
16
14
12
10
8
12
10
8
V
T
R
= ±5V
= 25°C
= 0Ω
V
T
= ±5V
= 25°C
= 100k
S
A
S
S
A
R
S
–55°C
25°C
140
120
100
80
6
125°C
4
60
40
2
20
0
0
10
100
1k
10k
100k
0
2
4
6
8
10
10
100
1k
10k
100k
±SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
FREQUENCY (Hz)
LT1189 • TPC04
LT1189 • TPC05
LT1189 • TPC06
Shutdown Supply Current vs
Temperature
Gain Error vs Temperature
Open-Loop Gain vs Temperature
16
14
–1.2
–1.4
–1.6
–1.8
–2.0
6.0
5.0
4.0
3.0
2.0
1.0
0
V
V
= ±5V
= ±3V
V
= ±5V
V
V
A
= ±5V
S
O
R
= 1k
S
S
L
= ±1V
OUT
= 10
V
L
12
10
8
R = 1k
V
= –V + 0.6V
EE
S/D
R
= 500Ω
L
V
= –V + 0.4V
EE
S/D
6
V
= –V + 0.2V
EE
S/D
4
–2.2
–2.4
2
V
= –V
S/D
EE
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1189 • TPC09
LT1189 • TPC07
LT1189 • TPC08
5
LT1189
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Open-Loop Voltage Gain vs
Load Resistance
Gain Bandwidth Product vs
Supply Voltage
Gain, Phase vs Frequency
100
80
60
40
20
0
100
80
250
200
30
20
10
TA = –55°C
V
= ±5V
= 25°C
= 1k
AV = 20dB
S
A
L
V
V
= ±5V
= ±3V
= 25°C
S
O
A
T
PHASE
GAIN
R
T
TA = 25°C
60
40
20
0
TA = 125°C
150
100
–20
100k
–20
0
1M
10M
100M
0
2
4
6
8
10
100
1k
LOAD RESISTANCE (Ω)
10k
FREQUENCY (Hz)
±SUPPLY VOLTAGE (V)
LT1189 • TPC11
LT1189• TPC10
LT1189 • TPC12
Gain Bandwidth Product and
Phase Margin vs Temperature
Common-Mode Rejection Ratio
vs Frequency
Output Impedance vs Frequency
85
75
65
55
100
10
1
90
80
70
60
50
40
30
250
200
150
100
V
= ±5V
V
= ±5V
S
A
V
V
T
= ±5V
= 25°C
= 1k
S
L
S
T
= 25°C
R
A
= 1k
A
A
= 10
= 20dB
R
V
L
GAIN BANDWIDTH
PRODUCT
PHASE MARGIN
0.1
1k
10k
100k
1M
10M
100M
–50 –25
0
25
50
75 100 125
100k
1M
10M
100M
FREQUENCY (Hz)
TEMPERATURE (°C)
FREQUENCY (Hz)
LT1189 • TPC14
LT1189 • TPC13
LT1189 • TPC15
Power Supply Rejection Ratio vs
Frequency
Output Short Circuit Current vs
Temperature
± Output Swing vs Supply Voltage
+
V
80
60
40
20
0
36
35
–0.7
–0.8
–0.9
–1.0
–1.1
V
= ±5V
V
= ±5V
S
A
S
T
= 25°C
125°C
V
= ±300mV
RIPPLE
25°C
34
33
32
31
30
–55°C
+PSRR
–PSRR
R
= 1k
L
±1.8V ≤ V ≤ ±9V
125°C
25°C
S
0.5
0.4
0.3
–55°C
0.2
0.1
–20
–
1k
10k
100k
1M
10M
100M
–50 –25
0
25
50
75
100 125
0
2
4
6
8
10
V
FREQUENCY (Hz)
TEMPERATURE (°C)
±SUPPLY VOLTAGE (V)
LT1189 • TPC16
LT1189 • TPC17
LT1189 • TPC18
6
LT1189
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage Swing vs
Load Resistance
Slew Rate vs Temperature
5
300
250
200
V
= ±5V
S
–SLEW RATE
3
1
T = –55°C
A
T = 25°C
A
T = 25°C
A
+SLEW RATE
T = –55°C
A
–1
–3
–5
T = 25°C
A
V
= ±5V
= 1k
= ±2V
= 10
S
T = 25°C
A
R
L
O
V
V
A
10
100
LOAD RESISTANCE (Ω)
1000
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
LT1189 • TPC19
LT1189 • TPC20
Harmonic Distortion vs
Output Level
Output Voltage Step vs
Settling Time, AV = 10
4
2
0
–10
–20
–30
–40
–50
–60
V
T
= ±5V
= 25°C
= 1k
V
T
= ±5V
= 25°C
= 1k
S
S
A
A
R
10mV
R
L
L
f = 10MHz
= 10
A
V
HD
3
0
HD
2
10mV
180
–2
–4
3
100 140
220
260
300
340
0
1
2
4
SETTLING TIME (ns)
OUTPUT VOLTAGE (V
)
P-P
LT1189 • TPC22
LT1189 • TPC21
Large-Signal Transient Reponse
Small-Signal Transient Reponse
AV = 10, RL = 1k, +SR = 223V/µs, –SR = 232V/µs
AV = 10, RL = 1k, tr = 9.40ns
LT1189 • TPC23
LT1189 • TPC24
7
LT1189
PPLICATI
O U
W
U
A
S I FOR ATIO
The primary use of the LT1189 is in converting high speed
differential signals to a single-ended output. The LT1189
videodifferenceamplifierhastwouncommittedhighinput
impedance (+) and (–) inputs. The amplifier has another
set of inputs which can be used for reference and feed-
back. Additionally, this set of inputs give gain adjust, and
DC control to the differential amplifier. The voltage gain of
the LT1189issetlikeaconventionaloperationalamplifier.
Feedback is applied to pin 8, and it is optimized for gains
of 10 or greater. The amplifier can be operated single-
ended by connecting either the (+) or (–) inputs to the
+/REF (pin 1). The voltage gain is set by the resistors:
(RFB + RG)/RG.
Power Supply Bypassing
The LT1189 is quite tolerant of power supply bypassing.
In some applications a 0.1µF ceramic disc capacitor
placed 1/2 inch from the amplifier is all that is required. In
applications requiringgood settling time, it isimportant to
use multiple bypass capacitors. A 0.1µF ceramic disc in
parallel with a 4.7µF tantalum is recommended.
Calculating the Output Offset Voltage
Both input stages contribute to the output offset voltage at
pin 6. The feedback correction forces balance in the input
stages by introducing an Input VOS at pin 8. The complete
expression for the output offset voltage is:
Like the single-ended case, the differential voltage gain is
setbytheexternalresistors:(RFB +RG)/RG. Themaximum
input differential signal for which the output will respond
is approximately ±170mV.
VOUT=(VOS +IOS(RS)+IB(RREF)) ×(RFB +RG)/RG +IB(RFB)
RS represents the input source resistance, typically 75Ω,
and RREF represents finite source impedance from the
DC reference voltage, for VREF grounded, RREF = 0Ω the
IOS is normally a small contributor and the expression
simplifies to:
S/D
S/D
+
+
V
V
5
5
3
2
3
2
7
7
V
+
+
IN
V
–
–
IN
6
6
LT1189
LT1189
V
V
OUT
1
8
1
8
OUT
+/REF
–/FB
+/REF
–/FB
VOUT = VOS(RFB + RG)/RG + IB(RFB)
4
4
If RFB is limited to 1k, the last term of the equation
contributes only 2mV since IB is less than 2µA.
–
–
V
V
R
R
FB
FB
R
+
+
R
G
FB
R
R
G
FB
A
= +
V
R
G
A
V
= –
R
G
+
7
V
R
G
R
G
6
S/D
S/D
+
+
V
V
5
5
3
2
3
2
7
7
R
+
–
+
FB
V
V
IN DIFF
IN DIFF
8
–
Q1
Q2
Q3
Q4
6
6
LT1189
+/REF
–/FB
LT1189
V
V
OUT
1
8
1
8
OUT
V
+/REF
–/FB
IN
R
G
R
G
V
+
3
2
1
REF
+
+
–
IN
R
R
R
E
300
4
4
–
E
300
–
R
R
R
REF
V
R
V
R
S
S
FB
FB
345µA
350µA
R
FB
R
+R
G
R
G
FB
FB
–
4
V
V
= (V
IN DIFF
+ V
)
V
O
=
V
–
V
IN
O
IN
IN DIFF
LT1189 • AI02
(
(
(
(
R
G
R
R
R
G
G
G
LT1189 • AI01
Figure 1. Simplified Input Stage Schematic
8
LT1189
O U
W
U
PPLICATI
A
S I FOR ATIO
High Voltage Instrumentation Amplifier Response
Instrumentation Amplifier Rejects High Voltage
20
Instrumentation amplifiers are often used to process
slowlyvaryingoutputsfromtransducers.WiththeLT1189
it is easy to make an instrumentation amplifier that can
respond to rapidly varying signals. Attenuation resistors
in front of the LT1189 allow very large common-mode
signals to be rejected while maintaining good frequency
response.Theinputcommon-modeanddifferential-mode
signals are reduced by 100:1, while the closed-loop gain
is set to be 100, thereby maintaining unity-gain input to
output. The unique topology allows for frequency re-
sponse boost by adding 150pF to pin 8 as shown.
DIFFERENTIAL-MODE RESPONSE
0
–20
COMMON-MODE RESPONSE
–40
–60
100k
1M
10M
100M
FREQUENCY (Hz)
LT1189 • AI05
3.5MHz Instrumentation Amplifier Rejects 120VP-P
Operating with Low Closed-Loop Gain
The LT1189 has been optimized for closed-loop gains of
10orgreater. Theamplifiercanbeoperatedatmuchlower
closed-loop gains with the aid of a capacitor CFB across
the feedback resistor, (feedback zero). This capacitor
lowers the closed-loop 3dB bandwidth. The bandwidth
cannot be made arbitrarily low because CFB is a short at
high frequency and the amplifier will appear configured
unity-gain. As an approximate guideline, make BW × AVCL
= 200MHz. This expression expands to:
5V
100*
100*
10k*
10k*
2
1
3
8
+
7
REF
V
6
IN
LT1189
–
FB
V
4
CM
120V
P-P
–5V
10k
100Ω
150pF
* 0.1% RESISTORS
WORST CASE CMRR = 48dB
LT1189 • AI03
A
VCL
= 200MHz
2π R
C
(
)(
)
FB
FB
Output of Instrumentation Amplifier with 1MHz Square Wave
Riding on 120VP-P at the Input
or:
A
VCL
C
=
FB
200MHz 2π R
)( )(
(
)
FB
The effect of the feedback zero on the transient and
frequency response is shown for AV = 4.
LT1189 • AI04
9
LT1189
O U
W
U
PPLICATI
A
S I FOR ATIO
Closed-Loop Voltage Gain vs Frequency
Reducing the Closed-Loop Bandwidth
30
Although it is possible to reduce the closed-loop band-
width by using a feedback zero, instability can occur if the
bandwidth is made too low. An alternate technique is to do
differential filtering at the input of the amplifier. This
technique filters the differential input signal, and the
differentialnoise,butdoesnotfiltercommon-modenoise.
Common-mode noise is rejected by the LT1189’s CMRR.
C
C
= 0pF
= 5pF
FB
FB
20
10
0
V
= ±5V
= 25°C
= 4
S
A
T
A
–10
–20
V
R
R
= 900Ω
FB
= 300Ω
10MHz Bandwidth Limited Amplifier
G
100k
1M
10M
FREQUENCY (Hz)
100M
R1
5V
110Ω
3
LT1189 • AI06
+
–
7
2
SIG
eN
6
C1
68pF
V
LT1189
OUT
1
8
Small-Signal Transient Response
REF
FB
D
4
909Ω
–5V
R2
110Ω
eN
CM
AV = 10
1
2π(R1 + R2)C1
eN
100Ω
f
=
–3dB
SIG + eN
CM
D
V
=
+
OUT
CMR
FILTER
LT1189 • AI09
Using the Shutdown Feature
The LT1189 has a unique feature that allows the amplifier
to be shutdown for conserving power, or for multiplexing
several amplifiers onto a common cable. The amplifier will
shutdown by taking pin 5 to V–. In shutdown, the amplifier
dissipates15mWwhilemaintainingatruehighimpedance
output state of about 20kΩ in parallel with the feedback
resistors. For MUX applications, the amplifiers may be
configured inverting, non-inverting, or differential. When
theoutputisloadedwithaslittleas1kΩfromtheamplifier’s
feedback resistors, the amplifier shuts off in 600ns. This
shutoff can be under the control of HC CMOS operating
between 0V and –5V.
AV = 4, RFB = 910Ω, RG = 300Ω
LT1189 • AI07
Small-Signal Transient Response
AV = 4, RFB = 910Ω, RG = 300Ω, CFB = 5pF
LT1189 • AI08
10
LT1189
O U
W
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PPLICATI
A
S I FOR ATIO
1MHz Sine Wave Gated Off with Shutdown Pin
The ability to maintain shutoff is shown on the curve Shut
down Supply Current vs Temperature in the Typical Per-
formance Characteristics section. At very high elevated
temperature it is important to hold the shutdown pin close
to the negative supply to keep the supply current from
increasing.
SHUTDOWN
VOUT
AV = 10, RFB = 900Ω, RG = 100Ω
LT1189 • AI10
U
O
TYPICAL APPLICATI
Differential Receiver MUX for Power Down Applications
15k
1.5k
CABLE 1
5V
3
2
+
–
15k
1.5k
CMOS IN
7
6
LT1189
5
1
8
VDC
REF
FB
4
–5V
1k
CHANNEL SELECT
100Ω
1k
74HC04
74HC04
VOUT
1k
–5V
15k
1.5k
15k
1.5k
CABLE 2
5V
7
3
2
5
+
–
6
LT1189
1
8
V
DC
REF
FB
4
–5V
1% RESISTORS WORST CASE CMRR = 28dB
TYPICALLY 35dB
1k
100Ω
LT1189 • TA03
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT1189
W
W
SI PLIFIED SCHE ATIC
+
V
7
V
V
BIAS
BIAS
C
M
+
–
3
2
C
FF
+V
V
6
+V
OUT
*
–
V
4
5
S/D
1 +/REF
8
–/FB
* SUBSTRATE DIODE, DO NOT FORWARD BIAS
LT1189 • SS
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
0.405
(10.287)
MAX
0.005
(0.127)
MIN
0.200
(5.080)
MAX
0.290 – 0.320
(7.366 – 8.128)
CORNER LEADS OPTION
(4 PLCS)
6
5
8
7
0.015 – 0.060
(0.381 – 1.524)
0.023 – 0.045
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
J8 Package
8-Lead Hermetic DIP
(0.58 – 1.14)
HALF LEAD
OPTION
0.008 – 0.018
(0.203 – 0.460)
0° – 15°
0.045 – 0.065
(1.14 – 1.65)
FULL LEAD
OPTION
1
2
3
4
0.045 – 0.065
(1.14 – 1.65)
0.385 ± 0.025
(9.779 ± 0.635)
0.125
3.175
MIN
0.100 ± 0.010
0.014 – 0.026
(2.540 ± 0.254)
(0.360 – 0.660)
0.400
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.320
(7.620 – 8.128)
0.045 – 0.065
(1.143 – 1.651)
8
7
6
5
4
0.065
(1.651)
TYP
N8 Package
8-Lead Plastic DIP
0.250 ± 0.010
(6.350 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
0.125
(3.175)
MIN
0.020
(0.508)
MIN
+0.025
–0.015
1
2
3
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
0.325
+0.635
8.255
(
)
–0.381
0.018 ± 0.003
(0.457 ± 0.076)
0.189 – 0.197
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
S8 Package
8-Lead Plastic SOIC
0.228 – 0.244
(5.791 – 6.197)
0.150 – 0.157
(3.810 – 3.988)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
0°– 8° TYP
1
2
3
4
BA/LT/GP 0293 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
12
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1993
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