LT1325 [Linear]
Microprocessor-Controlled Battery Management System; 微处理器控制的电池管理系统
| 型号： | LT1325 |
| 厂家： | 
Linear |
| 描述： | Microprocessor-Controlled Battery Management System |
| 文件： | 总24页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1325
Microprocessor-Controlled
Battery Management System
U
FEATURES
DESCRIPTION
The LTC®1325 provides the core of a flexible, cost-effec-
■
Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride,
Lithium Ion or Lead-Acid Batteries under
Flexible Current Regulation:
µP Control
tive solution for an integrated battery management sys-
tem. The monolithic CMOS chip controls the fast charging
of nickel-cadmium, nickel-metal-hydride, lead-acid or
lithium batteries under microprocessor control. The de-
vice features a programmable 111kHz PWM constant
current source controller with built-in FET driver, 10-bit
ADC, internal voltage regulator, discharge-before-charge
controller, programmable battery voltage attenuator and
an easy-to-use serial interface.
■
– Programmable 111kHz PWM Current Regulator
with Built-In PFET Driver
– PFET Current Gating for Use with External Current
Regulator or Current Limited Transformer
Discharge Mode
Measures Battery Voltage, Battery Temperature and
Ambient Temperature with Internal 10-Bit ADC
Battery Voltage, Temperature and Charge Time
Fault Protection
■
■
■
■
The chip may operate in one of five modes: power shut-
down, idle, discharge, charge or gas gauge. In power
shutdown the supply current drops to 30µA and in the idle
mode,anADCreadingmaybemadewithoutanyswitching
noise affecting the accuracy of the measurement. In the
discharge mode, the battery is discharged by an external
transistor while the battery is being monitored by the
LTC1325 for fault conditions. The charge mode is termi-
nated by the µP while monitoring any combination of
battery voltage and temperature, ambient temperature
and charge time. The LTC1325 also monitors the battery
for fault conditions before and during charging. In the gas
gauge mode the LTC1325 allows the total charge leaving
the battery to be calculated.
Built-In Voltage Regulator and Programmable
Battery Attenuator
■
■
■
■
■
Easy-to-Use 3- or 4-Wire Serial
Accurate Gas Gauge Function
Wide Supply Range: VDD = 4.5V to 16V
Can Charge Batteries with Voltages Greater Than VDD
Can Charge Batteries from Charging Supplies Greater
Than VDD
µP Interface
■
Digital Input Pins Are High Impedance in
Shutdown Mode
U
APPLICATIONS
■
System Integrated Battery Charger
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATION
Battery Charger for up to 8 NiCd or NiMH Cells
V
DD
4.5V TO 16V
+
P1
IRF9730
C2
10µF
D1
1N6818
LTC1325
REG
1
2
3
4
5
6
7
8
9
MPU
18
17
16
15
14
13
12
11
10
R
R13
TRK
+
V
DD
C
L1
REG
(e.g. 8051)
4.7µF
62µH
D
OUT
D
IN
PGATE
DIS
R5
p1.4
p1.3
p1.2
100Ω
CS
V
T
BAT
BAT
CLK
LTF
MCV
HTF
GND
R
DIS
C1
0.1µF
R1
R2
R3
T
AMB
THERM 1
+
BAT
C
REG
22µF
V
IN
N1
IRFZ34
THERM 2
SENSE
FILTER
C
F
R
SENSE
1µF
R4
LTC1325 • TA01
1
LTC1325
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
ORDER PART
NUMBER
VDD to GND............................................................. 17V
All Other Pins................................ –0.3V to VDD + 0.3V
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
REG
1
2
3
4
5
6
7
8
9
18
17 PGATE
V
DD
D
OUT
D
16
15
14
13
12
11
10
DIS
V
LTC1325CN
LTC1325CSW
IN
CS
CLK
LTF
BAT
T
T
BAT
AMB
MCV
HTF
GND
V
IN
SENSE
FILTER
SW PACKAGE
18-LEAD PLASTIC SO WIDE
N PACKAGE
18-LEAD PDIP
TJMAX = 125°C, θJA = 75°C/ W (N)
JMAX = 125°C, θJA = 100°C/ W (SW)
T
Consult factory for Industrial and Military grade parts.
VDD = 12V ±5%, TA = 25°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
16
2000
50
3.097
–5
–100
UNITS
V
V
V
V
V
Supply Voltage
Supply Current
Supply Current
●
●
●
●
4.5
DD
DD
DD
DD
I
I
All TTL Inputs = 0V or 5V, No Load on REG
Power-Down Mode, All TTL Inputs = 0V or 5V
No Load
1200
30
3.072
–1
–60
50
160
55
µA
µA
V
DD
PD
V
REG
Regulator Output Voltage
Regulator Load Regulation
Regulator Line Regulation
Regulator Output Tempco
DAC Output Voltage
3.047
LD
LI
TC
Sourcing Only, I
= 0mA to 2mA
REG
mV/mA
µV/V
ppm/°C
REG
No Load, V = 4.5V to 16V
REG
DD
No Load, 0°C < T < 70°C
REG
A
V
DAC
VR1 = 1, VR0 = 1, 100% Duty Ratio, I
VR1 = 1, VR0 = 0, 100% Duty Ratio, I
VR1 = 0, VR0 = 1, 100% Duty Ratio, I
VR1 = 0, VR0 = 0, 100% Duty Ratio, I
= I (Note 7)
= I/3
= I/5
140
48
30
180
62
38
mV
mV
mV
mV
CHRG
CHRG
CHRG
CHRG
34
18
= I/10
16
21
V
V
Fault Comparator Hysteresis
Fault Comparator Offset
V
V
V
V
= 1V, V
= 0.9V, V
= 100mV
±20
±10
±50
mV
mV
mV
HYST
HTF
EDV
BATR
= V = 2V
MCV
LTF
= 1V, V
= 0.9V, V
EDV
= 100mV
OS
HTF
BATR
= V = 2V
MCV
LTF
V
V
V
V
V
A
V
V
V
for BATR = 1
for BATP = 1
100
mV
V
mV
V
BATR
BATP
EDV
BAT
●
●
V
– 1.8
DD
860
1.6
0.5
BAT
Internal EDV Voltage
LTF, MCV Voltage Range
HTF Voltage Range
Gas Gauge Gain
900
945
2.8
1.3
, V
LTF MCV
HTF
V
–0.4V < V
–0.4V < V
< 0V
< 0V (Note 6)
–4
±1
1000
GG
SENSE
SENSE
Gas Gauge Offset
LSB
Ω
OS(GG)
R
TOL
Internal Filter Resistor
Battery Divider Tolerance
Input Low Voltage
Input High Voltage
Low Level Input Current
High Level Input Current
F
All Division Ratios
CLK, CS, D
CLK, CS, D
●
●
●
●
●
–2
0.8
2
%
V
V
µA
µA
BATD
V
V
1.3
1.7
IL
IN
IN
2.4
2.5
2.5
IH
I
I
V
V
, V or V = 0V
–2.5
–2.5
IL
IH
CLK CS
DIN
, V or V = 5V
CLK CS
DIN
2
LTC1325
VDD = 12V ±5%, TA = 25°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Output Low Voltage
Output High Voltage
Hi-Z Output Leakage
DIS or PGATE Output High
DIS or PGATE Output Low
D
D
, I = 1.6mA
OUT OUT
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0.4
OL
OH
, I
= –1.6mA
2.4
V
µA
V
OUT OUT
I
V
V
V
= 5V
= 4.5V to 16V
= 4.5V to 16V
±10
OZ
CS
DD
DD
V
V
V
– 0.05
DD
OHFET
OLFET
dDO
0.05
650
510
400
V
t
t
t
t
t
t
f
t
t
f
Delay Time, CLK↓ to D
Valid
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
CLK Pin
ns
ns
ns
ns
ns
ns
kHz
ns
ns
kHz
OUT
Delay Time, CS↑ to D
Hi-Z
dis
OUT
Delay Time, CLK↓ to D
Time D
Enabled
en
OUT
Remains Valid After CLK↓
OUT
30
hDO
D
OUT
D
OUT
Rise Time
Fall Time
250
100
500
150
150
130
rDOUT
fDOUT
CLK
Serial I/O Clock Frequency
PGATE Rise Time
PGATE Fall Time
25
90
C
C
= 1500pF
= 1500pF
rPGATE
fPGATE
OSC
LOAD
LOAD
Internal Oscillator Frequency
Charge Mode, Fail-Safes Disabled
111
A/D Converter
Offset Error
Linearity Error
Full-Scale Error
On-Channel Leakage
Off-Channel Leakage
V
V
V
V
V
Channel (Note 3)
Channel (Notes 3, 4)
Channel (Note 3)
Channel ON Only (Notes 3, 5)
Channel OFF (Notes 3, 5)
●
●
●
●
●
±2
±0.5
±1
±10
±10
LSB
LSB
LSB
µA
IN
IN
IN
IN
IN
µA
W U W
RECO E DED CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
150
1
400
0.8
1
1
43
52
TYP
MAX
UNITS
ns
t
t
t
t
t
t
t
Hold Time, D After CLK↑
Setup Time, CS Before First CLK↑
hDI
IN
µs
ns
µs
µs
dsuCS
dsuDI
WHCLK
WLCLK
WHCS
WLCS
Setup Time, D Stable Before First CLK↑
IN
CLK High Time
CLK Low Time
CS High Time Between Data Transfers
CS Low Time During Data Transfer
µs
MSBF = 1
MSBF = 0
CLK Cycles
CLK Cycles
The
●
denotes specifications which apply over the full operating
Note 4: Linearity error is specified between the actual end points of the
A/D transfer curve.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: Channel leakage is measured after channel selection.
Note 6: Gas gauge offset excludes A/D offset error.
Note 2: All voltage values are with respect to the GND pin.
Note 7: I = V (Duty Ratio)/R
, where V
SENSE
is the DAC output
DAC
DAC
Note 3: V
within specified min and max limits, CLK (Pin 5) = 500kHz,
voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and R
determined by the user.
is
REG
SENSE
unless otherwise stated. ADC clock is the serial CLK.
3
LTC1325
TYPICAL PERFORMANCE CHARACTERISTICS
U W
VDD Supply Current vs
Temperature
Regulator Output Voltage vs
Load Current
Regulator Output Voltage vs
Temperature
3.082
3.081
3.080
3.079
3.078
3.077
3.076
3.075
3.074
3.073
3.072
1000
900
800
700
600
500
400
300
200
100
0
3.077
3.076
T
A
= 27°C
I
= 0
REG
V
= 16V
DD
V
DD
= 16V
V
= 16V
DD
3.075
V
DD
= 12V
V
DD
= 12V
V
DD
= 4.5V
3.074
3.073
3.072
3.071
V
DD
= 12V
V
= 4.5V
DD
V
= 4.5V
DD
3.070
0.5 1.0 1.5 2.0 2.5
LOAD CURRENT (mA)
3.5 4.0
0
10 20 30
50
70 80 90
0
3.0
40
60
70
0
10 20 30 40 50 60
80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
1325 G01
1325 G02
1325 G03
DAC Output Voltage vs
Temperature
Shutdown Current vs Temperature
Charge Current vs Battery Voltage
180
160
140
120
100
80
160
140
120
100
80
25
VR1 = 1, VR0 = 1
VR1 = 1, VR0 = 1
V
DD
= 16V
20
15
V
= 12V, R
= 1Ω,
SENSE
DD
L = 100µH, P1: IRF9531
V
DD
= 12V
V
DD
= 12V
VR1 = 1, VR0 = 0
10
5
60
VR1 = 1, VR0 = 0
VR1 = 0, VR0 = 1
60
VR1 = 0, VR0 = 1
40
40
20
20
V
DD
= 4.5V
VR1 = 0, VR0 = 0
VR1 = 0, VR0 = 0
0
0
0
40
TEMPERATURE (°C)
60
70
0
10
20
30
50
0
4
6
8
10
12
2
0
10 20 30 40 50 60 70 80 90
BATTERY VOLTAGE (V)
TEMPERATURE (°C)
1325 G05
1325 G04
1325 G06
Gas Gauge Gain and Offset vs
Temperature
Fault Comparator Threshold vs
Temperature
Fault Comparator Threshold vs
Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
11
10
9
0
V
= –0.2V AND –0.4V
SENSE
V
BAT
FOR BATP = HIGH, V = 12V
DD
–0.5
INCLUDES CHANGES IN V
WITH TEMPERATURE
REG
V
CELL
FOR EDV = HIGH
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
8
7
V
CELL
FOR MCV = HIGH, V
TBAT
= 2.8V AND
LTF
MCV
6
GAS GAUGE OFFSET
V
FOR LTF = HIGH, V = 2.8V
V
TBAT
FOR HTF = HIGH, V
= 0.4V
5
HTF
V
FOR MCV = HIGH, V
TBAT
= 1.6V
CELL
MCV
LTF
4
V
FOR LTF = HIGH, V = 1.6V
3
GAS GAUGE GAIN
V
CELL
FOR BATR = HIGH
V
TBAT
FOR HTF = HIGH, V
= 1.35V
HTF
2
1
–4.5
0
40
TEMPERATURE (°C)
60 70
0
40
TEMPERATURE (°C)
60 70
10 20 30
50
80
10 20 30
50
80
0
10 20 30 40 50
80
60 70
TEMPERATURE (°C)
1325 G07
1325 G08
1325 G09
4
LTC1325
U W
TYPICAL PERFORMANCE CHARACTERISTICS
PGATE Fall Time vs
Load Capacitance
PGATE Rise Time vs
Load Capacitance
Differential Nonlinearity
1000
900
800
700
600
500
400
300
200
1200
1000
800
600
400
200
0
1.0
0.5
V
CLK
= 12V
= 500kHz
DD
f
T
= 27°C
A
T
= 27°C
= 0°C
A
T
= 70°C
T
= 70°C
A
A
0
T
= 0°C
A
T
A
–0.5
–1.0
100
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
512
0
128
384
640 768
1024
896
256
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
CODE
LTC1325 G11
1325 G10
1325 G12
Discharge Rise and Fall Time
vs Load Capacitance
Minimum Charging Supply vs
Number of Cells
Integral Nonlinearity
14
12
10
16
14
12
10
8
1.0
0.5
T
T
T
= 70°C
= 27°C
= 0°C
R
= 0.15, VR1 = 1,VR0 = 1
V
f
= 12V
= 500kHz
A
A
A
SENSE
DD
CLK
L = 10µH TO 100µH
RISE TIME
IRF9Z30PFET, 1N5819 DIODE
8
6
4
2
0
R
= 1, VR1 = 1, VR0 = 1
SENSE
6
FALL TIME
L = 25µH TO 100µH
IRF9Z30PFET, 1N5819 DIODE
4
–0.5
–1.0
2
T
= 27°C, NiCd BATTERIES
CELL
A
V
= 1.4V NOMINAL
0
0
2
3
4
5
6
8
1
7
0
6
10 12 14 16 18 20
0
128
384 512 640 768
CODE
1024
896
2
4
8
256
LOAD CAPACITANCE (nF)
NUMBER OF CELLS
1325 G14
1325 G13
1325 G15
CLK to DOUT Enable Delay Time
vs Temperature
Oscillator Frequency vs
Temperature
CLK to DOUT Valid Delay Time
vs Temperature
500
450
400
350
300
250
200
150
100
50
118
117
116
115
114
113
112
111
110
109
108
700
600
D
OUT
GOING HIGH
500
D
OUT
GOING LOW
400
300
200
100
0
0
10 20 30 40 50
70
80
70
0
60
0
40
TEMPERATURE (°C)
60
–40
0
20
60
80 100
10 20 30
50
80
40
–20
TEMPERATURE (°C)
TEMPERATURE (°C)
1325 G18
1325 G17
1325 G16
5
LTC1325
U
U
U
PIN FUNCTIONS
SENSE (Pin 11): The Sense pin controls the switching of
the 111kHz PWM constant current source in the charging
mode. The Sense pin is connected to an external sense
resistor RSENSE and the negative side of the battery. The
charging loop forces the average voltage at the Sense pin
REG (Pin 1): Internal Regulator Output. The regulator
provides a steady 3.072V to the internal analog circuitry
and provides a temperature stable reference voltage for
generating MCV, HTF, LTF and thermistor bias voltages
withexternalresistors. Requiresa4.7µForgreaterbypass
capacitor to ground.
to equal a programmable internal reference voltage VDAC
The battery charging current is equal to VDAC/RSENSE
.
.
DOUT (Pin 2): TTL Data Output Signal for the Serial
Interface. DOUT and DIN may be tied together to form a
3-wire interface, or remain separated to form a 4-wire
interface. Data is transmitted on the falling edge of CLK
(Pin 5).
In the gas gauge mode the voltage across the Sense pin
is filtered by an RC network (RF and CF), amplified by
an inverting gain of four, then multiplexed to the ADC so
the average discharge current through the battery may
be measured and the total charge leaving the battery
calculated.
DIN (Pin 3): TTL Data Input Signal for the Serial Interface.
The data is latched into the chip on the rising edge of the
CLK (Pin 5).
VIN (Pin 12): General Purpose ADC Input.
TAMB (Pin 13): Ambient Temperature Input. Connect to an
external thermistor network. Tie to REG if not used. May
be used as another general purpose ADC input.
CS (Pin 4): TTL Chip Select Signal for the Serial Interface.
CLK (Pin 5): TTL Clock for the Serial Interface.
LTF (Pin 6): Minimum Allowable Battery Temperature
Analog Input. LTF may be generated by a resistive divider
between REG (Pin 1) and ground.
TBAT (Pin 14): Battery Temperature Input. Connect to an
external NTC thermistor network. Tie to REG if not used.
VBAT (Pin 15): Battery Input. An internal voltage divider is
connected between the VBAT and Sense pins to normalize
all battery measurements to one cell voltage. The divider
is programmable to the following ratios: 1/1, 1/2, 1/3 . . .
1/15, 1/16. In shutdown and gas gauge modes the divider
is disconnected.
MCV (Pin 7): Maximum Allowable Cell Voltage Analog
Input. MCV may be generated by a resistive divider be-
tween REG (Pin 1) and ground.
HTF (Pin 8): Maximum Allowable Battery Temperature
Analog Input. HTF may be generated by a resistive divider
between REG (Pin 1) and ground.
DIS (Pin 16): Active High Discharge Control Pin. Used
to turn on an external transistor which discharges the
battery.
GND (Pin 9): Ground.
FILTER (Pin 10): The external filter capacitor CF is con-
nected to this pin. The filter capacitor is connected to the
outputoftheinternalresistivedivideracrossthebatteryto
reduce the switching noise while charging. In the gas
gauge mode, CF along with an internal RF = 1k form a
lowpass filter to average the voltage across the sense
resistor.
PGATE (Pin 17): FET Driver Output. Swings from GND
to VDD.
VDD (Pin 18): Positive Supply Voltage. 4.5V < VDD < 16V.
6
LTC1325
W
BLOCK DIAGRAM
18
V
DD
DIGITAL INPUT CIRCUITS
5V
3.072V
ANALOG
REGULATOR
PS
1
DIGITAL
REG
REGULATOR
ANALOG AND DIGITAL V
ADC REFERENCE
DD
16
DIS
BATP, BATR, FMCV,
t
9
OUT
FEDV, FHTF, FLTF, t
OUT
6
8
7
GND
LTF
7
HTF
MCV
5
4
3
2
FAULT
DETECT
CIRCUITRY
MOD0 TO MOD1, PS
3
CONTROL
LOGIC
CLK
CS
SERIAL
I/O
D
IN
D
OUT
DS0 TO DS1
SGL/DIFF
PS, MSBF
2
3
10
12
13
14
15
V
IN
T
T
AMB
BAT
DIV0 TO DIV3
V
BAT
4
10-BIT
A/D CONVERTER
ADC
MUX
5
MOD0 TO MOD1, VR0 TO VR1, PS
CHARGE
GAS GAUGE
11
10
17
SENSE
FILTER
PGATE
CHARGE LOOP
AND
GAS GAUGE
PS
111kHz
OSCILLATOR
DIVIDER
T
DR0 TO DR3
DUTY RATIO
GENERATOR
OUT
3
TIMEOUT LOGIC
3
LTC1325 • BD
TO0 TO TO2
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Load Circuit for tdis and ten
1.4V
TEST POINT
3k
5V t WAVEFORM 2, t
dis
en
3k
D
OUT
D
OUT
t
dis
WAVEFORM 1
100pF
100pF
LTC1325 • TC01
LTC1325 • TC02
7
LTC1325
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
2.4V
CLK
0.8V
0.4V
t
dDO
t
r
t
f
2.4V
LTC1325 • TC04
D
OUT
0.4V
LTC1325 • TC03
On and Off Channel Leakage
Voltage Waveforms for tdis
3.072V
2V
I
ON
A
CS
ON CHANNEL
D
OUT
WAVEFORM 1
(SEE NOTE 1)
I
90%
10%
OFF
A
OFF
t
dis
}
CHANNELS
D
OUT
WAVEFORM 2
(SEE NOTE 2)
NOTE: EXTERNAL CHANNELS ONLY––
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS
SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY CS.
LTC1325 • TC05
T
, T
AND V
BAT AMB
IN
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS
SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY CS.
LTC1325 • TC06
Voltage Waveforms for ten
CS
D
START
IN
VR1
CLK
0.4V
1
21
22
23
24
t
en
THREE-STATE
NULL
0.4V
D9
D
OUT
LTC1325 • TC07
8
LTC1325
W U
W
TI I G DIAGRA
MSB-FIRST DATA (MSBF = 1)
CS
CLK
START
MSBF
D
IN
NULL
D9
BATP
D1 D0
FS
HI-Z
HI-Z
D
OUT
CS
COMMAND WORD
ADC DATA
STATUS WORD
MSB-FIRST DATA (MSBF = 0)
CLK
START
HI-Z
VR1
D
IN
BATP
D9
FS
NULL
D9
HI-Z
D
OUT
D1 D0 D1
ADC DATA
LTC1325 • TD
COMMAND WORD
STATUS WORD
NOTE: THE TIMING DIAGRAM SHOWS TWO POSSIBLE COMMAND WORDS.
REFER TO FUNCTIONAL DESCRIPTION FOR INFORMATION ON HOW TO
CONSTRUCT THE COMMAND WORD
U
U
U
FUNCTIONAL DESCRIPTIO
GENERAL DESCRIPTION
During the discharge mode, the battery is discharged by
an external transistor and series resistor. The battery is
monitored for fault conditions.
During normal operation, a command word is shifted into
the chip via the serial interface, then an ADC measurement
is made and the 10-bit reading and chip status word are
shifted out. The command word configures the LTC1325
andforcesitintooneoffivemodes:powershutdown, idle,
discharge, charge or gas gauge mode.
In the charge mode, the µP monitors the battery’s voltage,
temperature and ambient temperature via the 10-bit ADC.
Termination methods such as –∆VBAT, ∆VBAT/∆Time,
∆TBAT, ∆TBAT/∆Time, ∆(TBAT – TA), maximum tempera-
ture, maximumvoltageandmaximumchargetimemaybe
accurately implemented in software. The LTC1325 also
monitors the battery for fault conditions.
In the power shutdown mode, the analog section is turned
off and the supply current drops to 30µA. The voltage
regulator, which provides power to the internal analog
circuitry and external bias networks, is shut down. The
voltagedivideracrossthebatteryisdisconnectedandonly
the voltage regulator for the serial interface logic is left on.
In the gas gauge mode, the average voltage across the
sense resistor can be measured to determine the average
battery load current. The sense voltage is filtered by an RC
circuit, multiplied by an inverting gain of four, then con-
verted by the ADC. The µP can then accumulate the ADC
measurements and do a time average to determine the
total charge leaving the battery. The RC circuit consists of
an internal 1k resistor RF and an external capacitor CF
connected to the Filter pin.
During the idle mode, the chip is fully powered but the
discharge, charge, and gas gauge circuits are off. The chip
may be placed in the idle mode momentarily while charg-
ing the battery, allowing an ADC measurement to be made
withoutanyswitchingnoisefromthePWMcurrentsource
affectingtheaccuracyofthe reading. The modecommand
bits are picked off as they appear at DIN, allowing the
charging loop to turn off and settle while the remainder of
the command word is being shifted in.
9
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
COMMAND WORD
Bit 5: MSB-First/LSB-First (MSBF)
The command word is 22 bits long and contains all the
information needed to configure and control the chip. On
power-up all bits are cleared to logical “0.”
The ADC data is programmed for MSB-first or LSB-first
sequence using the MSBF bit. See Serial I/O description
for details.
1
2
3
4
5
6
7
8
MSBF
DESCRIPTION
START
= 1
SGL/
DIFF
MOD0 MOD1
10 11
MSBF DS0
DS1
DS2
0
1
LSB-First Data Follows MSB-First Data
MSB-First Data Only
9
12
13
14
15
16
DIV0 DIV1 DIV2
PS
DR0
DR1
DR2
DIV3
Bits 6 to 8: ADC Data Input Select (DS0 to DS2)
DS2, DS1 and DS0 select which circuit is connected to the
ADC input. Do not use unlisted combinations.
17
18
19
20
21
22
FSCLR TO0
TO1
VR0
VR1
TO2
LTC1325 • F01
DS2
0
0
DS1
0
0
DS0
0
1
DESCRIPTION
Figure 1. Command Word
Gas Gauge Output
Battery Temperature Pin, T
Bit 1: Start Bit (Start)
BAT
0
1
0
Ambient Temperature Pin, T
AMB
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeros which precede this logical
one will be ignored. After the start bit is received, the
remaining bits of the command word will be clocked in.
0
1
1
0
1
0
Battery Divider Output Voltage, V
CELL
V Pin
IN
Bits 9 to 12: Battery Divider Ratio Select (DIV0 to DIV3)
DIV3, DIV2, DIV1 and DIV0 select the division ratio for the
voltage divider across the battery.
Bits 2 and 3: Mode Select (MOD0 and MOD1)
Thetwomodebitsdeterminewhichoffourmodesthechip
will be in: idle, discharge, charge or gas gauge.
DIV3
0
DIV2
0
DIV1
0
DIV0
0
DESCRIPTION
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
)/1
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
0
0
0
1
)/2
MOD1
MOD0
DESCRIPTION
Idle
Discharge
Charge
0
0
0
0
1
1
0
1
)/3
)/4
0
0
1
1
0
1
0
1
0
1
0
0
)/5
0
0
1
1
0
1
1
0
)/6
)/7
Gas Gauge
0
1
1
0
1
0
1
0
)/8
)/9
Bit 4: Single-Ended Differential Conversion (SGL/DIFF)
1
0
0
1
)/10
)/11
)/12
)/13
)/14
)/15
)/16
SGL/DIFF determines whether the ADC makes a single-
ended measurement with respect to ground or a differen-
tial measurement with respect to the Sense pin.
1
1
0
0
1
1
0
1
1
1
0
0
SGL/DIFF
DESCRIPTION
1
1
1
1
0
1
1
0
0
1
Single-Ended ADC Conversion
Differential ADC Conversion (with respect to Sense)
1
1
1
1
10
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
Bits 21 and 22: Charging Loop Reference Voltage
Bit 13: Power Shutdown (PS)
Select (VR0 and VR1)
PS selects between the normal operating mode, or the
shutdown mode.
VR1 and VR0 select the desired reference voltage VCHRG
for the charging loop. The charging loop will force the
average voltage at the Sense pin to be equal to VDAC. The
average charging current is VDAC/RSENSE (see Figure 4).
PS
0
DESCRIPTION
Normal Operation
1
Shutdown All Circuits Except Digital Inputs
VR1
0
VR0
0
V
18
(mV)
DAC
Bits 14 to 16: Duty Ratio Select (DR0 to DR2)
0
1
34
DR2, DR1 and DR0 select the duty cycle of the charging
loop operation (not 111kHz PWM duty cycle). The last
three selections place the chip into a test mode and should
not be used.
1
0
55
1
1
160
STATUS WORD
DR2
0
0
DR1
0
0
DR0
0
1
DESCRIPTION
1/16
1/8
The status word is 8 bits long and contains the status of
the internal fail-safe circuits.
0
0
1
1
0
1
1/4
1/2
1
2
3
4
5
6
7
8
1
0
0
1
BATP BATR FMCV FEDV FHTF FLTF
t
FS
OUT
1
1
1
0
1
1
1
0
1
Test Mode 1
Test Mode 2
Test Mode 3
LTC1325 • F02
Figure 2. Status Word
Bit 17: Fail-Safe Latch Clear (FSCLR)
Bit 1: Battery Present (BATP)
When FSCLR bit is set to one, the internal fail-safe timer is
reset to 0, and the fail-safe latches are reset. FSCLR is
automatically reset to 0 when CS goes high.
The BATP bit = 1 indicates the presence of the battery. The
bit is set to 1 when the voltage at the VBAT pin falls below
(VDD – 1.8V). BATP = 0 when the battery is removed and
VBAT is pulled high by RTRK (see Figure 3).
FSCLR
DESCRIPTION
0
1
No Action
Reset Fail-Safe Timer and Latches
BATP
CONDITIONS
(V – 1.8) < V
0
1
< V
DD
DD
BAT
V
< (V – 1.8)
DD
BAT
Bits 18 to 20: Timeout Period Select (TO0 to TO2)
TO2, TO1 and TO0 select the desired fail-safe timeout
period,tOUT.Onpower-up,thedefaulttimeoutis5minutes.
Bit 2: Battery Reversed (BATR) or Shorted
The BATR bit indicates when the battery is connected
backwards or shorted. The bit is set when the battery cell
voltage at the output of the battery divider VCELL is below
100mV.
TO2
0
TO1
0
TO0
0
TIMEOUT (MINUTES)
5
0
0
1
10
0
1
0
20
0
1
1
40
BATR
CONDITIONS
1
1
1
0
0
1
0
1
0
80
160
320
0
1
V
V
> 100mV
< 100mV
CELL
CELL
1
1
1
Indefinite (No Timeout)
11
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
Bit 3: Maximum Cell Voltage (FMCV)
T
CONDITIONS
No Timeout Has Occurred
Timeout Has Occurred
OUT
0
The MCV bit indicates when the battery cell voltage has
exceeded the preset limit. The bit is set when VCELL is
greater than the voltage at the MCV pin.
1
Bit 8: Fail-Safe Occurred (FS)
FMCV
CONDITIONS
The FS bit indicates that one of the fault detection circuits
halted the discharging or charging cycle. The bit is set
when an EDV, LTF, HTF, or tOUT fault occurs during
discharge. During charging, the bit is set when a MCV,
LTF, HTF, or tOUT fault occurs. The bit is reset by the
command word bit FSCLR.
0
1
V
V
< V
> V
CELL
CELL
MCV
MCV
Bit 4: End Discharge Voltage (FEDV)
The EDV bit indicates when the battery cell voltage has
dropped below an internally preset limit. The bit is set
when the battery cell voltage at the output of the voltage
divider VCELL is less than 900mV.
FS
0
CONDITIONS
No Fail-Safe Has Occurred
Fail-Safe Has Occurred
1
FEDV
CONDITIONS
0
1
V
V
> 900mV
< 900mV
CELL
CELL
DETAILED DESCRIPTION
Fault Conditions
Bit 5: High Temperature Fault (FHTF)
The LTC1325 monitors the battery for fault conditions
before and during discharge and charge (see Figure 3).
They include: battery removed/present (BATP), battery
reversed/shorted(BATR),maximumcellvoltageexceeded
The HTF bit indicates when the battery temperature is too
high. Using a negative TC thermistor, the bit is set when
the voltage at the TBAT pin is less than the voltage at the
HTF pin.
V
DD
FHTF
CONDITIONS
V
DD
R
TRK
3.072V
LINEAR
REG
1.8V
0
1
T
T
> V
< V
BAT
BAT
HTF
HTF
+
–
REGULATOR
C1
C2
+
R1
R2
V
BATP
FMCV
BAT
–
Bit 6: Low Temperature Fault (FLTF)
PROGRAMMABLE
BATTERY
DIVIDER
The LTF bit indicates when the battery temperature is too
low. UsinganegativeTCthermistor, thebitissetwhenthe
voltage at the TBAT pin is greater than the voltage at the
LTF pin.
SENSE
MCV
+
–
REG
C3
C4
900mV
100mV
+
–
FLTF
0
1
CONDITIONS
FEDV
BATR
R3
R4
R
R
L
T
T
< V
> V
BAT
BAT
LTF
LTF
+
–
T
BAT
C5
C6
–
+
Bit 7: Timeout (tOUT
)
FHTF
FLTF
HTF
T
The tOUT bit indicates that the battery charging time has
exceeded the preset limit. The bit is set when the internal
timer exceeds the limit set by the command bits TO0, TO1
and TO2.
+
–
LTF
LTC1325 • F03
Figure 3. Fail-Safe or Fault Detection Circuitry
12
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
(MCV), minimum cell voltage exceeded (EDV), high tem-
perature limit exceeded (HTF), low temperature limit ex-
ceeded (LTF) and time limit exceeded (tOUT). When a fault
condition occurs, the discharge and charge loops are
disabled or prevented from turning on and the fail-safe bit
(FS) is set. The chip is reset by shifting in a new command
wordwiththefail-safeclearFSCLRbitset. The8-bitstatus
word contains the state of each fault condition.
The chip enters the discharge mode when the proper
mode command bits are set and the power shutdown
command bit is clear. If a fault condition does not exist,
then the DIS pin is pulled up to VDD by the internal driver.
The DIS voltage is used to turn on an external transistor
which discharges the battery through an external series
resistor RDIS
.
Discharging will continue until a new command word is
input to change the mode or a fault condition occurs.
Power Shutdown Mode
Command: MOD1 = X, MOD0 = X, PS = 1
Charge Mode
Status:
BATP = X, BATR = X, FMCV = X, FEDV = X,
FHTF = X, FLTF = X, tOUT = X
Command: MOD1 = 1, MOD0 = 0, PS = 0
Status:
BATP = 1, BATR = 0, FMCV = 0, FEDV = X,
FHTF = 0, FLTF = 0, tOUT = 0
In the power shutdown mode, the analog section is turned
off and the supply current drops to 30µA. The voltage
regulator, which provides power to the internal analog
circuitry and external bias networks, is shut down. The
voltage divider across the battery is disconnected and the
only circuit left on is the voltage regulator for the serial
interface logic.
The chip enters the charge mode when the proper mode
command bits are set and the power shutdown command
bit is clear. If a fault condition does not exist then charging
can begin. Charging will continue until a new command
word is input to change the mode or a fault condition
occurs.
Idle Mode
The charge current may be regulated by a programmable
111kHzPWMbuckcurrentregulator, orbyusingthePFET
to gate an external current regulator or current limited
transformer.
Command: MOD1 = 0, MOD0 = 0, PS = 0
Status:
BATP = X, BATR = X, FMCV = X, FEDV = X,
FHTF = X, FLTF = X, tOUT = X
111kHz PWM Controller
The chip enters the idle mode when the proper mode
command bits are set and the power shutdown command
bit is cleared. During the idle mode, the chip is fully
powered, butthedischarge, chargeandgasgaugecircuits
are off. The chip may be placed in the idle mode momen-
tarily while charging the battery, allowing an ADC mea-
surementtobemadewithoutanyswitchingnoisefromthe
PWMcurrentsourceaffectingtheaccuracyofthereading.
The mode command bits are picked off as they appear at
DIN, so that while the rest of the command word is being
shifted in, the charging loop has time to settle before an
ADC measurement is made.
The block diagram of the charging loop connected as a
PWM buck current regulator is shown in Figure 4. The
PWM may operate in either continuous or discontinuous
mode. The loop forces the average voltage across the
senseresistortobeequaltothevoltageattheoutputofthe
DAC, so that the charging current becomes VDAC/RSENSE
.
With switch S2 on and the others off, amplifier A1 along
with C1, R1 and R2 are configured as an integrator with
16kHz bandwidth. The output of the integrator is the
average difference between the voltage across the sense
resistor and the DAC output voltage.
Discharge Mode
Therisingedgeoftheoscillatorwaveformtriggerstheone
shot which sets the flip-flop output high. This turns on the
external PFET P1 by pulling its gate low via the FET driver.
With P1 on, the current through the inductor L1 starts to
Command: MOD1 = 0, MOD0 = 1, PS = 0
Status:
BATP = 1, BATR = 0, FMCV = X, FEDV = 0,
FHTF = 0, FLTF = 0, tOUT = 0
13
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
V
DD
4.5V TO 16V
CHARGE
PGATE
DIS
P1
R
R
TRK
DIS
IRF9Z30
D1
3
DR0 TO
DR2
DUTY RATIO
GENERATOR
DISCHARGE
1N5818
L1
111kHz
OSCILLATOR
GG
BATTERY
N1
IRFZ34
R1
500k
R2
125k
R
F
ONE SHOT
1k
SENSE
S1
Q
S
R
C1
16pF
C
F
R
SENSE
S2
S3
S4
+
–
FILTER
A2
–
+
REG
3.072V
TO
ADC MUX
A1
GG VR1 VR0 DAC VOLTAGE
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
18mV
34mV
55mV
160mV
0mV
V
DAC
DAC
2
VR0, VR1
GG
CHIP
(GAS GAUGE) BOUNDARY
LTC1325 • F04
Figure 4. Charging Loop Block Diagram
rise as does the voltage across the sense resistor. When
the voltage across the sense resistor is greater than the
output of the integrator, comparator A2 changes state.
This resets the flip-flop and P1 is turned off. Catch diode
D1 clamps the drain of P1 one diode drop below ground
when the inductor flies back and the current through the
inductor starts to drop. The voltage across the sense
resistor also drops and may reach zero and stay there until
the next clock cycle begins.
ample, if a duty ratio of 1/2 is programmed, the generator
output is low only for 42/2 = 21 seconds. Since the loop
operates for only 21 out of every 42 seconds, the average
charging current is halved. In general, the average charg-
ing current is:
ICHRG = VDAC(Duty Ratio)/RSENSE
Gated PFET Controller
When using an external current regulator or current lim-
ited wall pack, simply remove the inductor L1 and catch
diode D1. Set the DAC control bits VR1 = 1 and VR0 = 1,
and select the desired duty ratio. By insuring that the
voltage at the Sense pin is never greater than 140mV, the
output of the integrator A1 will saturate high and the
comparator A2 will never trip and turn the loop off. This
can be achieved by removing the sense resistor and
grounding the Sense pin or if the gas gauge is to be used,
The average charging current is set by the output of the
DAC (VDAC) and the duty ratio generator. VDAC can be
programmed to one of four values with the following
ratios: 1, 1/3, 1/5 or 1/10. The duty ratio can be set to
1/16, 1/8, 1/4, 1/2 or 1. When the duty ratio is 1, the duty
ratio generator output is always low and the charge loop
operates continuously (see Figure 4). At other duty ratio
settings, the duty generator output is a square wave with
a period of 42 seconds. The time for which the generator
output is low varies with the duty ratio setting. For ex-
selecting RSENSE so that RSENSE CHRG < 140mV.
/I
14
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
Gas Gauge Mode
duplex operation, DIN and DOUT may be tied together
allowing transmission over just three wires: CS, CLK and
DATA (DIN/DOUT).
Command: MOD1 = 1, MOD0 = 1, PS = 0
Status:
BATP = X, BATR = X, FMCV = X, FEDV = X,
FHTF = X, FLTF = X, tOUT = X
Data transfer is initiated by a falling chip select CS signal.
After CS falls, the LTC1325 looks for a start bit on DIN. The
start bit is the first “logical one” clocked into the DIN input
after CS goes low. The LTC1325 will ignore all leading
zeros which precede this logical one. After the start bit is
received, the 21 other control bits are shifted into the DIN
pin to configure the LTC1325 and start a conversion. After
the last command bit, the DOUT pin remains in three-state
for one clock period before it is taken low for one null bit.
Following the null bit, the conversion results and the 8
statusbitsareshiftedoutontheDOUT pin. Attheendofthe
data exchange, CS should be brought high.
In the gas gauge mode, the average voltage across the
sense resistor can be measured to determine the average
batteryloadcurrent.TheoutputoftheDACissettoground
and switches S1, S3 and S4 are closed. A1 is configured
as an inverting amplifier with R1 and R2 setting the gain
to –4. The voltage across the sense resistor is filtered by
an RC circuit (RF, CF) amplified by A1, then converted by
the ADC.
The microprocessor can then accumulate the ADC mea-
surements and do a time average to determine the total
charge leaving the battery. The Sense pin voltage should
not be more negative than –450mV to ensure linearity.
MSB-First/LSB-First (MSBF Control Bit)
The output data of the LTC1325 is programmed for MSB-
first or LSB-first sequence using the MSFB control bit.
When MSBF = 1, data will appear on DOUT in MSB-first
format. This is followed by the 8 status bits. Logical zeros
will be filled in indefinitely following the last data bit to
accommodate longer word lengths required by some
microprocessors. When MSBF = 0, LSB-first data will
follow the MSB-first data. Regardless of the state of
MSBF, the status bits are always shifted out in the same
order (see Figure 2).
The RFCF circuit consists of an internal 1k resistor and an
external capacitor connected to the Filter pin. RFCF should
be longer than the measurement interval. With the serial
clock running at 100kHz, it take 380µs to shift in the
command word and shift out the ADC measurement and
status word.
Trickle Resistor
An external trickle resistor has several functions. First, it
provides a continuous trickle charge current for topping
offthebatteryandcounteringtheeffectsofself-discharge.
Second, it can be used to condition a deeply discharged
batteryforcharging.TheLTC1325willnotchargeabattery
unless its cell voltage is above 100mV (BATR). Finally, the
resistor is required by the battery detect circuit to pull the
VBAT pin high when the battery is removed.
Accommodating Microprocessors with Different Word
Lengths
The LTC1325 will fill zeros indefinitely after the transmit-
ted data until CS is brought high. At that time DOUT is
disabled (three-stated). This makes for easy interfacing
to MPU serial ports with different transfer increments
including 4 bits (e.g., COP400) and 8 bits (e.g., SPI and
MICROWIRE/PLUSTM). Any word length can be accom-
modated by the correct positioning of the start bit in the
input word.
SERIAL INTERFACE
The LTC1325 communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface. The clock CLK synchronizes the
data transfer with each bit being transmitted on the falling
edgeandcapturedontherisingCLKedgeinbothtransmit-
ting and receiving systems. The LTC1325 first receives
input data and then transmits back the A/D conversion
result and status word (half duplex). Because of the half
Operation with DIN and DOUT Tied Together
The LTC1325 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
MICROWIRE/PLUS is a trademark of National Semiconductor Corp.
15
LTC1325
U
U
U
FUNCTIONAL DESCRIPTIO
communicate with the microprocessor. Data is transmit-
ted in both directions on a single wire. The processor pin
connectedtothisdatalineshouldbeconfigurableaseither
an input or an output. The LTC1325 will take control of the
data line and drive it low after the 23rd falling CLK edge
after the start bit is received. Therefore the processor port
must be switched to an input before this happens to avoid
a conflict.
RT
RTO
1
T
1
TO
= exp β
−
(2)
(3)
(4)
(5)
(6)
β − 2TO
β + 2TO
RL = RTO
TO
TO − T
RT
β = T
In
RTO
Power-Up After Shutdown
When a control word with the PS bit set to one is written
totheLTC1325, itentersshutdownmodeinwhichtheVDD
supply current is reduced to 30µA. In this mode the on-
chip 3V regulator and all circuits powered off it are shut
down. The only circuits that remain alive are DIN, CS and
CLK input buffers. To take the LTC1325 out from shut-
down mode, a high to low edge must be applied to the CS
pin. Either DIN or CLK must be low when CS is low to
prevent a false control word from being transmitted to the
LTC1325. The 3V output decays with a time constant of
300ms with CREG = 4.7µF. The microprocessor should
wait three seconds before applying a wake-up edge to the
CS pin to ensure proper power-up.
1 dRT
RT dT
α =
α =
−β
2
T
dV
dT
−β
1
TO
DIV
= V
T
–
+
DIV( )
O
(7)
2
2TO
where,
VDIV (T) is the output of the divider,
TEMPERATURE SENSING
VREG is the voltage at the REG pin (3.072V nominal),
RT is the thermistor resistance at some temperature T,
NTC (Negative Temperature Coefficient) Thermistors
R
TO is the thermistor resistance at some reference
The simplest method to sense temperature (battery or
ambient)withanNTCthermistoristouseavoltagedivider
powered by the REG pin. This divider consists of a load
resistor RL in series with a thermistor RT as shown in
Figure 3. For a given thermistor, there is a value of RL
which makes VDIV (T) linear over a narrow but adequate
temperature range. The easiest method (Inflection Point
Method) to calculate RL is to set the second temperature
derivativeofthedivideroutputto0.Theequationsrelevant
to this method are:
temperature TO,
β is a constant dependent on thermistor material,
α is the temperature coefficient (in %/°C) of RT at
TO, and
all temperatures are in °K (i.e., T°C + 273)
There are two assumptions in the derivation of the above
equations. β is assumed to be constant and the tempera-
ture coefficient of RL is small compared to that of the
thermistor.
V
T
( )
1
1+R
DIV
=
= f T
( )
Most thermistor data sheets specify RTO, β, RT/RTO ratios
for two temperatures, α, and tolerances for β and RTO.
Given β, and RTO, it is easy to calculate RL from equation
V
REG
L
(1)
R
T
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(3). Alternatively, β may be calculated from the RT/RTO
ratio using equation (4) or from α, using equation (6).
T = [2.605 – VDIV(T)]/0.034. The straight line approxima-
tion is accurate to within 2°C over a temperature range of
5°C to 45°C, assuming 3% β and 10% RTO tolerances.
As a numerical example, consider the Panasonic
ERT-D2FHL103Sthermistorwhichhasthefollowingchar-
acteristics:
PTC (Positive Temperature Coefficient) Thermistors
Positive Temperature Coefficient (PTC) thermistors may
be used in battery chargers that do not require accurate
temperature measurements. The resistance vs tempera-
ture characteristics of PTC exhibits a sharp increase at a
selectable switch temperature TS. This sharp change is
exploitedinchargerswhichuseTCO(TemperatureCutoff)
or ∆TCO (Difference between battery and ambient tem-
perature).WithTCOtermination,avoltagedividerconsist-
ingofaPTCandalowtemperaturecoefficientloadresistor
isconnectedbetweenREGandGNDwiththetopendofthe
PTC at REG. The PTC is mounted on the battery to sense
its temperature. The divider output is tied to TBAT. When
the switch temperature is reached, the PTC resistance
increases sharply causing TBAT to fall below HTF. This
causes an HTF fault and charging is terminated. To imple-
ment ∆TCO termination, theloadresistorcan, in principle,
be replaced by a matching PTC and the divider now
responds to differences between battery and ambient
temperature. With both TCO and ∆TCO terminations, the
position of the battery temperature PTC can be swapped
with the load resistor or ambient temperature PTC. In both
cases, an LTF fault terminates charge when the trip point
is reached. Note that in practice, matched PTCs are not
readily available and for ∆TCO termination, NTC ther-
mistors are recommended.
1. RT (25°C) = RTO = 10k
2. α = –4.6%/°C at TO = 25°C
3. Ratio R25/R50 = 2.9
Using equation (4) and R25/R50 = 2.9, β = (323 × 298)In
(2.9)/(298 – 323) = 4099k. Alternatively, using equation
(6) and α = –4.6%/°C, β = –(–0.046)(298)2 = 4085k.
Both values of β are close to each other. Substituting
β = 4085k into equation (3) gives RL = 10k [4085 – (2 ×
298)]/[4085 + (2 × 298)] = 7.45k. The nearest 1% resistor
value is 7.5k. Figure 5 shows a plot of VDIV(T) measured
at various temperatures for this thermistor with a 7.5k RL.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IDEAL
ACTUAL
–0.5
–60
–20
0
20
40
60
80
–40
TEMPERATURE (°C)
LTC1325 • F05
HARDWARE DESIGN PROCEDURE
Figure 5. ERT-D2FHL103S Divider
This section discusses the considerations in selecting
each component of a simple battery charger (see Figures
3 and 4). Further applications assistance is provided in
Application Note 64, using the LTC1325 Battery Manage-
ment IC.
There are two methods of calculating battery or ambient
temperature from ADC readings of the TBAT or TAMB
channels. The first method is to store the VDIV(T) vs T
curve as a lookup table. The second method is to use a
straight line approximation. The equation of this line may
be calculated from the slope dVDIV/dT at TO [see equation
(7)] and assuming that the line passes through the point
[TO, VDIV(TO)] on the curve. For the ERT-D2FHL103S, the
slope is minus 34mV/°C and the equation of the line is
1. RSENSE: There are three factors in selecting RSENSE
a. LTC1325 VREF and Duty Ratio Settings
b. Sense Resistor Dissipation
:
c. ILOAD(RSENSE) < –450mV for Gas Gauge Linearity
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between the VBAT and Sense pins and the internal
divider should be set to divide-by-1.
TheLTC1325hasfivedutyratioandfourVDAC settings
giving 20 possible charge rates (for a given value of
RSENSE) as shown in the following table. For any
combination of VDAC and duty ratio, the average
charging current is given by:
The minimum VDD supply must be greater than the
end-of-charge voltage VEC times the number of cells
(n) in the battery plus drops across the on-resistance
of the PFET, inductor (VL), battery internal resistance
AVG ICHRG = VDAC(Duty Ratio)/RSENSE
RINT and sense resistor RSENSE
.
DUTY RATIO
NORMALIZED
VDAC
1(VR1 = 1, VR0 = 1)
1/3(VR1 = 1, VR0 = 0)
1/5(VR1 = 0, VR0 = 1)
Minimum VDD should be the greater voltage of the
results from these two equations:
1
1
1/3
1/5
1/2
1/2
1/6
1/4
1/4
1/8 1/16
1/8 1/16
1/12 1/24 1/48
l/20 1/40 1/80
Min VDD = ICHRG[RDS(ON)(P1) + RSENSE
n(RINT)] + n(VEC) + VL
+
1/10
1/10(VR1 = 0, VR0 = 0) 1/10 1/20 1/40 1/80 1/160
or,
Note that the table entries give relative charge rates
assumingthattheVR1=1,VR0=1,dutyratio=1entry
isequivalenttoa1Cchargerate. Therefore, thecharge
rate (in C-units) for other VR1, VR0, and duty ratio
settings may be read directly from the table. In gen-
eral, the VR1 = 1, VR0 = 1, duty ratio = 1 entry can be
equivalent to any charge rate, say k times 1C. Then all
entries in the table should be multiplied by k. In
general, VDAC and duty ratio settings are changed by
the microprocessor to charge batteries of different
capacities or to alter charge rates when charging the
samebatteryinseveralstages.Forbestaccuracy,VR1
and VR0 should be set to 1 where possible.
Min VDD = n(VEC) + 1.8V
Assuming VEC = 1.6V, the LTC1325 will charge up to
8 cells with a 16V supply. Fora highernumberof cells,
an external level shifter and regulator are needed.
In some applications, there are other circuits attached
to the charging supply. When the charging supply
(VDC) is powered down or removed, the battery may
supplycurrenttothesecircuitsthroughthePFETbody
diode. To prevent this, a blocking diode can be added
in series with VDC as shown in the circuit in the Typical
Application section.
3. Inductor L: To minimize losses, the inductor should
have low winding resistance. It should be able to
handle expected peak charging currents without satu-
ration. If the inductor saturates, the charging current
is limited only by the total PFET RDS(ON), inductor
winding resistance, RSENSE and VDD source resis-
tance. This fault current may be high enough to
damage the battery or cause the maximum power
ratings of the PFET, inductor or RSENSE to be ex-
ceeded.
The power dissipation of the sense resistor varies
between charge, discharge and gas gauge modes and
should be calculated for all three modes. Typically,
dissipation is higher in discharge and gas gauge
modessincebatteriescandeliverhighercurrentsthan
they can be charged with.
In gas gauge mode, the load current supplied by the
battery should not exceed 450mV/RSENSE for the gas
gauge to remain linear in response. RSENSE should be
low enough to ensure that ILOAD(RSENSE) does not
fall below ground by more than 1 diode drop.
4. Catch Diode D1: The catch diode should have a low
forward drop and fast reverse recovery time to mini-
mize power dissipation. Total power loss is given by:
2. VDD Supply: VDD should be at least 1.8V above the
maximum battery voltage to prevent a BATP = 0 error
when the LTC1325 is in charge or discharge mode. If
this requirement cannot be met in a specific applica-
tion, an external battery divider should be connected
PdD1 = VF(IF) + (VR)(f)(tRR)(IF′)
18
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where,
d. Thermistor Divider Temperature Curve
IF = forward diode current,
Typical temperature limits for both NiCd and NiMH
batteries are shown below.
IF′ = forward diode current just prior to turn off,
VF = forward drop,
CHARGE TEMP
RANGE (°C)
DISCHARGE TEMP
BATTERY
TYPE
RANGE (°C)
VR=reversediodevoltage(approximatelyequaltoVDD),
f = PWM frequency (111kHz), and
tRR = reverse recovery time
MIN
–20
–20
–20
–20
MAX
MIN
0
MAX
Standard
Quick
Fast or Rapid
Trickle
45 to 50
45 to 50
45 to 50
45 to 50
45 to 50
45 to 50
45 to 50
45 to 50
10
15
0
The power and maximum reverse voltage ratings of the
diode should be greater than PdD1 and VDD respectively.
The catch diode should also have fast turn-on times to
reduce the voltage glitch at its cathode when turning on.
Note that the discharge limits are wider than the
charge limits. To prolong battery life, manufacturers
generally recommend discharge temperatures that
are similar to the charge limits. For this reason, the
LTC1325 recognizes the same LTF and HTF limits in
both charge and discharge modes. MCV should be set
just above the charging voltage per cell given in
battery specifications. The voltage at the LTF and HTF
pins should be set to correspond to narrowest tem-
perature range. These are typically 15°C and 45°C.
The corresponding voltages may be read from the
thermistor divider temperature curve such as that
shown in Figure 5. For this thermistor, it works out to
be about for 2.12V for LTF and for 1.13V for HTF. The
MCV may be conveniently tied to LTF since MCV is
typically2V.Ifdesired,externalanalogswitchesunder
microprocessor control may be used to vary the LTF,
HTF and MCV voltagesbetween modesor fordifferent
chargerates.ThevaluesofR1,R2,R3andR4inFigure
3 can be calculated from the following equations:
Schottky diodes have fast switching times and low
forward drops and are recommended for D1.
5. Trickle Resistor RTRK: RTRK sets the desired trickle
current in the battery to compensate for self-dis-
chargewhichisintheorder1%and2%ofcapacityper
day for NiCd and NiMH batteries respectively. Trickle
charge rates are typically in the C/30 to C/50 range,
where C is battery capacity.
I
TRK = (VDD – VBAT)/RTRK
where VBAT is the voltage of a full charged battery.
Note that ITRK varies as the battery is being charged.
6. Thermistor RT and Load RL: The total resistance of the
thermistor network should be greater than 30k at the
high temperature extreme to minimize effects of load
regulation (see REG pin loading).
R4 = VHTF(RE/VREG
)
7. FaultSettingResistorsR1,R2,R3andR4:Thevoltage
levels at the LTF, HTF and MCV pins are tapped from
a resistor divider powered by the REG pin. The voltage
levels are selected taking into account:
R3 = VMCV(RE – R4)
R2 = VLTF (RE) – (R3 + R4)
R1 = RE – (R2 + R3 + R4)
a. Manufacturer Recommended Temperature and
Voltage limits,
where RE = R1 + R2 + R3 + R4 is chosen to minimize
loading on the REG pin. A minimum value of 30k is
recommended.NotethatVLTF isassumedtobegreater
than VMCV. If this is not the case, VLTF and VMCV in the
above equations should be swapped. If the MCV and
LTF pins are shorted to the same point, R2 should be
set to 0.
b. Loading on the REG Pin (< 2mA)
c. Input Voltage Ranges of the LTF, HTF and MCV
Comparators:
1.6V < VLTF, VMCV < 2.8V and 0.5V < VHTF < 1.3V
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8. REG Pin Loading: The 3.072V regulator has a load
regulation specification of –5mV/mA. Since the ADC
uses the same regulator as reference, it is desirable to
reduce loading effects on the REG pin especially over
temperature. Thermistors with RTO values of at least
10k at 25°C are recommended. At 50°C, the ther-
mistor resistance could drop by a factor of 3 from its
value at 25°C. RL is chosen as explained in the section
on Temperature Sensing. The temperature coefficient
of RL is not critical since the thermistor tempco
dominates the sensing circuit.
PFET to within the maximum gate source voltage rating of
the latter. Finally, D2 clamps VBAT to 15V.
Charging Batteries with Voltages Above 16V
To charge a battery with a maximum (fully charged) voltage
of above 16V, the charging supply VDC must be above 16V.
Thus the charger will need the regulator, level shifter and
clamp mentioned in the previous section. In addition, an
external battery divider must be added to limit the voltage at
the VBAT pin to less than VDD. This is shown in the typical
application circuit, Wide Voltage Battery Charger. The resis-
tors R9 and R10 are selected to divide the battery voltage by
the number of cells in the battery and the battery divider
internal to the LTC1325 is set to divide-by-1. The external
dividerprevents VBAT fromeverrising to VDD andthis causes
the BATP (Battery Present Flag) to be high regardless of
whetherthebatteryisphysicallypresentornot.Thisdoesnot
affect the other operations of the LTC1325.
9. RDIS: RDIS is selected to limit the discharge current to
avaluewithinthebatterydischargespecificationsand
must have a power rating above IDIS2(RDIS) where:
IDIS = VBAT/[RDIS + RDS(ON)(N1)]
10. PFET(P1) and NFET(N1): For operation of the charge
and discharge loops, VGS < VDD since the PGATE
and DIS pins swing between 0 and VDD. VGS << VDD
to minimize power dissipation. The power ratings of
P1 and N1 should be above ICHRG2[RDS(ON)(P1)] and
IDIS2[RDS(ON)(N1)] respectively. VDS(MAX) should be
above VDD.
SOFTWARE DESIGN
A general charging algorithm consists of the following
stages:
Discharge Before Charge
Fast Charge
Charging from Supplies Above 16V
Top Off Charge
Trickle Charge
In many applications, the charging supply is greater than
the16VmaximumVDD ratingoftheLTC1325.TheLTC1325
can easily be adapted to charge the batteries from a
charging supply VDC that is above 16V by adding three
external sub-circuits:
Under some operating and storage conditions, NiCd and
NiMHbatteriesmaynotprovidefullcapacity. Inparticular,
repeated shallow charge and discharge cycles cause the
“memory effect” in NiCd batteries. In order to restore full
capacity (battery conditioning), these batteries have to be
subjected to several deep discharge/charge cycles which
will be provided by repetitions of the above algorithm.
1. A regulator to drop VDC down to within the supply
range of the LTC1325.
2. A level shifter between the PGATE and the gate of the
PFET, P1, to ensure that P1 can be completely turned
off when PGATE rises to VDD.
Figure 6 shows a simplified flowchart of a charging algo-
rithm. In practice, this flowchart has to be augmented to
take into account the occurrence of fail-safes at any point
in the algorithm. For example, the battery temperature
could rise above HTF during discharging or charging.
General programming notes are as follows:
3. A voltage clamp on the VBAT pin to prevent RTRK from
pulling VBAT above VDD.
The Wide Voltage Battery Charger circuit in the Typical
Applicationsectionshowslowcostimplementationsofall
three sub-circuits. C1, R11 and D4 generate a 15V VDD for
the LTC1325. D3, R12 and C2 form a level shifter. The
zener D3 is chosen to clamp the source gate voltage of the
1. The start bit is always high.
2. TheSGL/DIFFbitisgenerallysettolowsothattheADC
makes conversions with respect to ground.
20
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3. The MSBF bit is set depending on whether the micro-
during the same I/O operation (that FSCLR is set to 1)
should be checked to determine if faults were indeed
cleared, i.e., discharging or charging has begun. This
is not shown in the simplified flowchart of Figure 6.
For commands other than the START commands,
FSCLR should be set to 0 so as not to reset the timer.
processorclocksinserialdatawithMSB-orLSB-first.
4. The DS0 to DS2 bits can be anything except when
entering idle mode or when requesting for ADC read-
ings. In these cases, DS0 to DS2 are set to select the
desired reading: TBAT, VCELL or TAMB
.
8. The TO0 to TO2 bits should all be set to 1 in discharge
mode to ensure discharge does not end prematurely
due to a timeout fault. During Fast charge or Top Off
charge, these bits are set to a value suitable for the
charge rate used. For example, if the charge rate is 1C,
the timeout period should be set to 80 minutes.
5. The PS bit should always be 0 so that the LTC1325
does not go into shutdown mode.
6. The DR0 to DR2 should not select any of the test modes.
It may assume different settings between Fast charge
and Top Off charge in order to alter the charging current.
9. Inchargemode, theCF capacitorfilterstheVCELL node
and sees a small ripple due to ripple at the Sense pin.
Prior to taking an ADC reading, the LTC1325 is put in
7. TheFSCLRbitshouldbesetto1toclearanyfaultsand
reset the timer when starting Discharge, Fast charge
or Top Off. The status bits that the LTC1325 returns
START
NO
CONDITIONING?
YES
START
DISCHARGE
START
TOP OFF CHARGE
WAIT
WAIT
READ
STATUS
RESUME
IDLE MODE
TOP OFF CHARGE
NO
EDV = 1?
READ ADC
AND STATUS
YES
START
FAST CHARGE
NO
TERMINATE?
WAIT
YES
IDLE MODE
AND WAIT
RESUME
FAST CHARGE
IDLE MODE
AND WAIT
MORE
CONDITIONING?
YES
READ ADC
AND STATUS
NO
NO
YES
END
LTC1325 • F06
TERMINATE?
Figure 6. Simple Charging Algorithm
21
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idle mode to minimize noise. The microprocessor
should either disregard readings or wait for a second
or so before taking a reading. This is to allow VCELL to
decay to the correct cell voltage. The worst case time
constant is 150kΩ(CF).
wiper on a potentiometer between these two. Table 1
illustrates a complete 6-byte exchange. Note that the first
byte is padded with zeroes to align the A/D data and status
with byte boundaries.
SPCR = (SPIE = 0, SPE = 1, DWOM = 0, MSTR = 1,
CPOL = 0, CPHA = 0, SPR1 = 0, SPR0 = 1)
10. Prior to the first START command, the battery divider
setting may be incorrect so that CF may charge to a
voltage that causes EDV, BATR or MCV faults. The
worst case time constant is as in (9). The micropro-
cessor should check faults during the transmission of
a START command and resend the START command
again when CF has been given enough time to charge
up to the correct value.
DDRD = (BIT7 = 0, BIT6 = 0, DDR5 = 1, DDR4 = 1,
DDR3 = 1, DDR2 = 0, DDR1 = 0, DDR0 = 1)
Table 1. 6-Byte Exchange SPI Communication with LTC1325
5V
68HC11
SS
LTC1325
CLK
SCK
MOSI
MICROPROCESSOR INTERFACES
D
IN
CS
D
PORTD.0
MISO
TheLTC1325caninterfacedirectlytoeithersynchronous,
serial or parallel I/O ports of most popular microproces-
sors. With a parallel port, 3 or 4 I/O lines can be pro-
grammed to form a serial link to the LTC1325.
OUT
BYTE #1 TX
BYTE #1 RX
BYTE #2 TX
BYTE #2 RX
BYTE #3 TX
BYTE #3 RX
BYTE #4 TX
BYTE #4 RX
BYTE #5 TX
BYTE #5 RX
BYTE #6 TX
0
X
0
0
0
0
X
0
X
START MOD0
Motorola SPI (68HC11)
X
X
X
X
X
The 68HC11 has a dedicated synchronous serial interface
called the Serial Peripheral Interface (SPI) which transfers
datawithMSB-firstandin8-bitincrements.Tocommunicate
with this microprocessor, the LTC1325 MSBF control bit
shouldbesetto1.TheSPIhasfourlines:MasterInSlaveOut
(MISO), Master Out Slave In (MOSI), Serial Clock (SCK) and
Slave Select (SS). The 68HC11 is configured as a Master by
tying the SS line high. A control byte is written to the Serial
Peripheral Control Register (SPCR) to select master mode,
set baud rate and clock timing relationship. Another byte is
written to the Port D Direction Register (DDRD) to set MOSI,
SCK and bit 0 (CS of LTC1325) as outputs. The 68HC11
clocks in data from the LTC1325 simultaneously under the
control of SCK. The microprocessor transmits the LTC1325
commandwordin4bytes.Thisisfollowedby2moredummy
bytes (with all bits set low) in order to clock in the remaining
LTC1325 ADC and status bits.
SGL/
DIFF
MOD1
X
MSBF DS0
DS1
X
DS2
X
DIV0 DIV1
X
X
PS
X
X
DR0
X
X
X
DIV2 DIV3
DR1
X
DR2 FSCLR TO0
X
TO1
X
X
TO2
X
X
0
X
0
X
0
VR0
X
VR1
X
0
X
0
D9
X
D8
X
X
X
X
X
X
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
This software example allows you to verify communica-
tions with the LTC1325. The command word configures
the LTC1325 to perform an A/D conversion on the general
purpose VIN input. VIN can be tied to GND or REG or to a
BYTE #6 RX
BATP BATR FMCV FEVD FHTF FLTF
X = DON’T CARE
t
FS
0UT
LTC1325 • AI01
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LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
STAA
LDAA
STAA
LDX
#$51
$1028
#$39
Write control byte to the SPCR
LOOP4 TST
BPL
$1029
LOOP4
$102A
#$03
HIDATA
#$00
$102A
$1029
LOOP5
$102A
LODATA
#$00
$102A
$1029
LOOP6
$102A
STATUS
$08,X,#$01
CSLOW
Check for SPI transfer
complete bit
Get A/D high byte
Mask off unwanted bits
Store in user memory
Send dummy Byte #1
Setup Port D DDRD
Port D Bit 0 is CS
Load port base ADDR
Take CS low
Send Byte #1 (MSB) with
START bit
Check for SPI transfer
complete bit
Send Byte 2
LDAA
$1009
#$1000
$08,X,#$01
#$02
$102A
$1029
LOOP1
#$24
$102A
$1029
LOOP2
#$03
$102A
$1029
LOOP3
#$C0
ANDA
STAA
LDAA
STAA
CSLOW BCLR
LDAA
STAA
LOOP1 TST
LOOP5 TST
Check for SPI transfer
complete bit
Get A/D low byte
Store in user memory
Send dummy Byte #2
BPL
BPL
LDAA
STAA
LDAA
STAA
LDAA
STAA
LOOP2 TST
BPL
LDAA
STAA
LOOP3 TST
BPL
Check for SPI transfer
complete bit
Send Byte 3
LOOP6 TST
Check for SPI transfer
complete bit
Get STATUS byte
Store in user memory
Raise CS high
Loop for continuous readings
BPL
LDAA
STAA
BSET
BRA
Check for SPI transfer
complete bit
Send Byte 4
LDAA
STAA
$102A
U
TYPICAL APPLICATION
Wide Voltage Battery Charger
V
DC
25V
MBR320
NOTE 7
NOTE 1
NOTE 3
NOTE 1
R11
220Ω
1/2W
NOTE 2
D3
R12
100k
1N4740A
D1
1N5818
P1
IRF9Z30
+
D4
1N4744A
15V
C1
1µF
C2
0.1µF
R
TRK
L1
62µH
MPU
(e.g. 8051)
p1.4
REG
V
DD
D
OUT
D
IN
PGATE
DIS
R6
R13
R
DIS
p1.3
p1.2
CS
V
T
BAT
BAT
NOTE 5
R14
R9
CLK
LTF
MCV
HTF
GND
100Ω
C5
T
R1
AMB
0.1µF
NOTE 1
NOTE 4
+
C4
V
IN
NOTE 6
R10
22µF
SENSE
FILTER
THERM 2
R5
N1
IRF830
R2
R3
+
C
REG
4.7µF
THERM 1
V
BAT
R7
D2
LTC1325
1N4744A
15V
R8
100Ω
C
C3
500pF
F
R
SENSE
1µF
R4
NOTE 7: OPTIONAL DIODE TO PREVENT BATTERY
DRAIN WHEN THE CHARGING SUPPLY IS POWERED
DOWN (SEE SECTION 2, HARDWARE DESIGN
PROCEDURE).
NOTE 1: NEEDED WHEN V > 16V OR MAXIMUM
DC
NOTE 4: ZENER TO CLAMP V
TO BELOW V
.
DD
BAT
BATTERY VOLTAGE, V
> 16V.
OMIT WHEN V < 16V.
BAT
DC
NOTE 2: REGULATOR. OMIT THIS BLOCK AND SHORT
VDD TO V WHEN V < 16V.
NOTE 5: EXTERNAL BATTERY DIVIDER. NEEDED WHEN
MAXIMUM BATTERY VOLTAGE, V > 16V.
DC
DC
BAT
NOTE 6: V IS AN UNCOMMITTED A/D CHANNEL.
NOTE 3: LEVEL SHIFTER. OMIT THIS BLOCK AND SHORT
PGATE TO P1 GATE WHEN V < 16V.
IN
1325 TA02
DC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1325
PACKAGE DESCRIPTION
U
Dimension in inches (millimeters) unless otherwise noted.
N Package
18-Lead Plastic DIP
0.900*
(22.860)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
18
17
16
15
14
13
12
11
10
0.015
(0.381)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.325
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
–0.015
0.125
(3.175)
MIN
1
2
3
5
6
9
4
7
8
0.018 ± 0.003
+0.635
8.255
(0.457 ± 0.076)
(
)
–0.381
N18 0695
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S Package
18-Lead Plastic SOL
0.447 – 0.463*
(11.354 – 11.760)
14 13
11
15
12
10
18 17 16
0.291 – 0.299**
(7.391 – 7.595)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
0.010 – 0.029
× 45°
(2.362 – 2.642)
(0.254 – 0.737)
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
2
3
5
7
8
9
1
4
6
NOTE:
SW18 0695
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
1.3A, Li-Ion, NiCd, NiMH, Pb-Acid Charger
LT®1510
Constant Voltage/Constant Current Battery Charger
LT1512
SEPIC Constant Current/Constant Voltage Battery Charger 0.75A, V Greater or Less Than V
IN
BAT
LT/GP 0895 2K REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
24
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1994
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