LT1468CS8 [Linear]
90MHz, 22V/us 16-Bit Accurate Operational Amplifier; 90MHz的， 22V / us的16位的高精度运算放大器
| 型号： | LT1468CS8 |
| 厂家： | 
Linear |
| 描述： | 90MHz, 22V/us 16-Bit Accurate Operational Amplifier |
| 文件： | 总12页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1468
90MHz, 22V/µs
16-Bit Accurate
Operational Amplifier
U
DESCRIPTIO
FEATURES
The LT®1468 is a precision high speed operational ampli-
fier with 16-bit accuracy and 900ns settling to 150µV for
10V signals. This unique blend of precision and AC perfor-
mance makes the LT1468 the optimum choice for high
accuracy applications such as DAC current-to-voltage
conversion and ADC buffers. The initial accuracy and drift
characteristics of the input offset voltage and inverting
input bias current are tailored for inverting applications.
■
90MHz Gain Bandwidth, f = 100kHz
22V/µs Slew Rate
■
■
■
■
■
■
■
■
■
■
■
■
■
Settling Time: 900ns (AV = –1, 150µV, 10V Step)
Low Distortion, –96.5dB for 100kHz, 10VP-P
Maximum Input Offset Voltage: 75µV
Maximum Input Offset Voltage Drift: 2µV/°C
Maximum (–) Input Bias Current: 10nA
Minimum DC Gain: 1000V/mV
Minimum Output Swing into 2k: ±12.8V
Unity Gain Stable
Input Noise Voltage: 5nV/√Hz
Input Noise Current: 0.6pA/√Hz
Total Input Noise Optimized for 1k < RS < 20k
Specified at ±5V and ±15V
The 90MHz gain bandwidth ensures high open-loop gain
atfrequencyforreducingdistortion. Innoninvertingappli-
cations such as an ADC buffer, the low distortion and DC
accuracy allow full 16-bit AC and DC performance.
The 22V/µs slew rate of the LT1468 improves large-signal
performance in applications such as active filters and
instrumentation amplifiers compared to other precision
op amps.
U
APPLICATIONS
■
16-Bit DAC Current-to-Voltage Converter
The LT1468 is manufactured on Linear Technology’s
complementary bipolar process.
■
Precision Instrumentation
■
ADC Buffer
Low Distortion Active Filters
High Accuracy Data Acquisition Systems
Photodiode Amplifiers
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
■
■
U
TYPICAL APPLICATIO
Total Harmonic Distortion vs Frequency
–80
V
A
= ±15V
= 2
16-Bit DAC I-to-V Converter
S
V
L
R
= 2k
–90
–100
–110
–120
–130
V
= 10V
OUT
P-P
20pF
16
6k
DAC
INPUTS
–
+
2k
V
LT1468
OUT
LTC®1597
50pF
OPTIONAL NOISE FILTER
OFFSET: V + I (6kΩ) < 1LSB
SETTLING TIME TO 150µV = 1.7µs
SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE
OS
B
100
1k
10k
100k
1468 TA01
FREQUENCY (Hz)
1468 TA02
1
LT1468
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
Total Supply Voltage (V+ to V–) ............................... 36V
Maximum Input Current (Note 2) ......................... 10mA
Output Short-Circuit Duration (Note 3)............ Indefinite
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 4)... –40°C to 85°C
Junction Temperature........................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NULL
–IN
1
2
3
4
8
7
6
5
DNC*
LT1468CN8
LT1468CS8
LT1468IN8
LT1468IS8
+
V
+IN
V
OUT
–
V
NULL
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
*DO NOT CONNECT
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 190°C/W (S8)
1468
1468I
Consult factory for Military Grade parts.
TA = 25°C, VCM = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
V
Input Offset Voltage
±15V
±5V
30
50
75
175
µV
µV
OS
I
I
I
Input Offset Current
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
13
3
50
nA
nA
nA
OS
–
Inverting Input Bias Current
Noninverting Input Bias Current
Input Noise Voltage
±10
±40
B
B
+
–10
0.3
5
0.1Hz to 10Hz
f = 10kHz
µV
P-P
e
Input Noise Voltage
nV/√Hz
pA/√Hz
n
i
Input Noise Current
f = 10kHz
0.6
n
R
Input Resistance
V
= ±12.5V
CM
±15V
±15V
100
50
240
150
MΩ
kΩ
IN
Differential
C
Input Capacitance
±15V
4
pF
IN
Input Voltage Range +
±15V
±5V
12.5
2.5
13.5
3.5
V
V
Input Voltage Range –
±15V
±5V
–14.3
–4.3
–12.5
–2.5
V
V
CMRR
PSRR
Common Mode Rejection Ratio
V
V
= ±12.5V
= ±2.5V
±15V
±5V
96
96
110
112
dB
dB
CM
CM
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V = ±4.5V to ±15V
100
112
dB
S
A
V
V
V
V
= ±12.5V, R = 10k
±15V
±15V
±5V
1000
500
1000
500
9000
5000
6000
3000
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
L
= ±12.5V, R = 2k
L
= ±2.5V, R = 10k
L
= ±2.5V, R = 2k
±5V
L
V
Output Swing
R = 10k, V = ±1mV
±15V
±15V
±5V
±13.0
±12.8
±3.0
±2.8
±13.6
±13.5
±3.6
V
V
V
V
OUT
L
IN
R = 2k, V = ±1mV
L
IN
R = 10k, V = ±1mV
L
IN
R = 2k, V = ±1mV
±5V
±3.5
L
IN
I
I
Output Current
V
V
= ±12.5V
= ±2.5V
±15V
±5V
±15
±15
±22
±22
mA
mA
OUT
SC
OUT
OUT
Short-Circuit Current
V
= 0V, V = ±0.2V
±15V
±25
±40
mA
OUT
IN
2
LT1468
TA = 25°C, VCM = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
SR
Slew Rate
A = –1, R = 2k (Note 5)
±15V
±5V
15
11
22
17
V/µs
V/µs
V
L
Full-Power Bandwidth
Gain Bandwidth
Total Harmonic Distortion
Rise Time, Fall Time
Overshoot
10V Peak, (Note 6)
3V Peak, (Note 6)
±15V
±5V
350
900
kHz
kHz
GBW
THD
f = 100kHz, R = 2k
±15V
±5V
60
55
90
88
MHz
MHz
L
A = 2, V = 10V , f = 1kHz
±15V
±15V
0.00007
0.0015
%
%
V
O
P-P
A = 2, V = 10V , f = 100kHz
V
O
P-P
t , t
A = 1, 10% to 90%, 0.1V
V
±15V
±5V
11
12
ns
ns
r
f
A = 1, 0.1V
V
±15V
±5V
30
35
%
%
Propagation Delay
Settling Time
A = 1, 50% V to 50% V , 0.1V
±15V
±5V
9
10
ns
ns
V
IN
OUT
t
10V Step, 0.01%, A = –1
±15V
±15V
±5V
760
900
770
ns
ns
ns
s
V
10V Step, 150µV, A = –1
V
5V Step, 0.01%, A = –1
V
R
Output Resistance
Supply Current
A = 1, f = 100kHz
V
±15V
0.02
Ω
O
I
±15V
±5V
3.9
3.6
5.2
5.0
mA
mA
S
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
Input Offset Voltage
V
MIN
TYP
MAX
UNITS
SUPPLY
V
±15V
±5V
●
●
150
250
µV
µV
OS
Input V Drift
(Note 7)
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
●
●
0.7
60
40
2.0
65
µV/°C
nA
OS
I
I
I
Input Offset Current
OS
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Common Mode Rejection Ratio
pA/°C
nA
–
●
±15
±50
B
B
pA/°C
nA
+
●
CMRR
V
V
= ±12.5V
= ±2.5V
±15V
±5V
●
●
94
94
dB
dB
CM
CM
PSRR
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V = ±4.5V to ±15V
●
98
dB
S
A
V
V
V
V
V
= ±12.5V, R = 10k
±15V
±15V
±5V
●
●
●
●
500
250
500
250
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
OUT
L
= ±12.5V, R = 2k
L
= ±2.5V, R = 10k
L
= ±2.5V, R = 2k
±5V
L
Output Swing
Output Current
R = 10k, V = ±1mV
±15V
±15V
±5V
●
●
●
●
±12.9
±12.7
±2.9
V
V
V
V
L
IN
R = 2k, V = ±1mV
L
IN
R = 10k, V = ±1mV
L
IN
R = 2k, V = ±1mV
±5V
±2.7
L
IN
I
I
V
V
= ±12.5V
= ±2.5V
±15V
±5V
●
●
±12.5
±12.5
mA
mA
OUT
SC
OUT
OUT
Short-Circuit Current
Slew Rate
V
= 0V, V = ±0.2V
±15V
●
±17
mA
OUT
IN
SR
A = –1, R = 2k (Note 5)
±15V
±5V
●
●
13
9
V/µs
V/µs
V
L
3
LT1468
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
GBW
Gain Bandwidth
f = 100kHz, R = 2k
±15V
±5V
●
●
55
50
MHz
MHz
L
I
Supply Current
±15V
±5V
●
●
6.5
6.3
mA
mA
S
–40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted (Note 4).
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
V
±15V
±5V
●
●
230
330
µV
µV
OS
Input V Drift
(Note 7)
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
●
●
0.7
120
80
2.5
80
µV/°C
nA
OS
I
I
I
Input Offset Current
OS
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Common Mode Rejection Ratio
pA/°C
nA
–
●
●
±30
±60
B
B
pA/°C
nA
+
CMRR
V
V
= ±12.5V
= ±2.5V
±15V
±5V
●
●
92
92
dB
dB
CM
CM
PSRR
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V = ±4.5V to ±15V
●
96
dB
S
A
V
V
V
V
V
= ±12V, R = 10k
±15V
±15V
±5V
●
●
●
●
300
150
300
150
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
OUT
L
= ±10V, R = 2k
L
= ±2.5V, R = 10k
L
= ±2.5V, R = 2k
±5V
L
Output Swing
Output Current
R = 10k, V = ±1mV
±15V
±15V
±5V
●
●
●
●
±12.8
±12.6
±2.8
V
V
V
V
L
IN
R = 2k, V = ±1mV
L
IN
R = 10k, V = ±1mV
L
IN
R = 2k, V = ±1mV
±5V
±2.6
L
IN
I
I
V
V
= ±12.5V
= ±2.5V
±15V
±5V
●
●
±7
±7
mA
mA
OUT
SC
OUT
OUT
Short-Circuit Current
Slew Rate
V
= 0V, V = ±0.2V
±15V
●
±12
mA
OUT
IN
SR
A = –1, R = 2k (Note 5)
±15V
±5V
●
●
9
6
V/µs
V/µs
V
L
GBW
Gain Bandwidth
Supply Current
f = 100kHz, R = 2k
±15V
±5V
●
●
45
40
MHz
MHz
L
I
±15V
±5V
●
●
7.0
6.8
mA
mA
S
The
●
denotes specifications that apply over the full operating
Note 4: The LT1468C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and at 85°C. The
LT1468I is guaranteed to meet the extended temperature limits.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: Slew rate is measured between ±8V on the output with ±12V input
for ±15V supplies and ±2V on the output with ±3V input for ±5V supplies.
Note 6: Full power bandwidth is calculated from the slew rate
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.7V, the input
current should be limited to 10mA. Input voltages outside the supplies will
be clamped by ESD protection devices and input currents should also be
limited to 10mA.
measurement: FPBW = SR/2πV
P
Note 7: This parameter is not 100% tested.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
4
LT1468
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
and Temperature
Input Common Mode Range
vs Supply Voltage
Input Bias Current
vs Input Common Mode Voltage
+
7
6
80
60
V
T
= 25°C
OS
V
T
= ±15V
= 25°C
A
S
A
–0.5
–1.0
–1.5
–2.0
∆V < 100µV
40
125°C
5
4
20
–
I
B
0
+
25°C
I
B
2.0
1.5
1.0
0.5
–20
–40
–60
–80
3
2
1
–55°C
–
V
0
5
10
15
20
–10
–5
5
–15
10
15
0
0
3
9
12
15
18
6
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
INPUT COMMON MODE VOLTAGE (V)
1468 G01
1468 G03
1468 G02
Input Bias Current
vs Temperature
Input Noise Spectral Density
0.1Hz to 10Hz Voltage Noise
30
20
1000
10
V
= ±15V
S
V
= ±15V
V
= ±15V
= 25°C
= 101
S
S
A
V
T
A
R
= 100k FOR i
S
n
i
n
10
100
10
1
1
–
+
I
I
B
0
–10
–20
–30
–40
e
n
0.1
B
0.01
50
TEMPERATURE (°C)
100 125
1
10
100
1k
10k
100k
–50 –25
0
25
75
TIME (1s/DIV)
FREQUENCY (Hz)
1468 G06
1468 G05
1468 G04
Open-Loop Gain
vs Resistive Load
Open-Loop Gain
vs Temperature
Warm-Up Drift vs Time
140
5
0
160
150
T
= 25°C
R
= 2k
A
L
V
= ±15V
S
135
130
125
120
115
110
N8 ±5V
V
= ±15V
= ±5V
S
S
–5
V
= ±5V
S
140
130
120
110
100
S0-8 ±5V
–10
–15
–20
–25
–30
–35
–40
V
N8 ±15V
S0-8 ±15V
90
10
100
1k
10k
50
100 125
–50 –25
0
25
75
0
20
40
60
80 100 120 140
LOAD RESISTANCE (Ω)
TIME AFTER POWER UP (s)
TEMPERATURE (°C)
1468 G08
1468 G09
1468 G07
5
LT1468
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage Swing
vs Supply Voltage
Output Voltage Swing
vs Load Current
Output Short-Circuit Current
vs Temperature
+
+
60
55
50
45
40
35
30
25
20
15
10
V
–0.5
–1.0
–1.5
–2.0
–2.5
V
R
L
= 2k
V
= ±15V
V
V
= ±15V
IN
S
85°C
S
25°C
= ±0.2V
–1
–2
–3
–4
4
R
L
= 10k
–40°C
SOURCE
SINK
2.5
2.0
1.5
1.0
40°C
85°C
3
2
R
L
= 2k
25°C
1
R
L
= 10k
T
= 25°C
A
–
–
V
0.5
–20
V
–50
–25
0
25
50
75 100 125
–15 –10 –5
0
5
10 15
20
0
5
10
15
20
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (±V)
1468 G12
1468 G11
1468 G10
Settling Time to 0.01%
vs Output Step, VS = ±15V
Settling Time to 0.01%
vs Output Step, VS = ±5V
Settling Time to 150µV
vs Output Step
10
8
5
4
10
8
V
= ±15V
= 1k
V
= ±5V
V
A
= ±15V
S
L
S
S
V
F
F
R
R
= 1k
L
= –1
A
= –1
A = 1
V
A
= 1
A = –1
V
V
V
R
= R = 2k
G
6
3
6
C
= 8pF
4
2
4
2
1
2
0
0
0
–2
–4
–6
–8
–10
–1
–2
–3
–4
–5
–2
–4
–6
–8
–10
A
= –1
A
= 1
V
V
A
= 1
A = –1
V
V
0
200
400
600
800
1000
300
400
500
600
700
800
0
200
600
SETTLING TIME (ns)
800
1000
400
SETTLING TIME (ns)
SETTLING TIME (ns)
1468 G13
1468 G14
1468 G15
Gain Bandwidth and Phase
Margin vs Supply Voltage
Gain Bandwidth and Phase
Margin vs Temperature
Output Impedance vs Frequency
104
46
100
10
98
96
94
92
90
88
86
84
82
44
42
40
38
36
34
32
30
28
V
T
= ±15V
= 25°C
T
= 25°C
S
A
A
V
F
F
L
102
100
98
96
94
92
90
88
86
84
44
42
40
38
36
34
32
30
28
26
A
= –1
PHASE MARGIN
R
= R = 5.1k
V
= ±15V
G
S
PHASE MARGIN
C
= 5pF
= 2k
A
= 100
V
R
V
= ±5V
S
1
A
= 10
V
0.1
V
= 15V
S
GAIN BANDWIDTH
GAIN BANDWIDTH
A
= 1
V
0.01
0.001
V
= 5V
S
10
SUPPLY VOLTAGE (±V)
–55
0
25
50
75
125
0
5
15
20
–25
100
10k
100k
1M
FREQUENCY (Hz)
10M
100M
TEMPERATURE (°C)
1468 G19
1468 G17
1468 G18
6
LT1468
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Rejection Ratio
Common Mode Rejection Ratio
vs Frequency
Gain and Phase vs Frequency
vs Frequency
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
100
80
160
140
120
100
V
= ±15V
= 25°C
V
= ±15V
= 25°C
S
A
S
A
T
T
PHASE
+PSRR
–PSRR
60
±15V
40
±5V
20
80
60
GAIN
0
±15V
T
= 25°C
A
V
F
F
L
–20
–40
–60
40
20
0
A
= –1
±5V
R
= R = 5.1k
G
C
= 5pF
= 2k
R
–10
100
10k
100k 1M
10M 100M
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1k
10k
1M
1k
100
10M 100M
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
1468 G16
1468 G21
1468 G20
Frequency Response
vs Capacitive Load, AV = 1
Frequency Response
vs Supply Voltage, AV = 1
Frequency Response
vs Supply Voltage, AV = –1
14
12
10
8
5
5
4
3
2
V
T
= ±15V
= 25°C
= 1
T
= 25°C
= 1
= 2k
S
A
V
A
V
L
4
3
2
A
R
= R = 2k
G
F
A
R
±5V
NO R
L
±15V
R
= R = 5.1k
G
F
100pF
50pF
20pF
±5V
±5V
±15V
6
4
1
0
1
0
±15V
2
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
10pF
T
= 25°C
= –1
A
V
L
F
–2
–4
–6
A
R
C
= 2k
= 5pF
100k
1M
10M
100M
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
1468 G24
1468 G22
1468 G23
Frequency Response
vs Capacitive Load, AV = –1
Slew Rate vs Supply Voltage
Slew Rate vs Temperature
14
12
10
8
45
30
28
26
24
22
20
18
16
14
T
= 25°C
= –1
= 2k
V
T
= ±15V
= 25°C
= –1
V
A
= ±15V
= –1
= 2k
A
V
L
S
A
V
F
F
S
V
L
A
40
35
R
A
R
–SR
R
C
NO R
= R = 5.1k
G
300pF
= 5pF
–SR
+SR
L
30
25
20
15
10
6
4
+SR
200pF
2
0
100pF
50pF
–2
–4
–6
5
10
SUPPLY VOLTAGE (±V)
–50
–25
0
25
50
75 100 125
100k
1M
FREQUENCY (Hz)
10M
100M
0
5
15
20
TEMPERATURE (°C)
1468 G25
1468 G26
1468 G27
7
LT1468
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Total Harmonic Distortion + Noise
vs Frequency
Undistorted Output Swing
Total Harmonic Distortion + Noise
vs Amplitude
vs Frequency, ±15V
0.010
0.001
–50
–60
30
25
20
15
10
5
V
= ±15V
= 25°C
= 600Ω
= 20V
S
A
L
T
R
V
A
V
=1
O
P-P
±5V ±15V
NOISE BW = 80kHz
–70
A
V
= –1
A
= 10
= 1
V
–80
A
V
–90
MEASUREMENT
LIMIT
T
= 25°C
= 10
A
V
L
A
–100
R
= 600Ω
V
= ±15V
= 2k
S
L
f = 10kHz
R
NOISE BW = 80kHz
0.0001
–110
0
20
100
1k
FREQUENCY (Hz)
10k 20k
0.01
0.1
1
10
1
10
100
1000
OUTPUT SIGNAL (V
)
FREQUENCY (kHz)
RMS
1468 G28
1468 G29
1468 G30
Undistorted Output Swing
Small-Signal Transient, AV = –1
Small-Signal Transient, AV = 1
vs Frequency, ±5V
10
9
V
= ±5V
= 2k
S
R
L
8
A
V
= 1
7
6
5
A
= –1
V
4
3
2
1
0
1468 G32
1468 G31
VS = ±15V
VS = ±15V
1
10
100
1000
FREQUENCY (kHz)
1468 G33
Total Noise vs Unmatched
Source Resistance
Large-Signal Transient, AV = –1
Large-Signal Transient, AV = 1
100
10
1
V
= ±15V
= 25°C
S
A
T
f = 10kHz
TOTAL
NOISE
RESISTOR
NOISE ONLY
R
S
+
–
1468 G32
1468 G34
VS = ±15V
VS = ±15V
0.1
10
100
1k
10k
100k
SOURCE RESISTANCE, R (Ω)
S
1468 G36
8
LT1468
U
W U U
APPLICATIONS INFORMATION
The LT1468 may be inserted directly into many opera-
tional amplifier applications improving both DC and AC
performance, provided that the nulling circuitry is re-
moved. The suggested nulling circuit for the LT1468 is
shown below.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
theinputcapacitancetoformapolethatcancausepeaking
or even oscillations. For feedback resistors greater than
2k, a feedback capacitor of the value:
CF > (RG)(CIN/RF)
Offset Nulling
+
V
should be used to cancel the input pole and optimize dy-
namic performance. For applications where the DC noise
gainisone,andalargefeedbackresistorisused,CF should
begreaterthanorequaltoCIN.AnexamplewouldbeaDAC
I-to-V converter as shown on the front page of this data
sheet where the DAC can have many tens of pF of output
capacitance. Another example would be a gain of
–1 with 5k resistors; a 5pF to 10pF capacitor should be
addedacrossthefeedbackresistor.Thefrequencyresponse
in a gain of –1 is shown in the Typical Performance curves
with 2k and 5.1k resistors with a 5pF feedback capacitor.
3
0.1µF
0.1µF
2.2µF
2.2µF
+
–
7
4
6
LT1468
5
2
1
100k
–
1468 AI01
V
Layout and Passive Components
The LT1468 requires attention to detail in board layout in
order to maximize DC and AC performance. For best AC
results(forexamplefastsettlingtime)useagroundplane,
short lead lengths, and RF-quality bypass capacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capaci-
tors(1µFto10µFtantalum). ForbestDCperformance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (i.e., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB– specification.)
Nulling Input Capacitance
R
F
C
F
R
G
–
+
C
LT1468
V
OUT
IN
V
IN
1468 AI02
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs. For inverting configurations tie the ring
to ground, in noninverting connections tie the ring to the
inverting input (note the input capacitance will increase
whichmayrequireacompensatingcapacitorasdiscussed
below.)
Input Considerations
Each input of the LT1468 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of the
input devices. If the inputs can be pulled apart, the input
current should be limited to less than 10mA with an
external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
abovethesupply,limitthecurrentwithanexternalresistor
to less than 10mA.
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects caused by tem-
perature gradients across dissimilar metals at the con-
tacts to the inputs can exceed the inherent drift of the
amplifier. Air currents over device leads should be mini-
mized, package leads should be short, and the two input
leads should be as close together as possible and main-
tained at the same temperature.
The LT1468 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-V converters. The noninverting
input current is not trimmed and has a wider variation and
therefore a larger maximum value. As the input offset
Make no connection to Pin 8. This pin is used for factory
trim of the inverting input current.
9
LT1468
U
W U U
APPLICATIONS INFORMATION
Driving Capacitive Loads
current can be greater than either input current, the use of
balanced source resistance is NOT recommended as it
actually degrades DC accuracy and also increases noise.
R
F
C
F
R
R
C
≥ (1 + R /R )/(2πC 5MHz)
F G L
O
F
F
≥ 10R
O
O
The input bias currents vary with common mode voltage
as shown in the Typical Performance Characteristics. The
cancellation circuitry was not designed to track this com-
mon mode voltage because the settling time would have
been adversely affected.
R
G
= (2R /R )C
L
F
–
+
R
O
LT1468
V
OUT
C
V
L
IN
1468 AI04
The LT1468 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the
positive supply, the output reverses phase.
excellentLinearTechnology reference sources forsettling
measurements, Application Notes 47 and 74. Appendix B
of AN47 is a vital primer on 12-bit settling measurements,
and AN74 extends the state of the art while concentrating
on settling time with a 16-bit current output DAC input.
Input Stage Protection
The 150µV settling curve in the Typical Performance
Characteristics is measured using the Differential Ampli-
fiermethodofAN74followedbyaclamped, nonsaturating
gain of 100. The total gain of 500 allows a resolution of
100µV/DIV with an oscilloscope setting of 0.05V/DIV
R1
100Ω
R2
100Ω
Q1
Q2
+IN
–IN
1468 AI03
The settling of the DAC I-to-V converter on the front page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
20pF across the 6k feedback resistor. The theoretical limit
for 16-bit settling is 11.1 times this RC time constant or
1.33µs. The actual settling time is 1.7µs at the output of
the LT1468. The LT1468 is the fastest Linear Technology
amplifier in this application.
Total Input Noise
ThecurveofTotalNoisevsUnmatchedSourceResistance
intheTypicalPerformanceCharacteristicsshowsthatwith
source resistance below 1k, the voltage noise of the am-
plifier dominates. In the 1k to 20k region the increase in
noise is due to the source resistance. Above 20k the input
current noise component is larger than the resistor noise.
The optional noise filter adds a slight delay of 100ns, but
reduces the noise bandwidth to 1.6MHz which increases
the output resolution for 16-bit accuracy.
Capacitive Loading
The LT1468 drives capacitive loads of up to 100pF in unity
gain and 300pF in a gain of –1. When there is a need to
drivealargercapacitiveload,asmallseriesresistorshould
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Driving Capacitive Loads.
Distortion
The LT1468 has outstanding distortion performance as
shownintheTypicalPerformancecurvesofTotalHarmonic
Distortion + Noise vs Frequency and Amplitude. The high
open-loopgainandinherentlybalancedarchitecturereduce
errors to yield 16-bit accuracy to frequencies as high as
100kHz. An example of this performance is the Typical
Application titled 100kHz Low Distortion Bandpass Filter.
This circuit is useful for cleaning up the output of a high
performance signal generator such as the B & K type 1051
or HP3326A.
Settling Time
The LT1468 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling
performance. Measuring settling, even at the 12-bit level
is very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
10
LT1468
U
W U U
APPLICATIONS INFORMATION
Another key application for LT1468 is buffering the input
to a 16-bit A/D converter. In a gain of 1 or 2 this straight-
forward circuit provides uncorrupted AC and DC levels to
the converter, while buffering the A/D input sample-and-
holdcircuitfromhighsourceimpedancewhichcanreduce
the maximum sampling rate. The front page graph shows
better than 16-bit distortion for a gain of 2 with a 10VP-P
output.
W
W
SI PLIFIED SCHEMATIC
+
V
I1
I2
I5
Q10
Q8
Q9
OUT
+IN
Q1
Q2
–IN Q5
Q3
Q6
Q7
Q11
Q4
C
BIAS
I3
I4
I6
–
V
1468 SS
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.400*
(10.160)
MAX
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
2
3
1
0.053 – 0.069
2
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0.065
(1.651)
TYP
0°– 8° TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
(3.175)
MIN
0.016 – 0.050
0.406 – 1.270
0.020
(0.508)
MIN
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
+0.035
–0.015
0.325
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
(
)
N8 1197
–0.381
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT1468
U
TYPICAL APPLICATIONS
Instrumentation Amplifier
16-Bit ADC Buffer
10pF
2k
R5
1.1k
R4
50k
R2
5k
C2
2pF
C1
10pF
R1
50k
2k
–
+
16 BITS
200Ω
LT1468
LTC1605
CAP
R3
5k
1000pF
V
–
IN
1468 TA04
33.2k
LT1468
–
+
LT1468
–
V
OUT
2.2µF
1468 TA03
+
V
IN
+
GAIN = [R4/R3][1 + (1/2)(R2/R1 + R3/R4) + (R2 + R3)/R5] = 102
TRIM R5 FOR GAIN
TRIM R1 FOR COMMON MODE REJECTION
BW = 480kHz
100kHz Low Distortion Bandpass Filter
1000pF
22.1k
100kHz Distortion
SIGNAL LEVEL
R
2ND HARMONIC 3RD HARMONIC
L
1V
2V
1M
1M
1M
2k
2k
2k
–106dB
–105dB
–106dB
–103dB
–99dB
–103dB
–105dB
–104dB
–103dB
–103dB
–102dB
RMS
RMS
1000pF
11k
3.5V
RMS
RMS
RMS
V
IN
–
1V
2V
LT1468
V
OUT
121Ω
R
L
+
3.5V
–96.5dB
RMS
1468 TA05
f
= 100kHz
O
Q = 7
= –1
A
V
RELATED PARTS
PART NUMBER
LT1167
DESCRIPTION
COMMENTS
Precision Instrumentation Amplifier
Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
±2.5V Input, SINAD = 90dB, THD = –100dB
LTC1595/LTC1596
LTC1597
16-Bit Serial Multiplying I
DACs
OUT
16-Bit Parallel Multiplying I
DAC
OUT
LTC1604
16-Bit, 333ksps Sampling ADC
Single 5V, 16-Bit, 100ksps Sampling ADC
LTC1605
Low Power, ±10V Inputs, Parallel/Byte Interface
1468f LT/TP 1098 4K • PRINTED IN USA
12 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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