LT1765_技术文档

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

Monolithic 3A, 1.25MHz

Step-Down Switching Regulator

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FEATURES

DESCRIPTIO

The LT^®1765 is a 1.25MHz monolithic buck switching

regulator. A high efficiency 3A, 0.09Ω switch is included

on the die together with all the control circuitry required

to construct a high frequency, current mode switching

regulator. Current mode control provides fast transient

response and excellent loop stability.

■

3A Switch in a Thermally Enhanced 16-Lead

TSSOP or 8-Lead SO Package

■

Constant 1.25MHz Switching Frequency

■

Wide Operating Voltage Range: 3V to 25V

■

High Efficiency 0.09Ω Switch

■

1.2V Feedback Reference Voltage

■

Uses Low Profile Surface Mount Components

New design techniques achieve high efficiency at high

switchingfrequenciesoverawideoperatingvoltagerange.

A low dropout internal regulator maintains consistent

performance over a wide range of inputs from 24V

systems to Li-Ion batteries. An operating supply current

of 1mA improves efficiency, especially at lower output

currents. Shutdown reduces quiescent current to 15µA.

Maximum switch current remains constant at all duty

cycles. Synchronization allows an external logic level

signal to increase the internal oscillator into the range of

1.6MHz to 2MHz.

■

Low Shutdown Current: 15µA

■

Synchronizable to 2MHz

■

Current Mode Loop Control

■

Constant Maximum Switch Current Rating at

All Duty Cycles*

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APPLICATIO S

■

DSL Modems

■

Portable Computers

■

Regulated Wall Adapters

Full cycle-by-cycle current control and thermal shutdown

are provided. High frequency operation allows the reduc-

tion of input and output filtering components and permits

the use of chip inductors.

■

Battery-Powered Systems

■

Distributed Power

, LTC and LT are registered trademarks of Linear Technology Corporation.

* Patent Pending

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TYPICAL APPLICATIO

5V to 3.3V Step-Down Converter

Efficiency vs Load Current

90

CMDSH-3

V

= 10V

OUT

IN

= 5V

0.18µF

85

80

75

70

1.5µH

OUTPUT

3.3V

BOOST

INPUT

5V

V

IN

V

SW

FB

2.5A

2.2µF

CERAMIC

LT1765-3.3

OFF ON

SHDN

SYNC GND

V

C

4.7µF

CERAMIC

2.2nF

UPS120

1765 TA01

1.0

1.5

0

2.0

0.5

SWITCH CURRENT (A)

1765 • TAO1a

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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ABSOLUTE AXI U RATI GS

(Note 1)

Input Voltage .......................................................... 25V

BOOST Pin Above SW ............................................ 20V

Max BOOST Pin Voltage .......................................... 35V

SHDN Pin ............................................................... 25V

FB Pin Current ....................................................... 1mA

SYNC Pin Current .................................................. 1mA

Operating Junction Temperature Range

(Note 2) ........................................... –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

ORDER PART

NUMBER

TOP VIEW

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

NC

TOP VIEW

LT1765ES8

LT1765EFE

BOOST

LT1765EFE-1.8

LT1765EFE-2.5

LT1765EFE-3.3

LT1765EFE-5

BOOST

1

2

3

4

8

7

6

5

SYNC

V

IN

SYNC

V

IN

V

C

V

IN

V

C

SW

FB

SW

FB

GND

SHDN

NC

S8 PART

MARKING

NC

S8 PACKAGE

8-LEAD PLASTIC SO

FE PART MARKING

GND

T_JMAX= 125°C, θ_JA= 90°C/W,

θ_{JC(PIN 4)}= 30°C/W

1765EFE

1765

FE PACKAGE

16-LEAD PLASTIC TSSOP

GROUND PIN CONNECTED TO

LARGE COPPER AREA

1765EFE18

1765EFE25

1765EFE33

1765EFE-5

θ_JA= 45°C/W, θ_JC(PAD)= 10°C/W

EXPOSED PAD SOLDERED TO LARGE

COPPER PLANE

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C.

V_IN= 15V, V_C= 0.8V, Boost = V_IN+ 5V, SHDN, SYNC and switch open unless otherwise noted.

PARAMETER

CONDITIONS

MIN

3

TYP

4

MAX

6

UNITS

A

Maximum Switch Current Limit

Oscillator Frequency

Switch On Voltage Drop

3.3V < V < 25V

●

1.1

1.25

270

2.6

1

1.6

430

2.73

1.3

MHz

mV

V

IN

I = 3A

V

IN

V

IN

Undervoltage Lockout

Supply Current

(Note 3)

2.47

mA

Shutdown Supply Current

V

SHDN

= 0V, V = 25V, V = 0V

15

35

55

µA

IN

SW

●

Feedback Voltage

3V < V < 25V, 0.4V < V < 0.9V

(Note 3)

LT1765 (Adj)

1.182

1.176

1.2

1.218

1.224

V

IN

C

●

LT1765-1.8

LT1765-2.5

LT1765-3.3

LT1765-5

1.764

2.45

3.234

4.9

1.8

2.5

3.3

5

1.836

2.55

3.366

5.1

V

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C.

V_IN= 15V, V_C= 0.8V, Boost = V_IN+ 5V, SHDN, SYNC and switch open unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

FB Input Current

FB Input Resistance

LT1765 (Adj)

●

–0.25

–0.5

µA

LT1765

●

10.5

14.7

19

15

21

27.5

42

21

30

39

60

kΩ

LT1765-1.8

LT1765-3.3

LT1765-5

29

FB Error Amp Voltage Gain

0.4V < V < 0.9V

150

500

80

350

850

120

110

5

C

FB Error Amp Transconductance

∆I = ±10µA

VC

●

1300

160

µMho

µA

A/V

V

V Pin Source Current

C

V

= V

– 17%

+ 17%

FB

NOM

V Pin Sink Current

C

70

180

V Pin to Switch Current Transconductance

C

V Pin Minimum Switching Threshold

Duty Cycle = 0%

0.4

0.9

90

C

V Pin 3A I Threshold

V

C

SW

Maximum Switch Duty Cycle

V = 1.2V, I = 800mA, V = 6V

85

80

%

C

SW

IN

●

Minimum Boost Voltage Above Switch

Boost Current

I

= 3A

1.8

2.7

V

SW

I

= 1A (Note 4)

= 3A (Note 4)

●

20

70

30

140

mA

SW

SHDN Threshold Voltage

●

1.27

4

1.33

7

1.40

10

V

µA

SHDN Threshold Current Hysteresis

SHDN Input Current (Shutting Down)

SYNC Threshold Voltage

SHDN = 60mV Above Threshold

– 7

– 10

1.5

– 13

2.2

2

µA

V

SYNC Input Frequency

1.6

MHz

kΩ

SYNC Pin Resistance

I

= 1mA

20

SYNC

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LT1765E is guaranteed to meet performance specifications

from 0°C to 125°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls.

Note 3: Minimum input voltage is defined as the voltage where the internal

regulator enters lockout. Actual minimum input voltage to maintain a

regulated output will depend on output voltage and load current. See

Applications Information.

Note 4: Current flows into the BOOST pin only during the on period of the

switch cycle.

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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TYPICAL PERFOR A CE CHARACTERISTICS

FB vs Temperature (Adj)

Switch On Voltage Drop

Oscillator Frequency

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

350

300

250

200

150

100

50

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

T

= 125°C

A

T

= –40°C

A

T

= 25°C

A

0

–25

0

25

50

75

125

–50

100

2

3

0

1

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

SWITCH CURRENT (A)

1765 G01

1765 G02

1765 G03

SHDN Threshold vs Temperature

SHDN Supply Current vs V_IN

7

1.40

1.38

1.36

1.34

1.32

1.30

SHDN = 0V

6

5

4

3

2

1

0

–50 –25

0

25

50

75 100 125

0

5

10

15

(V)

20

25

30

TEMPERATURE (°C)

V

IN

1765 G04

1765 G05

SHDN I_PCurrent vs Temperature

–12

–10

–8

–6

–4

–2

0

SHUTTING DOWN

STARTING UP

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

1765 G06

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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TYPICAL PERFOR A CE CHARACTERISTICS

Minimum Input Voltage for

2.5V Out

SHDN Supply Current

Input Supply Current

1200

1000

800

600

400

200

0

3.5

3.3

3.1

2.9

2.7

2.5

300

250

200

150

100

50

V

= 15V

IN

UNDERVOLTAGE

LOCKOUT

0

0.001

0.01

0.1

1

0

0.2 0.4 0.6 0.8

1

1.2 1.4

0

5

10

15

20

25

30

LOAD CURRENT (A)

SHUTDOWN VOLTAGE (V)

INPUT VOLTAGE (V)

1765 G07

1765 G08

1765 G09

Maximum Load Current,

V_OUT= 5V

Current Limit Foldback

3.0

2.8

2.6

2.4

2.2

2.0

4

40

30

20

10

0

L = 4.7µH

3

2

1

0

SWITCH CURRENT

L = 2.2µH

FB CURRENT

L = 1.5µH

0

5

10

15

20

25

0

0.2

0.4

0.6

0.8

1

1.2

INPUT VOLTAGE (V)

FEEDBACK VOLTAGE (V)

1765 G11

1765 G10

Maximum Load Current,

V_OUT= 2.5V

3.0

2.8

2.6

2.4

2.2

L = 4.7µH

L = 2.2µH

L = 1.5µH

0

5

10

15

20

25

INPUT VOLTAGE (V)

1765 G12

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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PI FU CTIO S

V_SW: The switch pin is the emitter of the on-chip power

NPN switch. This pin is driven up to the input pin voltage

during switch on time. Inductor current drives the switch

pin negative during switch off time. Negative voltage must

be clamped with an external catch diode with a V_BR<0.8V.

Both V_SWpins of the TSSOP package must be shorted

together on the PC board.

FB: The feedback pin is used to set output voltage using

an external voltage divider (adjustable version) that gen-

erates 1.2V at the pin when connected to the desired

output voltage. The fixed voltage 1.8V, 2.5V, 3.3V and 5V

versions have the divider network included internally and

the FB pin is connected directly to the output. If required,

the current limit can be reduced during start up or short-

circuitwhentheFBpinisbelow0.5V(seetheCurrentLimit

Foldback graph in the Typical Performance Characteris-

tics section). An impedance of less than 5kΩ on the

adjustable version at the FB pin is needed for this feature

to operate.

SYNC: The sync pin is used to synchronize the internal

oscillator to an external signal. It is directly logic compat-

ible and can be driven with any signal between 20% and

80% duty cycle. The synchronizing range is from 1.6MHz

to 2MHz. See Synchronization section in Applications

Informationfordetails. Whennotinuse, thispinshouldbe

grounded.

BOOST: The BOOST pin is used to provide a drive voltage,

higher than the input voltage, to the internal bipolar NPN

power switch.

SHDN: The shutdown pin is used to turn off the regulator

and to reduce input drain current to a few microamperes.

The 1.33V threshold can function as an accurate under-

voltage lockout (UVLO), preventing the regulator from

operating until the input voltage has reached a predeter-

mined level. Float or pull high to put the regulator in the

operating mode.

V_IN:This is the collector of the on-chip power NPN switch.

This pin powers the internal circuitry and internal regula-

tor. At NPN switch on and off, high di/dt edges occur on

this pin. Keep the external bypass capacitor and catch

diodeclosetothispin.Alltraceinductanceonthispathwill

create a voltage spike at switch off, adding to the V_CE

voltage across the internal NPN. Both V_INpins of the

TSSOP package must be shorted together on the PC

board.

V_C: The V_Cpin is the output of the error amplifier and the

input of the peak switch current comparator. It is normally

used for frequency compensation, but can do double duty

as a current clamp or control loop override. This pin sits

at about 0.4V for very light loads and 0.9V at maximum

load. It can be driven to ground to shut off the output.

GND: The GND pin acts as the reference for the regulated

output, soloadregulationwillsufferifthe“ground”endof

the load is not at the same voltage as the GND pin of the

IC. This condition will occur when load current or other

currents flow through metal paths between the GND pin

and the load ground point. Keep the ground path short

between the GND pin and the load and use a ground plane

when possible. Keep the path between the input bypass

and the GND pin short. The exposed GND pad and/or GND

pinsofthepackagearedirectlyattachedtotheinternaltab.

These pins/pad should be attached to a large copper area

to reduce thermal resistance.

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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BLOCK DIAGRA

The LT1765 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

twofeedbackloopsthatcontrolthedutycycleofthepower

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

tor pulse which sets the R_Sflip-flop to turn the switch on.

When switch current reaches a level set by the inverting

input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by

using the output of the error amplifier to set the switch

current trip point. This technique means that the error

amplifier commands current to be delivered to the output

rather than voltage. A voltage fed system will have low

phase shift up to the resonant frequency of the inductor

and output capacitor, then an abrupt 180° shift will occur.

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

itmucheasiertofrequencycompensatethefeedbackloop

and also gives much quicker transient response.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing the switch to be saturated.

This boosted voltage is generated with an external capaci-

tor and diode. A comparator connected to the shutdown

pin disables the internal regulator, reducing supply

current.

0.005Ω

INPUT

+

–

CURRENT

SENSE

INTERNAL

CC

2.5V BIAS

REGULATOR

AMPLIFIER

V

VOLTAGE GAIN = 40

SLOPE COMP

BOOST

Σ

0.4V

1.25MHz

S

R

SYNC

Q1

POWER

SWITCH

OSCILLATOR

R

DRIVER

CURRENT

COMPARATOR

S

FLIP-FLOP

CIRCUITRY

+

–

SHUTDOWN

COMPARATOR

V

SW

PARASITIC DIODES

DO NOT FORWARD BIAS

7µA

–

+

–

FB

1.33V

+

ERROR

V

C

AMPLIFIER

1.2V

INTERNAL

CC

g

m

= 850µMho

SHDN

V

GND

3µA

1765 F01

Figure 1. Block Diagram

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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APPLICATIO S I FOR ATIO

FB RESISTOR NETWORK

rating and turn-on surge problems. Y5V or similar type

ceramics can be used since the absolute value of capaci-

tance is less important and has no significant effect on

loop stability. If operation is required close to the mini-

mum input required by the output or the LT1765, a larger

value may be required. This is to prevent excessive ripple

causingdipsbelowtheminimumoperatingvoltageresult-

ing in erratic operation.

If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required,

the respective fixed option part, -1.8, -2.5, -3.3 or -5,

shouldbeused. TheFBpinistieddirectlytotheoutput;the

necessary resistive divider is already included on the part.

For other voltage outputs, the adjustable part should be

used and an external resistor divider added. The sug-

gested resistor (R2) from FB to ground is 10k. This

reduces the contribution of FB input bias current to output

voltage to less than 0.25%. The formula for the resistor

(R1) from V_OUTto FB is:

Iftantalumcapacitorsareused,valuesinthe22µFto470µF

range are generally needed to minimize ESR and meet

ripple current and surge ratings. Care should be taken to

ensure the ripple and surge ratings are not exceeded. The

AVX TPS and Kemet T495 series tantalum capacitors are

surge rated. AVX recommends derating capacitor operat-

ing voltage by 2:1 for high surge applications.

R2(V_OUT– 1.2)

1.2 – R2(0.25µA)

R1=

LT1765 (ADJ)

V

SW

OUTPUT

OUTPUT CAPACITOR

ERROR

AMPLIFIER

Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular, with an RMS value given by:

1.2V

+

–

R1

+

FB

R2

10k

1765 F02

0.29 V

_OUT)(

=

V − V

IN OUT

(

)

I_{RIPPLE RMS}

V

C

GND

(

)

L f V

( )( )(

)

IN

Figure 2. Feedback Network

The LT1765 will operate with both ceramic and tantalum

output capacitors. Ceramic capacitors are generally cho-

sen for their small size, very low ESR (effective series

resistance), and good high frequency operation. Ceramic

output capacitors in the 1µF to 10µF range, X7R or X5R

type are recommended.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple at the input of LT1765 and to force the switching

currentintoatightlocalloop,therebyminimizingEMI.The

RMS ripple current can be calculated from:

Tantalum capacitors are usually chosen for their bulk

capacitance properties, useful in high transient load appli-

cations. ESR rather than absolute value defines output

ripple at 1.25MHz. Typical LT1765 applications require a

tantalum capacitor with less than 0.3Ω ESR at 22µF to

500µF, see Table 2. This ESR provides a useful zero in the

frequency response. Ceramic output capacitors with low

ESR usually require a larger V_Ccapacitor or an additional

series R to compensate for this.

2

IN

I_{RIPPLE RMS}=I_OUTV_OUTV − V_OUT/ V

(

IN

)

(

)

Ceramiccapacitorsareidealforinputbypassing.Athigher

switching frequency, the energy storage requirement of

theinputcapacitorisreducedsovaluesintherangeof1µF

to 4.7µF are suitable for most applications. Their high

frequency capacitive nature removes most ripple current

sn1765 1765fas

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LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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APPLICATIO S I FOR ATIO

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Table 2. Surface Mount Solid Tantalum Capacitor ESR

I_{OUT MAX}

=

(V_OUT)(V_IN– V_OUT

2(L)(f)(V_IN)

)

(

)

and Ripple Current

I_P–

E Case Size

ESR (Max, Ω)

0.1 to 0.3

Ripple Current (A)

0.7 to 1.1

0.4

Continuous Mode

AVX TPS, Sprague 593D

AVX TAJ

For V_IN= 8V, V_OUT= 5V and L = 3.3µH,

0.7 to 0.9

D Case Size

5 8 − 5

( )(

)

AVX TPS, Sprague 593D

C Case Size

0.1 to 0.3

0.2 (typ)

0.7 to 1.1

0.5 (typ)

I_OUT(MAX)= 3 −

2 3.3 •10⁻⁶1.25•10⁶8

( )

(

)(

)

AVX TPS

= 3 − 0.23 = 2.77A

Figure3showsacomparisonofoutputrippleforaceramic

and tantalum capacitor at 200mA ripple current.

Note that the worst case (minimum output current avail-

able) condition is at the maximum input voltage. For the

same circuit at 15V, maximum output current would be

only 2.6A.

V_OUTUSING 47µF, 0.1Ω

TANTALUM CAPACITOR

(10mV/DIV)

Inductor Selection

The output inductor should have a saturation current

rating greater than the peak inductor current set by the

current comparator of the LT1765. The peak inductor

currentwilldependontheoutputcurrent,inputandoutput

voltages and the inductor value:

V

_OUTUSING 2.2µF

CERAMIC CAPACITOR

(10mV/DIV)

V_SW

(5V/DIV)

V_OUTV − V

(

)

IN

OUT

I_PEAK= I_OUT+

2 L f V

( )( )(

)

IN

0.2µs/DIV

1765 F03

V_IN= Maximum input voltage

f = Switching frequency, 1.25MHz

Figure 3. Output Ripple Voltage Waveform

If an inductor with a peak current lower than the maximum

switch current of the LT1765 is chosen a soft-start circuit

in Figure 10 should be used. Also, short-circuit conditions

should not be allowed because the inductor may saturate

resulting in excessive power dissipation.

INDUCTOR CHOICE AND MAXIMUM OUTPUT

CURRENT

Maximum output current for an LT1765 buck converter is

equal to the maximum switch rating (I_P) minus one half

peaktopeakinductorripplecurrent.TheLT1765maintains

a constant switch current rating at all duty cycles. (Patent

Pending)

Also, consideration should be given to the resistance of

the inductor. Inductor conduction loses are directly pro-

portional to the DC resistance of inductor. Sometime, the

manufacturers will also provide maximum current rating

based on the allowable losses in the inductor. Care should

be taken, however. At high input voltages and low DCR,

excessiveswitchcurrentcouldflowduringshortedoutput

condition.

For most applications, the output inductor will be in the

1µHto10µHrange. Lowervaluesarechosentoreducethe

physical size of the inductor, higher values allow higher

outputcurrentsduetoreducedpeaktopeakripplecurrent.

The following formula gives maximum output current for

continuous mode operation, implying that the peak to

peak ripple (2x the term on the right) is less than the

maximum switch current.

SuitableinductorsareavailablefromCoilcraft,Coiltronics,

Dale, Sumida, Toko, Murata, Panasonic and other

manufacturers.

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APPLICATIO S I FOR ATIO

Table 3

supply is used. The boost diode can be connected to the

input, although, care must be taken to prevent the 2x V_IN

boost voltage from exceeding the BOOST pin absolute

maximum rating. The additional voltage across the switch

driver also increases power loss, reducing efficiency. If

available, an independent supply can be used with a local

bypass capacitor.

VALUE

I

DCR

HEIGHT

(mm)

RMS

PART NUMBER

Coiltcraft

(µH)

(Amps)

(Ω)

DO1608C-222

Sumida

2.2

2.4

0.07

2.9

CDRH3D16-1R5

CDRH4D18-1R0

CDC5D23-2R2

CR43-1R4

1.5

1.0

2.2

1.4

2.6

1.6

1.7

2.2

2.5

2.6

0.043

0.035

0.03

1.8

2.0

2.5

3.5

3.0

A 0.18µF boost capacitor is recommended for most appli-

cations. Almost any type of film or ceramic capacitor is

suitable, but the ESR should be <1Ω to ensure it can be

fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

700ns on-time, 90mA boost current, and 0.7V discharge

ripple.Thisvalueisthenguardbandedby2xforsecondary

factors such as capacitor tolerance, ESR and temperature

effects. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve

circuitoperationorefficiency.Underlowinputvoltageand

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start up operation.

0.056

0.013

CDRH5D28-2R6

Toko

(D62F)847FY-2R4M

(D73LF)817FY-2R2M

2.4

2.2

2.5

2.7

0.037

0.03

2.7

3.0

CATCH DIODE

ThediodeD1conductscurrentonlyduringswitchofftime.

Peak reverse voltage is equal to regulator input voltage.

Averageforwardcurrentinnormaloperationcanbecalcu-

lated from:

I_OUTV − V_OUT

(

IN

)

SHUTDOWN AND UNDERVOLTAGE LOCKOUT

I_D₍_AVG

=

)

V

IN

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1765. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

loadtothesourceandcancausethesourcetocurrentlimit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

The only reason to consider a larger than 3A diode is the

worst-case condition of a high input voltage and shorted

output. With a shorted condition, diode current will in-

crease to a typical value of 4A, determined by peak switch

current limit of the LT1765. A higher forward voltage will

also limit switch current. This is safe for short periods of

time, but it would be prudent to check with the diode

manufacturer if continuous operation under these condi-

tions must be tolerated.

BOOST PIN

LT1765

Formostapplications, theboostcomponentsarea0.18µF

capacitor and a CMDSH-3 diode. The anode is typically

connected to the regulated output voltage to generate a

voltage approximately V_OUTabove V_INto drive the output

stage. The output driver requires at least 2.7V of head-

room throughout the on period to keep the switch fully

saturated.However,theoutputstagedischargestheboost

capacitor during this on time. If the output voltage is less

than 3.3V, it is recommended that an alternate boost

V

SW

7µA

IN

INPUT

1.33V

R1

R2

3µA

V

CC

OUTPUT

SHDN

+

C1

GND

1765 F04

Figure 4. Undervoltage Lockout

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An internal comparator will force the part into shutdown

below the minimum V_INof 2.6V. This feature can be used

to prevent excessive discharge of battery-operated sys-

tems. If an adjustable UVLO threshold is required, the

shutdown pin can be used. The threshold voltage of the

shutdown pin comparator is 1.33V. A 3µA internal current

sourcedefaultstheopenpinconditiontobeoperating(see

TypicalPerformanceGraphs). Currenthysteresisisadded

above the SHDN threshold. This can be used to set voltage

hysteresis of the UVLO using the following:

input can be driven directly from a logic level output. The

synchronizing range is equal to initial operating frequency

up to 2MHz. This means that minimum practical sync

frequency is equal to the worst-case high self-oscillating

frequency (1.6MHz), not the typical operating frequency

of 1.25MHz. Caution should be used when synchronizing

above 1.8MHz because at higher sync frequencies the

amplitude of the internal slope compensation used to

prevent subharmonic switching is reduced. This type of

subharmonic switching only occurs at input voltages less

than twice output voltage. Higher inductor values will tend

to eliminate this problem. See Frequency Compensation

section for a discussion of an entirely different cause of

subharmonic switching before assuming that the cause is

insufficient slope compensation. Application Note 19 has

more details on the theory of slope compensation.

V_H− V_L

R1=

7µA

1.33V

R2 =

V − 1.33V

(

)

H

+ 3µA

R1

V_H– Turn-on threshold

V_L– Turn-off threshold

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermalandnoiseperformance. Formaximum

efficiency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted,thehighspeedswitchingcurrentpath,shown

inFigure5, mustbekeptasshortaspossible. Shortening

thispathwillalsoreducetheparasitictraceinductanceof

approximately 25nH/inch. At switch off, this parasitic

inductance produces a flyback spike across the LT1765

switch. When operating at higher currents and input

voltages, with poor layout, this spike can generate

voltages across the LT1765 that may exceed its absolute

Example: switching should not start until the input is

above 4.75V and is to stop if the input falls below 3.75V.

V_H= 4.75V

V_L= 3.75V

4.75V − 3.75V

R1=

R2 =

= 143k

7µA

1.33V

= 49.4k

4.75V − 1.33V

(

)

+ 3µA

143k

Keep the connections from the resistors to the SHDN pin

short and make sure that the interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

torvaluesareused,theSHDNpinshouldbebypassedwith

a 1nF capacitor to prevent coupling problems from the

switch node.

LT1765

L1

V

IN

SW

5V

HIGH

FREQUENCY

CIRCULATING

PATH

C3

D1 C1

V

IN

LOAD

SYNCHRONIZATION

1765 F05

TheSYNCpinisusedtosynchronizetheinternaloscillator

to an external signal. The SYNC input must pass from a

logic level low, through the maximum synchronization

threshold with a duty cycle between 20% and 80%. The

Figure 5. High Speed Switching Path

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MINIMIZE D1, C3

LT1765 LOOP

V

IN

GND

D2

CMDSH-3

C3

KEEP FB AND V

C

INPUT

COMPONENTS AND

TRACES AWAY FROM

HIGH FREQUENCY,

HIGH INPUT

C

D2

C2

C

15V

C2

C3

0.18µF

4.7µF

CERAMIC

L1

2.7µH

OUTPUT

3.3V

BOOST

COMPONENTS

V

IN

V

SW

FB

C

2.5A

LT1765-33

D1

OFF ON

SHDN

SYNC GND

L1

V

C

C1

4.7µF

CERAMIC

D1

B220A

C

2.2nF

PLACE FEEDTHROUGHS

UNDER AND AROUND

GROUND PAD FOR

GOOD THERMAL

V

OUT

GND

C1

1765 F06

CONDUCTIVITY

KELVIN

SENSE

1765 F6a

V

OUT

Figure 6. Typical Application and Layout (Topside Only Shown)

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

THERMAL CALCULATIONS

Power dissipation in the LT1765 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current, and input quiescent current. The following

formulas show how to calculate each of these losses.

These formulas assume continuous mode operation, so

they should not be used for calculating efficiency at light

load currents.

The V_Cand FB components should be kept as far away as

possible from the switch and boost nodes. The LT1765

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic like oscillation.

Switch loss:

Board layout also has a significant effect on thermal

resistance. The exposed pad or GND pin is a continuous

copper plate that runs under the LT1765 die. This is the

best thermal path for heat out of the package as can be

seenbythelowθ_JCoftheexposedpadpackage. Reducing

the thermal resistance from Pin 4 or exposed pad onto the

board will reduce die temperature and increase the power

capability of the LT1765. This is achieved by providing as

much copper area as possible around this pin/pad. Also,

having multiple solder filled feedthroughs to a continuous

copper plane under LT1765 will help in reducing thermal

resistance. Ground plane is usually suitable for this pur-

pose. In multilayer PCB designs, placing a ground plane

next to the layer with the LT1765 will reduce thermal

resistance to a minimum.

2

R_{SW OUT}

I

V

OUT

(

) (

)

P

SW

=

+ 17ns I

V

f

(

_OUT)( _IN)( )

V

IN

Boost current loss for V_BOOST= V_OUT

:

2

V_OUT

I

/50

(

)

OUT

P_BOOST

=

V

IN

Quiescent current loss:

P_Q=V 0.001

IN

(

)

R_SW= Switch resistance (≈0.13Ω at hot)

17ns = Equivalent switch current/voltage overlap time

f = Switch frequency

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DIE TEMPERATURE MEASUREMENT

Example: with V_IN= 10V, V_OUT= 5V and I_OUT= 2A:

If a true die temperature is required, a measurement of the

SYNC to GND pin resistance can be used. The SYNC pin

resistance across temperature must first be calibrated,

with no significant output load, in an oven. An initial value

of 40k with a temperature coefficient of 0.16%/°C is

typical. The same measurement can then be used in

operation to indicate the die temperature.

0.13 2 ²5

(

)( ) ( )

P

=

+ 17 •10⁻⁹2 10 1.25 •10⁶

( )( )

SW

(

)

(

)

10

=0.26 + 0.43 = 0.69W

5 ²2 /50

( ) (

)

P_BOOST

=

= 0.1W

10

P =10 0.001 = 0.01W

(

)

Q

FREQUENCY COMPENSATION

Total power dissipation, P_TOT, is 0.69 + 0.1 + 0.01 = 0.8W.

Before starting on the theoretical analysis of frequency

response,thefollowingshouldberemembered—theworse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the ‘LAYOUT CONSIDERATIONS’ section

first. Common layout errors that appear as stability prob-

lems are distant placement of input decoupling capacitor

and/or catch diode, and connecting the V_Ccompensation

to a ground track carrying significant switch current. In

addition,thetheoretical analysisconsidersonlyfirstorder

ideal component behavior. For these reasons, it is impor-

tant that a final stability check is made with production

layout and components.

Thermal resistance for the LT1765 16-lead TSSOP ex-

posed pad package is influenced by the presence of

internal or backside planes. With a full plane under the

package, thermal resistance will be about 45°C/W. With

no plane under the package, thermal resistance will in-

crease to about 110°C/W. For the exposed pad package

θ_JC(PAD)= 10°C/W. Thermal resistance is dominated by

board performance. To calculate die temperature, use the

appropriate thermal resistance number and add in worst-

case ambient temperature:

T_J= T_A+ θ_JA(P_TOT

)

When estimating ambient, remember the nearby catch

diode will also be dissipating power.

The LT1765 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 7,

with both tantalum and ceramic capacitor equivalent cir-

cuits. TheLT1765canbeconsideredastwog_mblocks, the

error amplifier and the power stage.

V V − V

( )( _OUT)( _LOAD

=

I

)

F

IN

P_DIODE

V

IN

V_F= Forward voltage of diode (assume 0.5V at 2A)

0.5 10 − 5 2

(

)(

)( )

LT1765

P_DIODE

=

= 0.5W

10

CURRENT MODE

POWER STAGE

g = 5mho

m

V

SW

FB

OUTPUT

ERROR

AMPLIFIER

Notice that the catch diode’s forward voltage contributes

a significant loss in the overall system efficiency. A larger,

lower V_Fdiode can improve efficiency by several percent.

R1

R2

–

TANTALUM CERAMIC

g

=

m

850µmho

ESR

C1

ESL

C1

+

500k

1.2V

Typicalthermalresistanceoftheboardθ_Bis35°C/W.Atan

ambient temperature of 25°C,

+

GND

V

C

T_J= T_A+ θ_JA(P_TOT) + θ_B(P_DIODE

)

R

C

F

T_J= 25 + 45 (0.8) + 35 (0.5) = 79°C

C

1765 F07

Figure 7. Model for Loop Response

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Figure 8 shows the overall loop response with a 330pF V_C

capacitor and a typical 100µF tantalum output capacitor.

The response is set by the following terms:

ciently at the switching frequency, output ripple will

perturb the V_Cpin enough to cause unstable duty cycle

switching similar to subharmonic oscillation. This may

not be apparent at the output. Small signal analysis will

notshowthissinceacontinuoustimesystemisassumed.

If needed, an additional capacitor (C_F) can be added to the

V_Cpin to form a pole at typically one fifth the switching

frequency (If R_C= ~ 5k, C_F= ~ 100pF)

Error amplifier:

DC gain set by g_mand R_L= 850µ • 500k = 425.

Pole set by C_Fand R_L= (2π • 500k • 330p)^–1= 965Hz.

Unity-gain set by C_Fand g_m= (2π • 330p • 850µ^–1)^–1

410kHz.

=

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and tem-

perature range. Any transient loads should be applied and

the output voltage monitored for a well-damped behavior.

Power stage:

DC gain set by g_mand R_L(assume 5Ω) = 5 • 5 = 25.

Pole set by C_OUTand R_L= (2π • 100µ • 10)^–1= 159Hz.

Unity-gainsetbyC_OUTandg_m=(2π •100µ•5^–1)^–1=8kHz.

Tantalum output capacitor:

CONVERTER WITH BACKUP OUTPUT REGULATOR

Zero set by C_OUTand C_ESR= (2π • 100µ• 0.1)^–1= 15.9kHz.

In systems with a primary and backup supply, for ex-

ample, a battery powered device with a wall adapter input,

the output of the LT1765 can be held up by the backup

supply with its input disconnected. In this condition, the

SW pin will source current into the V_INpin. If the SHDN pin

is held at ground, only the shutdown current of 6µA will be

pulled via the SW pin from the second supply. With the

SHDN pin floating, the LT1765 will consume its quiescent

operating current of 1mA. The V_INpin will also source

current to any other components connected to the input

line. If this load is greater than 10mA or the input could be

shortedtoground, aseriesSchottkydiodemustbeadded,

as shown in Figure 9. With these safeguards, the output

can be held at voltages up to the V_INabsolute maximum

rating.

The zero produced by the ESR of the tantalum output

capacitor is very useful in maintaining stability. Ceramic

output capacitors do not have a zero due to very low ESR,

but are dominated by their ESL. They form a notch in the

1MHzto10MHzrange. Withoutthiszero, theV_Cpolemust

be made dominant. A typical value of 2.2nF will achieve

this.

If better transient response is required, a zero can be

added to the loop using a resistor (R_C) in series with the

compensation capacitor. As the value of R_Cis increased,

transient response will generally improve, but two effects

limit its value. First, the combination of output capacitor

ESR and a large R_Cmay stop loop gain rolling off

altogether. Second, if the loop gain is not rolled suffi-

80

60

180

150

120

90

V

C

= 5V

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

OUT

C

= 100µF, 0.1Ω

= 330pF

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 10 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

configuration with the addition of R3, R4, C_SSand Q1. As

the output starts to rise, Q1 turns on, regulating switch

current via the V_Cpin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current

through C_SSdefined by R4 and Q1’s V_BE. Once the output

is in regulation, Q1 turns off and the circuit operates

normally. R3 is transient protection for the base of Q1.

R /C = 0

C

F

I

= 1A

LOAD

40

PHASE

GAIN

20

0

60

–20

–40

30

0

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

1765 F08

Figure 8. Overall Loop Response

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CMDSH-3

0.18µF

MBRS330T3*

83k

5µH

BOOST

REMOVABLE

INPUT

V

SW

IN

3.3V, 2A

ALTERNATE

SUPPLY

LT1765-3.3

SHDN

SYNC GND

FB

V

C

28.5k

2.2µF

2.2nF

4.7µF

UPS120

1765 F09

* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA

Figure 9. Dual Source Supply with 6µA Reverse Leakage

D2

CMDSH-3

Dual Output Converter

The circuit in Figure 11 generates both positive and

negative 5V outputs with a single piece of magnetics. The

two inductors shown are actually just two windings on a

standard B H Electronics inductor. The topology for the 5V

output is a standard buck converter. The –5V topology

would be a simple flyback winding coupled to the buck

converter if C4 were not present. C4 creates a SEPIC

(single-ended primary inductance converter) topology

which improves regulation and reduces ripple current in

L1. Without C4, the voltage swing on L1B compared to

L1A would vary due to relative loading and coupling

losses. C4 provides a low impedance path to maintain an

equal voltage swing in L1B, improving regulation. In a

flybackconverter,duringswitchontime,alltheconverter’s

energyisstoredinL1Aonly, sincenocurrentflowsinL1B.

At switch off, energy is transferred by magnetic coupling

into L1B, powering the –5V rail. C4 pulls L1B positive

duringswitchontime, causingcurrenttoflow, andenergy

to build in L1B and C4. At switch off, the energy stored in

both L1B and C4 supply the –5V rail. This reduces the

current in L1A and changes L1B current waveform from

square to triangular. For details on this circuit, including

maximum output currents, see Design Note 100.

C2

0.18µF

L1

5µH

OUTPUT

5V

BOOST

INPUT

12V

C3

2.2µF

V

IN

V

SW

1A

+

C1

LT1765-5

SHDN

SYNC GND

D1

100µF

FB

C

V

C

SS

R3

2k

15nF

Q1

C

330pF

1765 F10

R4

47k

D1: UPS120

Q1: 2N3904

Figure 10. Buck Converter with Adjustable Soft Start

(R4)(C_SS)(V_OUT

(V_BE)

)

RiseTime =

Using the values shown in Figure 10,

(47 •10³)(15•10^–9)(5)

RiseTime =

= 5ms

0.7

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

outputcurrentisunchanged. Variantsofthiscircuitcanbe

used for sequencing multiple regulator outputs.

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D2

CMDSH-3

C2

0.18µF

L1A*

BOOST

OUTPUT

INPUT

12V

V

IN

SW

FB

5V AT 1.5A

LT1765-5

SHDN

SYNC GND

4.7µF

6.3V

CERAMIC

V

C

C3

2.2µF

25V

R

3.3k

C

D1

C

CERAMIC

4700pF

GND

C4

4.7µF

16V

CERAMIC

6.3V

L1B*

CERAMIC

OUTPUT

†

–5V AT 1.1A

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS CTX5-1A

D3

1765 F11a

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

D1, D3: B220A

Figure 11a. Dual Output Converter

Max Negative Load vs

Positive Load

1200

1000

800

600

400

200

0

10

100

1000

10000

5V LOAD CURRENT (mA)

1765 F11b

Figure 11b. Dual Output Converter (Output Currents)

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D2

CMDSH-3

C2

0.22µF

L1

3µH

BOOST

INPUT

V

IN

SW

FB

5V

U1

LT1765-5

SYNC

SHDN

C1

D1

B220A

GND

V

C

10µF

6.3V X5R

CERAMIC

C3

C

2.2µF

C

1800pF

16V X5R

C

F

CERAMIC

R

100pF

C

2.4k

OUTPUT

–5V AT 1A

L1: CDRH6D28-3R0

1765 F12

Figure 12. Positive-to-Negative Low Output Ripple Converter

D2

CMDSH-3

INPUT

–5V

C2

0.22µF

L1

2.5µH

BOOST

V

IN

SW

FB

U1

LT1765FE

SYNC

SHDN

D1

UPS120

C1

2.2µF

GND

V

C

6.3V X5R

C3

R2

10k

R1

64.9k

C

22µF

C

4700pF

16V X5R

CERAMIC

C

F

R

100pF

C

6.8k

OUTPUT

–9V AT 1A

L1: CDRH5D28-2R5

BOLD LINES INDICATE HIGH CURRENT PATHS

1765 F13

Figure 13. Negative Boost Converter

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PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663,

Exposed Pad Variation BB)

4.95 – 5.05*

(.196 – .204)

3.8

(.149)

16 1514 13 12 1110

9

6.60 ±0.10

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

4.50 ±0.10

3.0

(.118)

6.25 – 6.50

(.246 – .256)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD

1.15

(.0453)

MAX

4.30 – 4.48*

(.169 – .176)

0° – 8°

0.65

(.0256)

BSC

0.50 – 0.70

(.020 – .028)

0.105 – 0.180

(.0041 – .0071)

0.05 – 0.15

(.002 – .006)

FE16 TSSOP 1101

0.195 – 0.30

(.0077 – .0118)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

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PACKAGE DESCRIPTIO

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

7

5

8

6

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

1

3

4

2

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SO8 1298

sn1765 1765fas

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

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to 600mA at V = 5V

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Q

OUT

550kHz, MS8, V Up to 6V, I = 10µA, I

to 600mA at V = 3.3V

IN

Q

LT1956/LT1956-5 Wide Input Range, 1.5A, Step-Down Regulator

500kHz, V = 5.5V to 60V, Adjustable Fixed 5V,

SSOP-16, TSSOP-16E

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Single Cell, High Current (1A), Micropower, Synchronous 3MHz

Step-Up DC/DC Converter

V = 0.5V to 5V, Up to 97% Efficiency Synchronizable

IN

Oscillator from 100kHz to 3MHz, MS10

Single Cell, High Current (2A), Micropower, Synchronous 3MHz

Step-Up DC/DC Converter

V

IN

= 0.7V to 5V, Up to 95% Efficiency Synchronizable

Oscillator from 100kHz to 3MHz, MS10

1.4MHz High Efficiency, Monolithic Synchronous Step-Down

Regulator

Up to 95% Efficiency, 100% Duty Cycle, I = 10µA,

Q

V

= 2.65V to 6V, MS8

IN

Burst Mode is a registered trademark of Linear Technology Corporation.

ThinSOT is a trademark of Linear Technology Corporation.

sn1765 1765fas

LT/TP 0802 1.5K REV A • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001


型号：	LT1765
厂家：	Linear
描述：	Monolithic 3A, 1.25MHz Step-Down Switching Regulator 单片式3A ， 1.25MHz的降压型开关稳压器稳压器开关
文件：	总20页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1765 [Linear]

相关型号：

LT1765-1.8

LT1765-1.8_15

LT1765-2.5

LT1765-2.5_15

LT1765-3.3

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LT1765EFE#TRPBF