LT1769IGN#PBF_技术文档

LTC1960

Dual Battery Charger/

Selector with SPI Interface

FEATURES

DESCRIPTION

The LTC^®1960 is a highly integrated battery charger and

selector intended for portable products using dual smart

batteries.AserialSPIinterfaceallowsanexternalmicrocon-

troller to control and monitor status of both batteries.

n

Complete Dual-Battery Charger/Selector System

n

Serial SPI Interface Allows External µC Control and

Monitoring

n

Simultaneous Dual-Battery Discharge Extends Run

Time by Typically 10%

A proprietary PowerPath architecture supports simulta-

neous charging or discharging of both batteries. Typical

battery run times are extended by 10%, while charging

times are reduced by up to 50%. The LTC1960 automati-

cally switches between power sources in less than 10µs

to prevent power interruption upon battery or wall adapter

removal.

n

Simultaneous Dual-Battery Charging Reduces

Charging Time by Up to 50%

n

Automatic PowerPath™ Switching in <10µs

Prevents Power Interruption

n

Circuit Breaker Protects Against Overcurrent Faults

n

5% Accurate Adapter Current Limit Maximizes

Charging Rate

n

The synchronous buck battery charger delivers 95% effi-

ciencywithonly0.5Vdropoutvoltage,andpreventsaudible

noise in all operating modes. Patented input current limit-

ing with 5% accuracy charges batteries in the shortest

possible time without overloading the wall adapter.

95% Efficient Synchronous Buck Charger

n

Charger Has Low 0.5V Dropout Voltage

n

No Audible Noise Generation, Even with Ceramic

Capacitors

n

11-Bit VDAC Delivers 0.8% Voltage Accuracy

n

10-Bit IDAC Delivers 5% Current Accuracy

The LTC1960’s 5mm × 7mm 38-pin QFN and 36-pin nar-

row SSOP packages allow implementation of a complete

SBS-compliant dual battery system while consuming

minimum PCB area.

n

V Up to 32V; V

IN

Up to 28V

BATT

n

Available in 5mm × 7mm 38-Pin QFN and 36-Pin

Narrow SSOP Packages

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

APPLICATIONS

No R

and PowerPath are trademarks of Linear Technology Corporation. All other

SENSE

trademarks are the property of their respective owners. Protected by U.S. Patents, including

5481178, 5723970, 6304066, 6580258.

n

Portable Computers

n

Portable Instruments

Dual vs Sequential Charging

TYPICAL APPLICATION

3500

LTC1960 Dual Battery/Selector System Architecture

BAT2

CURRENT

BAT1

CURRENT

3000

2500

2000

1500

1000

500

SEQUENTIAL

DC

IN

0

3500

3000

2500

2000

1500

1000

500

SYSTEM POWER

BAT1

CURRENT

BAT2

DUAL

CURRENT

LTC1960

MICROCONTROLLER

SMBus

100

MINUTES

4

0

SPI

0

100

150

200 250

300

50

BAT2 BAT1

TIME (MINUTES)

1960 TA01

BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)

REQUESTED CURRENT = 3A

REQUESTED VOLTAGE = 12.3V

MAX CHARGER CURRENT = 4.1A

1960 TA01b

1960fb

1

LTC1960

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Voltage from DCIN, SCP, SCN, CLP, V

,

COMP1 to GND ............................................ –0.3V to 5V

Operating Ambient Temperature

Range (Note 7) ............................................ 0°C to 70°C

Operating Junction Temperature............ –40°C to 125°C

Storage Temperature.............................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

PLUS

SW to GND................................................. –0.3V to 32V

Voltage from SCH1, SCH2 to GND ............. –0.3V to 28V

Voltage from BOOST to GND ......................–0.3V to 41V

PGND with Respect to GND ................................... 0.3V

CSP, CSN, BAT1, BAT2 to GND...................... –5V to 28V

LOPWR, DCDIV to GND ............................. –0.3V to 10V

SSB, SCK, MOSI, MISO to GND ................... –0.3V to 7V

SSOP Only........................................................300°C

PIN CONFIGURATION

TOP VIEW

1

2

SCH2

GCH2

GCH1

SCH1

TGATE

BOOST

SW

36

25

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

V

PLUS

BAT2

BAT1

SCN

3

38 37 36 35 34 33 32

4

V

I

1

2

3

4

5

6

7

8

9

31 SCP

30 SCN

SET

I

5

SCP

TH

BAT1

BAT2

29

28

27

26

6

SET

GDCO

GDCI

GB1O

GB1I

GND

DCDIV

SSB

7

V

PLUS

8

DCIN

GND

9

V

CC

39

SCK

25 SCH2

24 GCH2

23 GCH1

22 SCH1

21 TGATE

10

11

12

13

14

15

16

17

18

BGATE

PGND

COMP1

CLP

GB2O

GB2I

MISO

MOSI

LOPWR

GND 10

CSN 11

CSP 12

V

SET

CSP

I

TH

SET

20

BOOST

CSN

I

13 14 15 16 17 18 19

UHF PACKAGE

MOSI

MISO

SCK

GND

DCDIV

SSB

38-LEAD (5mm × 7mm) PLASTIC QFN

G PACKAGE

36-LEAD PLASTIC SSOP

T

= 125°C, θ = 34°C/W

JMAX

JA

THE EXPOSED PAD (PIN 39) IS GND. MUST BE SOLDERED TO THE PCB

T

= 125°C, θ = 70°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LTC1960CG

1960

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC1960CG#PBF

LTC1960CG#TRPBF

LTC1960CUHF#TRPBF

36-Lead Plastic SSOP

0°C to 70°C

LTC1960CUHF#PBF

38-Lead (5mm × 7mm) Plastic QFN

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

1960fb

2

LTC1960

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range (Note 7), otherwise specifications are at T_A= 25°C. V_DCIN= 20V, V_BAT1= 12V, V_BAT2= 12V, unless otherwise noted.

SYMBOL PARAMETER

Supply and Reference

CONDITIONS

MIN

TYP

MAX

UNITS

DCIN Operating Range

DCIN Selected

6

28

V

I

CH

DCIN Operating Current

Not Charging (DCIN Selected)

Charging (DCIN Selected)

1

1.3

1.5

2

mA

Battery Operating Voltage Range

Battery Drain Current

Battery Selected, PowerPath Function (Note 2)

6

28

V

Battery Selected, Not Charging, V

= 0V

175

µA

DCIN

V

Diodes Forward Voltage:

PLUS

V

DCIN to V

I

= 10mA

= 0mA

0.8

0.7

V

FDC

FB1

FB2

PLUS

VCC

BAT1 to V

BAT2 to V

SCN to V

FSCN

l

UVLO

Undervoltage Lockout Threshold

V

Ramping Down, Measured at V

3

5

3.5

3.9

V

PLUS

to GND

UVHYS

UV Lockout Hysteresis

V

Rising, Measured at V to GND

PLUS

60

5.2

0.2

mV

V

PLUS

V

Regulator Output Voltage

Load Regulation

5.4

1

VCC

LDR

CC

I

= 0mA to 10mA

%

VCC

Switching Regulator

V

Overall Voltage Accuracy

Overall Current Accuracy

Regulator Switching Frequency

5V ≤ V

< 25V, (Note 3)

–0.8

–1

0.8

1

%

TOL

OUT

l

I

IDAC Value = 3FF

–5

–6

5

6

%

TOL

HEX

= 12V

V

, V

CSP

CSN

f

255

20

300

25

345

kHz

OSC

Regulator Switching Frequency in Low

Dropout Mode

Duty Cycle ≥ 99%

DO

DC

Regulator Maximum Duty Cycle

Maximum Current Sense Threshold

CA1 Input Bias Current

99

99.5

155

150

%

mV

µA

V

MAX

I

V

= 2.2V

140

190

MAX

SNS

ITH

= V

> 5V

CSN

CSP

CMSL

CMSH

CAI Input Common Mode Low

CAI Input Common Mode High

CL1 Turn-On Threshold

0

V

–0.2

DCIN

V

95

100

105

mV

CL1

TGATE Transition Time:

TGATE Rise Time

TGATE Fall Time

TG t

C

LOAD

C

LOAD

= 3300pF, 10% to 90%

50

90

ns

r

f

BGATE Transition Time:

BGATE Rise Time

BGATE Fall Time

BG t

C

LOAD

C

LOAD

= 3300pF, 10% to 90%

50

40

90

80

ns

r

f

Trip Points

l

V

DCDIV/LOPWR Threshold

V

or V

Falling

Rising

= 1.19V

1.166

1.19

30

1.215

V

mV

nA

mV

V

TR

DCDIV

LOPWR

V

DCDIV/LOPWR Hysteresis Voltage

DCDIV/LOPWR Input Bias Current

Short-Circuit Comparator Threshold

Fast PowerPath Turn-Off Threshold

THYS

BVT

I

20

200

115

7.9

V

– V , V ≥ 5V

90

6

100

7

TSC

SCP

SCN CC

Rising from V

CC

FTO

DCDIV

Overvoltage Shutdown Threshold as a Percent

of Programmed Charger Voltage

Rising from 0.8V Until TGATE and

SET

BGATE Stop Switching

107

%

OVSD

1960fb

3

LTC1960

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range (Note 7), otherwise specifications are at T_A= 25°C. V_DCIN= 20V, V_BAT1= 12V, V_BAT2= 12V, unless otherwise noted.

SYMBOL PARAMETER

DACs

CONDITIONS

MIN

TYP

MAX

UNITS

I

IDAC Resolution

Guaranteed Monotonic Above I

/16

10

6

bits

RES

MAX

IDAC Pulse Period:

Normal Mode

Low Current Mode

t

10

50

15

µs

ms

IP

ILOW

V

VDAC Resolution

VDAC Granularity

VDAC Offset

Guaranteed Monotonic (5V < V < 25V)

11

bits

mV

V

RES

STEP

OFF

BAT

16

0.8

11

(Note 6)

t

VP

VDAC Pulse Period

7

16.5

µs

Charge MUX Switches

t

GCH1/GCH2 Turn-On Time

GCH1/GCH2 Turn-Off Time

V

– V

> 3V, C = 3nF

LOAD

5

3

10

7

ms

µs

ONC

GCHX

SCHX

V

GCHX

V

BATX

< 1V, from Time of V

<

CSN

– 30mV, C

= 3nF

LOAD

V

CON

CH Gate Clamp Voltage

GCH1

GCH2

I

= 1µA

GCH1

GCH2

LOAD

V

– V

5

5.8

7

V

SCH1

SCH2

V

COFF

CH Gate Off Voltage

GCH1

GCH2

I

= 10µA

LOAD

V

– V

–0.8

–0.4

0

V

GCH1

GCH2

SCH1

SCH2

l

V

CH Switch Reverse Turn-Off Voltage

CH Switch Forward Regulation Voltage

V

– V

, 5V ≤ V

≤ 28V

5

20

35

40

60

mV

TOC

CSN

BATX

– V , 5V ≤ V

≤ 28V

15

FC

BATX

GCHX

CSN

BATX

GCH1/GCH2 Active Regulation:

Max Source Current

Max Sink Current

– V

= 1.5V

SCHX

I

–2

2

µA

OC(SRC)

OC(SNK)

V

BATX Voltage Below Which Charging Is Inhibited (Note 8)

PowerPath Switches

3.5

4.7

V

CHMIN

t

Blanking Period After UVLO Trip

Blanking Period After LOPWR Trip

GB1O/GB2O/GDCO Turn-On Time

Switches Held Off

Switches in 3-Diode Mode

< –3V, from Time of Battery/DC

250

1

ms

sec

µs

DLY

PPB

l

V

5

10

7

ONPO

GS

Removal, or LOPWR Indication

t

GB1O/GB2O/GDCO Turn-Off Time

V

GS

> –1V, from Time of Battery/DC

3

µs

OFFPO

Removal, or LOPWR Indication

V

PONO

Output Gate Clamp Voltage

I

= 1µA

LOAD

GB1O

GB2O

GDCO

Highest (V

or V ) – V

4.75

6.25

7

V

BAT1

BAT2

DCIN

SCP

GB1O

GB2O

GDCO

or V ) – V

SCP

or V ) – V

SCP

V

POFFO

Output Gate Off Voltage

I

= –25µA

LOAD

GB1O

GB2O

GDCO

Highest (V

or V ) – V

0.18

0.25

V

BAT1

BAT2

DCIN

SCP

GB1O

GB2O

GDCO

or V ) – V

SCP

or V ) – V

SCP

l

V

PowerPath Switch Reverse Turn-Off Voltage

V

– V

SCP

or V

– V

DCIN

5

0

20

60

mV

TOP

SCP

BATX

SCP

6V ≤ V

≤ 28V

PowerPath Switch Forward Regulation Voltage

V

BATX

– V

SCP

or V

– V

25

50

mV

FP

SCP

DCIN SCP

6V ≤ V

≤ 28V

GDCI/GB1I/GB2I Active Regulation

Source Current

Sink Current

(Note 4)

I

–4

75

µA

OP(SRC)

OP(SNK)

1960fb

4

LTC1960

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range (Note 7), otherwise specifications are at T_A= 25°C. V_DCIN= 20V, V_BAT1= 12V, V_BAT2= 12V, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

300

10

MAX

UNITS

µs

t

Gate B1I/B2I/DCI Turn-On Time

Gate B1I/B2I/DCI Turn-Off Time

V

GS

< –3V, C

> –1V, C

= 3nF (Note 5)

ONPI

LOAD

t

V

µs

OFFPI

V

PONI

Input Gate Clamp Voltage

I

= 1µA

LOAD

GB1I

GB2I

GDCI

Highest (V

or V ) – V

4.75

6.7

7.5

V

BAT1

BAT2

DCIN

SCP

GB1I

GB2I

GDCI

or V ) – V

SCP

or V ) – V

SCP

V

POFFI

Input Gate Off Voltage

I

= 25µA

LOAD

GB1I

GB2I

GDCI

Highest (V

or V ) – V

0.18

0.25

V

BAT1

BAT2

DCIN

SCP

GB1I

GB2I

GDCI

or V ) – V

SCP

or V ) – V

SCP

Logic I/O

I /I

l

SSB/SCK/MOSI Input High/Low Current

SSB/MOSI/SCK Input Low Voltage

SSB/MOSI/SCK Input High Voltage

MISO Output Low Voltage

–1

2

1

µA

V

IH IL

V

0.8

IL

IH

V

I

= 1.3mA

0.4

2

V

OL

OFF

OL

I

MISO Output Off-State Leakage Current

V

= 5V

µA

MISO

LOAD

SPI Timing (See Timing Diagram)

l

T

Watch Dog Timer

1.2

680

2

2.5

4.5

sec

ns

µs

ns

WD

SSH

CYC

SH

SL

LD

LG

su

t

SSB High Time

SCK Period

C

= 200pF R

= 4.7k on MISO

PULLUP

SCK High Time

680

200

100

SCK Low Time

Enable Lead Time

Enable Lag Time

l

Input Data Set-Up Time

Input Data Hold Time

Access Time (From Hi-Z to Data Active on MISO)

Disable Time (Hold Time to Hi-Z State on MISO)

Output Data Valid

H

125

580

A

dis

V

C = 200pF, R

= 4.7k on MISO

L

PULLUP

Output Data Hold

0

HO

Ir

SCK/MOSI/SSB Rise Time

SCK/MOSI/SSB Fall Time

MISO Fall Time

0.8V to 2V

2V to 0.8V

250

400

If

l

2V to 0.4V, C = 200pF

Of

L

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. Battery voltage must be adequate to drive gates of PowerPath

P-channel FET switches. This does not affect charging voltage of the

battery, which can be zero volts.

Note 3. See Test Circuit.

Note 4. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are

forced to 10.5V. SCP is set at 12.0V to measure source current at GDCI,

GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I

and GB2I.

Note 5. Extrapolated from testing with C = 50pF.

L

Note 6. VDAC offset is equal to the reference voltage, since

V

OUT

= V (16mV • VDAC

/2047 + 1)

(VALUE)

REF

Note 7. The LTC1960C is guaranteed to meet specified performance from

0°C to 70°C and is designed, characterized and expected to meet specified

performance at –40°C and 85°C, but is not tested at these extended

temperature limits.

Note 8. Does not apply to low current mode. Refer to “The Current DAC

Block” in the Operation section.

1960fb

5

LTC1960

TYPICAL PERFORMANCE CHARACTERISTICS

Battery Drain Current

(BAT1 Selected)

PowerPath Autonomous

Switching

PowerPath Switching

250

240

230

220

210

200

190

180

170

160

150

16

15

14

13

12

11

10

9

16

15

14

13

12

11

10

9

T

= 25°C

C

= 20µF

= 0.8A

A

LOAD

I

T

= 25°C

A

BAT1

REMOVED

LOPWR

THRESHOLD

8

NOTE: LIGHT LOAD TO

EXAGGERATE SWITCHING EVENT

7

6

12

18

24

30

–10

–50 –40 –30 –20

0

10 20 30 40 50

–1

0

2

3

4

5

1

BAT1 VOLTAGE (V)

TIME (µs)

TIME (SEC)

1960 G03

1960 G01

1960 G02

Charger Efficiency

Charger Start-Up

Charger Load Dump

100

90

80

70

60

50

40

30

20

10

0

12

10

8

14

12

10

8

BAT1

OUTPUT

V

= 20V

IN

VDAC = 12.29V

IDAC = 3000mA

LOAD CURRENT = 1A

= 25°C

T

A

6

LOAD

CONNECTED

4

2

LOAD

DISCONNECTED

2

0

–4 –2

6

8

10 12 14 16

0

0.025

0.10

0.50

2.5 4.0

0

2

4

–0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

I

(A)

TIME (ms)

TIME (SEC)

OUT

1960 G04

1960 G06

1960 G05

IDAC Low Current Mode

vs Normal Mode

Charger Load Regulation

Charging Current Accuracy

500

450

400

350

300

250

200

150

100

50

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

120

100

80

V

= 20V

V

= 20V

IN

BAT1

DCIN

BAT1

SNS

= 12V

R

T

= 0.025Ω

R

T

= 0.025Ω

= 25°C

SNS

= 25°C

A

60

LOW CURRENT

MODE

40

20

NORMAL

MODE

V

= 20V

0

IN

VDAC = 12.288V

IDAC = 4000mA

–20

–40

T

= 25°C

A

0

1000

2000

3000

4000

1000

0

160

240 320 400 480 560

0

200

400

600

800

1200

80

IDAC VALUE

PROGRAMMED CURRENT (mA)

CHARGE CURRENT (mA)

1960 G08

1960 G07

1960 G09

1960fb

6

LTC1960

TYPICAL PERFORMANCE CHARACTERISTICS

Dual Charging Batteries with

Different Charge State

Voltage Accuracy

Dual vs Sequential Charging

3500

3000

2500

2000

1500

1000

500

3500

3000

2500

2000

1500

1000

500

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

100

75

BAT2

VOLTAGE

BAT1

BAT2

BAT1

DCIN = 24V

CURRENT

T

= 25°C

A

I

= 100mA

LOAD

SEQUENTIAL

VOLTAGE

50

25

0

3500

3000

2500

2000

1500

1000

500

BAT1

–25

–50

–75

–100

CURRENT

BAT2

DUAL

CURRENT

BAT2

CURRENT

100

MINUTES

0

20 40 60 80 100

TIME (MINUTES)

120

140 160

1250

0

250

450

650

VDAC VALUE

850 1050

1450

0

100

150

200 250

300

50

TIME (MINUTES)

1960 G10

BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)

REQUESTED CURRENT = 3A

BAT1 INITIAL CAPACITY = 0%

BAT2 INITIAL CAPACITY = 90%

PROGRAMMED CHARGER CURRENT = 3A

PROGRAMMED CHARGER VOLTAGE = 16.8V

REQUESTED VOLTAGE = 12.3V

MAX CHARGER CURRENT = 4.1A

1960 G12

1960 G11

Dual vs Sequential Discharge

15

14

13

12

11

10

15

14

13

12

11

10

12.0

BAT1

VOLTAGE

DUAL

BAT2

VOLTAGE

11.0

10.0

9.0

DUAL

BAT2

VOLTAGE

BAT1

VOLTAGE

BAT2

8.0

BAT2

VOLTAGE

SEQUENTIAL

VOLTAGE

12.0

11.0

10.0

9.0

SEQUENTIAL

BAT1

VOLTAGE

BAT1

VOLTAGE

11

MINUTES

16

MINUTES

8.0

0

20

60

80

100

140

40

120

160

180

0

20

60 80 100

140

40

120

TIME (MINUTES)

BATTERY TYPE: 12V NIMH (MOLTECH NJ1020)

BATTERY TYPE: 10.8V Li-Ion(MOLTECH NI2020)

1960 G14

LOAD: 33W

LOAD CURRENT = 3A

1960 G13

1960fb

7

LTC1960

PIN FUNCTIONS ^(G/UHF)

Input Power Related

Battery Charging Related

V (Pin 13/Pin 1): The Tap Point of a Programmable

SET

SCN (Pin 4/Pin 30): PowerPath Current Sensing Negative

Input.Thispinshouldbeconnecteddirectlytothe“bottom”

ResistorDividerWhichProvidesBatteryVoltageFeedback

to the Charger. A capacitor from CSN to V and from

(output side) of the sense resistor, R , in series with the

SC

SET

three PowerPath switch pairs, for detecting short-circuit

current events. Also powers LTC1960 internal circuitry

when all other sources are absent.

V

toGNDprovidenecessarycompensationandfiltering

SET

for the voltage loop.

I

(Pin 14/Pin 2): The Control Signal of the Inner Loop of

TH

SCP (Pin 5/Pin 31): PowerPath Current Sensing Positive

theCurrentModePWM.HigherI voltagecorrespondsto

TH

Input. This pin should be connected directly to the “top”

higher charging current in normal operation. A capacitor

of at least 0.1µF to GND filters out PWM ripple. Typical

full-scale output current is 30µA. Nominal voltage range

for this pin is 0V to 2.4V.

(switch side) of the sense resistor, R , in series with the

SC

three PowerPath switch pairs, for detecting short-circuit

current events.

GDCO (Pin 6/Pin 32): DCIN Output Switch Gate Drive.

TogetherwithGDCI,thispindrivesthegateoftheP-channel

switch in series with the DCIN input switch.

I

(Pin 15/Pin 3): A capacitor from I

to ground is

SET

required to filter higher frequency components from the

delta-sigma IDAC.

GDCI (Pin 7/Pin 33): DCIN Input Switch Gate Drive.

Together with GDCO, this pin drives the gate of the

P-channel switch connected to the DCIN input.

CSN (Pin 22/Pin 11): Current Amplifier CA1 Input. Con-

nect this to the common output of the charger MUX

switches.

GB1O (Pin 8/Pin 34): BAT1 Output Switch Gate Drive.

TogetherwithGB1I,thispindrivesthegateoftheP-channel

switch in series with the BAT1 input switch.

CSP (Pin 23/Pin 12): Current Amplifier CA1 Input. This

pin and the CSN pin measure the voltage across the

sense resistor, R , to provide the instantaneous cur-

SNS

rent signals required for both peak and average current

GB1I (Pin 9/Pin 35): BAT1 Input Switch Gate Drive.

TogetherwithGB1O,thispindrivesthegateoftheP-channel

switch connected to the BAT1 input.

mode operation.

COMP1 (Pin 25/Pin 14): The Compensation Node for the

AmplifierCL1. AcapacitorisrequiredfromthispintoGND

if input current amplifier CL1 is used. At input adapter

current limit, this node rises to 1V. By forcing COMP1 low,

amplifier CL1 will be defeated (no adapter current limit).

COMP1 can source 10µA.

GB2O (Pin 10/Pin 36): BAT2 Output Switch Gate Drive.

TogetherwithGB2I,thispindrivesthegateoftheP-channel

switch in series with the BAT2 input switch.

GB2I (Pin 11/Pin 37): BAT2 Input Switch Gate Drive.

TogetherwithGB2O,thispindrivesthegateoftheP-channel

switch connected to the BAT2 input.

BGATE(Pin27/Pin16):DrivesthebottomexternalMOSFET

of the battery charger buck converter.

CLP (Pin 24/Pin 13): The Positive Input to the Supply

Current Limiting Amplifier CL1. The threshold is set at

100mV above the voltage at the DCIN pin. When used

to limit supply current, a filter is needed to filter out the

switching noise.

SW(Pin30/Pin19):PWMswitchnodeconnectedtosource

of the top external MOSFET switch. Used as reference for

top gate driver.

BOOST (Pin 31/Pin 20): Supply to Topside Floating Driver.

The bootstrap capacitor is returned to this pin. Voltage

swing at this pin is from a diode drop below V to (DCIN

CC

+ V ).

CC

1960fb

8

LTC1960

PIN FUNCTIONS ^(G/UHF)

TGATE (Pin 32/Pin 21): Drives the top external MOSFET

DCIN (Pin 29/Pin 18): Supply. External DC power source.

A 1µF bypass capacitor should be connected to this pin as

close as possible. No series resistance is allowed, since

the adapter current limit comparator input is also this pin.

of the battery charger buck converter.

SCH1 (Pin 33/Pin 22), SCH2 (Pin 36/Pin 25): Charger

MUX N-Channel Switch Source Returns. These two pins

are connected to the sources of the back-to-back switch

pairs, Q3/Q4 and Q9/Q10 (see Typical Application on back

page of data sheet), respectively. A small pull-down cur-

rent source returns these nodes to 0V when the switches

are turned off.

Internal Power Supply Pins

GND (Pin 16/Pin 4, Pin 10, Pin 26, Pin 39): Ground for

Low Power Circuitry.

PGND (Pin 26/Pin 15): High Current Ground Return for

BGATE Driver.

GCH1 (Pin 34/Pin 23), GCH2 (Pin 35/Pin 24): Charger

MUX N-Channel Switch Gate Drives. These two pins drive

the gates of the back-to-back switch pairs, Q3/Q4 and Q9/

Q10, between the charger output and the two batteries.

V

CC

(Pin 28/Pin 17): Internal Regulator Output. Bypass

this output with at least a 2µF to 4.7µF capacitor. Do not

use this regulator output to supply more than 1mA to

external circuitry.

External Power Supply Pins

Digital Interface Pins

V

(Pin 1/Pin 27): Supply. The V

pin is connected

PLUS

SSB (Pin 18/Pin 6): SPI Slave Select Input. Active low.

TTL levels. This signal is low when clocking data to/from

the LTC1960.

via four internal diodes to the DCIN, SCN, BAT1, and BAT2

pins. Bypass this pin with a 1µF to 2µF capacitor.

BAT1 (Pin 3/Pin 29), BAT2 (Pin 2/Pin 28): These two

pins are the inputs from the two batteries for power to

the LTC1960 and to provide voltage feedback to the bat-

tery charger.

SCK (Pin 19/Pin 7): Serial SPI Clock. TTL levels.

MISO (Pin 20/Pin 8): SPI Master-In-Slave-Out Output,

Open Drain. Serial data is transmitted from the LTC1960,

when SSB is low, on the falling edge of SCK. TTL levels.

A 4.7k pull-up resistor is recommended.

LOPWR (Pin 12/Pin 38): LOPWR Comparator Input from

SCN External Resistor Divider to GND. If the voltage at

LOPWR is lower than the LOPWR comparator threshold,

then system power has failed and power is autonomously

switched to a higher voltage source, if available. See

PowerPath section of LTC1960 operation.

MOSI(Pin21/Pin9):SPIMaster-Out-Slave-InInput.Serial

data is transmitted to the LTC1960, when SSB is low, on

the rising edge of SCK. TTL levels.

GND (Exposed Pad Pin 39, UHF Package Only): Ground.

Must be soldered to the PCB ground for rated thermal

performance.

DCDIV (Pin 17/Pin 5): External DC Source Comparator

Input from DCIN External Resistor Divider to GND. If the

voltage at DCDIV is above the DCDIV comparator thresh-

old, then the DC bit is set and the wall adapter power is

consideredtobeadequatetochargethebatteries.IfDCDIV

rises more than 1.8V above V , then all of the PowerPath

CC

switches are latched off until all power is removed.

AcapacitorfromDCDIVtoGNDisrecommendedtoprevent

noise-induced false emergency turn-off conditions from

being detected. Refer to “Fast PowerPath Turn-Off” in the

Operation section and the Typical Application on the back

page of this data sheet.

1960fb

9

LTC1960

BLOCK DIAGRAM ^{(LTC1960CG Pin Numbers Shown)}

GB1I GB1O

GB2I GB2O

11 10

GDCI GDCO

9

8

7

6

100mV

SCP

5

+

SHORT CIRCUIT

AC_PRESENT

100Ω

CHARGE

PUMP

SWB1

DRIVER

SWB2

DRIVER

SWDC

DRIVER

DCIN

–

SCN

4

+

–

DCDIV

17

ON

–

+

GCH1

SCH1

34

33

+

–

LOPWR

12

SELECTOR

CONTROLLER

ON

–

+

GCH2

SCH2

1.19V

35

36

CSN

21 MOSI

20 MISO

BAT1

BAT2

3

2

SPI

INTERFACE

CHGMON

CHARGE

SCK

19

400k

18 SSB

11

V

1

SCN

PLUS

15

I

11-BIT ∆Σ

VOLTAGE DAC

10-BIT ∆Σ

CURRENT DAC

SET

V

28

16

CC

V

CC

CSP-CSN

3kΩ

REGULATOR

–

+

GND

0.86V

0.8V

0V

DCIN

29

13

V

SET

Ω

g

= 1.4m

–

m

3k

–

EA

CSP

CSN

23

22

OSCILLATOR

LOW DROP

DETECT

+

CA1

+

BGATE

T

Ω

ON

g

= 1.4m

–

+

m

CA2

31

32

30

BOOST

TGATE

SW

S

R

0.8V

TH

Q

BUFFERED I

PWM

LOGIC

÷15

+

–

+

–

I

CHARGE

CMP

V

CC

BGATE

PGND

27

26

–

+

I

REV

40mV

Ω

g

= 0.4m

–

m

DCIN

CLP

+

100mV

CL1

0.75V

–

+

CHGMON

24

CLAMP

1960 BD

25

14

COMP1

I

TH

1960fb

10

LTC1960

TEST CIRCUIT

+

–

V

REF

EA

CHGMON

V

SW

I

BAT1

BAT2

V

SET

TH

+

–

0.5V

1960 TC01

TIMING DIAGRAM

SPI Timing Diagram

SSB

SCK

t

SSH

t

LD

CYC

LG

t

SH

t

SL

H

t

su

MOSI

BIT 7

BIT 0

t

HO

t

dis

A

V

SLAVE

BIT 7 OUT

SLAVE

BIT 0 OUT

MISO

1960 TD01

1960fb

11

LTC1960

OPERATION ^{(Refer to Block Diagram and Typical Application)}

OVERVIEW

to reduce the power dissipation in the PFET bulk diode. In

effect, this system provides diode -like behavior from the

FET switches, without the attendant high power dissipa-

tion from diodes. The microprocessor is informed of this

3-diode mode status when it polls the PowerPath status

registerviatheSPIinterface.Themicroprocessorcanthen

assess which power source is capable of providing power,

and program the PowerPath switches accordingly. Since

high speed PowerPath switching at LOPWR trip points

is handled autonomously, there is no need for real-time

microprocessor resources to accomplish this task.

The LTC1960 is composed of a battery charger controller,

charge MUX controller, PowerPath controller, SPI inter-

face, a 10-bit current DAC (IDAC) and 11-bit voltage DAC

(VDAC). When coupled with a low cost microprocessor, it

forms a complete battery charger/selector system for two

batteries. The battery charger is programmed for voltage

and current, and the charging battery is selected via the

SPI interface. Charging can be accomplished only if the

voltage at DCDIV indicates that sufficient voltage is avail-

able from the input power source, usually an AC adapter.

The charge MUX, which selects the battery to be charged,

is capable of charging both batteries simultaneously by

selecting both batteries for charging. The charge MUX

switch drivers are configured to allow charger current to

share between the two batteries and to prevent current

from flowing in a reverse direction in the switch. The

amount of current that each battery receives will depend

upon the relative capacity of each battery and the battery

voltage. This can result in significantly shorter charging

times (up to 50% for Li-Ion batteries) than sequential

charging of each battery. In order to continue charging,

the CHARGE_BAT information must be updated more

frequently than the internal watchdog timer.

Simultaneousdischargeofbothbatteriesisaccomplished

by simply programming both batteries for discharge into

thesystemload.Theswitchdriverspreventreversecurrent

flow in the switches and automatically discharge both bat-

teriesintotheload,sharingcurrentaccordingtotherelative

capacityofthebatteries. Simultaneousdualdischargecan

increase battery operating time by approximately 10%

by reducing losses in the switches and reducing internal

losses associated with high discharge rates.

SPI Interface

TheSPIinterfaceisusedtowritetotheinternalPowerPath

registers, the charger control registers, the current DAC,

and the voltage DAC. The SPI is also able to read internal

status registers. There are two types of SPI write com-

mands.Thefirstwritecommandisa1-bytecommandused

to load PowerPath and charger control bits. The second

write command is a 2-byte command used to load the

DACs. The SPI read command is a 2-byte command. In

order to ensure the integrity of the SPI communication,

the last bit received by the SPI is echoed back over the

MISO output after the next falling SCK. The data format

is set up so that the master has the option of aborting a

write if the returned MISO bit is not as expected.

The PowerPath controller selects which of the pairs of

PFET switches, input and output, will provide power to

the system load. The selection is accomplished over

the SPI interface. If the system voltage drops below the

threshold set by the LOPWR resistor divider, then all of

the output side PFETs are turned on quickly and power

is taken from the highest voltage source available at the

DCIN, BAT1 or BAT2 inputs. The input side PFETs act as

diodes in this mode and power is taken from the source

with the highest voltage. The input side PowerPath switch

driver that is delivering power then closes its input switch

1960fb

12

LTC1960

OPERATION

1-Byte SPI Write Format:

bit 7........byte 1..........bit 0

D0 D1 D2 X A0 A1 A2 0

X D0 D1 D2 X A0 A1 A2

A[2:0] = b111

MOSI

MISO

Charger Write Address:

Charger Write Data:

D2 = X

D1 = CHARGE_BAT2

D0 = CHARGE_BAT1

A[2:0] = b110

PowerPath Write Address:

PowerPath Write Data:

D2 = POWER_BY_DC

D1 = POWER_BY_BAT2

D0 = POWER_BY_BAT1

2-Byte SPI Write Format:

bit 7........byte 1..........bit 0

D0 D1 D2 D3 D4 D5 D6 1

X D0 D1 D2 D3 D4 D5 D6

A[2:0] = b000

bit 7..........byte 2............bit 0

MOSI

D7 D8 D9 D10 A0 A1 A2 0

1 D7 D8 D9 D10 A0 A1 A2

MISO

IDAC Write Address:

IDAC Data Bits D9-D0:

IDAC Data Bit D10 :

VDAC Write Address:

VDAC Data Bits D10-D0:

IDAC value data (MSB-LSB)

Normal mode = 0, low current mode = 1 (Dual battery charging is disabled)

A[2:0] = b001

VDAC value (MSB-LSB)

Subsequent SPI communication is inhibited until after the addressed DAC is finished loading. It is recommended that

the master transmit all zeros until MISO goes low. This handshaking procedure is illustrated in Figure 1.

BYTE 1

BYTE 2

SSB

SCK

MOSI

MISO

1960 F01

Figure 1. SPI Write to VDAC of Data = b101_0101_0101

1960fb

13

LTC1960

OPERATION

2-Byte SPI Read Format:

bit 7........byte 1.......bit 0

0 0 0 0 A0 A1 A2 0

X 0 0 0 0 A0 A1 A2

A[2:0] = b010

bit 7........byte 2............bit 0

0 A0 A1 A2 1

X FA LP DC PF CH X

MOSI

0 0 0

MISO

X

Status Address:

Status Read Data:

LP = LOW_POWER (Low power comparator output)

DC = DCDIV (DCDIV comparator output)

PF=POWER_FAIL(Setifselectedpowersupplyfailedtoholdupsystempowerafter

three tries)

CH = CHARGING (One or more batteries are being charged)

FA = FAULT. This bit is set for any of the following conditions:

1) The LTC1960 is still in power-on reset.

2) The LTC1960 has detected a short circuit and has shut down power and charging.

3) The system has asserted a fast off using DCDIV.

Note: All other values of A[2:0] are reserved and must not be used.

A status read is illustrated in Figure 2.

BYTE 1

SSB

BYTE 2

SCK

MOSI

MISO

1960 F02

Figure 2. SPI Read of FA = 0, LP = 0, DC = 1, PF = 0, and CH = 1

1960fb

14

LTC1960

OPERATION

Battery Charger Controller

the boost capacitor. It is also required for stability and

power-on reset purposes.

The LTC1960 charger controller uses a constant off-time,

current mode step-down architecture. During normal

operation, the top MOSFET is turned on each cycle when

the oscillator sets the SR latch and turned off when the

main current comparator ICMP resets the SR latch. While

the top MOSFET is off, the bottom MOSFET is turned on

until either the inductor current reverses, as indicated by

current comparator IREV, or the beginning of the next

cycle. The oscillator uses the equation:

As V decreases towards the selected battery voltage,

IN

the converter will attempt to turn on the top MOSFET

continuously (“dropout’’). A dropout timer detects this

condition and forces the top MOSFET to turn off, and the

bottom MOSFET on, for about 200ns at 40µs intervals to

recharge the bootstrap capacitor.

Charge MUX Switches

1

f_OSC

(V_DCIN− V_CSN)

The equivalent circuit of a charge MUX switch driver is

shown in Figure 3. If the charger controller is not enabled,

the charge MUX drivers will drive the gate and source of

the series-connected MOSFETs to a low voltage and the

switch is off. When the chargercontrolleris on, the charge

MUX driver will keep the MOSFETs off until the voltage at

CSN rises at least 35mV above the battery voltage. GCH1

is then driven with an error amplifier EAC until the volt-

age between BAT1 and CSN satisfies the error amplifier

or until GCH1 is clamped by the internal Zener diode.

The time required to close the switch could be quite long

(many ms) due to the small currents output by the error

amp and depending upon the size of the MOSFET switch.

t_OFF

=

•

V_DCIN

to set the bottom MOSFET on time. The peak inductor

current at which ICMP resets the SR latch is controlled

by the voltage on I . I is in turn controlled by several

TH TH

loops, depending upon the situation at hand. The average

currentcontrolloopconvertsthevoltagebetweenCSPand

CSN to a representative current. Error amp CA2 compares

this current against the desired current requested by the

IDAC at the I

pin and adjusts I until the IDAC value

SET

TH

is satisfied. The BAT1/BAT2 MUX provides the selected

battery voltage at CHGMON, which is divided down to the

V

pin by the VDAC resistor divider and is used by error

SET

If the voltage at CSN decreases below V

– 20mV, a

BAT1

ampEAtodecreaseI iftheV voltageisabovethe0.8V

TH

SET

comparator CC quickly turns off the MOSFETs to prevent

reverse current from flowing in the switches. In essence,

this system performs as a low forward voltage diode.

Operation is identical for BAT2.

reference. The amplifier CL1 monitors and limits the input

current, normally from the AC adapter, to a preset level

(100mV/R ). At input current limit, CL1 will decrease the

CL

I

voltage and thus reduce battery charging current.

TH

DCIN + 10V

An overvoltage comparator, 0V, guards against transient

overshoots (>7%). In this case, the top MOSFET is turned

off until the overvoltage condition is cleared. This feature

is useful for batteries which “load dump” themselves by

opening their protection switch to perform functions such

as calibration or pulse mode charging.

(CHARGE PUMPED)

BAT1

CSN

TO

BATTERY

1

–

+

GCH1

SCH1

Q3

EAC

35mV

FROM

CHARGER

+

–

Charging is inhibited for battery voltages below the mini-

CC

20mV

10k

mumchargingthreshold,V

.Chargingisnotinhibited

CHMIN

Q4

OFF

when the low current mode of the IDAC is selected.

The top MOSFET driver is powered from a floating boot-

strap capacitor C . This capacitor is normally recharged

B

1960 F03

from V through an external diode when the top MOSFET

CC

is turned off. A 2µF to 4.7µF capacitor across V to GND

Figure 3. Charge MUX Switch Driver Equivalent Circuit

CC

is required to provide a low dynamic impedance to charge

1960fb

15

LTC1960

OPERATION

Dual Charging

voltages present at the input/output. When the output

PFET turns on, the voltage at SCP will be pulled up to a

diode drop below the source voltage by the bulk diode of

the input PFET. If the source voltage is more than 25mV

above SCP, EAP will drive the gate of the input PFET low

until the input PFET turns on and reduces the voltage

across the input/output to the EAP set point, or until the

Zener clamp engages to limit the voltage applied to the

input PFET. If the source voltage drops more than 20mV

below SCP, then comparator CP turns on SWP to quickly

prevent large reverse current in the switch. This operation

mimics a diode with a low forward voltage drop.

Note that the charge MUX switch drivers will operate

together to allow both batteries to be charged simultane-

ously. If both charge MUX switch drivers are enabled,

only the battery with the lowest voltage will be charged

until its voltage rises to equal the higher voltage battery.

The charge current will then share between the batteries

according to the capacity of each battery.

If both batteries are selected for charging, only batteries

with voltages above V

charging is not allowed when the low current mode of

the IDAC is selected. If dual charging is enabled when

the IDAC enters low current mode, then only BAT1 will

be charged.

are allowed to charge. Dual

CHMIN

OFF

20mV

–

+

CP

Charger Start-Up

FROM

BATTERY

1

WhenthechargercontrollerisenabledbytheSPIInterface

block, the charger output CSN will ramp from 0V until it

exceedstheselectedbatteryvoltage. Theclamperroramp

is used to prevent the charger output from exceeding the

selected battery voltage by more than 0.7V during the

start-up transient while the charge MUX switches, have

yet to close. Once the charge MUX switches have closed,

BAT1

SWP

–

+

GB1I

Q7

Q8

EAP

SCP

25mV

GB1O

OFF

the clamp releases I to allow control by another loop.

TH

PowerPath Controller

R

SC

TO

The PowerPath switches are turned on and off via the SPI

interface, in any combination. The external P-MOSFETs

are usually connected as an input switch and an output

switch. TheoutputswitchPFETisconnectedinserieswith

the input PFET and the positive side of the short-circuit

LOAD

C

L

1960 F04

Figure 4. PowerPath Driver Equivalent Circuit

Autonomous PowerPath Switching

sensing resistor, R . The input switch is connected in

SC

The LOPWR comparator monitors the voltage at the

load through the resistor divider from pin SCN. If any

POWER_BY bit is set and the LOPWR comparator trips,

then all of the switches are turned on (3-diode mode) by

the PowerPath controller to ensure that the system is

powered from the source with the highest voltage. The

PowerPath controller waits approximately 1 second, to

allow power to stabilize, and then reverts to the previous

PowerPath switch configuration. A power-fail counter is

incremented to indicate that a failure has occurred. If the

power-fail counter equals a value of 3, then the PowerPath

series between the power source and the output PFET.

The PowerPath switch driver equivalent circuit is shown

in Figure 4. The output PFET is driven high and low by the

output side driver controlling pin GXXO, the PFET is either

on or off. The gate of the input PFET is driven by an error

amplifier which monitors the voltage between the input

power source (BAT1 in this case) and SCP. If the switch

is turned off, the two outputs are driven to the higher of

thetwovoltagespresentacrosstheinput/outputterminals

of the switch. When the switch is instructed to turn on,

the output side driver immediately drives the gate of the

output PFET approximately 6V below the highest of the

controller sets the switches to 3-diode mode and the PF

1960fb

16

LTC1960

OPERATION

bit is set in the status register. This is a three-strikes-and-

you’re-out process which is intended to debounce the

PowerPath PF indicator. The power-fail counter is reset

by a PowerPath SPI write.

delay is to prevent oscillation from a turn-on transient

near the UVLO threshold.

The Voltage DAC Block

The voltage DAC (VDAC) is a delta-sigma modulator

which controls the effective value of an internal resistor,

VSET

voltage. Figure 5 is a simplified diagram of the VDAC

operation. The charger monitor MUX is connected to the

appropriate battery indicated by the CHARGE_BATx bit.

The delta-sigma modulator and switch SWV convert the

VDAC value, received via SPI communication, to a vari-

Short-Circuit Protection

Short-circuit protection operates in both a current mode

and a voltage mode. If the voltage between SCP and SCN

exceeds the short-circuit comparator threshold V

more than 15ms, then all of the PowerPath switches are

turned off and the FAULT bit (FA) is set. Similarly, if the

voltage at SCN falls below 3V for more than 15ms, then

all of the PowerPath switches are turned off and the FA bit

is set. The FA bit is reset by removing all power sources

R

= 7.2k, used to program the maximum charger

for

TSC

ableresistanceequalto(11/8)R

/(VDAC

/2047).

VSET

(VALUE)

In regulation, V

is servo driven to the 0.8V reference

SET

and allowing the voltage at V

threshold. If the FA bit is set, charging is disabled until

to fall below the UVLO

voltage, V

.

PLUS

REF

Therefore, programmed voltage is:

= (8/11) V 405.3k/7.2k • (VDAC /2047)

(VALUE)

V

exceeds the UVLO threshold and charging is re-

PLUS

V

BATx

quested via the SPI interface.

REF

+ V = 32,752mV • (VDAC

/2047) + 0.8V

REF

(VALUE)

When a hard short-circuit occurs, it might pull all of the

power sources down to near 0V potentials. The capacitors

Note that the reference voltage must be subtracted from

the VDAC value in order to obtain the correct output volt-

on V and V

must be large enough to keep the circuit

CC

PLUS

operating correctly during the 15ms short-circuit event.

The charger will stop within a few microseconds leaving

a small current which must be provided by the capacitor

age. This value is V /16mV = 50 (32 ).

REF

HEX

Capacitors C and C are used to average the voltage

B1

B2

present at the V

pin as well as provide a zero in the

SET

on V

PLUS

. The recommended minimum values (1µF on

PLUS

voltage loop to help stability and transient response time

to voltage variations. See the Applications Information

section.

V

and 2µF on V , including tolerances) should keep

CC

the LTC1960 operating above the UVLO trip voltage long

enough to perform the short-circuit function when the

input voltages are greater than 8V. Increasing the capaci-

tor across V to 4.7µF will allow operation down to the

CHGMON

BAT1

BAT2

CC

recommended 6V minimum.

R

VF

405.3k

C

B2

V

SET

C

Fast PowerPath Turn-Off

CSN

–

+

TO

TH

EA

All of the PowerPath switches can be forced off by set-

ting the DCDIV pin to a voltage between 8V and 10V. This

will have the same effect as a short-circuit event. The PF

status bit will also be set. DCDIV must be less than 5V

I

B1

V

REF

R

VSET

7.2k

DAC

11

∆Σ

MODULATOR

VALUE

SWV

and V

must decrease below the UVLO threshold to

(11 BITS)

PLUS

1960 F05

re-enable the PowerPath switches.

Power-Up Strategy

Figure 5. Voltage DAC Operation

All three PowerPath switches are turned on after V

exceeds the UVLO threshold for more than 250ms. This

PLUS

1960fb

17

LTC1960

OPERATION

The Current DAC Block

Whenthelowcurrentmodebit(D10)issetto1,thecurrent

DACentersadifferentmodeofoperation. ThecurrentDAC

outputispulse-widthmodulatedwithahighfrequencyclock

having a duty cycle value of 1/8. Therefore, the maximum

ThecurrentDACisadelta-sigmamodulatorwhichcontrols

the effective value of an internal resistor, R

= 18.77k,

SET

usedtoprogramthemaximumchargercurrent.Figure6is

asimplifieddiagramoftheDACoperation.Thedelta-sigma

modulator and switch convert the IDAC value, received

via SPI communication, to a variable resistance equal to

output current provided by the charger is I

/8. The

MAX

delta-sigma output gates this low duty cycle signal on

and off. The delta-sigma shift registers are then clocked

at a slower rate, about 40ms/bit, so that the charger has

1.25R /(IDAC

/1023). In regulation, I is servo

SET

(VALUE)

SET

time to settle to the I

/8 value. The resulting average

MAX

driven to the 0.8V reference voltage, V , and the cur-

REF

chargingcurrentisequalto1/8ofthecurrentprogrammed

in normal mode. Dual battery charging is disabled in low

current mode. If both batteries are selected for charging,

then only BAT1 will charge.

rent from R

is matched against a current derived from

SET

the voltage between pins CSP and CSN. This current is

(V – V )/3k.

CSP

CSN

Therefore, programmed current is:

IDAC



_(VALUE)

V_REF• 3k

(1.25R_SNSR_SET

I_AVG

=

•





)

1023





(V

CSP

– V

)

CSN

3kΩ

(FROM CA1 AMPLIFIER)

I

SET

C

+

–

TO

I

SET

TH

V

REF

R

SET

18.77k

DAC

VALUE

(10 BITS)

1960 F06

10

∆Σ

MODULATOR

Figure 6. Current DAC Operation

AVERAGE CHARGER CURRENT

I

/8

0

MAX

1960 F07

~40ms

Figure 7. Charging Current Waveform in Low Current Mode

1960fb

18

LTC1960

APPLICATIONS INFORMATION

Automatic Current Sharing

it is actual physical capacity rating at the time of charge.

Capacity rating will change with age and use and hence

the current sharing ratios can change over time.

In a dual parallel charge configuration, the LTC1960 does

notactuallycontrolthecurrentflowingintoeachindividual

battery. The capacity, or amp-hour rating, of each battery

determines how the charger current is shared. This auto-

matic steering of current is what allows both batteries to

reach their full capacity points at the same time. In other

words, given all other things equal, charge termination

will happen simultaneously.

In dual charge mode, the charger uses feedback from the

BAT2 input to determine charger output voltage. When

chargingbatterieswithsignificantlydifferentinitialstatesof

charge(i.e.,onealmostfull,theotheralmostdepleted),the

full battery will get a much lower current. This will cause a

voltagedifferenceacrossthechargeMUXswitches,which

may cause the BAT1 voltage to exceed the programmed

voltage. Using MOSFETs in the charge MUX with lower

A battery can be modeled as a huge capacitor and hence

governed by the same laws.

R

will alleviate this problem.

DS(ON)

I = C • (dV/dT), where:

I = The current flowing through the capacitor

Adapter Limiting

An important feature of the LTC1960 is the ability to auto-

matically adjust charging current to a level which avoids

overloading the wall adapter. This allows the product to

operate at the same time that batteries are being charged

without complex load management algorithms. Addition-

ally,batterieswillautomaticallybechargedatthemaximum

possible rate of which the adapter is capable.

C = Capacity rating of battery (using amp-hour value

instead of capacitance)

dV = Change in voltage

dt = Change in time

The equivalent model of a set or parallel batteries is a

set of parallel capacitors. Since they are in parallel, the

change in voltage over change in time is the same for both

batteries 1 and 2.

This feature is created by sensing total adapter output cur-

rent and adjusting charging current downward if a preset

adapter current limit is exceeded. True analog control is

used, with closed loop feedback ensuring that adapter

load current remains within limits. Amplifier CL1 in Figure

dV

=

dt_BAT1dt_BAT2

8 senses the voltage across R , connected between the

From here we can simplify.

CL

CLP and DCIN pins. When this voltage exceeds 100mV,

I

/C

= dV/dt = I

/C

BAT1 BAT1

BAT2 BAT2

the amplifier will override programmed charging current

= I

C /C

BAT1 BAT2 BAT1

to limit adapter current to 100mV/R . A lowpass filter

BAT2

CL

formed by 5kΩ and 0.1µF is required to eliminate switch-

ing noise. If the current limit is not used, CLP should be

connected to DCIN.

At this point you can see that the current divides as the

ratio of the two batteries capacity ratings. The sum of the

currentintoboth batteries is the sameasthecurrent being

supply by the charger. This is independent of the mode of

the charger (CC or CV).

100mV

CLP

+

–

0.1µF

I

= I

+ I

BAT1 BAT2

CHRG

5kΩ

CL1

+

From here we solve for the actual current for each battery.

AC ADAPTER

INPUT

R

*

DCIN

CL

V

IN

I

= I

C

/(C

+ C

)

BAT2

BAT1

CHRG BAT2 BAT1

BAT2

+

11960 F08

C

IN

C

/(C

CHRG BAT1 BAT1

100mV

ADAPTER CURRENT LIMIT

*R

CL

=

Please note that the actual observed current sharing will

vary from manufactures claimed capacity ratings since

Figure 8. Adapter Current Limiting

1960fb

19

LTC1960

APPLICATIONS INFORMATION

Watchdog Timer

If this procedure is not followed, and BAT2 is significantly

higher voltage than BAT1, the charger could refuse to

charge either battery.

Charging will begin when either CHARGE_BAT1 or

CHARGE_BAT2 bits are set in the charger register (ad-

dress: 111). Charging will stop if the charger register is

not updated prior to the expiration of the watchdog timer.

Simplyrepeatingthesamedatatransmissiontothecharger

register at a rate higher than once per second will ensure

that charging will continue uninterrupted.

Charge Termination Issues

Batterieswithconstant-currentchargingandvoltage-based

charger termination might experience problems with re-

ductions of charger current caused by adapter limiting. It

is recommended that input limiting feature be defeated in

suchcases. Consultthebatterymanufacturerforinforma-

tion on how your battery terminates charging.

Extending System to More Than Two Batteries

TheLTC1960canbeextendedtomanagesystemswithmore

than three sources of power. Contact Linear Technology

Applications Engineering for more information.

Setting Output Current Limit

Thefull-scaleoutputcurrentsettingoftheIDACwillproduce

Charging Depleted Batteries

= 102.3mV between CSP and CSN. To set the full-

V

MAX

scale current of the DAC simply divide V

by R

.

MAX

SNS

Some batteries contain internal protection switches that

disconnect a load if the battery voltage falls below what

is considered a reasonable minimum. In this case, the

charger may not start because the voltage at the battery

terminal is less than 5V. The low current mode of the IDAC

must be used in this case to condition the battery. In low

current mode, there is no minimum voltage requirement

(but dual charging is not allowed). Usually, the battery will

detect that it is being charged and then close its protec-

tion switch, which will allow the IDAC to switch to normal

mode. Smart batteries require that charging current not

exceed 100mA until valid charging voltage and charging

current parameters are transmitted via the SMBus. The

low current IDAC mode is ideal for this purpose.

This is expressed by the following equation:

= 0.1023/I

R

SNS

Table 1. Recommended R_SNSResistor Values

(A) (Ω) 1%

MAX

I

R

SNS

R

(W)

SNS

MAX

1.023

2.046

4.092

8.184

0.100

0.25

0.050

0.025

0.012

0.25

0.5

1

Use resistors with low ESL.

Inductor Selection

Higher operating frequencies allow the use of smaller

inductor and capacitor values. A higher frequency gener-

ally results in lower efficiency because of MOSFET gate

charge losses. In addition, the effect of inductor value

on ripple current and low current operation must also be

Starting Charge with Dissimilar Batteries in Dual

Charge Mode

When charging batteries of different charger termination

voltages, the charger should be started using the follow-

ing procedure:

considered.Theinductorripplecurrent∆I decreaseswith

L

higher frequency and increases with higher V .

IN

Step 1. Select only the lowest termination voltage bat-

tery for charging, and set the charger to its charging

parameters.





1

f L

( )(

V_OUT

V_IN

∆I_L

=

V_OUT1−









)

Step 2. When the battery current is flowing into that bat-

tery, change to dual charging mode (without stopping the

charger) and set the appropriate charging parameters for

this dual charger condition.

Accepting larger values of ∆I allows the use of low

L

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ∆I = 0.4(I

). In no case should

L

MAX

1960fb

20

LTC1960

APPLICATIONS INFORMATION

∆I exceed 0.6(I

) due to limits imposed by IREV and

with lower C actually provides higher efficiency. The

RSS

synchronous MOSFET losses are greatest at high input

voltageorduringashort-circuitwhenthedutycycleinthis

L

MAX

CA1. Remember the maximum ∆I occurs at the maxi-

L

mum input voltage. In practice, 10µH is the lowest value

recommended for use.

switch is nearly 100%. The term (1 +

d∆T) is generally

given for a MOSFET in the form of a normalized R

DS(ON)

Charger Switching Power MOSFET and Diode

Selection

vs Temperature curve, but

d

= 0.005/°C can be used as

an approximation for low voltage MOSFETs. C

is usu-

RSS

ally specified in the MOSFET characteristics. The constant

k = 1.7 can be used to estimate the contributions of the

two terms in the main switch dissipation equation.

TwoexternalpowerMOSFETsmustbeselectedforusewith

the LTC1960 charger: An N-channel MOSFET for the top

(main) switch and an N-channel MOSFET for the bottom

(synchronous) switch.

If the LTC1960 charger is to operate in low dropout mode

or with a high duty cycle greater than 85%, then the top-

side N-channel efficiency generally improves with a larger

MOSFET. Using asymmetrical MOSFETs may achieve cost

savings or efficiency gains.

The peak-to-peak gate drive levels are set by the V volt-

CC

age.Thisvoltageistypically5.2V.Consequently,logic-level

threshold MOSFETs must be used. Pay close attention to

the B

specification for the MOSFETs as well; many of

VDSS

the logic-level MOSFETs are limited to 30V or less.

The Schottky diode D1, shown in the Typical Application

on the back page, conducts during the dead-time between

the conduction of the two power MOSFETs. This prevents

thebodydiodeofthebottomMOSFETfromturningonand

storing charge during the dead-time, which could cost as

muchas1%inefficiency.A1ASchottkyisgenerallyagood

size for 4A regulators due to the relatively small average

current. Larger diodes can result in additional transition

losses due to their larger junction capacitance. The diode

may be omitted if the efficiency loss can be tolerated.

Selection criteria for the power MOSFETs include the on-

resistance R

, reverse transfer capacitance C

DS(ON)

,

RSS

input voltage and maximum output current. The LTC1960

chargerisalwaysoperatingincontinuousmodesotheduty

cycles for the top and bottom MOSFETs are given by:

Main Switch Duty Cycle = V /V

OUT IN

Synchronous Switch Duty Cycle = (V – V )/V

IN

OUT

The MOSFET power dissipations at maximum output

current are given by:

Calculating IC Power Dissipation

2

P

MAIN

= V /V (I

) (1 +

d∆T

)R + k(V )

DS(ON) IN

OUT IN MAX

ThepowerdissipationoftheLTC1960isdependentuponthe

gate charge of Q and Q (refer to Typical Application).

(I

MAX

)(C )(f)

RSS

TG

BG

The gate charge is determined from the manufacturer’s

data sheet and is dependent upon both the gate voltage

swing and the drain voltage swing of the FET.

2

P

= (V – V )/V (I

) (1 + d∆T) R

SYNC

IN

OUT

IN MAX DS(ON)

Where

d

∆T

isthetemperaturedependencyofR

and

DS(ON)

k is a constant inversely related to the gate drive current.

P = (V

– V ) • [f (Q + Q ) + I

]

2

D

DCIN

VCC

OSC TG

BG

VCC

BothMOSFETshaveI RlosseswhilethetopsideN-channel

+ V

• I

DCIN DCIN

equation includes an additional term for transition losses,

which are highest at high input voltages. For V < 20V,

IN

Example: V

= 5.2V, V

= 19V, f

= 345kHz,

OSC

VCC

DCIN

= 0mA.

the high current efficiency generally improves with larger

Q

= Q = 15nC, I

G2

G3

VCC

MOSFETs, while for V > 20V the transition losses rapidly

IN

P = 165mW

D

increasetothepointthattheuseofahigherR

device

DS(ON)

1960fb

21

LTC1960

APPLICATIONS INFORMATION

V

/I Capacitors

SET SET

overshoot during start-up transients the time constant as-

sociated with C must be shorter than the time constant

B2

Capacitor C7 is used to filter the delta-sigma modulation

frequency components to a level which is essentially DC.

of C5 at the I pin. If C is increased to improve ripple

TH

B2

rejection, then C5 should be increased proportionally and

charger response time to voltage variation will degrade.

Acceptable voltage ripple at I is about 10mV . Since

SET

P-P

the period of the delta-sigma switch closure, T , is about

∆∑

10µs and the internal IDAC resistor, R , is 18.77k, the

SET

Input and Output Capacitors

ripple voltage can be approximated by:

In the 4A Lithium Battery Charger (Typical Application

V_REF• T_{∆ ∑}

section), theinputcapacitor(C )isassumedtoabsorball

∆V

=

IN

ISET

R_SET• C7

input switching ripple current in the converter, so it must

haveadequateripplecurrentrating.Worst-caseRMSripple

currentwillbeequaltoone-halfofoutputchargingcurrent.

Actual capacitance value is not critical. Solid tantalum,

low ESR capacitors have a high ripple current rating in a

relatively small surface mount package, but caution must

be used when tantalum capacitors are used for input or

output bypass. High input surge currents can be created

when the adapter is hot-plugged to the charger or when a

battery is connected to the charger. Solid tantalum capaci-

tors have a known failure mechanism when subjected to

very high turn-on surge currents. Only Kemet T495 series

of “surge robust” low ESR tantalums are rated for high

surge conditions such as battery to ground.

Then the equation to extract C7 is:

V_REF• T_{∆ ∑}

C7 =

∆V

•R_SET

ISET

= 0.8/0.01/18.77k(10µs) @ 0.043µF

In order to prevent overshoot during start-up transients,

the time constant associated with C7 must be shorter than

the time constant of C5 at the I pin. If C7 is increased

TH

to improve ripple rejection, then C5 should be increased

proportionally and charger response time to average cur-

rent variation will degrade.

Capacitor C and C are used to filter the VDAC delta-

B1

B2

The relatively high ESR of an aluminum electrolytic for

C15, located at the AC adapter input terminal, is helpful

in reducing ringing during the hot-plug event.

sigma modulation frequency components to a level which

is essentially DC. C is the primary filter capacitor and

B2

C

is used to provide a zero in the response to cancel

B1

the pole associated with C . Acceptable voltage ripple

B2

Highest possible voltage rating on the capacitor will

minimize problems. Consult with the manufacturer before

use. Alternatives include new high capacity ceramic (at

least 20µF) from Tokin, United Chemi-Con/Marcon, et al.

Other alternative capacitors include OSCON capacitors

from Sanyo.

at V

is about 10mV . Since the period of the delta-

SET

P-P

∆∑

sigma switch closure, T , is about 11µs and the internal

VDAC resistor, R

approximated by:

, is 7.2kΩ, the ripple voltage can be

VSET

V_REF• T_{∆ ∑}

∆V_VSET

=

R_VSETC ||C

(

)

The output capacitor (C ) is also assumed to absorb

B1

B2

OUT

output switching current ripple. The general formula for

Then the equation to extract C || C is:

B1

B2

capacitor current is:

V_REF• T_{∆ ∑}











V_BAT

V_DCIN

C_B1||C_B2

=

0.29(V_BAT) 1−



R_VSET∆V_VSET

I_RMS

=

C

should be 10× to 20× C to divide the ripple voltage

(L1)(f)

B2

B1

present at the charger output. Therefore C = 0.01µF and

B2

B1

For example:

= 19V, V

C

= 0.1µF are good starting values. In order to prevent

V

= 12.6V, L1 = 10µH, and f = 300kHz,

BAT

DCIN

I

= 0.41A.

RMS

1960fb

22

LTC1960

APPLICATIONS INFORMATION

EMI considerations usually make it desirable to minimize

ripple current in the battery leads, and beads or inductors

maybeaddedtoincreasebatteryimpedanceatthe300kHz

switching frequency. Switching ripple current splits be-

tween the battery and the output capacitor depending on

theESRoftheoutputcapacitorandthebatteryimpedance.

IfyouuseidenticalMOSFETsforbothbatterypaths,voltage

drops will track over a wide current range. The LTC1960

linear 25mV CV drop regulation will not occur until the

current has dropped below:

25mV

2R_DS(ON)MAX

I_LINEARMAX

=

If the ESR of C

is 0.2Ω and the battery impedance is

OUT

raised to 4Ω with a bead or inductor, only 5% of the cur-

However, if you try to use the above equation to determine

rent ripple will flow in the battery.

R

to force linear mode at full current, the MOSFET

value becomes unreasonably low for MOSFETs

DS(ON)

PowerPath and Charge MUX MOSFET Selection

available at this time. The need for the LTC1960 voltage

drop regulation only comes into play for parallel battery

configurations that terminate charge or discharge using

voltage. At first this seems to be a problem, but there are

several factors helping out:

Three pairs of P-channel MOSFETs must be used with

the wall adapter and the two battery discharge paths. Two

pairsofN-channelMOSFETsmustbeusedwiththebattery

charge path. The nominal gate drive levels are set by the

clamp drive voltage of their respective control circuitry.

This voltage is typically 6.25V. Consequently, logic-level

threshold MOSFETs must be used. Pay close attention to

1. Whenbatteriesareinparallelcurrentsharing,thecurrent

flow through any one battery is less than if it is running

standalone.

the B

specification for the MOSFETs as well; many of

VDSS

2. Most batteries that charge in constant-voltage mode,

such as Li-Ion, charge terminate at a current value of

C/10 or less which is well within the linear operation

range of the MOSFETs.

the logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the

on-resistance R

, input voltage and maximum out-

DS(ON)

put current. For the N-channel charge path, the maximum

current is the maximum programmed current to be used.

For the P-channel discharge path maximum current typi-

cally occurs at end of life of the battery when using only

3. Voltage tracking for the discharge process does not

need such precise voltage tracking values.

The LTC1960 has two transient conditions that force the

dischargepathP-channelMOSFETstohavetwoadditional

parameters to consider. The parameters are gate charge

onebattery.TheupperlimitofR

valueisafunctionof

DS(ON)

the actual power dissipation capability of a given MOSFET

package that must take into account the PCB layout. As a

starting point, without knowing what the PCB dissipation

capability would be, derate the package power rating by

a factor of two.

Q

and single pulse power capability.

GATE

When the LTC1960 senses a LOW_POWER event, all

the P-channel MOSFETs are turned on simultaneously

to allow voltage recovery due to a loss of a given power

source. However, there is a delay in the time it takes to

turn on all the MOSFETs. Slow MOSFETs will require more

bulk capacitance to hold up all the system’s power sup-

ply function during the transition and fast MOSFET will

require less bulk capacitance. The transition speed of a

MOSFET to an on or off state is a direct function of the

MOSFET gate charge.

P

MOSFET

R

=

DS(ON)MAX

2

2 I

(

)

MAX

If you are using a dual MOSFET package with both MOS-

FETs in series, you must cut the package power rating in

half again and recalculate.

P

MOSFETDUAL

R

=

DS(ON)MAX

2

Q_GATE

I_DRIVE

4 I

(

)

t =

MAX

1960fb

23

LTC1960

APPLICATIONS INFORMATION

The highest frequency switching loop has the highest

layout priority. For best results, avoid using vias in this

loop and keep the entire high frequency loop on a single

externalPCBlayer. Ifyoumust, usemultipleviastokeep

the impedance down (see Figure 9).

I

is the fixed drive current into the gate from the

DRIVE

LTC1960 and “t” is the time it takes to move that charge

to a new state and change the MOSFET conduction mode.

Hence, time is directly related to Q

. Since Q

GATE

goes up with MOSFETs of lower R

, choosing such

DS(ON)

MOSFETshasacounterproductiveincreaseingatecharge

making the MOSFET slower. Please note that the LTC1960

recovery time specification only refers to the time it takes

for the voltage to recover to the level just prior to the

LOW_POWER event as opposed to full voltage.

SWITCH NODE

L1

V

BAT

HIGH

FREQUENCY

CIRCULATING

PATH

C

IN

D1

C

OUT

V

IN

BAT

ThesinglepulsecurrentratingoftheMOSFETisimportant

whenashort-circuittakesplace.TheMOSFETmustsurvive

a 15ms overload. MOSFETs of lower R

or MOSFETs

DS(ON)

that use more powerful thermal packages will have a high

power surge rating. Using too small of a pulse rating will

allow the MOSFET to blow to the open-circuit condition

instantly like a fuse. Typically there is no outward sign of

failure because it happens so fast. Please measure the

surge current for all discharge power paths under worse

case conditions and consult the MOSFET data sheet for

the limitations. Voltage sources with the highest voltage

and the most bulk capacitance are often the biggest risk.

SpecificallytheMOSFETsinthewalladapterpathwithwall

adapters of high voltage, large bulk capacitance and low

resistance DC cables between the adapter and device are

the most common failures. Remember to only use the real

wall adapter with a production DC power cord when per-

forming the wall adapter path test. The use of a laboratory

power supply is unrealistic for this test and will force you

to over specify the MOSFET ratings. A battery pack usu-

ally has enough series resistance to limit the peak current

or are too low in voltage to create enough instantaneous

power to damage their respective PowerPath MOSFETs.

1960 F09

Figure 9. High Speed Switching Path

2. Run long power traces in parallel. Best results are

achievedifyouruneachtraceonseparatePCBlayerone

on top of the other for maximum capacitance coupling

and common mode noise rejection.

3. If possible, use a ground plane under the switcher

circuitry to minimize capacitive interplane noise cou-

pling.

4. Keep signal or analog ground separate. Tie this analog

ground back to the power supply at the output ground

using a single point connection.

5.ForbestcurrentprogrammingaccuracyprovideaKelvin

connectionfromR

as an example.

toCSPandCSN. SeeFigure 10

SENSE

DIRECTION OF CHARGING CURRENT

PCB Layout Considerations

R

SNS

For maximum efficiency, the switch node rise and fall

time is kept as short as possible. To prevent magnetic

and electrical field radiation and high frequency resonant

problems, proper layout of the components connected to

the IC is essential.

1960 F10

CSN

CSP

1. Keep the highest frequency loop path as small and

tight as possible. This includes the bypass capacitors,

with the higher frequency capacitors being closer to

the noise source than the lower frequency capacitors.

Figure 10. Kelvin Sensing of Charging Current

1960fb

24

LTC1960

PACKAGE DESCRIPTION

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 0.12

5.3 – 5.7

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

7.40 – 8.20

(.291 – .323)

0.42 0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

G36 SSOP 0204

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

1960fb

25

LTC1960

PACKAGE DESCRIPTION

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ± 0.05

5.50 ± 0.05

4.10 ± 0.05

3.00 REF

5.15 0.05

3.15 0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.5 REF

6.10 ± 0.05

7.50 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 ± 0.05

3.00 REF

5.00 ± 0.10

37

38

0.00 – 0.05

0.40 ±0.10

PIN 1

TOP MARK

1

2

(SEE NOTE 6)

5.15 0.10

5.50 REF

7.00 ± 0.10

3.15 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ± 0.05

R = 0.125

TYP

R = 0.10

TYP

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

1960fb

26

LTC1960

REVISION HISTORY ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

04/11 Updated Absolute Maximum Ratings section

Added Note 8

2

5

Updated Pin Functions

8, 9

18

21

28

Updated equation in “The Current DAC Block” section

Updated equation in “Calculating IC Power Dissipation” section

Updated Typical Application

1960fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC1960

(LTC1960CG Pin Numbers Shown)

TYPICAL APPLICATION

Dual Battery Selector and 4A Charger

PowerPath MUX

BAT2

BAT1

V

IN

C2

1µF

C6

1µF

R

CL

0.03

100Ω

R1

5.1k

1%

Q1

Q6

Q5

Q7

Q8

C1

0.1µF

C8

0.1µF

LTC1960

Q2

V

1

7

6

9

DD

24

CLP

VPLUS

GDCI

GDCO

GB1I

GB1O

GB2I

GB2O

SCP

SCN

LOPWR

CSN

CSP

ITH

ISET

29

3

2

DCIN

BAT1

BAT2

MISO

SCK

4.7k

R4

14k

1%

MISO

SCK

20

19

21

18

17

25

35

36

34

33

13

28

16

8

11

10

5

R

SC

0.02Ω

MOSI

SSB

MOSI

SSB

4

DCDIV

COMP1

GCH2

SCH2

GCH1

SCH1

VSET

VCC

LOAD

12

22

23

14

15

30

31

32

27

26

R2

649k

1%

R3

100k

1%

C9

100pF

CL

20µF

25V

R5

1k

1%

R7

49.9k

1%

C3

0.01µF

R9

3.3k

1%

SW

C5

0.15µF

BOOST

TGATE

BGATE

PGND

C7

0.1µF

GND

C

20µF

25V

IN

Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY

Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A

D1: MBR130T3

QTG

BAT2

D3

BAT1

D4

D2: CMDSH-3 TYPE

L1

D3, D4: BAT54A TYPE

10µH

4A

C4

0.1µF

R11

1k

D2

C

OUT

R

SNS

20µF 25V CHARGE MUX

0.025Ω

1%

C6

2µF

QBG

Q9

CB2

0.1µF

D1

CB1

0.01µF

R6

100Ω

Q4

Q3

Q10

1960 TA02

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LT1505

High Efficiency Battery Charger

Up to 97% Efficiency; AC Adapter Current Limit

; Power Good Output; 3.5V ≤ V ≤ 36V

LTC1628-PG

LTC1709

2-Phase, Dual Synchronous Step-Down Controller Minimizes C and C

IN

OUT

IN

2-Phase, Dual Synchronous Step-Down Controller Up to 42A Output; Minimum C and C

with VID

; Uses Smallest Components for Intel

IN

OUT

and AMD Processors

LTC3711

LTC1759

LT1769

No R

™ Synchronous Step-Down Controller

3.5V ≤ V ≤ 36V; 0.925V ≤ V

≤ 2V; for Transmeta, AMD and Intel Mobile

OUT

SENSE

IN

with VID

Processors

SMBus Controlled Smart Battery Charger

Synchronous Operation for High Efficiency; Integrated SMBus Accelerator;

AC Adapter Current Limit

2A Battery Charger

Constant-Current/Constant-Voltage Switching Regulator; Input Current Limiting

Maximizes Charge Current

1960fb

LT 0411 REV B • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2001

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1769IGN#PBF
厂家：	Linear
描述：	LT1769 - Constant-Current/Constant-Voltage 2A Battery Charger with Input Current Limiting; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 电池
文件：	总28页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1769IGN#PBF [Linear]

相关型号：

LT1769IGN#TR

LT1776

LT1776C

LT1776CN8

LT1776CN8#PBF

LT1776CS8

LT1776I

LT1776IN8

LT1776IN8#PBF

LT1776IS8

LT1776IS8#PBF

LT1776IS8#TR